[Intel-gfx] [PULL] drm-intel-gt-next

[Tvrtko Ursulin]

Hi Dave, Daniel,

Here goes the final drm-intel-gt-next PR towards 5.19.

A fix for a security issue affecting Tigerlake onwards and a plain fix for
a race in VMA handling have landed since the previous pull.

Also last two bits of DG2 enablement are included - GuC firmware version
has been defined and compute command streamers have been exposed to
userspace.

Else just a handful of small cleanups and selftest fixes. There are
initial Ponte Vecchio definitions but no impact oustside development
branch management.

Regards,

Tvrtko

drm-intel-gt-next-2022-05-05:
UAPI Changes:

- Add kerneldoc for engine class enum (Matt Roper)
- Add compute engine ABI (Matt Roper)

Driver Changes:

- Define GuC firmware version for DG2 (John Harrison)
- Clear SET_PREDICATE_RESULT prior to executing the ring (Chris Wilson)
- Fix race in __i915_vma_remove_closed (Karol Herbst)

- Add register for compute engine's MMIO-based TLB invalidation (Matt Roper)
- Xe_HP SDV and DG2 have up to 4 CCS engines (Daniele Ceraolo Spurio)
- Add initial Ponte Vecchio definitions (Stuart Summers)
- Document the eviction of the Flat-CCS objects (Ramalingam C)

- Use existing uncore helper to read gpm_timestamp (Umesh Nerlige Ramappa)
- Fix issue with LRI relative addressing (Akeem G Abodunrin)
- Skip poisoning SET_PREDICATE_RESULT on dg2 (Chris Wilson)
- Optimize the ccs_sz calculation per chunk (Ramalingam C)
- Remove superfluous string helper include (Jani Nikula)
- Fix assert in i915_ggtt_pin (Tvrtko Ursulin)
- Use IOMEM_ERR_PTR() directly (Kefeng Wang)
The following changes since commit f15856d7de914595d0daa2c706f53a693b48e228:

  drm/i915/dg2: add gsc with special gsc bar offsets (2022-04-21 11:34:39 -0700)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-gt-next-2022-05-05

for you to fetch changes up to 1df1c79cbb7ac9bf148930be3418973c76ba8dde:

  drm/i915: Fix race in __i915_vma_remove_closed (2022-05-04 16:22:13 +0100)


UAPI Changes:

- Add kerneldoc for engine class enum (Matt Roper)
- Add compute engine ABI (Matt Roper)

Driver Changes:

- Define GuC firmware version for DG2 (John Harrison)
- Clear SET_PREDICATE_RESULT prior to executing the ring (Chris Wilson)
- Fix race in __i915_vma_remove_closed (Karol Herbst)

- Add register for compute engine's MMIO-based TLB invalidation (Matt Roper)
- Xe_HP SDV and DG2 have up to 4 CCS engines (Daniele Ceraolo Spurio)
- Add initial Ponte Vecchio definitions (Stuart Summers)
- Document the eviction of the Flat-CCS objects (Ramalingam C)

- Use existing uncore helper to read gpm_timestamp (Umesh Nerlige Ramappa)
- Fix issue with LRI relative addressing (Akeem G Abodunrin)
- Skip poisoning SET_PREDICATE_RESULT on dg2 (Chris Wilson)
- Optimize the ccs_sz calculation per chunk (Ramalingam C)
- Remove superfluous string helper include (Jani Nikula)
- Fix assert in i915_ggtt_pin (Tvrtko Ursulin)
- Use IOMEM_ERR_PTR() directly (Kefeng Wang)


Akeem G Abodunrin (1):
  drm/i915/xehpsdv/dg1/tgl: Fix issue with LRI relative addressing

Chris Wilson (2):
  drm/i915/selftests: Skip poisoning SET_PREDICATE_RESULT on dg2
  drm/i915/gt: Clear SET_PREDICATE_RESULT prior to executing the ring

Daniele Ceraolo Spurio (1):
  drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines

Jani Nikula (1):
  drm/i915: remove superfluous string helper include

John Harrison (1):
  drm/i915/dg2: Define GuC firmware version for DG2

Karol Herbst (1):
  drm/i915: Fix race in __i915_vma_remove_closed

Kefeng Wang (1):
  drm/i915: use IOMEM_ERR_PTR() directly

Matt Roper (3):
  drm/i915/uapi: Add kerneldoc for engine class enum
  drm/i915/xehp: Add register for compute engine's MMIO-based TLB 
invalidation
  drm/i915/xehp: Add compute engine ABI

Ramalingam C (2):
  drm/i915/gt: optimize the ccs_sz calculation per chunk
  drm/i915/gt: Document the eviction of the Flat-CCS objects

Stuart Summers (1):
  drm/i915/pvc: add initial Ponte Vecchio definitions

Tvrtko Ursulin (1):
  drm/i915: Fix assert in i915_ggtt_pin

Umesh Nerlige Ramappa (1):
  drm/i915/pmu: Use existing uncore helper to read gpm_timestamp

 drivers/gpu/drm/i915/gt/gen8_engine_cs.c   | 54 
 drivers/gpu/drm/i915/gt/gen8_engine_cs.h   |  7 ++
 drivers/gpu/drm/i915/gt/intel_engine_regs.h|  2 +
 drivers/gpu/drm/i915/gt/intel_engine_user.c|  2 +-
 .../gpu/drm/i915/gt/intel_execlists_submission.c   | 15 +++--
 drivers/gpu/drm/i915/gt/intel_gpu_commands.h   |  2 +
 drivers/gpu/drm/i915/gt/intel_gt.c |  1 +
 drivers/gpu/drm/i915/gt/intel_gt_regs.h|  1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c| 75 --
 drivers/gpu/drm/i915/gt/intel_lrc.h|  5 ++
 drivers/gpu/drm/i915/gt/intel_migrate.c| 59 +

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc/slpc: Use non-blocking H2G for waitboost

[Patchwork]

== Series Details ==

Series: drm/i915/guc/slpc: Use non-blocking H2G for waitboost
URL   : https://patchwork.freedesktop.org/series/103598/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11607 -> Patchwork_103598v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/index.html

Participating hosts (41 -> 41)
--

  Additional (3): fi-hsw-4770 bat-adlm-1 bat-dg2-9 
  Missing(3): bat-rpls-1 fi-bsw-cyan bat-dg2-8 

Known issues


  Here are the changes found in Patchwork_103598v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#3012])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gem_migrate:
- fi-bdw-5557u:   [PASS][3] -> [INCOMPLETE][4] ([i915#5716])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-bdw-5557u/igt@i915_selftest@live@gem_migrate.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/fi-bdw-5557u/igt@i915_selftest@live@gem_migrate.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][5] ([i915#4785])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-snb-2600:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/fi-snb-2600/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#4312] / 
[i915#5594])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/fi-hsw-4770/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][12] ([i915#3303] / [i915#4785]) -> 
[PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
- {fi-ehl-2}: [INCOMPLETE][14] ([i915#5134]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[INCOMPLETE][16] ([i915#3921]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_flip@basic-flip-vs-modeset@b-edp1:
- {bat-adlp-6}:   [DMESG-WARN][18] ([i915#3576]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@b-edp1.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103598v1/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@b-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesk

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Prepare for GSC-loaded HuC (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Prepare for GSC-loaded HuC (rev2)
URL   : https://patchwork.freedesktop.org/series/103186/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11607_full -> Patchwork_103186v2_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103186v2_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_whisper@basic-fds-forked-all:
- {shard-tglu}:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-tglu-8/igt@gem_exec_whis...@basic-fds-forked-all.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-tglu-6/igt@gem_exec_whis...@basic-fds-forked-all.html

  
Known issues


  Here are the changes found in Patchwork_103186v2_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-skl:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) -> 
([PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [FAIL][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44]) ([i915#5032])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl9/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl9/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl9/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl7/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl6/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl6/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl5/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl5/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl3/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl3/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl2/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl2/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl1/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl1/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl10/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl10/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl9/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl9/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl7/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl7/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl7/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl6/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl6/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl6/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl4/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl4/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl4/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl3/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl2/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/shard-skl2/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-

Re: [Intel-gfx] [PATCH] drm/i915: Support Async Flip on Linear buffers

[Murthy, Arun R]

> > There is that GTT alignment restriction that should be mentioned
> > somewhere. Can't quite remember where it was, maybe in PLANE_SURF.
> >
> I checked the BSpec, and don't find anything as such specific for Async flip.
> I also cross verified with the hardware team.
> 
> > But I guess the bigger question is what is the actual use case for this?
> This feature is a requirement for TGL.

Can I have your Reviewed-by for this patch?

Thanks and Regards,
Arun R Murthy

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dmc: Add MMIO range restrictions (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add MMIO range restrictions (rev5)
URL   : https://patchwork.freedesktop.org/series/102630/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11607_full -> Patchwork_102630v5_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_102630v5_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-snb:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [FAIL][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) ([i915#4338]) -> ([PASS][26], [PASS][27], [PASS][28], 
[PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], 
[PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], 
[PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], 
[PASS][47], [PASS][48], [PASS][49], [PASS][50])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb7/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb7/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb7/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb7/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb7/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb6/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb6/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb6/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb6/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb5/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb5/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb5/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb5/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb4/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb4/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb4/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb2/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb2/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb2/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb2/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb2/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb2/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb7/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb7/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb7/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb7/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb7/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb6/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb6/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb6/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb6/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb6/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb5/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb5/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb5/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb5/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb5/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb5/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/shard-snb4/boot.html
   [43]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v

[Intel-gfx] [PATCH] drm/i915/guc/slpc: Use non-blocking H2G for waitboost

[Vinay Belgaumkar]

SLPC min/max frequency updates require H2G calls. We are seeing
timeouts when GuC channel is backed up and it is unable to respond
in a timely fashion causing warnings and affecting CI.

This is seen when waitboosting happens during a stress test.
this patch updates the waitboost path to use a non-blocking
H2G call instead, which returns as soon as the message is
successfully transmitted.

Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 38 -
 1 file changed, 30 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 1db833da42df..c852f73cf521 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -98,6 +98,30 @@ static u32 slpc_get_state(struct intel_guc_slpc *slpc)
return data->header.global_state;
 }
 
+static int guc_action_slpc_set_param_nb(struct intel_guc *guc, u8 id, u32 
value)
+{
+   u32 request[] = {
+   GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
+   SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
+   id,
+   value,
+   };
+   int ret;
+
+   ret = intel_guc_send_nb(guc, request, ARRAY_SIZE(request), 0);
+
+   return ret > 0 ? -EPROTO : ret;
+}
+
+static int slpc_set_param_nb(struct intel_guc_slpc *slpc, u8 id, u32 value)
+{
+   struct intel_guc *guc = slpc_to_guc(slpc);
+
+   GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+   return guc_action_slpc_set_param_nb(guc, id, value);
+}
+
 static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
 {
u32 request[] = {
@@ -208,12 +232,10 @@ static int slpc_force_min_freq(struct intel_guc_slpc 
*slpc, u32 freq)
 */
 
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
-   ret = slpc_set_param(slpc,
-SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
-freq);
-   if (ret)
-   i915_probe_error(i915, "Unable to force min freq to %u: 
%d",
-freq, ret);
+   /* Non-blocking request will avoid stalls */
+   ret = slpc_set_param_nb(slpc,
+   
SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+   freq);
}
 
return ret;
@@ -231,8 +253,8 @@ static void slpc_boost_work(struct work_struct *work)
 */
mutex_lock(&slpc->lock);
if (atomic_read(&slpc->num_waiters)) {
-   slpc_force_min_freq(slpc, slpc->boost_freq);
-   slpc->num_boosts++;
+   if (!slpc_force_min_freq(slpc, slpc->boost_freq))
+   slpc->num_boosts++;
}
mutex_unlock(&slpc->lock);
 }
-- 
2.35.1

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/12] drm/i915: Drop IPC from display 13 and newer

[Patchwork]

== Series Details ==

Series: series starting with [01/12] drm/i915: Drop IPC from display 13 and 
newer
URL   : https://patchwork.freedesktop.org/series/103562/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11606_full -> Patchwork_103562v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_103562v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_103562v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 12)
--

  Missing(1): shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103562v1_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-tglb6/igt@kms_frontbuffer_track...@psr-farfromfence-mmap-gtt.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/shard-tglb8/igt@kms_frontbuffer_track...@psr-farfromfence-mmap-gtt.html

  
Known issues


  Here are the changes found in Patchwork_103562v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@hang:
- shard-skl:  NOTRUN -> [SKIP][3] ([fdo#109271]) +6 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/shard-skl1/igt@gem_ctx_persiste...@hang.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl:  [PASS][4] -> [FAIL][5] ([i915#2842])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-kbl1/igt@gem_exec_fair@basic-none-...@rcs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/shard-kbl7/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_flush@basic-uc-prw-default:
- shard-snb:  [PASS][8] -> [SKIP][9] ([fdo#109271]) +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-snb5/igt@gem_exec_fl...@basic-uc-prw-default.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/shard-snb6/igt@gem_exec_fl...@basic-uc-prw-default.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
- shard-kbl:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/shard-kbl1/igt@gem_lmem_swapp...@heavy-verify-multi.html

  * igt@gem_lmem_swapping@verify-random:
- shard-apl:  NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/shard-apl3/igt@gem_lmem_swapp...@verify-random.html

  * igt@gen9_exec_parse@allowed-single:
- shard-glk:  [PASS][12] -> [DMESG-WARN][13] ([i915#5566] / 
[i915#716])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-glk2/igt@gen9_exec_pa...@allowed-single.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/shard-glk1/igt@gen9_exec_pa...@allowed-single.html
- shard-apl:  [PASS][14] -> [DMESG-WARN][15] ([i915#5566] / 
[i915#716])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-apl2/igt@gen9_exec_pa...@allowed-single.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/shard-apl7/igt@gen9_exec_pa...@allowed-single.html

  * igt@i915_selftest@live@hangcheck:
- shard-snb:  [PASS][16] -> [INCOMPLETE][17] ([i915#3921])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-snb4/igt@i915_selftest@l...@hangcheck.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/shard-snb4/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-apl:  NOTRUN -> [SKIP][18] ([fdo#109271]) +49 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/shard-apl3/igt@kms_big...@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#110723])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/shard-iclb5/igt@kms_big...@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-skl:  NOTRUN -> [SKIP][20] ([fdo#109271

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/bios: Rework BDB block handling (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: Rework BDB block handling (rev7)
URL   : https://patchwork.freedesktop.org/series/101496/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11607 -> Patchwork_101496v7


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/index.html

Participating hosts (41 -> 40)
--

  Additional (2): fi-hsw-4770 bat-dg2-9 
  Missing(3): bat-rpls-1 bat-rpls-2 fi-bsw-cyan 

Known issues


  Here are the changes found in Patchwork_101496v7 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#3012])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][3] ([i915#4785])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][4] -> [DMESG-FAIL][5] ([i915#4528])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][10] ([i915#5594])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/fi-hsw-4770/igt@run...@aborted.html
- fi-blb-e6850:   NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/fi-blb-e6850/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][12] ([i915#3303] / [i915#4785]) -> 
[PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
- {fi-ehl-2}: [INCOMPLETE][14] ([i915#5134]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_flip@basic-flip-vs-modeset@b-edp1:
- {bat-adlp-6}:   [DMESG-WARN][16] ([i915#3576]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@b-edp1.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v7/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@b-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/357

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/bios: Rework BDB block handling (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: Rework BDB block handling (rev7)
URL   : https://patchwork.freedesktop.org/series/101496/
State : warning

== Summary ==

Error: dim checkpatch failed
5c4f46729d27 drm/i915/bios: Reorder panel DTD parsing
d34ebed1abf7 drm/i915/bios: Generate LFP data table pointers if the VBT lacks 
them
-:46: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#46: FILE: drivers/gpu/drm/i915/display/intel_bios.c:319:
+   if (data[i] == 0xff && data[i+1] == 0xff)
 ^

-:134: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#134: FILE: drivers/gpu/drm/i915/display/intel_bios.c:407:
+   next_lfp_data_ptr(&ptrs->ptr[i].fp_timing, 
&ptrs->ptr[i-1].fp_timing, size);
   ^

-:135: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#135: FILE: drivers/gpu/drm/i915/display/intel_bios.c:408:
+   next_lfp_data_ptr(&ptrs->ptr[i].dvo_timing, 
&ptrs->ptr[i-1].dvo_timing, size);
^

-:136: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#136: FILE: drivers/gpu/drm/i915/display/intel_bios.c:409:
+   next_lfp_data_ptr(&ptrs->ptr[i].panel_pnp_id, 
&ptrs->ptr[i-1].panel_pnp_id, size);
  ^

total: 0 errors, 0 warnings, 4 checks, 161 lines checked
dd0b53fecb41 drm/i915/bios: Get access to the tail end of the LFP data block
b444cf795df2 drm/i915/bios: Document the mess around the LFP data tables
b8fa66dfa50d drm/i915/bios: Assume panel_type==0 if the VBT has bogus data
f80f07fab7e2 drm/i915/bios: Extract get_panel_type()
6e1e7f4d7703 drm/i915/bios: Refactor panel_type code
79b6c615ef02 drm/i915/bios: Parse the seamless DRRS min refresh rate
80a1a2def814 drm/i915: Respect VBT seamless DRRS min refresh rate

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: remove unused GEM_DEBUG_DECL() and GEM_DEBUG_BUG_ON()

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: remove unused GEM_DEBUG_DECL() and 
GEM_DEBUG_BUG_ON()
URL   : https://patchwork.freedesktop.org/series/103560/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11606_full -> Patchwork_103560v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103560v1_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
- {shard-dg1}:NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/shard-dg1-17/igt@kms_plane_multi...@atomic-pipe-d-tiling-x.html

  
Known issues


  Here are the changes found in Patchwork_103560v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-skl:  NOTRUN -> [SKIP][2] ([fdo#109271]) +48 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/shard-skl9/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2842])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_flush@basic-uc-set-default:
- shard-snb:  [PASS][5] -> [SKIP][6] ([fdo#109271]) +3 similar 
issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-snb4/igt@gem_exec_fl...@basic-uc-set-default.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/shard-snb6/igt@gem_exec_fl...@basic-uc-set-default.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
- shard-kbl:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/shard-kbl3/igt@gem_lmem_swapp...@heavy-verify-multi.html

  * igt@gem_lmem_swapping@verify-random:
- shard-apl:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/shard-apl8/igt@gem_lmem_swapp...@verify-random.html

  * igt@gen9_exec_parse@allowed-single:
- shard-glk:  [PASS][9] -> [DMESG-WARN][10] ([i915#5566] / 
[i915#716])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-glk2/igt@gen9_exec_pa...@allowed-single.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/shard-glk7/igt@gen9_exec_pa...@allowed-single.html
- shard-apl:  [PASS][11] -> [DMESG-WARN][12] ([i915#5566] / 
[i915#716]) +1 similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-apl2/igt@gen9_exec_pa...@allowed-single.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/shard-apl6/igt@gen9_exec_pa...@allowed-single.html

  * igt@i915_selftest@live@hangcheck:
- shard-snb:  [PASS][13] -> [INCOMPLETE][14] ([i915#3921])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-snb4/igt@i915_selftest@l...@hangcheck.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/shard-snb7/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271]) +49 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/shard-apl8/igt@kms_big...@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][16] ([fdo#110723])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/shard-iclb7/igt@kms_big...@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-skl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3886]) +2 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/shard-skl3/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3886]) +1 
similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/shard-apl8/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-kbl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3886]) +1 
similar issue
   [19]: 
https://int

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)
URL   : https://patchwork.freedesktop.org/series/103491/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11607 -> Patchwork_103491v4


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/index.html

Participating hosts (41 -> 40)
--

  Additional (2): bat-adlm-1 bat-dg2-9 
  Missing(3): bat-dg2-8 fi-rkl-11600 fi-bsw-cyan 

Known issues


  Here are the changes found in Patchwork_103491v4 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@execlists:
- fi-bsw-kefka:   [PASS][1] -> [INCOMPLETE][2] ([i915#5801] / 
[i915#5847])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-8809g:   [PASS][3] -> [DMESG-FAIL][4] ([i915#5334])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-kbl-8809g/igt@i915_selftest@live@gt_heartbeat.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-kbl-8809g/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-snb-2600:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-snb-2600/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@runner@aborted:
- fi-bsw-kefka:   NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#3428] / 
[i915#4312])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-bsw-kefka/igt@run...@aborted.html
- fi-bxt-dsi: NOTRUN -> [FAIL][8] ([i915#5257])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-bxt-dsi/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][9] ([i915#3303] / [i915#4785]) -> 
[PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
- {fi-ehl-2}: [INCOMPLETE][11] ([i915#5134]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[INCOMPLETE][13] ([i915#3921]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- {bat-rpls-1}:   [INCOMPLETE][15] ([i915#4983] / [i915#5338]) -> 
[PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/bat-rpls-1/igt@i915_selftest@l...@requests.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/bat-rpls-1/igt@i915_selftest@l...@requests.html

  * igt@kms_flip@basic-flip-vs-modeset@b-edp1:
- {bat-adlp-6}:   [DMESG-WARN][17] ([i915#3576]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@b-edp1.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@b-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)
URL   : https://patchwork.freedesktop.org/series/103491/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)
URL   : https://patchwork.freedesktop.org/series/103491/
State : warning

== Summary ==

Error: dim checkpatch failed
c22b28cfffd3 drm/i915: Split shared dpll .get_dplls() into compute and get 
phases
-:194: CHECK:CAMELCASE: Avoid CamelCase: 
#194: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+   SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;

total: 0 errors, 0 warnings, 1 checks, 516 lines checked
879cc74477fa drm/i915: Do .crtc_compute_clock() earlier
35d18170c1ab drm/i915: Clean up DPLL related debugs
bd06d6413c61 drm/i915: Reassign DPLLs only for crtcs going throug 
.compute_config()
60c9a564c630 drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible 
side-effects?
#21: FILE: drivers/gpu/drm/i915/display/intel_display.c:6076:
+#define PIPE_CONF_CHECK_TIMINGS(name) do { \
+   PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
+   PIPE_CONF_CHECK_I(name.crtc_htotal); \
+   PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
+   PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
+   PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
+   PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
+   PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
+   PIPE_CONF_CHECK_I(name.crtc_vtotal); \
+   PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
+   PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
+   PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
+   PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 63 lines checked
6de8ad90b89b drm/i915: Extract PIPE_CONF_CHECK_RECT()
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible 
side-effects?
#21: FILE: drivers/gpu/drm/i915/display/intel_display.c:6091:
+#define PIPE_CONF_CHECK_RECT(name) do { \
+   PIPE_CONF_CHECK_I(name.x1); \
+   PIPE_CONF_CHECK_I(name.x2); \
+   PIPE_CONF_CHECK_I(name.y1); \
+   PIPE_CONF_CHECK_I(name.y2); \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 40 lines checked
514a77ad0c48 drm/i915: Adjust intel_modeset_pipe_config() & co. calling 
convention
-:81: CHECK:SPACING: No space is necessary after a cast
#81: FILE: drivers/gpu/drm/i915/display/intel_display.c:5649:
+   pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;

total: 0 errors, 0 warnings, 1 checks, 127 lines checked
99f57f1bbfb6 drm/i915: s/pipe_config/crtc_state/
-:92: CHECK:SPACING: No space is necessary after a cast
#92: FILE: drivers/gpu/drm/i915/display/intel_display.c:5649:
+   crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;

-:190: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_display.c:5767:
+   crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
   ^

total: 0 errors, 0 warnings, 2 checks, 169 lines checked
24b44ff8d3cc drm/i915: Improve modeset debugs
6736bc609e67 drm/i915: Extract intel_crtc_dotclock()
cfc0b6db drm/i915: Introduce struct iclkip_params
5f9ecd0a3455 drm/i915: Feed the DPLL output freq back into crtc_state
-:36: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#36: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:933:
+int intel_crtc_dotclock(const struct intel_crtc_state *crtc_state);

-:181: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#181: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1460:
+int intel_calculate_dotclock(const struct intel_crtc_state *crtc_state);

total: 0 errors, 2 warnings, 0 checks, 261 lines checked
b99e6189702a drm/i915: Compute clocks earlier
90e0b8e479b7 drm/i915: Skip FDI vs. dotclock sanity check during readout
b1ba2dd163dc drm/i915: Make M/N checks non-fuzzy
a21379dc8365 drm/i915: Make all clock checks non-fuzzy
c310a1210f63 drm/i915: Set active dpll early for icl+
86fafa6d29d8 drm/i915: Nuke fastet state copy hacks
9811567591ac drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not 
enabled
2c1626fe0bbb drm/i915: Check hw.enable and hw.active in 
intel_pipe_config_compare()
d699f5d194c8 drm/i915: Add intel_panel_highest_mode()
190d3ba0aa1f drm/i915: Allow M/N change during fastset on bdw+
d686b8dfd9db drm/i915: Require an exact DP link freq match for the DG2 PLL
b470ae0f272b drm/i915: Use a fixed N value always
fd6a9551796d drm/i915: Round to closest in M/N calculations
7b1987f4581b drm/i915: Round TMDS clock to nearest

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dmc: Add MMIO range restrictions (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add MMIO range restrictions (rev7)
URL   : https://patchwork.freedesktop.org/series/102168/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11606_full -> Patchwork_102168v7_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_102168v7_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_102168v7_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_102168v7_full:

### IGT changes ###

 Warnings 

  * igt@kms_ccs@pipe-d-ccs-on-another-bo-yf_tiled_ccs:
- shard-kbl:  [SKIP][1] ([fdo#109271]) -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-kbl4/igt@kms_ccs@pipe-d-ccs-on-another-bo-yf_tiled_ccs.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/shard-kbl1/igt@kms_ccs@pipe-d-ccs-on-another-bo-yf_tiled_ccs.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/shard-dg1-17/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-d.html

  
Known issues


  Here are the changes found in Patchwork_102168v7_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: NOTRUN -> [SKIP][4] ([i915#658])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/shard-iclb8/igt@feature_discov...@psr2.html

  * igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-iclb4/igt@gem_exec_balan...@parallel-balancer.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/shard-iclb8/igt@gem_exec_balan...@parallel-balancer.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl:  [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-kbl1/igt@gem_exec_fair@basic-none-...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/shard-kbl4/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
- shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842]) +3 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/shard-iclb8/igt@gem_exec_fair@basic-n...@vecs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/shard-tglb5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_schedule@smoketest-all:
- shard-glk:  [PASS][12] -> [DMESG-WARN][13] ([i915#118])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-glk4/igt@gem_exec_sched...@smoketest-all.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/shard-glk9/igt@gem_exec_sched...@smoketest-all.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
- shard-kbl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/shard-kbl7/igt@gem_lmem_swapp...@heavy-verify-multi.html

  * igt@gem_lmem_swapping@verify-random:
- shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/shard-apl6/igt@gem_lmem_swapp...@verify-random.html

  * igt@gen9_exec_parse@allowed-all:
- shard-skl:  NOTRUN -> [DMESG-WARN][16] ([i915#5566] / [i915#716])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/shard-skl9/igt@gen9_exec_pa...@allowed-all.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl:  [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +4 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/shard-apl3/igt@i915_susp...@fence-restore-tiled2untiled.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/shard-apl8/igt@i915_susp...@fence-restore-tiled2untiled.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#5286]) +1 similar issue
   [19]: 
htt

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Support programming the EU priority in the GuC descriptor (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Support programming the EU priority in the GuC descriptor 
(rev2)
URL   : https://patchwork.freedesktop.org/series/103515/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11607 -> Patchwork_103515v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/index.html

Participating hosts (41 -> 35)
--

  Additional (2): fi-hsw-4770 fi-icl-u2 
  Missing(8): bat-dg2-8 fi-bsw-cyan bat-adlp-6 bat-adln-1 bat-rpls-1 
bat-rpls-2 bat-jsl-2 bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_103515v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][2] ([i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#3012])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@execlists:
- fi-bdw-gvtdvm:  [PASS][5] -> [INCOMPLETE][6] ([i915#2940] / 
[i915#5801])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-bdw-gvtdvm/igt@i915_selftest@l...@execlists.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-bdw-gvtdvm/igt@i915_selftest@l...@execlists.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-g3258:   NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-snb-2600:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-snb-2600/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  NOTRUN -> [SKIP][11] ([fdo#109278]) +2 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][12] ([fdo#109285])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([i915#3555])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][16] ([i915#3301])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-icl-u2/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-bdw-gvtdvm:  NOTRUN -> [FAIL][17] ([i915#4312])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v2/fi-bdw-gvtdvm/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][18] ([i915#3303] / [i915#4785]) -> 
[PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [19]: 
https://intel-gfx-ci.01.org

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)
URL   : https://patchwork.freedesktop.org/series/103491/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11607 -> Patchwork_103491v3


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_103491v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_103491v3, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/index.html

Participating hosts (41 -> 43)
--

  Additional (4): bat-adlm-1 bat-dg2-9 bat-dg1-6 bat-dg1-5 
  Missing(2): bat-rpls-1 fi-bsw-cyan 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103491v3:

### CI changes ###

 Possible regressions 

  * boot:
- fi-kbl-7500u:   [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-kbl-7500u/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/fi-kbl-7500u/boot.html

  
Known issues


  Here are the changes found in Patchwork_103491v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@fbdev@write:
- bat-dg1-5:  NOTRUN -> [SKIP][3] ([i915#2582]) +4 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@fb...@write.html

  * igt@gem_mmap@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@gem_m...@basic.html
- bat-dg1-5:  NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@gem_m...@basic.html

  * igt@gem_tiled_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@gem_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][7] ([i915#4077]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg1-5:  NOTRUN -> [SKIP][8] ([i915#4079]) +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@gem_tiled_pread_basic.html
- bat-dg1-6:  NOTRUN -> [SKIP][9] ([i915#4079]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-5:  NOTRUN -> [SKIP][10] ([i915#1155])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html
- bat-dg1-6:  NOTRUN -> [SKIP][11] ([i915#1155])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-6:  NOTRUN -> [INCOMPLETE][12] ([i915#4418])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
- fi-rkl-guc: [PASS][13] -> [INCOMPLETE][14] ([i915#4418])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-5:  NOTRUN -> [DMESG-FAIL][15] ([i915#4494] / [i915#4957])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_suspend@system-suspend-without-i915:
- bat-dg1-5:  NOTRUN -> [INCOMPLETE][16] ([i915#5849])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@i915_susp...@system-suspend-without-i915.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-dg1-6:  NOTRUN -> [SKIP][17] ([i915#4212]) +7 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5:  NOTRUN -> [SKIP][18] ([i915#4215])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
- bat-dg1-6:  NOTRUN -> [SKIP][19] ([i915#4215])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)
URL   : https://patchwork.freedesktop.org/series/103491/
State : warning

== Summary ==

Error: dim checkpatch failed
231785cfe6ad drm/i915: Split shared dpll .get_dplls() into compute and get 
phases
-:194: CHECK:CAMELCASE: Avoid CamelCase: 
#194: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+   SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;

total: 0 errors, 0 warnings, 1 checks, 516 lines checked
149c650e3c92 drm/i915: Do .crtc_compute_clock() earlier
fa07341e9078 drm/i915: Clean up DPLL related debugs
cd38c6f33ca7 drm/i915: Reassign DPLLs only for crtcs going throug 
.compute_config()
2bfa7d6f7335 drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible 
side-effects?
#21: FILE: drivers/gpu/drm/i915/display/intel_display.c:6076:
+#define PIPE_CONF_CHECK_TIMINGS(name) do { \
+   PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
+   PIPE_CONF_CHECK_I(name.crtc_htotal); \
+   PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
+   PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
+   PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
+   PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
+   PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
+   PIPE_CONF_CHECK_I(name.crtc_vtotal); \
+   PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
+   PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
+   PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
+   PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 63 lines checked
ff6cab1d620b drm/i915: Extract PIPE_CONF_CHECK_RECT()
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible 
side-effects?
#21: FILE: drivers/gpu/drm/i915/display/intel_display.c:6091:
+#define PIPE_CONF_CHECK_RECT(name) do { \
+   PIPE_CONF_CHECK_I(name.x1); \
+   PIPE_CONF_CHECK_I(name.x2); \
+   PIPE_CONF_CHECK_I(name.y1); \
+   PIPE_CONF_CHECK_I(name.y2); \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 40 lines checked
fb7078b9e786 drm/i915: Adjust intel_modeset_pipe_config() & co. calling 
convention
-:81: CHECK:SPACING: No space is necessary after a cast
#81: FILE: drivers/gpu/drm/i915/display/intel_display.c:5649:
+   pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;

total: 0 errors, 0 warnings, 1 checks, 127 lines checked
fc7e80cb709d drm/i915: s/pipe_config/crtc_state/
-:92: CHECK:SPACING: No space is necessary after a cast
#92: FILE: drivers/gpu/drm/i915/display/intel_display.c:5649:
+   crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;

-:190: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_display.c:5767:
+   crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
   ^

total: 0 errors, 0 warnings, 2 checks, 169 lines checked
27b6922af13b drm/i915: Improve modeset debugs
38e979baf682 drm/i915: Extract intel_crtc_dotclock()
8b15f2405ad0 drm/i915: Introduce struct iclkip_params
f61c5b50fa28 drm/i915: Feed the DPLL output freq back into crtc_state
-:36: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#36: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:933:
+int intel_crtc_dotclock(const struct intel_crtc_state *crtc_state);

-:181: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#181: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1460:
+int intel_calculate_dotclock(const struct intel_crtc_state *crtc_state);

total: 0 errors, 2 warnings, 0 checks, 261 lines checked
07c0d384f102 drm/i915: Compute clocks earlier
ccbe5abf3ae6 drm/i915: Skip FDI vs. dotclock sanity check during readout
83ec228a297a drm/i915: Make M/N checks non-fuzzy
91e845fa1ecd drm/i915: Make all clock checks non-fuzzy
c27f33a67564 drm/i915: Set active dpll early for icl+
d9544b07e2ba drm/i915: Nuke fastet state copy hacks
477d1ccd6fac drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not 
enabled
5827bb6bd270 drm/i915: Check hw.enable and hw.active in 
intel_pipe_config_compare()
5c18a117f889 drm/i915: Add intel_panel_highest_mode()
7e294526263c drm/i915: Allow M/N change during fastset on bdw+
0d94627a7bee drm/i915: Require an exact DP link freq match for the DG2 PLL
13b567379cec drm/i915: Use a fixed N value always
47089a91ef2e drm/i915: Round to closest in M/N calculations
4776e9b1dc55 drm/i915: Round TMDS clock to nearest

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)
URL   : https://patchwork.freedesktop.org/series/103491/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/bios: Rework BDB block handling (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: Rework BDB block handling (rev6)
URL   : https://patchwork.freedesktop.org/series/101496/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11607 -> Patchwork_101496v6


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_101496v6 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_101496v6, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/index.html

Participating hosts (41 -> 41)
--

  Additional (3): fi-hsw-4770 fi-icl-u2 bat-dg2-9 
  Missing(3): fi-kbl-soraka fi-rkl-11600 fi-bsw-cyan 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_101496v6:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hugepages:
- fi-icl-u2:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-icl-u2/igt@i915_selftest@l...@hugepages.html

  
Known issues


  Here are the changes found in Patchwork_101496v6 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271]) +9 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3012])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][6] ([i915#4785])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +7 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][9] ([fdo#111827]) +7 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([fdo#109278]) +2 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][11] ([fdo#109285])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2:  NOTRUN -> [SKIP][14] ([i915#3555])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([i915#3301])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-icl-u2/igt@prime_v...@basic-userptr.html

  * igt@runner@aborted:
- fi-icl-u2:  NOTRUN -> [FAIL][16] ([i915#4312])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v6/fi-icl-u2/igt@run...@aborted.html
 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/bios: Rework BDB block handling (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: Rework BDB block handling (rev6)
URL   : https://patchwork.freedesktop.org/series/101496/
State : warning

== Summary ==

Error: dim checkpatch failed
876e81fcc079 drm/i915/bios: Reorder panel DTD parsing
326b27338109 drm/i915/bios: Generate LFP data table pointers if the VBT lacks 
them
-:46: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#46: FILE: drivers/gpu/drm/i915/display/intel_bios.c:319:
+   if (data[i] == 0xff && data[i+1] == 0xff)
 ^

-:134: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#134: FILE: drivers/gpu/drm/i915/display/intel_bios.c:407:
+   next_lfp_data_ptr(&ptrs->ptr[i].fp_timing, 
&ptrs->ptr[i-1].fp_timing, size);
   ^

-:135: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#135: FILE: drivers/gpu/drm/i915/display/intel_bios.c:408:
+   next_lfp_data_ptr(&ptrs->ptr[i].dvo_timing, 
&ptrs->ptr[i-1].dvo_timing, size);
^

-:136: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#136: FILE: drivers/gpu/drm/i915/display/intel_bios.c:409:
+   next_lfp_data_ptr(&ptrs->ptr[i].panel_pnp_id, 
&ptrs->ptr[i-1].panel_pnp_id, size);
  ^

total: 0 errors, 0 warnings, 4 checks, 161 lines checked
35c60af6bb1f drm/i915/bios: Get access to the tail end of the LFP data block
71f95ff8c3ef drm/i915/bios: Document the mess around the LFP data tables
e9170fcfc201 drm/i915/bios: Assume panel_type==0 if the VBT has bogus data
bfc8971c33c6 drm/i915/bios: Extract get_panel_type()
dec911cb1f83 drm/i915/bios: Refactor panel_type code
256a5ae6951e drm/i915/bios: Parse the seamless DRRS min refresh rate
683197035787 drm/i915: Respect VBT seamless DRRS min refresh rate

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/bios: Rework BDB block handling (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: Rework BDB block handling (rev6)
URL   : https://patchwork.freedesktop.org/series/101496/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Prepare for GSC-loaded HuC (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Prepare for GSC-loaded HuC (rev2)
URL   : https://patchwork.freedesktop.org/series/103186/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11607 -> Patchwork_103186v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/index.html

Participating hosts (41 -> 44)
--

  Additional (5): bat-dg1-6 bat-adlm-1 fi-icl-u2 bat-dg2-9 fi-hsw-4770 
  Missing(2): fi-rkl-11600 fi-bsw-cyan 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103186v2:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gt_mocs:
- {bat-adlm-1}:   NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/bat-adlm-1/igt@i915_selftest@live@gt_mocs.html

  
Known issues


  Here are the changes found in Patchwork_103186v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271]) +9 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html
- fi-icl-u2:  NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_mmap@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/bat-dg1-6/igt@gem_m...@basic.html

  * igt@gem_tiled_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/bat-dg1-6/igt@gem_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg1-6:  NOTRUN -> [SKIP][7] ([i915#4079]) +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/bat-dg1-6/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3012])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html
- bat-dg1-6:  NOTRUN -> [SKIP][9] ([i915#1155])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-6:  NOTRUN -> [INCOMPLETE][10] ([i915#4418])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/bat-dg1-6/igt@i915_selftest@live@gt_engines.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-dg1-6:  NOTRUN -> [SKIP][11] ([i915#4212]) +7 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/bat-dg1-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6:  NOTRUN -> [SKIP][12] ([i915#4215])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-g3258:   NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-edid-read:
- bat-dg1-6:  NOTRUN -> [SKIP][15] ([fdo#111827]) +7 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/bat-dg1-6/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][16] ([fdo#111827]) +8 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg1-6:  NOTRUN -> [SKIP][17] ([i915#4103] / [i915#4213]) +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103186v2/bat-dg1-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
-

Re: [Intel-gfx] [PATCH 02/11] drm/i915/pvc: Add forcewake support

[Matt Roper]

On Mon, May 02, 2022 at 03:33:53PM -0700, Summers, Stuart wrote:
> On Mon, 2022-05-02 at 09:34 -0700, Matt Roper wrote:
> > Add PVC's forcewake ranges.
> >
> > Bspec: 67609
> > Cc: Daniele Ceraolo Spurio 
> > Signed-off-by: Matt Roper 
> > ---
> >  drivers/gpu/drm/i915/intel_uncore.c   | 150
> > +-
> >  drivers/gpu/drm/i915/selftests/intel_uncore.c |   2 +
> >  2 files changed, 151 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > b/drivers/gpu/drm/i915/intel_uncore.c
> > index 83517a703eb6..3352065635e8 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -1080,6 +1080,45 @@ static const struct i915_range
> > dg2_shadowed_regs[] = {
> >   { .start = 0x1F8510, .end = 0x1F8550 },
> >  };
> >
> > +static const struct i915_range pvc_shadowed_regs[] = {
> > + { .start =   0x2030, .end =   0x2030 },
> > + { .start =   0x2510, .end =   0x2550 },
> > + { .start =   0xA008, .end =   0xA00C },
> > + { .start =   0xA188, .end =   0xA188 },
> > + { .start =   0xA278, .end =   0xA278 },
> > + { .start =   0xA540, .end =   0xA56C },
> > + { .start =   0xC4C8, .end =   0xC4C8 },
> > + { .start =   0xC4E0, .end =   0xC4E0 },
> > + { .start =   0xC600, .end =   0xC600 },
> > + { .start =   0xC658, .end =   0xC658 },
> > + { .start =  0x22030, .end =  0x22030 },
> > + { .start =  0x22510, .end =  0x22550 },
> > + { .start = 0x1C0030, .end = 0x1C0030 },
> > + { .start = 0x1C0510, .end = 0x1C0550 },
> > + { .start = 0x1C4030, .end = 0x1C4030 },
> > + { .start = 0x1C4510, .end = 0x1C4550 },
> > + { .start = 0x1C8030, .end = 0x1C8030 },
> > + { .start = 0x1C8510, .end = 0x1C8550 },
> > + { .start = 0x1D0030, .end = 0x1D0030 },
> > + { .start = 0x1D0510, .end = 0x1D0550 },
> > + { .start = 0x1D4030, .end = 0x1D4030 },
> > + { .start = 0x1D4510, .end = 0x1D4550 },
> > + { .start = 0x1D8030, .end = 0x1D8030 },
> > + { .start = 0x1D8510, .end = 0x1D8550 },
> > + { .start = 0x1E0030, .end = 0x1E0030 },
> > + { .start = 0x1E0510, .end = 0x1E0550 },
> > + { .start = 0x1E4030, .end = 0x1E4030 },
> > + { .start = 0x1E4510, .end = 0x1E4550 },
> > + { .start = 0x1E8030, .end = 0x1E8030 },
> > + { .start = 0x1E8510, .end = 0x1E8550 },
> > + { .start = 0x1F0030, .end = 0x1F0030 },
> > + { .start = 0x1F0510, .end = 0x1F0550 },
> > + { .start = 0x1F4030, .end = 0x1F4030 },
> > + { .start = 0x1F4510, .end = 0x1F4550 },
> > + { .start = 0x1F8030, .end = 0x1F8030 },
> > + { .start = 0x1F8510, .end = 0x1F8550 },
> > +};
> > +
> >  static int mmio_range_cmp(u32 key, const struct i915_range *range)
> >  {
> >   if (key < range->start)
> > @@ -1490,6 +1529,111 @@ static const struct intel_forcewake_range
> > __dg2_fw_ranges[] = {
> >   XEHP_FWRANGES(FORCEWAKE_RENDER)
> >  };
> >
> > +/*
> > + * *Must* be sorted by offset ranges! See intel_fw_table_check().
> > + *
> > + * Note that the spec lists several reserved/unused ranges that
> > don't actually
> > + * contain any registers.  In the table below we'll combine those
> > reserved
> > + * ranges with either the preceding or following range to keep the
> > table small
> 
> Looks like not just the reserved ranges are being used here. Maybe add
> "combine all ranges with preceding or following range with similar FW
> unit" or something similar.

The comment here is a duplicate of the one on the TGL table.  We've been
copy/pasting it onto new forcewake tables, but we should probably just
delete all except one of those comments and clarify that it applies to
all tables now (and possibly tweak the wording if necessary).

By "similar FW unit" are you referring to where the bspec has table rows
like:

0x1000 - 0x1fff:  GT
0x2000 - 0x2fff:  GT

so the same domain shows up on consecutive rows?  The fact that those
even show up as two rows in the bspec is a relatively new change due to
the hardware people starting to document additional information in the
same table (e.g., multicast register characteristics); back when the
comment was written the extra information hadn't been added so there
really was only a single consolidated range in the spec for cases like
this.


Matt

> 
> Thanks,
> Stuart
> 
> > + * and lookups fast.
> > + */
> > +static const struct intel_forcewake_range __pvc_fw_ranges[] = {
> > + GEN_FW_RANGE(0x0, 0xaff, 0),
> > + GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
> > + GEN_FW_RANGE(0xc00, 0xfff, 0),
> > + GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT),
> > + GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
> > + GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
> > + GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
> > + GEN_FW_RANGE(0x4000, 0x813f, FORCEWAKE_GT), /*
> > + 0x4000 - 0x4aff: gt
> > + 0x4b00 - 0x4fff: reserved
> > + 0x5000 - 0x51ff: gt

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Prepare for GSC-loaded HuC (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Prepare for GSC-loaded HuC (rev2)
URL   : https://patchwork.freedesktop.org/series/103186/
State : warning

== Summary ==

Error: dim checkpatch failed
6c310d719f23 drm/i915/huc: drop intel_huc_is_authenticated
-:6: WARNING:TYPO_SPELLING: 'fuction' may be misspelled - perhaps 'function'?
#6: 
The fuction name is confusing, because it doesn't check the actual auth
^^^

total: 0 errors, 1 warnings, 0 checks, 19 lines checked
084f343e6130 drm/i915/huc: Add fetch support for gsc-loaded HuC binary
3a2dd8822f93 drm/i915/huc: Prepare for GSC-loaded HuC
-:25: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#25: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h:99:
+#define   GSC_LOADS_HUC(1<<30)
  ^

total: 0 errors, 0 warnings, 1 checks, 209 lines checked
7ea03ed800d8 drm/i915/huc: Don't fail the probe if HuC init fails

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dmc: Add MMIO range restrictions (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add MMIO range restrictions (rev5)
URL   : https://patchwork.freedesktop.org/series/102630/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11607 -> Patchwork_102630v5


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/index.html

Participating hosts (41 -> 39)
--

  Additional (2): fi-hsw-4770 bat-dg2-9 
  Missing(4): fi-kbl-soraka bat-dg2-8 fi-rkl-11600 fi-bsw-cyan 

Known issues


  Here are the changes found in Patchwork_102630v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/fi-hsw-4770/igt@gem_huc_c...@huc-copy.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#3012])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-g3258:   NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#533])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/fi-hsw-4770/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770:NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1072]) +3 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][7] ([i915#3303] / [i915#4785]) -> 
[PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
- {fi-ehl-2}: [INCOMPLETE][9] ([i915#5134]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- {bat-rpls-1}:   [INCOMPLETE][11] ([i915#4983] / [i915#5338]) -> 
[PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/bat-rpls-1/igt@i915_selftest@l...@requests.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102630v5/bat-rpls-1/igt@i915_selftest@l...@requests.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5134]: https://gitlab.freedesktop.org/drm/intel/issues/5134
  [i915#5171]: https://gitlab.freedesktop.org/drm/intel/issues/5171
  [i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
  [i915#5181]: https://gitlab.freedesktop.org/drm/intel/issues/5181
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5338]: https://gitlab.freedesktop.org/drm/intel/issues/5338
  [i915#5606]: https://gitlab.freedesktop.org/drm/intel/issues/5606
  [i915#5703]: https://gitlab.freedesktop.org/drm/intel/issues/5703
  [i915#5775]: https://gitlab.freedesktop.org/drm/intel/issues/5775


Build changes
-

  * Linux: CI_DRM_11607 -> Patchwork_102630v5

  CI-20190529: 20190529
  CI_DRM_11607: b0f0de5bb000952abb29696adb93f289e49b129c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6465: f6bb4399881a806f

[Intel-gfx] [PATCH v2] drm/i915/guc: Support programming the EU priority in the GuC descriptor

[Daniele Ceraolo Spurio]

From: Matthew Brost 

In GuC submission mode the EU priority must be updated by the GuC rather
than the driver as the GuC owns the programming of the context descriptor.

Given that the GuC code uses the GuC priorities, we can't use a generic
function using i915 priorities for both execlists and GuC submission.
The existing function has therefore been pushed to the execlists
back-end while a new one has been added for GuC.

v2: correctly use the GuC prio.

Cc: John Harrison 
Cc: Matt Roper 
Signed-off-by: Matthew Brost 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Daniele Ceraolo Spurio 
---
 .../drm/i915/gt/intel_execlists_submission.c  | 12 +-
 drivers/gpu/drm/i915/gt/intel_lrc.h   | 10 -
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 22 +++
 3 files changed, 33 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 86f7a9ac1c394..2b0266cab66b9 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -661,6 +661,16 @@ static inline void execlists_schedule_out(struct 
i915_request *rq)
i915_request_put(rq);
 }
 
+static u32 map_i915_prio_to_lrc_desc_prio(int prio)
+{
+   if (prio > I915_PRIORITY_NORMAL)
+   return GEN12_CTX_PRIORITY_HIGH;
+   else if (prio < I915_PRIORITY_NORMAL)
+   return GEN12_CTX_PRIORITY_LOW;
+   else
+   return GEN12_CTX_PRIORITY_NORMAL;
+}
+
 static u64 execlists_update_context(struct i915_request *rq)
 {
struct intel_context *ce = rq->context;
@@ -669,7 +679,7 @@ static u64 execlists_update_context(struct i915_request *rq)
 
desc = ce->lrc.desc;
if (rq->engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
-   desc |= lrc_desc_priority(rq_prio(rq));
+   desc |= map_i915_prio_to_lrc_desc_prio(rq_prio(rq));
 
/*
 * WaIdleLiteRestore:bdw,skl
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h 
b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 31be734010db3..a390f0813c8b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -111,16 +111,6 @@ enum {
 #define XEHP_SW_COUNTER_SHIFT  58
 #define XEHP_SW_COUNTER_WIDTH  6
 
-static inline u32 lrc_desc_priority(int prio)
-{
-   if (prio > I915_PRIORITY_NORMAL)
-   return GEN12_CTX_PRIORITY_HIGH;
-   else if (prio < I915_PRIORITY_NORMAL)
-   return GEN12_CTX_PRIORITY_LOW;
-   else
-   return GEN12_CTX_PRIORITY_NORMAL;
-}
-
 static inline void lrc_runtime_start(struct intel_context *ce)
 {
struct intel_context_stats *stats = &ce->stats;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 75291e9846c50..8bf8b6d588d43 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2394,6 +2394,26 @@ static int guc_context_policy_init(struct intel_context 
*ce, bool loop)
return ret;
 }
 
+static u32 map_guc_prio_to_lrc_desc_prio(u8 prio)
+{
+   /*
+* this matches the mapping we do in map_i915_prio_to_guc_prio()
+* (e.g. prio < I915_PRIORITY_NORMAL maps to GUC_CLIENT_PRIORITY_NORMAL)
+*/
+   switch (prio) {
+   default:
+   MISSING_CASE(prio);
+   fallthrough;
+   case GUC_CLIENT_PRIORITY_KMD_NORMAL:
+   return GEN12_CTX_PRIORITY_NORMAL;
+   case GUC_CLIENT_PRIORITY_NORMAL:
+   return GEN12_CTX_PRIORITY_LOW;
+   case GUC_CLIENT_PRIORITY_HIGH:
+   case GUC_CLIENT_PRIORITY_KMD_HIGH:
+   return GEN12_CTX_PRIORITY_HIGH;
+   }
+}
+
 static void prepare_context_registration_info(struct intel_context *ce,
  struct guc_ctxt_registration_info 
*info)
 {
@@ -2420,6 +2440,8 @@ static void prepare_context_registration_info(struct 
intel_context *ce,
 */
info->hwlrca_lo = lower_32_bits(ce->lrc.lrca);
info->hwlrca_hi = upper_32_bits(ce->lrc.lrca);
+   if (engine->flags & I915_ENGINE_HAS_EU_PRIORITY)
+   info->hwlrca_lo |= 
map_guc_prio_to_lrc_desc_prio(ce->guc_state.prio);
info->flags = CONTEXT_REGISTRATION_FLAG_KMD;
 
/*
-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/12] drm/i915: Drop IPC from display 13 and newer

[Patchwork]

== Series Details ==

Series: series starting with [01/12] drm/i915: Drop IPC from display 13 and 
newer
URL   : https://patchwork.freedesktop.org/series/103562/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11606 -> Patchwork_103562v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/index.html

Participating hosts (42 -> 40)
--

  Additional (1): bat-adlm-1 
  Missing(3): fi-bsw-cyan bat-dg2-9 bat-dg1-5 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103562v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@module-reload:
- {bat-adlm-1}:   NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/bat-adlm-1/igt@i915_pm_...@module-reload.html

  
Known issues


  Here are the changes found in Patchwork_103562v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][2] -> [INCOMPLETE][3] ([i915#4785])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-pnv-d510:NOTRUN -> [SKIP][4] ([fdo#109271])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-g3258:   NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#4312] / 
[i915#5594])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/fi-hsw-4770/igt@run...@aborted.html

  
 Possible fixes 

  * igt@core_hotunplug@unbind-rebind:
- {bat-rpls-2}:   [DMESG-WARN][7] ([i915#4391]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/bat-rpls-2/igt@core_hotunp...@unbind-rebind.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/bat-rpls-2/igt@core_hotunp...@unbind-rebind.html

  * igt@i915_selftest@live@client:
- {bat-dg2-8}:[DMESG-FAIL][9] ([i915#5879]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/bat-dg2-8/igt@i915_selftest@l...@client.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/bat-dg2-8/igt@i915_selftest@l...@client.html

  * igt@i915_selftest@live@gtt:
- fi-bdw-5557u:   [DMESG-FAIL][11] ([i915#3674]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][13] ([i915#3303] / [i915#4785]) -> 
[PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][15] ([i915#4528]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/fi-pnv-d510/igt@i915_selftest@l...@requests.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103562v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3674]: https://gitlab.freedesktop.org/drm/intel/issues/3674
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/12] drm/i915: Drop IPC from display 13 and newer

[Patchwork]

== Series Details ==

Series: series starting with [01/12] drm/i915: Drop IPC from display 13 and 
newer
URL   : https://patchwork.freedesktop.org/series/103562/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/12] drm/i915: Drop IPC from display 13 and newer

[Patchwork]

== Series Details ==

Series: series starting with [01/12] drm/i915: Drop IPC from display 13 and 
newer
URL   : https://patchwork.freedesktop.org/series/103562/
State : warning

== Summary ==

Error: dim checkpatch failed
fe464ec005a5 drm/i915: Drop IPC from display 13 and newer
-:29: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible 
side-effects?
#29: FILE: drivers/gpu/drm/i915/i915_drv.h:1347:
+#define HAS_IPC(dev_priv)   (DISPLAY_VER(dev_priv) >= 9 && \
+ DISPLAY_VER(dev_priv) <= 12)

total: 0 errors, 0 warnings, 1 checks, 37 lines checked
bf709b66d5eb drm/i915/display: Disable DSB for DG2 and Alderlake-P
d6397bf6d28a drm/i915: Drop has_gt_uc from device info
41e40333f07a drm/i915: Drop has_rc6 from device info
6648e12a8320 drm/i915: Drop has_rc6p from device info
-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible 
side-effects?
#25: FILE: drivers/gpu/drm/i915/i915_drv.h:1313:
+#define HAS_RC6p(dev_priv)  (GRAPHICS_VER(dev_priv) >= 6 && \
+ GRAPHICS_VER(dev_priv) <= 7 && \
+ !IS_HASWELL(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 38 lines checked
a491192e6234 drm/i915: Drop has_reset_engine from device info
7a051e739286 drm/i915: Drop has_logical_ring_elsq from device info
707c49a2bf72 drm/i915: Drop has_ddi from device info
-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible 
side-effects?
#25: FILE: drivers/gpu/drm/i915/i915_drv.h:1302:
+#define HAS_DDI(dev_priv)   (DISPLAY_VER(dev_priv) >= 9 || \
+ IS_HASWELL(dev_priv) || \
+ IS_BROADWELL(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 38 lines checked
0ada70a2b0be drm/i915: Drop has_dp_mst from device info
0f2bb0d4f67d drm/i915: Drop has_psr from device info
85050c08ff9a drm/i915: Drop has_psr_hw_tracking from device info
-:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible 
side-effects?
#26: FILE: drivers/gpu/drm/i915/i915_drv.h:1307:
+#define HAS_PSR_HW_TRACKING(dev_priv)   ((DISPLAY_VER(dev_priv) >= 9 && \
+  DISPLAY_VER(dev_priv) <= 11) || \
+ IS_TIGERLAKE(dev_priv) || \
+ IS_DG1(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 54 lines checked
37af30910ec8 drm/i915: Drop supports_tv from device info
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible 
side-effects?
#23: FILE: drivers/gpu/drm/i915/i915_drv.h:1289:
+#define SUPPORTS_TV(dev_priv)  (IS_I915GM(dev_priv) || 
IS_I945GM(dev_priv) || \
+IS_I965GM(dev_priv) || 
IS_GM45(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 46 lines checked

Re: [Intel-gfx] [PATCH v2 00/20] drm/edid: CEA data block iterators, and more

[Ville Syrjälä]

On Tue, May 03, 2022 at 12:23:45PM +0300, Jani Nikula wrote:
> I've kind of lost track of the version numbers on some of the iterator
> patches, but this is the next version (or mostly a resend) of
> [1]. There's an additional rename patch for SCDS.
> 
> BR,
> Jani.
> 
> 
> [1] https://patchwork.freedesktop.org/series/102703/
> 
> 
> Jani Nikula (19):
>   drm/edid: reset display info in drm_add_edid_modes() for NULL edid
>   drm/edid: rename HDMI Forum VSDB to SCDS
>   drm/edid: clean up CTA data block tag definitions
>   drm/edid: add iterator for EDID base and extension blocks
>   drm/edid: add iterator for CTA data blocks
>   drm/edid: clean up cea_db_is_*() functions
>   drm/edid: convert add_cea_modes() to use cea db iter
>   drm/edid: convert drm_edid_to_speaker_allocation() to use cea db iter
>   drm/edid: convert drm_edid_to_sad() to use cea db iter
>   drm/edid: convert drm_detect_hdmi_monitor() to use cea db iter
>   drm/edid: convert drm_detect_monitor_audio() to use cea db iter
>   drm/edid: convert drm_parse_cea_ext() to use cea db iter
>   drm/edid: convert drm_edid_to_eld() to use cea db iter
>   drm/edid: sunset the old unused cea data block iterators
>   drm/edid: restore some type safety to cea_db_*() functions
>   drm/edid: detect basic audio in all CEA extensions
>   drm/edid: skip CTA extension scan in drm_edid_to_eld() just for CTA
> rev
>   drm/edid: sunset drm_find_cea_extension()
> 
> Lee Shawn C (1):
>   drm/edid: check for HF-SCDB block

All of the above patches look OK to me.
Reviewed-by: Ville Syrjälä 

>   drm/edid: detect color formats and CTA revision in all CTA extensions

For this one I'm not entirely convinced the behavioural change
for the no-CTA ext case is what we want. Replied to that one
individually.

> 
>  drivers/gpu/drm/drm_edid.c | 799 +
>  1 file changed, 458 insertions(+), 341 deletions(-)
> 
> -- 
> 2.30.2

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v2 13/20] drm/edid: convert drm_parse_cea_ext() to use cea db iter

[Ville Syrjälä]

On Tue, May 03, 2022 at 12:23:58PM +0300, Jani Nikula wrote:
> Iterate through all CTA data blocks across all CTA Extensions and
> DisplayID data blocks.
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/drm_edid.c | 25 +
>  1 file changed, 13 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 3433d9fa4799..98b2e6164468 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -5497,8 +5497,9 @@ static void drm_parse_cea_ext(struct drm_connector 
> *connector,
> const struct edid *edid)
>  {
>   struct drm_display_info *info = &connector->display_info;
> + const struct cea_db *db;
> + struct cea_db_iter iter;
>   const u8 *edid_ext;
> - int i, start, end;
>  
>   edid_ext = drm_find_cea_extension(edid);
>   if (!edid_ext)
> @@ -5517,26 +5518,26 @@ static void drm_parse_cea_ext(struct drm_connector 
> *connector,
>   info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
>   }
>  
> - if (cea_db_offsets(edid_ext, &start, &end))
> - return;
> -
> - for_each_cea_db(edid_ext, i, start, end) {
> - const u8 *db = &edid_ext[i];
> + cea_db_iter_edid_begin(edid, &iter);
> + cea_db_iter_for_each(db, &iter) {
> + /* FIXME: convert parsers to use struct cea_db */
> + const u8 *data = (const u8 *)db;
>  
>   if (cea_db_is_hdmi_vsdb(db))
> - drm_parse_hdmi_vsdb_video(connector, db);
> + drm_parse_hdmi_vsdb_video(connector, data);
>   if (cea_db_is_hdmi_forum_vsdb(db) ||
>   cea_db_is_hdmi_forum_scdb(db))

BTW looks like all of these could be 'else if'. Dunno if that actually
affects the generated code though, or if the compiler is smart enough
to see only one condition can by true.

Reviewed-by: Ville Syrjälä 

> - drm_parse_hdmi_forum_scds(connector, db);
> + drm_parse_hdmi_forum_scds(connector, data);
>   if (cea_db_is_microsoft_vsdb(db))
> - drm_parse_microsoft_vsdb(connector, db);
> + drm_parse_microsoft_vsdb(connector, data);
>   if (cea_db_is_y420cmdb(db))
> - drm_parse_y420cmdb_bitmap(connector, db);
> + drm_parse_y420cmdb_bitmap(connector, data);
>   if (cea_db_is_vcdb(db))
> - drm_parse_vcdb(connector, db);
> + drm_parse_vcdb(connector, data);
>   if (cea_db_is_hdmi_hdr_metadata_block(db))
> - drm_parse_hdr_metadata_block(connector, db);
> + drm_parse_hdr_metadata_block(connector, data);
>   }
> + cea_db_iter_end(&iter);
>  }
>  
>  static
> -- 
> 2.30.2

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v2 18/20] drm/edid: detect color formats and CTA revision in all CTA extensions

[Ville Syrjälä]

On Tue, May 03, 2022 at 12:24:03PM +0300, Jani Nikula wrote:
> Convert drm_find_cea_extension() to EDID block iterator in color format
> and CTA revision detection. Detect them in all CTA extensions.
> 
> Also parse CTA Data Blocks in DisplayID even if there's no CTA EDID
> extension.
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/drm_edid.c | 24 
>  1 file changed, 16 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 3b18a6e501df..41f24f4c2d23 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -5447,32 +5447,40 @@ static void drm_parse_cea_ext(struct drm_connector 
> *connector,
> const struct edid *edid)
>  {
>   struct drm_display_info *info = &connector->display_info;
> + struct drm_edid_iter edid_iter;
>   const struct cea_db *db;
>   struct cea_db_iter iter;
>   const u8 *edid_ext;
>  
> - edid_ext = drm_find_cea_extension(edid);
> - if (!edid_ext)
> - return;
> + drm_edid_iter_begin(edid, &edid_iter);
> + drm_edid_iter_for_each(edid_ext, &edid_iter) {
> + if (edid_ext[0] != CEA_EXT)
> + continue;
>  
> - info->cea_rev = edid_ext[1];
> + if (!info->cea_rev)
> + info->cea_rev = edid_ext[1];
>  
> - /* The existence of a CEA block should imply RGB support */
> - info->color_formats = DRM_COLOR_FORMAT_RGB444;
> + if (info->cea_rev != edid_ext[1])
> + DRM_DEBUG_KMS("CEA extension version mismatch %u != 
> %u\n",
> +   info->cea_rev, edid_ext[1]);
>  
> - /* CTA DisplayID Data Block does not have byte #3 */
> - if (edid_ext[0] == CEA_EXT) {
> + /* The existence of a CTA extension should imply RGB support */
> + info->color_formats = DRM_COLOR_FORMAT_RGB444;
>   if (edid_ext[3] & EDID_CEA_YCRCB444)
>   info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
>   if (edid_ext[3] & EDID_CEA_YCRCB422)
>   info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
>   }
> + drm_edid_iter_end(&edid_iter);
>  
>   cea_db_iter_edid_begin(edid, &iter);
>   cea_db_iter_for_each(db, &iter) {
>   /* FIXME: convert parsers to use struct cea_db */
>   const u8 *data = (const u8 *)db;
>  
> + /* The existence of a CTA block should imply RGB support */
> + info->color_formats = DRM_COLOR_FORMAT_RGB444;

This part seems a bit iffy. DisplayID has its own way to specify the
supported color depths/encodings. So I think eventually we'll just
want to split this into three logical parts: parse CTA ext block,
parse DispID color stuff, parse CTA data blocks.

> +
>   if (cea_db_is_hdmi_vsdb(db))
>   drm_parse_hdmi_vsdb_video(connector, data);
>   if (cea_db_is_hdmi_forum_vsdb(db) ||
> -- 
> 2.30.2

-- 
Ville Syrjälä
Intel

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: remove unused GEM_DEBUG_DECL() and GEM_DEBUG_BUG_ON()

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: remove unused GEM_DEBUG_DECL() and 
GEM_DEBUG_BUG_ON()
URL   : https://patchwork.freedesktop.org/series/103560/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11606 -> Patchwork_103560v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/index.html

Participating hosts (42 -> 41)
--

  Additional (2): bat-rpls-1 fi-rkl-11600 
  Missing(3): bat-dg2-8 fi-bsw-cyan bat-dg1-5 

Known issues


  Here are the changes found in Patchwork_103560v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-rkl-11600:   NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html

  * igt@gem_tiled_pread_basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][3] ([i915#3282])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600:   NOTRUN -> [SKIP][4] ([i915#3012])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][5] -> [INCOMPLETE][6] ([i915#4785])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[PASS][7] -> [INCOMPLETE][8] ([i915#3921])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@mman:
- fi-bdw-5557u:   [PASS][9] -> [INCOMPLETE][10] ([i915#5704])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/fi-bdw-5557u/igt@i915_selftest@l...@mman.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-bdw-5557u/igt@i915_selftest@l...@mman.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-pnv-d510:NOTRUN -> [SKIP][11] ([fdo#109271])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-g3258:   NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-rkl-11600:   NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-rkl-11600/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-rkl-11600:   NOTRUN -> [SKIP][14] ([i915#4070] / [i915#4103]) +1 
similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600:   NOTRUN -> [SKIP][15] ([fdo#109285] / [i915#4098])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-rkl-11600/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-rkl-11600:   NOTRUN -> [SKIP][16] ([i915#4070] / [i915#533])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-rkl-11600/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-rkl-11600:   NOTRUN -> [SKIP][17] ([i915#1072]) +3 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-rkl-11600/igt@kms_psr@primary_mmap_gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-rkl-11600:   NOTRUN -> [SKIP][18] ([i915#3555] / [i915#4098])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-rkl-11600/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-rkl-11600:   NOTRUN -> [SKIP][19] ([i915#3301] / [i915#3708])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103560v1/fi-rkl-11600/igt@prime_v...@basic-userptr.html

  * igt@prime_vgem@basic-write:
- fi-rkl-11600:   NOTRUN -> [SKIP][20] ([i915#3291] / [i915#3708]) +2 
similar issues
   [20]: 
https:/

Re: [Intel-gfx] [PATCH v2 03/20] drm/edid: rename HDMI Forum VSDB to SCDS

[Ville Syrjälä]

On Tue, May 03, 2022 at 12:23:48PM +0300, Jani Nikula wrote:
> The HDMI spec talks about SCDS, Sink Capability Data Structure, exposed
> via HF-VSDB or HF-SCDB. Rename VSDB to SCDS.
> 
> Suggested-by: Ville Syrjälä 
> Signed-off-by: Jani Nikula 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/drm_edid.c | 41 +++---
>  1 file changed, 21 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index fe527a0c50bc..18d05cbb2124 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -5132,17 +5132,18 @@ static void drm_parse_ycbcr420_deep_color_info(struct 
> drm_connector *connector,
>   hdmi->y420_dc_modes = dc_mask;
>  }
>  
> -static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
> -  const u8 *hf_vsdb)
> +/* Sink Capability Data Structure */
> +static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
> +   const u8 *hf_scds)
>  {
>   struct drm_display_info *display = &connector->display_info;
>   struct drm_hdmi_info *hdmi = &display->hdmi;
>  
>   display->has_hdmi_infoframe = true;
>  
> - if (hf_vsdb[6] & 0x80) {
> + if (hf_scds[6] & 0x80) {
>   hdmi->scdc.supported = true;
> - if (hf_vsdb[6] & 0x40)
> + if (hf_scds[6] & 0x40)
>   hdmi->scdc.read_request = true;
>   }
>  
> @@ -5155,9 +5156,9 @@ static void drm_parse_hdmi_forum_vsdb(struct 
> drm_connector *connector,
>* Lets check it out.
>*/
>  
> - if (hf_vsdb[5]) {
> + if (hf_scds[5]) {
>   /* max clock is 5000 KHz times block value */
> - u32 max_tmds_clock = hf_vsdb[5] * 5000;
> + u32 max_tmds_clock = hf_scds[5] * 5000;
>   struct drm_scdc *scdc = &hdmi->scdc;
>  
>   if (max_tmds_clock > 34) {
> @@ -5170,42 +5171,42 @@ static void drm_parse_hdmi_forum_vsdb(struct 
> drm_connector *connector,
>   scdc->scrambling.supported = true;
>  
>   /* Few sinks support scrambling for clocks < 340M */
> - if ((hf_vsdb[6] & 0x8))
> + if ((hf_scds[6] & 0x8))
>   scdc->scrambling.low_rates = true;
>   }
>   }
>  
> - if (hf_vsdb[7]) {
> + if (hf_scds[7]) {
>   u8 max_frl_rate;
>   u8 dsc_max_frl_rate;
>   u8 dsc_max_slices;
>   struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
>  
>   DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
> - max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
> + max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
>   drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
>&hdmi->max_frl_rate_per_lane);
> - hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2;
> + hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
>  
>   if (hdmi_dsc->v_1p2) {
> - hdmi_dsc->native_420 = hf_vsdb[11] & 
> DRM_EDID_DSC_NATIVE_420;
> - hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP;
> + hdmi_dsc->native_420 = hf_scds[11] & 
> DRM_EDID_DSC_NATIVE_420;
> + hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
>  
> - if (hf_vsdb[11] & DRM_EDID_DSC_16BPC)
> + if (hf_scds[11] & DRM_EDID_DSC_16BPC)
>   hdmi_dsc->bpc_supported = 16;
> - else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC)
> + else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
>   hdmi_dsc->bpc_supported = 12;
> - else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC)
> + else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
>   hdmi_dsc->bpc_supported = 10;
>   else
>   hdmi_dsc->bpc_supported = 0;
>  
> - dsc_max_frl_rate = (hf_vsdb[12] & 
> DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
> + dsc_max_frl_rate = (hf_scds[12] & 
> DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
>   drm_get_max_frl_rate(dsc_max_frl_rate, 
> &hdmi_dsc->max_lanes,
>&hdmi_dsc->max_frl_rate_per_lane);
> - hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & 
> DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
> + hdmi_dsc->total_chunk_kbytes = hf_scds[13] & 
> DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
>  
> - dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES;
> + dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
>   switch (dsc_max_slices) {
>   case

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dmc: Add MMIO range restrictions (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add MMIO range restrictions (rev7)
URL   : https://patchwork.freedesktop.org/series/102168/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11606 -> Patchwork_102168v7


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/index.html

Participating hosts (42 -> 42)
--

  Additional (3): bat-rpls-1 fi-icl-u2 bat-dg1-6 
  Missing(3): fi-bsw-cyan bat-dg2-9 bat-dg1-5 

Known issues


  Here are the changes found in Patchwork_102168v7 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/fi-icl-u2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_mmap@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][3] ([i915#4083])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/bat-dg1-6/igt@gem_m...@basic.html

  * igt@gem_tiled_blits@basic:
- bat-dg1-6:  NOTRUN -> [SKIP][4] ([i915#4077]) +2 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/bat-dg1-6/igt@gem_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg1-6:  NOTRUN -> [SKIP][5] ([i915#4079]) +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/bat-dg1-6/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6:  NOTRUN -> [SKIP][6] ([i915#1155])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-6:  NOTRUN -> [INCOMPLETE][7] ([i915#4418])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/bat-dg1-6/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][8] -> [INCOMPLETE][9] ([i915#3921])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11606/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-dg1-6:  NOTRUN -> [SKIP][10] ([i915#4212]) +7 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/bat-dg1-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6:  NOTRUN -> [SKIP][11] ([i915#4215])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-pnv-d510:NOTRUN -> [SKIP][12] ([fdo#109271])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-g3258:   NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-edid-read:
- bat-dg1-6:  NOTRUN -> [SKIP][14] ([fdo#111827]) +7 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/bat-dg1-6/igt@kms_chamel...@hdmi-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg1-6:  NOTRUN -> [SKIP][16] ([i915#4103] / [i915#4213]) +1 
similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/bat-dg1-6/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2:  NOTRUN -> [SKIP][17] ([fdo#109278]) +2 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-6:  NOTRUN -> [SKIP][18] ([fdo#109285])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v7/bat-dg1-6/igt@kms_force_connector_ba...@force-load-detect.html
- fi-icl-u2:  NOTRUN -> [SKIP][19] ([fdo#109285])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_

Re: [Intel-gfx] [PATCH 01/12] drm/i915: Drop IPC from display 13 and newer

[Ville Syrjälä]

On Wed, May 04, 2022 at 12:07:45PM -0700, José Roberto de Souza wrote:
> This feature is supported from display 9 to display 12 and was
> incorrectly being applied to DG2 and Alderlake-P.

They just renamed the register to ARB_HP_CTL.

> 
> While at is also taking the oportunity to drop it from
> intel_device_info struct as a display check is more simple
> and less prone to be left enabled in future platforms.
> 
> BSpec: 50039
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c  | 3 ---
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  3 files changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2dddc27a1b0ed..695b35cd6b5e4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1344,7 +1344,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   */
>  #define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
>  
> -#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
> +#define HAS_IPC(dev_priv) (DISPLAY_VER(dev_priv) >= 9 && \
> +   DISPLAY_VER(dev_priv) <= 12)
>  
>  #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
>  #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 498708b33924f..c4f9c805cffd1 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -646,7 +646,6 @@ static const struct intel_device_info chv_info = {
>   .display.has_dmc = 1, \
>   .has_gt_uc = 1, \
>   .display.has_hdcp = 1, \
> - .display.has_ipc = 1, \
>   .display.has_psr = 1, \
>   .display.has_psr_hw_tracking = 1, \
>   .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
> @@ -712,7 +711,6 @@ static const struct intel_device_info skl_gt4_info = {
>   .has_reset_engine = 1, \
>   .has_snoop = true, \
>   .has_coherent_ggtt = false, \
> - .display.has_ipc = 1, \
>   HSW_PIPE_OFFSETS, \
>   IVB_CURSOR_OFFSETS, \
>   IVB_COLORS, \
> @@ -955,7 +953,6 @@ static const struct intel_device_info adl_s_info = {
>   .display.has_fpga_dbg = 1,  
> \
>   .display.has_hdcp = 1,  
> \
>   .display.has_hotplug = 1,   
> \
> - .display.has_ipc = 1,   
> \
>   .display.has_psr = 1,   
> \
>   .display.ver = 13,  
> \
>   .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | 
> BIT(PIPE_D), \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index e7d2cf7d65c85..c9660b4282d9e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -180,7 +180,6 @@ enum intel_ppgtt_type {
>   func(has_hdcp); \
>   func(has_hotplug); \
>   func(has_hti); \
> - func(has_ipc); \
>   func(has_modular_fia); \
>   func(has_overlay); \
>   func(has_psr); \
> -- 
> 2.36.0

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 05/12] drm/i915: Drop has_rc6p from device info

[Ville Syrjälä]

On Wed, May 04, 2022 at 12:07:49PM -0700, José Roberto de Souza wrote:
> No need to have this parameter in intel_device_info struct
> as it was only supported in graphics version 6 and 7 not including
> haswell.

nor vlv

> 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 4 +++-
>  drivers/gpu/drm/i915/i915_pci.c  | 3 ---
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  3 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d29dca83185ac..602e056edd314 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1310,7 +1310,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  
>  /* ilk does support rc6, but we do not implement [power] contexts */
>  #define HAS_RC6(dev_priv) (GRAPHICS_VER(dev_priv) >= 6)
> -#define HAS_RC6p(dev_priv)(INTEL_INFO(dev_priv)->has_rc6p)
> +#define HAS_RC6p(dev_priv)(GRAPHICS_VER(dev_priv) >= 6 && \
> +   GRAPHICS_VER(dev_priv) <= 7 && \
> +   !IS_HASWELL(dev_priv))
>  #define HAS_RC6pp(dev_priv)   (false) /* HW was never validated */
>  
>  #define HAS_RPS(dev_priv)(INTEL_INFO(dev_priv)->has_rps)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 90584c462f225..516f28d4db611 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -405,7 +405,6 @@ static const struct intel_device_info ilk_m_info = {
>   .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>   .has_coherent_ggtt = true, \
>   .has_llc = 1, \
> - .has_rc6p = 1, \
>   .has_rps = true, \
>   .dma_mask_size = 40, \
>   .ppgtt_type = INTEL_PPGTT_ALIASING, \
> @@ -455,7 +454,6 @@ static const struct intel_device_info snb_m_gt2_info = {
>   .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>   .has_coherent_ggtt = true, \
>   .has_llc = 1, \
> - .has_rc6p = 1, \
>   .has_reset_engine = true, \
>   .has_rps = true, \
>   .dma_mask_size = 40, \
> @@ -540,7 +538,6 @@ static const struct intel_device_info vlv_info = {
>   .display.has_ddi = 1, \
>   .display.has_fpga_dbg = 1, \
>   .display.has_dp_mst = 1, \
> - .has_rc6p = 0 /* RC6p removed-by HSW */, \
>   HSW_PIPE_OFFSETS, \
>   .has_runtime_pm = 1
>  
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index b3244170c4638..599cb265946b8 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -156,7 +156,6 @@ enum intel_ppgtt_type {
>   func(has_mslices); \
>   func(has_pooled_eu); \
>   func(has_pxp); \
> - func(has_rc6p); \
>   func(has_rps); \
>   func(has_runtime_pm); \
>   func(has_snoop); \
> -- 
> 2.36.0

-- 
Ville Syrjälä
Intel

[Intel-gfx] [PATCH v2 11/26] drm/i915: Introduce struct iclkip_params

[Ville Syrjala]

From: Ville Syrjälä 

Pull the various iCLKIP parameters into a struct. Later on
we'll reuse this during the state computation to determine
the exact dotclock the hardware will be generating for us.

v2: Don't lost the phaseinc calculation

Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_crt.c  |  1 +
 .../gpu/drm/i915/display/intel_pch_refclk.c   | 92 ---
 2 files changed, 58 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c 
b/drivers/gpu/drm/i915/display/intel_crt.c
index 6a3893c8ff22..d746c85e7e8c 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -46,6 +46,7 @@
 #include "intel_gmbus.h"
 #include "intel_hotplug.h"
 #include "intel_pch_display.h"
+#include "intel_pch_refclk.h"
 
 /* Here's the desired hotplug mode */
 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |   \
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c 
b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index b688fd87e3da..752dab11667f 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -122,16 +122,29 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
mutex_unlock(&dev_priv->sb_lock);
 }
 
-/* Program iCLKIP clock to the desired frequency */
-void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
+struct iclkip_params {
+   u32 iclk_virtual_root_freq;
+   u32 iclk_pi_range;
+   u32 divsel, phaseinc, auxdiv, phasedir, desired_divisor;
+};
+
+static void iclkip_params_init(struct iclkip_params *p)
 {
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   int clock = crtc_state->hw.adjusted_mode.crtc_clock;
-   u32 divsel, phaseinc, auxdiv, phasedir = 0;
-   u32 temp;
+   memset(p, 0, sizeof(*p));
+
+   p->iclk_virtual_root_freq = 172800 * 1000;
+   p->iclk_pi_range = 64;
+}
 
-   lpt_disable_iclkip(dev_priv);
+static int lpt_iclkip_freq(struct iclkip_params *p)
+{
+   return DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
+p->desired_divisor << p->auxdiv);
+}
+
+static void lpt_compute_iclkip(struct iclkip_params *p, int clock)
+{
+   iclkip_params_init(p);
 
/* The iCLK virtual clock root frequency is in MHz,
 * but the adjusted_mode->crtc_clock in KHz. To get the
@@ -139,50 +152,61 @@ void lpt_program_iclkip(const struct intel_crtc_state 
*crtc_state)
 * convert the virtual clock precision to KHz here for higher
 * precision.
 */
-   for (auxdiv = 0; auxdiv < 2; auxdiv++) {
-   u32 iclk_virtual_root_freq = 172800 * 1000;
-   u32 iclk_pi_range = 64;
-   u32 desired_divisor;
-
-   desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
-   clock << auxdiv);
-   divsel = (desired_divisor / iclk_pi_range) - 2;
-   phaseinc = desired_divisor % iclk_pi_range;
+   for (p->auxdiv = 0; p->auxdiv < 2; p->auxdiv++) {
+   p->desired_divisor = 
DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
+  clock << p->auxdiv);
+   p->divsel = (p->desired_divisor / p->iclk_pi_range) - 2;
+   p->phaseinc = p->desired_divisor % p->iclk_pi_range;
 
/*
 * Near 20MHz is a corner case which is
 * out of range for the 7-bit divisor
 */
-   if (divsel <= 0x7f)
+   if (p->divsel <= 0x7f)
break;
}
+}
+
+/* Program iCLKIP clock to the desired frequency */
+void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
+{
+   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   int clock = crtc_state->hw.adjusted_mode.crtc_clock;
+   struct iclkip_params p;
+   u32 temp;
+
+   lpt_disable_iclkip(dev_priv);
+
+   lpt_compute_iclkip(&p, clock);
+   drm_WARN_ON(&dev_priv->drm, lpt_iclkip_freq(&p) != clock);
 
/* This should not happen with any sane values */
-   drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
+   drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &
~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
-   drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
+   drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) &
~SBI_SSCDIVINTPHASE_INCVAL_MASK);
 
drm_dbg_kms(&dev_priv->drm,
"iCLKIP clock: found settings for %dKHz refresh rate: 
auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
-   clock, auxdiv, divsel, phasedir, phase

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc: Add MMIO range restrictions (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add MMIO range restrictions (rev7)
URL   : https://patchwork.freedesktop.org/series/102168/
State : warning

== Summary ==

Error: dim checkpatch failed
b3b699d828b8 drm/i915/dmc: Add MMIO range restrictions
-:77: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#77: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:483:
+   if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 
dmc_header->header_ver, dmc_id)) {

total: 0 errors, 1 warnings, 0 checks, 78 lines checked

Re: [Intel-gfx] [PATCH 11/12] drm/i915: Drop has_psr_hw_tracking from device info

[Matt Roper]

On Wed, May 04, 2022 at 12:07:55PM -0700, José Roberto de Souza wrote:
> No need to have this parameter in intel_device_info struct
> as this feature was only supported by display 9, display 11, tigerlake

The code below is correct, but the description here misses display
version 10 (i.e., GLK).

> and DG1, no newer platform will have this feature.
> 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 6 --
>  drivers/gpu/drm/i915/i915_pci.c  | 5 -
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  3 files changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d8fa1d09cc828..d866287c663a2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1304,8 +1304,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define HAS_DP_MST(dev_priv)  (HAS_DDI(dev_priv))
>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
> (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>  #define HAS_PSR(dev_priv) (DISPLAY_VER(dev_priv) >= 9)
> -#define HAS_PSR_HW_TRACKING(dev_priv) \
> - (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
> +#define HAS_PSR_HW_TRACKING(dev_priv) ((DISPLAY_VER(dev_priv) >= 9 
> && \
> +DISPLAY_VER(dev_priv) <= 11) || \

As noted before, we can simplify the range with IS_DISPLAY_VER.

Aside from the commit message tweak and the simplification here,

Reviewed-by: Matt Roper 

> +   IS_TIGERLAKE(dev_priv) || \
> +   IS_DG1(dev_priv))
>  #define HAS_PSR2_SEL_FETCH(dev_priv)  (DISPLAY_VER(dev_priv) >= 12)
>  #define HAS_TRANSCODER(dev_priv, trans)   
> ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
>  
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 098d47cc47b44..c6e99305e24d0 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -631,7 +631,6 @@ static const struct intel_device_info chv_info = {
>   GEN9_DEFAULT_PAGE_SIZES, \
>   .display.has_dmc = 1, \
>   .display.has_hdcp = 1, \
> - .display.has_psr_hw_tracking = 1, \
>   .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
>   .dbuf.slice_mask = BIT(DBUF_S1)
>  
> @@ -679,7 +678,6 @@ static const struct intel_device_info skl_gt4_info = {
>   .display.has_fpga_dbg = 1, \
>   .display.fbc_mask = BIT(INTEL_FBC_A), \
>   .display.has_hdcp = 1, \
> - .display.has_psr_hw_tracking = 1, \
>   .has_runtime_pm = 1, \
>   .display.has_dmc = 1, \
>   .has_rps = true, \
> @@ -865,7 +863,6 @@ static const struct intel_device_info rkl_info = {
>   .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>   BIT(TRANSCODER_C),
>   .display.has_hti = 1,
> - .display.has_psr_hw_tracking = 0,
>   .platform_engine_mask =
>   BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
>  };
> @@ -897,7 +894,6 @@ static const struct intel_device_info adl_s_info = {
>   PLATFORM(INTEL_ALDERLAKE_S),
>   .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | 
> BIT(PIPE_D),
>   .display.has_hti = 1,
> - .display.has_psr_hw_tracking = 0,
>   .platform_engine_mask =
>   BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>   .dma_mask_size = 39,
> @@ -955,7 +951,6 @@ static const struct intel_device_info adl_p_info = {
>  BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
>   .display.has_cdclk_crawl = 1,
>   .display.has_modular_fia = 1,
> - .display.has_psr_hw_tracking = 0,
>   .platform_engine_mask =
>   BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>   .ppgtt_size = 48,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 5c17257f3f44b..bea9f92e2264c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -174,7 +174,6 @@ enum intel_ppgtt_type {
>   func(has_hti); \
>   func(has_modular_fia); \
>   func(has_overlay); \
> - func(has_psr_hw_tracking); \
>   func(overlay_needs_physical); \
>   func(supports_tv);
>  
> -- 
> 2.36.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH 10/12] drm/i915: Drop has_psr from device info

[Matt Roper]

On Wed, May 04, 2022 at 12:07:54PM -0700, José Roberto de Souza wrote:
> No need to have this parameter in intel_device_info struct
> as all platforms with display version 9 or newer has this feature.
> 
> Signed-off-by: José Roberto de Souza 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 2 +-
>  drivers/gpu/drm/i915/i915_pci.c  | 3 ---
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  3 files changed, 1 insertion(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6b8a4e6649d9b..d8fa1d09cc828 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1303,7 +1303,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> IS_BROADWELL(dev_priv))
>  #define HAS_DP_MST(dev_priv)  (HAS_DDI(dev_priv))
>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
> (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
> -#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
> +#define HAS_PSR(dev_priv) (DISPLAY_VER(dev_priv) >= 9)
>  #define HAS_PSR_HW_TRACKING(dev_priv) \
>   (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
>  #define HAS_PSR2_SEL_FETCH(dev_priv)  (DISPLAY_VER(dev_priv) >= 12)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d8b5e972109f9..098d47cc47b44 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -631,7 +631,6 @@ static const struct intel_device_info chv_info = {
>   GEN9_DEFAULT_PAGE_SIZES, \
>   .display.has_dmc = 1, \
>   .display.has_hdcp = 1, \
> - .display.has_psr = 1, \
>   .display.has_psr_hw_tracking = 1, \
>   .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
>   .dbuf.slice_mask = BIT(DBUF_S1)
> @@ -680,7 +679,6 @@ static const struct intel_device_info skl_gt4_info = {
>   .display.has_fpga_dbg = 1, \
>   .display.fbc_mask = BIT(INTEL_FBC_A), \
>   .display.has_hdcp = 1, \
> - .display.has_psr = 1, \
>   .display.has_psr_hw_tracking = 1, \
>   .has_runtime_pm = 1, \
>   .display.has_dmc = 1, \
> @@ -928,7 +926,6 @@ static const struct intel_device_info adl_s_info = {
>   .display.has_fpga_dbg = 1,  
> \
>   .display.has_hdcp = 1,  
> \
>   .display.has_hotplug = 1,   
> \
> - .display.has_psr = 1,   
> \
>   .display.ver = 13,  
> \
>   .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | 
> BIT(PIPE_D), \
>   .pipe_offsets = {   
> \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index c4e85976d8948..5c17257f3f44b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -174,7 +174,6 @@ enum intel_ppgtt_type {
>   func(has_hti); \
>   func(has_modular_fia); \
>   func(has_overlay); \
> - func(has_psr); \
>   func(has_psr_hw_tracking); \
>   func(overlay_needs_physical); \
>   func(supports_tv);
> -- 
> 2.36.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH 09/12] drm/i915: Drop has_dp_mst from device info

[Matt Roper]

On Wed, May 04, 2022 at 12:07:53PM -0700, José Roberto de Souza wrote:
> No need to have this parameter in intel_device_info struct
> as the requirement to support it is the DDI support.
> 
> Signed-off-by: José Roberto de Souza 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 2 +-
>  drivers/gpu/drm/i915/i915_pci.c  | 3 ---
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  3 files changed, 1 insertion(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a354815445238..6b8a4e6649d9b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1295,13 +1295,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  
>  #define HAS_IPS(dev_priv)(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
>  
> -#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
>  #define HAS_DP20(dev_priv)   (IS_DG2(dev_priv))
>  
>  #define HAS_CDCLK_CRAWL(dev_priv) 
> (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
>  #define HAS_DDI(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || \
> IS_HASWELL(dev_priv) || \
> IS_BROADWELL(dev_priv))
> +#define HAS_DP_MST(dev_priv)  (HAS_DDI(dev_priv))
>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
> (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>  #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
>  #define HAS_PSR_HW_TRACKING(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 96270c0ddf06c..d8b5e972109f9 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -534,7 +534,6 @@ static const struct intel_device_info vlv_info = {
>   .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
>   BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
>   .display.has_fpga_dbg = 1, \
> - .display.has_dp_mst = 1, \
>   HSW_PIPE_OFFSETS, \
>   .has_runtime_pm = 1
>  
> @@ -686,7 +685,6 @@ static const struct intel_device_info skl_gt4_info = {
>   .has_runtime_pm = 1, \
>   .display.has_dmc = 1, \
>   .has_rps = true, \
> - .display.has_dp_mst = 1, \
>   .has_logical_ring_contexts = 1, \
>   .dma_mask_size = 39, \
>   .ppgtt_type = INTEL_PPGTT_FULL, \
> @@ -925,7 +923,6 @@ static const struct intel_device_info adl_s_info = {
>   .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | 
> \
>   BIT(DBUF_S4),   
> \
>   .display.has_dmc = 1,   
> \
> - .display.has_dp_mst = 1,
> \
>   .display.has_dsc = 1,   
> \
>   .display.fbc_mask = BIT(INTEL_FBC_A),   
> \
>   .display.has_fpga_dbg = 1,  
> \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index d809d44098c63..c4e85976d8948 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -166,7 +166,6 @@ enum intel_ppgtt_type {
>   func(cursor_needs_physical); \
>   func(has_cdclk_crawl); \
>   func(has_dmc); \
> - func(has_dp_mst); \
>   func(has_dsc); \
>   func(has_fpga_dbg); \
>   func(has_gmch); \
> -- 
> 2.36.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH] i915/guc/reset: Make __guc_reset_context aware of guilty engines

[Teres Alexis, Alan Previn]

Thanks Umesh for clarifying that question. With that, here is my rvb and 
apologies for the tardiness.

Reviewed-by: Alan Previn 


On Mon, 2022-05-02 at 13:07 -0700, Umesh Nerlige Ramappa wrote:
> On Thu, Apr 28, 2022 at 09:13:57AM -0700, Teres Alexis, Alan Previn wrote:
> > At a high level, this change looks good and simple.
> > However, inside __guc_reset_context, i think there might be
> > an observed change in behavior for parallel submission.
> > (or perhaps this change is part the intent?):
> > 
> > Unless my understanding is incorrect, assuming a
> > parallel submission comes in with virtual engines that
> > repeat the same kinds of workloads across multiple
> > physical engines (which i assume would be the typical
> > end-user usage of this UAPI feature), we would end up
> > marking the parent content (and other children contexts
> > that use the same engine) as guilty but not children
> > contexts that are running on a different engine.
> > I'm not sure if this would be an expected UAPI response
> > for parallel submission. (i.e. one or more children
> > get a re-run on other engines? I havent checked if
> > the replay is revoked later if the parent's or sibling's
> > 'request' was reset and marked as -EIO ... this marking
> > of req->force_error as -EIO or -EAGAIN is part of the
> > call to __i915_request_reset where the guilty param
> > value sees this change i am referring to).
> > 
> > Is this intended / expected?
> 
> Expectation: For virtual engine, only the virtual context must be marked 
> guilty. For parallel engines, parent/child contexts must be marked as 
> guilty.
> 
> Looking into the code, I see the expected behavior is already taken care 
> of.
> 
> For virtual engines, only one context is created with a mask of engines 
> that can be used by GuC. This context is registered with GuC and the 
> workloads are run on any one of these engines. When a reset occurs, the 
> G2H notification points to this context. When the __guc_reset_context 
> executes, it will only mark this context as guilty.
> 
> fwiu, for parallel submission, if N engines can run in parallel, then N 
> contexts are submitted. If there are no siblings, then there is only one 
> parent and the below reset logic works fine because G2H has only the 
> parent context.
> 
> If there are more than 1 siblings in parallel submission, then the 
> execution between siblings is just treated like virtual engines where 
> the parent has the mask of engines used. In this case, G2H points to 
> parent context and parent has a mask of all sibling engines, so this 
> works as expected too (in __guc_reset_context).
> 
> Thanks,
> Umesh
> 
> > ...alan
> > 
> > 
> > On Mon, 2022-04-25 at 17:30 -0700, Umesh Nerlige Ramappa wrote:
> > > There are 2 ways an engine can get reset in i915 and the method of reset
> > > affects how KMD labels a context as guilty/innocent.
> > > 
> > > (1) GuC initiated engine-reset: GuC resets a hung engine and notifies
> > > KMD. The context that hung on the engine is marked guilty and all other
> > > contexts are innocent. The innocent contexts are resubmitted.
> > > 
> > > (2) GT based reset: When an engine heartbeat fails to tick, KMD
> > > initiates a gt/chip reset. All active contexts are marked as guilty and
> > > discarded.
> > > 
> > > In order to correctly mark the contexts as guilty/innocent, pass a mask
> > > of engines that were reset to __guc_reset_context.
> > > 
> > > Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC 
> > > interface")
> > > Signed-off-by: Umesh Nerlige Ramappa 
> > > ---
> > >  drivers/gpu/drm/i915/gt/intel_reset.c|  2 +-
> > >  drivers/gpu/drm/i915/gt/uc/intel_guc.h   |  2 +-
> > >  .../gpu/drm/i915/gt/uc/intel_guc_submission.c| 16 
> > >  drivers/gpu/drm/i915/gt/uc/intel_uc.c|  2 +-
> > >  drivers/gpu/drm/i915/gt/uc/intel_uc.h|  2 +-
> > >  5 files changed, 12 insertions(+), 12 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
> > > b/drivers/gpu/drm/i915/gt/intel_reset.c
> > > index 5422a3b84bd4..a5338c3fde7a 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > > @@ -808,7 +808,7 @@ static int gt_reset(struct intel_gt *gt, 
> > > intel_engine_mask_t stalled_mask)
> > >   __intel_engine_reset(engine, stalled_mask & engine->mask);
> > >   local_bh_enable();
> > > 
> > > - intel_uc_reset(>->uc, true);
> > > + intel_uc_reset(>->uc, ALL_ENGINES);
> > > 
> > >   intel_ggtt_restore_fences(gt->ggtt);
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
> > > b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > > index 3f3373f68123..966e69a8b1c1 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> > > @@ -443,7 +443,7 @@ int intel_guc_global_policies_update(struct 

Re: [Intel-gfx] [PATCH 08/12] drm/i915: Drop has_ddi from device info

[Matt Roper]

On Wed, May 04, 2022 at 12:07:52PM -0700, José Roberto de Souza wrote:
> No need to have this parameter in intel_device_info struct
> as all platforms with display version 9 or newer, haswell or broadwell
> supports it.
> 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 4 +++-
>  drivers/gpu/drm/i915/i915_pci.c  | 3 ---
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  3 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f23e5c5cbf82b..a354815445238 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1299,7 +1299,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define HAS_DP20(dev_priv)   (IS_DG2(dev_priv))
>  
>  #define HAS_CDCLK_CRAWL(dev_priv) 
> (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
> -#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
> +#define HAS_DDI(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || \
> +   IS_HASWELL(dev_priv) || \
> +   IS_BROADWELL(dev_priv))

Technically the order of broadwell and haswell should be reversed here
(if we're going from newest to oldest).  Aside from that,

Reviewed-by: Matt Roper 

>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
> (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>  #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
>  #define HAS_PSR_HW_TRACKING(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 25aa8f5957f1e..96270c0ddf06c 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -533,7 +533,6 @@ static const struct intel_device_info vlv_info = {
>   .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 
> \
>   .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
>   BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
> - .display.has_ddi = 1, \
>   .display.has_fpga_dbg = 1, \
>   .display.has_dp_mst = 1, \
>   HSW_PIPE_OFFSETS, \
> @@ -679,7 +678,6 @@ static const struct intel_device_info skl_gt4_info = {
>   BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
>   BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
>   .has_64bit_reloc = 1, \
> - .display.has_ddi = 1, \
>   .display.has_fpga_dbg = 1, \
>   .display.fbc_mask = BIT(INTEL_FBC_A), \
>   .display.has_hdcp = 1, \
> @@ -926,7 +924,6 @@ static const struct intel_device_info adl_s_info = {
>   .dbuf.size = 4096,  
> \
>   .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | 
> \
>   BIT(DBUF_S4),   
> \
> - .display.has_ddi = 1,   
> \
>   .display.has_dmc = 1,   
> \
>   .display.has_dp_mst = 1,
> \
>   .display.has_dsc = 1,   
> \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 7cf16b0315b54..d809d44098c63 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -166,7 +166,6 @@ enum intel_ppgtt_type {
>   func(cursor_needs_physical); \
>   func(has_cdclk_crawl); \
>   func(has_dmc); \
> - func(has_ddi); \
>   func(has_dp_mst); \
>   func(has_dsc); \
>   func(has_fpga_dbg); \
> -- 
> 2.36.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH 07/12] drm/i915: Drop has_logical_ring_elsq from device info

[Matt Roper]

On Wed, May 04, 2022 at 12:07:51PM -0700, José Roberto de Souza wrote:
> No need to have this parameter in intel_device_info struct
> as all platforms with graphics version 11 or newer has this feature.
> 
> Signed-off-by: José Roberto de Souza 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 3 +--
>  drivers/gpu/drm/i915/i915_pci.c  | 4 +---
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  3 files changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 602e056edd314..f23e5c5cbf82b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1247,8 +1247,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  
>  #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
>   (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
> -#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
> - (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
> +#define HAS_LOGICAL_RING_ELSQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11)
>  
>  #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
>  
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index b47f8b1ab9c6c..25aa8f5957f1e 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -804,8 +804,7 @@ static const struct intel_device_info cml_gt2_info = {
>   .dbuf.size = 2048, \
>   .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
>   .display.has_dsc = 1, \
> - .has_coherent_ggtt = false, \
> - .has_logical_ring_elsq = 1
> + .has_coherent_ggtt = false
>  
>  static const struct intel_device_info icl_info = {
>   GEN11_FEATURES,
> @@ -989,7 +988,6 @@ static const struct intel_device_info adl_p_info = {
>   .has_global_mocs = 1, \
>   .has_llc = 1, \
>   .has_logical_ring_contexts = 1, \
> - .has_logical_ring_elsq = 1, \
>   .has_mslices = 1, \
>   .has_rps = 1, \
>   .has_runtime_pm = 1, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 62c9616ea6a9c..7cf16b0315b54 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -151,7 +151,6 @@ enum intel_ppgtt_type {
>   func(has_l3_dpf); \
>   func(has_llc); \
>   func(has_logical_ring_contexts); \
> - func(has_logical_ring_elsq); \
>   func(has_mslices); \
>   func(has_pooled_eu); \
>   func(has_pxp); \
> -- 
> 2.36.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] [PATCH v2 4/4] drm/i915/huc: Don't fail the probe if HuC init fails

[Daniele Ceraolo Spurio]

The previous patch introduced new failure cases in the HuC init flow
that can be hit by simply changing the config, so we want to avoid
failing the probe in those scenarios. HuC load failure is already
considered a non-fatal error and we have a way to report to userspace
if the HuC is not available via a dedicated getparam, so no changes
in expectation there.
The error message in the HuC init code has also been lowered to info to
avoid throwing error message for an expected behavior.

Signed-off-by: Daniele Ceraolo Spurio 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/gt/uc/intel_huc.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c  | 11 ++-
 2 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index c36e2bf9b0f29..3bb8838e325a4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -113,7 +113,7 @@ int intel_huc_init(struct intel_huc *huc)
return 0;
 
 out:
-   i915_probe_error(i915, "failed with %d\n", err);
+   drm_info(&i915->drm, "HuC init failed with %d\n", err);
return err;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 0dce94f896a8c..ecf149c5fdb02 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -323,17 +323,10 @@ static int __uc_init(struct intel_uc *uc)
if (ret)
return ret;
 
-   if (intel_uc_uses_huc(uc)) {
-   ret = intel_huc_init(huc);
-   if (ret)
-   goto out_guc;
-   }
+   if (intel_uc_uses_huc(uc))
+   intel_huc_init(huc);
 
return 0;
-
-out_guc:
-   intel_guc_fini(guc);
-   return ret;
 }
 
 static void __uc_fini(struct intel_uc *uc)
-- 
2.25.1

[Intel-gfx] [PATCH v2 2/4] drm/i915/huc: Add fetch support for gsc-loaded HuC binary

[Daniele Ceraolo Spurio]

On newer platforms (starting DG2 G10 B-step and G11 A-step), ownership of
HuC loading has been moved from the GuC to the GSC. As part of the
change, the header format of the HuC binary has been updated and does not
match the GuC anymore. The GSC will perform all the required checks on
the binary size, so we only need to check that the version matches.

Note that since we still haven't added any gsc-loaded FWs, the
loaded_via_gsc variable will always be kept to its initialization value
of zero.

v2: Add a note about loaded_via_gsc being zero (Alan)

Signed-off-by: Daniele Ceraolo Spurio 
Reviewed-by: Alan Previn 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 99 
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h |  2 +
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h |  9 ++
 3 files changed, 72 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d078f884b5e32..9361532726d6c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -301,45 +301,31 @@ static void __force_fw_fetch_failures(struct intel_uc_fw 
*uc_fw, int e)
}
 }
 
-/**
- * intel_uc_fw_fetch - fetch uC firmware
- * @uc_fw: uC firmware
- *
- * Fetch uC firmware into GEM obj.
- *
- * Return: 0 on success, a negative errno code on failure.
- */
-int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
+static int check_gsc_manifest(const struct firmware *fw,
+ struct intel_uc_fw *uc_fw)
 {
-   struct drm_i915_private *i915 = __uc_fw_to_gt(uc_fw)->i915;
-   struct device *dev = i915->drm.dev;
-   struct drm_i915_gem_object *obj;
-   const struct firmware *fw = NULL;
-   struct uc_css_header *css;
-   size_t size;
-   int err;
+   u32 *dw = (u32 *)fw->data;
+   u32 version = dw[HUC_GSC_VERSION_DW];
 
-   GEM_BUG_ON(!i915->wopcm.size);
-   GEM_BUG_ON(!intel_uc_fw_is_enabled(uc_fw));
-
-   err = i915_inject_probe_error(i915, -ENXIO);
-   if (err)
-   goto fail;
+   uc_fw->major_ver_found = FIELD_GET(HUC_GSC_MAJOR_VER_MASK, version);
+   uc_fw->minor_ver_found = FIELD_GET(HUC_GSC_MINOR_VER_MASK, version);
 
-   __force_fw_fetch_failures(uc_fw, -EINVAL);
-   __force_fw_fetch_failures(uc_fw, -ESTALE);
+   return 0;
+}
 
-   err = request_firmware(&fw, uc_fw->path, dev);
-   if (err)
-   goto fail;
+static int check_ccs_header(struct drm_i915_private *i915,
+   const struct firmware *fw,
+   struct intel_uc_fw *uc_fw)
+{
+   struct uc_css_header *css;
+   size_t size;
 
/* Check the size of the blob before examining buffer contents */
if (unlikely(fw->size < sizeof(struct uc_css_header))) {
drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu < 
%zu\n",
 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
 fw->size, sizeof(struct uc_css_header));
-   err = -ENODATA;
-   goto fail;
+   return -ENODATA;
}
 
css = (struct uc_css_header *)fw->data;
@@ -352,8 +338,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
 "%s firmware %s: unexpected header size: %zu != %zu\n",
 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
 fw->size, sizeof(struct uc_css_header));
-   err = -EPROTO;
-   goto fail;
+   return -EPROTO;
}
 
/* uCode size must calculated from other sizes */
@@ -368,8 +353,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu < 
%zu\n",
 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
 fw->size, size);
-   err = -ENOEXEC;
-   goto fail;
+   return -ENOEXEC;
}
 
/* Sanity check whether this fw is not larger than whole WOPCM memory */
@@ -378,8 +362,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu > 
%zu\n",
 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
 size, (size_t)i915->wopcm.size);
-   err = -E2BIG;
-   goto fail;
+   return -E2BIG;
}
 
/* Get version numbers from the CSS header */
@@ -388,6 +371,49 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_UC_MINOR,
   css->sw_version);
 
+   if (uc_fw->type == INTEL_UC_FW_TYPE_GUC)
+   uc_fw->private_data_size = css->private_data_size;
+
+   return 0;
+}
+
+/**
+ * intel_uc_fw_fetch - fetch uC firmware
+ * @uc_fw: uC firmware
+ *
+ * Fetch uC firmware into 

[Intel-gfx] [PATCH v2 3/4] drm/i915/huc: Prepare for GSC-loaded HuC

[Daniele Ceraolo Spurio]

HuC loading via GSC is performed via a PXP command sent through the mei
modules, so we need both MEI_GSC and MEI_PXP to be available. Given that
the GSC will do both the transfer and the authentication, the legacy HuC
loading paths can be safely skipped.
Also note that the GSC-loaded HuC survives GT reset.

v2: move the huc_is_authenticated() function to this patch.

Signed-off-by: Daniele Ceraolo Spurio 
Reviewed-by: Alan Previn  #v1
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_huc.c | 95 ++
 drivers/gpu/drm/i915/gt/uc/intel_huc.h |  6 ++
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c  |  5 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c  | 11 ++-
 5 files changed, 100 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index 66027a42cda9e..2516705b9f365 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -96,6 +96,7 @@
 
 #define GUC_SHIM_CONTROL2  _MMIO(0xc068)
 #define   GUC_IS_PRIVILEGED(1<<29)
+#define   GSC_LOADS_HUC(1<<30)
 
 #define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
 #define   GUC_SEND_TRIGGER   (1<<0)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 7b759b99cf3c8..c36e2bf9b0f29 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -6,6 +6,7 @@
 #include 
 
 #include "gt/intel_gt.h"
+#include "intel_guc_reg.h"
 #include "intel_huc.h"
 #include "i915_drv.h"
 
@@ -17,11 +18,15 @@
  * capabilities by adding HuC specific commands to batch buffers.
  *
  * The kernel driver is only responsible for loading the HuC firmware and
- * triggering its security authentication, which is performed by the GuC. For
- * The GuC to correctly perform the authentication, the HuC binary must be
- * loaded before the GuC one. Loading the HuC is optional; however, not using
- * the HuC might negatively impact power usage and/or performance of media
- * workloads, depending on the use-cases.
+ * triggering its security authentication, which is performed by the GuC on
+ * older platforms and by the GSC on newer ones. For the GuC to correctly
+ * perform the authentication, the HuC binary must be loaded before the GuC 
one.
+ * Loading the HuC is optional; however, not using the HuC might negatively
+ * impact power usage and/or performance of media workloads, depending on the
+ * use-cases.
+ * HuC must be reloaded on events that cause the WOPCM to lose its contents
+ * (S3/S4, FLR); GuC-authenticated HuC must also be reloaded on GuC/GT reset,
+ * while GSC-managed HuC will survive that.
  *
  * See https://github.com/intel/media-driver for the latest details on HuC
  * functionality.
@@ -54,11 +59,51 @@ void intel_huc_init_early(struct intel_huc *huc)
}
 }
 
+#define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy")
+static int check_huc_loading_mode(struct intel_huc *huc)
+{
+   struct intel_gt *gt = huc_to_gt(huc);
+   bool fw_needs_gsc = intel_huc_is_loaded_by_gsc(huc);
+   bool hw_uses_gsc = false;
+
+   /*
+* The fuse for HuC load via GSC is only valid on platforms that have
+* GuC deprivilege.
+*/
+   if (HAS_GUC_DEPRIVILEGE(gt->i915))
+   hw_uses_gsc = intel_uncore_read(gt->uncore, GUC_SHIM_CONTROL2) &
+ GSC_LOADS_HUC;
+
+   if (fw_needs_gsc != hw_uses_gsc) {
+   drm_err(>->i915->drm,
+   "mismatch between HuC FW (%s) and HW (%s) load modes\n",
+   HUC_LOAD_MODE_STRING(fw_needs_gsc),
+   HUC_LOAD_MODE_STRING(hw_uses_gsc));
+   return -ENOEXEC;
+   }
+
+   /* make sure we can access the GSC via the mei driver if we need it */
+   if (!(IS_ENABLED(CONFIG_INTEL_MEI_PXP) && 
IS_ENABLED(CONFIG_INTEL_MEI_GSC)) &&
+   fw_needs_gsc) {
+   drm_info(>->i915->drm,
+"Can't load HuC due to missing MEI modules\n");
+   return -EIO;
+   }
+
+   drm_dbg(>->i915->drm, "GSC loads huc=%s\n", str_yes_no(fw_needs_gsc));
+
+   return 0;
+}
+
 int intel_huc_init(struct intel_huc *huc)
 {
struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
int err;
 
+   err = check_huc_loading_mode(huc);
+   if (err)
+   goto out;
+
err = intel_uc_fw_init(&huc->fw);
if (err)
goto out;
@@ -96,17 +141,20 @@ int intel_huc_auth(struct intel_huc *huc)
struct intel_guc *guc = >->uc.guc;
int ret;
 
-   GEM_BUG_ON(intel_uc_fw_is_running(&huc->fw));
-
if (!intel_uc_fw_is_loaded(&huc->fw))
return -ENOEXEC;
 
+   /* GSC will do the auth */
+   if (intel_huc_is_loaded_by_gsc(huc))
+   return -ENODEV;
+
ret = i

[Intel-gfx] [PATCH v2 1/4] drm/i915/huc: drop intel_huc_is_authenticated

[Daniele Ceraolo Spurio]

The fuction name is confusing, because it doesn't check the actual auth
status in HW but the SW status. Given that there is only one user (the
huc_auth function itself), just get rid of it and use the FW status
checker directly.

Signed-off-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc.h | 5 -
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 556829de9c172..7b759b99cf3c8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -96,7 +96,7 @@ int intel_huc_auth(struct intel_huc *huc)
struct intel_guc *guc = >->uc.guc;
int ret;
 
-   GEM_BUG_ON(intel_huc_is_authenticated(huc));
+   GEM_BUG_ON(intel_uc_fw_is_running(&huc->fw));
 
if (!intel_uc_fw_is_loaded(&huc->fw))
return -ENOEXEC;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 73ec670800f2b..77d813840d76c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -50,11 +50,6 @@ static inline bool intel_huc_is_used(struct intel_huc *huc)
return intel_uc_fw_is_available(&huc->fw);
 }
 
-static inline bool intel_huc_is_authenticated(struct intel_huc *huc)
-{
-   return intel_uc_fw_is_running(&huc->fw);
-}
-
 void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p);
 
 #endif
-- 
2.25.1

[Intel-gfx] [PATCH v2 0/4] drm/i915: Prepare for GSC-loaded HuC

[Daniele Ceraolo Spurio]

On newer platforms (starting DG2 G10 B-step and G11 A-step), ownership of
HuC loading and authentication has been moved from the GuC to the GSC, with
both actions being performed via a single PXP command.
Given that the mei code has not fully landed yet (see [1]), we can't
implement the new load mechanism, but we can start getting ready for it
by taking care of the changes required for the existing code:

- The HuC header is now different from the GuC one. This also means that
  if the FW is for GSC-loading and the HW fuse is set to legacy load (or
  vice-versa) we can't load the HuC.

- To send a PXP message to the GSC we need both MEI_GSC and MEI_PXP.

- All legacy HuC loading paths can be skipped.

Note that the HuC fw version for DG2 is still not defined, so the HuC
code will be skipped until the define is added.

v2: drop changes in auth checking for legacy paths.

[1] https://patchwork.freedesktop.org/series/102339/

Cc: Alan Previn 
Cc: John Harrison 

Daniele Ceraolo Spurio (4):
  drm/i915/huc: drop intel_huc_is_authenticated
  drm/i915/huc: Add fetch support for gsc-loaded HuC binary
  drm/i915/huc: Prepare for GSC-loaded HuC
  drm/i915/huc: Don't fail the probe if HuC init fails

 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h   |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_huc.c   | 97 +++
 drivers/gpu/drm/i915/gt/uc/intel_huc.h   |  5 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c|  5 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c| 22 +++--
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 99 
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h |  2 +
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h |  9 ++
 8 files changed, 172 insertions(+), 68 deletions(-)

-- 
2.25.1

Re: [Intel-gfx] [PATCH 06/12] drm/i915: Drop has_reset_engine from device info

[Matt Roper]

On Wed, May 04, 2022 at 12:07:50PM -0700, José Roberto de Souza wrote:
> No need to have this parameter in intel_device_info struct
> as all platforms with graphics version 7 or newer can reset engines.
> 
> Signed-off-by: José Roberto de Souza 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/gt/intel_reset.c| 2 +-
>  drivers/gpu/drm/i915/i915_pci.c  | 5 -
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  3 files changed, 1 insertion(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 5422a3b84bd44..894f17f8b4cea 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -699,7 +699,7 @@ bool intel_has_reset_engine(const struct intel_gt *gt)
>   if (gt->i915->params.reset < 2)
>   return false;
>  
> - return INTEL_INFO(gt->i915)->has_reset_engine;
> + return GRAPHICS_VER(gt->i915) >= 7;
>  }
>  
>  int intel_reset_guc(struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 516f28d4db611..b47f8b1ab9c6c 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -454,7 +454,6 @@ static const struct intel_device_info snb_m_gt2_info = {
>   .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>   .has_coherent_ggtt = true, \
>   .has_llc = 1, \
> - .has_reset_engine = true, \
>   .has_rps = true, \
>   .dma_mask_size = 40, \
>   .ppgtt_type = INTEL_PPGTT_ALIASING, \
> @@ -512,7 +511,6 @@ static const struct intel_device_info vlv_info = {
>   .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
>   .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
>   .has_runtime_pm = 1,
> - .has_reset_engine = true,
>   .has_rps = true,
>   .display.has_gmch = 1,
>   .display.has_hotplug = 1,
> @@ -615,7 +613,6 @@ static const struct intel_device_info chv_info = {
>   .dma_mask_size = 39,
>   .ppgtt_type = INTEL_PPGTT_FULL,
>   .ppgtt_size = 32,
> - .has_reset_engine = 1,
>   .has_snoop = true,
>   .has_coherent_ggtt = false,
>   .display_mmio_offset = VLV_DISPLAY_BASE,
> @@ -696,7 +693,6 @@ static const struct intel_device_info skl_gt4_info = {
>   .dma_mask_size = 39, \
>   .ppgtt_type = INTEL_PPGTT_FULL, \
>   .ppgtt_size = 48, \
> - .has_reset_engine = 1, \
>   .has_snoop = true, \
>   .has_coherent_ggtt = false, \
>   HSW_PIPE_OFFSETS, \
> @@ -995,7 +991,6 @@ static const struct intel_device_info adl_p_info = {
>   .has_logical_ring_contexts = 1, \
>   .has_logical_ring_elsq = 1, \
>   .has_mslices = 1, \
> - .has_reset_engine = 1, \
>   .has_rps = 1, \
>   .has_runtime_pm = 1, \
>   .ppgtt_size = 48, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 599cb265946b8..62c9616ea6a9c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -142,7 +142,6 @@ enum intel_ppgtt_type {
>   func(has_64k_pages); \
>   func(needs_compact_pt); \
>   func(gpu_reset_clobbers_display); \
> - func(has_reset_engine); \
>   func(has_4tile); \
>   func(has_flat_ccs); \
>   func(has_global_mocs); \
> -- 
> 2.36.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH 05/12] drm/i915: Drop has_rc6p from device info

[Matt Roper]

On Wed, May 04, 2022 at 12:07:49PM -0700, José Roberto de Souza wrote:
> No need to have this parameter in intel_device_info struct
> as it was only supported in graphics version 6 and 7 not including
> haswell.
> 
> Signed-off-by: José Roberto de Souza 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 4 +++-
>  drivers/gpu/drm/i915/i915_pci.c  | 3 ---
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  3 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d29dca83185ac..602e056edd314 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1310,7 +1310,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  
>  /* ilk does support rc6, but we do not implement [power] contexts */
>  #define HAS_RC6(dev_priv) (GRAPHICS_VER(dev_priv) >= 6)
> -#define HAS_RC6p(dev_priv)(INTEL_INFO(dev_priv)->has_rc6p)
> +#define HAS_RC6p(dev_priv)(GRAPHICS_VER(dev_priv) >= 6 && \
> +   GRAPHICS_VER(dev_priv) <= 7 && \

BTW, I just remembered that we can write simple ranges like this (where
the release number doesn't matter) as:

IS_GRAPHICS_VER(i915, 6, 7)

so you might want to use that to simplify here and in some of the other
patches.

Otherwise,

Reviewed-by: Matt Roper 


> +   !IS_HASWELL(dev_priv))
>  #define HAS_RC6pp(dev_priv)   (false) /* HW was never validated */
>  
>  #define HAS_RPS(dev_priv)(INTEL_INFO(dev_priv)->has_rps)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 90584c462f225..516f28d4db611 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -405,7 +405,6 @@ static const struct intel_device_info ilk_m_info = {
>   .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>   .has_coherent_ggtt = true, \
>   .has_llc = 1, \
> - .has_rc6p = 1, \
>   .has_rps = true, \
>   .dma_mask_size = 40, \
>   .ppgtt_type = INTEL_PPGTT_ALIASING, \
> @@ -455,7 +454,6 @@ static const struct intel_device_info snb_m_gt2_info = {
>   .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>   .has_coherent_ggtt = true, \
>   .has_llc = 1, \
> - .has_rc6p = 1, \
>   .has_reset_engine = true, \
>   .has_rps = true, \
>   .dma_mask_size = 40, \
> @@ -540,7 +538,6 @@ static const struct intel_device_info vlv_info = {
>   .display.has_ddi = 1, \
>   .display.has_fpga_dbg = 1, \
>   .display.has_dp_mst = 1, \
> - .has_rc6p = 0 /* RC6p removed-by HSW */, \
>   HSW_PIPE_OFFSETS, \
>   .has_runtime_pm = 1
>  
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index b3244170c4638..599cb265946b8 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -156,7 +156,6 @@ enum intel_ppgtt_type {
>   func(has_mslices); \
>   func(has_pooled_eu); \
>   func(has_pxp); \
> - func(has_rc6p); \
>   func(has_rps); \
>   func(has_runtime_pm); \
>   func(has_snoop); \
> -- 
> 2.36.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for 
unexpected l3bank/mslice config
URL   : https://patchwork.freedesktop.org/series/103536/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11602_full -> Patchwork_103536v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103536v1_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_suspend@basic-s3@smem:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][1] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-dg1-13/igt@gem_exec_suspend@basic...@smem.html

  
Known issues


  Here are the changes found in Patchwork_103536v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][2], [PASS][3], [PASS][4], [PASS][5], 
[PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
[FAIL][49], [PASS][50]) ([i915#4392])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk9/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk9/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk9/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk8/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk8/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk8/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk7/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk7/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk6/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk6/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk6/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk5/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk5/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk4/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk4/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk4/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk3/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk3/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk2/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk2/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk2/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk1/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk1/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk9/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk9/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk9/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk8/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk8/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk8/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk7/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk7/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk6/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk6/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk6/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-ti

Re: [Intel-gfx] [PATCH 04/12] drm/i915: Drop has_rc6 from device info

[Matt Roper]

On Wed, May 04, 2022 at 12:07:48PM -0700, José Roberto de Souza wrote:
> No need to have this parameter in intel_device_info struct
> as all platforms with graphics version 6 or newer have software
> support for this feature.
> 
> Signed-off-by: José Roberto de Souza 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c  | 8 
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  3 files changed, 2 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3a3d57485b09c..d29dca83185ac 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1308,7 +1308,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define HAS_PSR2_SEL_FETCH(dev_priv)  (DISPLAY_VER(dev_priv) >= 12)
>  #define HAS_TRANSCODER(dev_priv, trans)   
> ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
>  
> -#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
> +/* ilk does support rc6, but we do not implement [power] contexts */
> +#define HAS_RC6(dev_priv) (GRAPHICS_VER(dev_priv) >= 6)
>  #define HAS_RC6p(dev_priv)(INTEL_INFO(dev_priv)->has_rc6p)
>  #define HAS_RC6pp(dev_priv)   (false) /* HW was never validated */
>  
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index df20818ce8eae..90584c462f225 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -376,8 +376,6 @@ static const struct intel_device_info gm45_info = {
>   .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
>   .has_snoop = true, \
>   .has_coherent_ggtt = true, \
> - /* ilk does support rc6, but we do not implement [power] contexts */ \
> - .has_rc6 = 0, \
>   .dma_mask_size = 36, \
>   I9XX_PIPE_OFFSETS, \
>   I9XX_CURSOR_OFFSETS, \
> @@ -407,7 +405,6 @@ static const struct intel_device_info ilk_m_info = {
>   .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>   .has_coherent_ggtt = true, \
>   .has_llc = 1, \
> - .has_rc6 = 1, \
>   .has_rc6p = 1, \
>   .has_rps = true, \
>   .dma_mask_size = 40, \
> @@ -458,7 +455,6 @@ static const struct intel_device_info snb_m_gt2_info = {
>   .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
>   .has_coherent_ggtt = true, \
>   .has_llc = 1, \
> - .has_rc6 = 1, \
>   .has_rc6p = 1, \
>   .has_reset_engine = true, \
>   .has_rps = true, \
> @@ -518,7 +514,6 @@ static const struct intel_device_info vlv_info = {
>   .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
>   .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
>   .has_runtime_pm = 1,
> - .has_rc6 = 1,
>   .has_reset_engine = true,
>   .has_rps = true,
>   .display.has_gmch = 1,
> @@ -617,7 +612,6 @@ static const struct intel_device_info chv_info = {
>   .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
>   .has_64bit_reloc = 1,
>   .has_runtime_pm = 1,
> - .has_rc6 = 1,
>   .has_rps = true,
>   .has_logical_ring_contexts = 1,
>   .display.has_gmch = 1,
> @@ -699,7 +693,6 @@ static const struct intel_device_info skl_gt4_info = {
>   .display.has_psr_hw_tracking = 1, \
>   .has_runtime_pm = 1, \
>   .display.has_dmc = 1, \
> - .has_rc6 = 1, \
>   .has_rps = true, \
>   .display.has_dp_mst = 1, \
>   .has_logical_ring_contexts = 1, \
> @@ -1005,7 +998,6 @@ static const struct intel_device_info adl_p_info = {
>   .has_logical_ring_contexts = 1, \
>   .has_logical_ring_elsq = 1, \
>   .has_mslices = 1, \
> - .has_rc6 = 1, \
>   .has_reset_engine = 1, \
>   .has_rps = 1, \
>   .has_runtime_pm = 1, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 6d2eafaab4ef0..b3244170c4638 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -156,7 +156,6 @@ enum intel_ppgtt_type {
>   func(has_mslices); \
>   func(has_pooled_eu); \
>   func(has_pxp); \
> - func(has_rc6); \
>   func(has_rc6p); \
>   func(has_rps); \
>   func(has_runtime_pm); \
> -- 
> 2.36.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH 03/12] drm/i915: Drop has_gt_uc from device info

[Matt Roper]

On Wed, May 04, 2022 at 12:07:47PM -0700, José Roberto de Souza wrote:
> No need to have this parameter in intel_device_info struct
> as all platforms with graphics version 9 or newer has graphics
> microcontroller.
> 
> Signed-off-by: José Roberto de Souza 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 2 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c| 2 +-
>  drivers/gpu/drm/i915/i915_pci.c  | 3 ---
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  4 files changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d23180d1b10cb..3a3d57485b09c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1357,7 +1357,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   */
>  #define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
>  
> -#define HAS_GT_UC(dev_priv)  (INTEL_INFO(dev_priv)->has_gt_uc)
> +#define HAS_GT_UC(dev_priv)  (GRAPHICS_VER(dev_priv) >= 9)
>  
>  #define HAS_POOLED_EU(dev_priv)  (INTEL_INFO(dev_priv)->has_pooled_eu)
>  
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 0512c66fa4f3f..5bd9cb8998527 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -2008,7 +2008,7 @@ __i915_gpu_coredump(struct intel_gt *gt, 
> intel_engine_mask_t engine_mask, u32 du
>   return ERR_PTR(-ENOMEM);
>   }
>  
> - if (INTEL_INFO(i915)->has_gt_uc) {
> + if (HAS_GT_UC(i915)) {
>   error->gt->uc = gt_record_uc(error->gt, compress);
>   if (error->gt->uc) {
>   if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index fc3e7c8bc69d1..df20818ce8eae 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -644,7 +644,6 @@ static const struct intel_device_info chv_info = {
>   GEN(9), \
>   GEN9_DEFAULT_PAGE_SIZES, \
>   .display.has_dmc = 1, \
> - .has_gt_uc = 1, \
>   .display.has_hdcp = 1, \
>   .display.has_psr = 1, \
>   .display.has_psr_hw_tracking = 1, \
> @@ -704,7 +703,6 @@ static const struct intel_device_info skl_gt4_info = {
>   .has_rps = true, \
>   .display.has_dp_mst = 1, \
>   .has_logical_ring_contexts = 1, \
> - .has_gt_uc = 1, \
>   .dma_mask_size = 39, \
>   .ppgtt_type = INTEL_PPGTT_FULL, \
>   .ppgtt_size = 48, \
> @@ -1003,7 +1001,6 @@ static const struct intel_device_info adl_p_info = {
>   .has_64bit_reloc = 1, \
>   .has_flat_ccs = 1, \
>   .has_global_mocs = 1, \
> - .has_gt_uc = 1, \
>   .has_llc = 1, \
>   .has_logical_ring_contexts = 1, \
>   .has_logical_ring_elsq = 1, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index d16515cea22fd..6d2eafaab4ef0 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -146,7 +146,6 @@ enum intel_ppgtt_type {
>   func(has_4tile); \
>   func(has_flat_ccs); \
>   func(has_global_mocs); \
> - func(has_gt_uc); \
>   func(has_heci_pxp); \
>   func(has_heci_gscfi); \
>   func(has_guc_deprivilege); \
> -- 
> 2.36.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH 01/12] drm/i915: Drop IPC from display 13 and newer

[Matt Roper]

On Wed, May 04, 2022 at 12:07:45PM -0700, José Roberto de Souza wrote:
> This feature is supported from display 9 to display 12 and was
> incorrectly being applied to DG2 and Alderlake-P.
> 
> While at is also taking the oportunity to drop it from
> intel_device_info struct as a display check is more simple
> and less prone to be left enabled in future platforms.
> 
> BSpec: 50039
> Signed-off-by: José Roberto de Souza 

Reviewed-by: Matt Roper 

> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c  | 3 ---
>  drivers/gpu/drm/i915/intel_device_info.h | 1 -
>  3 files changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2dddc27a1b0ed..695b35cd6b5e4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1344,7 +1344,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   */
>  #define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
>  
> -#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
> +#define HAS_IPC(dev_priv) (DISPLAY_VER(dev_priv) >= 9 && \
> +   DISPLAY_VER(dev_priv) <= 12)
>  
>  #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
>  #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 498708b33924f..c4f9c805cffd1 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -646,7 +646,6 @@ static const struct intel_device_info chv_info = {
>   .display.has_dmc = 1, \
>   .has_gt_uc = 1, \
>   .display.has_hdcp = 1, \
> - .display.has_ipc = 1, \
>   .display.has_psr = 1, \
>   .display.has_psr_hw_tracking = 1, \
>   .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
> @@ -712,7 +711,6 @@ static const struct intel_device_info skl_gt4_info = {
>   .has_reset_engine = 1, \
>   .has_snoop = true, \
>   .has_coherent_ggtt = false, \
> - .display.has_ipc = 1, \
>   HSW_PIPE_OFFSETS, \
>   IVB_CURSOR_OFFSETS, \
>   IVB_COLORS, \
> @@ -955,7 +953,6 @@ static const struct intel_device_info adl_s_info = {
>   .display.has_fpga_dbg = 1,  
> \
>   .display.has_hdcp = 1,  
> \
>   .display.has_hotplug = 1,   
> \
> - .display.has_ipc = 1,   
> \
>   .display.has_psr = 1,   
> \
>   .display.ver = 13,  
> \
>   .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | 
> BIT(PIPE_D), \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index e7d2cf7d65c85..c9660b4282d9e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -180,7 +180,6 @@ enum intel_ppgtt_type {
>   func(has_hdcp); \
>   func(has_hotplug); \
>   func(has_hti); \
> - func(has_ipc); \
>   func(has_modular_fia); \
>   func(has_overlay); \
>   func(has_psr); \
> -- 
> 2.36.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2

[Anusha Srivatsa]

Add Support for DC states on Dg2.

v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)

Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Rodrigo Vivi (v1)
---
 drivers/gpu/drm/i915/display/intel_display_power.c |  4 +++-
 drivers/gpu/drm/i915/display/intel_dmc.c   | 10 +-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1d9bd5808849..15b15f434fcf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -907,7 +907,9 @@ static u32 get_allowed_dc_mask(const struct 
drm_i915_private *dev_priv,
if (!HAS_DISPLAY(dev_priv))
return 0;
 
-   if (IS_DG1(dev_priv))
+   if (IS_DG2(dev_priv))
+   max_dc = 0;
+   else if (IS_DG1(dev_priv))
max_dc = 3;
else if (DISPLAY_VER(dev_priv) >= 12)
max_dc = 4;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c 
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 257cf662f9f4..2f01aca4d981 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -52,6 +52,10 @@
 
 #define DISPLAY_VER12_DMC_MAX_FW_SIZE  ICL_DMC_MAX_FW_SIZE
 
+#define DG2_DMC_PATH   DMC_PATH(dg2, 2, 06)
+#define DG2_DMC_VERSION_REQUIRED   DMC_VERSION(2, 06)
+MODULE_FIRMWARE(DG2_DMC_PATH);
+
 #define ADLP_DMC_PATH  DMC_PATH(adlp, 2, 16)
 #define ADLP_DMC_VERSION_REQUIRED  DMC_VERSION(2, 16)
 MODULE_FIRMWARE(ADLP_DMC_PATH);
@@ -688,7 +692,11 @@ void intel_dmc_ucode_init(struct drm_i915_private 
*dev_priv)
 */
intel_dmc_runtime_pm_get(dev_priv);
 
-   if (IS_ALDERLAKE_P(dev_priv)) {
+   if (IS_DG2(dev_priv)) {
+   dmc->fw_path = DG2_DMC_PATH;
+   dmc->required_version = DG2_DMC_VERSION_REQUIRED;
+   dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
+   } else if (IS_ALDERLAKE_P(dev_priv)) {
dmc->fw_path = ADLP_DMC_PATH;
dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
-- 
2.25.1

[Intel-gfx] [PATCH 0/1] DG2 DMC Support

[Anusha Srivatsa]

While DG2 supports DC5 and DC9, some of the tests in
fast-feedback blew up DG2 when the tests forced transition
from dc5->dc9 on suspend and dc9->dc5 on resume. Some local
experiments performed with Rodrigo on a RIL system  showed promising
results when dc5 was completely diabled and i915 took only dc9 paths.

Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue

Cc: Rodrigo Vivi 
Cc: Imre Deak 

Anusha Srivatsa (1):
  drm/i915/dmc: Load DMC on DG2

 drivers/gpu/drm/i915/display/intel_display_power.c |  4 +++-
 drivers/gpu/drm/i915/display/intel_dmc.c   | 10 +-
 2 files changed, 12 insertions(+), 2 deletions(-)

-- 
2.25.1

Re: [Intel-gfx] [PATCH] drm/i915: warn about missing ->get_buf_trans initialization

[Jani Nikula]

On Wed, 04 May 2022, "Murthy, Arun R"  wrote:
>> -Original Message-
>> From: Intel-gfx  On Behalf Of Jani
>> Nikula
>> Sent: Tuesday, May 3, 2022 1:52 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani 
>> Subject: [Intel-gfx] [PATCH] drm/i915: warn about missing ->get_buf_trans
>> initialization
>> 
>> Make sure each DDI platform has sane ->get_buf_trans initialized.
>> 
>> Suggested-by: Matt Roper 
>> Cc: Matt Roper 
>> Signed-off-by: Jani Nikula 
>> ---
>
> Reviewed-by: Arun R Murthy 

Thanks for the review, pushed to drm-intel-next.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 12/12] drm/i915: Drop supports_tv from device info

[José Roberto de Souza]

Only four platforms ever support this feature so we can elimitate
this from device info and use platform checks instead.

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h  | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c  | 4 
 drivers/gpu/drm/i915/intel_device_info.h | 3 +--
 3 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d866287c663a2..3c5980d174f81 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1286,7 +1286,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
  */
 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
 !(IS_I915G(dev_priv) || 
IS_I915GM(dev_priv)))
-#define SUPPORTS_TV(dev_priv)  
(INTEL_INFO(dev_priv)->display.supports_tv)
+#define SUPPORTS_TV(dev_priv)  (IS_I915GM(dev_priv) || 
IS_I945GM(dev_priv) || \
+IS_I965GM(dev_priv) || 
IS_GM45(dev_priv))
 #define I915_HAS_HOTPLUG(dev_priv) 
(INTEL_INFO(dev_priv)->display.has_hotplug)
 
 #define HAS_FW_BLC(dev_priv)   (DISPLAY_VER(dev_priv) > 2)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c6e99305e24d0..184a1eb6e2fce 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -259,7 +259,6 @@ static const struct intel_device_info i915gm_info = {
.display.cursor_needs_physical = 1,
.display.has_overlay = 1,
.display.overlay_needs_physical = 1,
-   .display.supports_tv = 1,
.display.fbc_mask = BIT(INTEL_FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
@@ -284,7 +283,6 @@ static const struct intel_device_info i945gm_info = {
.display.cursor_needs_physical = 1,
.display.has_overlay = 1,
.display.overlay_needs_physical = 1,
-   .display.supports_tv = 1,
.display.fbc_mask = BIT(INTEL_FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
@@ -346,7 +344,6 @@ static const struct intel_device_info i965gm_info = {
.is_mobile = 1,
.display.fbc_mask = BIT(INTEL_FBC_A),
.display.has_overlay = 1,
-   .display.supports_tv = 1,
.hws_needs_physical = 1,
.has_snoop = false,
 };
@@ -363,7 +360,6 @@ static const struct intel_device_info gm45_info = {
PLATFORM(INTEL_GM45),
.is_mobile = 1,
.display.fbc_mask = BIT(INTEL_FBC_A),
-   .display.supports_tv = 1,
.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
.gpu_reset_clobbers_display = false,
 };
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index bea9f92e2264c..a1d111fc83346 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -174,8 +174,7 @@ enum intel_ppgtt_type {
func(has_hti); \
func(has_modular_fia); \
func(has_overlay); \
-   func(overlay_needs_physical); \
-   func(supports_tv);
+   func(overlay_needs_physical);
 
 struct ip_version {
u8 ver;
-- 
2.36.0

[Intel-gfx] [PATCH 09/12] drm/i915: Drop has_dp_mst from device info

[José Roberto de Souza]

No need to have this parameter in intel_device_info struct
as the requirement to support it is the DDI support.

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h  | 2 +-
 drivers/gpu/drm/i915/i915_pci.c  | 3 ---
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a354815445238..6b8a4e6649d9b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1295,13 +1295,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_IPS(dev_priv)  (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
 
-#define HAS_DP_MST(dev_priv)   (INTEL_INFO(dev_priv)->display.has_dp_mst)
 #define HAS_DP20(dev_priv) (IS_DG2(dev_priv))
 
 #define HAS_CDCLK_CRAWL(dev_priv)   
(INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
 #define HAS_DDI(dev_priv)   (DISPLAY_VER(dev_priv) >= 9 || \
  IS_HASWELL(dev_priv) || \
  IS_BROADWELL(dev_priv))
+#define HAS_DP_MST(dev_priv)(HAS_DDI(dev_priv))
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
(INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)   (INTEL_INFO(dev_priv)->display.has_psr)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 96270c0ddf06c..d8b5e972109f9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -534,7 +534,6 @@ static const struct intel_device_info vlv_info = {
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
.display.has_fpga_dbg = 1, \
-   .display.has_dp_mst = 1, \
HSW_PIPE_OFFSETS, \
.has_runtime_pm = 1
 
@@ -686,7 +685,6 @@ static const struct intel_device_info skl_gt4_info = {
.has_runtime_pm = 1, \
.display.has_dmc = 1, \
.has_rps = true, \
-   .display.has_dp_mst = 1, \
.has_logical_ring_contexts = 1, \
.dma_mask_size = 39, \
.ppgtt_type = INTEL_PPGTT_FULL, \
@@ -925,7 +923,6 @@ static const struct intel_device_info adl_s_info = {
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | 
\
BIT(DBUF_S4),   
\
.display.has_dmc = 1,   
\
-   .display.has_dp_mst = 1,
\
.display.has_dsc = 1,   
\
.display.fbc_mask = BIT(INTEL_FBC_A),   
\
.display.has_fpga_dbg = 1,  
\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index d809d44098c63..c4e85976d8948 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -166,7 +166,6 @@ enum intel_ppgtt_type {
func(cursor_needs_physical); \
func(has_cdclk_crawl); \
func(has_dmc); \
-   func(has_dp_mst); \
func(has_dsc); \
func(has_fpga_dbg); \
func(has_gmch); \
-- 
2.36.0

[Intel-gfx] [PATCH 11/12] drm/i915: Drop has_psr_hw_tracking from device info

[José Roberto de Souza]

No need to have this parameter in intel_device_info struct
as this feature was only supported by display 9, display 11, tigerlake
and DG1, no newer platform will have this feature.

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h  | 6 --
 drivers/gpu/drm/i915/i915_pci.c  | 5 -
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d8fa1d09cc828..d866287c663a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1304,8 +1304,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DP_MST(dev_priv)(HAS_DDI(dev_priv))
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
(INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)   (DISPLAY_VER(dev_priv) >= 9)
-#define HAS_PSR_HW_TRACKING(dev_priv) \
-   (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
+#define HAS_PSR_HW_TRACKING(dev_priv)   ((DISPLAY_VER(dev_priv) >= 9 && \
+  DISPLAY_VER(dev_priv) <= 11) || \
+ IS_TIGERLAKE(dev_priv) || \
+ IS_DG1(dev_priv))
 #define HAS_PSR2_SEL_FETCH(dev_priv)(DISPLAY_VER(dev_priv) >= 12)
 #define HAS_TRANSCODER(dev_priv, trans) 
((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 098d47cc47b44..c6e99305e24d0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -631,7 +631,6 @@ static const struct intel_device_info chv_info = {
GEN9_DEFAULT_PAGE_SIZES, \
.display.has_dmc = 1, \
.display.has_hdcp = 1, \
-   .display.has_psr_hw_tracking = 1, \
.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
.dbuf.slice_mask = BIT(DBUF_S1)
 
@@ -679,7 +678,6 @@ static const struct intel_device_info skl_gt4_info = {
.display.has_fpga_dbg = 1, \
.display.fbc_mask = BIT(INTEL_FBC_A), \
.display.has_hdcp = 1, \
-   .display.has_psr_hw_tracking = 1, \
.has_runtime_pm = 1, \
.display.has_dmc = 1, \
.has_rps = true, \
@@ -865,7 +863,6 @@ static const struct intel_device_info rkl_info = {
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
BIT(TRANSCODER_C),
.display.has_hti = 1,
-   .display.has_psr_hw_tracking = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 };
@@ -897,7 +894,6 @@ static const struct intel_device_info adl_s_info = {
PLATFORM(INTEL_ALDERLAKE_S),
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | 
BIT(PIPE_D),
.display.has_hti = 1,
-   .display.has_psr_hw_tracking = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.dma_mask_size = 39,
@@ -955,7 +951,6 @@ static const struct intel_device_info adl_p_info = {
   BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
.display.has_cdclk_crawl = 1,
.display.has_modular_fia = 1,
-   .display.has_psr_hw_tracking = 0,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.ppgtt_size = 48,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 5c17257f3f44b..bea9f92e2264c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -174,7 +174,6 @@ enum intel_ppgtt_type {
func(has_hti); \
func(has_modular_fia); \
func(has_overlay); \
-   func(has_psr_hw_tracking); \
func(overlay_needs_physical); \
func(supports_tv);
 
-- 
2.36.0

[Intel-gfx] [PATCH 10/12] drm/i915: Drop has_psr from device info

[José Roberto de Souza]

No need to have this parameter in intel_device_info struct
as all platforms with display version 9 or newer has this feature.

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h  | 2 +-
 drivers/gpu/drm/i915/i915_pci.c  | 3 ---
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6b8a4e6649d9b..d8fa1d09cc828 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1303,7 +1303,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
  IS_BROADWELL(dev_priv))
 #define HAS_DP_MST(dev_priv)(HAS_DDI(dev_priv))
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
(INTEL_INFO(dev_priv)->display.has_fpga_dbg)
-#define HAS_PSR(dev_priv)   (INTEL_INFO(dev_priv)->display.has_psr)
+#define HAS_PSR(dev_priv)   (DISPLAY_VER(dev_priv) >= 9)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(dev_priv)(DISPLAY_VER(dev_priv) >= 12)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d8b5e972109f9..098d47cc47b44 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -631,7 +631,6 @@ static const struct intel_device_info chv_info = {
GEN9_DEFAULT_PAGE_SIZES, \
.display.has_dmc = 1, \
.display.has_hdcp = 1, \
-   .display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
.dbuf.slice_mask = BIT(DBUF_S1)
@@ -680,7 +679,6 @@ static const struct intel_device_info skl_gt4_info = {
.display.has_fpga_dbg = 1, \
.display.fbc_mask = BIT(INTEL_FBC_A), \
.display.has_hdcp = 1, \
-   .display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
.has_runtime_pm = 1, \
.display.has_dmc = 1, \
@@ -928,7 +926,6 @@ static const struct intel_device_info adl_s_info = {
.display.has_fpga_dbg = 1,  
\
.display.has_hdcp = 1,  
\
.display.has_hotplug = 1,   
\
-   .display.has_psr = 1,   
\
.display.ver = 13,  
\
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | 
BIT(PIPE_D), \
.pipe_offsets = {   
\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index c4e85976d8948..5c17257f3f44b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -174,7 +174,6 @@ enum intel_ppgtt_type {
func(has_hti); \
func(has_modular_fia); \
func(has_overlay); \
-   func(has_psr); \
func(has_psr_hw_tracking); \
func(overlay_needs_physical); \
func(supports_tv);
-- 
2.36.0

[Intel-gfx] [PATCH 07/12] drm/i915: Drop has_logical_ring_elsq from device info

[José Roberto de Souza]

No need to have this parameter in intel_device_info struct
as all platforms with graphics version 11 or newer has this feature.

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h  | 3 +--
 drivers/gpu/drm/i915/i915_pci.c  | 4 +---
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 602e056edd314..f23e5c5cbf82b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1247,8 +1247,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
-#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
-   (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
+#define HAS_LOGICAL_RING_ELSQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b47f8b1ab9c6c..25aa8f5957f1e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -804,8 +804,7 @@ static const struct intel_device_info cml_gt2_info = {
.dbuf.size = 2048, \
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
.display.has_dsc = 1, \
-   .has_coherent_ggtt = false, \
-   .has_logical_ring_elsq = 1
+   .has_coherent_ggtt = false
 
 static const struct intel_device_info icl_info = {
GEN11_FEATURES,
@@ -989,7 +988,6 @@ static const struct intel_device_info adl_p_info = {
.has_global_mocs = 1, \
.has_llc = 1, \
.has_logical_ring_contexts = 1, \
-   .has_logical_ring_elsq = 1, \
.has_mslices = 1, \
.has_rps = 1, \
.has_runtime_pm = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 62c9616ea6a9c..7cf16b0315b54 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -151,7 +151,6 @@ enum intel_ppgtt_type {
func(has_l3_dpf); \
func(has_llc); \
func(has_logical_ring_contexts); \
-   func(has_logical_ring_elsq); \
func(has_mslices); \
func(has_pooled_eu); \
func(has_pxp); \
-- 
2.36.0

[Intel-gfx] [PATCH 08/12] drm/i915: Drop has_ddi from device info

[José Roberto de Souza]

No need to have this parameter in intel_device_info struct
as all platforms with display version 9 or newer, haswell or broadwell
supports it.

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h  | 4 +++-
 drivers/gpu/drm/i915/i915_pci.c  | 3 ---
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f23e5c5cbf82b..a354815445238 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1299,7 +1299,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DP20(dev_priv) (IS_DG2(dev_priv))
 
 #define HAS_CDCLK_CRAWL(dev_priv)   
(INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
-#define HAS_DDI(dev_priv)   (INTEL_INFO(dev_priv)->display.has_ddi)
+#define HAS_DDI(dev_priv)   (DISPLAY_VER(dev_priv) >= 9 || \
+ IS_HASWELL(dev_priv) || \
+ IS_BROADWELL(dev_priv))
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
(INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)   (INTEL_INFO(dev_priv)->display.has_psr)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 25aa8f5957f1e..96270c0ddf06c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -533,7 +533,6 @@ static const struct intel_device_info vlv_info = {
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), 
\
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
-   .display.has_ddi = 1, \
.display.has_fpga_dbg = 1, \
.display.has_dp_mst = 1, \
HSW_PIPE_OFFSETS, \
@@ -679,7 +678,6 @@ static const struct intel_device_info skl_gt4_info = {
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
.has_64bit_reloc = 1, \
-   .display.has_ddi = 1, \
.display.has_fpga_dbg = 1, \
.display.fbc_mask = BIT(INTEL_FBC_A), \
.display.has_hdcp = 1, \
@@ -926,7 +924,6 @@ static const struct intel_device_info adl_s_info = {
.dbuf.size = 4096,  
\
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | 
\
BIT(DBUF_S4),   
\
-   .display.has_ddi = 1,   
\
.display.has_dmc = 1,   
\
.display.has_dp_mst = 1,
\
.display.has_dsc = 1,   
\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 7cf16b0315b54..d809d44098c63 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -166,7 +166,6 @@ enum intel_ppgtt_type {
func(cursor_needs_physical); \
func(has_cdclk_crawl); \
func(has_dmc); \
-   func(has_ddi); \
func(has_dp_mst); \
func(has_dsc); \
func(has_fpga_dbg); \
-- 
2.36.0

[Intel-gfx] [PATCH 06/12] drm/i915: Drop has_reset_engine from device info

[José Roberto de Souza]

No need to have this parameter in intel_device_info struct
as all platforms with graphics version 7 or newer can reset engines.

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/gt/intel_reset.c| 2 +-
 drivers/gpu/drm/i915/i915_pci.c  | 5 -
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 5422a3b84bd44..894f17f8b4cea 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -699,7 +699,7 @@ bool intel_has_reset_engine(const struct intel_gt *gt)
if (gt->i915->params.reset < 2)
return false;
 
-   return INTEL_INFO(gt->i915)->has_reset_engine;
+   return GRAPHICS_VER(gt->i915) >= 7;
 }
 
 int intel_reset_guc(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 516f28d4db611..b47f8b1ab9c6c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -454,7 +454,6 @@ static const struct intel_device_info snb_m_gt2_info = {
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_coherent_ggtt = true, \
.has_llc = 1, \
-   .has_reset_engine = true, \
.has_rps = true, \
.dma_mask_size = 40, \
.ppgtt_type = INTEL_PPGTT_ALIASING, \
@@ -512,7 +511,6 @@ static const struct intel_device_info vlv_info = {
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
.has_runtime_pm = 1,
-   .has_reset_engine = true,
.has_rps = true,
.display.has_gmch = 1,
.display.has_hotplug = 1,
@@ -615,7 +613,6 @@ static const struct intel_device_info chv_info = {
.dma_mask_size = 39,
.ppgtt_type = INTEL_PPGTT_FULL,
.ppgtt_size = 32,
-   .has_reset_engine = 1,
.has_snoop = true,
.has_coherent_ggtt = false,
.display_mmio_offset = VLV_DISPLAY_BASE,
@@ -696,7 +693,6 @@ static const struct intel_device_info skl_gt4_info = {
.dma_mask_size = 39, \
.ppgtt_type = INTEL_PPGTT_FULL, \
.ppgtt_size = 48, \
-   .has_reset_engine = 1, \
.has_snoop = true, \
.has_coherent_ggtt = false, \
HSW_PIPE_OFFSETS, \
@@ -995,7 +991,6 @@ static const struct intel_device_info adl_p_info = {
.has_logical_ring_contexts = 1, \
.has_logical_ring_elsq = 1, \
.has_mslices = 1, \
-   .has_reset_engine = 1, \
.has_rps = 1, \
.has_runtime_pm = 1, \
.ppgtt_size = 48, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 599cb265946b8..62c9616ea6a9c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -142,7 +142,6 @@ enum intel_ppgtt_type {
func(has_64k_pages); \
func(needs_compact_pt); \
func(gpu_reset_clobbers_display); \
-   func(has_reset_engine); \
func(has_4tile); \
func(has_flat_ccs); \
func(has_global_mocs); \
-- 
2.36.0

[Intel-gfx] [PATCH 04/12] drm/i915: Drop has_rc6 from device info

[José Roberto de Souza]

No need to have this parameter in intel_device_info struct
as all platforms with graphics version 6 or newer have software
support for this feature.

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h  | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c  | 8 
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3a3d57485b09c..d29dca83185ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1308,7 +1308,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_PSR2_SEL_FETCH(dev_priv)(DISPLAY_VER(dev_priv) >= 12)
 #define HAS_TRANSCODER(dev_priv, trans) 
((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
 
-#define HAS_RC6(dev_priv)   (INTEL_INFO(dev_priv)->has_rc6)
+/* ilk does support rc6, but we do not implement [power] contexts */
+#define HAS_RC6(dev_priv)   (GRAPHICS_VER(dev_priv) >= 6)
 #define HAS_RC6p(dev_priv)  (INTEL_INFO(dev_priv)->has_rc6p)
 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index df20818ce8eae..90584c462f225 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -376,8 +376,6 @@ static const struct intel_device_info gm45_info = {
.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
.has_snoop = true, \
.has_coherent_ggtt = true, \
-   /* ilk does support rc6, but we do not implement [power] contexts */ \
-   .has_rc6 = 0, \
.dma_mask_size = 36, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
@@ -407,7 +405,6 @@ static const struct intel_device_info ilk_m_info = {
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_coherent_ggtt = true, \
.has_llc = 1, \
-   .has_rc6 = 1, \
.has_rc6p = 1, \
.has_rps = true, \
.dma_mask_size = 40, \
@@ -458,7 +455,6 @@ static const struct intel_device_info snb_m_gt2_info = {
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_coherent_ggtt = true, \
.has_llc = 1, \
-   .has_rc6 = 1, \
.has_rc6p = 1, \
.has_reset_engine = true, \
.has_rps = true, \
@@ -518,7 +514,6 @@ static const struct intel_device_info vlv_info = {
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
.has_runtime_pm = 1,
-   .has_rc6 = 1,
.has_reset_engine = true,
.has_rps = true,
.display.has_gmch = 1,
@@ -617,7 +612,6 @@ static const struct intel_device_info chv_info = {
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
.has_64bit_reloc = 1,
.has_runtime_pm = 1,
-   .has_rc6 = 1,
.has_rps = true,
.has_logical_ring_contexts = 1,
.display.has_gmch = 1,
@@ -699,7 +693,6 @@ static const struct intel_device_info skl_gt4_info = {
.display.has_psr_hw_tracking = 1, \
.has_runtime_pm = 1, \
.display.has_dmc = 1, \
-   .has_rc6 = 1, \
.has_rps = true, \
.display.has_dp_mst = 1, \
.has_logical_ring_contexts = 1, \
@@ -1005,7 +998,6 @@ static const struct intel_device_info adl_p_info = {
.has_logical_ring_contexts = 1, \
.has_logical_ring_elsq = 1, \
.has_mslices = 1, \
-   .has_rc6 = 1, \
.has_reset_engine = 1, \
.has_rps = 1, \
.has_runtime_pm = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 6d2eafaab4ef0..b3244170c4638 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -156,7 +156,6 @@ enum intel_ppgtt_type {
func(has_mslices); \
func(has_pooled_eu); \
func(has_pxp); \
-   func(has_rc6); \
func(has_rc6p); \
func(has_rps); \
func(has_runtime_pm); \
-- 
2.36.0

[Intel-gfx] [PATCH 05/12] drm/i915: Drop has_rc6p from device info

[José Roberto de Souza]

No need to have this parameter in intel_device_info struct
as it was only supported in graphics version 6 and 7 not including
haswell.

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h  | 4 +++-
 drivers/gpu/drm/i915/i915_pci.c  | 3 ---
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d29dca83185ac..602e056edd314 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1310,7 +1310,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /* ilk does support rc6, but we do not implement [power] contexts */
 #define HAS_RC6(dev_priv)   (GRAPHICS_VER(dev_priv) >= 6)
-#define HAS_RC6p(dev_priv)  (INTEL_INFO(dev_priv)->has_rc6p)
+#define HAS_RC6p(dev_priv)  (GRAPHICS_VER(dev_priv) >= 6 && \
+ GRAPHICS_VER(dev_priv) <= 7 && \
+ !IS_HASWELL(dev_priv))
 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
 
 #define HAS_RPS(dev_priv)  (INTEL_INFO(dev_priv)->has_rps)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 90584c462f225..516f28d4db611 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -405,7 +405,6 @@ static const struct intel_device_info ilk_m_info = {
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_coherent_ggtt = true, \
.has_llc = 1, \
-   .has_rc6p = 1, \
.has_rps = true, \
.dma_mask_size = 40, \
.ppgtt_type = INTEL_PPGTT_ALIASING, \
@@ -455,7 +454,6 @@ static const struct intel_device_info snb_m_gt2_info = {
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_coherent_ggtt = true, \
.has_llc = 1, \
-   .has_rc6p = 1, \
.has_reset_engine = true, \
.has_rps = true, \
.dma_mask_size = 40, \
@@ -540,7 +538,6 @@ static const struct intel_device_info vlv_info = {
.display.has_ddi = 1, \
.display.has_fpga_dbg = 1, \
.display.has_dp_mst = 1, \
-   .has_rc6p = 0 /* RC6p removed-by HSW */, \
HSW_PIPE_OFFSETS, \
.has_runtime_pm = 1
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index b3244170c4638..599cb265946b8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -156,7 +156,6 @@ enum intel_ppgtt_type {
func(has_mslices); \
func(has_pooled_eu); \
func(has_pxp); \
-   func(has_rc6p); \
func(has_rps); \
func(has_runtime_pm); \
func(has_snoop); \
-- 
2.36.0

[Intel-gfx] [PATCH 03/12] drm/i915: Drop has_gt_uc from device info

[José Roberto de Souza]

No need to have this parameter in intel_device_info struct
as all platforms with graphics version 9 or newer has graphics
microcontroller.

Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h  | 2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c| 2 +-
 drivers/gpu/drm/i915/i915_pci.c  | 3 ---
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 4 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d23180d1b10cb..3a3d57485b09c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1357,7 +1357,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
  */
 #define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
 
-#define HAS_GT_UC(dev_priv)(INTEL_INFO(dev_priv)->has_gt_uc)
+#define HAS_GT_UC(dev_priv)(GRAPHICS_VER(dev_priv) >= 9)
 
 #define HAS_POOLED_EU(dev_priv)(INTEL_INFO(dev_priv)->has_pooled_eu)
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0512c66fa4f3f..5bd9cb8998527 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -2008,7 +2008,7 @@ __i915_gpu_coredump(struct intel_gt *gt, 
intel_engine_mask_t engine_mask, u32 du
return ERR_PTR(-ENOMEM);
}
 
-   if (INTEL_INFO(i915)->has_gt_uc) {
+   if (HAS_GT_UC(i915)) {
error->gt->uc = gt_record_uc(error->gt, compress);
if (error->gt->uc) {
if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fc3e7c8bc69d1..df20818ce8eae 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -644,7 +644,6 @@ static const struct intel_device_info chv_info = {
GEN(9), \
GEN9_DEFAULT_PAGE_SIZES, \
.display.has_dmc = 1, \
-   .has_gt_uc = 1, \
.display.has_hdcp = 1, \
.display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
@@ -704,7 +703,6 @@ static const struct intel_device_info skl_gt4_info = {
.has_rps = true, \
.display.has_dp_mst = 1, \
.has_logical_ring_contexts = 1, \
-   .has_gt_uc = 1, \
.dma_mask_size = 39, \
.ppgtt_type = INTEL_PPGTT_FULL, \
.ppgtt_size = 48, \
@@ -1003,7 +1001,6 @@ static const struct intel_device_info adl_p_info = {
.has_64bit_reloc = 1, \
.has_flat_ccs = 1, \
.has_global_mocs = 1, \
-   .has_gt_uc = 1, \
.has_llc = 1, \
.has_logical_ring_contexts = 1, \
.has_logical_ring_elsq = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index d16515cea22fd..6d2eafaab4ef0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -146,7 +146,6 @@ enum intel_ppgtt_type {
func(has_4tile); \
func(has_flat_ccs); \
func(has_global_mocs); \
-   func(has_gt_uc); \
func(has_heci_pxp); \
func(has_heci_gscfi); \
func(has_guc_deprivilege); \
-- 
2.36.0

[Intel-gfx] [PATCH 02/12] drm/i915/display: Disable DSB for DG2 and Alderlake-P

[José Roberto de Souza]

Commit 99510e1afb48 ("drm/i915: Disable DSB usage for now") disabled
DSB for all display 12 platforms because it is not properly
programming gamma LUT but left display 13 platforms with it enabled
what I believe is not intentional.

kms_color@pipe-a-gamma test is still passing on TGL with DSB enabled
like reported in https://gitlab.freedesktop.org/drm/intel/-/issues/3916
and got the same behavior on Alderlake-P.

So here disabling DSB for all platforms and to avoid this mistake in
future platforms dropping the it from intel_device_info struct.

Fixes: 99510e1afb48 ("drm/i915: Disable DSB usage for now")
Cc: Ville Syrjälä 
Cc: Uma Shankar 
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h  | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c  | 4 +---
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 695b35cd6b5e4..d23180d1b10cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -937,7 +937,8 @@ static inline struct intel_gt *to_gt(struct 
drm_i915_private *i915)
 
 #define INTEL_REVID(dev_priv)  (to_pci_dev((dev_priv)->drm.dev)->revision)
 
-#define HAS_DSB(dev_priv)  (INTEL_INFO(dev_priv)->display.has_dsb)
+/* FIXME: LUT load is broken with DSB */
+#define HAS_DSB(dev_priv)  (DISPLAY_VER(i915) >= 12 && 0)
 
 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c4f9c805cffd1..fc3e7c8bc69d1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -870,8 +870,7 @@ static const struct intel_device_info jsl_info = {
}, \
TGL_CURSOR_OFFSETS, \
.has_global_mocs = 1, \
-   .has_pxp = 1, \
-   .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */
+   .has_pxp = 1
 
 static const struct intel_device_info tgl_info = {
GEN12_FEATURES,
@@ -947,7 +946,6 @@ static const struct intel_device_info adl_s_info = {
.display.has_ddi = 1,   
\
.display.has_dmc = 1,   
\
.display.has_dp_mst = 1,
\
-   .display.has_dsb = 1,   
\
.display.has_dsc = 1,   
\
.display.fbc_mask = BIT(INTEL_FBC_A),   
\
.display.has_fpga_dbg = 1,  
\
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index c9660b4282d9e..d16515cea22fd 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -173,7 +173,6 @@ enum intel_ppgtt_type {
func(has_dmc); \
func(has_ddi); \
func(has_dp_mst); \
-   func(has_dsb); \
func(has_dsc); \
func(has_fpga_dbg); \
func(has_gmch); \
-- 
2.36.0

[Intel-gfx] [PATCH 01/12] drm/i915: Drop IPC from display 13 and newer

[José Roberto de Souza]

This feature is supported from display 9 to display 12 and was
incorrectly being applied to DG2 and Alderlake-P.

While at is also taking the oportunity to drop it from
intel_device_info struct as a display check is more simple
and less prone to be left enabled in future platforms.

BSpec: 50039
Signed-off-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/i915_drv.h  | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c  | 3 ---
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 3 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2dddc27a1b0ed..695b35cd6b5e4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1344,7 +1344,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
  */
 #define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
 
-#define HAS_IPC(dev_priv)   (INTEL_INFO(dev_priv)->display.has_ipc)
+#define HAS_IPC(dev_priv)   (DISPLAY_VER(dev_priv) >= 9 && \
+ DISPLAY_VER(dev_priv) <= 12)
 
 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 498708b33924f..c4f9c805cffd1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -646,7 +646,6 @@ static const struct intel_device_info chv_info = {
.display.has_dmc = 1, \
.has_gt_uc = 1, \
.display.has_hdcp = 1, \
-   .display.has_ipc = 1, \
.display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
@@ -712,7 +711,6 @@ static const struct intel_device_info skl_gt4_info = {
.has_reset_engine = 1, \
.has_snoop = true, \
.has_coherent_ggtt = false, \
-   .display.has_ipc = 1, \
HSW_PIPE_OFFSETS, \
IVB_CURSOR_OFFSETS, \
IVB_COLORS, \
@@ -955,7 +953,6 @@ static const struct intel_device_info adl_s_info = {
.display.has_fpga_dbg = 1,  
\
.display.has_hdcp = 1,  
\
.display.has_hotplug = 1,   
\
-   .display.has_ipc = 1,   
\
.display.has_psr = 1,   
\
.display.ver = 13,  
\
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | 
BIT(PIPE_D), \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index e7d2cf7d65c85..c9660b4282d9e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -180,7 +180,6 @@ enum intel_ppgtt_type {
func(has_hdcp); \
func(has_hotplug); \
func(has_hti); \
-   func(has_ipc); \
func(has_modular_fia); \
func(has_overlay); \
func(has_psr); \
-- 
2.36.0

Re: [Intel-gfx] [PATCH] drm/i915/reset: Add Wa_22011802037 for gen11 and execlist backend

[Umesh Nerlige Ramappa]

On Wed, May 04, 2022 at 07:09:09PM +0100, Tvrtko Ursulin wrote:


On 04/05/2022 18:35, Umesh Nerlige Ramappa wrote:

On Wed, May 04, 2022 at 09:10:42AM +0100, Tvrtko Ursulin wrote:


On 03/05/2022 20:49, Umesh Nerlige Ramappa wrote:

On Tue, May 03, 2022 at 09:42:52AM +0100, Tvrtko Ursulin wrote:


On 02/05/2022 23:18, Umesh Nerlige Ramappa wrote:

Current implementation of Wa_22011802037 is limited to the GuC backend
and gen12. Add support for execlist backend and gen11 as well.


Is the implication f6aa0d713c88 ("drm/i915: Add Wa_22011802037 
force cs halt") does not work on Tigerlake? Fixes: tag 
probably required in that case since I have sold that fix as 
a, well, fix.


After the fix was made, the WA has evolved and added some more 
steps for handling pending MI_FORCE_WAKEs. This patch is the 
additional set of steps needed for the WA. As you mentioned 
offline, I should correct the commit message to indicate that 
the WA does exist for execlists, but needs additional steps. 
Will add Fixes: tag.


Ok, that would be good then since it does sound they need to be 
tied together (as in cherry picked for fixes).


Will it be followed up with preempt-to-idle implementation to 
avoid the, as I understand it, potential for activity on one CCS 
engine defeating the WA on another by timing out the wait for 
idle?


fwiu, for the case where we want to limit the reset to a single 
engine, the preempt-to-idle implementation may be required - 
https://patchwork.freedesktop.org/series/101432/. If preempt-to-idle 
fails, the hangcheck should kick in and then do a gt-reset. If that 
happens, then the WA flow in the patch should be applied.


Okay I read that as yes. That is fine by me since this patch alone is 
better than without it.



Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/gt/intel_engine.h    |  2 +
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 81 
++-

 .../drm/i915/gt/intel_execlists_submission.c  |  7 ++
 .../gpu/drm/i915/gt/intel_ring_submission.c   |  7 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc.c    |  4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 81 
++-

 6 files changed, 103 insertions(+), 79 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h 
b/drivers/gpu/drm/i915/gt/intel_engine.h

index 1431f1e9dbee..04e435bce79b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -201,6 +201,8 @@ int intel_ring_submission_setup(struct 
intel_engine_cs *engine);

 int intel_engine_stop_cs(struct intel_engine_cs *engine);
 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
+void intel_engine_wait_for_pending_mi_fw(struct 
intel_engine_cs *engine);

+
 void intel_engine_set_hwsp_writemask(struct intel_engine_cs 
*engine, u32 mask);
 u64 intel_engine_get_active_head(const struct 
intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c

index 14c6ddbbfde8..0bda665a407c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1282,10 +1282,10 @@ static int 
__intel_engine_stop_cs(struct intel_engine_cs *engine,
 intel_uncore_write_fw(uncore, mode, 
_MASKED_BIT_ENABLE(STOP_RING));

 /*
- * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is
+ * Wa_22011802037 : gen11, gen12, Prior to doing a 
reset, ensure CS is

  * stopped, set ring stop bit and prefetch disable bit to halt CS
  */
-    if (GRAPHICS_VER(engine->i915) == 12)
+    if (GRAPHICS_VER(engine->i915) == 11 || 
GRAPHICS_VER(engine->i915) == 12)


IS_GRAPHICS_VER(11, 12)

 intel_uncore_write_fw(uncore, 
RING_MODE_GEN7(engine->mmio_base),

_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
@@ -1308,6 +1308,14 @@ int intel_engine_stop_cs(struct 
intel_engine_cs *engine)

 return -ENODEV;
 ENGINE_TRACE(engine, "\n");
+    /*
+ * TODO: Occasionally trying to stop the cs times out, 
but does not


What is the TODO part? To figure out why is sometimes does not work?


+ * adversely affect functionality. The timeout is set as a config
+ * parameter that defaults to 100ms. Assuming that this 
timeout is
+ * sufficient for any pending MI_FORCEWAKEs to 
complete. Once root

+ * caused, the caller must check and handler the return from this


s/handler/handle/

TODO is to convert the function to return an error?


TODO: Find out why occasionally stopping the CS times out. Seen 
especially with gem_eio tests.


I will update the comment to be clear.


This timeout is in general or with this patch only?


In general. I only tried it on dg2, but I don't see any existing 
caller checking the return value of intel_engine_stop_cs.


Okay, then perhaps adding a comment in this patch added some 
confusion. Fine either way.





+ * function.
+ */
 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
 ENGINE_TRAC

[Intel-gfx] [PATCH 3/3] drm/i915/display: stop using BUG()

[Jani Nikula]

Avoid bringing the entire machine down even if there's a bug that
shouldn't happen, but won't corrupt the system either. Log them loudly
and limp on.

Cc: Tvrtko Ursulin 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_ddi.c  | 11 ++-
 drivers/gpu/drm/i915/display/intel_display.c  | 19 +++
 .../drm/i915/display/intel_display_types.h| 15 +--
 3 files changed, 26 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9e6fa59eabba..52cf6fb9994a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -455,6 +455,9 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder 
*encoder,
temp |= TRANS_DDI_SELECT_PORT(port);
 
switch (crtc_state->pipe_bpp) {
+   default:
+   MISSING_CASE(crtc_state->pipe_bpp);
+   fallthrough;
case 18:
temp |= TRANS_DDI_BPC_6;
break;
@@ -467,8 +470,6 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder 
*encoder,
case 36:
temp |= TRANS_DDI_BPC_12;
break;
-   default:
-   BUG();
}
 
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
@@ -478,6 +479,9 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder 
*encoder,
 
if (cpu_transcoder == TRANSCODER_EDP) {
switch (pipe) {
+   default:
+   MISSING_CASE(pipe);
+   fallthrough;
case PIPE_A:
/* On Haswell, can only use the always-on power well for
 * eDP when not using the panel fitter, and when not
@@ -494,9 +498,6 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder 
*encoder,
case PIPE_C:
temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
break;
-   default:
-   BUG();
-   break;
}
}
 
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 0decf3d24237..1a421dda36d7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -500,6 +500,9 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
i915_reg_t dpll_reg;
 
switch (dig_port->base.port) {
+   default:
+   MISSING_CASE(dig_port->base.port);
+   fallthrough;
case PORT_B:
port_mask = DPLL_PORTB_READY_MASK;
dpll_reg = DPLL(0);
@@ -513,8 +516,6 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
port_mask = DPLL_PORTD_READY_MASK;
dpll_reg = DPIO_PHY_STATUS;
break;
-   default:
-   BUG();
}
 
if (intel_de_wait_for_register(dev_priv, dpll_reg,
@@ -3157,6 +3158,10 @@ static void i9xx_set_pipeconf(const struct 
intel_crtc_state *crtc_state)
PIPECONF_DITHER_TYPE_SP;
 
switch (crtc_state->pipe_bpp) {
+   default:
+   /* Case prevented by intel_choose_pipe_bpp_dither. */
+   MISSING_CASE(crtc_state->pipe_bpp);
+   fallthrough;
case 18:
pipeconf |= PIPECONF_BPC_6;
break;
@@ -3166,9 +3171,6 @@ static void i9xx_set_pipeconf(const struct 
intel_crtc_state *crtc_state)
case 30:
pipeconf |= PIPECONF_BPC_10;
break;
-   default:
-   /* Case prevented by intel_choose_pipe_bpp_dither. */
-   BUG();
}
}
 
@@ -3464,6 +3466,10 @@ static void ilk_set_pipeconf(const struct 
intel_crtc_state *crtc_state)
val = 0;
 
switch (crtc_state->pipe_bpp) {
+   default:
+   /* Case prevented by intel_choose_pipe_bpp_dither. */
+   MISSING_CASE(crtc_state->pipe_bpp);
+   fallthrough;
case 18:
val |= PIPECONF_BPC_6;
break;
@@ -3476,9 +3482,6 @@ static void ilk_set_pipeconf(const struct 
intel_crtc_state *crtc_state)
case 36:
val |= PIPECONF_BPC_12;
break;
-   default:
-   /* Case prevented by intel_choose_pipe_bpp_dither. */
-   BUG();
}
 
if (crtc_state->dither)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 408152f9f46a..8b10ef5153f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1727,13 +1727,14 @@ static inline enum dpio_channel

[Intel-gfx] [PATCH 1/3] drm/i915: remove unused GEM_DEBUG_DECL() and GEM_DEBUG_BUG_ON()

[Jani Nikula]

There are already too many choices here, take away the unused ones.

Cc: Tvrtko Ursulin 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_gem.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index d0752e5553db..b7b257f54d2e 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -54,9 +54,7 @@ struct drm_i915_private;
} while(0)
 #define GEM_WARN_ON(expr) WARN_ON(expr)
 
-#define GEM_DEBUG_DECL(var) var
 #define GEM_DEBUG_EXEC(expr) expr
-#define GEM_DEBUG_BUG_ON(expr) GEM_BUG_ON(expr)
 #define GEM_DEBUG_WARN_ON(expr) GEM_WARN_ON(expr)
 
 #else
@@ -66,9 +64,7 @@ struct drm_i915_private;
 #define GEM_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
 #define GEM_WARN_ON(expr) ({ unlikely(!!(expr)); })
 
-#define GEM_DEBUG_DECL(var)
 #define GEM_DEBUG_EXEC(expr) do { } while (0)
-#define GEM_DEBUG_BUG_ON(expr)
 #define GEM_DEBUG_WARN_ON(expr) ({ BUILD_BUG_ON_INVALID(expr); 0; })
 #endif
 
-- 
2.30.2

[Intel-gfx] [PATCH 2/3] drm/i915: remove single-use GEM_DEBUG_EXEC()

[Jani Nikula]

Reduce the magic of what's going on in GEM_DEBUG_EXEC() by expanding it
inline and being explicit about it. It's as single use case anyway, so
the macro feels overkill.

Cc: Tvrtko Ursulin 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/gt/intel_ring.c | 3 ++-
 drivers/gpu/drm/i915/i915_gem.h  | 2 --
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c 
b/drivers/gpu/drm/i915/gt/intel_ring.c
index 40ffcb94e379..15ec64d881c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -299,7 +299,8 @@ u32 *intel_ring_begin(struct i915_request *rq, unsigned int 
num_dwords)
GEM_BUG_ON(ring->emit > ring->size - bytes);
GEM_BUG_ON(ring->space < bytes);
cs = ring->vaddr + ring->emit;
-   GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs)));
+   if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+   memset32(cs, POISON_INUSE, bytes / sizeof(*cs));
ring->emit += bytes;
ring->space -= bytes;
 
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index b7b257f54d2e..a2be323a4be5 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -54,7 +54,6 @@ struct drm_i915_private;
} while(0)
 #define GEM_WARN_ON(expr) WARN_ON(expr)
 
-#define GEM_DEBUG_EXEC(expr) expr
 #define GEM_DEBUG_WARN_ON(expr) GEM_WARN_ON(expr)
 
 #else
@@ -64,7 +63,6 @@ struct drm_i915_private;
 #define GEM_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
 #define GEM_WARN_ON(expr) ({ unlikely(!!(expr)); })
 
-#define GEM_DEBUG_EXEC(expr) do { } while (0)
 #define GEM_DEBUG_WARN_ON(expr) ({ BUILD_BUG_ON_INVALID(expr); 0; })
 #endif
 
-- 
2.30.2

[Intel-gfx] [PATCH] drm/i915/dmc: Add MMIO range restrictions

[Anusha Srivatsa]

Bspec has added some steps that check forDMC MMIO range before
programming them

v2: Fix for CI
v3: move register defines to .h (Anusha)
- Check MMIO restrictions per pipe
- Add MMIO restricton for v1 dmc header as well (Lucas)
v4: s/_PICK/_PICK_EVEN and use it only for Pipe DMC scenario.
- clean up sanity check logic.(Lucas)
- Add MMIO range for RKL as well.(Anusha)
v5: Use DISPLAY_VER instead of per platform check (Lucas)

BSpec: 49193

Cc: 
Cc: Lucas De Marchi 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/display/intel_dmc.c  | 42 +++
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 18 +++-
 2 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c 
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 257cf662f9f4..e7437ed2597e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -374,6 +374,43 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
}
 }
 
+static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, const u32 
*mmioaddr,
+  u32 mmio_count, int header_ver, u8 
dmc_id)
+{
+   struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+   u32 start_range, end_range;
+   int i;
+
+   if (dmc_id >= DMC_FW_MAX) {
+   drm_warn(&i915->drm, "Unsupported firmware id %u\n", dmc_id);
+   return false;
+   }
+
+   if (header_ver == 1) {
+   start_range = DMC_MMIO_START_RANGE;
+   end_range = DMC_MMIO_END_RANGE;
+   } else if (dmc_id == DMC_FW_MAIN) {
+   start_range = TGL_MAIN_MMIO_START;
+   end_range = TGL_MAIN_MMIO_END;
+   } else if (DISPLAY_VER(i915) >= 13) {
+   start_range = ADLP_PIPE_MMIO_START;
+   end_range = ADLP_PIPE_MMIO_END;
+   } else if (DISPLAY_VER(i915) >= 12) {
+   start_range = TGL_PIPE_MMIO_START(dmc_id);
+   end_range = TGL_PIPE_MMIO_END(dmc_id);
+   } else {
+   drm_warn(&i915->drm, "Unknown mmio range for sanity check");
+   return false;
+   }
+
+   for (i = 0; i < mmio_count; i++) {
+   if (mmioaddr[i] < start_range || mmioaddr[i] > end_range)
+   return false;
+   }
+
+   return true;
+}
+
 static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
   const struct intel_dmc_header_base *dmc_header,
   size_t rem_size, u8 dmc_id)
@@ -443,6 +480,11 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
return 0;
}
 
+   if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 
dmc_header->header_ver, dmc_id)) {
+   drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n");
+   return 0;
+   }
+
for (i = 0; i < mmio_count; i++) {
dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
dmc_info->mmiodata[i] = mmiodata[i];
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h 
b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index d65e698832eb..67e14eb96a7a 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -16,7 +16,23 @@
 #define DMC_LAST_WRITE _MMIO(0x8F034)
 #define DMC_LAST_WRITE_VALUE   0xc003b400
 #define DMC_MMIO_START_RANGE   0x8
-#define DMC_MMIO_END_RANGE 0x8
+#define DMC_MMIO_END_RANGE 0x8
+#define DMC_V1_MMIO_START_RANGE0x8
+#define TGL_MAIN_MMIO_START0x8F000
+#define TGL_MAIN_MMIO_END  0x8
+#define _TGL_PIPEA_MMIO_START  0x92000
+#define _TGL_PIPEA_MMIO_END0x93FFF
+#define _TGL_PIPEB_MMIO_START  0x96000
+#define _TGL_PIPEB_MMIO_END0x97FFF
+#define ADLP_PIPE_MMIO_START   0x5F000
+#define ADLP_PIPE_MMIO_END 0x5
+
+#define TGL_PIPE_MMIO_START(dmc_id)_PICK_EVEN(((dmc_id) - 1), 
_TGL_PIPEA_MMIO_START,\
+ _TGL_PIPEB_MMIO_START)
+
+#define TGL_PIPE_MMIO_END(dmc_id)  _PICK_EVEN(((dmc_id) - 1), 
_TGL_PIPEA_MMIO_END,\
+ _TGL_PIPEB_MMIO_END)
+
 #define SKL_DMC_DC3_DC5_COUNT  _MMIO(0x80030)
 #define SKL_DMC_DC5_DC6_COUNT  _MMIO(0x8002C)
 #define BXT_DMC_DC3_DC5_COUNT  _MMIO(0x80038)
-- 
2.25.1

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config

[Matt Roper]

On Wed, May 04, 2022 at 06:59:32PM +0100, Tvrtko Ursulin wrote:
> 
> On 04/05/2022 17:48, Matt Roper wrote:
> > On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin 
> > > 
> > > DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
> > > to exercise a certain code path, so in case of values coming from MMIO
> > > reads we cannot be sure CI will have all the possible SKUs and parts.
> > > 
> > > Use drm_warn instead and move logging to init phase while at it.
> > 
> > Changing to drm_warn looks good, although moving the location changes
> > the intent a bit; I think originally the idea was to warn if we were
> > trying to do a steering lookup for a type that we never initialized
> > (e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
> > read the register in the first place).  But I don't think we've ever
> > made a mistake that would cause us to trip the warning, so it probably
> > isn't terribly important to keep it there.
> 
> Ah I see.. there we could put something like:
> 
>   case MSLICE:
>   GEM_WARN_ON(!HAS_MSLICES(...));
> 

Yeah, that would work for MSLICE and LNCF.  Although L3BANK is a bit
stranger since we have multiple platforms that obtain the L3 bank mask
in completely different ways (Xe_HP reads it from XEHP_FUSE4, whereas
gen11/gen12 reads it from GEN10_MIRROR_FUSE3).  We want to make sure
there that no matter which branch of init we take, we didn't forget to
initialize l3bank_mask somehow.


Matt

> ?
> 
> Regards,
> 
> Tvrtko
> 
> > 
> > Reviewed-by: Matt Roper 
> > 
> > > 
> > > Signed-off-by: Tvrtko Ursulin 
> > > Cc: Matt Roper 
> > > Cc: Jani Nikula 
> > > ---
> > >   drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++---
> > >   1 file changed, 6 insertions(+), 7 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
> > > b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > index 53307ca0eed0..c474e5c3ea5e 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > >* An mslice is unavailable only if both the meml3 for the 
> > > slice is
> > >* disabled *and* all of the DSS in the slice (quadrant) are 
> > > disabled.
> > >*/
> > > - if (HAS_MSLICES(i915))
> > > + if (HAS_MSLICES(i915)) {
> > >   gt->info.mslice_mask =
> > >   slicemask(gt, GEN_DSS_PER_MSLICE) |
> > >   (intel_uncore_read(gt->uncore, 
> > > GEN10_MIRROR_FUSE3) &
> > >GEN12_MEML3_EN_MASK);
> > > + if (!gt->info.mslice_mask) /* should be impossible! */
> > > + drm_warn(&i915->drm, "mslice mask all zero!\n");
> > > + }
> > >   if (IS_DG2(i915)) {
> > >   gt->steering_table[MSLICE] = 
> > > xehpsdv_mslice_steering_table;
> > > @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > >   gt->info.l3bank_mask =
> > >   ~intel_uncore_read(gt->uncore, 
> > > GEN10_MIRROR_FUSE3) &
> > >   GEN10_L3BANK_MASK;
> > > + if (!gt->info.l3bank_mask) /* should be impossible! */
> > > + drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
> > >   } else if (HAS_MSLICES(i915)) {
> > >   MISSING_CASE(INTEL_INFO(i915)->platform);
> > >   }
> > > @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct 
> > > intel_gt *gt,
> > >   {
> > >   switch (type) {
> > >   case L3BANK:
> > > - GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be 
> > > impossible! */
> > > -
> > >   *sliceid = 0;   /* unused */
> > >   *subsliceid = __ffs(gt->info.l3bank_mask);
> > >   break;
> > >   case MSLICE:
> > > - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be 
> > > impossible! */
> > > -
> > >   *sliceid = __ffs(gt->info.mslice_mask);
> > >   *subsliceid = 0;/* unused */
> > >   break;
> > >   case LNCF:
> > > - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be 
> > > impossible! */
> > > -
> > >   /*
> > >* An LNCF is always present if its mslice is present, 
> > > so we
> > >* can safely just steer to LNCF 0 in all cases.
> > > -- 
> > > 2.32.0
> > > 
> > 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/fbdev: print error in case drm_fb_helper_initial_config fails

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/fbdev: print error in case 
drm_fb_helper_initial_config fails
URL   : https://patchwork.freedesktop.org/series/103533/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11601_full -> Patchwork_103533v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_103533v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_103533v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 13)
--

  Additional (3): shard-rkl shard-dg1 shard-tglu 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103533v1_full:

### CI changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * boot:
- {shard-rkl}:NOTRUN -> ([PASS][1], [FAIL][2], [PASS][3], 
[PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], 
[PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], 
[PASS][17], [PASS][18], [PASS][19])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-6/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-5/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-5/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-5/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-5/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-5/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-4/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-4/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-2/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-2/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-2/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-2/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-2/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-1/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-1/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-1/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-1/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-1/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-rkl-1/boot.html

  

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_parallel@userptr@bcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][20]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-skl5/igt@gem_exec_parallel@user...@bcs0.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][21] +1 similar issue
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-dg1-19/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-d.html

  * igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
- {shard-dg1}:NOTRUN -> [FAIL][22]
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v1/shard-dg1-12/igt@kms_plane_multi...@atomic-pipe-d-tiling-x.html

  
Known issues


  Here are the changes found in Patchwork_103533v1_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- shard-skl:  ([PASS][23], [PASS][24], [PASS][25], [PASS][26], 
[PASS][27], [PASS][28], [PASS][29], [FAIL][30], [PASS][31], [PASS][32], 
[PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], 
[PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], 
[PASS][45]) ([i915#5032]) -> ([PASS][46], [PASS][47], [PASS][48], [PASS][49], 
[PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], 
[PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], 
[PASS][62], [PASS][63])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11601/shard-skl9/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11601/shard-skl9/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11601/shard-sk

Re: [Intel-gfx] [PATCH] drm/i915: Change semantics of context isolation reporting to UM

[Matt Roper]

On Wed, May 04, 2022 at 06:42:37PM +0200, Daniel Vetter wrote:
> On Wed, May 04, 2022 at 07:59:27AM -0700, Matt Roper wrote:
> > On Wed, May 04, 2022 at 02:24:07PM +0200, Daniel Vetter wrote:
> > > On Fri, 29 Apr 2022 at 17:11, Adrian Larumbe
> > >  wrote:
> > > > I915_PARAM_HAS_CONTEXT_ISOLATION was already being used as a boolean by
> > > > both Iris and Vulkan , and stood for the guarantee that, when creating a
> > > > new context, all state set by it will not leak to any other context.
> > > >
> > > > However the actual return value was a bitmask where every bit stood for 
> > > > an
> > > > initialised engine, and IGT test gem_ctx_isolation makes use of this 
> > > > mask
> > > > for deciding on the actual context engine isolation status.
> > > >
> > > > However, we do not provide UAPI for IGT tests, so the value returned by 
> > > > the
> > > > PARAM ioctl has to reflect Mesa usage as a boolean.
> > > >
> > > > This change only made sense after compute engine support was added to 
> > > > the
> > > > driver in commit 944823c9463916dd53f3 ("drm/i915/xehp: Define compute 
> > > > class
> > > > and engine") because no context isolation can be assumed on any device 
> > > > with
> > > > both RCS annd CCS engines.
> > > >
> > > > Signed-off-by: Adrian Larumbe 
> > > 
> > > Top level post and adding Matt Roper and dri-devel.
> > > 
> > > This was meant as a simple cleanup after CCS enabling in upstream, but
> > > that CCS enabling seems to have gone wrong.
> > > 
> > > What I thought we should be done for CCS enabling is the following:
> > > - actually have some igt-side hardcoded assumption about how much
> > > engines are isolated from each another, which is a hw property. I
> > > think some of that landed, but it's very incomplete
> > > 
> > > - convert all igt tests over to that. At least gem_ctx_isolation.c is
> > > not converted over, as Adrian pointed out.
> > 
> > I pointed that out last week in one of our offline syncs and that's what
> > got the ball rolling on that test again.  But you specifically told us
> > that the uapi cleanup for context isolation shouldn't block the CCS
> > patches from landing since that was still happening in parallel:
> > 
> > "...I do see the uapi cleanup as part of this multi engine/CCS
> > enabling, but it's not a blocker to land the patches..."
> > 
> > Did we misunderstand what you were trying to say in that email or was
> > there a change of direction here?
> 
> The cleanup (which Adrian is now working on, but there's confusion) is
> totally fine to do later. What looks really iffy is the test coverage, and
> at least from me looking around gem_ctx_isolation wasn't touched or
> updated for CCS engines, and that looks like it's not enough. Either those
> tests are bogus or not actually testing a lot, and then we should delete
> them. Or there's probably going to be some impact on how much exactly the
> engines/contexts are isolated against each another.

The test automatically picks up any new engines that show up and
includes them in execution.  The test is already running properly on DG2
CCS engines in CI right now.  E.g.,


https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/re-dg2-12/igt@gem_ctx_isolation@dirty-cre...@ccs0.html

Is the concern just that we haven't added extra registers to the list to
check on the CCS engines?  For that matter, we're missing a bunch of
registers for RCS, BCS, VCS, and VECS for newer platforms too; the CCS
isn't really special there.

My understanding is that most of what gem_ctx_isolation tests is that
context switches really do save/restore registers properly (i.e., the
hardware behavior is sane) and there's really nothing special about CCS
engines regarding general context switching behavior.  Where things get
unusual with CCS engines is the shared reset domain, and that's more the
realm of what tests like i915_hangman cover.  But even there, the
workarounds that are in place right now (which only allow parallelism
between engines if they belong to the same VM) means that in most cases
there actually isn't any userspace-visible impact of the shared resets.

Adding JohnH and Umesh since they're a lot more familiar with all of
this stuff than I.

I can send a revert if you think that's what we need, but from what I'm
hearing we don't really expect many areas where there's
userspace-visible behavior from CCS engines that would need non-standard
IGT handling, and the few places where there are have already been
updated.  But there are so many orphaned IGT tests out there, many of
which have bitrotted away over the years, that it's possible we might
still be missing something.


Matt

> 
> That's the part that I think should be done before we call CCS support
> done and ready for merging. And if that's done properly it should also
> take care of the "igt uses HAS_CONTEXT_ISOLATION getparam" issue, since
> you need something more fancy anyway.
> -Daniel
> 
> 
> > 
> > 
> > Matt
> > 
> > > 
> > > - once igt stopped usi

Re: [Intel-gfx] [PATCH] drm/i915/reset: Add Wa_22011802037 for gen11 and execlist backend

[Tvrtko Ursulin]

On 04/05/2022 18:35, Umesh Nerlige Ramappa wrote:

On Wed, May 04, 2022 at 09:10:42AM +0100, Tvrtko Ursulin wrote:


On 03/05/2022 20:49, Umesh Nerlige Ramappa wrote:

On Tue, May 03, 2022 at 09:42:52AM +0100, Tvrtko Ursulin wrote:


On 02/05/2022 23:18, Umesh Nerlige Ramappa wrote:

Current implementation of Wa_22011802037 is limited to the GuC backend
and gen12. Add support for execlist backend and gen11 as well.


Is the implication f6aa0d713c88 ("drm/i915: Add Wa_22011802037 force 
cs halt") does not work on Tigerlake? Fixes: tag probably required 
in that case since I have sold that fix as a, well, fix.


After the fix was made, the WA has evolved and added some more steps 
for handling pending MI_FORCE_WAKEs. This patch is the additional set 
of steps needed for the WA. As you mentioned offline, I should 
correct the commit message to indicate that the WA does exist for 
execlists, but needs additional steps. Will add Fixes: tag.


Ok, that would be good then since it does sound they need to be tied 
together (as in cherry picked for fixes).


Will it be followed up with preempt-to-idle implementation to avoid 
the, as I understand it, potential for activity on one CCS engine 
defeating the WA on another by timing out the wait for idle?


fwiu, for the case where we want to limit the reset to a single engine, 
the preempt-to-idle implementation may be required - 
https://patchwork.freedesktop.org/series/101432/. If preempt-to-idle 
fails, the hangcheck should kick in and then do a gt-reset. If that 
happens, then the WA flow in the patch should be applied.


Okay I read that as yes. That is fine by me since this patch alone is 
better than without it.



Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/gt/intel_engine.h    |  2 +
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 81 
++-

 .../drm/i915/gt/intel_execlists_submission.c  |  7 ++
 .../gpu/drm/i915/gt/intel_ring_submission.c   |  7 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc.c    |  4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 81 
++-

 6 files changed, 103 insertions(+), 79 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h 
b/drivers/gpu/drm/i915/gt/intel_engine.h

index 1431f1e9dbee..04e435bce79b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -201,6 +201,8 @@ int intel_ring_submission_setup(struct 
intel_engine_cs *engine);

 int intel_engine_stop_cs(struct intel_engine_cs *engine);
 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
+void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs 
*engine);

+
 void intel_engine_set_hwsp_writemask(struct intel_engine_cs 
*engine, u32 mask);
 u64 intel_engine_get_active_head(const struct intel_engine_cs 
*engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c

index 14c6ddbbfde8..0bda665a407c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1282,10 +1282,10 @@ static int __intel_engine_stop_cs(struct 
intel_engine_cs *engine,
 intel_uncore_write_fw(uncore, mode, 
_MASKED_BIT_ENABLE(STOP_RING));

 /*
- * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is
+ * Wa_22011802037 : gen11, gen12, Prior to doing a reset, 
ensure CS is

  * stopped, set ring stop bit and prefetch disable bit to halt CS
  */
-    if (GRAPHICS_VER(engine->i915) == 12)
+    if (GRAPHICS_VER(engine->i915) == 11 || 
GRAPHICS_VER(engine->i915) == 12)


IS_GRAPHICS_VER(11, 12)

 intel_uncore_write_fw(uncore, 
RING_MODE_GEN7(engine->mmio_base),
   
_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
@@ -1308,6 +1308,14 @@ int intel_engine_stop_cs(struct 
intel_engine_cs *engine)

 return -ENODEV;
 ENGINE_TRACE(engine, "\n");
+    /*
+ * TODO: Occasionally trying to stop the cs times out, but 
does not


What is the TODO part? To figure out why is sometimes does not work?


+ * adversely affect functionality. The timeout is set as a config
+ * parameter that defaults to 100ms. Assuming that this 
timeout is
+ * sufficient for any pending MI_FORCEWAKEs to complete. Once 
root

+ * caused, the caller must check and handler the return from this


s/handler/handle/

TODO is to convert the function to return an error?


TODO: Find out why occasionally stopping the CS times out. Seen 
especially with gem_eio tests.


I will update the comment to be clear.


This timeout is in general or with this patch only?


In general. I only tried it on dg2, but I don't see any existing caller 
checking the return value of intel_engine_stop_cs.


Okay, then perhaps adding a comment in this patch added some confusion. 
Fine either way.





+ * function.
+ */
 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
 ENGINE_TRACE(engine,
  "timed out on ST

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/bios: Rework BDB block handling (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: Rework BDB block handling (rev5)
URL   : https://patchwork.freedesktop.org/series/101496/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11603 -> Patchwork_101496v5


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_101496v5 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_101496v5, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/index.html

Participating hosts (42 -> 43)
--

  Additional (3): fi-cml-u2 fi-rkl-11600 bat-dg1-5 
  Missing(2): fi-hsw-4770 fi-bsw-cyan 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_101496v5:

### IGT changes ###

 Possible regressions 

  * igt@i915_suspend@system-suspend-without-i915:
- fi-cml-u2:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/fi-cml-u2/igt@i915_susp...@system-suspend-without-i915.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_chamelium@common-hpd-after-suspend:
- {bat-rpls-1}:   NOTRUN -> [INCOMPLETE][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/bat-rpls-1/igt@kms_chamel...@common-hpd-after-suspend.html

  
Known issues


  Here are the changes found in Patchwork_101496v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@fbdev@write:
- bat-dg1-5:  NOTRUN -> [SKIP][3] ([i915#2582]) +4 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/bat-dg1-5/igt@fb...@write.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][4] ([i915#1208]) +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-cml-u2:  NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/fi-cml-u2/igt@gem_huc_c...@huc-copy.html
- fi-rkl-11600:   NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2:  NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/fi-cml-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_mmap@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][9] ([i915#4083])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/bat-dg1-5/igt@gem_m...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-5:  NOTRUN -> [SKIP][10] ([i915#4077]) +2 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg1-5:  NOTRUN -> [SKIP][11] ([i915#4079]) +1 similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/bat-dg1-5/igt@gem_tiled_pread_basic.html
- fi-rkl-11600:   NOTRUN -> [SKIP][12] ([i915#3282])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- bat-dg1-5:  NOTRUN -> [SKIP][13] ([i915#1155])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/bat-dg1-5/igt@i915_pm_backli...@basic-brightness.html
- fi-rkl-11600:   NOTRUN -> [SKIP][14] ([i915#3012])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gem_contexts:
- fi-bdw-5557u:   [PASS][15] -> [INCOMPLETE][16] ([i915#5502] / 
[i915#5801])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11603/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-5:  NOTRUN -> [INCOMPLETE][17] ([i915#4418])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101496v5/bat-dg1-5/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@hangcheck:

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config

[Tvrtko Ursulin]

On 04/05/2022 17:48, Matt Roper wrote:

On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
to exercise a certain code path, so in case of values coming from MMIO
reads we cannot be sure CI will have all the possible SKUs and parts.

Use drm_warn instead and move logging to init phase while at it.


Changing to drm_warn looks good, although moving the location changes
the intent a bit; I think originally the idea was to warn if we were
trying to do a steering lookup for a type that we never initialized
(e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
read the register in the first place).  But I don't think we've ever
made a mistake that would cause us to trip the warning, so it probably
isn't terribly important to keep it there.


Ah I see.. there we could put something like:

case MSLICE:
GEM_WARN_ON(!HAS_MSLICES(...));

?

Regards,

Tvrtko



Reviewed-by: Matt Roper 



Signed-off-by: Tvrtko Ursulin 
Cc: Matt Roper 
Cc: Jani Nikula 
---
  drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++---
  1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 53307ca0eed0..c474e5c3ea5e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
 * An mslice is unavailable only if both the meml3 for the slice is
 * disabled *and* all of the DSS in the slice (quadrant) are disabled.
 */
-   if (HAS_MSLICES(i915))
+   if (HAS_MSLICES(i915)) {
gt->info.mslice_mask =
slicemask(gt, GEN_DSS_PER_MSLICE) |
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
 GEN12_MEML3_EN_MASK);
+   if (!gt->info.mslice_mask) /* should be impossible! */
+   drm_warn(&i915->drm, "mslice mask all zero!\n");
+   }
  
  	if (IS_DG2(i915)) {

gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
@@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
gt->info.l3bank_mask =
~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN10_L3BANK_MASK;
+   if (!gt->info.l3bank_mask) /* should be impossible! */
+   drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
} else if (HAS_MSLICES(i915)) {
MISSING_CASE(INTEL_INFO(i915)->platform);
}
@@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt 
*gt,
  {
switch (type) {
case L3BANK:
-   GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be 
impossible! */
-
*sliceid = 0;   /* unused */
*subsliceid = __ffs(gt->info.l3bank_mask);
break;
case MSLICE:
-   GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be 
impossible! */
-
*sliceid = __ffs(gt->info.mslice_mask);
*subsliceid = 0;/* unused */
break;
case LNCF:
-   GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be 
impossible! */
-
/*
 * An LNCF is always present if its mslice is present, so we
 * can safely just steer to LNCF 0 in all cases.
--
2.32.0

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/bios: Rework BDB block handling (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: Rework BDB block handling (rev5)
URL   : https://patchwork.freedesktop.org/series/101496/
State : warning

== Summary ==

Error: dim checkpatch failed
d75e921156be drm/i915/bios: Reorder panel DTD parsing
13196c04b00e drm/i915/bios: Generate LFP data table pointers if the VBT lacks 
them
-:46: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#46: FILE: drivers/gpu/drm/i915/display/intel_bios.c:319:
+   if (data[i] == 0xff && data[i+1] == 0xff)
 ^

-:134: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#134: FILE: drivers/gpu/drm/i915/display/intel_bios.c:407:
+   next_lfp_data_ptr(&ptrs->ptr[i].fp_timing, 
&ptrs->ptr[i-1].fp_timing, size);
   ^

-:135: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#135: FILE: drivers/gpu/drm/i915/display/intel_bios.c:408:
+   next_lfp_data_ptr(&ptrs->ptr[i].dvo_timing, 
&ptrs->ptr[i-1].dvo_timing, size);
^

-:136: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#136: FILE: drivers/gpu/drm/i915/display/intel_bios.c:409:
+   next_lfp_data_ptr(&ptrs->ptr[i].panel_pnp_id, 
&ptrs->ptr[i-1].panel_pnp_id, size);
  ^

total: 0 errors, 0 warnings, 4 checks, 161 lines checked
80f6822f3eb1 drm/i915/bios: Get access to the tail end of the LFP data block
e731df8f0bd2 drm/i915/bios: Document the mess around the LFP data tables
c2ce8b91b07d drm/i915/bios: Assume panel_type==0 if the VBT has bogus data
610b6e58d9d3 drm/i915/bios: Extract get_panel_type()
e5ef6e07e160 drm/i915/bios: Refactor panel_type code
fc9a0a104734 drm/i915/bios: Parse the seamless DRRS min refresh rate
d628e4268828 drm/i915: Respect VBT seamless DRRS min refresh rate

Re: [Intel-gfx] [PATCH] drm/i915/reset: Add Wa_22011802037 for gen11 and execlist backend

[Umesh Nerlige Ramappa]

On Wed, May 04, 2022 at 09:10:42AM +0100, Tvrtko Ursulin wrote:


On 03/05/2022 20:49, Umesh Nerlige Ramappa wrote:

On Tue, May 03, 2022 at 09:42:52AM +0100, Tvrtko Ursulin wrote:


On 02/05/2022 23:18, Umesh Nerlige Ramappa wrote:

Current implementation of Wa_22011802037 is limited to the GuC backend
and gen12. Add support for execlist backend and gen11 as well.


Is the implication f6aa0d713c88 ("drm/i915: Add Wa_22011802037 
force cs halt") does not work on Tigerlake? Fixes: tag probably 
required in that case since I have sold that fix as a, well, fix.


After the fix was made, the WA has evolved and added some more steps 
for handling pending MI_FORCE_WAKEs. This patch is the additional 
set of steps needed for the WA. As you mentioned offline, I should 
correct the commit message to indicate that the WA does exist for 
execlists, but needs additional steps. Will add Fixes: tag.


Ok, that would be good then since it does sound they need to be tied 
together (as in cherry picked for fixes).


Will it be followed up with preempt-to-idle implementation to avoid 
the, as I understand it, potential for activity on one CCS engine 
defeating the WA on another by timing out the wait for idle?


fwiu, for the case where we want to limit the reset to a single engine, 
the preempt-to-idle implementation may be required - 
https://patchwork.freedesktop.org/series/101432/. If preempt-to-idle 
fails, the hangcheck should kick in and then do a gt-reset. If that 
happens, then the WA flow in the patch should be applied.





Signed-off-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/gt/intel_engine.h    |  2 +
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 81 ++-
 .../drm/i915/gt/intel_execlists_submission.c  |  7 ++
 .../gpu/drm/i915/gt/intel_ring_submission.c   |  7 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc.c    |  4 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 81 ++-
 6 files changed, 103 insertions(+), 79 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h 
b/drivers/gpu/drm/i915/gt/intel_engine.h

index 1431f1e9dbee..04e435bce79b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -201,6 +201,8 @@ int intel_ring_submission_setup(struct 
intel_engine_cs *engine);

 int intel_engine_stop_cs(struct intel_engine_cs *engine);
 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
+void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs 
*engine);

+
 void intel_engine_set_hwsp_writemask(struct intel_engine_cs 
*engine, u32 mask);

 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c

index 14c6ddbbfde8..0bda665a407c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1282,10 +1282,10 @@ static int __intel_engine_stop_cs(struct 
intel_engine_cs *engine,

 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
 /*
- * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is
+ * Wa_22011802037 : gen11, gen12, Prior to doing a reset, 
ensure CS is

  * stopped, set ring stop bit and prefetch disable bit to halt CS
  */
-    if (GRAPHICS_VER(engine->i915) == 12)
+    if (GRAPHICS_VER(engine->i915) == 11 || 
GRAPHICS_VER(engine->i915) == 12)


IS_GRAPHICS_VER(11, 12)

 intel_uncore_write_fw(uncore, 
RING_MODE_GEN7(engine->mmio_base),

   _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
@@ -1308,6 +1308,14 @@ int intel_engine_stop_cs(struct 
intel_engine_cs *engine)

 return -ENODEV;
 ENGINE_TRACE(engine, "\n");
+    /*
+ * TODO: Occasionally trying to stop the cs times out, but does not


What is the TODO part? To figure out why is sometimes does not work?


+ * adversely affect functionality. The timeout is set as a config
+ * parameter that defaults to 100ms. Assuming that this timeout is
+ * sufficient for any pending MI_FORCEWAKEs to complete. Once root
+ * caused, the caller must check and handler the return from this


s/handler/handle/

TODO is to convert the function to return an error?


TODO: Find out why occasionally stopping the CS times out. Seen 
especially with gem_eio tests.


I will update the comment to be clear.


This timeout is in general or with this patch only?


In general. I only tried it on dg2, but I don't see any existing caller 
checking the return value of intel_engine_stop_cs.







+ * function.
+ */
 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
 ENGINE_TRACE(engine,
  "timed out on STOP_RING -> IDLE; HEAD:%04x, 
TAIL:%04x\n",
@@ -1334,6 +1342,75 @@ void intel_engine_cancel_stop_cs(struct 
intel_engine_cs *engine)
 ENGINE_WRITE_FW(engine, RING_MI_MODE, 
_MASKED_BIT_DISABLE(STOP_RING));

 }
+static u32 __cs_pending_mi_force_

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/fbdev: print error in case drm_fb_helper_initial_config fails (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/fbdev: print error in case 
drm_fb_helper_initial_config fails (rev2)
URL   : https://patchwork.freedesktop.org/series/103533/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11603 -> Patchwork_103533v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_103533v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_103533v2, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/index.html

Participating hosts (42 -> 42)
--

  Additional (3): fi-cml-u2 fi-rkl-11600 fi-icl-u2 
  Missing(3): fi-bsw-cyan bat-rpls-1 bat-dg2-9 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103533v2:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_gttfill@basic:
- fi-icl-u2:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-icl-u2/igt@gem_exec_gttf...@basic.html

  
Known issues


  Here are the changes found in Patchwork_103533v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][2] ([i915#1208]) +1 similar issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-cml-u2/igt@gem_huc_c...@huc-copy.html
- fi-rkl-11600:   NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-rkl-11600/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-cml-u2:  NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-cml-u2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][7] ([i915#3282])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600:   NOTRUN -> [SKIP][8] ([i915#3012])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@coherency:
- fi-bdw-5557u:   [PASS][9] -> [INCOMPLETE][10] ([i915#5674] / 
[i915#5685])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11603/fi-bdw-5557u/igt@i915_selftest@l...@coherency.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-bdw-5557u/igt@i915_selftest@l...@coherency.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-rkl-11600:   NOTRUN -> [SKIP][11] ([fdo#111827]) +8 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-rkl-11600/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@dp-hpd-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][12] ([fdo#109284] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-cml-u2/igt@kms_chamel...@dp-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-rkl-11600:   NOTRUN -> [SKIP][13] ([i915#4070] / [i915#4103]) +1 
similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-cml-u2:  NOTRUN -> [SKIP][14] ([fdo#109278]) +1 similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-cml-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2:  NOTRUN -> [SKIP][15] ([fdo#109285])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-cml-u2/igt@kms_force_connector_ba...@force-load-detect.html
- fi-rkl-11600:   NOTRUN -> [SKIP][16] ([fdo#109285] / [i915#4098])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103533v2/fi-rkl-11600/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2:  NOTRUN -> [DMESG-WARN][17] ([i915#4269])
   [17]: 
https://intel-gfx-ci.01.org

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Introduce Ponte Vecchio

[Vudum, Lakshminarayana]

igt@kms_concurrent@pipe-b@hdmi-a-3 is not yet in CBL, otherwise failures are 
addressed and are-reported.

-Original Message-
From: Roper, Matthew D  
Sent: Tuesday, May 3, 2022 10:33 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana 
Subject: Re: ✗ Fi.CI.IGT: failure for i915: Introduce Ponte Vecchio

On Mon, May 02, 2022 at 10:58:32PM +, Patchwork wrote:
> == Series Details ==
> 
> Series: i915: Introduce Ponte Vecchio
> URL   : https://patchwork.freedesktop.org/series/103443/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_11588_full -> Patchwork_103443v1_full 
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_103443v1_full absolutely need 
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_103443v1_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (13 -> 13)
> --
> 
>   No changes in participating hosts
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_103443v1_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@i915_pm_rpm@system-suspend-modeset:
> - shard-kbl:  [PASS][1] -> [INCOMPLETE][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-kbl4/igt@i915_pm_...@system-suspend-modeset.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-kbl6
> /igt@i915_pm_...@system-suspend-modeset.html

https://gitlab.freedesktop.org/drm/intel/-/issues/3614

> 
>   * {igt@kms_concurrent@pipe-b@hdmi-a-3} (NEW):
> - {shard-dg1}:NOTRUN -> [CRASH][3] +1 similar issue
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-dg1-
> 18/igt@kms_concurrent@pip...@hdmi-a-3.html

https://gitlab.freedesktop.org/drm/intel/-/issues/4886

> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
> - shard-tglb: [PASS][4] -> [INCOMPLETE][5]
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-tglb7/igt@kms_frontbuffer_track...@fbcpsr-1p-pri-indfb-multidraw.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-tglb
> 8/igt@kms_frontbuffer_track...@fbcpsr-1p-pri-indfb-multidraw.html

No obvious warnings/errors.  Maybe the same as
https://gitlab.freedesktop.org/drm/intel/-/issues/5756 ?


None of the changes here are caused by the PVC series.  I'm going to apply 
patch #1 to drm-intel-gt-next to get the ball rolling on having the basic 
IS_PONTEVECCHIO() definition in the tree (which will help cut down on future 
cross-tree dependencies).

We'll hold off on applying any of the others until after the next 
drm-intel-gt-next pull requests gets sent.


Matt

> 
>   
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@i915_pm_rpm@gem-evict-pwrite:
> - {shard-rkl}:[PASS][6] -> [INCOMPLETE][7] +1 similar issue
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-rkl-5/igt@i915_pm_...@gem-evict-pwrite.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-rkl-
> 5/igt@i915_pm_...@gem-evict-pwrite.html
> 
>   * igt@i915_pm_rpm@system-suspend-devices:
> - {shard-dg1}:NOTRUN -> [INCOMPLETE][8] +3 similar issues
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-dg1-
> 18/igt@i915_pm_...@system-suspend-devices.html
> 
>   * igt@i915_selftest@live:
> - {shard-rkl}:NOTRUN -> [INCOMPLETE][9]
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-rkl-
> 5/igt@i915_selft...@live.html
> 
>   
> New tests
> -
> 
>   New tests have been introduced between CI_DRM_11588_full and 
> Patchwork_103443v1_full:
> 
> ### New IGT tests (2) ###
> 
>   * igt@kms_concurrent@pipe-a@hdmi-a-3:
> - Statuses : 1 crash(s)
> - Exec time: [0.03] s
> 
>   * igt@kms_concurrent@pipe-b@hdmi-a-3:
> - Statuses : 1 crash(s)
> - Exec time: [0.04] s
> 
>   
> 
> Known issues
> 
> 
>   Here are the changes found in Patchwork_103443v1_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@api_intel_bb@blit-reloc-keep-cache:
> - shard-skl:  [PASS][10] -> [DMESG-WARN][11] ([i915#1982])
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-skl7/igt@api_intel...@blit-reloc-keep-cache.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-skl6
> /igt@api_intel...@blit-reloc-keep-cache.html
> 
>   * igt@feature_discovery@display-4x:
> - shard-tglb: 

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config

[Matt Roper]

On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
> to exercise a certain code path, so in case of values coming from MMIO
> reads we cannot be sure CI will have all the possible SKUs and parts.
> 
> Use drm_warn instead and move logging to init phase while at it.

Changing to drm_warn looks good, although moving the location changes
the intent a bit; I think originally the idea was to warn if we were
trying to do a steering lookup for a type that we never initialized
(e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
read the register in the first place).  But I don't think we've ever
made a mistake that would cause us to trip the warning, so it probably
isn't terribly important to keep it there.

Reviewed-by: Matt Roper 

> 
> Signed-off-by: Tvrtko Ursulin 
> Cc: Matt Roper 
> Cc: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++---
>  1 file changed, 6 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 53307ca0eed0..c474e5c3ea5e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
>* An mslice is unavailable only if both the meml3 for the slice is
>* disabled *and* all of the DSS in the slice (quadrant) are disabled.
>*/
> - if (HAS_MSLICES(i915))
> + if (HAS_MSLICES(i915)) {
>   gt->info.mslice_mask =
>   slicemask(gt, GEN_DSS_PER_MSLICE) |
>   (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
>GEN12_MEML3_EN_MASK);
> + if (!gt->info.mslice_mask) /* should be impossible! */
> + drm_warn(&i915->drm, "mslice mask all zero!\n");
> + }
>  
>   if (IS_DG2(i915)) {
>   gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
> @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
>   gt->info.l3bank_mask =
>   ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
>   GEN10_L3BANK_MASK;
> + if (!gt->info.l3bank_mask) /* should be impossible! */
> + drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
>   } else if (HAS_MSLICES(i915)) {
>   MISSING_CASE(INTEL_INFO(i915)->platform);
>   }
> @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt 
> *gt,
>  {
>   switch (type) {
>   case L3BANK:
> - GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be 
> impossible! */
> -
>   *sliceid = 0;   /* unused */
>   *subsliceid = __ffs(gt->info.l3bank_mask);
>   break;
>   case MSLICE:
> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be 
> impossible! */
> -
>   *sliceid = __ffs(gt->info.mslice_mask);
>   *subsliceid = 0;/* unused */
>   break;
>   case LNCF:
> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be 
> impossible! */
> -
>   /*
>* An LNCF is always present if its mslice is present, so we
>* can safely just steer to LNCF 0 in all cases.
> -- 
> 2.32.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] ✓ Fi.CI.IGT: success for i915: Introduce Ponte Vecchio

[Patchwork]

== Series Details ==

Series: i915: Introduce Ponte Vecchio
URL   : https://patchwork.freedesktop.org/series/103443/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11588_full -> Patchwork_103443v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103443v1_full:

### IGT changes ###

 Possible regressions 

  * {igt@kms_concurrent@pipe-b@hdmi-a-3} (NEW):
- {shard-dg1}:NOTRUN -> [CRASH][1] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-dg1-18/igt@kms_concurrent@pip...@hdmi-a-3.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@gem-evict-pwrite:
- {shard-rkl}:[PASS][2] -> [INCOMPLETE][3] +1 similar issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-rkl-5/igt@i915_pm_...@gem-evict-pwrite.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-rkl-5/igt@i915_pm_...@gem-evict-pwrite.html

  * igt@i915_pm_rpm@system-suspend-devices:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][4] +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-dg1-18/igt@i915_pm_...@system-suspend-devices.html

  * igt@i915_selftest@live:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][5]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-rkl-5/igt@i915_selft...@live.html

  
New tests
-

  New tests have been introduced between CI_DRM_11588_full and 
Patchwork_103443v1_full:

### New IGT tests (2) ###

  * igt@kms_concurrent@pipe-a@hdmi-a-3:
- Statuses : 1 crash(s)
- Exec time: [0.03] s

  * igt@kms_concurrent@pipe-b@hdmi-a-3:
- Statuses : 1 crash(s)
- Exec time: [0.04] s

  

Known issues


  Here are the changes found in Patchwork_103443v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@api_intel_bb@blit-reloc-keep-cache:
- shard-skl:  [PASS][6] -> [DMESG-WARN][7] ([i915#1982])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-skl7/igt@api_intel...@blit-reloc-keep-cache.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-skl6/igt@api_intel...@blit-reloc-keep-cache.html

  * igt@feature_discovery@display-4x:
- shard-tglb: NOTRUN -> [SKIP][8] ([i915#1839])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-tglb1/igt@feature_discov...@display-4x.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-kbl:  NOTRUN -> [DMESG-WARN][9] ([i915#5076] / [i915#5614])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-kbl4/igt@gem_exec_balan...@parallel-keep-in-fence.html

  * igt@gem_exec_fair@basic-none@vecs0:
- shard-apl:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-apl1/igt@gem_exec_fair@basic-n...@vecs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-apl4/igt@gem_exec_fair@basic-n...@vecs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-iclb7/igt@gem_exec_fair@basic-p...@vcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-iclb7/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-uc:
- shard-snb:  [PASS][14] -> [SKIP][15] ([fdo#109271]) +3 similar 
issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-snb4/igt@gem_exec_fl...@basic-batch-kernel-default-uc.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-snb6/igt@gem_exec_fl...@basic-batch-kernel-default-uc.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-kbl7/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- shard-apl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-apl2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_userptr_blits@coherency-unsync:
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#3297])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-tglb1/igt@gem_userptr_bl...@coherency-unsync.html

  * igt@gem_userptr_blits@input-checking:
- shard-skl:   

Re: [Intel-gfx] [PATCH] drm/i915: Change semantics of context isolation reporting to UM

[Daniel Vetter]

On Wed, May 04, 2022 at 07:59:27AM -0700, Matt Roper wrote:
> On Wed, May 04, 2022 at 02:24:07PM +0200, Daniel Vetter wrote:
> > On Fri, 29 Apr 2022 at 17:11, Adrian Larumbe
> >  wrote:
> > > I915_PARAM_HAS_CONTEXT_ISOLATION was already being used as a boolean by
> > > both Iris and Vulkan , and stood for the guarantee that, when creating a
> > > new context, all state set by it will not leak to any other context.
> > >
> > > However the actual return value was a bitmask where every bit stood for an
> > > initialised engine, and IGT test gem_ctx_isolation makes use of this mask
> > > for deciding on the actual context engine isolation status.
> > >
> > > However, we do not provide UAPI for IGT tests, so the value returned by 
> > > the
> > > PARAM ioctl has to reflect Mesa usage as a boolean.
> > >
> > > This change only made sense after compute engine support was added to the
> > > driver in commit 944823c9463916dd53f3 ("drm/i915/xehp: Define compute 
> > > class
> > > and engine") because no context isolation can be assumed on any device 
> > > with
> > > both RCS annd CCS engines.
> > >
> > > Signed-off-by: Adrian Larumbe 
> > 
> > Top level post and adding Matt Roper and dri-devel.
> > 
> > This was meant as a simple cleanup after CCS enabling in upstream, but
> > that CCS enabling seems to have gone wrong.
> > 
> > What I thought we should be done for CCS enabling is the following:
> > - actually have some igt-side hardcoded assumption about how much
> > engines are isolated from each another, which is a hw property. I
> > think some of that landed, but it's very incomplete
> > 
> > - convert all igt tests over to that. At least gem_ctx_isolation.c is
> > not converted over, as Adrian pointed out.
> 
> I pointed that out last week in one of our offline syncs and that's what
> got the ball rolling on that test again.  But you specifically told us
> that the uapi cleanup for context isolation shouldn't block the CCS
> patches from landing since that was still happening in parallel:
> 
> "...I do see the uapi cleanup as part of this multi engine/CCS
> enabling, but it's not a blocker to land the patches..."
> 
> Did we misunderstand what you were trying to say in that email or was
> there a change of direction here?

The cleanup (which Adrian is now working on, but there's confusion) is
totally fine to do later. What looks really iffy is the test coverage, and
at least from me looking around gem_ctx_isolation wasn't touched or
updated for CCS engines, and that looks like it's not enough. Either those
tests are bogus or not actually testing a lot, and then we should delete
them. Or there's probably going to be some impact on how much exactly the
engines/contexts are isolated against each another.

That's the part that I think should be done before we call CCS support
done and ready for merging. And if that's done properly it should also
take care of the "igt uses HAS_CONTEXT_ISOLATION getparam" issue, since
you need something more fancy anyway.
-Daniel


> 
> 
> Matt
> 
> > 
> > - once igt stopped using this context isolation getparam (we do not,
> > ever, create uapi just for testcases), fix up the uapi to what iris
> > actually needs, which is _only_ a boolean which indicates whether the
> > kernel's context setup code leaks register state from existing
> > contexts to newly created ones. Which is the bug iris works around
> > here, where using iris caused gpu hangs in libva. Iow, the kernel
> > should always and unconditionally return true here. Check out iris
> > history for details please, actual iris usage has nothing to do with
> > any other cross-context or cross-engine isolation guarantee we're
> > making, it's purely about whether our hw ctx code is buggy or not and
> > leaks state between clients, because we accidentally used the
> > currently running ctx as template instead of a fixed one created once
> > at driver load.
> > 
> > Matt, since the CCS enabling on the igt validation side looks very
> > incomplete I'm leaning very much towards "pls revert, try again".
> > 
> > Cheers, Daniel
> > 
> > > ---
> > >  drivers/gpu/drm/i915/gt/intel_engine_user.c | 13 -
> > >  drivers/gpu/drm/i915/gt/intel_engine_user.h |  1 +
> > >  drivers/gpu/drm/i915/i915_drm_client.h  |  2 +-
> > >  drivers/gpu/drm/i915/i915_getparam.c|  2 +-
> > >  include/uapi/drm/i915_drm.h | 14 +++---
> > >  5 files changed, 18 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c 
> > > b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > index 0f6cd96b459f..2d6bd36d6150 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > > @@ -47,7 +47,7 @@ static const u8 uabi_classes[] = {
> > > [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
> > > [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
> > > [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDE

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Support programming the EU priority in the GuC descriptor

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Support programming the EU priority in the GuC descriptor
URL   : https://patchwork.freedesktop.org/series/103515/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11599_full -> Patchwork_103515v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103515v1_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@system-suspend:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][1] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-dg1-16/igt@i915_pm_...@system-suspend.html

  
Known issues


  Here are the changes found in Patchwork_103515v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@kms:
- shard-tglb: [PASS][2] -> [FAIL][3] ([i915#5784])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-tglb6/igt@gem_...@kms.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-tglb3/igt@gem_...@kms.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-tglb7/igt@gem_...@unwedge-stress.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-tglb7/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl:  [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-kbl1/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-kbl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-tglb8/igt@gem_exec_fair@basic-p...@bcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-tglb8/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: NOTRUN -> [FAIL][12] ([i915#2849])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_flush@basic-uc-rw-default:
- shard-snb:  [PASS][13] -> [SKIP][14] ([fdo#109271]) +3 similar 
issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-snb7/igt@gem_exec_fl...@basic-uc-rw-default.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-snb6/igt@gem_exec_fl...@basic-uc-rw-default.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][15] ([fdo#112283])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-iclb8/igt@gem_exec_par...@secure-non-root.html

  * igt@gem_flink_race@flink_close:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#5687])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-iclb1/igt@gem_flink_race@flink_close.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-iclb8/igt@gem_flink_race@flink_close.html

  * igt@gem_lmem_swapping@heavy-multi:
- shard-apl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +1 
similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-apl3/igt@gem_lmem_swapp...@heavy-multi.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-skl9/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@smem-oom:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#4613]) +1 similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-iclb3/igt@gem_lmem_swapp...@smem-oom.html

  * igt@gem_pxp@create-regular-context-1:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#4270])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103515v1/shard-iclb5/igt@gem_...@create-regular-context-1.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
- shard-iclb:

[Intel-gfx] ✓ Fi.CI.IGT: success for i915: Introduce Ponte Vecchio

[Patchwork]

== Series Details ==

Series: i915: Introduce Ponte Vecchio
URL   : https://patchwork.freedesktop.org/series/103443/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11588_full -> Patchwork_103443v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103443v1_full:

### IGT changes ###

 Possible regressions 

  * {igt@kms_concurrent@pipe-b@hdmi-a-3} (NEW):
- {shard-dg1}:NOTRUN -> [CRASH][1] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-dg1-18/igt@kms_concurrent@pip...@hdmi-a-3.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@gem-evict-pwrite:
- {shard-rkl}:[PASS][2] -> [INCOMPLETE][3] +1 similar issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-rkl-5/igt@i915_pm_...@gem-evict-pwrite.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-rkl-5/igt@i915_pm_...@gem-evict-pwrite.html

  * igt@i915_pm_rpm@system-suspend-devices:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][4] +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-dg1-18/igt@i915_pm_...@system-suspend-devices.html

  * igt@i915_selftest@live:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][5]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-rkl-5/igt@i915_selft...@live.html

  
New tests
-

  New tests have been introduced between CI_DRM_11588_full and 
Patchwork_103443v1_full:

### New IGT tests (2) ###

  * igt@kms_concurrent@pipe-a@hdmi-a-3:
- Statuses : 1 crash(s)
- Exec time: [0.03] s

  * igt@kms_concurrent@pipe-b@hdmi-a-3:
- Statuses : 1 crash(s)
- Exec time: [0.04] s

  

Known issues


  Here are the changes found in Patchwork_103443v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@api_intel_bb@blit-reloc-keep-cache:
- shard-skl:  [PASS][6] -> [DMESG-WARN][7] ([i915#1982])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-skl7/igt@api_intel...@blit-reloc-keep-cache.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-skl6/igt@api_intel...@blit-reloc-keep-cache.html

  * igt@feature_discovery@display-4x:
- shard-tglb: NOTRUN -> [SKIP][8] ([i915#1839])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-tglb1/igt@feature_discov...@display-4x.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-kbl:  NOTRUN -> [DMESG-WARN][9] ([i915#5076] / [i915#5614])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-kbl4/igt@gem_exec_balan...@parallel-keep-in-fence.html

  * igt@gem_exec_fair@basic-none@vecs0:
- shard-apl:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-apl1/igt@gem_exec_fair@basic-n...@vecs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-apl4/igt@gem_exec_fair@basic-n...@vecs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-iclb7/igt@gem_exec_fair@basic-p...@vcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-iclb7/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-uc:
- shard-snb:  [PASS][14] -> [SKIP][15] ([fdo#109271]) +3 similar 
issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11588/shard-snb4/igt@gem_exec_fl...@basic-batch-kernel-default-uc.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-snb6/igt@gem_exec_fl...@basic-batch-kernel-default-uc.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-kbl7/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- shard-apl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-apl2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_userptr_blits@coherency-unsync:
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#3297])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v1/shard-tglb1/igt@gem_userptr_bl...@coherency-unsync.html

  * igt@gem_userptr_blits@input-checking:
- shard-skl:   

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dmc: Add MMIO range restrictions (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add MMIO range restrictions (rev6)
URL   : https://patchwork.freedesktop.org/series/102168/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11599_full -> Patchwork_102168v6_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_102168v6_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_102168v6_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_102168v6_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@mock@requests:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-skl6/igt@i915_selftest@m...@requests.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v6/shard-skl10/igt@i915_selftest@m...@requests.html

  * {igt@kms_concurrent@pipe-a@hdmi-a-3} (NEW):
- {shard-dg1}:NOTRUN -> [CRASH][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v6/shard-dg1-18/igt@kms_concurrent@pip...@hdmi-a-3.html

  
 Warnings 

  * igt@i915_pm_dc@dc6-dpms:
- shard-skl:  [FAIL][4] ([i915#454]) -> [INCOMPLETE][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-skl9/igt@i915_pm...@dc6-dpms.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v6/shard-skl4/igt@i915_pm...@dc6-dpms.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_flink_race@flink_close:
- {shard-tglu}:   NOTRUN -> [FAIL][6]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v6/shard-tglu-3/igt@gem_flink_race@flink_close.html

  * igt@i915_pm_rpm@system-suspend-devices:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][7] +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v6/shard-dg1-18/igt@i915_pm_...@system-suspend-devices.html

  
New tests
-

  New tests have been introduced between CI_DRM_11599_full and 
Patchwork_102168v6_full:

### New IGT tests (1) ###

  * igt@kms_concurrent@pipe-a@hdmi-a-3:
- Statuses : 1 crash(s)
- Exec time: [0.03] s

  

Known issues


  Here are the changes found in Patchwork_102168v6_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#5784]) +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-tglb7/igt@gem_...@unwedge-stress.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v6/shard-tglb2/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v6/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl:  [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-kbl1/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v6/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-tglb8/igt@gem_exec_fair@basic-p...@bcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v6/shard-tglb5/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v6/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_flush@basic-uc-pro-default:
- shard-snb:  [PASS][17] -> [SKIP][18] ([fdo#109271]) +3 similar 
issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-snb4/igt@gem_exec_fl...@basic-uc-pro-default.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v6/shard-snb6/igt@gem_exec_fl...@basic-uc-pro-default.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#112283])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102168v6/shard-iclb7/igt@g

[Intel-gfx] ✓ Fi.CI.IGT: success for DG2 DMC Support

[Patchwork]

== Series Details ==

Series: DG2 DMC Support
URL   : https://patchwork.freedesktop.org/series/103513/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11599_full -> Patchwork_103513v1_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_103513v1_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_103513v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103513v1_full:

### IGT changes ###

 Warnings 

  * igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: [SKIP][1] ([fdo#109642] / [fdo#111068] / [i915#658]) 
-> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-iclb4/igt@kms_psr2_su@page_flip-nv12.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103513v1/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_flink_race@flink_close:
- {shard-tglu}:   NOTRUN -> [FAIL][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103513v1/shard-tglu-5/igt@gem_flink_race@flink_close.html

  * igt@i915_pm_rpm@system-suspend-devices:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][4] +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103513v1/shard-dg1-13/igt@i915_pm_...@system-suspend-devices.html

  * igt@i915_selftest@live@gem_contexts:
- {shard-rkl}:[PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-rkl-5/igt@i915_selftest@live@gem_contexts.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103513v1/shard-rkl-5/igt@i915_selftest@live@gem_contexts.html

  
Known issues


  Here are the changes found in Patchwork_103513v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_eio@kms:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#5784])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-tglb6/igt@gem_...@kms.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103513v1/shard-tglb1/igt@gem_...@kms.html

  * igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][9] -> [TIMEOUT][10] ([i915#3070])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-iclb4/igt@gem_...@unwedge-stress.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103513v1/shard-iclb2/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103513v1/shard-apl8/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar 
issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-kbl6/igt@gem_exec_fair@basic-n...@vcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103513v1/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-tglb8/igt@gem_exec_fair@basic-p...@bcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103513v1/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_flush@basic-wb-ro-default:
- shard-snb:  [PASS][17] -> [SKIP][18] ([fdo#109271])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-snb4/igt@gem_exec_fl...@basic-wb-ro-default.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103513v1/shard-snb6/igt@gem_exec_fl...@basic-wb-ro-default.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#112283])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103513v1/shard-iclb7/igt@gem_exec_par...@secure-non-root.html

  * igt@gem_exec_suspend@basic-s3@smem:
- shard-apl:  [PASS][20] -> [DMESG-WARN][21] ([i915#180]) +3 
similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11599/shard-apl1/igt@gem_exec_suspend@basic...@smem.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103513v1/shard-apl8/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_lmem_swapping@heavy-multi:
- shard-apl:  

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Make fastset not suck and allow seamless M/N changes (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev2)
URL   : https://patchwork.freedesktop.org/series/103491/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11602 -> Patchwork_103491v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_103491v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_103491v2, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/index.html

Participating hosts (33 -> 40)
--

  Additional (7): fi-rkl-11600 bat-adlm-1 bat-adlp-6 bat-adln-1 bat-rpls-1 
bat-rpls-2 bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_103491v2:

### IGT changes ###

 Possible regressions 

  * igt@runner@aborted:
- fi-hsw-g3258:   NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-hsw-g3258/igt@run...@aborted.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gt_heartbeat:
- {bat-adlm-1}:   NOTRUN -> [INCOMPLETE][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/bat-adlm-1/igt@i915_selftest@live@gt_heartbeat.html

  
Known issues


  Here are the changes found in Patchwork_103491v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-rkl-11600:   NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-rkl-11600:   NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][5] ([i915#3282])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600:   NOTRUN -> [SKIP][6] ([i915#3012])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-rkl-11600:   NOTRUN -> [SKIP][7] ([fdo#111827]) +8 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-rkl-11600:   NOTRUN -> [SKIP][8] ([i915#4070] / [i915#4103]) +1 
similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600:   NOTRUN -> [SKIP][9] ([fdo#109285] / [i915#4098])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-rkl-11600:   NOTRUN -> [SKIP][10] ([i915#4070] / [i915#533])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-rkl-11600:   NOTRUN -> [SKIP][11] ([i915#1072]) +3 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@kms_psr@primary_mmap_gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-rkl-11600:   NOTRUN -> [SKIP][12] ([i915#3555] / [i915#4098])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
- fi-rkl-11600:   NOTRUN -> [SKIP][13] ([i915#3301] / [i915#3708])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@prime_v...@basic-userptr.html

  * igt@prime_vgem@basic-write:
- fi-rkl-11600:   NOTRUN -> [SKIP][14] ([i915#3291] / [i915#3708]) +2 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@prime_v...@basic-write.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][15] ([i915#5594])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-hsw-4770/igt@run...@aborted.html
- fi-bxt-dsi: NOTRUN -> [FAIL][16] ([i915#5257])
   [16]: 
https://intel-gfx-ci.01

Re: [Intel-gfx] [PATCH i-g-t 1/2] tests/i915/gem_caching: handle discrete

[Das, Nirmoy]

The series is Reviewed-by: Nirmoy Das 

On 5/4/2022 5:08 PM, Matthew Auld wrote:

Test should still be valid, even if we can't explicitly control the PTE
caching bits, like on discrete, where the caching should already be
enabled by default for system memory objects.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/4873
Signed-off-by: Matthew Auld 
Cc: Nirmoy Das 
---
  tests/i915/gem_caching.c | 6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/tests/i915/gem_caching.c b/tests/i915/gem_caching.c
index 4e844952..eb0170ab 100644
--- a/tests/i915/gem_caching.c
+++ b/tests/i915/gem_caching.c
@@ -147,7 +147,8 @@ igt_main
  
  		igt_require_gem(data.fd);

gem_require_blitter(data.fd);
-   gem_require_caching(data.fd);
+   if (!gem_has_lmem(data.fd))
+   gem_require_caching(data.fd);
  
  		data.devid = intel_get_drm_devid(data.fd);

if (IS_GEN2(data.devid)) /* chipset only handles cached -> 
uncached */
@@ -162,7 +163,8 @@ igt_main
scratch_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,
   32, 0, I915_TILING_NONE, 0);
  
-		gem_set_caching(data.fd, scratch_buf->handle, 1);

+   if (!gem_has_lmem(data.fd))
+   gem_set_caching(data.fd, scratch_buf->handle, 1);
  
  		staging_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,

   32, 0, I915_TILING_NONE, 0);

Re: [Intel-gfx] [PATCH v2] drm/i915: Fix race in __i915_vma_remove_closed

[Tvrtko Ursulin]

On 20/04/2022 10:57, Karol Herbst wrote:

i915_vma_reopen checked if the vma is closed before without taking the
lock. So multiple threads could attempt removing the vma.

Instead the lock needs to be taken before actually checking.

v2: move struct declaration

Cc: Chris Wilson 
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5732
Signed-off-by: Karol Herbst 


Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko


---
  drivers/gpu/drm/i915/i915_vma.c | 11 +++
  1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 162e8d83691b..2efdad2b43fa 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1615,17 +1615,17 @@ void i915_vma_close(struct i915_vma *vma)
  
  static void __i915_vma_remove_closed(struct i915_vma *vma)

  {
-   struct intel_gt *gt = vma->vm->gt;
-
-   spin_lock_irq(>->closed_lock);
list_del_init(&vma->closed_link);
-   spin_unlock_irq(>->closed_lock);
  }
  
  void i915_vma_reopen(struct i915_vma *vma)

  {
+   struct intel_gt *gt = vma->vm->gt;
+
+   spin_lock_irq(>->closed_lock);
if (i915_vma_is_closed(vma))
__i915_vma_remove_closed(vma);
+   spin_unlock_irq(>->closed_lock);
  }
  
  static void force_unbind(struct i915_vma *vma)

@@ -1641,6 +1641,7 @@ static void force_unbind(struct i915_vma *vma)
  static void release_references(struct i915_vma *vma, bool vm_ddestroy)
  {
struct drm_i915_gem_object *obj = vma->obj;
+   struct intel_gt *gt = vma->vm->gt;
  
  	GEM_BUG_ON(i915_vma_is_active(vma));
  
@@ -1651,7 +1652,9 @@ static void release_references(struct i915_vma *vma, bool vm_ddestroy)
  
  	spin_unlock(&obj->vma.lock);
  
+	spin_lock_irq(>->closed_lock);

__i915_vma_remove_closed(vma);
+   spin_unlock_irq(>->closed_lock);
  
  	if (vm_ddestroy)

i915_vm_resv_put(vma->vm);

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix race in __i915_vma_remove_closed (rev4)

[Tvrtko Ursulin]

On 04/05/2022 14:30, Patchwork wrote:

*Patch Details*
*Series:*   drm/i915: Fix race in __i915_vma_remove_closed (rev4)
*URL:*	https://patchwork.freedesktop.org/series/102845/ 


*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102845v4/index.html 




  CI Bug Log - changes from CI_DRM_11597_full -> Patchwork_102845v4_full


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_102845v4_full absolutely 
need to be

verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_102845v4_full, please notify your bug team to 
allow them

to document this new failure mode, which will reduce false positives in CI.


Participating hosts (13 -> 13)

No changes in participating hosts


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_102845v4_full:



  IGT changes


Possible regressions

  *

igt@gem_ctx_persistence@engines-hostile@vecs0:

  o shard-apl: PASS


-> FAIL


  *

{igt@kms_concurrent@pipe-a@hdmi-a-3} (NEW):

  o {shard-dg1}: NOTRUN -> CRASH




Neither failure is new - will merge.

Regards,

Tvrtko



Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *

igt@i915_pm_rpm@cursor-dpms:

  o {shard-rkl}: NOTRUN -> INCOMPLETE


  *

igt@i915_pm_rpm@system-suspend-devices:

  o {shard-dg1}: NOTRUN -> INCOMPLETE


+1 similar issue
  *

igt@i915_selftest@live@hangcheck:

  o {shard-rkl}: NOTRUN -> DMESG-FAIL




New tests

New tests have been introduced between CI_DRM_11597_full and 
Patchwork_102845v4_full:



  New IGT tests (1)

  * igt@kms_concurrent@pipe-a@hdmi-a-3:
  o Statuses : 1 crash(s)
  o Exec time: [0.03] s


Known issues

Here are the changes found in Patchwork_102845v4_full that come from 
known issues:



  IGT changes


Issues hit

  *

igt@gem_eio@unwedge-stress:

  o shard-skl: PASS


-> TIMEOUT


(i915#3063 )
  *

igt@gem_exec_fair@basic-none-vip@rcs0:

  o shard-kbl: PASS


-> FAIL


(i915#2842
) +2
similar issues
  *

igt@gem_exec_fair@basic-none@vecs0:

  o shard-glk: PASS


-> FAIL


(i915#2842 )
  *

igt@gem_exec_fair@basic-pace@bcs0:

  o shard-tglb: PASS


-> FAIL


(i915#2842 )
  *

igt@gem_exec_fair@basic-pace@vcs1:

  o shard-iclb: NOTRUN -> FAIL


(i915#2842 )
  *

igt@gem_flink_race@flink_close:

  o shard-iclb: PASS


-> FAIL

[Intel-gfx] [PATCH i-g-t 1/2] tests/i915/gem_caching: handle discrete

[Matthew Auld]

Test should still be valid, even if we can't explicitly control the PTE
caching bits, like on discrete, where the caching should already be
enabled by default for system memory objects.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/4873
Signed-off-by: Matthew Auld 
Cc: Nirmoy Das 
---
 tests/i915/gem_caching.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/tests/i915/gem_caching.c b/tests/i915/gem_caching.c
index 4e844952..eb0170ab 100644
--- a/tests/i915/gem_caching.c
+++ b/tests/i915/gem_caching.c
@@ -147,7 +147,8 @@ igt_main
 
igt_require_gem(data.fd);
gem_require_blitter(data.fd);
-   gem_require_caching(data.fd);
+   if (!gem_has_lmem(data.fd))
+   gem_require_caching(data.fd);
 
data.devid = intel_get_drm_devid(data.fd);
if (IS_GEN2(data.devid)) /* chipset only handles cached -> 
uncached */
@@ -162,7 +163,8 @@ igt_main
scratch_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,
   32, 0, I915_TILING_NONE, 0);
 
-   gem_set_caching(data.fd, scratch_buf->handle, 1);
+   if (!gem_has_lmem(data.fd))
+   gem_set_caching(data.fd, scratch_buf->handle, 1);
 
staging_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,
   32, 0, I915_TILING_NONE, 0);
-- 
2.34.1

[Intel-gfx] [PATCH i-g-t 2/2] tests/i915/gem_workarounds: handle discrete

[Matthew Auld]

On discrete the object should already be using I915_CACHING_CACHED, by
default, for system memory objects, although we can no longer explicitly
control the PTE caching bits.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/4873
Signed-off-by: Matthew Auld 
Cc: Nirmoy Das 
---
 tests/i915/gem_workarounds.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
index 3d185127..70967b3f 100644
--- a/tests/i915/gem_workarounds.c
+++ b/tests/i915/gem_workarounds.c
@@ -107,7 +107,8 @@ static int workaround_fail_count(int i915, const 
intel_ctx_t *ctx)
 
memset(obj, 0, sizeof(obj));
obj[0].handle = gem_create(i915, result_sz);
-   gem_set_caching(i915, obj[0].handle, I915_CACHING_CACHED);
+   if (!gem_has_lmem(i915))
+   gem_set_caching(i915, obj[0].handle, I915_CACHING_CACHED);
obj[1].handle = gem_create(i915, batch_sz);
obj[1].relocs_ptr = to_user_pointer(reloc);
obj[1].relocation_count = !ahnd ? num_wa_regs : 0;
-- 
2.34.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev2)
URL   : https://patchwork.freedesktop.org/series/103491/
State : warning

== Summary ==

Error: dim checkpatch failed
e071bdd7839d drm/i915: Split shared dpll .get_dplls() into compute and get 
phases
-:194: CHECK:CAMELCASE: Avoid CamelCase: 
#194: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+   SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;

total: 0 errors, 0 warnings, 1 checks, 516 lines checked
c986a8eec081 drm/i915: Do .crtc_compute_clock() earlier
af15247e6cc6 drm/i915: Clean up DPLL related debugs
5524d78e52c7 drm/i915: Reassign DPLLs only for crtcs going throug 
.compute_config()
19a1131cf0b7 drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible 
side-effects?
#21: FILE: drivers/gpu/drm/i915/display/intel_display.c:6076:
+#define PIPE_CONF_CHECK_TIMINGS(name) do { \
+   PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
+   PIPE_CONF_CHECK_I(name.crtc_htotal); \
+   PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
+   PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
+   PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
+   PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
+   PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
+   PIPE_CONF_CHECK_I(name.crtc_vtotal); \
+   PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
+   PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
+   PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
+   PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 63 lines checked
f124e0c495ef drm/i915: Extract PIPE_CONF_CHECK_RECT()
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible 
side-effects?
#21: FILE: drivers/gpu/drm/i915/display/intel_display.c:6091:
+#define PIPE_CONF_CHECK_RECT(name) do { \
+   PIPE_CONF_CHECK_I(name.x1); \
+   PIPE_CONF_CHECK_I(name.x2); \
+   PIPE_CONF_CHECK_I(name.y1); \
+   PIPE_CONF_CHECK_I(name.y2); \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 40 lines checked
bf14ee24645d drm/i915: Adjust intel_modeset_pipe_config() & co. calling 
convention
-:81: CHECK:SPACING: No space is necessary after a cast
#81: FILE: drivers/gpu/drm/i915/display/intel_display.c:5649:
+   pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;

total: 0 errors, 0 warnings, 1 checks, 127 lines checked
9c1f612c7a53 drm/i915: s/pipe_config/crtc_state/
-:92: CHECK:SPACING: No space is necessary after a cast
#92: FILE: drivers/gpu/drm/i915/display/intel_display.c:5649:
+   crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;

-:190: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_display.c:5767:
+   crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
   ^

total: 0 errors, 0 warnings, 2 checks, 169 lines checked
0b3d6909d086 drm/i915: Improve modeset debugs
a34799f2c9d5 drm/i915: Extract intel_crtc_dotclock()
ca638562f4a7 drm/i915: Introduce struct iclkip_params
3d3e8c895f11 drm/i915: Feed the DPLL output freq back into crtc_state
-:36: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#36: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:933:
+int intel_crtc_dotclock(const struct intel_crtc_state *crtc_state);

-:181: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#181: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1460:
+int intel_calculate_dotclock(const struct intel_crtc_state *crtc_state);

total: 0 errors, 2 warnings, 0 checks, 261 lines checked
daeb16028fe9 drm/i915: Compute clocks earlier
da303a89e10e drm/i915: Skip FDI vs. dotclock sanity check during readout
2d347b951e01 drm/i915: Make M/N checks non-fuzzy
a758ec2669c5 drm/i915: Make all clock checks non-fuzzy
9796263531df drm/i915: Set active dpll early for icl+
5eeb6716be8f drm/i915: Nuke fastet state copy hacks
4afe7158b868 drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not 
enabled
5e4f5952612c drm/i915: Check hw.enable and hw.active in 
intel_pipe_config_compare()
5f9c7c33e952 drm/i915: Add intel_panel_highest_mode()
a83f45006a03 drm/i915: Allow M/N change during fastset on bdw+
ce552dfa0ce1 drm/i915: Require an exact DP link freq match for the DG2 PLL
36dcfffc51fd drm/i915: Use a fixed N value always
fe0376ddca68 drm/i915: Round to closest in M/N calculations
f82c7d74a445 drm/i915: Round TMDS clock to nearest