Re: [Intel-gfx] [PATCH v17 1/1] drm/i915: Allow user to set cache at BO creation
> -Original Message-
> From: Andi Shyti
> Sent: Wednesday, June 7, 2023 1:11 PM
> To: Zhang, Carl
> Cc: Andi Shyti ; Joonas Lahtinen
> ; Tvrtko Ursulin
> ; Yang, Fei ; Chris
> Wilson ; Roper, Matthew D
> ; Justen, Jordan L ;
> Gu, Lihao ; Intel GFX ;
> DRI Devel
> Subject: Re: [PATCH v17 1/1] drm/i915: Allow user to set cache at BO creation
>
> Hi Carl,
>
> On Wed, Jun 07, 2023 at 03:40:20AM +, Zhang, Carl wrote:
> > Media driver reverted previous patches, and file a new PR
> > https://github.com/intel/media-driver/pull/1680
> > will hold this PR until the uapi changes appear in drm_next.
>
> That's great, thanks a lot for the quick actions here.
>
> Before pushing I am going to replace the Media part in the commit log with
> the following sentence:
>
> "
> The media driver supprt has bin submitted in this merge request:
> https://github.com/intel/media-driver/pull/1680
> "
>
> > besides this, ask a dumb question.
> > How we retrieve the pat_index from a shared resource though dma_buf fd?
> > maybe we need to know whether it could be CPU cached if we want map it.
> > Of course, looks there are no real usage to access it though CPU.
> > Just use it directly without any pat related options ?
>
> I am not understanding. Do you want to ask the PAT table to the driver? Are
> you referring to the CPU PAT index?
>
> In any case, if I understood correctly, you don't necessarily always need to
> set the PAT options and the cache options will fall into the default values.
>
> Please let me know if I haven't answered the question.
>
If mesa create a resource , then use DRM_IOCTL_PRIME_HANDLE_TO_FD convert it to
a dma fd.
Then share it to media, media use DRM_IOCTL_PRIME_FD_TO_HANDLE convert it to a
gem bo.
But media does not know the PAT index , because mesa create it and set it.
So, if media want to call DRM_IOCTL_I915_GEM_MMAP_OFFSET, media does not know
whether it could be WB.
> Andi
>
> > Thanks
> > Carl
> >
> > > -Original Message-
> > > From: Andi Shyti
> > > Sent: Tuesday, June 6, 2023 7:15 PM
> > > To: Joonas Lahtinen
> > > Cc: Andi Shyti ; Tvrtko Ursulin
> > > ; Yang, Fei ;
> > > Chris Wilson ; Roper, Matthew D
> > > ; Justen, Jordan L
> > > ; Zhang, Carl ; Gu,
> > > Lihao ; Intel GFX
> > > ; DRI Devel > > de...@lists.freedesktop.org>
> > > Subject: Re: [PATCH v17 1/1] drm/i915: Allow user to set cache at BO
> > > creation
> > >
> > > > > > > To comply with the design that buffer objects shall have
> > > > > > > immutable cache setting through out their life cycle, {set,
> > > > > > > get}_caching ioctl's are no longer supported from MTL onward.
> > > > > > > With that change caching policy can only be set at object
> > > > > > > creation time. The current code applies a default (platform
> > > > > > > dependent)
> > > cache setting for all objects.
> > > > > > > However this is not optimal for performance tuning. The
> > > > > > > patch extends the existing gem_create uAPI to let user set
> > > > > > > PAT index for the object at creation time.
> > > > > > > The new extension is platform independent, so UMD's can
> > > > > > > switch to using this extension for older platforms as well,
> > > > > > > while {set, get}_caching are still supported on these legacy
> > > > > > > paltforms for
> > > compatibility reason.
> > > > > > > However, since PAT index was not clearly defined for
> > > > > > > platforms prior to
> > > > > > > GEN12 (TGL), so we are limiting this externsion to GEN12+
> > > > > > > platforms only. See ext_set_pat() in for the implementation
> > > > > > > details.
> > > > > > >
> > > > > > > Note: The documentation related to the PAT/MOCS tables is
> > > > > > > currently available for Tiger Lake here:
> > > > > > > https://www.intel.com/content/www/us/en/docs/graphics-for-li
> > > > > > > nux/ developer-reference/1-0/tiger-lake.html
> > > > > > >
> > > > > > > BSpec: 45101
> > > > > > >
> > > > > > > Mesa support has been submitted in this merge request:
> > > > > > > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22
> > > > > > > 878
> > > > > > >
> > > > > > > The media driver is supported by the following commits:
> > > > > > > https://github.com/intel/media-
> > > driver/commit/92c00a857433ebb34ec
> > > > > > > 575e9834f473c6fcb6341
> > > > > > > https://github.com/intel/media-driver/commit/fd375cf2c5e1f6b
> > > > > > > f6b4
> > > > > > > 3258ff797b3134aadc9fd
> > > > > > > https://github.com/intel/media-
> > > driver/commit/08dd244b22484770a33
> > > > > > > 464c2c8ae85430e548000
> > > >
> > > > Andi, let's still get these corrected before merging once the
> > > > media-driver revert is completed.
> > >
> > > Sure!
> > >
> > > At least this doesn't need a new version to be respinned.
> > >
> > > Please, Carl, link the new pull request and I will update the commit log.
> > >
> > > Andi
Re: [Intel-gfx] [PATCH v17 1/1] drm/i915: Allow user to set cache at BO creation
Hi Carl,
On Wed, Jun 07, 2023 at 03:40:20AM +, Zhang, Carl wrote:
> Media driver reverted previous patches, and file a new PR
> https://github.com/intel/media-driver/pull/1680
> will hold this PR until the uapi changes appear in drm_next.
That's great, thanks a lot for the quick actions here.
Before pushing I am going to replace the Media part in the commit
log with the following sentence:
"
The media driver supprt has bin submitted in this merge request:
https://github.com/intel/media-driver/pull/1680
"
> besides this, ask a dumb question.
> How we retrieve the pat_index from a shared resource though dma_buf fd?
> maybe we need to know whether it could be CPU cached if we want map it.
> Of course, looks there are no real usage to access it though CPU.
> Just use it directly without any pat related options ?
I am not understanding. Do you want to ask the PAT table to the
driver? Are you referring to the CPU PAT index?
In any case, if I understood correctly, you don't necessarily
always need to set the PAT options and the cache options will
fall into the default values.
Please let me know if I haven't answered the question.
Andi
> Thanks
> Carl
>
> > -Original Message-
> > From: Andi Shyti
> > Sent: Tuesday, June 6, 2023 7:15 PM
> > To: Joonas Lahtinen
> > Cc: Andi Shyti ; Tvrtko Ursulin
> > ; Yang, Fei ; Chris
> > Wilson ; Roper, Matthew D
> > ; Justen, Jordan L ;
> > Zhang, Carl ; Gu, Lihao ; Intel
> > GFX ; DRI Devel > de...@lists.freedesktop.org>
> > Subject: Re: [PATCH v17 1/1] drm/i915: Allow user to set cache at BO
> > creation
> >
> > > > > > To comply with the design that buffer objects shall have
> > > > > > immutable cache setting through out their life cycle, {set,
> > > > > > get}_caching ioctl's are no longer supported from MTL onward.
> > > > > > With that change caching policy can only be set at object
> > > > > > creation time. The current code applies a default (platform
> > > > > > dependent)
> > cache setting for all objects.
> > > > > > However this is not optimal for performance tuning. The patch
> > > > > > extends the existing gem_create uAPI to let user set PAT index
> > > > > > for the object at creation time.
> > > > > > The new extension is platform independent, so UMD's can switch
> > > > > > to using this extension for older platforms as well, while {set,
> > > > > > get}_caching are still supported on these legacy paltforms for
> > compatibility reason.
> > > > > > However, since PAT index was not clearly defined for platforms
> > > > > > prior to
> > > > > > GEN12 (TGL), so we are limiting this externsion to GEN12+
> > > > > > platforms only. See ext_set_pat() in for the implementation details.
> > > > > >
> > > > > > Note: The documentation related to the PAT/MOCS tables is
> > > > > > currently available for Tiger Lake here:
> > > > > > https://www.intel.com/content/www/us/en/docs/graphics-for-linux/
> > > > > > developer-reference/1-0/tiger-lake.html
> > > > > >
> > > > > > BSpec: 45101
> > > > > >
> > > > > > Mesa support has been submitted in this merge request:
> > > > > > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
> > > > > >
> > > > > > The media driver is supported by the following commits:
> > > > > > https://github.com/intel/media-
> > driver/commit/92c00a857433ebb34ec
> > > > > > 575e9834f473c6fcb6341
> > > > > > https://github.com/intel/media-driver/commit/fd375cf2c5e1f6bf6b4
> > > > > > 3258ff797b3134aadc9fd
> > > > > > https://github.com/intel/media-
> > driver/commit/08dd244b22484770a33
> > > > > > 464c2c8ae85430e548000
> > >
> > > Andi, let's still get these corrected before merging once the
> > > media-driver revert is completed.
> >
> > Sure!
> >
> > At least this doesn't need a new version to be respinned.
> >
> > Please, Carl, link the new pull request and I will update the commit log.
> >
> > Andi
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mtl: Add new vswing table for C20 phy to support DP 1.4
== Series Details == Series: drm/i915/mtl: Add new vswing table for C20 phy to support DP 1.4 URL : https://patchwork.freedesktop.org/series/118925/ State : success == Summary == CI Bug Log - changes from CI_DRM_13236_full -> Patchwork_118925v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (7 -> 7) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_118925v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-hang: - shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-snb6/igt@gem_ctx_persiste...@engines-hang.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][2] -> [FAIL][3] ([i915#2842]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/shard-glk5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-glk1/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-glk9/igt@gem_lmem_swapp...@heavy-verify-random-ccs.html * igt@gem_lmem_swapping@parallel-random-verify-ccs: - shard-apl: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-apl2/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html * igt@gem_ppgtt@blt-vs-render-ctxn: - shard-snb: [PASS][6] -> [FAIL][7] ([i915#8295]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/shard-snb1/igt@gem_pp...@blt-vs-render-ctxn.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-snb1/igt@gem_pp...@blt-vs-render-ctxn.html * igt@gen9_exec_parse@allowed-single: - shard-glk: [PASS][8] -> [ABORT][9] ([i915#5566]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/shard-glk1/igt@gen9_exec_pa...@allowed-single.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-glk2/igt@gen9_exec_pa...@allowed-single.html * igt@kms_big_fb@y-tiled-64bpp-rotate-180: - shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271]) +36 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-snb6/igt@kms_big...@y-tiled-64bpp-rotate-180.html * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#3886]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-glk9/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#3886]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-apl2/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271]) +38 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-apl2/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs.html * igt@kms_cursor_crc@cursor-offscreen-max-size: - shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4579]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-apl2/igt@kms_cursor_...@cursor-offscreen-max-size.html * igt@kms_cursor_crc@cursor-random-32x10: - shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4579]) +6 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-glk9/igt@kms_cursor_...@cursor-random-32x10.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-apl: [PASS][16] -> [FAIL][17] ([i915#2346]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/shard-apl2/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-apl2/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1: - shard-glk: NOTRUN -> [FAIL][18] ([i915#2122]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/shard-glk9/igt@kms_flip@flip-vs-expired-vbl...@a-hdmi-a1.html * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-1: - shard-snb: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4579]) +9 similar issues [19]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mtl: update DP 2.0 vswing table for C20 phy
== Series Details == Series: drm/i915/mtl: update DP 2.0 vswing table for C20 phy URL : https://patchwork.freedesktop.org/series/118924/ State : success == Summary == CI Bug Log - changes from CI_DRM_13236_full -> Patchwork_118924v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (7 -> 7) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_118924v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-hang: - shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-snb1/igt@gem_ctx_persiste...@engines-hang.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][2] -> [FAIL][3] ([i915#2842]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/shard-glk5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-glk4/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-glk8/igt@gem_lmem_swapp...@heavy-verify-random-ccs.html * igt@gem_lmem_swapping@parallel-random-verify-ccs: - shard-apl: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-apl7/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html * igt@kms_big_fb@y-tiled-64bpp-rotate-180: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271]) +42 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-snb1/igt@kms_big...@y-tiled-64bpp-rotate-180.html * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#3886]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-glk8/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3886]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-apl7/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271]) +38 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-apl7/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs.html * igt@kms_cursor_crc@cursor-offscreen-max-size: - shard-apl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4579]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-apl7/igt@kms_cursor_...@cursor-offscreen-max-size.html * igt@kms_cursor_crc@cursor-random-32x10: - shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4579]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-glk8/igt@kms_cursor_...@cursor-random-32x10.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-apl: [PASS][12] -> [ABORT][13] ([i915#180]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/shard-apl1/igt@kms_fbcon_...@fbc-suspend.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-apl1/igt@kms_fbcon_...@fbc-suspend.html * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1: - shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271]) +45 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-glk8/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0...@pipe-a-hdmi-a-1.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-1: - shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4579]) +12 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-snb1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0...@pipe-b-hdmi-a-1.html * igt@kms_psr2_sf@overlay-plane-move-continuous-sf: - shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-apl7/igt@kms_psr2...@overlay-plane-move-continuous-sf.html * igt@kms_psr2_su@frontbuffer-xrgb: - shard-glk: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#658]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/shard-glk8/igt@kms_psr2...@frontbuffer-xrgb.html Possible fixes *
Re: [Intel-gfx] [PATCH v17 1/1] drm/i915: Allow user to set cache at BO creation
Media driver reverted previous patches, and file a new PR
https://github.com/intel/media-driver/pull/1680
will hold this PR until the uapi changes appear in drm_next.
besides this, ask a dumb question.
How we retrieve the pat_index from a shared resource though dma_buf fd?
maybe we need to know whether it could be CPU cached if we want map it.
Of course, looks there are no real usage to access it though CPU.
Just use it directly without any pat related options ?
Thanks
Carl
> -Original Message-
> From: Andi Shyti
> Sent: Tuesday, June 6, 2023 7:15 PM
> To: Joonas Lahtinen
> Cc: Andi Shyti ; Tvrtko Ursulin
> ; Yang, Fei ; Chris
> Wilson ; Roper, Matthew D
> ; Justen, Jordan L ;
> Zhang, Carl ; Gu, Lihao ; Intel
> GFX ; DRI Devel de...@lists.freedesktop.org>
> Subject: Re: [PATCH v17 1/1] drm/i915: Allow user to set cache at BO creation
>
> > > > > To comply with the design that buffer objects shall have
> > > > > immutable cache setting through out their life cycle, {set,
> > > > > get}_caching ioctl's are no longer supported from MTL onward.
> > > > > With that change caching policy can only be set at object
> > > > > creation time. The current code applies a default (platform dependent)
> cache setting for all objects.
> > > > > However this is not optimal for performance tuning. The patch
> > > > > extends the existing gem_create uAPI to let user set PAT index
> > > > > for the object at creation time.
> > > > > The new extension is platform independent, so UMD's can switch
> > > > > to using this extension for older platforms as well, while {set,
> > > > > get}_caching are still supported on these legacy paltforms for
> compatibility reason.
> > > > > However, since PAT index was not clearly defined for platforms
> > > > > prior to
> > > > > GEN12 (TGL), so we are limiting this externsion to GEN12+
> > > > > platforms only. See ext_set_pat() in for the implementation details.
> > > > >
> > > > > Note: The documentation related to the PAT/MOCS tables is
> > > > > currently available for Tiger Lake here:
> > > > > https://www.intel.com/content/www/us/en/docs/graphics-for-linux/
> > > > > developer-reference/1-0/tiger-lake.html
> > > > >
> > > > > BSpec: 45101
> > > > >
> > > > > Mesa support has been submitted in this merge request:
> > > > > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
> > > > >
> > > > > The media driver is supported by the following commits:
> > > > > https://github.com/intel/media-
> driver/commit/92c00a857433ebb34ec
> > > > > 575e9834f473c6fcb6341
> > > > > https://github.com/intel/media-driver/commit/fd375cf2c5e1f6bf6b4
> > > > > 3258ff797b3134aadc9fd
> > > > > https://github.com/intel/media-
> driver/commit/08dd244b22484770a33
> > > > > 464c2c8ae85430e548000
> >
> > Andi, let's still get these corrected before merging once the
> > media-driver revert is completed.
>
> Sure!
>
> At least this doesn't need a new version to be respinned.
>
> Please, Carl, link the new pull request and I will update the commit log.
>
> Andi
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Allow user to set cache at BO creation
== Series Details == Series: drm/i915: Allow user to set cache at BO creation URL : https://patchwork.freedesktop.org/series/118921/ State : success == Summary == CI Bug Log - changes from CI_DRM_13236_full -> Patchwork_118921v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (7 -> 7) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_118921v1_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@engines-hang: - shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-snb2/igt@gem_ctx_persiste...@engines-hang.html * igt@gem_eio@in-flight-suspend: - shard-snb: [PASS][2] -> [DMESG-WARN][3] ([i915#5090]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/shard-snb4/igt@gem_...@in-flight-suspend.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-snb2/igt@gem_...@in-flight-suspend.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-glk: [PASS][4] -> [FAIL][5] ([i915#2842]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/shard-glk5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-glk5/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-glk9/igt@gem_lmem_swapp...@heavy-verify-random-ccs.html * igt@gem_lmem_swapping@parallel-random-verify-ccs: - shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-apl7/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html * igt@gem_userptr_blits@huge-split: - shard-snb: [PASS][10] -> [FAIL][11] ([i915#2724]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/shard-snb5/igt@gem_userptr_bl...@huge-split.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-snb2/igt@gem_userptr_bl...@huge-split.html * igt@i915_module_load@reload-with-fault-injection: - shard-snb: [PASS][12] -> [ABORT][13] ([i915#4528]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/shard-snb4/igt@i915_module_l...@reload-with-fault-injection.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-snb1/igt@i915_module_l...@reload-with-fault-injection.html * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3886]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-glk5/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3886]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-apl6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-missing-ccs-buffer-4_tiled_mtl_rc_ccs: - shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271]) +50 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-snb4/igt@kms_ccs@pipe-c-missing-ccs-buffer-4_tiled_mtl_rc_ccs.html * igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271]) +38 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-apl2/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs.html * igt@kms_cursor_crc@cursor-offscreen-max-size: - shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4579]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-apl4/igt@kms_cursor_...@cursor-offscreen-max-size.html * igt@kms_cursor_crc@cursor-random-32x10: - shard-glk: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4579]) +6 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/shard-glk2/igt@kms_cursor_...@cursor-random-32x10.html * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-hdmi-a-1: - shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271] /
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/i915/gem_ctx_persistence: Skip some subtests
On 6/1/2023 12:55 PM, Andrzej Hajda wrote:
On 24.05.2023 21:19, Vinay Belgaumkar wrote:
Hang and heartbeat subtests are not supported with GuC submission
enabled.
Signed-off-by: Vinay Belgaumkar
---
tests/i915/gem_ctx_persistence.c | 32 +++-
1 file changed, 19 insertions(+), 13 deletions(-)
diff --git a/tests/i915/gem_ctx_persistence.c
b/tests/i915/gem_ctx_persistence.c
index 42cf96329..1e122535e 100644
--- a/tests/i915/gem_ctx_persistence.c
+++ b/tests/i915/gem_ctx_persistence.c
@@ -1366,19 +1366,25 @@ igt_main
igt_subtest("hostile")
test_nohangcheck_hostile(i915, _cfg);
- igt_subtest("hang")
- test_nohangcheck_hang(i915, _cfg);
-
- igt_subtest("heartbeat-stop")
- test_noheartbeat_many(i915, 1, 0);
- igt_subtest("heartbeat-hang")
- test_noheartbeat_many(i915, 1, IGT_SPIN_NO_PREEMPTION);
- igt_subtest("heartbeat-many")
- test_noheartbeat_many(i915, 16, 0);
- igt_subtest("heartbeat-close")
- test_noheartbeat_close(i915, 0);
- igt_subtest("heartbeat-hostile")
- test_noheartbeat_close(i915, IGT_SPIN_NO_PREEMPTION);
+
+ igt_subtest_group {
+ igt_fixture
+ igt_skip_on(gem_using_guc_submission(i915));
As Kamil said this should be put into test function.
Otherwise you will have misleading errors in other tests - fixture
will be called always regardless of running test.
+
+ igt_subtest("hang")
+ test_nohangcheck_hang(i915, _cfg);
What is 'missing' in GuC in case of this test? CI is happy :)
For now. I have seen this fail before, so better to skip. I have sent
out a patch with a skip for just this one since all others have been
taken care of.
https://patchwork.freedesktop.org/patch/541407/
Thanks,
Vinay.
+
+ igt_subtest("heartbeat-stop")
+ test_noheartbeat_many(i915, 1, 0);
+ igt_subtest("heartbeat-hang")
+ test_noheartbeat_many(i915, 1, IGT_SPIN_NO_PREEMPTION);
+ igt_subtest("heartbeat-many")
+ test_noheartbeat_many(i915, 16, 0);
+ igt_subtest("heartbeat-close")
+ test_noheartbeat_close(i915, 0);
+ igt_subtest("heartbeat-hostile")
+ test_noheartbeat_close(i915, IGT_SPIN_NO_PREEMPTION);
These tests are handled already by recently merged:
https://patchwork.freedesktop.org/patch/539647/?series=118423=3
Regards
Andrzej
+ }
igt_subtest_group {
igt_fixture
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Allow user to set cache at BO creation
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation
URL : https://patchwork.freedesktop.org/series/118913/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13235_full -> Patchwork_118913v1_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_118913v1_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_118913v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (8 -> 8)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118913v1_full:
### IGT changes ###
Warnings
* igt@gem_create@create-ext-set-pat:
- shard-glk: [SKIP][1] ([fdo#109271]) -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-glk1/igt@gem_cre...@create-ext-set-pat.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/shard-glk6/igt@gem_cre...@create-ext-set-pat.html
- shard-snb: [SKIP][3] ([fdo#109271]) -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-snb1/igt@gem_cre...@create-ext-set-pat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/shard-snb4/igt@gem_cre...@create-ext-set-pat.html
- shard-apl: [SKIP][5] ([fdo#109271]) -> [FAIL][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-apl6/igt@gem_cre...@create-ext-set-pat.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/shard-apl6/igt@gem_cre...@create-ext-set-pat.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_capture@capture@rcs0-lmem0:
- {shard-dg1}:[PASS][7] -> [DMESG-WARN][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-dg1-14/igt@gem_exec_capture@capt...@rcs0-lmem0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/shard-dg1-12/igt@gem_exec_capture@capt...@rcs0-lmem0.html
* igt@gem_exec_capture@capture@rcs0-smem:
- {shard-dg1}:[PASS][9] -> [ABORT][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-dg1-14/igt@gem_exec_capture@capt...@rcs0-smem.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/shard-dg1-12/igt@gem_exec_capture@capt...@rcs0-smem.html
Known issues
Here are the changes found in Patchwork_118913v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: NOTRUN -> [FAIL][13] ([i915#2842])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/shard-glk9/igt@gem_exec_fair@basic-none-...@rcs0.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/shard-glk9/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][15] -> [ABORT][16] ([i915#5566])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-apl1/igt@gen9_exec_pa...@allowed-single.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/shard-apl7/igt@gen9_exec_pa...@allowed-single.html
* igt@kms_big_fb@linear-64bpp-rotate-0:
- shard-snb: [PASS][17] -> [SKIP][18] ([fdo#109271])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-snb1/igt@kms_big...@linear-64bpp-rotate-0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/shard-snb6/igt@kms_big...@linear-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][19] ([fdo#109271]) +16 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/shard-glk9/igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_mc_ccs.html
*
igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-glk: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4579])
[20]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix a NULL vs IS_ERR() bug
== Series Details ==
Series: drm/i915: Fix a NULL vs IS_ERR() bug
URL : https://patchwork.freedesktop.org/series/118907/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13235_full -> Patchwork_118907v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (8 -> 7)
--
Missing(1): shard-rkl0
Known issues
Here are the changes found in Patchwork_118907v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][1] -> [FAIL][2] ([i915#2842])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: NOTRUN -> [FAIL][3] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/shard-glk3/igt@gem_exec_fair@basic-none-...@rcs0.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/shard-glk3/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html
* igt@i915_suspend@forcewake:
- shard-apl: [PASS][5] -> [ABORT][6] ([i915#180])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-apl3/igt@i915_susp...@forcewake.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/shard-apl6/igt@i915_susp...@forcewake.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271]) +16 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/shard-glk3/igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_mc_ccs.html
*
igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4579])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/shard-glk3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscal...@pipe-a-valid-mode.html
* igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
- shard-apl: [PASS][9] -> [FAIL][10] ([i915#1188])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-apl2/igt@kms_hdr@bpc-switch-d...@pipe-a-dp-1.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/shard-apl1/igt@kms_hdr@bpc-switch-d...@pipe-a-dp-1.html
*
igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4579]) +11
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/shard-snb7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-...@pipe-b-vga-1.html
*
igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271]) +17 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/shard-snb1/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scal...@pipe-a-hdmi-a-1.html
Possible fixes
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- {shard-rkl}:[FAIL][13] ([i915#7742]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-rkl-3/igt@drm_fdinfo@most-busy-check-...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/shard-rkl-2/igt@drm_fdinfo@most-busy-check-...@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][15] ([i915#2842]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- {shard-rkl}:[FAIL][17] ([i915#2842]) -> [PASS][18] +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-rkl-3/igt@gem_exec_fair@basic-p...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/shard-rkl-2/igt@gem_exec_fair@basic-p...@rcs0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- {shard-dg1}:[DMESG-WARN][19] ([i915#4936] / [i915#5493]) ->
[PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13235/shard-dg1-13/igt@gem_lmem_swapping@smem-...@lmem0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/shard-dg1-13/igt@gem_lmem_swapping@smem-...@lmem0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [ABORT][21] ([i915#5566]) -> [PASS][22]
[21]:
[Intel-gfx] ✓ Fi.CI.BAT: success for Avoid reading OA reports before they land (rev2)
== Series Details ==
Series: Avoid reading OA reports before they land (rev2)
URL : https://patchwork.freedesktop.org/series/118886/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13238 -> Patchwork_118886v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v2/index.html
Participating hosts (41 -> 39)
--
Missing(2): bat-rpls-2 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_118886v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][1] -> [ABORT][2] ([i915#7911] / [i915#7913])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v2/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-adlm-1: NOTRUN -> [SKIP][3] ([i915#7828])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v2/bat-adlm-1/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlm-1: NOTRUN -> [SKIP][4] ([i915#1845])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v2/bat-adlm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html
Possible fixes
* igt@i915_selftest@live@workarounds:
- bat-adlm-1: [INCOMPLETE][5] ([i915#4983] / [i915#7677]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v2/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
Warnings
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [SKIP][7] ([i915#3555] / [i915#4579]) -> [ABORT][8]
([i915#4579] / [i915#8260])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v2/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260
Build changes
-
* Linux: CI_DRM_13238 -> Patchwork_118886v2
CI-20190529: 20190529
CI_DRM_13238: 8c0b302811d744b945dcb6d78164a76188914db9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7320: 1c96b08a4cde6f2d49824a8cc3303bd860617b52 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_118886v2: 8c0b302811d744b945dcb6d78164a76188914db9 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
eb3f1c965fb0 i915/perf: Do not add ggtt offset to hw_tail
a419e80343e6 i915/perf: Drop the aging_tail logic in perf OA
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118886v2/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Avoid reading OA reports before they land (rev2)
== Series Details == Series: Avoid reading OA reports before they land (rev2) URL : https://patchwork.freedesktop.org/series/118886/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp: Fix log level for "CDS interlane align done"
== Series Details == Series: drm/i915/dp: Fix log level for "CDS interlane align done" URL : https://patchwork.freedesktop.org/series/118977/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13238 -> Patchwork_118977v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_118977v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_118977v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118977v1/index.html Participating hosts (41 -> 39) -- Missing(2): bat-rpls-2 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_118977v1: ### IGT changes ### Possible regressions * igt@dmabuf@all-tests@dma_fence: - bat-dg1-5: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg1-5/igt@dmabuf@all-tests@dma_fence.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118977v1/bat-dg1-5/igt@dmabuf@all-tests@dma_fence.html * igt@dmabuf@all-tests@sanitycheck: - bat-dg1-5: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg1-5/igt@dmabuf@all-te...@sanitycheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118977v1/bat-dg1-5/igt@dmabuf@all-te...@sanitycheck.html * igt@gem_exec_basic@basic@bcs0-smem: - bat-adlp-9: [PASS][5] -> [ABORT][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlp-9/igt@gem_exec_basic@ba...@bcs0-smem.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118977v1/bat-adlp-9/igt@gem_exec_basic@ba...@bcs0-smem.html * igt@gem_exec_basic@basic@vecs0-smem: - bat-adlp-9: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlp-9/igt@gem_exec_basic@ba...@vecs0-smem.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118977v1/bat-adlp-9/igt@gem_exec_basic@ba...@vecs0-smem.html * igt@i915_suspend@basic-s3-without-i915: - bat-dg2-9: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-9/igt@i915_susp...@basic-s3-without-i915.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118977v1/bat-dg2-9/igt@i915_susp...@basic-s3-without-i915.html Known issues Here are the changes found in Patchwork_118977v1 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [PASS][11] -> [ABORT][12] ([i915#7913]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118977v1/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][13] -> [DMESG-FAIL][14] ([i915#5334]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118977v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#7828]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118977v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html - bat-adlm-1: NOTRUN -> [SKIP][16] ([i915#7828]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118977v1/bat-adlm-1/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@suspend-read-crc: - bat-adlm-1: NOTRUN -> [SKIP][17] ([i915#1845]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118977v1/bat-adlm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html Possible fixes * igt@i915_selftest@live@hangcheck: - bat-dg2-11: [ABORT][18] ([i915#7913] / [i915#7979]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118977v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@workarounds: - bat-adlm-1: [INCOMPLETE][20] ([i915#4983] / [i915#7677]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlm-1/igt@i915_selftest@l...@workarounds.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118977v1/bat-adlm-1/igt@i915_selftest@l...@workarounds.html Warnings * igt@kms_setmode@basic-clone-single-crtc:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gsc: Fix error code in intel_gsc_uc_heci_cmd_submit_nonpriv()
== Series Details ==
Series: drm/i915/gsc: Fix error code in intel_gsc_uc_heci_cmd_submit_nonpriv()
URL : https://patchwork.freedesktop.org/series/118906/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13234_full -> Patchwork_118906v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118906v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-smem0:
- {shard-dg1}:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-dg1-12/igt@i915_pm_rpm@gem-execbuf-str...@extra-wait-smem0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118906v1/shard-dg1-13/igt@i915_pm_rpm@gem-execbuf-str...@extra-wait-smem0.html
Known issues
Here are the changes found in Patchwork_118906v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [PASS][3] -> [ABORT][4] ([i915#7461] / [i915#8211])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-glk2/igt@gem_barrier_race@remote-requ...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118906v1/shard-glk7/igt@gem_barrier_race@remote-requ...@rcs0.html
* igt@gem_eio@in-flight-suspend:
- shard-apl: [PASS][5] -> [ABORT][6] ([i915#180])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-apl4/igt@gem_...@in-flight-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118906v1/shard-apl1/igt@gem_...@in-flight-suspend.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118906v1/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2346])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-glk5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118906v1/shard-glk4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#79])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vbl...@bc-hdmi-a1-hdmi-a2.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118906v1/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vbl...@bc-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-snb: [PASS][13] -> [SKIP][14] ([fdo#109271])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-snb1/igt@kms_frontbuffer_track...@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118906v1/shard-snb1/igt@kms_frontbuffer_track...@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4579]) +3
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118906v1/shard-snb1/igt@kms_plane_scaling@plane-upscale-with-modifiers-20...@pipe-b-hdmi-a-1.html
* igt@kms_tv_load_detect@load-detect:
- shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271]) +32 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118906v1/shard-snb5/igt@kms_tv_load_det...@load-detect.html
Possible fixes
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-rkl}:[FAIL][17] ([i915#6268]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-rkl-4/igt@gem_ctx_e...@basic-nohangcheck.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118906v1/shard-rkl-1/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_eio@reset-stress:
- {shard-dg1}:[FAIL][19] ([i915#5784]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-dg1-18/igt@gem_...@reset-stress.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118906v1/shard-dg1-19/igt@gem_...@reset-stress.html
* igt@gem_exec_fair@basic-none@vecs0:
- {shard-rkl}:[FAIL][21]
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/quirk: Add quirk for devices that cannot be dimmed
== Series Details ==
Series: drm/i915/quirk: Add quirk for devices that cannot be dimmed
URL : https://patchwork.freedesktop.org/series/118971/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13238 -> Patchwork_118971v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118971v1/index.html
Participating hosts (41 -> 39)
--
Missing(2): bat-rpls-2 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_118971v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][1] ([i915#7828])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118971v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
- bat-adlm-1: NOTRUN -> [SKIP][2] ([i915#7828])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118971v1/bat-adlm-1/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [PASS][3] -> [FAIL][4] ([i915#7932])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118971v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlm-1: NOTRUN -> [SKIP][5] ([i915#1845])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118971v1/bat-adlm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: [ABORT][6] ([i915#7913] / [i915#7979]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118971v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@workarounds:
- bat-adlm-1: [INCOMPLETE][8] ([i915#4983] / [i915#7677]) ->
[PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118971v1/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-dp-5:
- {bat-adlp-11}: [ABORT][10] -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-dp-5.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118971v1/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-dp-5.html
Warnings
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [SKIP][12] ([i915#3555] / [i915#4579]) -> [ABORT][13]
([i915#4579] / [i915#8260])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118971v1/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7953]: https://gitlab.freedesktop.org/drm/intel/issues/7953
[i915#7979]: https://gitlab.freedesktop.org/drm/intel/issues/7979
[i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260
Build changes
-
* Linux: CI_DRM_13238 -> Patchwork_118971v1
CI-20190529: 20190529
CI_DRM_13238:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/quirk: Add quirk for devices that cannot be dimmed
== Series Details == Series: drm/i915/quirk: Add quirk for devices that cannot be dimmed URL : https://patchwork.freedesktop.org/series/118971/ State : warning == Summary == Error: dim checkpatch failed 0241c698ef5c drm/i915/quirk: Add quirk for devices that cannot be dimmed -:33: CHECK:LINE_SPACING: Please don't use multiple blank lines #33: FILE: drivers/gpu/drm/i915/display/intel_backlight.c:1214: + total: 0 errors, 0 warnings, 1 checks, 76 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix a VMA UAF for multi-gt platform (rev2)
== Series Details ==
Series: drm/i915: Fix a VMA UAF for multi-gt platform (rev2)
URL : https://patchwork.freedesktop.org/series/118887/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13238 -> Patchwork_118887v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v2/index.html
Participating hosts (41 -> 39)
--
Missing(2): bat-rpls-2 fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118887v2:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_addfb_basic@small-bo:
- {bat-adlp-11}: [PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlp-11/igt@kms_addfb_ba...@small-bo.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v2/bat-adlp-11/igt@kms_addfb_ba...@small-bo.html
Known issues
Here are the changes found in Patchwork_118887v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][3] -> [ABORT][4] ([i915#7911] / [i915#7920] /
[i915#7982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-rpls-1/igt@i915_selftest@l...@requests.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v2/bat-rpls-1/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#7828])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v2/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
- bat-adlm-1: NOTRUN -> [SKIP][6] ([i915#7828])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v2/bat-adlm-1/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [PASS][7] -> [FAIL][8] ([i915#7932])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlm-1: NOTRUN -> [SKIP][9] ([i915#1845])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v2/bat-adlm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: [ABORT][10] ([i915#7913] / [i915#7979]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v2/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@workarounds:
- bat-adlm-1: [INCOMPLETE][12] ([i915#4983] / [i915#7677]) ->
[PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v2/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1:
- bat-dg2-8: [FAIL][14] ([i915#7932]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
Warnings
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [SKIP][16] ([i915#3555] / [i915#4579]) -> [ABORT][17]
([i915#4579] / [i915#8260])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v2/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: GSC FW support for MTL (rev3)
== Series Details ==
Series: drm/i915: GSC FW support for MTL (rev3)
URL : https://patchwork.freedesktop.org/series/117396/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13234_full -> Patchwork_117396v3_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_117396v3_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][1] -> [FAIL][2] ([i915#2842])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#2346])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-apl4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/shard-apl4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2346])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-glk5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/shard-glk3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#79]) +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ab-hdmi-a1-hdmi-a2.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@ab-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-snb: [PASS][11] -> [SKIP][12] ([fdo#109271])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-snb1/igt@kms_frontbuffer_track...@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/shard-snb6/igt@kms_frontbuffer_track...@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
- shard-apl: [PASS][13] -> [FAIL][14] ([i915#1188])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-apl2/igt@kms_hdr@bpc-switch-d...@pipe-a-dp-1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/shard-apl4/igt@kms_hdr@bpc-switch-d...@pipe-a-dp-1.html
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-20x20@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4579]) +7
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/shard-snb5/igt@kms_plane_scaling@plane-upscale-with-pixel-format-20...@pipe-b-vga-1.html
* igt@kms_tv_load_detect@load-detect:
- shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271]) +43 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/shard-snb4/igt@kms_tv_load_det...@load-detect.html
Possible fixes
* igt@gem_eio@reset-stress:
- {shard-dg1}:[FAIL][17] ([i915#5784]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-dg1-18/igt@gem_...@reset-stress.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/shard-dg1-12/igt@gem_...@reset-stress.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- {shard-rkl}:[FAIL][19] ([i915#2842]) -> [PASS][20] +1 similar
issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-rkl-1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117396v3/shard-rkl-3/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [FAIL][21] ([i915#2842]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-apl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[22]:
Re: [Intel-gfx] [PATCH] drm/i915/guc: Force a reset on internal GuC error
On 6/5/2023 1:54 PM, john.c.harri...@intel.com wrote:
From: John Harrison
If GuC hits an internal error (and survives long enough to report it
to the KMD), it is basically toast and will stop until a GT reset and
subsequent GuC reload is performed. Previously, the KMD just printed
an error message and then waited for the heartbeat to eventually kick
in and trigger a reset (assuming the heartbeat had not been disabled).
Instead, force the reset immediately to guarantee that it happens and
to eliminate the very long heartbeat delay. The captured error state
is also more likely to be useful if captured at the time of the error
rather than many seconds later.
Note that it is not possible to trigger a reset from with the G2H
handler itself. The reset prepare process involves flushing
outstanding G2H contents. So a deadlock could result. Instead, the G2H
handler queues a worker thread to do the reset asynchronously.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 26 +++
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 9
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +-
3 files changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2eb891b270aec..c35cf10f52b56 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -159,6 +159,13 @@ static void gen11_disable_guc_interrupts(struct intel_guc
*guc)
gen11_reset_guc_interrupts(guc);
}
+static void guc_dead_worker_func(struct work_struct *w)
+{
+ struct intel_guc *guc = container_of(w, struct intel_guc,
dead_guc_worker);
+
+ intel_gt_handle_error(guc_to_gt(guc), ALL_ENGINES, I915_ERROR_CAPTURE, "dead
GuC");
+}
+
void intel_guc_init_early(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
@@ -171,6 +178,8 @@ void intel_guc_init_early(struct intel_guc *guc)
intel_guc_slpc_init_early(>slpc);
intel_guc_rc_init_early(guc);
+ INIT_WORK(>dead_guc_worker, guc_dead_worker_func);
+
mutex_init(>send_mutex);
spin_lock_init(>irq_lock);
if (GRAPHICS_VER(i915) >= 11) {
@@ -585,6 +594,20 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*request, u32 len,
return ret;
}
+int intel_guc_crash_process_msg(struct intel_guc *guc, u32 action)
+{
+ if (action == INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED)
+ guc_err(guc, "Crash dump notification\n");
+ else if (action == INTEL_GUC_ACTION_NOTIFY_EXCEPTION)
+ guc_err(guc, "Exception notification\n");
+ else
+ guc_err(guc, "Unknown crash notification\n");
+
+ queue_work(system_unbound_wq, >dead_guc_worker);
Do we need to flush the worker on suspend/unload?
+
+ return 0;
+}
+
int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
const u32 *payload, u32 len)
{
@@ -601,6 +624,9 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc
*guc,
if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
guc_err(guc, "Received early exception notification!\n");
+ if (msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED | INTEL_GUC_RECV_MSG_EXCEPTION))
+ queue_work(system_unbound_wq, >dead_guc_worker);
I'm a bit worried about queuing this for a failure during the init flow.
If we have a systemic issue (e.g. bad memory) we could end up trying and
failing to reset & reload multiple times, until the wedge code manages
to set the wedge on init flag.
Daniele
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 8dc291ff00935..0b54eec95fc00 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -266,6 +266,14 @@ struct intel_guc {
unsigned long last_stat_jiffies;
} timestamp;
+ /**
+* @dead_guc_worker: Asynchronous worker thread for forcing a GuC reset.
+* Specifically used when the G2H handler wants to issue a reset. Resets
+* require flushing the G2H queue. So, the G2H processing itself must
not
+* trigger a reset directly. Instead, go via this worker.
+*/
+ struct work_struct dead_guc_worker;
+
#ifdef CONFIG_DRM_I915_SELFTEST
/**
* @number_guc_id_stolen: The number of guc_ids that have been stolen
@@ -476,6 +484,7 @@ int intel_guc_engine_failure_process_msg(struct intel_guc
*guc,
const u32 *msg, u32 len);
int intel_guc_error_capture_process_msg(struct intel_guc *guc,
const u32 *msg, u32 len);
+int intel_guc_crash_process_msg(struct intel_guc *guc, u32 action);
struct intel_engine_cs *
intel_guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance);
diff --git
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Force a reset on internal GuC error
== Series Details ==
Series: drm/i915/guc: Force a reset on internal GuC error
URL : https://patchwork.freedesktop.org/series/118890/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13234_full -> Patchwork_118890v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_118890v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#79])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-apl1/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-dp1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-dp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-snb: [PASS][5] -> [SKIP][6] ([fdo#109271])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-snb1/igt@kms_frontbuffer_track...@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/shard-snb5/igt@kms_frontbuffer_track...@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
- shard-apl: [PASS][7] -> [FAIL][8] ([i915#1188])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-apl2/igt@kms_hdr@bpc-switch-d...@pipe-a-dp-1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/shard-apl1/igt@kms_hdr@bpc-switch-d...@pipe-a-dp-1.html
*
igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4579]) +5
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/shard-snb1/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0...@pipe-b-hdmi-a-1.html
* igt@kms_tv_load_detect@load-detect:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271]) +37 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/shard-snb2/igt@kms_tv_load_det...@load-detect.html
Possible fixes
* igt@gem_exec_fair@basic-none@vecs0:
- {shard-rkl}:[FAIL][11] ([i915#2842]) -> [PASS][12] +2 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-rkl-2/igt@gem_exec_fair@basic-n...@vecs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/shard-rkl-7/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- {shard-tglu}: [FAIL][13] ([i915#2842]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-tglu-9/igt@gem_exec_fair@basic-throt...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/shard-tglu-9/igt@gem_exec_fair@basic-throt...@rcs0.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-rkl}:[SKIP][15] ([i915#1397]) -> [PASS][16] +2 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-rkl-2/igt@i915_pm_...@dpms-mode-unset-lpsp.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/shard-rkl-7/igt@i915_pm_...@dpms-mode-unset-lpsp.html
* igt@i915_pm_rps@reset:
- shard-snb: [DMESG-FAIL][17] ([i915#8319]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-snb4/igt@i915_pm_...@reset.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/shard-snb2/igt@i915_pm_...@reset.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][19] ([i915#2346]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-apl1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118890v1/shard-apl7/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_draw_crc@draw-method-blt@xrgb2101010-ytiled:
- shard-glk: [DMESG-WARN][21] ([i915#7936]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13234/shard-glk7/igt@kms_draw_crc@draw-method-...@xrgb2101010-ytiled.html
[22]:
[Intel-gfx] ✓ Fi.CI.BAT: success for mtl: add support for pmdemand (rev15)
== Series Details ==
Series: mtl: add support for pmdemand (rev15)
URL : https://patchwork.freedesktop.org/series/116949/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13238 -> Patchwork_116949v15
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/index.html
Participating hosts (41 -> 39)
--
Missing(2): bat-rpls-2 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_116949v15 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@reset:
- bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#4983] / [i915#7461] /
[i915#7981] / [i915#8347] / [i915#8384])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-rpls-1/igt@i915_selftest@l...@reset.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#7828])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
- bat-adlm-1: NOTRUN -> [SKIP][4] ([i915#7828])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-adlm-1/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [PASS][5] -> [FAIL][6] ([i915#7932])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlm-1: NOTRUN -> [SKIP][7] ([i915#1845])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-adlm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: [ABORT][8] ([i915#7913] / [i915#7979]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@workarounds:
- bat-adlm-1: [INCOMPLETE][10] ([i915#4983] / [i915#7677]) ->
[PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-dp-5:
- {bat-adlp-11}: [ABORT][12] -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-dp-5.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v15/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-dp-5.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4309]: https://gitlab.freedesktop.org/drm/intel/issues/4309
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7953]: https://gitlab.freedesktop.org/drm/intel/issues/7953
[i915#7979]: https://gitlab.freedesktop.org/drm/intel/issues/7979
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
Build changes
-
* Linux: CI_DRM_13238 -> Patchwork_116949v15
CI-20190529: 20190529
CI_DRM_13238: 8c0b302811d744b945dcb6d78164a76188914db9 @
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mtl: add support for pmdemand (rev15)
== Series Details ==
Series: mtl: add support for pmdemand (rev15)
URL : https://patchwork.freedesktop.org/series/116949/
State : warning
== Summary ==
Error: dim checkpatch failed
595a7ad922f2 drm/i915: fix the derating percentage for MTL
6c642218f0cc drm/i915: update the QGV point frequency calculations
f73e6f3d3a89 drm/i915: store the peak bw per QGV point
a12a6f28079a drm/i915: extract intel_bw_check_qgv_points()
e1dbf9927a1c drm/i915: modify max_bw to return index to intel_bw_info
49909f81b052 drm/i915/mtl: find the best QGV point for the SAGV configuration
11ac7a3d546d drm/i915/mtl: Add support for PM DEMAND
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:425: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#425:
new file mode 100644
-:920: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'reg' - possible
side-effects?
#920: FILE: drivers/gpu/drm/i915/display/intel_pmdemand.c:491:
+#define update_reg(reg, field, mask) do { \
+ u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \
+ u32 old_val = old ? old->params.field : 0; \
+ u32 new_val = new->params.field; \
+\
+ *(reg) &= ~(mask); \
+ *(reg) |= REG_FIELD_PREP((mask), max3(old_val, new_val, current_val)); \
+} while (0)
-:920: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'field' - possible
side-effects?
#920: FILE: drivers/gpu/drm/i915/display/intel_pmdemand.c:491:
+#define update_reg(reg, field, mask) do { \
+ u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \
+ u32 old_val = old ? old->params.field : 0; \
+ u32 new_val = new->params.field; \
+\
+ *(reg) &= ~(mask); \
+ *(reg) |= REG_FIELD_PREP((mask), max3(old_val, new_val, current_val)); \
+} while (0)
-:920: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible
side-effects?
#920: FILE: drivers/gpu/drm/i915/display/intel_pmdemand.c:491:
+#define update_reg(reg, field, mask) do { \
+ u32 current_val = serialized ? 0 : REG_FIELD_GET((mask), *(reg)); \
+ u32 old_val = old ? old->params.field : 0; \
+ u32 new_val = new->params.field; \
+\
+ *(reg) &= ~(mask); \
+ *(reg) |= REG_FIELD_PREP((mask), max3(old_val, new_val, current_val)); \
+} while (0)
total: 0 errors, 1 warnings, 3 checks, 1016 lines checked
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for mtl: add support for pmdemand (rev15)
== Series Details == Series: mtl: add support for pmdemand (rev15) URL : https://patchwork.freedesktop.org/series/116949/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix a VMA UAF for multi-gt platform
== Series Details ==
Series: drm/i915: Fix a VMA UAF for multi-gt platform
URL : https://patchwork.freedesktop.org/series/118887/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13233_full -> Patchwork_118887v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 6)
--
Missing(1): shard-dg1
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118887v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_legacy@cursora-vs-flipa-varying-size:
- {shard-rkl}:[PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/shard-rkl-4/igt@kms_cursor_leg...@cursora-vs-flipa-varying-size.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/shard-rkl-7/igt@kms_cursor_leg...@cursora-vs-flipa-varying-size.html
Known issues
Here are the changes found in Patchwork_118887v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@engines-hang:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/shard-snb7/igt@gem_ctx_persiste...@engines-hang.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2842])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_schedule@thriceslice:
- shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271]) +98 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/shard-snb7/igt@gem_exec_sched...@thriceslice.html
* igt@kms_content_protection@atomic-dpms:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4579]) +16
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/shard-snb7/igt@kms_content_protect...@atomic-dpms.html
* igt@kms_setmode@basic@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [FAIL][8] ([i915#5465]) +1 similar issue
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/shard-snb1/igt@kms_setmode@ba...@pipe-a-hdmi-a-1.html
Possible fixes
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][9] ([i915#6268]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/shard-tglu-5/igt@gem_ctx_e...@basic-nohangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/shard-tglu-6/igt@gem_ctx_e...@basic-nohangcheck.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- {shard-rkl}:[FAIL][11] ([i915#2842]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/shard-rkl-3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/shard-rkl-1/igt@gem_exec_fair@basic-pace-s...@rcs0.html
- shard-apl: [FAIL][13] ([i915#2842]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/shard-apl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/shard-apl1/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_mmap_gtt@fault-concurrent-x:
- shard-snb: [ABORT][15] ([i915#5161]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/shard-snb4/igt@gem_mmap_...@fault-concurrent-x.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/shard-snb7/igt@gem_mmap_...@fault-concurrent-x.html
* igt@i915_pm_rpm@dpms-lpsp:
- {shard-rkl}:[SKIP][17] ([i915#1397]) -> [PASS][18] +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/shard-rkl-3/igt@i915_pm_...@dpms-lpsp.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/shard-rkl-7/igt@i915_pm_...@dpms-lpsp.html
* igt@i915_pm_rps@engine-order:
- shard-apl: [FAIL][19] ([i915#6537]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/shard-apl1/igt@i915_pm_...@engine-order.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118887v1/shard-apl7/igt@i915_pm_...@engine-order.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][21] ([i915#2346]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13233/shard-glk3/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
[22]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Load LUTs with DSB (rev2)
== Series Details ==
Series: drm/i915: Load LUTs with DSB (rev2)
URL : https://patchwork.freedesktop.org/series/113042/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13238 -> Patchwork_113042v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v2/index.html
Participating hosts (41 -> 39)
--
Missing(2): bat-rpls-2 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_113042v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][1] ([i915#7828])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v2/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
- bat-adlm-1: NOTRUN -> [SKIP][2] ([i915#7828])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v2/bat-adlm-1/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [PASS][3] -> [FAIL][4] ([i915#7932])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlm-1: NOTRUN -> [SKIP][5] ([i915#1845])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v2/bat-adlm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: [ABORT][6] ([i915#7913] / [i915#7979]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v2/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-WARN][8] ([i915#6367]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v2/bat-rpls-1/igt@i915_selftest@l...@slpc.html
* igt@i915_selftest@live@workarounds:
- bat-adlm-1: [INCOMPLETE][10] ([i915#4983] / [i915#7677]) ->
[PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v2/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7979]: https://gitlab.freedesktop.org/drm/intel/issues/7979
[i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260
Build changes
-
* Linux: CI_DRM_13238 -> Patchwork_113042v2
CI-20190529: 20190529
CI_DRM_13238: 8c0b302811d744b945dcb6d78164a76188914db9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7320: 1c96b08a4cde6f2d49824a8cc3303bd860617b52 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113042v2: 8c0b302811d744b945dcb6d78164a76188914db9 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
674b64159bd8 drm/i915: Do state check for color management changes
2e1001ec3012 drm/i915/dsb: Re-instate DSB for LUT updates
6e43a7fee4a7 drm/i915/dsb: Use DEwake to combat PkgC latency
5ec7a070502b drm/i915: Introudce intel_crtc_scanline_to_hw()
50f7843e76d9 drm/i915: Introduce skl_watermark_max_latency()
3f7be7a944e2 drm/i915/dsb: Evade transcoder undelayed vblank when using DSB
846fdd8f2a28 drm/i915/dsb: Use non-posted register writes for legacy LUT
cc7c791acea8 drm/i915/dsb: Load LUTs using the DSB during vblank
807de1a55e42 drm/i915/dsb: Don't use DSB to load the LUTs during full modeset
3d819e893e5e drm/i915/dsb: Add support for non-posted DSB registers writes
[Intel-gfx] [PATCH] drm/i915/dp: Fix log level for "CDS interlane align done"
"CDS interlane align done" is a passing condition not an error.
Before adding new macros for logs it was drm_dbg_kms.
Fixes: f48eab290287 ("drm/i915/dp: Add link training debug and error printing
helpers")
Cc: Imre Deak
CC: Jani Nikula
Signed-off-by: Khaled Almahallawy
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 0952a707358c..176b610642e7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1279,7 +1279,7 @@ intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp,
if (drm_dp_128b132b_eq_interlane_align_done(link_status) &&
drm_dp_128b132b_cds_interlane_align_done(link_status) &&
drm_dp_128b132b_lane_symbol_locked(link_status,
crtc_state->lane_count)) {
- lt_err(intel_dp, DP_PHY_DPRX, "CDS interlane align
done\n");
+ lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align
done\n");
break;
}
--
2.34.1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Load LUTs with DSB (rev2)
== Series Details == Series: drm/i915: Load LUTs with DSB (rev2) URL : https://patchwork.freedesktop.org/series/113042/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Load LUTs with DSB (rev2)
== Series Details == Series: drm/i915: Load LUTs with DSB (rev2) URL : https://patchwork.freedesktop.org/series/113042/ State : warning == Summary == Error: dim checkpatch failed 35a5ec5257a0 drm/i915: Constify LUT entries in checker 018aa36a0ba6 drm/i915/dsb: Use non-locked register access 7f1c6c879158 drm/i915/dsb: Dump the DSB command buffer when DSB fails -:34: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV) #34: FILE: drivers/gpu/drm/i915/display/intel_dsb.c:108: + i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]); ^ -:34: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV) #34: FILE: drivers/gpu/drm/i915/display/intel_dsb.c:108: + i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]); ^ -:34: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV) #34: FILE: drivers/gpu/drm/i915/display/intel_dsb.c:108: + i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]); ^ total: 0 errors, 0 warnings, 3 checks, 46 lines checked 0a4d1ee3a7dc drm/i915/dsb: Define more DSB bits 38081eebc4d0 drm/i915/dsb: Define the contents of some intstructions bit better 9f17b48cfa11 drm/i915/dsb: Avoid corrupting the first register write c42dd35aefce drm/i915/dsb: Don't use indexed writes when byte enables are not all set 3fbf457bbf91 drm/i915/dsb: Introduce intel_dsb_noop() dac21505a69f drm/i915/dsb: Introduce intel_dsb_reg_write_masked() 31801d2a8474 drm/i915/dsb: Add support for non-posted DSB registers writes 855a48b16b6a drm/i915/dsb: Don't use DSB to load the LUTs during full modeset 2c4cd85c5f78 drm/i915/dsb: Load LUTs using the DSB during vblank cfe38d031292 drm/i915/dsb: Use non-posted register writes for legacy LUT dd012e35d761 drm/i915/dsb: Evade transcoder undelayed vblank when using DSB 941cfcdee747 drm/i915: Introduce skl_watermark_max_latency() 2fb1138ee512 drm/i915: Introudce intel_crtc_scanline_to_hw() 952b6004f60c drm/i915/dsb: Use DEwake to combat PkgC latency d88af6de0a61 drm/i915/dsb: Re-instate DSB for LUT updates c745478e5c12 drm/i915: Do state check for color management changes
[Intel-gfx] [PATCH i-g-t] tests/gem_ctx_persistence: Skip hang subtest with GuC
Hang subtest is not supported with GuC submission enabled. Cc: Kamil Konieczny Signed-off-by: Vinay Belgaumkar --- tests/i915/gem_ctx_persistence.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/i915/gem_ctx_persistence.c b/tests/i915/gem_ctx_persistence.c index df9b1c491..d2558354e 100644 --- a/tests/i915/gem_ctx_persistence.c +++ b/tests/i915/gem_ctx_persistence.c @@ -577,6 +577,8 @@ static void test_nohangcheck_hang(int i915, const intel_ctx_cfg_t *cfg) int testable_engines = 0; int dir; + igt_require(!gem_using_guc_submission(i915)); + cleanup(i915); /* -- 2.38.1
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: do not dereference dangling engine pointer on fence release
== Series Details ==
Series: drm/i915: do not dereference dangling engine pointer on fence release
URL : https://patchwork.freedesktop.org/series/118879/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13232_full -> Patchwork_118879v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 6)
--
Missing(1): shard-dg1
Known issues
Here are the changes found in Patchwork_118879v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][1] -> [FAIL][2] ([i915#2842])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_lmem_swapping@random:
- shard-glk: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-glk5/igt@gem_lmem_swapp...@random.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2521])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/shard-glk2/igt@kms_async_flips@alternate-sync-async-f...@pipe-b-hdmi-a-1.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-glk5/igt@kms_async_flips@alternate-sync-async-f...@pipe-b-hdmi-a-1.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3886]) +1
similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-glk5/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#3886]) +2
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-apl1/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_ccs:
- shard-apl: NOTRUN -> [SKIP][8] ([fdo#109271]) +31 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-apl1/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_ccs.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4579]) +3
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-snb6/igt@kms_dit...@fb-8bpc-vs-panel-6bpc.html
* igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a1:
- shard-glk: [PASS][10] -> [FAIL][11] ([i915#2122])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/shard-glk2/igt@kms_flip@plain-flip-fb-recre...@a-hdmi-a1.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-glk5/igt@kms_flip@plain-flip-fb-recre...@a-hdmi-a1.html
*
igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-glk: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4579]) +2
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-glk5/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscal...@pipe-a-valid-mode.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#658])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-glk5/igt@kms_psr2...@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4579])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-apl1/igt@kms_setm...@clone-exclusive-crtc.html
* igt@kms_tv_load_detect@load-detect:
- shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271]) +30 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-snb5/igt@kms_tv_load_det...@load-detect.html
* igt@v3d/v3d_perfmon@create-perfmon-exceed:
- shard-glk: NOTRUN -> [SKIP][16] ([fdo#109271]) +49 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-glk5/igt@v3d/v3d_perf...@create-perfmon-exceed.html
Possible fixes
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- {shard-rkl}:[FAIL][17] ([i915#7742]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/shard-rkl-7/igt@drm_fdinfo@most-busy-check-...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118879v1/shard-rkl-2/igt@drm_fdinfo@most-busy-check-...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [FAIL][19]
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/adlp+: Allow DC states along with PW2 only for PWB functionality
== Series Details ==
Series: drm/i915/adlp+: Allow DC states along with PW2 only for PWB
functionality
URL : https://patchwork.freedesktop.org/series/118951/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13238 -> Patchwork_118951v1
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_118951v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_118951v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118951v1/index.html
Participating hosts (41 -> 39)
--
Missing(2): bat-rpls-2 fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118951v1:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@hangcheck:
- fi-skl-guc: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118951v1/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118951v1/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html
Known issues
Here are the changes found in Patchwork_118951v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- bat-rpls-1: [PASS][4] -> [ABORT][5] ([i915#7677])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118951v1/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#7828])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118951v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html
- bat-adlm-1: NOTRUN -> [SKIP][7] ([i915#7828])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118951v1/bat-adlm-1/igt@kms_chamelium_...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [PASS][8] -> [FAIL][9] ([i915#7932])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118951v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlm-1: NOTRUN -> [SKIP][10] ([i915#1845])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118951v1/bat-adlm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: [ABORT][11] ([i915#7913] / [i915#7979]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118951v1/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@workarounds:
- bat-adlm-1: [INCOMPLETE][13] ([i915#4983] / [i915#7677]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118951v1/bat-adlm-1/igt@i915_selftest@l...@workarounds.html
Warnings
* igt@kms_psr@primary_mmap_gtt:
- bat-rplp-1: [SKIP][15] ([i915#1072]) -> [ABORT][16] ([i915#8442])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13238/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118951v1/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7677]: https://gitlab.freedesktop.org/drm/intel/issues/7677
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Remove some obsolete definitions (rev2)
== Series Details ==
Series: drm/i915/guc: Remove some obsolete definitions (rev2)
URL : https://patchwork.freedesktop.org/series/118658/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13232_full -> Patchwork_118658v2_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
--
Additional (1): shard-rkl0
Missing(1): shard-dg1
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118658v2_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_persistence@processes:
- {shard-rkl}:[PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/shard-rkl-1/igt@gem_ctx_persiste...@processes.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/shard-rkl-1/igt@gem_ctx_persiste...@processes.html
Known issues
Here are the changes found in Patchwork_118658v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: NOTRUN -> [FAIL][3] ([i915#2842])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/shard-glk5/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_lmem_swapping@random:
- shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/shard-glk5/igt@gem_lmem_swapp...@random.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3886]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/shard-glk5/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3886]) +2
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/shard-apl4/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_ccs:
- shard-apl: NOTRUN -> [SKIP][7] ([fdo#109271]) +31 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/shard-apl4/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2346])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/shard-glk8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/shard-glk4/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][10] -> [ABORT][11] ([i915#180])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/shard-apl1/igt@kms_flip@flip-vs-suspend-interrupti...@c-dp1.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/shard-apl3/igt@kms_flip@flip-vs-suspend-interrupti...@c-dp1.html
*
igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-glk: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4579]) +2
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/shard-glk5/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscal...@pipe-a-valid-mode.html
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4579]) +4
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/shard-snb1/igt@kms_plane_scaling@plane-upscale-with-modifiers-20...@pipe-b-hdmi-a-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#658])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/shard-glk5/igt@kms_psr2...@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4579])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/shard-apl4/igt@kms_setm...@clone-exclusive-crtc.html
* igt@kms_tv_load_detect@load-detect:
- shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271]) +32 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118658v2/shard-snb2/igt@kms_tv_load_det...@load-detect.html
* igt@v3d/v3d_perfmon@create-perfmon-exceed:
- shard-glk: NOTRUN -> [SKIP][17] ([fdo#109271]) +49 similar issues
[17]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Allow user to set cache at BO creation (rev2)
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev2)
URL : https://patchwork.freedesktop.org/series/118660/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13232_full -> Patchwork_118660v2_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (7 -> 6)
--
Missing(1): shard-dg1
Known issues
Here are the changes found in Patchwork_118660v2_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@random:
- shard-glk: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-glk2/igt@gem_lmem_swapp...@random.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][2] -> [ABORT][3] ([i915#5566])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/shard-apl6/igt@gen9_exec_pa...@allowed-single.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-apl1/igt@gen9_exec_pa...@allowed-single.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#3886]) +1
similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-glk2/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3886]) +2
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-apl6/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_ccs:
- shard-apl: NOTRUN -> [SKIP][6] ([fdo#109271]) +31 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-apl6/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2346])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/shard-glk8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-glk7/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
*
igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-glk: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4579]) +2
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-glk2/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscal...@pipe-a-valid-mode.html
*
igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4579]) +12
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-snb7/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scal...@pipe-b-vga-1.html
*
igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271]) +17 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-snb4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-...@pipe-a-vga-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-glk: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#658])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-glk2/igt@kms_psr2...@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4579])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-apl6/igt@kms_setm...@clone-exclusive-crtc.html
* igt@v3d/v3d_perfmon@create-perfmon-exceed:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271]) +49 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-glk2/igt@v3d/v3d_perf...@create-perfmon-exceed.html
Possible fixes
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- {shard-rkl}:[FAIL][15] ([i915#7742]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/shard-rkl-7/igt@drm_fdinfo@most-busy-check-...@rcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-rkl-4/igt@drm_fdinfo@most-busy-check-...@rcs0.html
* igt@gem_create@create-ext-set-pat:
- shard-glk: [SKIP][17] ([fdo#109271]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13232/shard-glk3/igt@gem_cre...@create-ext-set-pat.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118660v2/shard-glk9/igt@gem_cre...@create-ext-set-pat.html
[Intel-gfx] [PATCH] drm/i915/quirk: Add quirk for devices that cannot be dimmed
Cybernet T10C cannot be dimmed without the backlight strobing. Create a
new quirk to lock the minimum brightness to the highest supported value.
This aligns the device with its behavior on Windows, which will not
lower the brightness below maximum.
Signed-off-by: Allen Ballway
---
.../gpu/drm/i915/display/intel_backlight.c| 6 +
drivers/gpu/drm/i915/display/intel_quirks.c | 27 +++
drivers/gpu/drm/i915/display/intel_quirks.h | 1 +
3 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 2e8f17c045222..863a33245a3d7 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1192,6 +1192,11 @@ static u32 get_backlight_min_vbt(struct intel_connector
*connector)
drm_WARN_ON(>drm, panel->backlight.pwm_level_max == 0);
+ if (intel_has_quirk(i915, QUIRK_NO_DIM)) {
+ /* Cannot dim backlight, set minimum to hightest value */
+ return panel->backlight.pwm_level_max - 1;
+ }
+
/*
* XXX: If the vbt value is 255, it makes min equal to max, which leads
* to problems. There are such machines out there. Either our
@@ -1206,6 +1211,7 @@ static u32 get_backlight_min_vbt(struct intel_connector
*connector)
connector->panel.vbt.backlight.min_brightness, min);
}
+
/* vbt value is a coefficient in range [0..255] */
return scale(min, 0, 255, 0, panel->backlight.pwm_level_max);
}
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c
b/drivers/gpu/drm/i915/display/intel_quirks.c
index a280448df771a..910c95840a539 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -65,6 +65,12 @@ static void quirk_no_pps_backlight_power_hook(struct
drm_i915_private *i915)
drm_info(>drm, "Applying no pps backlight power quirk\n");
}
+static void quirk_no_dim(struct drm_i915_private *i915)
+{
+ intel_set_quirk(i915, QUIRK_NO_DIM);
+ drm_info(>drm, "Applying no dim quirk\n");
+}
+
struct intel_quirk {
int device;
int subsystem_vendor;
@@ -90,6 +96,12 @@ static int intel_dmi_no_pps_backlight(const struct
dmi_system_id *id)
return 1;
}
+static int intel_dmi_no_dim(const struct dmi_system_id *id)
+{
+ DRM_INFO("No dimming allowed on %s\n", id->ident);
+ return 1;
+}
+
static const struct intel_dmi_quirk intel_dmi_quirks[] = {
{
.dmi_id_list = &(const struct dmi_system_id[]) {
@@ -136,6 +148,20 @@ static const struct intel_dmi_quirk intel_dmi_quirks[] = {
},
.hook = quirk_no_pps_backlight_power_hook,
},
+ {
+ .dmi_id_list = &(const struct dmi_system_id[]) {
+ {
+ .callback = intel_dmi_no_dim,
+ .ident = "Cybernet T10C Tablet",
+ .matches = {DMI_EXACT_MATCH(DMI_BOARD_VENDOR,
+ "Cybernet
Manufacturing Inc."),
+ DMI_EXACT_MATCH(DMI_BOARD_NAME,
"T10C Tablet"),
+ },
+ },
+ { }
+ },
+ .hook = quirk_no_dim,
+ },
};
static struct intel_quirk intel_quirks[] = {
@@ -218,6 +244,7 @@ void intel_init_quirks(struct drm_i915_private *i915)
q->subsystem_device == PCI_ANY_ID))
q->hook(i915);
}
+
for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
intel_dmi_quirks[i].hook(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h
b/drivers/gpu/drm/i915/display/intel_quirks.h
index 10a4d163149fd..b41c7bbf0a5e3 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.h
+++ b/drivers/gpu/drm/i915/display/intel_quirks.h
@@ -17,6 +17,7 @@ enum intel_quirk_id {
QUIRK_INVERT_BRIGHTNESS,
QUIRK_LVDS_SSC_DISABLE,
QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK,
+ QUIRK_NO_DIM,
};
void intel_init_quirks(struct drm_i915_private *i915);
--
2.41.0.162.gfafddb0af9-goog
Re: [Intel-gfx] [PATCH v2] drm/i915: Fix a VMA UAF for multi-gt platform
Hi Nirmoy,
On Tue, Jun 06, 2023 at 10:27:55PM +0200, Nirmoy Das wrote:
> Ensure correct handling of closed VMAs on multi-gt platforms to prevent
> Use-After-Free. Currently, when GT0 goes idle, closed VMAs that are
> exclusively added to GT0's closed_vma link (gt->closed_vma) and
> subsequently freed by i915_vma_parked(), which assumes the entire GPU is
> idle. However, on platforms with multiple GTs, such as MTL, GT1 may
> remain active while GT0 is idle. This causes GT0 to mistakenly consider
> the closed VMAs in its closed_vma list as unnecessary, potentially
> leading to Use-After-Free issues if a job for GT1 attempts to access a
> freed VMA.
>
> Although we do take a wakeref for GT0 but it happens later, after
> evaluating VMAs. To mitigate this, it is necessary to hold a GT0 wakeref
> early.
>
> v2: Use gt id to detect multi-tile(Andi)
> Fix the incorrect error path.
>
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Tvrtko Ursulin
> Cc: Thomas Hellström
> Cc: Chris Wilson
> Cc: Andi Shyti
> Cc: Andrzej Hajda
> Cc: Sushma Venkatesh Reddy
> Tested-by: Andi Shyti
> Signed-off-by: Nirmoy Das
I wonder if we need any Fixes tag here, maybe this:
Fixes: d93939730347 ("drm/i915: Remove the vma refcount")
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 3aeede6aee4d..c2a67435acfa 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -2683,6 +2683,7 @@ static int
> eb_select_engine(struct i915_execbuffer *eb)
> {
> struct intel_context *ce, *child;
> + struct intel_gt *gt;
> unsigned int idx;
> int err;
>
> @@ -2706,10 +2707,16 @@ eb_select_engine(struct i915_execbuffer *eb)
> }
> }
> eb->num_batches = ce->parallel.number_children + 1;
> + gt = ce->engine->gt;
>
> for_each_child(ce, child)
> intel_context_get(child);
> intel_gt_pm_get(ce->engine->gt);
> + /* Keep GT0 active on MTL so that i915_vma_parked() doesn't
> + * free VMAs while execbuf ioctl is validating VMAs.
> + */
> + if (gt->info.id)
> + intel_gt_pm_get(to_gt(gt->i915));
>
> if (!test_bit(CONTEXT_ALLOC_BIT, >flags)) {
> err = intel_context_alloc_state(ce);
> @@ -2748,6 +2755,9 @@ eb_select_engine(struct i915_execbuffer *eb)
> return err;
>
> err:
> + if (gt->info.id)
> + intel_gt_pm_put(to_gt(gt->i915));
> +
> intel_gt_pm_put(ce->engine->gt);
> for_each_child(ce, child)
> intel_context_put(child);
> @@ -2761,6 +2771,8 @@ eb_put_engine(struct i915_execbuffer *eb)
> struct intel_context *child;
>
> i915_vm_put(eb->context->vm);
> + if (eb->gt->info.id)
> + intel_gt_pm_put(to_gt(eb->gt->i915));
> intel_gt_pm_put(eb->gt);
I would add a comment up here, just not to scare people when they
see this.
Reviewed-by: Andi Shyti
Andi
> for_each_child(eb->context, child)
> intel_context_put(child);
> --
> 2.39.0
[Intel-gfx] [PATCH i-g-t] tests/i915_pm_freq_api: Add a suspend subtest
Verify that SLPC API works as expected after a suspend.
Signed-off-by: Vinay Belgaumkar
---
tests/i915/i915_pm_freq_api.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/tests/i915/i915_pm_freq_api.c b/tests/i915/i915_pm_freq_api.c
index 9005cd220..f35f1f8e0 100644
--- a/tests/i915/i915_pm_freq_api.c
+++ b/tests/i915/i915_pm_freq_api.c
@@ -18,6 +18,9 @@
*
* SUBTEST: freq-reset
* Description: Test basic freq API works after a reset
+ *
+ * SUBTEST: freq-suspend
+ * Description: Test basic freq API works after a runtime suspend
*/
IGT_TEST_DESCRIPTION("Test SLPC freq API");
@@ -99,6 +102,24 @@ static void test_reset(int i915, int dirfd, int gt)
igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpn);
}
+static void test_suspend(int i915, int dirfd, int gt)
+{
+ uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ);
+
+ igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0);
+ igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0);
+ usleep(ACT_FREQ_LATENCY_US);
+ igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpn);
+ igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpn);
+
+ /* Manually trigger a suspend */
+ igt_system_suspend_autoresume(SUSPEND_STATE_S3,
+ SUSPEND_TEST_NONE);
+
+ igt_assert(get_freq(dirfd, RPS_MIN_FREQ_MHZ) == rpn);
+ igt_assert(get_freq(dirfd, RPS_MAX_FREQ_MHZ) == rpn);
+}
+
igt_main
{
int i915 = -1;
@@ -143,6 +164,15 @@ igt_main
test_reset(i915, dirfd, gt);
}
+ igt_describe("Test basic freq API works after suspend");
+ igt_subtest_with_dynamic_f("freq-suspend") {
+ int dirfd, gt;
+
+ for_each_sysfs_gt_dirfd(i915, dirfd, gt)
+ igt_dynamic_f("gt%u", gt)
+ test_suspend(i915, dirfd, gt);
+ }
+
igt_fixture {
int dirfd, gt;
/* Restore frequencies */
--
2.38.1
[Intel-gfx] [PATCH v2] drm/i915: Fix a VMA UAF for multi-gt platform
Ensure correct handling of closed VMAs on multi-gt platforms to prevent
Use-After-Free. Currently, when GT0 goes idle, closed VMAs that are
exclusively added to GT0's closed_vma link (gt->closed_vma) and
subsequently freed by i915_vma_parked(), which assumes the entire GPU is
idle. However, on platforms with multiple GTs, such as MTL, GT1 may
remain active while GT0 is idle. This causes GT0 to mistakenly consider
the closed VMAs in its closed_vma list as unnecessary, potentially
leading to Use-After-Free issues if a job for GT1 attempts to access a
freed VMA.
Although we do take a wakeref for GT0 but it happens later, after
evaluating VMAs. To mitigate this, it is necessary to hold a GT0 wakeref
early.
v2: Use gt id to detect multi-tile(Andi)
Fix the incorrect error path.
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: Thomas Hellström
Cc: Chris Wilson
Cc: Andi Shyti
Cc: Andrzej Hajda
Cc: Sushma Venkatesh Reddy
Tested-by: Andi Shyti
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 3aeede6aee4d..c2a67435acfa 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2683,6 +2683,7 @@ static int
eb_select_engine(struct i915_execbuffer *eb)
{
struct intel_context *ce, *child;
+ struct intel_gt *gt;
unsigned int idx;
int err;
@@ -2706,10 +2707,16 @@ eb_select_engine(struct i915_execbuffer *eb)
}
}
eb->num_batches = ce->parallel.number_children + 1;
+ gt = ce->engine->gt;
for_each_child(ce, child)
intel_context_get(child);
intel_gt_pm_get(ce->engine->gt);
+ /* Keep GT0 active on MTL so that i915_vma_parked() doesn't
+* free VMAs while execbuf ioctl is validating VMAs.
+*/
+ if (gt->info.id)
+ intel_gt_pm_get(to_gt(gt->i915));
if (!test_bit(CONTEXT_ALLOC_BIT, >flags)) {
err = intel_context_alloc_state(ce);
@@ -2748,6 +2755,9 @@ eb_select_engine(struct i915_execbuffer *eb)
return err;
err:
+ if (gt->info.id)
+ intel_gt_pm_put(to_gt(gt->i915));
+
intel_gt_pm_put(ce->engine->gt);
for_each_child(ce, child)
intel_context_put(child);
@@ -2761,6 +2771,8 @@ eb_put_engine(struct i915_execbuffer *eb)
struct intel_context *child;
i915_vm_put(eb->context->vm);
+ if (eb->gt->info.id)
+ intel_gt_pm_put(to_gt(eb->gt->i915));
intel_gt_pm_put(eb->gt);
for_each_child(eb->context, child)
intel_context_put(child);
--
2.39.0
[Intel-gfx] [PATCH v15 7/7] drm/i915/mtl: Add support for PM DEMAND
From: Mika Kahola MTL introduces a new way to instruct the PUnit with power and bandwidth requirements of DE. Add the functionality to program the registers and handle waits using interrupts. The current wait time for timeouts is programmed for 10 msecs to factor in the worst case scenarios. Changes made to use REG_BIT for a register that we touched(GEN8_DE_MISC_IER _MMIO). Wa_14016740474 is added which applies to Xe_LPD+ display v2: checkpatch warning fixes, simplify program pmdemand part v3: update to dbufs and pipes values to pmdemand register(stan) Removed the macro usage in update_pmdemand_values() v4: move the pmdemand_pre_plane_update before cdclk update pmdemand_needs_update included cdclk params comparisons pmdemand_state NULL check (Gustavo) pmdemand.o in sorted order in the makefile (Jani) update pmdemand misc irq handler loop (Gustavo) active phys bitmask and programming correction (Gustavo) v5: simplify pmdemand_state structure simplify methods to find active phys and max port clock Timeout in case of previou pmdemand task pending (Gustavo) v6: rebasing updates to max_ddiclk calculations (Gustavo) updates to active_phys count method (Gustavo) v7: use two separate loop to iterate throug old and new crtc states to calculate the active phys (Gustavo) v8: use uniform function names (Gustavo) v9: For phys change iterate through connectors (Imre) Look for change in phys for pmdemand update (Gustavo, Imre) Some more stlying changes (Imre) Update pmdemand state during HW readout/sanitize (Imre) v10: Fix CI checkpatch warnings v11: use correct pmdemand object pointer during hw readout, simplify the check for phys need update (Gustavo) v12: Handle possible non serialize cases (Imre) Initialise also pmdemand params HW readout (Imre) Update active phys mask during sanitize calls (Imre) Check TC/encoder changes to limit connector update (Imre) v13: Check display version before accessing pmdemand functions v14: Move is_serialized to intel_global_state.c simplify update params and other stlying issues (Imre) Bspec: 66451, 64636, 64602, 64603 Cc: Matt Atwood Cc: Matt Roper Cc: Lucas De Marchi Cc: Gustavo Sousa Signed-off-by: José Roberto de Souza Signed-off-by: Radhakrishna Sripada Signed-off-by: Gustavo Sousa Signed-off-by: Mika Kahola Signed-off-by: Vinod Govindapillai Reviewed-by: Stanislav Lisovskiy #v4 Acked-by: Gustavo Sousa #v11 Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_display.c | 14 + .../gpu/drm/i915/display/intel_display_core.h | 9 + .../drm/i915/display/intel_display_driver.c | 7 + .../gpu/drm/i915/display/intel_display_irq.c | 23 +- .../drm/i915/display/intel_display_power.c| 14 +- .../gpu/drm/i915/display/intel_global_state.c | 12 + .../gpu/drm/i915/display/intel_global_state.h | 2 + .../drm/i915/display/intel_modeset_setup.c| 32 + drivers/gpu/drm/i915/display/intel_pmdemand.c | 620 ++ drivers/gpu/drm/i915/display/intel_pmdemand.h | 67 ++ drivers/gpu/drm/i915/i915_reg.h | 26 +- 12 files changed, 821 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 1c9ed4c52760..2cd8de174bf6 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -269,6 +269,7 @@ i915-y += \ display/intel_pch_display.o \ display/intel_pch_refclk.o \ display/intel_plane_initial.o \ + display/intel_pmdemand.o \ display/intel_psr.o \ display/intel_quirks.o \ display/intel_sprite.o \ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f51a55f4e9d0..5cbf5eae2414 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -99,6 +99,7 @@ #include "intel_pcode.h" #include "intel_pipe_crc.h" #include "intel_plane_initial.h" +#include "intel_pmdemand.h" #include "intel_pps.h" #include "intel_psr.h" #include "intel_sdvo.h" @@ -6352,6 +6353,10 @@ int intel_atomic_check(struct drm_device *dev, return ret; } + ret = intel_pmdemand_atomic_check(state); + if (ret) + goto fail; + ret = intel_atomic_check_crtcs(state); if (ret) goto fail; @@ -6997,6 +7002,14 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) crtc->config = new_crtc_state; + /* +* In XE_LPD+ Pmdemand combines many parameters such as voltage index, +* plls, cdclk frequency, QGV point selection parameter etc. Voltage +
Re: [Intel-gfx] [PATCH] drm/i915: Fix a VMA UAF for multi-gt platform
Hi Nirmoy, > > MTL is a > > weird multi-gt platform and, indeed, you can't shut down GT0 > > without affecting GT1. > > > > For now it's OK, though, as to test it. > > Looking forward to that. I did test it extensively and ChromeOS team as > well. great job, Nirmoy! I haven't been able to reproduce the issue. This is a great news! Tested-by: Andi Shyti Andi
Re: [Intel-gfx] [PATCH v2 1/2] vgaarb: various coding style and comments fix
Match the subject line style:
$ git log --oneline drivers/pci/vgaarb.c
f321c35feaee PCI/VGA: Replace full MIT license text with SPDX identifier
d5109fe4d1ec PCI/VGA: Use unsigned format string to print lock counts
4e6c91847a7f PCI/VGA: Log bridge control messages when adding devices
dc593fd48abb PCI/VGA: Remove empty vga_arb_device_card_gone()
...
Subject line should be a summary of the commit log, not just "various
style fixes". This one needs to say something about
vga_str_to_iostate().
On Mon, Jun 05, 2023 at 04:58:30AM +0800, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> To keep consistent with vga_iostate_to_str() function, the third argument
> of vga_str_to_iostate() function should be 'unsigned int *'.
>
> Signed-off-by: Sui Jingfeng
> ---
> drivers/pci/vgaarb.c | 29 +++--
> include/linux/vgaarb.h | 8 +++-
> 2 files changed, 18 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/pci/vgaarb.c b/drivers/pci/vgaarb.c
> index 5a696078b382..e40e6e5e5f03 100644
> --- a/drivers/pci/vgaarb.c
> +++ b/drivers/pci/vgaarb.c
> @@ -61,7 +61,6 @@ static bool vga_arbiter_used;
> static DEFINE_SPINLOCK(vga_lock);
> static DECLARE_WAIT_QUEUE_HEAD(vga_wait_queue);
>
> -
> static const char *vga_iostate_to_str(unsigned int iostate)
> {
> /* Ignore VGA_RSRC_IO and VGA_RSRC_MEM */
> @@ -77,10 +76,12 @@ static const char *vga_iostate_to_str(unsigned int
> iostate)
> return "none";
> }
>
> -static int vga_str_to_iostate(char *buf, int str_size, int *io_state)
> +static int vga_str_to_iostate(char *buf, int str_size, unsigned int
> *io_state)
> {
> - /* we could in theory hand out locks on IO and mem
> - * separately to userspace but it can cause deadlocks */
> + /*
> + * we could in theory hand out locks on IO and mem
> + * separately to userspace but it can cause deadlocks
> + */
Omit all the comment formatting changes. They are distractions from the
vga_str_to_iostate() parameter change.
I think this patch should be the single line change to the
vga_str_to_iostate() prototype so it matches the callers.
If you want to do the other comment formatting changes, they're fine,
but they should be all together in a separate patch that clearly
doesn't change the generated code.
Bjorn
[Intel-gfx] [PATCH v2 19/19] drm/i915: Do state check for color management changes
From: Ville Syrjälä
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening. Maybe we should have
an extra knob for this that we could enable in CI?
v2: Skip for initial_commit to avoid FDI dotclock
sanity checks/etc. tripping up
Reviewed-by: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_modeset_verify.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 138144a65a45..1ee3636f1b97 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -231,6 +231,8 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_crtc_state *new_crtc_state)
{
if (!intel_crtc_needs_modeset(new_crtc_state) &&
+ (!intel_crtc_needs_color_update(new_crtc_state) ||
+new_crtc_state->inherited) &&
!intel_crtc_needs_fastset(new_crtc_state))
return;
--
2.39.3
[Intel-gfx] [PATCH v2 18/19] drm/i915/dsb: Re-instate DSB for LUT updates
From: Ville Syrjälä With all the known issues sorted out we can start to use DSB to load the LUTs. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index c5a9ea53a718..213063872f26 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1814,9 +1814,6 @@ void intel_color_prepare_commit(struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - /* FIXME DSB has issues loading LUTs, disable it for now */ - return; - if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state)) return; -- 2.39.3
[Intel-gfx] [PATCH v2 17/19] drm/i915/dsb: Use DEwake to combat PkgC latency
From: Ville Syrjälä
Normally we could be in a deep PkgC state all the way up to the
point when DSB starts its execution at the transcoders undelayed
vblank. The DSB will then have to wait for the hardware to
wake up before it can execute anything. This will waste a huge
chunk of the vblank time just waiting, and risks the DSB execution
spilling into the vertical active period. That will be very bad,
especially when programming the LUTs as the anti-collision logic
will cause DSB to corrupt LUT writes during vertical active.
To avoid these problems we can instruct the DSB to pre-wake the
display engined on a specific scanline so that everything will
be 100% ready to go when we hit the transcoder's undelayed vblank.
One annoyance is that the scanline is specified as just that,
a single scanline. So if we happen to start the DSB execution
after passing said scanline no DEwake will happen and we may drop
back into some PkgC state before reaching the transcoder's undelayed
vblank. To prevent that we'll use the "force DEwake" bit to manually
force the display engined to stay awake. We'll then have to clear
the force bit again after the DSB is done (the force bit remains
effective even when the DSB is otherwise disabled).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 2 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 91 +++---
drivers/gpu/drm/i915/display/intel_dsb.h | 3 +-
3 files changed, 82 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index b3dd4013d058..c5a9ea53a718 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1824,7 +1824,7 @@ void intel_color_prepare_commit(struct intel_crtc_state
*crtc_state)
if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
return;
- crtc_state->dsb = intel_dsb_prepare(crtc, 1024);
+ crtc_state->dsb = intel_dsb_prepare(crtc_state, 1024);
if (!crtc_state->dsb)
return;
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 73d609507f24..3e32aa49b8eb 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -7,11 +7,16 @@
#include "gem/i915_gem_internal.h"
#include "i915_drv.h"
+#include "i915_irq.h"
#include "i915_reg.h"
+#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dsb.h"
#include "intel_dsb_regs.h"
+#include "intel_vblank.h"
+#include "intel_vrr.h"
+#include "skl_watermark.h"
struct i915_vma;
@@ -47,6 +52,8 @@ struct intel_dsb {
* register.
*/
unsigned int ins_start_offset;
+
+ int dewake_scanline;
};
/**
@@ -297,17 +304,40 @@ static void intel_dsb_align_tail(struct intel_dsb *dsb)
void intel_dsb_finish(struct intel_dsb *dsb)
{
+ struct intel_crtc *crtc = dsb->crtc;
+
+ /*
+* DSB_FORCE_DEWAKE remains active even after DSB is
+* disabled, so make sure to clear it (if set during
+* intel_dsb_commit()).
+*/
+ intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id),
+ DSB_FORCE_DEWAKE, 0);
+
intel_dsb_align_tail(dsb);
}
-/**
- * intel_dsb_commit() - Trigger workload execution of DSB.
- * @dsb: DSB context
- * @wait_for_vblank: wait for vblank before executing
- *
- * This function is used to do actual write to hardware using DSB.
- */
-void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank)
+static int intel_dsb_dewake_scanline(const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ const struct drm_display_mode *adjusted_mode =
_state->hw.adjusted_mode;
+ unsigned int latency = skl_watermark_max_latency(i915);
+ int vblank_start;
+
+ if (crtc_state->vrr.enable) {
+ vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
+ } else {
+ vblank_start = adjusted_mode->crtc_vblank_start;
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+ vblank_start = DIV_ROUND_UP(vblank_start, 2);
+ }
+
+ return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode,
latency));
+}
+
+static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
+ unsigned int dewake_scanline)
{
struct intel_crtc *crtc = dsb->crtc;
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -325,14 +355,49 @@ void intel_dsb_commit(struct intel_dsb *dsb, bool
wait_for_vblank)
}
intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id),
- (wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0) |
- DSB_ENABLE);
+ ctrl | DSB_ENABLE);
+
[Intel-gfx] [PATCH v2 16/19] drm/i915: Introudce intel_crtc_scanline_to_hw()
From: Ville Syrjälä
Add a helper to convert our idea of a scanline to the hw's idea
of the same scanline (ie. apply crtc->scanline_offset in reverse).
We'll need this to tell the DSB do stuff on a specific scanline.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vblank.c | 14 ++
drivers/gpu/drm/i915/display/intel_vblank.h | 1 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
b/drivers/gpu/drm/i915/display/intel_vblank.c
index f5659ebd08eb..2cec2abf9746 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -251,6 +251,20 @@ static int __intel_get_crtc_scanline(struct intel_crtc
*crtc)
return (position + crtc->scanline_offset) % vtotal;
}
+int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)
+{
+ const struct drm_vblank_crtc *vblank =
+ >base.dev->vblank[drm_crtc_index(>base)];
+ const struct drm_display_mode *mode = >hwmode;
+ int vtotal;
+
+ vtotal = mode->crtc_vtotal;
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ vtotal /= 2;
+
+ return (scanline + vtotal - crtc->scanline_offset) % vtotal;
+}
+
static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
bool in_vblank_irq,
int *vpos, int *hpos,
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h
b/drivers/gpu/drm/i915/display/intel_vblank.h
index 08e706b29149..17636f140c71 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.h
+++ b/drivers/gpu/drm/i915/display/intel_vblank.h
@@ -22,5 +22,6 @@ void intel_wait_for_pipe_scanline_stopped(struct intel_crtc
*crtc);
void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc);
void intel_crtc_update_active_timings(const struct intel_crtc_state
*crtc_state,
bool vrr_enable);
+int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline);
#endif /* __INTEL_VBLANK_H__ */
--
2.39.3
[Intel-gfx] [PATCH v2 12/19] drm/i915/dsb: Load LUTs using the DSB during vblank
From: Ville Syrjälä
Loading LUTs with the DSB outside of vblank doesn't really
work due to the palette anti-collision logic. Apparently the
DSB register writes don't get stalled like CPU mmio writes
do and instead we end up corrupting the LUT entries. Disabling
the anti-collision logic would allow us to successfully load
the LUT outside of vblank, but presumably that risks the LUT
reads from the scanout (temportarily) getting corrupted data
from the LUT instead.
The anti-collision logic isn't active during vblank so that
is when we can successfully load the LUT with the DSB. That is
what we want to do anyway to avoid tearing.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 30
drivers/gpu/drm/i915/display/intel_color.h | 2 ++
drivers/gpu/drm/i915/display/intel_crtc.c| 4 ++-
drivers/gpu/drm/i915/display/intel_display.c | 3 ++
4 files changed, 32 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 2db9d1d6dadd..077e45372dab 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1660,12 +1660,6 @@ static void icl_load_luts(const struct intel_crtc_state
*crtc_state)
MISSING_CASE(crtc_state->gamma_mode);
break;
}
-
- if (crtc_state->dsb) {
- intel_dsb_finish(crtc_state->dsb);
- intel_dsb_commit(crtc_state->dsb, false);
- intel_dsb_wait(crtc_state->dsb);
- }
}
static void vlv_load_luts(const struct intel_crtc_state *crtc_state)
@@ -1772,6 +1766,9 @@ void intel_color_load_luts(const struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ if (crtc_state->dsb)
+ return;
+
i915->display.funcs.color->load_luts(crtc_state);
}
@@ -1788,6 +1785,9 @@ void intel_color_commit_arm(const struct intel_crtc_state
*crtc_state)
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
i915->display.funcs.color->color_commit_arm(crtc_state);
+
+ if (crtc_state->dsb)
+ intel_dsb_commit(crtc_state->dsb, true);
}
void intel_color_post_update(const struct intel_crtc_state *crtc_state)
@@ -1801,6 +1801,7 @@ void intel_color_post_update(const struct
intel_crtc_state *crtc_state)
void intel_color_prepare_commit(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
/* FIXME DSB has issues loading LUTs, disable it for now */
return;
@@ -1813,6 +1814,12 @@ void intel_color_prepare_commit(struct intel_crtc_state
*crtc_state)
return;
crtc_state->dsb = intel_dsb_prepare(crtc, 1024);
+ if (!crtc_state->dsb)
+ return;
+
+ i915->display.funcs.color->load_luts(crtc_state);
+
+ intel_dsb_finish(crtc_state->dsb);
}
void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
@@ -1824,6 +1831,17 @@ void intel_color_cleanup_commit(struct intel_crtc_state
*crtc_state)
crtc_state->dsb = NULL;
}
+void intel_color_wait_commit(const struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->dsb)
+ intel_dsb_wait(crtc_state->dsb);
+}
+
+bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state)
+{
+ return crtc_state->dsb;
+}
+
static bool intel_can_preload_luts(const struct intel_crtc_state
*new_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_color.h
b/drivers/gpu/drm/i915/display/intel_color.h
index 8002492be709..8ecd36149def 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -19,6 +19,8 @@ void intel_color_crtc_init(struct intel_crtc *crtc);
int intel_color_check(struct intel_crtc_state *crtc_state);
void intel_color_prepare_commit(struct intel_crtc_state *crtc_state);
void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state);
+bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state);
+void intel_color_wait_commit(const struct intel_crtc_state *crtc_state);
void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state);
void intel_color_commit_arm(const struct intel_crtc_state *crtc_state);
void intel_color_post_update(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 182c6dd64f47..36c9b590a058 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -24,6 +24,7 @@
#include "intel_display_trace.h"
#include "intel_display_types.h"
#include "intel_drrs.h"
+#include "intel_dsb.h"
#include "intel_dsi.h"
[Intel-gfx] [PATCH v2 15/19] drm/i915: Introduce skl_watermark_max_latency()
From: Ville Syrjälä
The DSB code will want to know the maximum PkgC latency
it has to contend with. Add a helper to expose that
information.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 14 ++
drivers/gpu/drm/i915/display/skl_watermark.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index d1245c847f1c..a31adbca9dbc 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3719,3 +3719,17 @@ void skl_watermark_debugfs_register(struct
drm_i915_private *i915)
debugfs_create_file("i915_sagv_status", 0444,
minor->debugfs_root, i915,
_sagv_status_fops);
}
+
+unsigned int skl_watermark_max_latency(struct drm_i915_private *i915)
+{
+ int level;
+
+ for (level = i915->display.wm.num_levels - 1; level >= 0; level--) {
+ unsigned int latency = skl_wm_latency(i915, level, NULL);
+
+ if (latency)
+ return latency;
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h
b/drivers/gpu/drm/i915/display/skl_watermark.h
index f91a3d4ddc07..edb61e33df83 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -46,6 +46,8 @@ void skl_watermark_ipc_update(struct drm_i915_private *i915);
bool skl_watermark_ipc_enabled(struct drm_i915_private *i915);
void skl_watermark_debugfs_register(struct drm_i915_private *i915);
+unsigned int skl_watermark_max_latency(struct drm_i915_private *i915);
+
void skl_wm_init(struct drm_i915_private *i915);
struct intel_dbuf_state {
--
2.39.3
[Intel-gfx] [PATCH v2 14/19] drm/i915/dsb: Evade transcoder undelayed vblank when using DSB
From: Ville Syrjälä We want to start the DSB execution from the transcoder's undelayed vblank, so in order to guarantee atomicity with the all the other mmio register writes we need to evade both vblanks. Note that currently we don't add any vblank delay, so this is effectively a nop. But in the future when we start to program double buffered registers from the DSB we'll need to delay the pipe's vblank to provide the register programming "window2" for the DSB. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_crtc.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 36c9b590a058..ff0ebdf7cde3 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -519,8 +519,12 @@ void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state) /* * M/N is double buffered on the transcoder's undelayed vblank, * so with seamless M/N we must evade both vblanks. +* +* DSB execution waits for the transcoder's undelayed vblank, +* hence we must kick off the commit before that. */ - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) + if (new_crtc_state->dsb || + (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))) min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; if (min <= 0 || max <= 0) -- 2.39.3
[Intel-gfx] [PATCH v2 13/19] drm/i915/dsb: Use non-posted register writes for legacy LUT
From: Ville Syrjälä The DSB has problems writing the legacy LUT. The two workarounds I've discoverted are: - write each entry twice back to back - use non-posted writes Let's use non-posted writes as that seems a bit more standard. TODO: measure which is faster Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 077e45372dab..b3dd4013d058 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1265,9 +1265,20 @@ static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state, lut = blob->data; + /* +* DSB fails to correctly load the legacy LUT +* unless we either write each entry twice, +* or use non-posted writes +*/ + if (crtc_state->dsb) + intel_dsb_nonpost_start(crtc_state->dsb); + for (i = 0; i < 256; i++) ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), i9xx_lut_8([i])); + + if (crtc_state->dsb) + intel_dsb_nonpost_end(crtc_state->dsb); } static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state, -- 2.39.3
[Intel-gfx] [PATCH v2 11/19] drm/i915/dsb: Don't use DSB to load the LUTs during full modeset
From: Ville Syrjälä Using the DSB for LUT loading during full modesets would require some actual though. Let's just use mmio for the time being. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 2d5640aab4d8..2db9d1d6dadd 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1805,6 +1805,10 @@ void intel_color_prepare_commit(struct intel_crtc_state *crtc_state) /* FIXME DSB has issues loading LUTs, disable it for now */ return; + if (!crtc_state->hw.active || + intel_crtc_needs_modeset(crtc_state)) + return; + if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut) return; -- 2.39.3
[Intel-gfx] [PATCH v2 10/19] drm/i915/dsb: Add support for non-posted DSB registers writes
From: Ville Syrjälä
Writing specific transcoder registers (and as it turns out, the
legacy LUT as well) via DSB needs a magic sequence to emit
non-posted register writes. Add a helper for this.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c | 20
drivers/gpu/drm/i915/display/intel_dsb.h | 3 +++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 6be353fdc7fc..73d609507f24 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -261,6 +261,26 @@ void intel_dsb_noop(struct intel_dsb *dsb, int count)
DSB_OPCODE_NOOP << DSB_OPCODE_SHIFT);
}
+void intel_dsb_nonpost_start(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ enum pipe pipe = crtc->pipe;
+
+ intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id),
+ DSB_NON_POSTED, DSB_NON_POSTED);
+ intel_dsb_noop(dsb, 4);
+}
+
+void intel_dsb_nonpost_end(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ enum pipe pipe = crtc->pipe;
+
+ intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id),
+ DSB_NON_POSTED, 0);
+ intel_dsb_noop(dsb, 4);
+}
+
static void intel_dsb_align_tail(struct intel_dsb *dsb)
{
u32 aligned_tail, tail;
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 983b0d58ad44..54e9e1dc31ee 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -22,6 +22,9 @@ void intel_dsb_reg_write(struct intel_dsb *dsb,
void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
i915_reg_t reg, u32 mask, u32 val);
void intel_dsb_noop(struct intel_dsb *dsb, int count);
+void intel_dsb_nonpost_start(struct intel_dsb *dsb);
+void intel_dsb_nonpost_end(struct intel_dsb *dsb);
+
void intel_dsb_commit(struct intel_dsb *dsb,
bool wait_for_vblank);
void intel_dsb_wait(struct intel_dsb *dsb);
--
2.39.3
[Intel-gfx] [PATCH v2 09/19] drm/i915/dsb: Introduce intel_dsb_reg_write_masked()
From: Ville Syrjälä
Add a function for emitting masked register writes.
Note that the mask is implemented through bvyte enables,
so can only mask off aligned 8bit sets of bits.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c | 18 ++
drivers/gpu/drm/i915/display/intel_dsb.h | 2 ++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 4ef799c087b4..6be353fdc7fc 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -234,6 +234,24 @@ void intel_dsb_reg_write(struct intel_dsb *dsb,
}
}
+static u32 intel_dsb_mask_to_byte_en(u32 mask)
+{
+ return (!!(mask & 0xff00) << 3 |
+ !!(mask & 0x00ff) << 2 |
+ !!(mask & 0xff00) << 1 |
+ !!(mask & 0x00ff) << 0);
+}
+
+/* Note: mask implemented via byte enables! */
+void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
+ i915_reg_t reg, u32 mask, u32 val)
+{
+ intel_dsb_emit(dsb, val,
+ (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
+ (intel_dsb_mask_to_byte_en(mask) << DSB_BYTE_EN_SHIFT) |
+ i915_mmio_reg_offset(reg));
+}
+
void intel_dsb_noop(struct intel_dsb *dsb, int count)
{
int i;
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 5a08bc21beda..983b0d58ad44 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -19,6 +19,8 @@ void intel_dsb_finish(struct intel_dsb *dsb);
void intel_dsb_cleanup(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb,
i915_reg_t reg, u32 val);
+void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
+ i915_reg_t reg, u32 mask, u32 val);
void intel_dsb_noop(struct intel_dsb *dsb, int count);
void intel_dsb_commit(struct intel_dsb *dsb,
bool wait_for_vblank);
--
2.39.3
[Intel-gfx] [PATCH v2 08/19] drm/i915/dsb: Introduce intel_dsb_noop()
From: Ville Syrjälä
Add a helper for emitting a number of DSB NOOPs commands.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 22c716ee75e2..4ef799c087b4 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -234,6 +234,15 @@ void intel_dsb_reg_write(struct intel_dsb *dsb,
}
}
+void intel_dsb_noop(struct intel_dsb *dsb, int count)
+{
+ int i;
+
+ for (i = 0; i < count; i++)
+ intel_dsb_emit(dsb, 0,
+ DSB_OPCODE_NOOP << DSB_OPCODE_SHIFT);
+}
+
static void intel_dsb_align_tail(struct intel_dsb *dsb)
{
u32 aligned_tail, tail;
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index b8148b47022d..5a08bc21beda 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -19,6 +19,7 @@ void intel_dsb_finish(struct intel_dsb *dsb);
void intel_dsb_cleanup(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb,
i915_reg_t reg, u32 val);
+void intel_dsb_noop(struct intel_dsb *dsb, int count);
void intel_dsb_commit(struct intel_dsb *dsb,
bool wait_for_vblank);
void intel_dsb_wait(struct intel_dsb *dsb);
--
2.39.3
[Intel-gfx] [PATCH v2 07/19] drm/i915/dsb: Don't use indexed writes when byte enables are not all set
From: Ville Syrjälä
The indexed write instruction doesn't support byte-enables, so
if the non-indexed write used those we must not convert it to
an indexed write.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index a20ae5313d23..22c716ee75e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -149,7 +149,7 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb
*dsb,
if (dsb->free_pos == 0)
return false;
- prev_opcode = buf[dsb->ins_start_offset + 1] >> DSB_OPCODE_SHIFT;
+ prev_opcode = buf[dsb->ins_start_offset + 1] & ~DSB_REG_VALUE_MASK;
prev_reg = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg);
@@ -157,12 +157,18 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb
*dsb,
static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, i915_reg_t
reg)
{
- return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_MMIO_WRITE, reg);
+ /* only full byte-enables can be converted to indexed writes */
+ return intel_dsb_prev_ins_is_write(dsb,
+ DSB_OPCODE_MMIO_WRITE <<
DSB_OPCODE_SHIFT |
+ DSB_BYTE_EN << DSB_BYTE_EN_SHIFT,
+ reg);
}
static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb,
i915_reg_t reg)
{
- return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_INDEXED_WRITE, reg);
+ return intel_dsb_prev_ins_is_write(dsb,
+ DSB_OPCODE_INDEXED_WRITE <<
DSB_OPCODE_SHIFT,
+ reg);
}
/**
--
2.39.3
[Intel-gfx] [PATCH v2 06/19] drm/i915/dsb: Avoid corrupting the first register write
From: Ville Syrjälä i915_gem_object_create_internal() does not hand out zeroed memory. Thus we may confuse whatever stale garbage is in there as a previous register write and mistakenly handle the first actual register write as an indexed write. This can end up corrupting the instruction sufficiently well to lose the entire register write. Make sure we've actually emitted a previous instruction before attemting indexed register write merging. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 093b2567883d..a20ae5313d23 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -141,6 +141,14 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, const u32 *buf = dsb->cmd_buf; u32 prev_opcode, prev_reg; + /* +* Nothing emitted yet? Must check before looking +* at the actual data since i915_gem_object_create_internal() +* does *not* give you zeroed memory! +*/ + if (dsb->free_pos == 0) + return false; + prev_opcode = buf[dsb->ins_start_offset + 1] >> DSB_OPCODE_SHIFT; prev_reg = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK; -- 2.39.3
[Intel-gfx] [PATCH v2 05/19] drm/i915/dsb: Define the contents of some intstructions bit better
From: Ville Syrjälä
Add some defines to specify what goes inside certain DSB
instructions.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 42911abcd3ab..093b2567883d 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -70,17 +70,21 @@ struct intel_dsb {
#define DSB_OPCODE_SHIFT 24
#define DSB_OPCODE_NOOP0x0
#define DSB_OPCODE_MMIO_WRITE 0x1
+#define DSB_BYTE_EN 0xf
+#define DSB_BYTE_EN_SHIFT20
+#define DSB_REG_VALUE_MASK 0xf
#define DSB_OPCODE_WAIT_USEC 0x2
-#define DSB_OPCODE_WAIT_LINES 0x3
+#define DSB_OPCODE_WAIT_SCANLINE 0x3
#define DSB_OPCODE_WAIT_VBLANKS0x4
#define DSB_OPCODE_WAIT_DSL_IN 0x5
#define DSB_OPCODE_WAIT_DSL_OUT0x6
+#define DSB_SCANLINE_UPPER_SHIFT 20
+#define DSB_SCANLINE_LOWER_SHIFT 0
#define DSB_OPCODE_INTERRUPT 0x7
#define DSB_OPCODE_INDEXED_WRITE 0x9
+/* see DSB_REG_VALUE_MASK */
#define DSB_OPCODE_POLL0xA
-#define DSB_BYTE_EN0xF
-#define DSB_BYTE_EN_SHIFT 20
-#define DSB_REG_VALUE_MASK 0xf
+/* see DSB_REG_VALUE_MASK */
static bool assert_dsb_has_room(struct intel_dsb *dsb)
{
--
2.39.3
[Intel-gfx] [PATCH v2 03/19] drm/i915/dsb: Dump the DSB command buffer when DSB fails
From: Ville Syrjälä
Dump the full DSB command buffers and head/tail pointers if the
the DSB hasn't completed its job in time.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c | 33 +---
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 97e593d9f100..42911abcd3ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -93,6 +93,22 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb)
crtc->base.base.id, crtc->base.name, dsb->id);
}
+static void intel_dsb_dump(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ const u32 *buf = dsb->cmd_buf;
+ int i;
+
+ drm_dbg_kms(>drm, "[CRTC:%d:%s] DSB %d commands {\n",
+ crtc->base.base.id, crtc->base.name, dsb->id);
+ for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4)
+ drm_dbg_kms(>drm,
+ " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]);
+ drm_dbg_kms(>drm, "}\n");
+}
+
static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
enum dsb_id id)
{
@@ -258,10 +274,21 @@ void intel_dsb_wait(struct intel_dsb *dsb)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1))
+ if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) {
+ u32 offset = i915_ggtt_offset(dsb->vma);
+
+ intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id),
+ DSB_ENABLE | DSB_HALT);
+
drm_err(_priv->drm,
- "[CRTC:%d:%s] DSB %d timed out waiting for idle\n",
- crtc->base.base.id, crtc->base.name, dsb->id);
+ "[CRTC:%d:%s] DSB %d timed out waiting for idle
(current head=0x%x, head=0x%x, tail=0x%x)\n",
+ crtc->base.base.id, crtc->base.name, dsb->id,
+ intel_de_read_fw(dev_priv, DSB_CURRENT_HEAD(pipe,
dsb->id)) - offset,
+ intel_de_read_fw(dev_priv, DSB_HEAD(pipe, dsb->id)) -
offset,
+ intel_de_read_fw(dev_priv, DSB_TAIL(pipe, dsb->id)) -
offset);
+
+ intel_dsb_dump(dsb);
+ }
/* Attempt to reset it */
dsb->free_pos = 0;
--
2.39.3
[Intel-gfx] [PATCH v2 04/19] drm/i915/dsb: Define more DSB bits
From: Ville Syrjälä Define all the DSB register bits so I don't have to look through bspec to find them. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb_regs.h | 31 +++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dsb_regs.h b/drivers/gpu/drm/i915/display/intel_dsb_regs.h index 12535d478775..210e2665441d 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dsb_regs.h @@ -37,6 +37,19 @@ #define DSB_DEBUG(pipe, id)_MMIO(DSBSL_INSTANCE(pipe, id) + 0x14) #define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c) #define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24) +#define DSB_HP_IDLE_STATUS REG_BIT(31) +#define DSB_DEWAKE_STATUSREG_BIT(30) +#define DSB_REQARB_SM_STATE_MASK REG_GENMASK(29, 27) +#define DSB_SAFE_WINDOW_LIVE REG_BIT(26) +#define DSB_VTDFAULT_ARB_SM_STATE_MASK REG_GENMASK(25, 23) +#define DSB_TLBTRANS_SM_STATE_MASK REG_GENMASK(21, 20) +#define DSB_SAFE_WINDOW REG_BIT(19) +#define DSB_POINTERS_SM_STATE_MASK REG_GENMASK(18, 17) +#define DSB_BUSY_ON_DELAYED_VBLANK REG_BIT(16) +#define DSB_MMIO_ARB_SM_STATE_MASK REG_GENMASK(15, 13) +#define DSB_MMIO_INST_SM_STATE_MASK REG_GENMASK(11, 7) +#define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4) +#define DSB_RUN_SM_STATE_MASKREG_GENMASK(2, 0) #define DSB_INTERRUPT(pipe, id)_MMIO(DSBSL_INSTANCE(pipe, id) + 0x28) #define DSB_ATS_FAULT_INT_EN REG_BIT(20) #define DSB_GTT_FAULT_INT_EN REG_BIT(19) @@ -58,10 +71,28 @@ #define DSB_RM_READY_TIMEOUT_VALUE(x) REG_FIELD_PREP(DSB_RM_READY_TIMEOUT_VALUE, (x)) /* usec */ #define DSB_RMTIMEOUTREG_CAPTURE(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x34) #define DSB_PMCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x38) +#define DSB_ENABLE_DEWAKEREG_BIT(31) +#define DSB_SCANLINE_FOR_DEWAKE_MASK REG_GENMASK(30, 0) +#define DSB_SCANLINE_FOR_DEWAKE(x) REG_FIELD_PREP(DSB_SCANLINE_FOR_DEWAKE_MASK, (x)) #define DSB_PMCTRL_2(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x3c) +#define DSB_MMIOGEN_DEWAKE_DIS REG_BIT(31) +#define DSB_FORCE_DEWAKE REG_BIT(23) +#define DSB_BLOCK_DEWAKE_EXTENSION REG_BIT(15) +#define DSB_OVERRIDE_DC5_DC6_OK REG_BIT(7) #define DSB_PF_LN_LOWER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x40) #define DSB_PF_LN_UPPER(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x44) #define DSB_BUFRPT_CNT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x48) #define DSB_CHICKEN(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xf0) +#define DSB_FORCE_DMA_SYNC_RESET REG_BIT(31) +#define DSB_FORCE_VTD_ENGIE_RESETREG_BIT(30) +#define DSB_DISABLE_IPC_DEMOTE REG_BIT(29) +#define DSB_SKIP_WAITS_ENREG_BIT(23) +#define DSB_EXTEND_HP_IDLE REG_BIT(16) +#define DSB_CTRL_WAIT_SAFE_WINDOWREG_BIT(15) +#define DSB_CTRL_NO_WAIT_VBLANK REG_BIT(14) +#define DSB_INST_WAIT_SAFE_WINDOWREG_BIT(7) +#define DSB_INST_NO_WAIT_VBLANK REG_BIT(6) +#define DSB_MMIOGEN_DEWAKE_DIS_CHICKEN REG_BIT(2) +#define DSB_DISABLE_MMIO_COUNT_FOR_INDEXED REG_BIT(0) #endif /* __INTEL_DSB_REGS_H__ */ -- 2.39.3
[Intel-gfx] [PATCH v2 02/19] drm/i915/dsb: Use non-locked register access
From: Ville Syrjälä
Avoid the locking overhead for DSB registers. We don't need the locks
and intel_dsb_commit() in particular needs to be called from the
vblank evade critical section and thus needs to be fast.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index bed058d2c3ac..97e593d9f100 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -96,7 +96,7 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb)
static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
enum dsb_id id)
{
- return intel_de_read(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY;
+ return intel_de_read_fw(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY;
}
static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
@@ -243,13 +243,13 @@ void intel_dsb_commit(struct intel_dsb *dsb, bool
wait_for_vblank)
return;
}
- intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id),
- (wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0) |
- DSB_ENABLE);
- intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id),
- i915_ggtt_offset(dsb->vma));
- intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id),
- i915_ggtt_offset(dsb->vma) + tail);
+ intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id),
+ (wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0) |
+ DSB_ENABLE);
+ intel_de_write_fw(dev_priv, DSB_HEAD(pipe, dsb->id),
+ i915_ggtt_offset(dsb->vma));
+ intel_de_write_fw(dev_priv, DSB_TAIL(pipe, dsb->id),
+ i915_ggtt_offset(dsb->vma) + tail);
}
void intel_dsb_wait(struct intel_dsb *dsb)
@@ -266,7 +266,7 @@ void intel_dsb_wait(struct intel_dsb *dsb)
/* Attempt to reset it */
dsb->free_pos = 0;
dsb->ins_start_offset = 0;
- intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), 0);
+ intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), 0);
}
/**
--
2.39.3
[Intel-gfx] [PATCH v2 01/19] drm/i915: Constify LUT entries in checker
From: Ville Syrjälä
The LUT checker doesn't modify the LUT entries so make them const.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 8966e6560516..2d5640aab4d8 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2848,16 +2848,16 @@ static int icl_pre_csc_lut_precision(const struct
intel_crtc_state *crtc_state)
return 16;
}
-static bool err_check(struct drm_color_lut *lut1,
- struct drm_color_lut *lut2, u32 err)
+static bool err_check(const struct drm_color_lut *lut1,
+ const struct drm_color_lut *lut2, u32 err)
{
return ((abs((long)lut2->red - lut1->red)) <= err) &&
((abs((long)lut2->blue - lut1->blue)) <= err) &&
((abs((long)lut2->green - lut1->green)) <= err);
}
-static bool intel_lut_entries_equal(struct drm_color_lut *lut1,
- struct drm_color_lut *lut2,
+static bool intel_lut_entries_equal(const struct drm_color_lut *lut1,
+ const struct drm_color_lut *lut2,
int lut_size, u32 err)
{
int i;
@@ -2874,7 +2874,7 @@ static bool intel_lut_equal(const struct
drm_property_blob *blob1,
const struct drm_property_blob *blob2,
int check_size, int precision)
{
- struct drm_color_lut *lut1, *lut2;
+ const struct drm_color_lut *lut1, *lut2;
int lut_size1, lut_size2;
u32 err;
--
2.39.3
[Intel-gfx] [PATCH v2 00/19] drm/i915: Load LUTs with DSB
From: Ville Syrjälä Another attempt at re-enabling DSB based LUT loads. The main change from the last attempt is that we now use the DSB's DEwake mechanism to combat PkgC latency which was causing the LUT to not always load correctly (due to the anti-collision logic not working correctly for DSB LUT accesses). I also got the non-posted writes working correctly which lets us load the legacy LUT without the "write each entry twice" trick I used previously. Ville Syrjälä (19): drm/i915: Constify LUT entries in checker drm/i915/dsb: Use non-locked register access drm/i915/dsb: Dump the DSB command buffer when DSB fails drm/i915/dsb: Define more DSB bits drm/i915/dsb: Define the contents of some intstructions bit better drm/i915/dsb: Avoid corrupting the first register write drm/i915/dsb: Don't use indexed writes when byte enables are not all set drm/i915/dsb: Introduce intel_dsb_noop() drm/i915/dsb: Introduce intel_dsb_reg_write_masked() drm/i915/dsb: Add support for non-posted DSB registers writes drm/i915/dsb: Don't use DSB to load the LUTs during full modeset drm/i915/dsb: Load LUTs using the DSB during vblank drm/i915/dsb: Use non-posted register writes for legacy LUT drm/i915/dsb: Evade transcoder undelayed vblank when using DSB drm/i915: Introduce skl_watermark_max_latency() drm/i915: Introudce intel_crtc_scanline_to_hw() drm/i915/dsb: Use DEwake to combat PkgC latency drm/i915/dsb: Re-instate DSB for LUT updates drm/i915: Do state check for color management changes drivers/gpu/drm/i915/display/intel_color.c| 58 +++-- drivers/gpu/drm/i915/display/intel_color.h| 2 + drivers/gpu/drm/i915/display/intel_crtc.c | 10 +- drivers/gpu/drm/i915/display/intel_display.c | 3 + drivers/gpu/drm/i915/display/intel_dsb.c | 217 +++--- drivers/gpu/drm/i915/display/intel_dsb.h | 9 +- drivers/gpu/drm/i915/display/intel_dsb_regs.h | 31 +++ .../drm/i915/display/intel_modeset_verify.c | 2 + drivers/gpu/drm/i915/display/intel_vblank.c | 14 ++ drivers/gpu/drm/i915/display/intel_vblank.h | 1 + drivers/gpu/drm/i915/display/skl_watermark.c | 14 ++ drivers/gpu/drm/i915/display/skl_watermark.h | 2 + 12 files changed, 317 insertions(+), 46 deletions(-) -- 2.39.3
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: implement internal workqueues (rev2)
== Series Details ==
Series: drm/i915: implement internal workqueues (rev2)
URL : https://patchwork.freedesktop.org/series/118947/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13237 -> Patchwork_118947v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118947v2/index.html
Participating hosts (41 -> 40)
--
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118947v2:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-b-dp-6:
- {bat-adlp-11}: NOTRUN -> [FAIL][1] +2 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118947v2/bat-adlp-11/igt@kms_pipe_crc_basic@nonblocking-...@pipe-b-dp-6.html
Known issues
Here are the changes found in Patchwork_118947v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][2] -> [DMESG-FAIL][3] ([i915#5334])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13237/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118947v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [PASS][4] -> [ABORT][5] ([i915#4983] / [i915#7461] /
[i915#7913] / [i915#8347])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13237/bat-rpls-2/igt@i915_selftest@l...@reset.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118947v2/bat-rpls-2/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1:
- bat-dg2-8: [PASS][6] -> [FAIL][7] ([i915#7932]) +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13237/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118947v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
Possible fixes
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [DMESG-FAIL][8] ([i915#7269]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13237/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118947v2/bat-mtlp-8/igt@i915_selftest@l...@requests.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- {bat-adlp-11}: [DMESG-WARN][10] ([i915#6868]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13237/bat-adlp-11/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118947v2/bat-adlp-11/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- {bat-adlp-11}: [SKIP][12] ([i915#3546]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13237/bat-adlp-11/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118947v2/bat-adlp-11/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html
* {igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-5}:
- {bat-adlp-11}: [ABORT][14] ([i915#4423]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13237/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-d-dp-5.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118947v2/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-d-dp-5.html
Warnings
* igt@i915_selftest@live@reset:
- bat-rpls-1: [ABORT][16] ([i915#4983] / [i915#7461] / [i915#8347]
/ [i915#8384]) -> [ABORT][17] ([i915#4983] / [i915#7461] / [i915#7981] /
[i915#8347] / [i915#8384])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13237/bat-rpls-1/igt@i915_selftest@l...@reset.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118947v2/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-a-edp-1:
- bat-adlp-6: [ABORT][18] -> [ABORT][19] ([i915#8434])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13237/bat-adlp-6/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-a-edp-1.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118947v2/bat-adlp-6/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-a-edp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: implement internal workqueues (rev2)
== Series Details == Series: drm/i915: implement internal workqueues (rev2) URL : https://patchwork.freedesktop.org/series/118947/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: implement internal workqueues (rev2)
== Series Details == Series: drm/i915: implement internal workqueues (rev2) URL : https://patchwork.freedesktop.org/series/118947/ State : warning == Summary == Error: dim checkpatch failed 7c73f73cd55c drm/i915: use pointer to i915 instead of rpm in wakeref f7c19d8c6ca6 drm/i915: add a dedicated workqueue inside drm_i915_private -:624: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!dev_priv->unordered_wq" #624: FILE: drivers/gpu/drm/i915/i915_driver.c:142: + if (dev_priv->unordered_wq == NULL) total: 0 errors, 0 warnings, 1 checks, 514 lines checked c56c8365e283 drm/i915/selftests: add local workqueue for SW fence selftest -:30: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!wq" #30: FILE: drivers/gpu/drm/i915/selftests/i915_sw_fence.c:530: + if (wq == NULL) total: 0 errors, 0 warnings, 1 checks, 38 lines checked
Re: [Intel-gfx] [PATCH] drm/i915/gsc: Fix error code in intel_gsc_uc_heci_cmd_submit_nonpriv()
That was my bad, i could have sword i'd fixed that before the final rev. Thanks
for fixing this.
nit: below function applies to MTL only which at the moment is still
force-probed, so not sure if the fixes tag is significant.
Reviewed-by: Alan Previn
On Tue, 2023-06-06 at 11:22 +0300, Dan Carpenter wrote:
> This should return negative -EAGAIN instead of positive EAGAIN.
>
> Fixes: e5e1e6d28ebc ("drm/i915/pxp: Add MTL helpers to submit Heci-Cmd-Packet
> to GSC")
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
> b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
> index 579c0f5a1438..42218ae6ef13 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
> @@ -202,7 +202,7 @@ intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc
> *gsc,
> if (++trials < 10)
> goto retry;
> else
> - err = EAGAIN;
> + err = -EAGAIN;
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for Update various *MAX_GT* definitions
On Mon, Jun 05, 2023 at 05:00:56PM -, Patchwork wrote:
> == Series Details ==
>
> Series: Update various *MAX_GT* definitions
> URL : https://patchwork.freedesktop.org/series/118807/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_13225_full -> Patchwork_118807v1_full
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
Applied to drm-intel-gt-next. Thanks for the patches.
Matt
>
>
>
> Participating hosts (7 -> 7)
> --
>
> No changes in participating hosts
>
> Known issues
>
>
> Here are the changes found in Patchwork_118807v1_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gen9_exec_parse@allowed-single:
> - shard-glk: [PASS][1] -> [ABORT][2] ([i915#5566])
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13225/shard-glk4/igt@gen9_exec_pa...@allowed-single.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-glk9/igt@gen9_exec_pa...@allowed-single.html
>
> * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-vga:
> - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4579])
> +13 similar issues
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-snb4/igt@i915_pm_lpsp@kms-l...@kms-lpsp-vga.html
>
> * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
> - shard-glk: NOTRUN -> [SKIP][4] ([fdo#109271]) +27 similar
> issues
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-glk6/igt@kms_big...@x-tiled-32bpp-rotate-90.html
>
> * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
> - shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#3886]) +2
> similar issues
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-glk6/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
> - shard-apl: [PASS][6] -> [FAIL][7] ([i915#2346]) +1 similar
> issue
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13225/shard-apl1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-apl1/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions-varying-size.html
>
> * igt@kms_flip@2x-plain-flip-fb-recreate:
> - shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271]) +34 similar
> issues
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-snb7/igt@kms_f...@2x-plain-flip-fb-recreate.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
> - shard-apl: [PASS][9] -> [ABORT][10] ([i915#180])
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13225/shard-apl6/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-apl6/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
> - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180])
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13225/shard-apl6/igt@kms_flip@flip-vs-suspend-interrupti...@c-dp1.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-apl6/igt@kms_flip@flip-vs-suspend-interrupti...@c-dp1.html
>
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
> - shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#658])
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-glk6/igt@kms_psr2...@primary-plane-update-sf-dmg-area.html
>
> * igt@kms_scaling_modes@scaling-mode-full:
> - shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4579])
> +2 similar issues
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-glk6/igt@kms_scaling_mo...@scaling-mode-full.html
>
> * igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
> - shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271]) +4 similar
> issues
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-apl2/igt@kms_universal_pl...@disable-primary-vs-flip-pipe-d.html
>
>
> Possible fixes
>
> * igt@gem_barrier_race@remote-request@rcs0:
> - shard-apl: [ABORT][16] ([i915#7461] / [i915#8234] /
> [i915#8272]) -> [PASS][17]
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13225/shard-apl4/igt@gem_barrier_race@remote-requ...@rcs0.html
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118807v1/shard-apl2/igt@gem_barrier_race@remote-requ...@rcs0.html
>
> * igt@gem_ctx_exec@basic-nohangcheck:
> - {shard-rkl}:[FAIL][18] ([i915#6268]) -> [PASS][19]
>[18]:
>
Re: [Intel-gfx] [PATCH] drm/i915: Avoid circular locking dependency when flush delayed work on gt reset
On 6/5/2023 20:00, Zhanjun Dong wrote:
This attemps to avoid circular locing dependency between flush delayed work and
intel_gt_reset.
locing -> locking
WARNING: possible circular locking dependency detected
6.4.0-rc1-drmtip_1340-g31e3463b0edb+ #1 Not tainted
--
kms_pipe_crc_ba/6415 is trying to acquire lock:
88813e6cc640
((work_completion)(&(>timestamp.work)->work)){+.+.}-{0:0}, at:
__flush_work+0x42/0x530
but task is already holding lock:
88813e6cce90 (>reset.mutex){+.+.}-{3:3}, at: intel_gt_reset+0x19e/0x470
[i915]
which lock already depends on the new lock.
the existing dependency chain (in reverse order) is:
-> #3 (>reset.mutex){+.+.}-{3:3}:
lock_acquire+0xd8/0x2d0
i915_gem_shrinker_taints_mutex+0x31/0x50 [i915]
intel_gt_init_reset+0x65/0x80 [i915]
intel_gt_common_init_early+0xe1/0x170 [i915]
intel_root_gt_init_early+0x48/0x60 [i915]
i915_driver_probe+0x671/0xcb0 [i915]
i915_pci_probe+0xdc/0x210 [i915]
pci_device_probe+0x95/0x120
really_probe+0x164/0x3c0
__driver_probe_device+0x73/0x160
driver_probe_device+0x19/0xa0
__driver_attach+0xb6/0x180
bus_for_each_dev+0x77/0xd0
bus_add_driver+0x114/0x210
driver_register+0x5b/0x110
__pfx_vgem_open+0x3/0x10 [vgem]
do_one_initcall+0x57/0x270
do_init_module+0x5f/0x220
load_module+0x1ca4/0x1f00
__do_sys_finit_module+0xb4/0x130
do_syscall_64+0x3c/0x90
entry_SYSCALL_64_after_hwframe+0x72/0xdc
-> #2 (fs_reclaim){+.+.}-{0:0}:
lock_acquire+0xd8/0x2d0
fs_reclaim_acquire+0xac/0xe0
kmem_cache_alloc+0x32/0x260
i915_vma_instance+0xb2/0xc60 [i915]
i915_gem_object_ggtt_pin_ww+0x175/0x370 [i915]
vm_fault_gtt+0x22d/0xf60 [i915]
__do_fault+0x2f/0x1d0
do_pte_missing+0x4a/0xd20
__handle_mm_fault+0x5b0/0x790
handle_mm_fault+0xa2/0x230
do_user_addr_fault+0x3ea/0xa10
exc_page_fault+0x68/0x1a0
asm_exc_page_fault+0x26/0x30
-> #1 (>reset.backoff_srcu){}-{0:0}:
lock_acquire+0xd8/0x2d0
_intel_gt_reset_lock+0x57/0x330 [i915]
guc_timestamp_ping+0x35/0x130 [i915]
process_one_work+0x250/0x510
worker_thread+0x4f/0x3a0
kthread+0xff/0x130
ret_from_fork+0x29/0x50
-> #0 ((work_completion)(&(>timestamp.work)->work)){+.+.}-{0:0}:
check_prev_add+0x90/0xc60
__lock_acquire+0x1998/0x2590
lock_acquire+0xd8/0x2d0
__flush_work+0x74/0x530
__cancel_work_timer+0x14f/0x1f0
intel_guc_submission_reset_prepare+0x81/0x4b0 [i915]
intel_uc_reset_prepare+0x9c/0x120 [i915]
reset_prepare+0x21/0x60 [i915]
intel_gt_reset+0x1dd/0x470 [i915]
intel_gt_reset_global+0xfb/0x170 [i915]
intel_gt_handle_error+0x368/0x420 [i915]
intel_gt_debugfs_reset_store+0x5c/0xc0 [i915]
i915_wedged_set+0x29/0x40 [i915]
simple_attr_write_xsigned.constprop.0+0xb4/0x110
full_proxy_write+0x52/0x80
vfs_write+0xc5/0x4f0
ksys_write+0x64/0xe0
do_syscall_64+0x3c/0x90
entry_SYSCALL_64_after_hwframe+0x72/0xdc
other info that might help us debug this:
Chain exists of:
(work_completion)(&(>timestamp.work)->work) --> fs_reclaim -->
>reset.mutex
Possible unsafe locking scenario:
CPU0CPU1
lock(>reset.mutex);
lock(fs_reclaim);
lock(>reset.mutex);
lock((work_completion)(&(>timestamp.work)->work));
*** DEADLOCK ***
3 locks held by kms_pipe_crc_ba/6415:
#0: 888101541430 (sb_writers#15){.+.+}-{0:0}, at: ksys_write+0x64/0xe0
#1: 888136c7eab8 (>mutex){+.+.}-{3:3}, at:
simple_attr_write_xsigned.constprop.0+0x47/0x110
#2: 88813e6cce90 (>reset.mutex){+.+.}-{3:3}, at:
intel_gt_reset+0x19e/0x470 [i915]
Signed-off-by: Zhanjun Dong
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d2..22390704542e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1359,7 +1359,7 @@ static void guc_enable_busyness_worker(struct intel_guc
*guc)
static void guc_cancel_busyness_worker(struct intel_guc *guc)
{
- cancel_delayed_work_sync(>timestamp.work);
+ cancel_delayed_work(>timestamp.work);
I think it is worth adding a comment here to explain that it is safe to
call the non _sync variant (because of the trylock code in the worker
itself) and that the _sync variant hits circular mutex lock issues.
John.
}
[Intel-gfx] [PATCH] drm/i915/adlp+: Allow DC states along with PW2 only for PWB functionality
A recent bspec update added a restriction on when DC states can be enabled: [Before enabling DC states:] """ PG2 can be kept enabled only because PGB requires PG2. Do not use PG2 functions, such as type-C DDIs. DMC will dynamically control PG1, PGA, PG2, PGB. """ Accordingly prevent DC states if PW2 (aka PG2) is enabled for any other functionality. Bpsec: 49193 Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_power_map.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c index 1118ee9d224ca..5ad04cd42c158 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c @@ -1252,10 +1252,18 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a, POWER_DOMAIN_INIT); #define XELPD_DC_OFF_PORT_POWER_DOMAINS \ + POWER_DOMAIN_PORT_DDI_LANES_C, \ + POWER_DOMAIN_PORT_DDI_LANES_D, \ + POWER_DOMAIN_PORT_DDI_LANES_E, \ POWER_DOMAIN_PORT_DDI_LANES_TC1, \ POWER_DOMAIN_PORT_DDI_LANES_TC2, \ POWER_DOMAIN_PORT_DDI_LANES_TC3, \ POWER_DOMAIN_PORT_DDI_LANES_TC4, \ + POWER_DOMAIN_VGA, \ + POWER_DOMAIN_AUDIO_PLAYBACK, \ + POWER_DOMAIN_AUX_IO_C, \ + POWER_DOMAIN_AUX_IO_D, \ + POWER_DOMAIN_AUX_IO_E, \ POWER_DOMAIN_AUX_C, \ POWER_DOMAIN_AUX_D, \ POWER_DOMAIN_AUX_E, \ @@ -1272,14 +1280,6 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a, XELPD_PW_B_POWER_DOMAINS, \ XELPD_PW_C_POWER_DOMAINS, \ XELPD_PW_D_POWER_DOMAINS, \ - POWER_DOMAIN_PORT_DDI_LANES_C, \ - POWER_DOMAIN_PORT_DDI_LANES_D, \ - POWER_DOMAIN_PORT_DDI_LANES_E, \ - POWER_DOMAIN_VGA, \ - POWER_DOMAIN_AUDIO_PLAYBACK, \ - POWER_DOMAIN_AUX_IO_C, \ - POWER_DOMAIN_AUX_IO_D, \ - POWER_DOMAIN_AUX_IO_E, \ XELPD_DC_OFF_PORT_POWER_DOMAINS I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2, -- 2.37.2
[Intel-gfx] [PATCH v5 3/3] drm/i915/selftests: add local workqueue for SW fence selftest
Instead of using a global workqueue for the SW fence selftest,
allocate a separate one temporarily only while running the test.
Cc: Tetsuo Handa
Cc: Jani Nikula
Cc: Ville Syrjälä
Reviewed-by: Tvrtko Ursulin
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/selftests/i915_sw_fence.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
b/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
index daa985e5a19b..8f5ce71fa453 100644
--- a/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
@@ -523,12 +523,19 @@ static void task_ipc(struct work_struct *work)
static int test_ipc(void *arg)
{
struct task_ipc ipc;
+ struct workqueue_struct *wq;
int ret = 0;
+ wq = alloc_workqueue("i1915-selftest", 0, 0);
+ if (wq == NULL)
+ return -ENOMEM;
+
/* Test use of i915_sw_fence as an interprocess signaling mechanism */
ipc.in = alloc_fence();
- if (!ipc.in)
- return -ENOMEM;
+ if (!ipc.in) {
+ ret = -ENOMEM;
+ goto err_work;
+ }
ipc.out = alloc_fence();
if (!ipc.out) {
ret = -ENOMEM;
@@ -540,7 +547,7 @@ static int test_ipc(void *arg)
ipc.value = 0;
INIT_WORK_ONSTACK(, task_ipc);
- schedule_work();
+ queue_work(wq, );
wait_for_completion();
@@ -563,6 +570,9 @@ static int test_ipc(void *arg)
free_fence(ipc.out);
err_in:
free_fence(ipc.in);
+err_work:
+ destroy_workqueue(wq);
+
return ret;
}
--
2.39.2
[Intel-gfx] [PATCH v5 2/3] drm/i915: add a dedicated workqueue inside drm_i915_private
In order to avoid flush_scheduled_work() usage, add a dedicated
workqueue in the drm_i915_private structure. In this way, we don't
need to use the system queue anymore.
This change is mostly mechanical and based on Tetsuo's original
patch[1].
Link: https://patchwork.freedesktop.org/series/114608/ [1]
Cc: Tetsuo Handa
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++--
.../drm/i915/display/intel_display_driver.c | 2 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
.../drm/i915/display/intel_dp_link_training.c | 3 ++-
drivers/gpu/drm/i915/display/intel_drrs.c | 4 +++-
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c| 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 23 +++
drivers/gpu/drm/i915/display/intel_hotplug.c | 18 ++-
drivers/gpu/drm/i915/display/intel_opregion.c | 3 ++-
drivers/gpu/drm/i915/display/intel_pps.c | 4 +++-
drivers/gpu/drm/i915/display/intel_psr.c | 8 ---
.../drm/i915/gt/intel_execlists_submission.c | 5 ++--
.../gpu/drm/i915/gt/intel_gt_buffer_pool.c| 10
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gt_requests.c | 10
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 20
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
drivers/gpu/drm/i915/i915_driver.c| 13 +++
drivers/gpu/drm/i915/i915_drv.h | 10
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/intel_wakeref.c | 2 +-
24 files changed, 103 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f23dd937c27c..a2afb19ca0e3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7166,11 +7166,12 @@ intel_atomic_commit_ready(struct i915_sw_fence *fence,
break;
case FENCE_FREE:
{
+ struct drm_i915_private *i915 =
to_i915(state->base.dev);
struct intel_atomic_helper *helper =
-
_i915(state->base.dev)->display.atomic_helper;
+ >display.atomic_helper;
if (llist_add(>freed, >free_list))
- schedule_work(>free_work);
+ queue_work(i915->unordered_wq,
>free_work);
break;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 60ce10fc7205..a9e36ddb6c1d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -435,7 +435,7 @@ void intel_display_driver_remove_noirq(struct
drm_i915_private *i915)
intel_unregister_dsm_handler();
/* flush any delayed tasks or pending work */
- flush_scheduled_work();
+ flush_workqueue(i915->unordered_wq);
intel_hdcp_component_fini(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 8a88de67ff0a..5f479f3828bb 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1057,7 +1057,7 @@ void intel_dmc_init(struct drm_i915_private *i915)
i915->display.dmc.dmc = dmc;
drm_dbg_kms(>drm, "Loading %s\n", dmc->fw_path);
- schedule_work(>work);
+ queue_work(i915->unordered_wq, >work);
return;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f4192fda1a76..09dc6c88ad28 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5251,7 +5251,7 @@ static void intel_dp_oob_hotplug_event(struct
drm_connector *connector)
spin_lock_irq(>irq_lock);
i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin);
spin_unlock_irq(>irq_lock);
- queue_delayed_work(system_wq, >display.hotplug.hotplug_work, 0);
+ queue_delayed_work(i915->unordered_wq,
>display.hotplug.hotplug_work, 0);
}
static const struct drm_connector_funcs intel_dp_connector_funcs = {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 0952a707358c..20a970f1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1064,6 +1064,7 @@ static void
intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
[Intel-gfx] [PATCH v5 1/3] drm/i915: use pointer to i915 instead of rpm in wakeref
Currently a pointer to an intel_runtime_pm structure is stored in the
wake reference structures so the runtime data can be accessed. We can
save the entire device information (drm_i915_private) instead, since
we'll need to reference the new workqueue we'll add in subsequent
patches.
Reviewed-by: Tvrtko Ursulin
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
drivers/gpu/drm/i915/intel_wakeref.c | 20 +++-
drivers/gpu/drm/i915/intel_wakeref.h | 12 ++--
5 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index ee531a5c142c..21af0ec52223 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -296,9 +296,7 @@ static const struct intel_wakeref_ops wf_ops = {
void intel_engine_init__pm(struct intel_engine_cs *engine)
{
- struct intel_runtime_pm *rpm = engine->uncore->rpm;
-
- intel_wakeref_init(>wakeref, rpm, _ops);
+ intel_wakeref_init(>wakeref, engine->i915, _ops);
intel_engine_init_heartbeat(engine);
intel_gsc_idle_msg_enable(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index c2e69bafd02b..5a942af0a14e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -137,7 +137,7 @@ void intel_gt_pm_init_early(struct intel_gt *gt)
* runtime_pm is per-device rather than per-tile, so this is still the
* correct structure.
*/
- intel_wakeref_init(>wakeref, >i915->runtime_pm, _ops);
+ intel_wakeref_init(>wakeref, gt->i915, _ops);
seqcount_mutex_init(>stats.lock, >wakeref.mutex);
}
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index cf5122299b6b..6d8e5e5c0cba 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -658,5 +658,5 @@ void intel_runtime_pm_init_early(struct intel_runtime_pm
*rpm)
init_intel_runtime_pm_wakeref(rpm);
INIT_LIST_HEAD(>lmem_userfault_list);
spin_lock_init(>lmem_userfault_lock);
- intel_wakeref_auto_init(>userfault_wakeref, rpm);
+ intel_wakeref_auto_init(>userfault_wakeref, i915);
}
diff --git a/drivers/gpu/drm/i915/intel_wakeref.c
b/drivers/gpu/drm/i915/intel_wakeref.c
index dfd87d082218..40aafe676017 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.c
+++ b/drivers/gpu/drm/i915/intel_wakeref.c
@@ -8,17 +8,18 @@
#include "intel_runtime_pm.h"
#include "intel_wakeref.h"
+#include "i915_drv.h"
static void rpm_get(struct intel_wakeref *wf)
{
- wf->wakeref = intel_runtime_pm_get(wf->rpm);
+ wf->wakeref = intel_runtime_pm_get(>i915->runtime_pm);
}
static void rpm_put(struct intel_wakeref *wf)
{
intel_wakeref_t wakeref = fetch_and_zero(>wakeref);
- intel_runtime_pm_put(wf->rpm, wakeref);
+ intel_runtime_pm_put(>i915->runtime_pm, wakeref);
INTEL_WAKEREF_BUG_ON(!wakeref);
}
@@ -94,11 +95,11 @@ static void __intel_wakeref_put_work(struct work_struct
*wrk)
}
void __intel_wakeref_init(struct intel_wakeref *wf,
- struct intel_runtime_pm *rpm,
+ struct drm_i915_private *i915,
const struct intel_wakeref_ops *ops,
struct intel_wakeref_lockclass *key)
{
- wf->rpm = rpm;
+ wf->i915 = i915;
wf->ops = ops;
__mutex_init(>mutex, "wakeref.mutex", >mutex);
@@ -137,17 +138,17 @@ static void wakeref_auto_timeout(struct timer_list *t)
wakeref = fetch_and_zero(>wakeref);
spin_unlock_irqrestore(>lock, flags);
- intel_runtime_pm_put(wf->rpm, wakeref);
+ intel_runtime_pm_put(>i915->runtime_pm, wakeref);
}
void intel_wakeref_auto_init(struct intel_wakeref_auto *wf,
-struct intel_runtime_pm *rpm)
+struct drm_i915_private *i915)
{
spin_lock_init(>lock);
timer_setup(>timer, wakeref_auto_timeout, 0);
refcount_set(>count, 0);
wf->wakeref = 0;
- wf->rpm = rpm;
+ wf->i915 = i915;
}
void intel_wakeref_auto(struct intel_wakeref_auto *wf, unsigned long timeout)
@@ -161,13 +162,14 @@ void intel_wakeref_auto(struct intel_wakeref_auto *wf,
unsigned long timeout)
}
/* Our mission is that we only extend an already active wakeref */
- assert_rpm_wakelock_held(wf->rpm);
+ assert_rpm_wakelock_held(>i915->runtime_pm);
if (!refcount_inc_not_zero(>count)) {
spin_lock_irqsave(>lock, flags);
if (!refcount_inc_not_zero(>count)) {
INTEL_WAKEREF_BUG_ON(wf->wakeref);
-
[Intel-gfx] [PATCH v5 0/3] drm/i915: implement internal workqueues
Hi, This series implements internal workqueues in the i915 driver in order to avoid using the system queue. We add one generic workqueue in the drm_i915_private structure, one specific for wake references and one in a self-test. This is based on Tetsuo's work[1] and is required to get rid of the flush_scheduled_work() usage. As discussed, we can either take Tetsuo's implementation first, which uses a module-global workqueue, and then my series on top of that, to change the implementation to per-device workqueues, or apply my series directly. And a third option would be to keep the workqueue as module-global. I'm fine with any of this options. It's up to the maintainers to decide which one to take. In v2: * Removed per-engine workqueue and wakeref-specific queue; * Renamed the workqueue name from "i915-wq" to "unordered_wq"; * Added comment about when the new workqueue should be used; * Changed wakeref structs to store i915 instead of rpm; In v3: * Fixed queue to destroy in the init error path; * Improved the new queue's description a bit; * Removed stray empty-line removal; In v4: * Fixed the queue used in __intel_wakeref_put_last(), we were accidentally using the ordered workqueue. Thanks, Tvrtko! In v5: * Fix compilation error cause by change from dev_priv to i915 in intel_hdcp_enable(). Please review. [1] https://patchwork.freedesktop.org/series/114608/ Cheers, Luca. Luca Coelho (3): drm/i915: use pointer to i915 instead of rpm in wakeref drm/i915: add a dedicated workqueue inside drm_i915_private drm/i915/selftests: add local workqueue for SW fence selftest drivers/gpu/drm/i915/display/intel_display.c | 5 ++-- .../drm/i915/display/intel_display_driver.c | 2 +- drivers/gpu/drm/i915/display/intel_dmc.c | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- .../drm/i915/display/intel_dp_link_training.c | 3 ++- drivers/gpu/drm/i915/display/intel_drrs.c | 4 +++- drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- drivers/gpu/drm/i915/display/intel_fbdev.c| 3 ++- drivers/gpu/drm/i915/display/intel_hdcp.c | 23 +++ drivers/gpu/drm/i915/display/intel_hotplug.c | 18 ++- drivers/gpu/drm/i915/display/intel_opregion.c | 3 ++- drivers/gpu/drm/i915/display/intel_pps.c | 4 +++- drivers/gpu/drm/i915/display/intel_psr.c | 8 --- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +--- .../drm/i915/gt/intel_execlists_submission.c | 5 ++-- .../gpu/drm/i915/gt/intel_gt_buffer_pool.c| 10 drivers/gpu/drm/i915/gt/intel_gt_irq.c| 2 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_requests.c | 10 drivers/gpu/drm/i915/gt/intel_reset.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 20 drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +- drivers/gpu/drm/i915/i915_driver.c| 13 +++ drivers/gpu/drm/i915/i915_drv.h | 10 drivers/gpu/drm/i915/i915_request.c | 2 +- drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- drivers/gpu/drm/i915/intel_wakeref.c | 22 ++ drivers/gpu/drm/i915/intel_wakeref.h | 12 +- .../gpu/drm/i915/selftests/i915_sw_fence.c| 16 ++--- 29 files changed, 136 insertions(+), 77 deletions(-) -- 2.39.2
[Intel-gfx] PR for HuC v8.5.0 for MTL
The following changes since commit fc90c59beebd551dde5fe5eb3e76d36651ba08fb: Merge branch 'db410c' of https://github.com/lumag/linux-firmware (2023-05-31 07:35:15 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware mtl_huc_v8.5.0 for you to fetch changes up to 5de33fb45cee8d83abfe17e9e85bd74d51a2653f: i915: Add HuC v8.5.0 for MTL (2023-06-06 09:24:40 -0700) Daniele Ceraolo Spurio (1): i915: Add HuC v8.5.0 for MTL WHENCE | 3 +++ i915/mtl_huc_gsc.bin | Bin 0 -> 565248 bytes 2 files changed, 3 insertions(+) create mode 100755 i915/mtl_huc_gsc.bin
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: implement internal workqueues
== Series Details == Series: drm/i915: implement internal workqueues URL : https://patchwork.freedesktop.org/series/118947/ State : failure == Summary == Error: make failed CALLscripts/checksyscalls.sh DESCEND objtool INSTALL libsubcmd_headers CC [M] drivers/gpu/drm/i915/display/intel_hdcp.o drivers/gpu/drm/i915/display/intel_hdcp.c: In function ‘intel_hdcp_enable’: drivers/gpu/drm/i915/display/intel_hdcp.c:2403:22: error: ‘dev_priv’ undeclared (first use in this function); did you mean ‘dev_crit’? 2403 | queue_delayed_work(dev_priv->unordered_wq, >check_work, | ^~~~ | dev_crit drivers/gpu/drm/i915/display/intel_hdcp.c:2403:22: note: each undeclared identifier is reported only once for each function it appears in make[5]: *** [scripts/Makefile.build:252: drivers/gpu/drm/i915/display/intel_hdcp.o] Error 1 make[4]: *** [scripts/Makefile.build:494: drivers/gpu/drm/i915] Error 2 make[3]: *** [scripts/Makefile.build:494: drivers/gpu/drm] Error 2 make[2]: *** [scripts/Makefile.build:494: drivers/gpu] Error 2 make[1]: *** [scripts/Makefile.build:494: drivers] Error 2 make: *** [Makefile:2026: .] Error 2 Build failed, no error log produced
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: implement internal workqueues (rev3)
On Tue, 2023-06-06 at 14:30 +, Coelho, Luciano wrote:
> On Tue, 2023-06-06 at 14:33 +0100, Tvrtko Ursulin wrote:
> > On 06/06/2023 12:06, Coelho, Luciano wrote:
> > > On Tue, 2023-06-06 at 11:06 +0100, Tvrtko Ursulin wrote:
> > > > On 05/06/2023 16:06, Jani Nikula wrote:
> > > > > On Wed, 31 May 2023, Patchwork
> > > > > wrote:
> > > > > > Possible regressions
> > > > > >
> > > > > > * igt@gem_close_race@basic-process:
> > > > > > - fi-blb-e6850: [PASS][1] -> [ABORT][2]
> > > > > > [1]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/fi-blb-e6850/igt@gem_close_r...@basic-process.html
> > > > > > [2]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/fi-blb-e6850/igt@gem_close_r...@basic-process.html
> > > > > > - fi-hsw-4770:[PASS][3] -> [ABORT][4]
> > > > > > [3]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/fi-hsw-4770/igt@gem_close_r...@basic-process.html
> > > > > > [4]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/fi-hsw-4770/igt@gem_close_r...@basic-process.html
> > > > > > - fi-elk-e7500: [PASS][5] -> [ABORT][6]
> > > > > > [5]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/fi-elk-e7500/igt@gem_close_r...@basic-process.html
> > > > > > [6]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/fi-elk-e7500/igt@gem_close_r...@basic-process.html
> > > > > >
> > > > > > * igt@i915_selftest@live@evict:
> > > > > > - bat-adlp-9: [PASS][7] -> [ABORT][8]
> > > > > > [7]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-adlp-9/igt@i915_selftest@l...@evict.html
> > > > > > [8]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-adlp-9/igt@i915_selftest@l...@evict.html
> > > > > > - bat-rpls-2: [PASS][9] -> [ABORT][10]
> > > > > > [9]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-rpls-2/igt@i915_selftest@l...@evict.html
> > > > > > [10]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-rpls-2/igt@i915_selftest@l...@evict.html
> > > > > > - bat-adlm-1: [PASS][11] -> [ABORT][12]
> > > > > > [11]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-adlm-1/igt@i915_selftest@l...@evict.html
> > > > > > [12]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-adlm-1/igt@i915_selftest@l...@evict.html
> > > > > > - bat-rpls-1: [PASS][13] -> [ABORT][14]
> > > > > > [13]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-rpls-1/igt@i915_selftest@l...@evict.html
> > > > > > [14]:
> > > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-rpls-1/igt@i915_selftest@l...@evict.html
> > > > >
> > > > > This still fails consistently, I have no clue why, and the above
> > > > > aren't
> > > > > even remotely related to display.
> > > > >
> > > > > What now? Tvrtko?
> > > >
> > > > Hmm..
> > > >
> > > > <4> [46.782321] Chain exists of:
> > > > (wq_completion)i915 --> (work_completion)(>mm.free_work) -->
> > > > >mutex
> > > > <4> [46.782329] Possible unsafe locking scenario:
> > > > <4> [46.782332]CPU0CPU1
> > > > <4> [46.782334]
> > > > <4> [46.782337] lock(>mutex);
> > > > <4> [46.782340]
> > > > lock((work_completion)(>mm.free_work));
> > > > <4> [46.782344]lock(>mutex);
> > > > <4> [46.782348] lock((wq_completion)i915);
> > > >
> > > >
> > > > "(wq_completion)i915"
> > > >
> > > > So it's not about the new wq even. Perhaps it is this hunk:
> > > >
> > > > --- a/drivers/gpu/drm/i915/intel_wakeref.c
> > > > +++ b/drivers/gpu/drm/i915/intel_wakeref.c
> > > > @@ -75,7 +75,7 @@ void __intel_wakeref_put_last(struct intel_wakeref
> > > > *wf, unsigned long flags)
> > > >
> > > > /* Assume we are not in process context and so cannot sleep. */
> > > > if (flags & INTEL_WAKEREF_PUT_ASYNC ||
> > > > !mutex_trylock(>mutex)) {
> > > > - mod_delayed_work(system_wq, >work,
> > > > + mod_delayed_work(wf->i915->wq, >work,
> > > >
> > > > Transformation from this patch otherwise is system_wq with the new
> > > > unordered wq, so I'd try that first.
> > >
> > > Indeed this seems to be exactly the block that is causing the issue. I
> > > was sort of bisecting through all these changes and reverting this one
> > > prevents the lockdep splat from happening...
> > >
> > > So there's something that needs to be synced with the system_wq here,
> > > but what? I need to dig into it.
> >
> > AFAICT it is saying that i915->mm.free_work and engine->wakeref.work
> > must not be on the same ordered wq. Otherwise execbuf call trace
> > flushing under
[Intel-gfx] [PATCH v4 3/3] drm/i915/selftests: add local workqueue for SW fence selftest
Instead of using a global workqueue for the SW fence selftest,
allocate a separate one temporarily only while running the test.
Cc: Tetsuo Handa
Cc: Jani Nikula
Cc: Ville Syrjälä
Reviewed-by: Tvrtko Ursulin
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/selftests/i915_sw_fence.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
b/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
index daa985e5a19b..8f5ce71fa453 100644
--- a/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
@@ -523,12 +523,19 @@ static void task_ipc(struct work_struct *work)
static int test_ipc(void *arg)
{
struct task_ipc ipc;
+ struct workqueue_struct *wq;
int ret = 0;
+ wq = alloc_workqueue("i1915-selftest", 0, 0);
+ if (wq == NULL)
+ return -ENOMEM;
+
/* Test use of i915_sw_fence as an interprocess signaling mechanism */
ipc.in = alloc_fence();
- if (!ipc.in)
- return -ENOMEM;
+ if (!ipc.in) {
+ ret = -ENOMEM;
+ goto err_work;
+ }
ipc.out = alloc_fence();
if (!ipc.out) {
ret = -ENOMEM;
@@ -540,7 +547,7 @@ static int test_ipc(void *arg)
ipc.value = 0;
INIT_WORK_ONSTACK(, task_ipc);
- schedule_work();
+ queue_work(wq, );
wait_for_completion();
@@ -563,6 +570,9 @@ static int test_ipc(void *arg)
free_fence(ipc.out);
err_in:
free_fence(ipc.in);
+err_work:
+ destroy_workqueue(wq);
+
return ret;
}
--
2.39.2
[Intel-gfx] [PATCH v4 2/3] drm/i915: add a dedicated workqueue inside drm_i915_private
In order to avoid flush_scheduled_work() usage, add a dedicated
workqueue in the drm_i915_private structure. In this way, we don't
need to use the system queue anymore.
This change is mostly mechanical and based on Tetsuo's original
patch[1].
Link: https://patchwork.freedesktop.org/series/114608/ [1]
Cc: Tetsuo Handa
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++--
.../drm/i915/display/intel_display_driver.c | 2 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
.../drm/i915/display/intel_dp_link_training.c | 3 ++-
drivers/gpu/drm/i915/display/intel_drrs.c | 4 +++-
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c| 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 23 +++
drivers/gpu/drm/i915/display/intel_hotplug.c | 18 ++-
drivers/gpu/drm/i915/display/intel_opregion.c | 3 ++-
drivers/gpu/drm/i915/display/intel_pps.c | 4 +++-
drivers/gpu/drm/i915/display/intel_psr.c | 8 ---
.../drm/i915/gt/intel_execlists_submission.c | 5 ++--
.../gpu/drm/i915/gt/intel_gt_buffer_pool.c| 10
drivers/gpu/drm/i915/gt/intel_gt_irq.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gt_requests.c | 10
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 20
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
drivers/gpu/drm/i915/i915_driver.c| 13 +++
drivers/gpu/drm/i915/i915_drv.h | 10
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/intel_wakeref.c | 2 +-
24 files changed, 103 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f23dd937c27c..a2afb19ca0e3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7166,11 +7166,12 @@ intel_atomic_commit_ready(struct i915_sw_fence *fence,
break;
case FENCE_FREE:
{
+ struct drm_i915_private *i915 =
to_i915(state->base.dev);
struct intel_atomic_helper *helper =
-
_i915(state->base.dev)->display.atomic_helper;
+ >display.atomic_helper;
if (llist_add(>freed, >free_list))
- schedule_work(>free_work);
+ queue_work(i915->unordered_wq,
>free_work);
break;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 60ce10fc7205..a9e36ddb6c1d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -435,7 +435,7 @@ void intel_display_driver_remove_noirq(struct
drm_i915_private *i915)
intel_unregister_dsm_handler();
/* flush any delayed tasks or pending work */
- flush_scheduled_work();
+ flush_workqueue(i915->unordered_wq);
intel_hdcp_component_fini(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 8a88de67ff0a..5f479f3828bb 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1057,7 +1057,7 @@ void intel_dmc_init(struct drm_i915_private *i915)
i915->display.dmc.dmc = dmc;
drm_dbg_kms(>drm, "Loading %s\n", dmc->fw_path);
- schedule_work(>work);
+ queue_work(i915->unordered_wq, >work);
return;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f4192fda1a76..09dc6c88ad28 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5251,7 +5251,7 @@ static void intel_dp_oob_hotplug_event(struct
drm_connector *connector)
spin_lock_irq(>irq_lock);
i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin);
spin_unlock_irq(>irq_lock);
- queue_delayed_work(system_wq, >display.hotplug.hotplug_work, 0);
+ queue_delayed_work(i915->unordered_wq,
>display.hotplug.hotplug_work, 0);
}
static const struct drm_connector_funcs intel_dp_connector_funcs = {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 0952a707358c..20a970f1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1064,6 +1064,7 @@ static void
intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
[Intel-gfx] [PATCH v4 1/3] drm/i915: use pointer to i915 instead of rpm in wakeref
Currently a pointer to an intel_runtime_pm structure is stored in the
wake reference structures so the runtime data can be accessed. We can
save the entire device information (drm_i915_private) instead, since
we'll need to reference the new workqueue we'll add in subsequent
patches.
Reviewed-by: Tvrtko Ursulin
Signed-off-by: Luca Coelho
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
drivers/gpu/drm/i915/intel_wakeref.c | 20 +++-
drivers/gpu/drm/i915/intel_wakeref.h | 12 ++--
5 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index ee531a5c142c..21af0ec52223 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -296,9 +296,7 @@ static const struct intel_wakeref_ops wf_ops = {
void intel_engine_init__pm(struct intel_engine_cs *engine)
{
- struct intel_runtime_pm *rpm = engine->uncore->rpm;
-
- intel_wakeref_init(>wakeref, rpm, _ops);
+ intel_wakeref_init(>wakeref, engine->i915, _ops);
intel_engine_init_heartbeat(engine);
intel_gsc_idle_msg_enable(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index c2e69bafd02b..5a942af0a14e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -137,7 +137,7 @@ void intel_gt_pm_init_early(struct intel_gt *gt)
* runtime_pm is per-device rather than per-tile, so this is still the
* correct structure.
*/
- intel_wakeref_init(>wakeref, >i915->runtime_pm, _ops);
+ intel_wakeref_init(>wakeref, gt->i915, _ops);
seqcount_mutex_init(>stats.lock, >wakeref.mutex);
}
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index cf5122299b6b..6d8e5e5c0cba 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -658,5 +658,5 @@ void intel_runtime_pm_init_early(struct intel_runtime_pm
*rpm)
init_intel_runtime_pm_wakeref(rpm);
INIT_LIST_HEAD(>lmem_userfault_list);
spin_lock_init(>lmem_userfault_lock);
- intel_wakeref_auto_init(>userfault_wakeref, rpm);
+ intel_wakeref_auto_init(>userfault_wakeref, i915);
}
diff --git a/drivers/gpu/drm/i915/intel_wakeref.c
b/drivers/gpu/drm/i915/intel_wakeref.c
index dfd87d082218..40aafe676017 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.c
+++ b/drivers/gpu/drm/i915/intel_wakeref.c
@@ -8,17 +8,18 @@
#include "intel_runtime_pm.h"
#include "intel_wakeref.h"
+#include "i915_drv.h"
static void rpm_get(struct intel_wakeref *wf)
{
- wf->wakeref = intel_runtime_pm_get(wf->rpm);
+ wf->wakeref = intel_runtime_pm_get(>i915->runtime_pm);
}
static void rpm_put(struct intel_wakeref *wf)
{
intel_wakeref_t wakeref = fetch_and_zero(>wakeref);
- intel_runtime_pm_put(wf->rpm, wakeref);
+ intel_runtime_pm_put(>i915->runtime_pm, wakeref);
INTEL_WAKEREF_BUG_ON(!wakeref);
}
@@ -94,11 +95,11 @@ static void __intel_wakeref_put_work(struct work_struct
*wrk)
}
void __intel_wakeref_init(struct intel_wakeref *wf,
- struct intel_runtime_pm *rpm,
+ struct drm_i915_private *i915,
const struct intel_wakeref_ops *ops,
struct intel_wakeref_lockclass *key)
{
- wf->rpm = rpm;
+ wf->i915 = i915;
wf->ops = ops;
__mutex_init(>mutex, "wakeref.mutex", >mutex);
@@ -137,17 +138,17 @@ static void wakeref_auto_timeout(struct timer_list *t)
wakeref = fetch_and_zero(>wakeref);
spin_unlock_irqrestore(>lock, flags);
- intel_runtime_pm_put(wf->rpm, wakeref);
+ intel_runtime_pm_put(>i915->runtime_pm, wakeref);
}
void intel_wakeref_auto_init(struct intel_wakeref_auto *wf,
-struct intel_runtime_pm *rpm)
+struct drm_i915_private *i915)
{
spin_lock_init(>lock);
timer_setup(>timer, wakeref_auto_timeout, 0);
refcount_set(>count, 0);
wf->wakeref = 0;
- wf->rpm = rpm;
+ wf->i915 = i915;
}
void intel_wakeref_auto(struct intel_wakeref_auto *wf, unsigned long timeout)
@@ -161,13 +162,14 @@ void intel_wakeref_auto(struct intel_wakeref_auto *wf,
unsigned long timeout)
}
/* Our mission is that we only extend an already active wakeref */
- assert_rpm_wakelock_held(wf->rpm);
+ assert_rpm_wakelock_held(>i915->runtime_pm);
if (!refcount_inc_not_zero(>count)) {
spin_lock_irqsave(>lock, flags);
if (!refcount_inc_not_zero(>count)) {
INTEL_WAKEREF_BUG_ON(wf->wakeref);
-
[Intel-gfx] [PATCH v4 0/3] drm/i915: implement internal workqueues
Hi, This series implements internal workqueues in the i915 driver in order to avoid using the system queue. We add one generic workqueue in the drm_i915_private structure, one specific for wake references and one in a self-test. This is based on Tetsuo's work[1] and is required to get rid of the flush_scheduled_work() usage. As discussed, we can either take Tetsuo's implementation first, which uses a module-global workqueue, and then my series on top of that, to change the implementation to per-device workqueues, or apply my series directly. And a third option would be to keep the workqueue as module-global. I'm fine with any of this options. It's up to the maintainers to decide which one to take. In v2: * Removed per-engine workqueue and wakeref-specific queue; * Renamed the workqueue name from "i915-wq" to "unordered_wq"; * Added comment about when the new workqueue should be used; * Changed wakeref structs to store i915 instead of rpm; In v3: * Fixed queue to destroy in the init error path; * Improved the new queue's description a bit; * Removed stray empty-line removal; In v4: * Fixed the queue used in __intel_wakeref_put_last(), we were accidentally using the ordered workqueue. Thanks, Tvrtko! Please review. [1] https://patchwork.freedesktop.org/series/114608/ Cheers, Luca. Luca Coelho (3): drm/i915: use pointer to i915 instead of rpm in wakeref drm/i915: add a dedicated workqueue inside drm_i915_private drm/i915/selftests: add local workqueue for SW fence selftest drivers/gpu/drm/i915/display/intel_display.c | 5 ++-- .../drm/i915/display/intel_display_driver.c | 2 +- drivers/gpu/drm/i915/display/intel_dmc.c | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- .../drm/i915/display/intel_dp_link_training.c | 3 ++- drivers/gpu/drm/i915/display/intel_drrs.c | 4 +++- drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- drivers/gpu/drm/i915/display/intel_fbdev.c| 3 ++- drivers/gpu/drm/i915/display/intel_hdcp.c | 23 +++ drivers/gpu/drm/i915/display/intel_hotplug.c | 18 ++- drivers/gpu/drm/i915/display/intel_opregion.c | 3 ++- drivers/gpu/drm/i915/display/intel_pps.c | 4 +++- drivers/gpu/drm/i915/display/intel_psr.c | 8 --- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +--- .../drm/i915/gt/intel_execlists_submission.c | 5 ++-- .../gpu/drm/i915/gt/intel_gt_buffer_pool.c| 10 drivers/gpu/drm/i915/gt/intel_gt_irq.c| 2 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_requests.c | 10 drivers/gpu/drm/i915/gt/intel_reset.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 20 drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +- drivers/gpu/drm/i915/i915_driver.c| 13 +++ drivers/gpu/drm/i915/i915_drv.h | 10 drivers/gpu/drm/i915/i915_request.c | 2 +- drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- drivers/gpu/drm/i915/intel_wakeref.c | 22 ++ drivers/gpu/drm/i915/intel_wakeref.h | 12 +- .../gpu/drm/i915/selftests/i915_sw_fence.c| 16 ++--- 29 files changed, 136 insertions(+), 77 deletions(-) -- 2.39.2
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Add new vswing table for C20 phy to support DP 1.4
== Series Details ==
Series: drm/i915/mtl: Add new vswing table for C20 phy to support DP 1.4
URL : https://patchwork.freedesktop.org/series/118925/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13236 -> Patchwork_118925v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/index.html
Participating hosts (41 -> 40)
--
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_118925v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_flip@basic-flip-vs-wf_vblank@b-dp5:
- {bat-adlp-11}: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vbl...@b-dp5.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vbl...@b-dp5.html
New tests
-
New tests have been introduced between CI_DRM_13236 and Patchwork_118925v1:
### New IGT tests (3) ###
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-a-dp-7:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-c-dp-7:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-7:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_118925v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@requests:
- bat-adlp-9: [PASS][3] -> [ABORT][4] ([i915#7913] / [i915#7982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-adlp-9/igt@i915_selftest@l...@requests.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/bat-adlp-9/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: NOTRUN -> [ABORT][5] ([i915#4983] / [i915#7461] /
[i915#8347] / [i915#8384])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1:
- bat-dg2-8: [PASS][6] -> [FAIL][7] ([i915#7932])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
Possible fixes
* igt@i915_selftest@live@gt_pm:
- bat-rpls-2: [DMESG-FAIL][8] ([i915#4258] / [i915#7913]) ->
[PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [ABORT][10] ([i915#7911] / [i915#7920] / [i915#7982])
-> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-rpls-1/igt@i915_selftest@l...@requests.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118925v1/bat-rpls-1/igt@i915_selftest@l...@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
Build changes
-
* Linux: CI_DRM_13236 -> Patchwork_118925v1
CI-20190529: 20190529
CI_DRM_13236: 6ef9ba991d96572648aa75eb7818d8c111f2eb4f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7320: 1c96b08a4cde6f2d49824a8cc3303bd860617b52 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_118925v1: 6ef9ba991d96572648aa75eb7818d8c111f2eb4f @
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: update DP 2.0 vswing table for C20 phy
== Series Details ==
Series: drm/i915/mtl: update DP 2.0 vswing table for C20 phy
URL : https://patchwork.freedesktop.org/series/118924/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13236 -> Patchwork_118924v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/index.html
Participating hosts (41 -> 35)
--
Missing(6): fi-bsw-n3050 fi-ilk-650 fi-apl-guc fi-snb-2520m fi-cfl-8109u
fi-pnv-d510
Known issues
Here are the changes found in Patchwork_118924v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][1] -> [ABORT][2] ([i915#7911] / [i915#7913])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: NOTRUN -> [DMESG-WARN][3] ([i915#6367])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][4] ([i915#6687] / [i915#7978])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1:
- bat-dg2-8: [PASS][5] -> [FAIL][6] ([i915#7932])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
Possible fixes
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [DMESG-FAIL][7] ([i915#7059]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [DMESG-WARN][9] ([i915#7699]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [ABORT][11] ([i915#7911] / [i915#7920] / [i915#7982])
-> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-rpls-1/igt@i915_selftest@l...@requests.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/bat-rpls-1/igt@i915_selftest@l...@requests.html
* {igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-c-dp-5}:
- {bat-adlp-11}: [DMESG-FAIL][13] ([i915#6868]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-c-dp-5.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-c-dp-5.html
* {igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-5}:
- {bat-adlp-11}: [FAIL][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-d-dp-5.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-d-dp-5.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [FAIL][17] ([i915#7932]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118924v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-c-dp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7911]:
Re: [Intel-gfx] [PATCH] drm/i915/mtl: Add new vswing table for C20 phy to support DP 1.4
> -Original Message-
> From: Lee, Shawn C
> Sent: Tuesday, June 6, 2023 1:43 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Lee, Shawn C ; Kahola, Mika
> ; Taylor, Clinton A
> ; Sripada, Radhakrishna
> ; Shankar, Uma
>
> Subject: [PATCH] drm/i915/mtl: Add new vswing table for C20 phy to support DP
> 1.4
>
> Add vswing table to support DP 1.4 for C20 phy.
>
> Bspec: 74104
Reviewed-by: Mika Kahola
> Signed-off-by: Lee Shawn C
> Cc: Mika Kahola
> Cc: Clint Taylor
> Cc: Radhakrishna Sripada
> Cc: Uma Shankar
> ---
> .../drm/i915/display/intel_ddi_buf_trans.c| 21 +++
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index b7d20485bde5..6a1507515119 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1055,6 +1055,20 @@ static const struct intel_ddi_buf_trans mtl_cx0_trans
> = {
> .hdmi_default_entry = ARRAY_SIZE(_mtl_c10_trans_dp14) - 1, };
>
> +/* DP1.4 */
> +static const union intel_ddi_buf_trans_entry _mtl_c20_trans_dp14[] = {
> + { .snps = { 20, 0, 0 } }, /* preset 0 */
> + { .snps = { 24, 0, 4 } }, /* preset 1 */
> + { .snps = { 30, 0, 9 } }, /* preset 2 */
> + { .snps = { 34, 0, 14 } }, /* preset 3 */
> + { .snps = { 29, 0, 0 } }, /* preset 4 */
> + { .snps = { 34, 0, 5 } }, /* preset 5 */
> + { .snps = { 38, 0, 10 } }, /* preset 6 */
> + { .snps = { 36, 0, 0 } }, /* preset 7 */
> + { .snps = { 40, 0, 6 } }, /* preset 8 */
> + { .snps = { 48, 0, 0 } }, /* preset 9 */
> +};
> +
> /* DP2.0 */
> static const union intel_ddi_buf_trans_entry _mtl_c20_trans_uhbr[] = {
> { .snps = { 48, 0, 0 } }, /* preset 0 */
> @@ -1090,6 +1104,11 @@ static const struct intel_ddi_buf_trans
> mtl_c20_trans_hdmi = {
> .hdmi_default_entry = 0,
> };
>
> +static const struct intel_ddi_buf_trans mtl_c20_trans_dp14 = {
> + .entries = _mtl_c20_trans_dp14,
> + .num_entries = ARRAY_SIZE(_mtl_c20_trans_dp14), };
> +
> static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = {
> .entries = _mtl_c20_trans_uhbr,
> .num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr), @@ -1678,6 +1697,8 @@
> mtl_get_cx0_buf_trans(struct
> intel_encoder *encoder,
> return intel_get_buf_trans(_c20_trans_uhbr, n_entries);
> else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> !(intel_is_c10phy(i915, phy)))
> return intel_get_buf_trans(_c20_trans_hdmi, n_entries);
> + else if (!intel_is_c10phy(i915, phy))
> + return intel_get_buf_trans(_c20_trans_dp14, n_entries);
> else
> return intel_get_buf_trans(_cx0_trans, n_entries); }
> --
> 2.31.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow user to set cache at BO creation
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation
URL : https://patchwork.freedesktop.org/series/118921/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13236 -> Patchwork_118921v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/index.html
Participating hosts (41 -> 40)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_118921v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@mman:
- bat-rpls-2: [PASS][1] -> [TIMEOUT][2] ([i915#6794] / [i915#7392])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-rpls-2/igt@i915_selftest@l...@mman.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/bat-rpls-2/igt@i915_selftest@l...@mman.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: NOTRUN -> [ABORT][3] ([i915#4983] / [i915#7461] /
[i915#8347] / [i915#8384])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1:
- bat-dg2-8: [PASS][4] -> [FAIL][5] ([i915#7932])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
Possible fixes
* igt@i915_selftest@live@gt_mocs:
- {bat-mtlp-8}: [DMESG-FAIL][6] ([i915#7059]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [DMESG-WARN][8] ([i915#7699]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [ABORT][10] ([i915#7911] / [i915#7920] / [i915#7982])
-> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-rpls-1/igt@i915_selftest@l...@requests.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/bat-rpls-1/igt@i915_selftest@l...@requests.html
* {igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-c-dp-5}:
- {bat-adlp-11}: [DMESG-FAIL][12] ([i915#6868]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-c-dp-5.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-c-dp-5.html
* {igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-5}:
- {bat-adlp-11}: [FAIL][14] -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-d-dp-5.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118921v1/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-d-dp-5.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
Build changes
-
* IGT: IGT_7320 -> IGTPW_9114
* Linux: CI_DRM_13236 -> Patchwork_118921v1
CI-20190529: 20190529
CI_DRM_13236: 6ef9ba991d96572648aa75eb7818d8c111f2eb4f @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9114: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9114/index.html
IGT_7320:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Allow user to set cache at BO creation
== Series Details == Series: drm/i915: Allow user to set cache at BO creation URL : https://patchwork.freedesktop.org/series/118921/ State : warning == Summary == Error: dim checkpatch failed 445151c821ae drm/i915: Allow user to set cache at BO creation -:23: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #23: https://www.intel.com/content/www/us/en/docs/graphics-for-linux/developer-reference/1-0/tiger-lake.html total: 0 errors, 1 warnings, 0 checks, 136 lines checked
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Allow user to set cache at BO creation
== Series Details == Series: drm/i915: Allow user to set cache at BO creation URL : https://patchwork.freedesktop.org/series/118921/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH v11 20/23] vfio: Add VFIO_DEVICE_[AT|DE]TACH_IOMMUFD_PT
On Thu, May 25, 2023 at 03:03:54AM +, Liu, Yi L wrote: > vIOMMU may introduce some performance deduction if there > are frequent map/unmap. DPDK doesn't do that. And once you turn on the HW IOMMU you negate alot of the micro performance wins of bypassing. Maybe there is still some argument about giant/huge pages or something. > without vIOMMU is supposed to be more robust. But I'm not > sure if the noiommu userspace will adapt to cdev noiommu. > Perhaps yes if group may be deprecated in future. I think that is more a distro question, and we don't have to answer it fully now. Jason
Re: [Intel-gfx] [PATCH v11 20/23] vfio: Add VFIO_DEVICE_[AT|DE]TACH_IOMMUFD_PT
On Wed, May 24, 2023 at 09:31:42AM -0600, Alex Williamson wrote: > If a user creates an ioas within an iommufd, attaches a device to that > ioas and populates it with mappings, wouldn't the user expect the > device to have access to and honor those mappings? I think that's the > path we're headed down if we report a successful attach of a noiommu > device to an ioas. I understand we are going to drop no-iommu from this series, so this below is not relavent. But to clarify my general design idea here again The IOAS contains the mappings that userspace would like to use with no-iommu. Userspace would use a new IOCTL to pin and return the DMA addr's of those exact mappings. So attaching a noiommu to an IOAS is a necessary operation that should succeed. It doesn't make full API sense until we also get an ioctl to return the dma_addr_t lists. What is special about no-iommu is that the mapppings have to go through the special ioctl API to pin and translate, the IOVA cannot be used natively as a dma_addr. The IOAS is still used and still related to the device, it just for pinning and dma_addr generation not HW isolation. > We need to keep in mind that noiommu was meant to be a minimally > intrusive mechanism to provide a dummy vfio IOMMU backend and satisfy > the group requirements, solely for the purpose of making use of the > vfio device interface and without providing any DMA mapping services or > expectations. Well, no-iommu turned into a total hack job as soon as it wrongly relied on mlock() and /proc/ files to function. Even within its defined limitations this is an incorrect way to use the mm and DMA APIs. Memory under DMA must be locked using pin_user_pages(), mlock is not a substitution. I expect this is functionally broken these days, under some workloads, on certain kernel configurations. Even if we don't fully implement it, I prefer to imagine a design where no-iommu is implemented correctly and orient things toward that. > beyond the minimal code trickery of the legacy implementation. I hate > to ask, but could we reiterate our requirements for noiommu as a part of > the native iommufd interface for vfio? The nested userspace requirement > is gone now that hypervisors have vIOMMU support, so my assumption is > that this is only for bare metal systems without an IOMMU, which > ideally are less and less prevalent. I understood there was some desire for DPDK users to do this for higher performance on some systems. > that are actually going to adopt the noiommu cdev interface? What > terrible things happen if noiommu only exists in the vfio group compat > interface to iommufd and at some distant point in the future dies when > that gets disabled? I think it is fine, it is only for DPDK and if DPDK people really really care about this then they can implement it properly someday. I'm quite happy if we say we will not put no-iommu into the device cdev until it is put in fully correctly without relying on mlock/etc. Then the API construction would make alot more sense. Jason
[Intel-gfx] ✓ Fi.CI.BAT: success for mtl: add support for pmdemand (rev14)
== Series Details ==
Series: mtl: add support for pmdemand (rev14)
URL : https://patchwork.freedesktop.org/series/116949/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13236 -> Patchwork_116949v14
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/index.html
Participating hosts (41 -> 40)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_116949v14 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- bat-dg2-11: [PASS][1] -> [ABORT][2] ([i915#7913] / [i915#7979])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-dg2-11/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: NOTRUN -> [DMESG-WARN][3] ([i915#6367])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-rpls-1/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-rpls-1: NOTRUN -> [ABORT][4] ([i915#6687] / [i915#7978])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1:
- bat-dg2-8: [PASS][5] -> [FAIL][6] ([i915#7932])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-1.html
Possible fixes
* igt@i915_selftest@live@requests:
- bat-rpls-1: [ABORT][7] ([i915#7911] / [i915#7920] / [i915#7982])
-> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-rpls-1/igt@i915_selftest@l...@requests.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-rpls-1/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: [DMESG-WARN][9] ([i915#6367]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-rpls-2/igt@i915_selftest@l...@slpc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-rpls-2/igt@i915_selftest@l...@slpc.html
* {igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-c-dp-5}:
- {bat-adlp-11}: [DMESG-FAIL][11] ([i915#6868]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-c-dp-5.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-c-dp-5.html
* {igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-d-dp-5}:
- {bat-adlp-11}: [FAIL][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-d-dp-5.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-adlp-11/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-x...@pipe-d-dp-5.html
Warnings
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [SKIP][15] ([i915#3555] / [i915#4579]) -> [ABORT][16]
([i915#4579] / [i915#8260])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13236/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116949v14/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4309]: https://gitlab.freedesktop.org/drm/intel/issues/4309
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7979]: https://gitlab.freedesktop.org/drm/intel/issues/7979
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8260]:
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: implement internal workqueues (rev3)
On Tue, 2023-06-06 at 14:33 +0100, Tvrtko Ursulin wrote:
> On 06/06/2023 12:06, Coelho, Luciano wrote:
> > On Tue, 2023-06-06 at 11:06 +0100, Tvrtko Ursulin wrote:
> > > On 05/06/2023 16:06, Jani Nikula wrote:
> > > > On Wed, 31 May 2023, Patchwork wrote:
> > > > > Possible regressions
> > > > >
> > > > > * igt@gem_close_race@basic-process:
> > > > > - fi-blb-e6850: [PASS][1] -> [ABORT][2]
> > > > > [1]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/fi-blb-e6850/igt@gem_close_r...@basic-process.html
> > > > > [2]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/fi-blb-e6850/igt@gem_close_r...@basic-process.html
> > > > > - fi-hsw-4770:[PASS][3] -> [ABORT][4]
> > > > > [3]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/fi-hsw-4770/igt@gem_close_r...@basic-process.html
> > > > > [4]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/fi-hsw-4770/igt@gem_close_r...@basic-process.html
> > > > > - fi-elk-e7500: [PASS][5] -> [ABORT][6]
> > > > > [5]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/fi-elk-e7500/igt@gem_close_r...@basic-process.html
> > > > > [6]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/fi-elk-e7500/igt@gem_close_r...@basic-process.html
> > > > >
> > > > > * igt@i915_selftest@live@evict:
> > > > > - bat-adlp-9: [PASS][7] -> [ABORT][8]
> > > > > [7]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-adlp-9/igt@i915_selftest@l...@evict.html
> > > > > [8]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-adlp-9/igt@i915_selftest@l...@evict.html
> > > > > - bat-rpls-2: [PASS][9] -> [ABORT][10]
> > > > > [9]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-rpls-2/igt@i915_selftest@l...@evict.html
> > > > > [10]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-rpls-2/igt@i915_selftest@l...@evict.html
> > > > > - bat-adlm-1: [PASS][11] -> [ABORT][12]
> > > > > [11]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-adlm-1/igt@i915_selftest@l...@evict.html
> > > > > [12]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-adlm-1/igt@i915_selftest@l...@evict.html
> > > > > - bat-rpls-1: [PASS][13] -> [ABORT][14]
> > > > > [13]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-rpls-1/igt@i915_selftest@l...@evict.html
> > > > > [14]:
> > > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-rpls-1/igt@i915_selftest@l...@evict.html
> > > >
> > > > This still fails consistently, I have no clue why, and the above aren't
> > > > even remotely related to display.
> > > >
> > > > What now? Tvrtko?
> > >
> > > Hmm..
> > >
> > > <4> [46.782321] Chain exists of:
> > > (wq_completion)i915 --> (work_completion)(>mm.free_work) -->
> > > >mutex
> > > <4> [46.782329] Possible unsafe locking scenario:
> > > <4> [46.782332]CPU0CPU1
> > > <4> [46.782334]
> > > <4> [46.782337] lock(>mutex);
> > > <4> [46.782340]
> > > lock((work_completion)(>mm.free_work));
> > > <4> [46.782344]lock(>mutex);
> > > <4> [46.782348] lock((wq_completion)i915);
> > >
> > >
> > > "(wq_completion)i915"
> > >
> > > So it's not about the new wq even. Perhaps it is this hunk:
> > >
> > > --- a/drivers/gpu/drm/i915/intel_wakeref.c
> > > +++ b/drivers/gpu/drm/i915/intel_wakeref.c
> > > @@ -75,7 +75,7 @@ void __intel_wakeref_put_last(struct intel_wakeref *wf,
> > > unsigned long flags)
> > >
> > > /* Assume we are not in process context and so cannot sleep. */
> > > if (flags & INTEL_WAKEREF_PUT_ASYNC ||
> > > !mutex_trylock(>mutex)) {
> > > - mod_delayed_work(system_wq, >work,
> > > + mod_delayed_work(wf->i915->wq, >work,
> > >
> > > Transformation from this patch otherwise is system_wq with the new
> > > unordered wq, so I'd try that first.
> >
> > Indeed this seems to be exactly the block that is causing the issue. I
> > was sort of bisecting through all these changes and reverting this one
> > prevents the lockdep splat from happening...
> >
> > So there's something that needs to be synced with the system_wq here,
> > but what? I need to dig into it.
>
> AFAICT it is saying that i915->mm.free_work and engine->wakeref.work
> must not be on the same ordered wq. Otherwise execbuf call trace
> flushing under vm->mutex can deadlock against the free worker trying to
> grab vm->mutex. If engine->wakeref.work is on a separate unordered wq it
> would be safe since then execution will not be serialized with the
> free_work. So just using the new i915->unordered_wq for this hunk should
>
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for mtl: add support for pmdemand (rev14)
== Series Details == Series: mtl: add support for pmdemand (rev14) URL : https://patchwork.freedesktop.org/series/116949/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mtl: add support for pmdemand (rev14)
== Series Details == Series: mtl: add support for pmdemand (rev14) URL : https://patchwork.freedesktop.org/series/116949/ State : warning == Summary == Error: dim checkpatch failed 8bf8cd20b5c7 drm/i915: fix the derating percentage for MTL 0e53e38b6107 drm/i915: update the QGV point frequency calculations 2453db29ae96 drm/i915: store the peak bw per QGV point 6be9b38effe8 drm/i915: extract intel_bw_check_qgv_points() b67308525d7d drm/i915: modify max_bw to return index to intel_bw_info d56333a485fd drm/i915/mtl: find the best QGV point for the SAGV configuration 96502e589e60 drm/i915/mtl: Add support for PM DEMAND Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:409: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #409: new file mode 100644 -:1226: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #1226: FILE: drivers/gpu/drm/i915/i915_reg.h:4514: +#define XELPDP_PMDEMAND_QCLK_GV_BW(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x) -:1228: WARNING:LONG_LINE: line length of 109 exceeds 100 columns #1228: FILE: drivers/gpu/drm/i915/i915_reg.h:4516: +#define XELPDP_PMDEMAND_VOLTAGE_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x) -:1230: WARNING:LONG_LINE: line length of 109 exceeds 100 columns #1230: FILE: drivers/gpu/drm/i915/i915_reg.h:4518: +#define XELPDP_PMDEMAND_QCLK_GV_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x) -:1232: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #1232: FILE: drivers/gpu/drm/i915/i915_reg.h:4520: +#define XELPDP_PMDEMAND_PIPES(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x) -:1234: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #1234: FILE: drivers/gpu/drm/i915/i915_reg.h:4522: +#define XELPDP_PMDEMAND_DBUFS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x) -:1240: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #1240: FILE: drivers/gpu/drm/i915/i915_reg.h:4528: +#define XELPDP_PMDEMAND_CDCLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x) -:1242: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #1242: FILE: drivers/gpu/drm/i915/i915_reg.h:4530: +#define XELPDP_PMDEMAND_DDICLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x) -:1244: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #1244: FILE: drivers/gpu/drm/i915/i915_reg.h:4532: +#define XELPDP_PMDEMAND_SCALERS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x) total: 0 errors, 9 warnings, 0 checks, 1117 lines checked
Re: [Intel-gfx] [PATCH v14 7/7] drm/i915/mtl: Add support for PM DEMAND
On Tue, Jun 06, 2023 at 12:35:09PM +0300, Vinod Govindapillai wrote: > From: Mika Kahola > > MTL introduces a new way to instruct the PUnit with > power and bandwidth requirements of DE. Add the functionality > to program the registers and handle waits using interrupts. > The current wait time for timeouts is programmed for 10 msecs to > factor in the worst case scenarios. Changes made to use REG_BIT > for a register that we touched(GEN8_DE_MISC_IER _MMIO). > > Wa_14016740474 is added which applies to Xe_LPD+ display > > v2: checkpatch warning fixes, simplify program pmdemand part > > v3: update to dbufs and pipes values to pmdemand register(stan) > Removed the macro usage in update_pmdemand_values() > > v4: move the pmdemand_pre_plane_update before cdclk update > pmdemand_needs_update included cdclk params comparisons > pmdemand_state NULL check (Gustavo) > pmdemand.o in sorted order in the makefile (Jani) > update pmdemand misc irq handler loop (Gustavo) > active phys bitmask and programming correction (Gustavo) > > v5: simplify pmdemand_state structure > simplify methods to find active phys and max port clock > Timeout in case of previou pmdemand task pending (Gustavo) > > v6: rebasing > updates to max_ddiclk calculations (Gustavo) > updates to active_phys count method (Gustavo) > > v7: use two separate loop to iterate throug old and new > crtc states to calculate the active phys (Gustavo) > > v8: use uniform function names (Gustavo) > > v9: For phys change iterate through connectors (Imre) > Look for change in phys for pmdemand update (Gustavo, Imre) > Some more stlying changes (Imre) > Update pmdemand state during HW readout/sanitize (Imre) > > v10: Fix CI checkpatch warnings > > v11: use correct pmdemand object pointer during hw readout, > simplify the check for phys need update (Gustavo) > > v12: Handle possible non serialize cases (Imre) > Initialise also pmdemand params HW readout (Imre) > Update active phys mask during sanitize calls (Imre) > Check TC/encoder changes to limit connector update (Imre) > > v13: Check display version before accessing pmdemand functions > > Bspec: 66451, 64636, 64602, 64603 > Cc: Matt Atwood > Cc: Matt Roper > Cc: Lucas De Marchi > Cc: Gustavo Sousa > Signed-off-by: José Roberto de Souza > Signed-off-by: Radhakrishna Sripada > Signed-off-by: Gustavo Sousa > Signed-off-by: Mika Kahola > Signed-off-by: Vinod Govindapillai > Reviewed-by: Stanislav Lisovskiy > Acked-by: Gustavo Sousa > --- > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/display/intel_display.c | 14 + > .../gpu/drm/i915/display/intel_display_core.h | 9 + > .../drm/i915/display/intel_display_driver.c | 7 + > .../gpu/drm/i915/display/intel_display_irq.c | 23 +- > .../drm/i915/display/intel_display_power.c| 14 +- > .../drm/i915/display/intel_modeset_setup.c| 36 + > drivers/gpu/drm/i915/display/intel_pmdemand.c | 714 ++ > drivers/gpu/drm/i915/display/intel_pmdemand.h | 69 ++ > drivers/gpu/drm/i915/i915_reg.h | 36 +- > 10 files changed, 917 insertions(+), 6 deletions(-) > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.c > create mode 100644 drivers/gpu/drm/i915/display/intel_pmdemand.h > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index 1c9ed4c52760..2cd8de174bf6 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -269,6 +269,7 @@ i915-y += \ > display/intel_pch_display.o \ > display/intel_pch_refclk.o \ > display/intel_plane_initial.o \ > + display/intel_pmdemand.o \ > display/intel_psr.o \ > display/intel_quirks.o \ > display/intel_sprite.o \ > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index f51a55f4e9d0..5cbf5eae2414 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -99,6 +99,7 @@ > #include "intel_pcode.h" > #include "intel_pipe_crc.h" > #include "intel_plane_initial.h" > +#include "intel_pmdemand.h" > #include "intel_pps.h" > #include "intel_psr.h" > #include "intel_sdvo.h" > @@ -6352,6 +6353,10 @@ int intel_atomic_check(struct drm_device *dev, > return ret; > } > > + ret = intel_pmdemand_atomic_check(state); > + if (ret) > + goto fail; > + > ret = intel_atomic_check_crtcs(state); > if (ret) > goto fail; > @@ -6997,6 +7002,14 @@ static void intel_atomic_commit_tail(struct > intel_atomic_state *state) > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) > crtc->config = new_crtc_state; > > + /* > + * In XE_LPD+ Pmdemand combines many parameters such as voltage index, > + * plls, cdclk frequency, QGV point selection
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: implement internal workqueues (rev3)
On 06/06/2023 12:06, Coelho, Luciano wrote:
On Tue, 2023-06-06 at 11:06 +0100, Tvrtko Ursulin wrote:
On 05/06/2023 16:06, Jani Nikula wrote:
On Wed, 31 May 2023, Patchwork wrote:
Possible regressions
* igt@gem_close_race@basic-process:
- fi-blb-e6850: [PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/fi-blb-e6850/igt@gem_close_r...@basic-process.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/fi-blb-e6850/igt@gem_close_r...@basic-process.html
- fi-hsw-4770:[PASS][3] -> [ABORT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/fi-hsw-4770/igt@gem_close_r...@basic-process.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/fi-hsw-4770/igt@gem_close_r...@basic-process.html
- fi-elk-e7500: [PASS][5] -> [ABORT][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/fi-elk-e7500/igt@gem_close_r...@basic-process.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/fi-elk-e7500/igt@gem_close_r...@basic-process.html
* igt@i915_selftest@live@evict:
- bat-adlp-9: [PASS][7] -> [ABORT][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-adlp-9/igt@i915_selftest@l...@evict.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-adlp-9/igt@i915_selftest@l...@evict.html
- bat-rpls-2: [PASS][9] -> [ABORT][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-rpls-2/igt@i915_selftest@l...@evict.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-rpls-2/igt@i915_selftest@l...@evict.html
- bat-adlm-1: [PASS][11] -> [ABORT][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-adlm-1/igt@i915_selftest@l...@evict.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-adlm-1/igt@i915_selftest@l...@evict.html
- bat-rpls-1: [PASS][13] -> [ABORT][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13203/bat-rpls-1/igt@i915_selftest@l...@evict.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_117618v3/bat-rpls-1/igt@i915_selftest@l...@evict.html
This still fails consistently, I have no clue why, and the above aren't
even remotely related to display.
What now? Tvrtko?
Hmm..
<4> [46.782321] Chain exists of:
(wq_completion)i915 --> (work_completion)(>mm.free_work) -->
>mutex
<4> [46.782329] Possible unsafe locking scenario:
<4> [46.782332]CPU0CPU1
<4> [46.782334]
<4> [46.782337] lock(>mutex);
<4> [46.782340]
lock((work_completion)(>mm.free_work));
<4> [46.782344]lock(>mutex);
<4> [46.782348] lock((wq_completion)i915);
"(wq_completion)i915"
So it's not about the new wq even. Perhaps it is this hunk:
--- a/drivers/gpu/drm/i915/intel_wakeref.c
+++ b/drivers/gpu/drm/i915/intel_wakeref.c
@@ -75,7 +75,7 @@ void __intel_wakeref_put_last(struct intel_wakeref *wf,
unsigned long flags)
/* Assume we are not in process context and so cannot sleep. */
if (flags & INTEL_WAKEREF_PUT_ASYNC || !mutex_trylock(>mutex)) {
- mod_delayed_work(system_wq, >work,
+ mod_delayed_work(wf->i915->wq, >work,
Transformation from this patch otherwise is system_wq with the new unordered
wq, so I'd try that first.
Indeed this seems to be exactly the block that is causing the issue. I
was sort of bisecting through all these changes and reverting this one
prevents the lockdep splat from happening...
So there's something that needs to be synced with the system_wq here,
but what? I need to dig into it.
AFAICT it is saying that i915->mm.free_work and engine->wakeref.work
must not be on the same ordered wq. Otherwise execbuf call trace
flushing under vm->mutex can deadlock against the free worker trying to
grab vm->mutex. If engine->wakeref.work is on a separate unordered wq it
would be safe since then execution will not be serialized with the
free_work. So just using the new i915->unordered_wq for this hunk should
work.
Regards,
Tvrtko
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow user to set cache at BO creation
== Series Details == Series: drm/i915: Allow user to set cache at BO creation URL : https://patchwork.freedesktop.org/series/118913/ State : success == Summary == CI Bug Log - changes from CI_DRM_13235 -> Patchwork_118913v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/index.html Participating hosts (40 -> 40) -- Additional (1): bat-atsm-1 Missing(1): fi-snb-2520m New tests - New tests have been introduced between CI_DRM_13235 and Patchwork_118913v1: ### New IGT tests (1) ### * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-dp-5: - Statuses : 1 pass(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_118913v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap@basic: - bat-atsm-1: NOTRUN -> [SKIP][1] ([i915#4083]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-atsm-1/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-atsm-1: NOTRUN -> [SKIP][2] ([i915#4079]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-atsm-1/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-atsm-1: NOTRUN -> [SKIP][3] ([i915#4077]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-atsm-1/igt@gem_tiled_fence_bl...@basic.html * igt@i915_pm_backlight@basic-brightness@edp-1: - bat-rplp-1: NOTRUN -> [ABORT][4] ([i915#7077]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-rplp-1/igt@i915_pm_backlight@basic-brightn...@edp-1.html * igt@i915_pm_rps@basic-api: - bat-atsm-1: NOTRUN -> [SKIP][5] ([i915#6621]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-atsm-1/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@slpc: - bat-rpls-1: NOTRUN -> [DMESG-WARN][6] ([i915#6367]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html * igt@i915_suspend@basic-s3-without-i915: - bat-atsm-1: NOTRUN -> [SKIP][7] ([i915#6645]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-atsm-1/igt@i915_susp...@basic-s3-without-i915.html - bat-rpls-1: NOTRUN -> [ABORT][8] ([i915#6687] / [i915#7978]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@size-max: - bat-atsm-1: NOTRUN -> [SKIP][9] ([i915#6077]) +36 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-atsm-1/igt@kms_addfb_ba...@size-max.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#7828]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic: - bat-atsm-1: NOTRUN -> [SKIP][11] ([i915#6078]) +19 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-atsm-1/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html * igt@kms_flip@basic-flip-vs-wf_vblank: - bat-atsm-1: NOTRUN -> [SKIP][12] ([i915#6166]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-atsm-1/igt@kms_flip@basic-flip-vs-wf_vblank.html * igt@kms_force_connector_basic@force-load-detect: - bat-atsm-1: NOTRUN -> [SKIP][13] ([i915#6093]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-atsm-1/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence: - bat-atsm-1: NOTRUN -> [SKIP][14] ([i915#1836]) +6 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-atsm-1/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html - bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#1845] / [i915#5354]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-dg2-11/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html * igt@kms_prop_blob@basic: - bat-atsm-1: NOTRUN -> [SKIP][16] ([i915#7357]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-atsm-1/igt@kms_prop_b...@basic.html * igt@kms_psr@sprite_plane_onoff: - bat-atsm-1: NOTRUN -> [SKIP][17] ([i915#1072]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118913v1/bat-atsm-1/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-atsm-1: NOTRUN -> [SKIP][18] ([i915#6094]) [18]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Allow user to set cache at BO creation
== Series Details == Series: drm/i915: Allow user to set cache at BO creation URL : https://patchwork.freedesktop.org/series/118913/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Allow user to set cache at BO creation
== Series Details == Series: drm/i915: Allow user to set cache at BO creation URL : https://patchwork.freedesktop.org/series/118913/ State : warning == Summary == Error: dim checkpatch failed 61d84b10017c drm/i915: Allow user to set cache at BO creation -:23: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #23: https://www.intel.com/content/www/us/en/docs/graphics-for-linux/developer-reference/1-0/tiger-lake.html total: 0 errors, 1 warnings, 0 checks, 136 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix a NULL vs IS_ERR() bug
== Series Details == Series: drm/i915: Fix a NULL vs IS_ERR() bug URL : https://patchwork.freedesktop.org/series/118907/ State : success == Summary == CI Bug Log - changes from CI_DRM_13235 -> Patchwork_118907v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/index.html Participating hosts (40 -> 40) -- Additional (1): bat-atsm-1 Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_118907v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap@basic: - bat-atsm-1: NOTRUN -> [SKIP][1] ([i915#4083]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-atsm-1: NOTRUN -> [SKIP][2] ([i915#4079]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-atsm-1: NOTRUN -> [SKIP][3] ([i915#4077]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@gem_tiled_fence_bl...@basic.html * igt@i915_pm_backlight@basic-brightness@edp-1: - bat-rplp-1: NOTRUN -> [ABORT][4] ([i915#7077]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-rplp-1/igt@i915_pm_backlight@basic-brightn...@edp-1.html * igt@i915_pm_rps@basic-api: - bat-atsm-1: NOTRUN -> [SKIP][5] ([i915#6621]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@i915_pm_...@basic-api.html * igt@i915_suspend@basic-s3-without-i915: - bat-atsm-1: NOTRUN -> [SKIP][6] ([i915#6645]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@i915_susp...@basic-s3-without-i915.html - bat-rpls-1: NOTRUN -> [ABORT][7] ([i915#6687] / [i915#7978]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@size-max: - bat-atsm-1: NOTRUN -> [SKIP][8] ([i915#6077]) +36 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@kms_addfb_ba...@size-max.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#7828]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-dg2-11/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic: - bat-atsm-1: NOTRUN -> [SKIP][10] ([i915#6078]) +19 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html * igt@kms_flip@basic-flip-vs-wf_vblank: - bat-atsm-1: NOTRUN -> [SKIP][11] ([i915#6166]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@kms_flip@basic-flip-vs-wf_vblank.html * igt@kms_force_connector_basic@force-load-detect: - bat-atsm-1: NOTRUN -> [SKIP][12] ([i915#6093]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence: - bat-atsm-1: NOTRUN -> [SKIP][13] ([i915#1836]) +6 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html * igt@kms_prop_blob@basic: - bat-atsm-1: NOTRUN -> [SKIP][14] ([i915#7357]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@kms_prop_b...@basic.html * igt@kms_psr@sprite_plane_onoff: - bat-atsm-1: NOTRUN -> [SKIP][15] ([i915#1072]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-atsm-1: NOTRUN -> [SKIP][16] ([i915#6094]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-atsm-1: NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#6078]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@prime_v...@basic-fence-flip.html * igt@prime_vgem@basic-gtt: - bat-atsm-1: NOTRUN -> [SKIP][18] ([fdo#109295] / [i915#4077]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118907v1/bat-atsm-1/igt@prime_v...@basic-gtt.html * igt@prime_vgem@basic-write: - bat-atsm-1: NOTRUN -> [SKIP][19] ([fdo#109295]) +2 similar issues
Re: [Intel-gfx] [PATCH] drm/i915/mtl: update DP 2.0 vswing table for C20 phy
> -Original Message-
> From: Lee, Shawn C
> Sent: Tuesday, June 6, 2023 1:43 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Lee, Shawn C ; Kahola, Mika
> ; Taylor, Clinton A
> ; Sripada, Radhakrishna
> ; Shankar, Uma
>
> Subject: [PATCH] drm/i915/mtl: update DP 2.0 vswing table for C20 phy
>
> Update preset 15 setting to align the latest bspec value.
>
> Bspec: 74104
Reviewed-by: Mika Kahola
> Signed-off-by: Lee Shawn C
> Cc: Mika Kahola
> Cc: Clint Taylor
> Cc: Radhakrishna Sripada
> Cc: Uma Shankar
> ---
> drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index 6a1507515119..2af91a06f5fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1086,7 +1086,7 @@ static const union intel_ddi_buf_trans_entry
> _mtl_c20_trans_uhbr[] = {
> { .snps = { 37, 4, 7 } }, /* preset 12 */
> { .snps = { 33, 4, 11 } }, /* preset 13 */
> { .snps = { 40, 8, 0 } }, /* preset 14 */
> - { .snps = { 28, 2, 2 } }, /* preset 15 */
> + { .snps = { 30, 2, 2 } }, /* preset 15 */
> };
>
> /* HDMI2.0 */
> --
> 2.31.1
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Add some missing error propagation
== Series Details ==
Series: drm/i915/selftests: Add some missing error propagation
URL : https://patchwork.freedesktop.org/series/118867/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13230_full -> Patchwork_118867v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (8 -> 6)
--
Missing(2): shard-rkl0 shard-dg1
Known issues
Here are the changes found in Patchwork_118867v1_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@i915_suspend@forcewake:
- shard-apl: [PASS][1] -> [ABORT][2] ([i915#180])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13230/shard-apl1/igt@i915_susp...@forcewake.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/shard-apl6/igt@i915_susp...@forcewake.html
* igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][3] ([fdo#109271]) +20 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/shard-apl4/igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_mc_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2346]) +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13230/shard-glk8/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/shard-glk7/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* igt@kms_draw_crc@draw-method-blt@xrgb2101010-ytiled:
- shard-glk: [PASS][6] -> [DMESG-WARN][7] ([i915#7936])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13230/shard-glk4/igt@kms_draw_crc@draw-method-...@xrgb2101010-ytiled.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/shard-glk7/igt@kms_draw_crc@draw-method-...@xrgb2101010-ytiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#79])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13230/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interrupti...@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271]) +22 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/shard-snb2/igt@kms_f...@2x-plain-flip-fb-recreate.html
*
igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4579]) +14
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/shard-snb6/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-...@pipe-b-vga-1.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-dp-1:
- shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4579])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/shard-apl4/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0...@pipe-c-dp-1.html
* igt@kms_setmode@basic@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [FAIL][13] ([i915#5465]) +1 similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/shard-snb1/igt@kms_setmode@ba...@pipe-a-hdmi-a-1.html
Possible fixes
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[FAIL][14] ([i915#7742]) -> [PASS][15] +1 similar
issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13230/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/shard-rkl-7/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
* igt@gem_eio@hibernate:
- {shard-tglu}: [ABORT][16] ([i915#7975] / [i915#8213] / [i915#8398])
-> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13230/shard-tglu-10/igt@gem_...@hibernate.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/shard-tglu-6/igt@gem_...@hibernate.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][18] ([i915#2842]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13230/shard-apl3/igt@gem_exec_fair@basic-none-s...@rcs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_118867v1/shard-apl3/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][20] ([i915#2842]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13230/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[21]:
Re: [Intel-gfx] [PATCH v17 1/1] drm/i915: Allow user to set cache at BO creation
> > > > To comply with the design that buffer objects shall have immutable
> > > > cache setting through out their life cycle, {set, get}_caching ioctl's
> > > > are no longer supported from MTL onward. With that change caching
> > > > policy can only be set at object creation time. The current code
> > > > applies a default (platform dependent) cache setting for all objects.
> > > > However this is not optimal for performance tuning. The patch extends
> > > > the existing gem_create uAPI to let user set PAT index for the object
> > > > at creation time.
> > > > The new extension is platform independent, so UMD's can switch to using
> > > > this extension for older platforms as well, while {set, get}_caching are
> > > > still supported on these legacy paltforms for compatibility reason.
> > > > However, since PAT index was not clearly defined for platforms prior to
> > > > GEN12 (TGL), so we are limiting this externsion to GEN12+ platforms
> > > > only. See ext_set_pat() in for the implementation details.
> > > >
> > > > Note: The documentation related to the PAT/MOCS tables is currently
> > > > available for Tiger Lake here:
> > > > https://www.intel.com/content/www/us/en/docs/graphics-for-linux/developer-reference/1-0/tiger-lake.html
> > > >
> > > > BSpec: 45101
> > > >
> > > > Mesa support has been submitted in this merge request:
> > > > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
> > > >
> > > > The media driver is supported by the following commits:
> > > > https://github.com/intel/media-driver/commit/92c00a857433ebb34ec575e9834f473c6fcb6341
> > > > https://github.com/intel/media-driver/commit/fd375cf2c5e1f6bf6b43258ff797b3134aadc9fd
> > > > https://github.com/intel/media-driver/commit/08dd244b22484770a33464c2c8ae85430e548000
>
> Andi, let's still get these corrected before merging once the media-driver
> revert is completed.
Sure!
At least this doesn't need a new version to be respinned.
Please, Carl, link the new pull request and I will update the
commit log.
Andi
Re: [Intel-gfx] [PATCH v17 1/1] drm/i915: Allow user to set cache at BO creation
Quoting Andi Shyti (2023-06-06 13:18:06)
> On Tue, Jun 06, 2023 at 11:10:04AM +0100, Tvrtko Ursulin wrote:
> >
> > On 06/06/2023 11:00, Andi Shyti wrote:
> > > From: Fei Yang
> > >
> > > To comply with the design that buffer objects shall have immutable
> > > cache setting through out their life cycle, {set, get}_caching ioctl's
> > > are no longer supported from MTL onward. With that change caching
> > > policy can only be set at object creation time. The current code
> > > applies a default (platform dependent) cache setting for all objects.
> > > However this is not optimal for performance tuning. The patch extends
> > > the existing gem_create uAPI to let user set PAT index for the object
> > > at creation time.
> > > The new extension is platform independent, so UMD's can switch to using
> > > this extension for older platforms as well, while {set, get}_caching are
> > > still supported on these legacy paltforms for compatibility reason.
> > > However, since PAT index was not clearly defined for platforms prior to
> > > GEN12 (TGL), so we are limiting this externsion to GEN12+ platforms
> > > only. See ext_set_pat() in for the implementation details.
> > >
> > > Note: The documentation related to the PAT/MOCS tables is currently
> > > available for Tiger Lake here:
> > > https://www.intel.com/content/www/us/en/docs/graphics-for-linux/developer-reference/1-0/tiger-lake.html
> > >
> > > BSpec: 45101
> > >
> > > Mesa support has been submitted in this merge request:
> > > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
> > >
> > > The media driver is supported by the following commits:
> > > https://github.com/intel/media-driver/commit/92c00a857433ebb34ec575e9834f473c6fcb6341
> > > https://github.com/intel/media-driver/commit/fd375cf2c5e1f6bf6b43258ff797b3134aadc9fd
> > > https://github.com/intel/media-driver/commit/08dd244b22484770a33464c2c8ae85430e548000
Andi, let's still get these corrected before merging once the media-driver
revert is completed.
Regards, Joonas
> > > The IGT test related to this change is
> > > igt@gem_create@create-ext-set-pat
> > >
> > > Signed-off-by: Fei Yang
> > > Cc: Chris Wilson
> > > Cc: Matt Roper
> > > Cc: Andi Shyti
> > > Reviewed-by: Andi Shyti
> > > Acked-by: Jordan Justen
> > > Tested-by: Jordan Justen
> > > Acked-by: Carl Zhang
> > > Tested-by: Lihao Gu
> > > Signed-off-by: Andi Shyti
> >
> > Acked-by: Tvrtko Ursulin
>
> Fiuuu! Thanks a lot, Tvrtko!
>
> As soon as CI gives green light, I will get this in.
>
> Andi
Re: [Intel-gfx] [PATCH] drm/i915: Implement fdinfo memory stats printing
On 06/06/2023 10:47, Tvrtko Ursulin wrote:
On 05/06/2023 23:22, Andi Shyti wrote:
Hi Tvrtko,
On Mon, Jun 05, 2023 at 03:37:20PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Use the newly added drm_print_memory_stats helper to show memory
utilisation of our objects in drm/driver specific fdinfo output.
To collect the stats we walk the per memory regions object lists
and accumulate object size into the respective drm_memory_stats
categories.
Objects with multiple possible placements are reported in multiple
regions for total and shared sizes, while other categories are
counted only for the currently active region.
Signed-off-by: Tvrtko Ursulin
Cc: Rob Clark
---
drivers/gpu/drm/i915/i915_drm_client.c | 66 ++
1 file changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c
b/drivers/gpu/drm/i915/i915_drm_client.c
index 2a44b3876cb5..2a40f763f8f6 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -41,6 +41,70 @@ void __i915_drm_client_free(struct kref *kref)
}
#ifdef CONFIG_PROC_FS
+static void
+add_obj_meminfo(struct drm_i915_gem_object *obj,
+ struct intel_memory_region *mr,
+ struct drm_memory_stats stats[INTEL_REGION_UNKNOWN])
+{
+ u64 sz = obj->base.size;
+ enum intel_region_id id;
+ unsigned int i;
+
+ id = mr->id;
+ if (obj->base.handle_count > 1)
+ stats[id].shared += sz;
+ else
+ stats[id].private += sz;
+
+ if (i915_gem_object_has_pages(obj)) {
+ stats[id].resident += sz;
+
+ if (!dma_resv_test_signaled(obj->base.resv,
+ dma_resv_usage_rw(true)))
+ stats[id].active += sz;
+ else if (i915_gem_object_is_shrinkable(obj) &&
+ obj->mm.madv == I915_MADV_DONTNEED)
+ stats[id].purgeable += sz;
this is a bit off... otherwise:
Reviewed-by: Andi Shyti
Thanks!
I will sit on this until I can find time to add some tests to drm_fdinfo.c.
Actually.. Aravind pointed off list that my brain wasn't switched on
when writing this. Fdinfo stats need to be per client and this patch is
therefore almost completely bogus.
Regards,
Tvrtko
Andi
+ }
+
+ /* Attribute size and shared to all possible object memory
regions. */
+ for (i = 0; i < obj->mm.n_placements; i++) {
+ if (obj->mm.placements[i] == mr)
+ continue;
+
+ id = obj->mm.placements[i]->id;
+ if (obj->base.handle_count > 1)
+ stats[id].shared += sz;
+ else
+ stats[id].private += sz;
+ }
+}
+
+static void show_meminfo(struct drm_printer *p, struct drm_file *file)
+{
+ struct drm_i915_file_private *file_priv = file->driver_priv;
+ struct drm_memory_stats stats[INTEL_REGION_UNKNOWN] = {};
+ struct drm_i915_private *i915 = file_priv->i915;
+ struct intel_memory_region *mr;
+ unsigned int id;
+
+ for_each_memory_region(mr, i915, id) {
+ struct drm_i915_gem_object *obj;
+
+ mutex_lock(>objects.lock);
+ list_for_each_entry(obj, >objects.list, mm.region_link)
+ add_obj_meminfo(obj, mr, stats);
+ mutex_unlock(>objects.lock);
+ }
+
+ for_each_memory_region(mr, i915, id)
+ drm_print_memory_stats(p,
+ [id],
+ DRM_GEM_OBJECT_RESIDENT |
+ DRM_GEM_OBJECT_PURGEABLE,
+ mr->name);
+}
+
static const char * const uabi_class_names[] = {
[I915_ENGINE_CLASS_RENDER] = "render",
[I915_ENGINE_CLASS_COPY] = "copy",
@@ -102,6 +166,8 @@ void i915_drm_client_fdinfo(struct drm_printer
*p, struct drm_file *file)
*
**
*/
+ show_meminfo(p, file);
+
if (GRAPHICS_VER(i915) < 8)
return;
--
2.39.2
