[Intel-gfx] ✗ Fi.CI.IGT: failure for Reduce MTL-specific platform checks (rev4)
== Series Details == Series: Reduce MTL-specific platform checks (rev4) URL : https://patchwork.freedesktop.org/series/120943/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13517_full -> Patchwork_120943v4_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_120943v4_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_120943v4_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_120943v4_full: ### IGT changes ### Possible regressions * igt@perf@gen12-invalid-class-instance: - shard-apl: [PASS][1] -> [ABORT][2] +14 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/shard-apl1/igt@p...@gen12-invalid-class-instance.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-apl2/igt@p...@gen12-invalid-class-instance.html * igt@perf@gen12-unprivileged-single-ctx-counters@rcs0: - shard-dg1: [PASS][3] -> [ABORT][4] +13 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/shard-dg1-15/igt@perf@gen12-unprivileged-single-ctx-count...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-dg1-18/igt@perf@gen12-unprivileged-single-ctx-count...@rcs0.html * igt@perf@global-sseu-config: - shard-tglu: NOTRUN -> [ABORT][5] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-tglu-9/igt@p...@global-sseu-config.html - shard-glk: NOTRUN -> [ABORT][6] +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-glk4/igt@p...@global-sseu-config.html * igt@perf@invalid-oa-metric-set-id: - shard-glk: [PASS][7] -> [ABORT][8] +14 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/shard-glk5/igt@p...@invalid-oa-metric-set-id.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-glk3/igt@p...@invalid-oa-metric-set-id.html * igt@perf@missing-sample-flags: - shard-tglu: [PASS][9] -> [ABORT][10] +15 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/shard-tglu-3/igt@p...@missing-sample-flags.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-tglu-7/igt@p...@missing-sample-flags.html * igt@perf@non-system-wide-paranoid: - shard-dg2: [PASS][11] -> [ABORT][12] +10 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/shard-dg2-12/igt@p...@non-system-wide-paranoid.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-dg2-10/igt@p...@non-system-wide-paranoid.html * igt@perf@polling@0-rcs0: - shard-rkl: [PASS][13] -> [ABORT][14] +14 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/shard-rkl-1/igt@perf@poll...@0-rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-rkl-7/igt@perf@poll...@0-rcs0.html * igt@perf@stress-open-close: - shard-dg2: NOTRUN -> [ABORT][15] +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-dg2-2/igt@p...@stress-open-close.html - shard-rkl: NOTRUN -> [ABORT][16] +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-rkl-7/igt@p...@stress-open-close.html - shard-dg1: NOTRUN -> [ABORT][17] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-dg1-16/igt@p...@stress-open-close.html - shard-apl: NOTRUN -> [ABORT][18] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-apl3/igt@p...@stress-open-close.html Warnings * igt@perf@gen8-unprivileged-single-ctx-counters: - shard-dg2: [SKIP][19] ([i915#2436]) -> [ABORT][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/shard-dg2-6/igt@p...@gen8-unprivileged-single-ctx-counters.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-dg2-1/igt@p...@gen8-unprivileged-single-ctx-counters.html - shard-rkl: [SKIP][21] ([i915#2436]) -> [ABORT][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/shard-rkl-7/igt@p...@gen8-unprivileged-single-ctx-counters.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/shard-rkl-1/igt@p...@gen8-unprivileged-single-ctx-counters.html - shard-dg1: [SKIP][23] ([fdo#109289]) -> [ABORT][24] [23]: https://intel-gfx-ci.
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Dual refresh rate fastset fixes with VRR fastset (rev3)
== Series Details == Series: drm/i915/display: Dual refresh rate fastset fixes with VRR fastset (rev3) URL : https://patchwork.freedesktop.org/series/122252/ State : success == Summary == CI Bug Log - changes from CI_DRM_13517_full -> Patchwork_122252v3_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_122252v3_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@render-ccs: - shard-dg2: NOTRUN -> [FAIL][1] ([i915#6122]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-dg2-6/igt@api_intel...@render-ccs.html * igt@debugfs_test@basic-hwmon: - shard-mtlp: NOTRUN -> [SKIP][2] ([i915#7456]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-mtlp-2/igt@debugfs_t...@basic-hwmon.html * igt@device_reset@cold-reset-bound: - shard-dg2: NOTRUN -> [SKIP][3] ([i915#7701]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-dg2-10/igt@device_re...@cold-reset-bound.html * igt@drm_fdinfo@most-busy-check-all@bcs0: - shard-dg2: NOTRUN -> [SKIP][4] ([i915#8414]) +9 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-dg2-10/igt@drm_fdinfo@most-busy-check-...@bcs0.html * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [PASS][5] -> [FAIL][6] ([i915#7742]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/shard-rkl-7/igt@drm_fdinfo@most-busy-check-...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-rkl-1/igt@drm_fdinfo@most-busy-check-...@rcs0.html * igt@drm_fdinfo@virtual-idle: - shard-rkl: NOTRUN -> [FAIL][7] ([i915#7742]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-rkl-7/igt@drm_fdi...@virtual-idle.html * igt@drm_mm@drm_mm_test: - shard-mtlp: NOTRUN -> [SKIP][8] ([i915#8661]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-mtlp-3/igt@drm_mm@drm_mm_test.html * igt@feature_discovery@psr1: - shard-rkl: NOTRUN -> [SKIP][9] ([i915#658]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-rkl-7/igt@feature_discov...@psr1.html * igt@gem_basic@multigpu-create-close: - shard-dg2: NOTRUN -> [SKIP][10] ([i915#7697]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-dg2-6/igt@gem_ba...@multigpu-create-close.html * igt@gem_create@create-ext-cpu-access-big: - shard-dg2: NOTRUN -> [ABORT][11] ([i915#7461]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-dg2-10/igt@gem_cre...@create-ext-cpu-access-big.html * igt@gem_create@create-ext-set-pat: - shard-dg2: NOTRUN -> [SKIP][12] ([i915#8562]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-dg2-1/igt@gem_cre...@create-ext-set-pat.html * igt@gem_ctx_persistence@file: - shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-snb6/igt@gem_ctx_persiste...@file.html * igt@gem_ctx_persistence@hang: - shard-mtlp: NOTRUN -> [SKIP][14] ([i915#8555]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-mtlp-3/igt@gem_ctx_persiste...@hang.html * igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs1: - shard-mtlp: NOTRUN -> [SKIP][15] ([i915#5882]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-mtlp-3/igt@gem_ctx_persistence@saturated-hostile-nopree...@vcs1.html * igt@gem_eio@in-flight-contexts-immediate: - shard-mtlp: [PASS][16] -> [ABORT][17] ([i915#8503]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/shard-mtlp-5/igt@gem_...@in-flight-contexts-immediate.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-mtlp-3/igt@gem_...@in-flight-contexts-immediate.html * igt@gem_exec_balancer@full: - shard-mtlp: [PASS][18] -> [FAIL][19] ([i915#6032]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/shard-mtlp-1/igt@gem_exec_balan...@full.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-mtlp-6/igt@gem_exec_balan...@full.html * igt@gem_exec_balancer@noheartbeat: - shard-dg2: NOTRUN -> [SKIP][20] ([i915#8555]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/shard-dg2-6/igt@gem_exec_balan...@noheartbeat.html * igt@gem_exec_capture@pi@vcs0: - shard-mtlp: [PASS][21] -> [FAIL][22] ([i915#4475]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/
[Intel-gfx] ✗ Fi.CI.BAT: failure for Resolve suspend-resume racing with GuC destroy-context-worker (rev2)
== Series Details == Series: Resolve suspend-resume racing with GuC destroy-context-worker (rev2) URL : https://patchwork.freedesktop.org/series/121916/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13517 -> Patchwork_121916v2 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_121916v2 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_121916v2, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121916v2/index.html Participating hosts (41 -> 40) -- Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_121916v2: ### IGT changes ### Possible regressions * igt@kms_addfb_basic@size-max: - fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/fi-kbl-soraka/igt@kms_addfb_ba...@size-max.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121916v2/fi-kbl-soraka/igt@kms_addfb_ba...@size-max.html Warnings * igt@i915_suspend@basic-s3-without-i915: - bat-adlm-1: [INCOMPLETE][3] ([i915#7443]) -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-adlm-1/igt@i915_susp...@basic-s3-without-i915.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121916v2/bat-adlm-1/igt@i915_susp...@basic-s3-without-i915.html Known issues Here are the changes found in Patchwork_121916v2 that come from known issues: ### IGT changes ### Issues hit * igt@core_auth@basic-auth: - bat-adlp-11:NOTRUN -> [ABORT][5] ([i915#8011]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121916v2/bat-adlp-11/igt@core_a...@basic-auth.html * igt@i915_selftest@live@reset: - bat-rpls-2: [PASS][6] -> [ABORT][7] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#7981] / [i915#8347]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-rpls-2/igt@i915_selftest@l...@reset.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121916v2/bat-rpls-2/igt@i915_selftest@l...@reset.html * igt@i915_selftest@live@workarounds: - bat-rpls-1: [PASS][8] -> [DMESG-FAIL][9] ([i915#6763]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-rpls-1/igt@i915_selftest@l...@workarounds.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121916v2/bat-rpls-1/igt@i915_selftest@l...@workarounds.html * igt@kms_psr@cursor_plane_move: - bat-rplp-1: NOTRUN -> [SKIP][10] ([i915#1072]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121916v2/bat-rplp-1/igt@kms_psr@cursor_plane_move.html * igt@kms_psr@sprite_plane_onoff: - bat-rplp-1: NOTRUN -> [ABORT][11] ([i915#8442] / [i915#8668] / [i915#8712]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121916v2/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html Possible fixes * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: [DMESG-FAIL][12] ([i915#7059]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121916v2/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html - bat-mtlp-6: [DMESG-FAIL][14] ([i915#7059]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121916v2/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@migrate: - bat-adlp-9: [DMESG-FAIL][16] ([i915#7699] / [i915#7913]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-adlp-9/igt@i915_selftest@l...@migrate.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121916v2/bat-adlp-9/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [DMESG-FAIL][18] ([i915#8497]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-8/igt@i915_selftest@l...@requests.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121916v2/bat-mtlp-8/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@slpc: - bat-mtlp-8: [DMESG-WARN][20] ([i915#6367]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-8/igt@i915_selftest@l...@slpc.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121916v2/bat-mtlp-8/igt@i915_selftest@l...@slpc.html - bat-rpls-1: [DMESG-WARN][22] ([i9
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Resolve suspend-resume racing with GuC destroy-context-worker (rev2)
== Series Details == Series: Resolve suspend-resume racing with GuC destroy-context-worker (rev2) URL : https://patchwork.freedesktop.org/series/121916/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Resolve suspend-resume racing with GuC destroy-context-worker (rev2)
== Series Details == Series: Resolve suspend-resume racing with GuC destroy-context-worker (rev2) URL : https://patchwork.freedesktop.org/series/121916/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
Re: [Intel-gfx] [PATCH v2 0/3] Resolve suspend-resume racing with GuC destroy-context-worker
On Mon, 2023-08-14 at 18:12 -0700, Teres Alexis, Alan Previn wrote: > This series is the result of debugging issues root caused to > races between the GuC's destroyed_worker_func being triggered > vs repeating suspend-resume cycles with concurrent delayed > fence signals for engine-freeing. alan: forgot credit: Tested-by: Mousumi Jana alan:snip. > > > Alan Previn (3): > drm/i915/guc: Flush context destruction worker at suspend > drm/i915/guc: Close deregister-context race against CT-loss > drm/i915/gt: Timeout when waiting for idle in suspending > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_gt_pm.c | 7 ++- > drivers/gpu/drm/i915/gt/intel_gt_pm.h | 7 ++- > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 45 +-- > .../gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 + > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 + > drivers/gpu/drm/i915/intel_wakeref.c | 14 -- > drivers/gpu/drm/i915/intel_wakeref.h | 5 ++- > 8 files changed, 71 insertions(+), 13 deletions(-) > > > base-commit: 85f20fb339f05ec4221bb295c13e46061c5c566f
[Intel-gfx] [PATCH v2 2/3] drm/i915/guc: Close deregister-context race against CT-loss
If we are at the end of suspend or very early in resume
its possible an async fence signal could lead us to the
execution of the context destruction worker (after the
prior worker flush).
Even if checking that the CT is enabled before calling
destroyed_worker_func, guc_lrc_desc_unpin may still fail
because in corner cases, as we traverse the GuC's
context-destroy list, the CT could get disabled in the mid
of it right before calling the GuC's CT send function.
We've witnessed this race condition once every ~6000-8000
suspend-resume cycles while ensuring workloads that render
something onscreen is continuously started just before
we suspend (and the workload is small enough to complete
and trigger the queued engine/context free-up either very
late in suspend or very early in resume).
In such a case, we need to unroll the unpin process because
guc-lrc-unpin takes a gt wakeref which only gets released in
the G2H IRQ reply that never comes through in this corner
case. That will cascade into a kernel hang later at the tail
end of suspend in this function:
intel_wakeref_wait_for_idle(>->wakeref)
(called by) - intel_gt_pm_wait_for_idle
(called by) - wait_for_suspend
Doing this unroll and keeping the context in the GuC's
destroy-list will allow the context to get picked up on
the next destroy worker invocation or purged as part of a
major GuC sanitization or reset flow.
Signed-off-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 40 +--
1 file changed, 36 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 050572bb8dbe..ddb4ee4c4e51 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -235,6 +235,13 @@ set_context_destroyed(struct intel_context *ce)
ce->guc_state.sched_state |= SCHED_STATE_DESTROYED;
}
+static inline void
+clr_context_destroyed(struct intel_context *ce)
+{
+ lockdep_assert_held(&ce->guc_state.lock);
+ ce->guc_state.sched_state &= ~SCHED_STATE_DESTROYED;
+}
+
static inline bool context_pending_disable(struct intel_context *ce)
{
return ce->guc_state.sched_state & SCHED_STATE_PENDING_DISABLE;
@@ -3175,7 +3182,7 @@ static void guc_context_close(struct intel_context *ce)
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
}
-static inline void guc_lrc_desc_unpin(struct intel_context *ce)
+static inline int guc_lrc_desc_unpin(struct intel_context *ce)
{
struct intel_guc *guc = ce_to_guc(ce);
struct intel_gt *gt = guc_to_gt(guc);
@@ -3199,10 +3206,20 @@ static inline void guc_lrc_desc_unpin(struct
intel_context *ce)
if (unlikely(disabled)) {
release_guc_id(guc, ce);
__guc_context_destroy(ce);
- return;
+ return 0;
+ }
+
+ if (deregister_context(ce, ce->guc_id.id)) {
+ /* Seal race with concurrent suspend by unrolling */
+ spin_lock_irqsave(&ce->guc_state.lock, flags);
+ set_context_registered(ce);
+ clr_context_destroyed(ce);
+ intel_gt_pm_put(gt);
+ spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+ return -ENODEV;
}
- deregister_context(ce, ce->guc_id.id);
+ return 0;
}
static void __guc_context_destroy(struct intel_context *ce)
@@ -3270,7 +3287,22 @@ static void deregister_destroyed_contexts(struct
intel_guc *guc)
if (!ce)
break;
- guc_lrc_desc_unpin(ce);
+ if (guc_lrc_desc_unpin(ce)) {
+ /*
+* This means GuC's CT link severed mid-way which could
happen
+* in suspend-resume corner cases. In this case, put the
+* context back into the destroyed_contexts list which
will
+* get picked up on the next context deregistration
event or
+* purged in a GuC sanitization event
(reset/unload/wedged/...).
+*/
+ spin_lock_irqsave(&guc->submission_state.lock, flags);
+ list_add_tail(&ce->destroyed_link,
+
&guc->submission_state.destroyed_contexts);
+ spin_unlock_irqrestore(&guc->submission_state.lock,
flags);
+ /* Bail now since the list might never be emptied if
h2gs fail */
+ break;
+ }
+
}
}
--
2.39.0
[Intel-gfx] [PATCH v2 3/3] drm/i915/gt: Timeout when waiting for idle in suspending
When suspending, add a timeout when calling
intel_gt_pm_wait_for_idle else if we have a lost
G2H event that holds a wakeref (which would be
indicative of a bug elsewhere in the driver),
driver will at least complete the suspend-resume
cycle, (albeit not hitting all the targets for
low power hw counters), instead of hanging in the kernel.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 7 ++-
drivers/gpu/drm/i915/gt/intel_gt_pm.h | 7 ++-
drivers/gpu/drm/i915/intel_wakeref.c | 14 ++
drivers/gpu/drm/i915/intel_wakeref.h | 5 +++--
5 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ee15486fed0d..090438eb8682 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -688,7 +688,7 @@ void intel_engines_release(struct intel_gt *gt)
if (!engine->release)
continue;
- intel_wakeref_wait_for_idle(&engine->wakeref);
+ intel_wakeref_wait_for_idle(&engine->wakeref, 0);
GEM_BUG_ON(intel_engine_pm_is_awake(engine));
engine->release(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 5a942af0a14e..e8b006c3ef29 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -289,6 +289,8 @@ int intel_gt_resume(struct intel_gt *gt)
static void wait_for_suspend(struct intel_gt *gt)
{
+ int timeout_ms = CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT ? : 1;
+
if (!intel_gt_pm_is_awake(gt))
return;
@@ -301,7 +303,10 @@ static void wait_for_suspend(struct intel_gt *gt)
intel_gt_retire_requests(gt);
}
- intel_gt_pm_wait_for_idle(gt);
+ /* we are suspending, so we shouldn't be waiting forever */
+ if (intel_gt_pm_wait_timeout_for_idle(gt, timeout_ms) == -ETIME)
+ gt_warn(gt, "bailing from %s after %d milisec timeout\n",
+ __func__, timeout_ms);
}
void intel_gt_suspend_prepare(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index 6c9a46452364..5358acc2b5b1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -68,7 +68,12 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt)
static inline int intel_gt_pm_wait_for_idle(struct intel_gt *gt)
{
- return intel_wakeref_wait_for_idle(>->wakeref);
+ return intel_wakeref_wait_for_idle(>->wakeref, 0);
+}
+
+static inline int intel_gt_pm_wait_timeout_for_idle(struct intel_gt *gt, int
timeout_ms)
+{
+ return intel_wakeref_wait_for_idle(>->wakeref, timeout_ms);
}
void intel_gt_pm_init_early(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/intel_wakeref.c
b/drivers/gpu/drm/i915/intel_wakeref.c
index 718f2f1b6174..383a37521415 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.c
+++ b/drivers/gpu/drm/i915/intel_wakeref.c
@@ -111,14 +111,20 @@ void __intel_wakeref_init(struct intel_wakeref *wf,
"wakeref.work", &key->work, 0);
}
-int intel_wakeref_wait_for_idle(struct intel_wakeref *wf)
+int intel_wakeref_wait_for_idle(struct intel_wakeref *wf, int timeout_ms)
{
- int err;
+ int err = 0;
might_sleep();
- err = wait_var_event_killable(&wf->wakeref,
- !intel_wakeref_is_active(wf));
+ if (!timeout_ms)
+ err = wait_var_event_killable(&wf->wakeref,
+ !intel_wakeref_is_active(wf));
+ else if (wait_var_event_timeout(&wf->wakeref,
+ !intel_wakeref_is_active(wf),
+ msecs_to_jiffies(timeout_ms)) < 1)
+ err = -ETIMEDOUT;
+
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/intel_wakeref.h
b/drivers/gpu/drm/i915/intel_wakeref.h
index ec881b097368..6fbb7a2fb6ea 100644
--- a/drivers/gpu/drm/i915/intel_wakeref.h
+++ b/drivers/gpu/drm/i915/intel_wakeref.h
@@ -251,15 +251,16 @@ __intel_wakeref_defer_park(struct intel_wakeref *wf)
/**
* intel_wakeref_wait_for_idle: Wait until the wakeref is idle
* @wf: the wakeref
+ * @timeout_ms: timeout to wait in milisecs, zero means forever
*
* Wait for the earlier asynchronous release of the wakeref. Note
* this will wait for any third party as well, so make sure you only wait
* when you have control over the wakeref and trust no one else is acquiring
* it.
*
- * Return: 0 on success, error code if killed.
+ * Return: 0 on success, error code if killed, -ETIME if timed-out.
*/
-int intel_wakeref_wait_for_idle(struct intel_wakeref *wf);
+int intel_wakeref_wait_f
[Intel-gfx] [PATCH v2 0/3] Resolve suspend-resume racing with GuC destroy-context-worker
This series is the result of debugging issues root caused to races between the GuC's destroyed_worker_func being triggered vs repeating suspend-resume cycles with concurrent delayed fence signals for engine-freeing. The reproduction steps require that an app is launched right before the start of the suspend cycle where it creates a new gem context and submits a tiny workload that would complete in the middle of the suspend cycle. However this app uses dma-buffer sharing or dma-fence with non-GPU objects or signals that eventually triggers a FENCE_FREE via__i915_sw_fence_notify that connects to engines_notify -> free_engines_rcu -> intel_context_put -> kref_put(&ce->ref..) that queues the worker after the GuCs CTB has been disabled (i.e. after i915-gem's suspend-late). This sequence is a corner-case and required repeating this app->suspend->resume cycle ~1500 times across 4 identical systems to see it once. That said, based on above callstack, it is clear that merely flushing the context destruction worker, which is obviously missing and needed, isn't sufficient. Because of that, this series adds additional patches besides the obvious (Patch #1) flushing of the worker during the suspend flows. It also includes (Patch #2) closing a race between sending the context-deregistration H2G vs the CTB getting disabled in the midst of it (by detecing the failure and unrolling the guc-lrc-unpin flow) and (Patch #32) not infinitely waiting in intel_gt_pm_wait_timeout_for_idle when in the suspend-flow. Alan Previn (3): drm/i915/guc: Flush context destruction worker at suspend drm/i915/guc: Close deregister-context race against CT-loss drm/i915/gt: Timeout when waiting for idle in suspending drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 7 ++- drivers/gpu/drm/i915/gt/intel_gt_pm.h | 7 ++- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 45 +-- .../gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 + drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 + drivers/gpu/drm/i915/intel_wakeref.c | 14 -- drivers/gpu/drm/i915/intel_wakeref.h | 5 ++- 8 files changed, 71 insertions(+), 13 deletions(-) base-commit: 85f20fb339f05ec4221bb295c13e46061c5c566f -- 2.39.0
[Intel-gfx] [PATCH v2 1/3] drm/i915/guc: Flush context destruction worker at suspend
When suspending, flush the context-guc-id
deregistration worker at the final stages of
intel_gt_suspend_late when we finally call gt_sanitize
that eventually leads down to __uc_sanitize so that
the deregistration worker doesn't fire off later as
we reset the GuC microcontroller.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 5 +
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 ++
3 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d2..050572bb8dbe 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1578,6 +1578,11 @@ static void guc_flush_submissions(struct intel_guc *guc)
spin_unlock_irqrestore(&sched_engine->lock, flags);
}
+void intel_guc_submission_flush_work(struct intel_guc *guc)
+{
+ flush_work(&guc->submission_state.destroyed_worker);
+}
+
static void guc_flush_destroyed_contexts(struct intel_guc *guc);
void intel_guc_submission_reset_prepare(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
index c57b29cdb1a6..b6df75622d3b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
@@ -38,6 +38,8 @@ int intel_guc_wait_for_pending_msg(struct intel_guc *guc,
bool interruptible,
long timeout);
+void intel_guc_submission_flush_work(struct intel_guc *guc);
+
static inline bool intel_guc_submission_is_supported(struct intel_guc *guc)
{
return guc->submission_supported;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 98b103375b7a..eb3554cb5ea4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -693,6 +693,8 @@ void intel_uc_suspend(struct intel_uc *uc)
return;
}
+ intel_guc_submission_flush_work(guc);
+
with_intel_runtime_pm(&uc_to_gt(uc)->i915->runtime_pm, wakeref) {
err = intel_guc_suspend(guc);
if (err)
--
2.39.0
Re: [Intel-gfx] [PATCH v1 1/3] drm/i915/guc: Flush context destruction worker at suspend
> > > Rodrigo: And why here and not some upper layer? like in prepare > alan: wait_for_suspend does both the checking for idle as well as the > potential > wedging if guc or hw has hung at this late state. if i call from the upper > layer before this wait_for_suspend, it might be too early because the > wait-for-idle could experience workloads completing and new > contexts-derigtrations > being queued. If i call it from upper layer after wait_for_suspend, then it > would > be unnecessary if wait_for_suspend decided to nuke everything. Hmmm.. but i > guess > the latter could work too - since the nuke case would have emptied out the > link-list > of that worker and so it would either run and do nothing or would not even be > queued. > Would you rather i go that way? (i'll recheck with my team mates for > i-dotting/t-crossing > discussion. actually, after going up a layer, i realize the right place might be to insert late stage worker-flushing into intel_uc_suspend (called from intel_gt_suspend_late) which is also where the gsc worker is flushed. This will also mean we don't need to create intel_uc_suspend_prepare for new plumbing.
[Intel-gfx] [PATCH v3 0/3] drm/i915/pxp/mtl: Update gsc-heci cmd submission
For MTL, update the GSC-HECI packet size and the max firmware response timeout to match internal fw specs. Enforce setting run-alone bit in LRC for protected contexts. Changes from prio revs: v2: - Patch #3: fix sparse warning reported by kernel test robot. v1: - N/A (Re-test) Signed-off-by: Alan Previn Alan Previn (3): drm/i915/pxp/mtl: Update pxp-firmware response timeout drm/i915/pxp/mtl: Update pxp-firmware packet size drm/i915/gt/pxp: User PXP contexts requires runalone bit in lrc drivers/gpu/drm/i915/gt/intel_lrc.c | 25 +++ .../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 3 +++ .../drm/i915/pxp/intel_pxp_cmd_interface_43.h | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h| 6 ++--- 4 files changed, 32 insertions(+), 4 deletions(-) base-commit: 85f20fb339f05ec4221bb295c13e46061c5c566f -- 2.39.0
Re: [Intel-gfx] [PATCH 1/1] drm/i915/selftests: Align igt_spinner_create_request with hangcheck
On Thu, Aug 10, 2023 at 01:36:20PM -0700, Jonathan Cavitt wrote: > Align igt_spinner_create_request with the hang_create_request > implementation in selftest_hangcheck.c. The change looks fine, but can we refactor so that there's just a single copy of the common code in igt_spinner.c? If more changes are needed for future platforms it would be better if we didn't have to remember to make the changes in multiple places. Matt > > Signed-off-by: Jonathan Cavitt > --- > drivers/gpu/drm/i915/selftests/igt_spinner.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c > b/drivers/gpu/drm/i915/selftests/igt_spinner.c > index 0f064930ef11..8c3e1f20e5a1 100644 > --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c > +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c > @@ -179,6 +179,9 @@ igt_spinner_create_request(struct igt_spinner *spin, > > *batch++ = arbitration_command; > > + memset32(batch, MI_NOOP, 128); > + batch += 128; > + > if (GRAPHICS_VER(rq->i915) >= 8) > *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1; > else if (IS_HASWELL(rq->i915)) > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
[Intel-gfx] ✓ Fi.CI.BAT: success for Reduce MTL-specific platform checks (rev4)
== Series Details == Series: Reduce MTL-specific platform checks (rev4) URL : https://patchwork.freedesktop.org/series/120943/ State : success == Summary == CI Bug Log - changes from CI_DRM_13517 -> Patchwork_120943v4 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/index.html Participating hosts (41 -> 40) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_120943v4 that come from known issues: ### IGT changes ### Issues hit * igt@core_auth@basic-auth: - bat-adlp-11:NOTRUN -> [ABORT][1] ([i915#8011]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/bat-adlp-11/igt@core_a...@basic-auth.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [PASS][2] -> [DMESG-FAIL][3] ([i915#5334] / [i915#7872]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_lrc: - bat-dg2-11: [PASS][4] -> [INCOMPLETE][5] ([i915#7609] / [i915#7913]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html * igt@kms_psr@primary_mmap_gtt: - bat-rplp-1: NOTRUN -> [SKIP][6] ([i915#1072]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html * igt@kms_setmode@basic-clone-single-crtc: - bat-rplp-1: NOTRUN -> [ABORT][7] ([i915#8260]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [DMESG-FAIL][8] ([i915#5334]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: [DMESG-FAIL][10] ([i915#7059]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html - bat-mtlp-6: [DMESG-FAIL][12] ([i915#7059]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@migrate: - bat-adlp-9: [DMESG-FAIL][14] ([i915#7699] / [i915#7913]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-adlp-9/igt@i915_selftest@l...@migrate.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/bat-adlp-9/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [DMESG-FAIL][16] ([i915#8497]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-8/igt@i915_selftest@l...@requests.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/bat-mtlp-8/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@slpc: - bat-mtlp-6: [DMESG-WARN][18] ([i915#6367]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-6/igt@i915_selftest@l...@slpc.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/bat-mtlp-6/igt@i915_selftest@l...@slpc.html - bat-mtlp-8: [DMESG-WARN][20] ([i915#6367]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-8/igt@i915_selftest@l...@slpc.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/bat-mtlp-8/igt@i915_selftest@l...@slpc.html Warnings * igt@i915_module_load@load: - bat-adlp-11:[ABORT][22] ([i915#4423]) -> [DMESG-WARN][23] ([i915#4423]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-adlp-11/igt@i915_module_l...@load.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v4/bat-adlp-11/igt@i915_module_l...@load.html * igt@kms_psr@primary_page_flip: - bat-rplp-1: [ABORT][24] ([i915#8442] / [i915#8668] / [i915#8860]) -> [SKIP][25] ([i915#1072]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-rplp-1/igt@kms_psr@primary_page_flip.html [25]: https://
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Reduce MTL-specific platform checks (rev4)
== Series Details == Series: Reduce MTL-specific platform checks (rev4) URL : https://patchwork.freedesktop.org/series/120943/ State : warning == Summary == Error: dim sparse failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Reduce MTL-specific platform checks (rev4)
== Series Details == Series: Reduce MTL-specific platform checks (rev4) URL : https://patchwork.freedesktop.org/series/120943/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Dual refresh rate fastset fixes with VRR fastset (rev3)
== Series Details ==
Series: drm/i915/display: Dual refresh rate fastset fixes with VRR fastset
(rev3)
URL : https://patchwork.freedesktop.org/series/122252/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13517 -> Patchwork_122252v3
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/index.html
Participating hosts (41 -> 39)
--
Missing(2): fi-kbl-soraka fi-snb-2520m
Known issues
Here are the changes found in Patchwork_122252v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_auth@basic-auth:
- bat-adlp-11:NOTRUN -> [ABORT][1] ([i915#8011])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/bat-adlp-11/igt@core_a...@basic-auth.html
* igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3: [PASS][2] -> [ABORT][3] ([i915#5122])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [PASS][4] -> [ABORT][5] ([i915#4983] / [i915#7461] /
[i915#8347] / [i915#8384])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-rpls-1/igt@i915_selftest@l...@reset.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-jsl-3: [PASS][6] -> [FAIL][7] ([fdo#103375])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-adlp-9: NOTRUN -> [SKIP][8] ([i915#3546]) +2 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
- bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#1845] / [i915#5354]) +3
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][10] ([i915#5334]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@migrate:
- bat-adlp-9: [DMESG-FAIL][12] ([i915#7699] / [i915#7913]) ->
[PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-adlp-9/igt@i915_selftest@l...@migrate.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/bat-adlp-9/igt@i915_selftest@l...@migrate.html
- bat-dg2-11: [DMESG-WARN][14] ([i915#7699]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@i915_selftest@live@requests:
- bat-mtlp-8: [DMESG-FAIL][16] ([i915#8497]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/bat-mtlp-8/igt@i915_selftest@l...@requests.html
Warnings
* igt@i915_module_load@load:
- bat-adlp-11:[ABORT][18] ([i915#4423]) -> [DMESG-WARN][19]
([i915#4423])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-adlp-11/igt@i915_module_l...@load.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/bat-adlp-11/igt@i915_module_l...@load.html
* igt@kms_psr@primary_page_flip:
- bat-rplp-1: [ABORT][20] ([i915#8442] / [i915#8668] / [i915#8860])
-> [ABORT][21] ([i915#8860])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-rplp-1/igt@kms_psr@primary_page_flip.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122252v3/bat-rplp-1/igt@kms_psr@primary_page_flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/486
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1982]: https://gitlab.freedesktop.org/drm/intel
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: Dual refresh rate fastset fixes with VRR fastset (rev3)
== Series Details == Series: drm/i915/display: Dual refresh rate fastset fixes with VRR fastset (rev3) URL : https://patchwork.freedesktop.org/series/122252/ State : warning == Summary == Error: dim sparse failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Dual refresh rate fastset fixes with VRR fastset (rev3)
== Series Details == Series: drm/i915/display: Dual refresh rate fastset fixes with VRR fastset (rev3) URL : https://patchwork.freedesktop.org/series/122252/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix TLB-Invalidation seqno store
== Series Details ==
Series: drm/i915: Fix TLB-Invalidation seqno store
URL : https://patchwork.freedesktop.org/series/122433/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13517 -> Patchwork_122433v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122433v1/index.html
Participating hosts (41 -> 38)
--
Missing(3): bat-mtlp-8 fi-snb-2520m bat-mtlp-6
Known issues
Here are the changes found in Patchwork_122433v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_auth@basic-auth:
- bat-adlp-11:NOTRUN -> [ABORT][1] ([i915#8011])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122433v1/bat-adlp-11/igt@core_a...@basic-auth.html
* igt@i915_selftest@live@mman:
- bat-rpls-2: [PASS][2] -> [TIMEOUT][3] ([i915#6794] / [i915#7392])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-rpls-2/igt@i915_selftest@l...@mman.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122433v1/bat-rpls-2/igt@i915_selftest@l...@mman.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: [PASS][4] -> [WARN][5] ([i915#8747])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122433v1/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#1845] / [i915#5354]) +3
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122433v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][7] ([i915#5334]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122433v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@migrate:
- bat-adlp-9: [DMESG-FAIL][9] ([i915#7699] / [i915#7913]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-adlp-9/igt@i915_selftest@l...@migrate.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122433v1/bat-adlp-9/igt@i915_selftest@l...@migrate.html
- bat-dg2-11: [DMESG-WARN][11] ([i915#7699]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122433v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html
Warnings
* igt@i915_module_load@load:
- bat-adlp-11:[ABORT][13] ([i915#4423]) -> [DMESG-WARN][14]
([i915#4423])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-adlp-11/igt@i915_module_l...@load.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122433v1/bat-adlp-11/igt@i915_module_l...@load.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/486
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8747]: https://gitlab.freedesktop.org/drm/intel/issues/8747
[i915#8879]: https://gitlab.freedesktop.org/drm/intel/issues/8879
Build changes
-
* Linux: CI_DRM_13517 -> Patchwork_122433v1
CI-20190529: 20190529
CI_DRM_13517: 85f20fb339f05ec4221bb295c13e46061c5c566f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7435: b6eaa6bfdc94c94b34ec80f437c4b6125eb19357 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_122433v1: 85f20fb339f05ec4221bb295c13e46061c5c566f @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
87acfec976af drm/i915: Fix TLB-Invalidation seqno store
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122433v1/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix TLB-Invalidation seqno store
== Series Details == Series: drm/i915: Fix TLB-Invalidation seqno store URL : https://patchwork.freedesktop.org/series/122433/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix TLB-Invalidation seqno store
== Series Details == Series: drm/i915: Fix TLB-Invalidation seqno store URL : https://patchwork.freedesktop.org/series/122433/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] [PATCH v4 7/9] drm/i915/mtl: Eliminate subplatforms
Now that we properly match the Xe_LPG IP versions associated with
various workarounds, there's no longer any need to define separate MTL
subplatform in the driver. Nothing in the code is conditional on MTL-M
or MTL-P base platforms. Furthermore, I'm not sure the "M" and "P"
designations are even an accurate representation of which specific
platforms would have which IP versions; those were mostly just
placeholders from a long time ago. The reality is that the IP version
present on a platform gets read from a fuse register at driver init; we
shouldn't be trying to guess which IP is present based on PCI ID
anymore.
Signed-off-by: Matt Roper
Reviewed-by: Nemesa Garg
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/intel_device_info.c | 14 --
drivers/gpu/drm/i915/intel_device_info.h | 4
include/drm/i915_pciids.h| 11 +++
4 files changed, 3 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b11810308e8a..6d91b3f78b5b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -575,10 +575,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
-#define IS_METEORLAKE_M(i915) \
- IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
-#define IS_METEORLAKE_P(i915) \
- IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
#define IS_DG2_G10(i915) \
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
#define IS_DG2_G11(i915) \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index ea0ec6174ce5..9dfa680a4c62 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -206,14 +206,6 @@ static const u16 subplatform_g12_ids[] = {
INTEL_DG2_G12_IDS(0),
};
-static const u16 subplatform_m_ids[] = {
- INTEL_MTL_M_IDS(0),
-};
-
-static const u16 subplatform_p_ids[] = {
- INTEL_MTL_P_IDS(0),
-};
-
static bool find_devid(u16 id, const u16 *p, unsigned int num)
{
for (; num; num--, p++) {
@@ -275,12 +267,6 @@ static void intel_device_info_subplatform_init(struct
drm_i915_private *i915)
} else if (find_devid(devid, subplatform_g12_ids,
ARRAY_SIZE(subplatform_g12_ids))) {
mask = BIT(INTEL_SUBPLATFORM_G12);
- } else if (find_devid(devid, subplatform_m_ids,
- ARRAY_SIZE(subplatform_m_ids))) {
- mask = BIT(INTEL_SUBPLATFORM_M);
- } else if (find_devid(devid, subplatform_p_ids,
- ARRAY_SIZE(subplatform_p_ids))) {
- mask = BIT(INTEL_SUBPLATFORM_P);
}
GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index dbfe6443457b..2ca54417d19b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -129,10 +129,6 @@ enum intel_platform {
#define INTEL_SUBPLATFORM_N1
#define INTEL_SUBPLATFORM_RPLU 2
-/* MTL */
-#define INTEL_SUBPLATFORM_M0
-#define INTEL_SUBPLATFORM_P1
-
enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index e1e10dfbb661..38dae757d1a8 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -738,18 +738,13 @@
#define INTEL_ATS_M_IDS(info) \
INTEL_ATS_M150_IDS(info), \
INTEL_ATS_M75_IDS(info)
+
/* MTL */
-#define INTEL_MTL_M_IDS(info) \
+#define INTEL_MTL_IDS(info) \
INTEL_VGA_DEVICE(0x7D40, info), \
- INTEL_VGA_DEVICE(0x7D60, info)
-
-#define INTEL_MTL_P_IDS(info) \
INTEL_VGA_DEVICE(0x7D45, info), \
INTEL_VGA_DEVICE(0x7D55, info), \
+ INTEL_VGA_DEVICE(0x7D60, info), \
INTEL_VGA_DEVICE(0x7DD5, info)
-#define INTEL_MTL_IDS(info) \
- INTEL_MTL_M_IDS(info), \
- INTEL_MTL_P_IDS(info)
-
#endif /* _I915_PCIIDS_H */
--
2.41.0
[Intel-gfx] [PATCH v4 9/9] drm/i915: Replace several IS_METEORLAKE with proper IP version checks
Many of the IS_METEORLAKE conditions throughout the driver are supposed
to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
specifically. Update those checks to ensure that the code will still
operate properly if/when these IP versions show up on future platforms.
v2:
- Update two more conditions (one for pg_enable, one for MTL HuC
compatibility).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c| 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 ++-
drivers/gpu/drm/i915/i915_debugfs.c| 2 +-
drivers/gpu/drm/i915/i915_perf.c | 8 +---
9 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index d24c0ce8805c..19156ba4b9ef 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user
*base, void *data)
BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
- /* Limiting the extension only to Meteor Lake */
- if (!IS_METEORLAKE(i915))
+ /* Limiting the extension only to Xe_LPG and beyond */
+ if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))
return -ENODEV;
if (copy_from_user(&ext, base, sizeof(ext)))
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index b538b5c04948..e91fc881dbf1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs
*engine)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_METEORLAKE(i915) && engine->id == GSC0) {
+ if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
intel_uncore_write(engine->gt->uncore,
RC_PSMI_CTRL_GSCCS,
_MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 2c014407225c..a2d8a271fe68 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -507,7 +507,7 @@ static unsigned int get_mocs_settings(const struct
drm_i915_private *i915,
memset(table, 0, sizeof(struct drm_i915_mocs_table));
table->unused_entries_index = I915_MOCS_PTE;
- if (IS_METEORLAKE(i915)) {
+ if (IS_GFX_GT_IP_RANGE(&i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) {
table->size = ARRAY_SIZE(mtl_mocs_table);
table->table = mtl_mocs_table;
table->n_entries = MTL_NUM_MOCS_ENTRIES;
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 748b0c695072..a5d725508c77 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
* temporary wa and should be removed after fixing real cause
* of forcewake timeouts.
*/
- if (IS_METEORLAKE(gt->i915) ||
+ if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||
IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
pg_enable =
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index fd6c22aeb670..98575d79c446 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt)
static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t
engine_mask)
{
- if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))
+ if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0))
return false;
if (!__HAS_ENGINE(engine_mask, GSC0))
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 092542f53aad..4feef874e6d6 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1161,7 +1161,7 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct
intel_rps_freq_caps *c
{
struct drm_i915_private *i915 = rps_to_i915(rps);
- if (IS_METEORLAKE(i915))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
return mtl_get_freq_caps(rps, caps);
else
return __gen6_rps_get_freq_caps(rps, caps);
diff --git a/drivers/gpu/drm/i915/
[Intel-gfx] [PATCH v4 8/9] drm/i915/display: Eliminate IS_METEORLAKE checks
Most of the IS_METEORLAKE checks in the display code shouldn't actually
be tied to MTL as a platform, but rather to the Xe_LPD+ display IP
(which is used in MTL, but may show up again in future platforms). In
cases where we're trying to match that specific IP, use a version check
against IP_VER(14, 0). For cases where we're just handling new behavior
introduced by this IP (but which may also be inherited by future IP as
well), use a ver >= 14 check.
The one exception here is the stolen memory workaround Wa_13010847436
(which is mislabelled as "Wa_22018444074" in the code). That's truly a
MTL-specific issue rather than being tied to any of the IP blocks, so
leaving the condition as IS_METEORLAKE is correct there.
v2:
- cdclk check should be >=, not >. (Gustavo)
Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 2fb030b1ff1d..b0b9a6fbb786 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1840,7 +1840,7 @@ static bool
cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
{
- return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
+ return ((IS_DG2(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14,
0)) &&
dev_priv->display.cdclk.hw.vco > 0 &&
HAS_CDCLK_SQUASH(dev_priv));
}
@@ -3559,7 +3559,7 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_METEORLAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
dev_priv->display.cdclk.table = mtl_cdclk_table;
} else if (IS_DG2(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1b00ef2c6185..a42b3c4c0ed7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -31,7 +31,7 @@
bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
{
- if (IS_METEORLAKE(i915) && (phy < PHY_C))
+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && phy < PHY_C)
return true;
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 763ab569d8f3..462917787361 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1767,7 +1767,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv,
enum phy phy)
if (IS_DG2(dev_priv))
/* DG2's "TC1" output uses a SNPS PHY */
return false;
- else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
+ else if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER_FULL(dev_priv) ==
IP_VER(14, 0))
return phy >= PHY_F && phy <= PHY_I;
else if (IS_TIGERLAKE(dev_priv))
return phy >= PHY_D && phy <= PHY_I;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 5f479f3828bb..1623c0c5e8a1 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -998,7 +998,7 @@ void intel_dmc_init(struct drm_i915_private *i915)
INIT_WORK(&dmc->work, dmc_load_work_fn);
- if (IS_METEORLAKE(i915)) {
+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
dmc->fw_path = MTL_DMC_PATH;
dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
} else if (IS_DG2(i915)) {
--
2.41.0
[Intel-gfx] [PATCH v4 4/9] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
of these workarounds are actually tied to MTL as a platform; they only
relate to the Xe_LPG graphics IP, regardless of what platform it appears
in. At the moment MTL is the only platform that uses Xe_LPG with IP
versions 12.70 and 12.71, but we can't count on this being true in the
future. Switch these to use a new IS_GFX_GT_IP_STEP() macro instead
that is purely based on IP version. IS_GFX_GT_IP_STEP() is also
GT-based rather than device-based, which will help prevent mistakes
where we accidentally try to apply Xe_LPG graphics workarounds to the
Xe_LPM+ media GT and vice-versa.
v2:
- Switch to a more generic and shorter IS_GT_IP_STEP macro that can be
used for both graphics and media IP (and any other kind of GTs that
show up in the future).
v3:
- Switch back to long-form IS_GFX_GT_IP_STEP macro. (Jani)
- Move macro to intel_gt.h. (Andi)
v4:
- Build IS_GFX_GT_IP_STEP on top of IS_GFX_GT_IP_RANGE and
IS_GRAPHICS_STEP building blocks and name the parameters from/until
rather than begin/fixed. (Jani)
- Fix usage examples in comment.
Cc: Gustavo Sousa
Cc: Tvrtko Ursulin
Cc: Andi Shyti
Cc: Jani Nikula
Signed-off-by: Matt Roper
---
.../drm/i915/display/skl_universal_plane.c| 5 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 11 ++--
drivers/gpu/drm/i915/gt/intel_gt.h| 17 ++
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 7 ++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 52 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 --
10 files changed, 61 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ffc15d278a39..d557ecd4e1eb 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -20,6 +20,7 @@
#include "skl_scaler.h"
#include "skl_universal_plane.h"
#include "skl_watermark.h"
+#include "gt/intel_gt.h"
#include "pxp/intel_pxp.h"
static const u32 skl_plane_formats[] = {
@@ -2169,8 +2170,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private
*i915,
enum pipe pipe, enum plane_id plane_id)
{
/* Wa_14017240301 */
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ if (IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
return false;
/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index a4ff55aa5e55..6187b25b67ab 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -4,9 +4,9 @@
*/
#include "gen8_engine_cs.h"
-#include "i915_drv.h"
#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
+#include "intel_gt.h"
#include "intel_lrc.h"
#include "intel_ring.h"
@@ -226,8 +226,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs
*engine, u32 *cs)
static int mtl_dummy_pipe_control(struct i915_request *rq)
{
/* Wa_14016712196 */
- if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
+ if (IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0)
||
+ IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0,
STEP_B0)) {
u32 *cs;
/* dummy PIPE_CONTROL + depth flush */
@@ -799,6 +799,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request
*rq, u32 *cs)
u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{
struct drm_i915_private *i915 = rq->i915;
+ struct intel_gt *gt = rq->engine->gt;
u32 flags = (PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TLB_INVALIDATE |
PIPE_CONTROL_TILE_CACHE_FLUSH |
@@ -809,8 +810,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request
*rq, u32 *cs)
PIPE_CONTROL_FLUSH_ENABLE);
/* Wa_14016712196 */
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
/* dummy PIPE_CONTROL + depth flush */
cs = gen12_emit_pipe_control(cs, 0,
PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i
[Intel-gfx] [PATCH v4 2/9] drm/i915/xelpmp: Don't assume workarounds extend to future platforms
The currently implemented Xe_LPM+ workarounds are specific to media
version 13.00. When new IP versions show up in the future, they'll need
their own workaround lists.
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3ae0dbd39eaa..3108ad1d6207 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1818,10 +1818,10 @@ gt_init_workarounds(struct intel_gt *gt, struct
i915_wa_list *wal)
gt_tuning_settings(gt, wal);
if (gt->type == GT_MEDIA) {
- if (MEDIA_VER(i915) >= 13)
+ if (MEDIA_VER_FULL(i915) == IP_VER(13, 0))
xelpmp_gt_workarounds_init(gt, wal);
else
- MISSING_CASE(MEDIA_VER(i915));
+ MISSING_CASE(MEDIA_VER_FULL(i915));
return;
}
--
2.41.0
[Intel-gfx] [PATCH v4 1/9] drm/i915: Consolidate condition for Wa_22011802037
The workaround bounds for Wa_22011802037 are somewhat complex and are
replicated in several places throughout the code. Pull the condition
out to a helper function to prevent mistakes if this condition needs to
change again in the future.
Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +---
.../drm/i915/gt/intel_execlists_submission.c | 4 +---
drivers/gpu/drm/i915/gt/intel_reset.c | 18 ++
drivers/gpu/drm/i915/gt/intel_reset.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +---
6 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ee15486fed0d..dfb69fc977a0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1617,9 +1617,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs
*engine,
* Wa_22011802037: Prior to doing a reset, ensure CS is
* stopped, set ring stop bit and prefetch disable bit to halt CS
*/
- if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
- (GRAPHICS_VER(engine->i915) >= 11 &&
- GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
+ if (intel_engine_reset_needs_wa_22011802037(engine->gt))
intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 8a641bcf777c..4d05321dc5b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3001,9 +3001,7 @@ static void execlists_reset_prepare(struct
intel_engine_cs *engine)
* Wa_22011802037: In addition to stopping the cs, we need
* to wait for any pending mi force wakeups
*/
- if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
- (GRAPHICS_VER(engine->i915) >= 11 &&
- GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
+ if (intel_engine_reset_needs_wa_22011802037(engine->gt))
intel_engine_wait_for_pending_mi_fw(engine);
engine->execlists.reset_ccid = active_ccid(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index cc6bd21a3e51..1ff7b42521c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1632,6 +1632,24 @@ void __intel_fini_wedge(struct intel_wedge_me *w)
w->gt = NULL;
}
+/*
+ * Wa_22011802037 requires that we (or the GuC) ensure that no command
+ * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.
+ */
+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
+{
+ if (GRAPHICS_VER(gt->i915) < 11)
+ return false;
+
+ if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
+ return true;
+
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
+ return false;
+
+ return true;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_reset.c"
#include "selftest_hangcheck.c"
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h
b/drivers/gpu/drm/i915/gt/intel_reset.h
index 25c975b6e8fc..f615b30b81c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -78,4 +78,6 @@ void __intel_fini_wedge(struct intel_wedge_me *w);
bool intel_has_gpu_reset(const struct intel_gt *gt);
bool intel_has_reset_engine(const struct intel_gt *gt);
+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt);
+
#endif /* I915_RESET_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 569b5fe94c41..22649831d3bd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -292,9 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
flags |= GUC_WA_DUAL_QUEUE;
/* Wa_22011802037: graphics version 11/12 */
- if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
- (GRAPHICS_VER(gt->i915) >= 11 &&
- GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
+ if (intel_engine_reset_needs_wa_22011802037(gt))
flags |= GUC_WA_PRE_PARSER;
/* Wa_16011777198:dg2 */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d2..1bd5d8f7c40b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1658,9 +1658,7 @@ static void guc_engine_reset_prepare(struct
intel_engine_cs *engine)
* Wa_220118
[Intel-gfx] [PATCH v4 0/9] Reduce MTL-specific platform checks
Starting with MTL, the hardware moved to a disaggregated IP design where graphics, media, and display are supposed to be treated independently of the base platform that they're incorporated into. For driver logic that is conditional on these IPs, the code should be checking the IP versions (as read from the GMD_ID registers) rather than trying to match on a specific platform (e.g., MTL). It's possible that these IPs could show up again, without changes, on future non-MTL platforms, or that the current MTL platform could be extended to include new IP versions in future SKUs or refreshes; making sure our driver's conditions are handled appropriately future-proofs for both of these cases. Going forward, conditions like IS_METEORLAKE should be very rare in the driver; in most places our logic will be conditional upon the IP rather than the base platform. v2: - Rework macros slightly; new IP range and stepping range macros can be used with both GFX or MEDIA rather than needing separate macros for each IP. (Tvrtko, Gustavo) - Fix a > that should have been a >=. (Gustavo) - Split non-inheritance of media workarounds by future platforms into its own patch. (Gustavo) - Extra documentation comments v3: - Switch back to separate long-form gfx and media macros with no macro pasting. (Jani) - Move GT-specific macros from intel_drv.h to intel_gt.h. (Andi) - Replace two more IS_METEORLAKE() conditions with IP version checks. v4: - Build IS_*_IP_STEP macros on top of existing range check and stepping check building blocks. (Jani) - Fix parameters in comment examples. Cc: Tvrtko Ursulin Cc: Dnyaneshwar Bhadane Cc: Gustavo Sousa Cc: Jani Nikula Cc: Andi Shyti Matt Roper (9): drm/i915: Consolidate condition for Wa_22011802037 drm/i915/xelpmp: Don't assume workarounds extend to future platforms drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version drm/i915: Eliminate IS_MTL_GRAPHICS_STEP drm/i915: Eliminate IS_MTL_MEDIA_STEP drm/i915: Eliminate IS_MTL_DISPLAY_STEP drm/i915/mtl: Eliminate subplatforms drm/i915/display: Eliminate IS_METEORLAKE checks drm/i915: Replace several IS_METEORLAKE with proper IP version checks drivers/gpu/drm/i915/display/intel_cdclk.c| 4 +- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_device.h | 22 + drivers/gpu/drm/i915/display/intel_dmc.c | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 3 +- drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 10 +- .../drm/i915/display/skl_universal_plane.c| 5 +- drivers/gpu/drm/i915/gem/i915_gem_create.c| 4 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 11 ++- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +- .../drm/i915/gt/intel_execlists_submission.c | 4 +- drivers/gpu/drm/i915/gt/intel_gt.h| 58 drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 7 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +- drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +- drivers/gpu/drm/i915/gt/intel_reset.c | 20 +++- drivers/gpu/drm/i915/gt/intel_reset.h | 2 + drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 92 ++- drivers/gpu/drm/i915/gt/uc/intel_guc.c| 6 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 +- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 18 +--- drivers/gpu/drm/i915/i915_perf.c | 23 ++--- drivers/gpu/drm/i915/intel_device_info.c | 14 --- drivers/gpu/drm/i915/intel_device_info.h | 4 - include/drm/i915_pciids.h | 11 +-- 32 files changed, 206 insertions(+), 150 deletions(-) -- 2.41.0
[Intel-gfx] [PATCH v4 6/9] drm/i915: Eliminate IS_MTL_DISPLAY_STEP
Stepping-specific display behavior shouldn't be tied to MTL as a
platform, but rather specifically to the Xe_LPD+ IP. Future non-MTL
platforms may re-use this IP and will need to follow the exact same
logic and apply the same workarounds. IS_MTL_DISPLAY_STEP() is dropped
in favor of a new macro IS_DISPLAY_IP_STEP() that only checks the
display IP version.
v2:
- Rename macro to IS_DISPLAY_IP_STEP for consistency with the
corresponding GT macro and handle steppings the same way.
v3:
- Drop the automatic "STEP_" pasting.
v4:
- Implement IS_DISPLAY_IP_STEP on top of IS_DISPLAY_IP_RANGE /
IS_DISPLAY_STEP building blocks and make the parameters from/until
instead of begin/fixed. (Jani)
- Fix usage details in comment.
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_device.h | 22 +++
drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 10 -
drivers/gpu/drm/i915/i915_drv.h | 6 ++---
5 files changed, 32 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
index 215e682bd8b7..7aeff1a5204b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -71,6 +71,28 @@ struct drm_printer;
#define OVERLAY_NEEDS_PHYSICAL(i915)
(DISPLAY_INFO(i915)->overlay_needs_physical)
#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
+/* Check that device has a display IP version within the specific range. */
+#define IS_DISPLAY_IP_RANGE(__i915, from, until) ( \
+ BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
+ (DISPLAY_VER_FULL(__i915) >= (from) && \
+DISPLAY_VER_FULL(__i915) <= (until)))
+
+/*
+ * Check if a device has a specific IP version as well as a stepping within
+ * the specified range [begin, fixed). The lower bound is inclusive, the upper
+ * bound is exclusive (corresponding to the first hardware stepping when the
+ * workaround is no longer needed). E.g.,
+ *
+ *IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
+ *IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
+ *
+ * "STEP_FOREVER" can be passed as the upper stepping bound for workarounds
that
+ * have no upper bound on steppings of the specified IP version.
+ */
+#define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \
+ (IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \
+IS_DISPLAY_STEP((__i915), (from), (until)))
+
struct intel_display_runtime_info {
struct {
u16 ver;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 25382022cd27..1c6d467cec26 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -50,6 +50,7 @@
#include "i915_vma.h"
#include "intel_cdclk.h"
#include "intel_de.h"
+#include "intel_display_device.h"
#include "intel_display_trace.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
@@ -1100,7 +1101,7 @@ static int intel_fbc_check_plane(struct
intel_atomic_state *state,
/* Wa_14016291713 */
if ((IS_DISPLAY_VER(i915, 12, 13) ||
-IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
crtc_state->has_psr) {
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..744e332fa2af 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
&pmdemand_state->base,
&intel_pmdemand_funcs);
- if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+ if (IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))
/* Wa_14016740474 */
intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
DMD_RSP_TIMEOUT_DISABLE);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 97d5eef10130..72887c29fb51 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1360,7 +1360,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
bool set_wa_bit = false;
/* Wa_14015648006 */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+ if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
IS_DISPLAY_VER(dev_priv, 11, 13))
set_wa_bit |= crtc_state->wm_level_disabled;
@@ -1447,7 +1447,7 @@ static void intel_psr_enable_source(stru
[Intel-gfx] [PATCH v4 5/9] drm/i915: Eliminate IS_MTL_MEDIA_STEP
Stepping-specific media behavior shouldn't be tied to MTL as a platform,
but rather specifically to the Xe_LPM+ IP. Future non-MTL platforms may
re-use this IP and will need to follow the exact same logic and apply
the same workarounds. IS_MTL_MEDIA_STEP() is dropped in favor of
IS_MEDIA_GT_IP_STEP, which checks the media IP version associated with a
specific IP and also ensures that we're operating on the media GT, not
the primary GT.
v2:
- Switch to the IS_GT_IP_STEP macro.
v3:
- Switch back to long-form IS_MEDIA_GT_IP_STEP. (Jani)
v4:
- Build IS_MEDIA_GT_IP_STEP on top of IS_MEDIA_GT_IP_RANGE and
IS_MEDIA_STEP building blocks and name the parameters from/until
rather than begin/fixed.. (Jani)
Cc: Jani Nikula
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.h | 30 +
drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +--
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/i915_perf.c| 15 ---
4 files changed, 35 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 636fd651b8b2..abe9fe4a3bd9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -25,6 +25,20 @@ struct drm_printer;
GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
GRAPHICS_VER_FULL((gt)->i915) <= (until)))
+/*
+ * Check that the GT is a media GT and has an IP version within the
+ * specified range (inclusive).
+ *
+ * Only usable on platforms with a standalone media design (i.e., IP version 13
+ * and higher).
+ */
+#define IS_MEDIA_GT_IP_RANGE(gt, from, until) ( \
+ BUILD_BUG_ON_ZERO((from) < IP_VER(13, 0)) + \
+ BUILD_BUG_ON_ZERO((until) < (from)) + \
+ ((gt)->type == GT_MEDIA && \
+MEDIA_VER_FULL((gt)->i915) >= (from) && \
+MEDIA_VER_FULL((gt)->i915) <= (until)))
+
/*
* Check that the GT is a graphics GT with a specific IP version and has
* a stepping in the range [begin, fixed). The lower stepping bound is
@@ -42,6 +56,22 @@ struct drm_printer;
(IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \
IS_GRAPHICS_STEP((gt)->i915, (from), (until
+/*
+ * Check that the GT is a media GT with a specific IP version and has
+ * a stepping in the range [begin, fixed). The lower stepping bound is
+ * inclusive, the upper bound is exclusive (corresponding to the first hardware
+ * stepping at which the workaround is no longer needed).
+ * "STEP_FOREVER" can be passed as the upper stepping bound for workarounds
+ * that have no "fixed" version for the specified IP version.
+ *
+ * This macro may only be used to match on platforms that have a standalone
+ * media design (i.e., media version 13 or higher).
+ */
+#define IS_MEDIA_GT_IP_STEP(gt, ipver, from, until) ( \
+ BUILD_BUG_ON_ZERO((until) <= (from)) + \
+ (IS_MEDIA_GT_IP_RANGE((gt), (ipver), (ipver)) && \
+IS_MEDIA_STEP((gt)->i915, (from), (until
+
#define GT_TRACE(gt, fmt, ...) do {\
const struct intel_gt *gt__ __maybe_unused = (gt); \
GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 58bb1c55294c..748b0c695072 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -526,8 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
return false;
}
- if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
- gt->type == GT_MEDIA) {
+ if (IS_MEDIA_GT_IP_STEP(gt, IP_VER(13, 0), STEP_A0, STEP_B0)) {
drm_notice(&i915->drm,
"Media RC6 disabled on A step\n");
return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e0e0493d6c1f..42a86483c694 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -662,10 +662,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_METEORLAKE(__i915) && \
IS_DISPLAY_STEP(__i915, since, until))
-#define IS_MTL_MEDIA_STEP(__i915, since, until) \
- (IS_METEORLAKE(__i915) && \
-IS_MEDIA_STEP(__i915, since, until))
-
/*
* DG2 hardware steppings are a bit unusual. The hardware design was forked to
* create three variants (G10, G11, and G12) which each have distinct
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 04bc1f4a1115..2ef8addb0cfd 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4223,7 +4223,7 @@ static int read_properties_unlocked(struct i915_perf
*perf,
* C6 disable in BIOS. Fail if Media C6 is enabled on steppings where
OAM
* does not work as expected.
*/
- if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
+ if (IS_MEDIA_GT_
[Intel-gfx] [PATCH v4 3/9] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version
Although some of our Xe_LPG workarounds were already being applied based
on IP version correctly, others were matching on MTL as a base platform,
which is incorrect. Although MTL is the only platform right now that
uses Xe_LPG IP, this may not always be the case. If a future platform
re-uses this graphics IP, the same workarounds should be applied, even
if it isn't a "MTL" platform.
We were also incorrectly applying Xe_LPG workarounds/tuning to the
Xe_LPM+ media IP in one or two places; we should make sure that we don't
try to apply graphics workarounds to the media GT and vice versa where
they don't belong. A new helper macro IS_GT_IP_RANGE() is added to help
ensure this is handled properly -- it checks that the GT matches the IP
type being tested as well as the IP version falling in the proper range.
Note that many of the stepping-based workarounds are still incorrectly
checking for a MTL base platform; that will be remedied in a later
patch.
v2:
- Rework macro into a slightly more generic IS_GT_IP_RANGE() that can
be used for either GFX or MEDIA checks.
v3:
- Switch back to separate macros for gfx and media. (Jani)
- Move macro to intel_gt.h. (Andi)
Cc: Gustavo Sousa
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Andi Shyti
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.h | 11 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++--
2 files changed, 31 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 6c34547b58b5..15c25980411d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -14,6 +14,17 @@
struct drm_i915_private;
struct drm_printer;
+/*
+ * Check that the GT is a graphics GT and has an IP version within the
+ * specified range (inclusive).
+ */
+#define IS_GFX_GT_IP_RANGE(gt, from, until) ( \
+ BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
+ BUILD_BUG_ON_ZERO((until) < (from)) + \
+ ((gt)->type != GT_MEDIA && \
+GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
+GRAPHICS_VER_FULL((gt)->i915) <= (until)))
+
#define GT_TRACE(gt, fmt, ...) do {\
const struct intel_gt *gt__ __maybe_unused = (gt); \
GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3108ad1d6207..80d67e487b55 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -805,8 +805,8 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs
*engine,
wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
}
-static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
- struct i915_wa_list *wal)
+static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
+struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
@@ -817,12 +817,12 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs
*engine,
wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
}
-static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
-struct i915_wa_list *wal)
+static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- mtl_ctx_gt_tuning_init(engine, wal);
+ xelpg_ctx_gt_tuning_init(engine, wal);
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
@@ -931,8 +931,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
if (engine->class != RENDER_CLASS)
goto done;
- if (IS_METEORLAKE(i915))
- mtl_ctx_workarounds_init(engine, wal);
+ if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
+ xelpg_ctx_workarounds_init(engine, wal);
else if (IS_PONTEVECCHIO(i915))
; /* noop; none at this time */
else if (IS_DG2(i915))
@@ -1791,10 +1791,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
*/
static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
{
- if (IS_METEORLAKE(gt->i915)) {
- if (gt->type != GT_MEDIA)
- wa_mcr_write_or(wal, XEHP_L3SCQREG7,
BLEND_FILL_CACHING_OPT_DIS);
-
+ if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
+ wa_mcr_write_or(wal, XEHP_L3SCQREG7,
BLEND_FILL_CACHING_OPT_DIS);
wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
}
@@ -1826,7 +1824,7 @@ gt_init_workarounds(struct intel_gt *gt, struct
i915_wa_list *wal
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Remove Wa_15010599737
== Series Details == Series: drm/i915/dg2: Remove Wa_15010599737 URL : https://patchwork.freedesktop.org/series/122426/ State : success == Summary == CI Bug Log - changes from CI_DRM_13516_full -> Patchwork_122426v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_122426v1_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@blit-reloc-purge-cache: - shard-dg2: NOTRUN -> [SKIP][1] ([i915#8411]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-dg2-2/igt@api_intel...@blit-reloc-purge-cache.html * igt@api_intel_bb@render-ccs: - shard-dg2: NOTRUN -> [FAIL][2] ([i915#6122]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-dg2-2/igt@api_intel...@render-ccs.html * igt@debugfs_test@basic-hwmon: - shard-mtlp: NOTRUN -> [SKIP][3] ([i915#7456]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-mtlp-5/igt@debugfs_t...@basic-hwmon.html * igt@device_reset@cold-reset-bound: - shard-dg2: NOTRUN -> [SKIP][4] ([i915#7701]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-dg2-11/igt@device_re...@cold-reset-bound.html * igt@device_reset@unbind-reset-rebind: - shard-dg1: NOTRUN -> [ABORT][5] ([i915#4983] / [i915#7461]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-dg1-17/igt@device_re...@unbind-reset-rebind.html * igt@drm_fdinfo@busy-idle-check-all@vcs1: - shard-dg1: NOTRUN -> [SKIP][6] ([i915#8414]) +5 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-dg1-19/igt@drm_fdinfo@busy-idle-check-...@vcs1.html * igt@drm_fdinfo@virtual-busy-all: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#8414]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-dg2-2/igt@drm_fdi...@virtual-busy-all.html * igt@feature_discovery@display-4x: - shard-dg2: NOTRUN -> [SKIP][8] ([i915#1839]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-dg2-11/igt@feature_discov...@display-4x.html - shard-dg1: NOTRUN -> [SKIP][9] ([i915#1839]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-dg1-17/igt@feature_discov...@display-4x.html * igt@gem_basic@multigpu-create-close: - shard-dg2: NOTRUN -> [SKIP][10] ([i915#7697]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-dg2-2/igt@gem_ba...@multigpu-create-close.html * igt@gem_ccs@block-copy-compressed: - shard-dg1: NOTRUN -> [SKIP][11] ([i915#3555] / [i915#5325]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-dg1-19/igt@gem_...@block-copy-compressed.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-snb: NOTRUN -> [DMESG-WARN][12] ([i915#8841]) +9 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-snb5/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_sseu@invalid-args: - shard-dg2: NOTRUN -> [SKIP][14] ([i915#280]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-dg2-2/igt@gem_ctx_s...@invalid-args.html * igt@gem_exec_balancer@bonded-sync: - shard-dg1: NOTRUN -> [SKIP][15] ([i915#4771]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-dg1-19/igt@gem_exec_balan...@bonded-sync.html * igt@gem_exec_balancer@noheartbeat: - shard-dg2: NOTRUN -> [SKIP][16] ([i915#8555]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-dg2-2/igt@gem_exec_balan...@noheartbeat.html * igt@gem_exec_endless@dispatch@rcs0: - shard-tglu: [PASS][17] -> [TIMEOUT][18] ([i915#3778] / [i915#7392] / [i915#7921]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-tglu-8/igt@gem_exec_endless@dispa...@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-tglu-7/igt@gem_exec_endless@dispa...@rcs0.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#2846]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-glk3/igt@gem_exec_f...@basic-deadline.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/shard-glk2/igt@gem_exec_f...@basic-deadline.ht
Re: [Intel-gfx] [PATCH v1] drm/i915: Fix TLB-Invalidation seqno store
Hi Alan,
On Mon, Aug 14, 2023 at 11:24:49AM -0700, Alan Previn wrote:
> When getting the next gt's seqno to be stored into an
> objects mm.tlb[gt_id] array, fix the retrieval code
> to get it from the correct gt instead of the same one.
>
> Fixes: d6c531ab4820 ("drm/i915: Invalidate the TLBs on each GT")
> Signed-off-by: Alan Previn
> ---
> drivers/gpu/drm/i915/i915_vma.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index e52089564d79..6f180ee13853 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -1356,7 +1356,7 @@ void vma_invalidate_tlb(struct i915_address_space *vm,
> u32 *tlb)
>*/
> for_each_gt(gt, vm->i915, id)
> WRITE_ONCE(tlb[id],
> -intel_gt_next_invalidate_tlb_full(vm->gt));
> +intel_gt_next_invalidate_tlb_full(gt));
ops!
Reviewed-by: Andi Shyti
Thank you!
Andi
[Intel-gfx] [PATCH v3] drm/i915/display: Dual refresh rate fastset fixes with VRR fastset
Dual refresh rate (DRR) fastset seamlessly lets refresh rate
throttle without needing a full modeset.
However with the recent VRR fastset patches that got merged this
logic was broken. This is broken because now with VRR fastset
VRR parameters are calculated by default at the nominal refresh rate say 120Hz.
Now when DRR throttle happens to switch refresh rate to 60Hz, crtc clock
changes and this throws a mismatch in VRR parameters and fastset logic
for DRR gets thrown off and full modeset is indicated.
This patch fixes this by ignoring the pipe mismatch for VRR parameters
in the case of DRR and when VRR is not enabled. With this fix, DRR
will still throttle seamlessly as long as VRR is not enabled.
This will still need a full modeset for both DRR and VRR operating together
during the refresh rate throttle and then enabling VRR since now VRR
parameters need to be recomputed with new crtc clock and written to HW.
This DRR + VRR fastset in conjunction needs more work in the driver and
will be fixed in later patches.
v3:
Compute new VRR params whenever there is fastset and its non DRRS.
This will ensure it computes while switching to a fixed RR (Mitul)
v2:
Check for pipe config mismatch in crtc clock whenever VRR is enabled
Cc: Drew Davenport
Cc: Ville Syrjälä
Cc: Sean Paul
Cc: Mitul Golani
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 763ab569d8f3..2cf3b22adaf7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5352,7 +5352,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
- if (!fastset || !pipe_config->seamless_m_n) {
+ if (!fastset || !pipe_config->seamless_m_n || pipe_config->vrr.enable) {
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
}
@@ -5387,11 +5387,13 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
if (!fastset)
PIPE_CONF_CHECK_BOOL(vrr.enable);
- PIPE_CONF_CHECK_I(vrr.vmin);
- PIPE_CONF_CHECK_I(vrr.vmax);
- PIPE_CONF_CHECK_I(vrr.flipline);
- PIPE_CONF_CHECK_I(vrr.pipeline_full);
- PIPE_CONF_CHECK_I(vrr.guardband);
+ if ((fastset && !pipe_config->seamless_m_n) || pipe_config->vrr.enable)
{
+ PIPE_CONF_CHECK_I(vrr.vmin);
+ PIPE_CONF_CHECK_I(vrr.vmax);
+ PIPE_CONF_CHECK_I(vrr.flipline);
+ PIPE_CONF_CHECK_I(vrr.pipeline_full);
+ PIPE_CONF_CHECK_I(vrr.guardband);
+ }
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
--
2.41.0.694.ge786442a9b-goog
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI (rev3)
== Series Details == Series: drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI (rev3) URL : https://patchwork.freedesktop.org/series/122108/ State : success == Summary == CI Bug Log - changes from CI_DRM_13516_full -> Patchwork_122108v3_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_122108v3_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@blit-reloc-purge-cache: - shard-dg2: NOTRUN -> [SKIP][1] ([i915#8411]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-dg2-12/igt@api_intel...@blit-reloc-purge-cache.html * igt@api_intel_bb@render-ccs: - shard-dg2: NOTRUN -> [FAIL][2] ([i915#6122]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-dg2-6/igt@api_intel...@render-ccs.html * igt@device_reset@cold-reset-bound: - shard-dg2: NOTRUN -> [SKIP][3] ([i915#7701]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-dg2-2/igt@device_re...@cold-reset-bound.html * igt@device_reset@unbind-reset-rebind: - shard-dg1: NOTRUN -> [ABORT][4] ([i915#4983] / [i915#7461]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-dg1-18/igt@device_re...@unbind-reset-rebind.html * igt@drm_fdinfo@busy-idle-check-all@vcs1: - shard-dg1: NOTRUN -> [SKIP][5] ([i915#8414]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-dg1-15/igt@drm_fdinfo@busy-idle-check-...@vcs1.html * igt@drm_fdinfo@virtual-busy-all: - shard-dg2: NOTRUN -> [SKIP][6] ([i915#8414]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-dg2-12/igt@drm_fdi...@virtual-busy-all.html * igt@feature_discovery@display-4x: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#1839]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-dg2-11/igt@feature_discov...@display-4x.html - shard-dg1: NOTRUN -> [SKIP][8] ([i915#1839]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-dg1-18/igt@feature_discov...@display-4x.html * igt@gem_basic@multigpu-create-close: - shard-dg2: NOTRUN -> [SKIP][9] ([i915#7697]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-dg2-6/igt@gem_ba...@multigpu-create-close.html * igt@gem_ccs@block-copy-compressed: - shard-dg1: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#5325]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-dg1-15/igt@gem_...@block-copy-compressed.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglu: [PASS][11] -> [FAIL][12] ([i915#6268]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-tglu-3/igt@gem_ctx_e...@basic-nohangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-tglu-10/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_ctx_freq@sysfs@gt0: - shard-mtlp: [PASS][13] -> [FAIL][14] ([i915#6786]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-mtlp-3/igt@gem_ctx_freq@sy...@gt0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-mtlp-7/igt@gem_ctx_freq@sy...@gt0.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-snb: NOTRUN -> [DMESG-WARN][15] ([i915#8841]) +7 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-snb4/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1099]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-snb4/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_ctx_sseu@invalid-args: - shard-dg2: NOTRUN -> [SKIP][17] ([i915#280]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-dg2-12/igt@gem_ctx_s...@invalid-args.html * igt@gem_eio@hibernate: - shard-tglu: [PASS][18] -> [ABORT][19] ([i915#7975] / [i915#8213] / [i915#8398]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-tglu-3/igt@gem_...@hibernate.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-tglu-10/igt@gem_...@hibernate.html * igt@gem_exec_balancer@bonded-sync: - shard-dg1: NOTRUN -> [SKIP][20] ([i915#4771]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/shard-dg1-15/igt@gem_exec_balan...@bonded-sync.html * igt@gem_exec_balancer@noheartbeat: - shard-dg2: NOTRUN -> [SKIP][21] ([i915#8555]) +1 similar issue
[Intel-gfx] [PATCH v1] drm/i915: Fix TLB-Invalidation seqno store
When getting the next gt's seqno to be stored into an
objects mm.tlb[gt_id] array, fix the retrieval code
to get it from the correct gt instead of the same one.
Fixes: d6c531ab4820 ("drm/i915: Invalidate the TLBs on each GT")
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/i915_vma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index e52089564d79..6f180ee13853 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1356,7 +1356,7 @@ void vma_invalidate_tlb(struct i915_address_space *vm,
u32 *tlb)
*/
for_each_gt(gt, vm->i915, id)
WRITE_ONCE(tlb[id],
- intel_gt_next_invalidate_tlb_full(vm->gt));
+ intel_gt_next_invalidate_tlb_full(gt));
}
static void __vma_put_pages(struct i915_vma *vma, unsigned int count)
base-commit: 85f20fb339f05ec4221bb295c13e46061c5c566f
--
2.39.0
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: add lock while printing frontbuffer tracking bits to debugfs
== Series Details ==
Series: drm/i915/display: add lock while printing frontbuffer tracking bits to
debugfs
URL : https://patchwork.freedesktop.org/series/122429/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13517 -> Patchwork_122429v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122429v1/index.html
Participating hosts (41 -> 40)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_122429v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@core_auth@basic-auth:
- bat-adlp-11:NOTRUN -> [ABORT][1] ([i915#8011])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122429v1/bat-adlp-11/igt@core_a...@basic-auth.html
* igt@i915_selftest@live@requests:
- bat-mtlp-6: [PASS][2] -> [ABORT][3] ([i915#7982])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-6/igt@i915_selftest@l...@requests.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122429v1/bat-mtlp-6/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [PASS][4] -> [ABORT][5] ([i915#4983] / [i915#7461] /
[i915#8347] / [i915#8384])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-rpls-1/igt@i915_selftest@l...@reset.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122429v1/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: [PASS][6] -> [DMESG-WARN][7] ([i915#6367])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-rpls-2/igt@i915_selftest@l...@slpc.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122429v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#1845] / [i915#5354]) +3
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122429v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][9] -> [ABORT][10] ([i915#8442] / [i915#8668])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122429v1/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html
Possible fixes
* igt@i915_selftest@live@gt_mocs:
- bat-mtlp-8: [DMESG-FAIL][11] ([i915#7059]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122429v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@migrate:
- bat-adlp-9: [DMESG-FAIL][13] ([i915#7699] / [i915#7913]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-adlp-9/igt@i915_selftest@l...@migrate.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122429v1/bat-adlp-9/igt@i915_selftest@l...@migrate.html
- bat-dg2-11: [DMESG-WARN][15] ([i915#7699]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-dg2-11/igt@i915_selftest@l...@migrate.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122429v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html
* igt@i915_selftest@live@requests:
- bat-mtlp-8: [DMESG-FAIL][17] ([i915#8497]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-8/igt@i915_selftest@l...@requests.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122429v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html
* igt@i915_selftest@live@slpc:
- bat-mtlp-8: [DMESG-WARN][19] ([i915#6367]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-mtlp-8/igt@i915_selftest@l...@slpc.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122429v1/bat-mtlp-8/igt@i915_selftest@l...@slpc.html
Warnings
* igt@i915_module_load@load:
- bat-adlp-11:[ABORT][21] ([i915#4423]) -> [DMESG-WARN][22]
([i915#4423])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13517/bat-adlp-11/igt@i915_module_l...@load.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122429v1/bat-adlp-11/igt@i915_module_l...@load.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/486
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1982
[Intel-gfx] [PATCH v2 i-g-t] tests/i915_pm_freq_api: Ignore zero register value
Register read for requested_freq can return 0 when system is in runtime_pm. Make allowance for this case. v2: Explicit check for runtime_pm status (Riana) Link: https://gitlab.freedesktop.org/drm/intel/issues/8736 Link: https://gitlab.freedesktop.org/drm/intel/issues/8989 Signed-off-by: Vinay Belgaumkar --- tests/i915/i915_pm_freq_api.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/tests/i915/i915_pm_freq_api.c b/tests/i915/i915_pm_freq_api.c index cf21cc936..6713ad213 100644 --- a/tests/i915/i915_pm_freq_api.c +++ b/tests/i915/i915_pm_freq_api.c @@ -95,14 +95,16 @@ static void test_reset(int i915, int dirfd, int gt, int count) igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); usleep(ACT_FREQ_LATENCY_US); - igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn); + if (igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE) + igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn); /* Manually trigger a GT reset */ fd = igt_debugfs_gt_open(i915, gt, "reset", O_WRONLY); igt_require(fd >= 0); igt_ignore_warn(write(fd, "1\n", 2)); - igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn); + if (igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE) + igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn); } close(fd); } @@ -114,13 +116,15 @@ static void test_suspend(int i915, int dirfd, int gt) igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0); igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0); usleep(ACT_FREQ_LATENCY_US); - igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn); + if (igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE) + igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn); /* Manually trigger a suspend */ igt_system_suspend_autoresume(SUSPEND_STATE_S3, SUSPEND_TEST_NONE); - igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn); + if (igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE) + igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn); } int i915 = -1; -- 2.38.1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: add lock while printing frontbuffer tracking bits to debugfs
== Series Details == Series: drm/i915/display: add lock while printing frontbuffer tracking bits to debugfs URL : https://patchwork.freedesktop.org/series/122429/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: add lock while printing frontbuffer tracking bits to debugfs
== Series Details == Series: drm/i915/display: add lock while printing frontbuffer tracking bits to debugfs URL : https://patchwork.freedesktop.org/series/122429/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✓ Fi.CI.IGT: success for video/hdmi: convert *_infoframe_init() functions to void
== Series Details == Series: video/hdmi: convert *_infoframe_init() functions to void URL : https://patchwork.freedesktop.org/series/122417/ State : success == Summary == CI Bug Log - changes from CI_DRM_13516_full -> Patchwork_122417v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_122417v1_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@object-reloc-purge-cache: - shard-dg2: NOTRUN -> [SKIP][1] ([i915#8411]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-dg2-11/igt@api_intel...@object-reloc-purge-cache.html * igt@api_intel_bb@render-ccs: - shard-dg2: NOTRUN -> [FAIL][2] ([i915#6122]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-dg2-1/igt@api_intel...@render-ccs.html * igt@device_reset@cold-reset-bound: - shard-dg2: NOTRUN -> [SKIP][3] ([i915#7701]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-dg2-1/igt@device_re...@cold-reset-bound.html * igt@device_reset@unbind-reset-rebind: - shard-dg1: NOTRUN -> [ABORT][4] ([i915#4983] / [i915#7461]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-dg1-18/igt@device_re...@unbind-reset-rebind.html * igt@drm_fdinfo@virtual-busy-idle-all: - shard-dg2: NOTRUN -> [SKIP][5] ([i915#8414]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-dg2-11/igt@drm_fdi...@virtual-busy-idle-all.html - shard-dg1: NOTRUN -> [SKIP][6] ([i915#8414]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-dg1-18/igt@drm_fdi...@virtual-busy-idle-all.html * igt@feature_discovery@display-4x: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#1839]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-dg2-11/igt@feature_discov...@display-4x.html - shard-dg1: NOTRUN -> [SKIP][8] ([i915#1839]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-dg1-18/igt@feature_discov...@display-4x.html * igt@gem_basic@multigpu-create-close: - shard-dg2: NOTRUN -> [SKIP][9] ([i915#7697]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-dg2-1/igt@gem_ba...@multigpu-create-close.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-snb: NOTRUN -> [DMESG-WARN][10] ([i915#8841]) +7 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-snb4/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1099]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-snb4/igt@gem_ctx_persiste...@legacy-engines-mixed.html * igt@gem_eio@kms: - shard-dg2: [PASS][12] -> [INCOMPLETE][13] ([i915#7892]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-dg2-10/igt@gem_...@kms.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-dg2-2/igt@gem_...@kms.html * igt@gem_exec_balancer@noheartbeat: - shard-dg2: NOTRUN -> [SKIP][14] ([i915#8555]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-dg2-1/igt@gem_exec_balan...@noheartbeat.html * igt@gem_exec_capture@capture@vcs0-smem: - shard-mtlp: [PASS][15] -> [DMESG-WARN][16] ([i915#5591]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-mtlp-6/igt@gem_exec_capture@capt...@vcs0-smem.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-mtlp-3/igt@gem_exec_capture@capt...@vcs0-smem.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#2846]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-glk3/igt@gem_exec_f...@basic-deadline.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-glk1/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-pace: - shard-dg1: NOTRUN -> [SKIP][19] ([i915#3539]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-dg1-18/igt@gem_exec_f...@basic-pace.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-rkl: [PASS][20] -> [FAIL][21] ([i915#2842]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-rkl-2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/shard-rkl-2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_flush@basic-batch-kernel-default-uc: - shard-mtlp:
Re: [Intel-gfx] [PATCH i-g-t] tests/i915_pm_freq_api: Ignore zero register value
On 8/14/2023 12:24 AM, Riana Tauro wrote:
Hi Vinay
On 8/9/2023 6:20 AM, Vinay Belgaumkar wrote:
Register read for requested_freq can return 0 when system is
in runtime_pm. Make allowance for this case.
Link: https://gitlab.freedesktop.org/drm/intel/issues/8736
Link: https://gitlab.freedesktop.org/drm/intel/issues/8989
Signed-off-by: Vinay Belgaumkar
---
tests/i915/i915_pm_freq_api.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/tests/i915/i915_pm_freq_api.c
b/tests/i915/i915_pm_freq_api.c
index cf21cc936..9c71411ee 100644
--- a/tests/i915/i915_pm_freq_api.c
+++ b/tests/i915/i915_pm_freq_api.c
@@ -88,6 +88,7 @@ static void test_freq_basic_api(int dirfd, int gt)
static void test_reset(int i915, int dirfd, int gt, int count)
{
uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ);
+ uint32_t req_freq;
int fd;
for (int i = 0; i < count; i++) {
@@ -95,14 +96,18 @@ static void test_reset(int i915, int dirfd, int
gt, int count)
igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0);
igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0);
usleep(ACT_FREQ_LATENCY_US);
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
Is there anything else that can cause req_freq to be zero?
To differentiate can we assert only when runtime_status is active
(igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE) ?
Makes sense, re-sending.
Thanks,
Vinay.
Thanks
Riana Tauro
/* Manually trigger a GT reset */
fd = igt_debugfs_gt_open(i915, gt, "reset", O_WRONLY);
igt_require(fd >= 0);
igt_ignore_warn(write(fd, "1\n", 2));
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
}
close(fd);
}
@@ -110,17 +115,22 @@ static void test_reset(int i915, int dirfd, int
gt, int count)
static void test_suspend(int i915, int dirfd, int gt)
{
uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ);
+ uint32_t req_freq;
igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0);
igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0);
usleep(ACT_FREQ_LATENCY_US);
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
/* Manually trigger a suspend */
igt_system_suspend_autoresume(SUSPEND_STATE_S3,
SUSPEND_TEST_NONE);
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
}
int i915 = -1;
[Intel-gfx] [PATCH] drm/i915/display: add lock while printing frontbuffer tracking bits to debugfs
Add missing spin_lock/unlock
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 63c1fb9e479f..f05b52381a83 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -43,12 +43,16 @@ static int i915_frontbuffer_tracking(struct seq_file *m,
void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ spin_lock(&dev_priv->display.fb_tracking.lock);
+
seq_printf(m, "FB tracking busy bits: 0x%08x\n",
dev_priv->display.fb_tracking.busy_bits);
seq_printf(m, "FB tracking flip bits: 0x%08x\n",
dev_priv->display.fb_tracking.flip_bits);
+ spin_unlock(&dev_priv->display.fb_tracking.lock);
+
return 0;
}
--
2.41.0
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Remove Wa_15010599737
== Series Details == Series: drm/i915/dg2: Remove Wa_15010599737 URL : https://patchwork.freedesktop.org/series/122426/ State : success == Summary == CI Bug Log - changes from CI_DRM_13516 -> Patchwork_122426v1 Summary --- **WARNING** Minor unknown changes coming with Patchwork_122426v1 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122426v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/index.html Participating hosts (41 -> 36) -- Missing(5): fi-apl-guc fi-snb-2520m fi-glk-j4005 fi-pnv-d510 bat-dg2-14 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122426v1: ### IGT changes ### Warnings * igt@kms_psr@cursor_plane_move: - bat-rplp-1: [ABORT][1] ([i915#8469] / [i915#8668]) -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rplp-1/igt@kms_psr@cursor_plane_move.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/bat-rplp-1/igt@kms_psr@cursor_plane_move.html Known issues Here are the changes found in Patchwork_122426v1 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@reset: - bat-rpls-1: [PASS][3] -> [ABORT][4] ([i915#4983] / [i915#7461] / [i915#8347] / [i915#8384]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rpls-1/igt@i915_selftest@l...@reset.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/bat-rpls-1/igt@i915_selftest@l...@reset.html * igt@i915_selftest@live@slpc: - bat-rpls-2: [PASS][5] -> [DMESG-WARN][6] ([i915#6367]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rpls-2/igt@i915_selftest@l...@slpc.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/bat-rpls-2/igt@i915_selftest@l...@slpc.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-jsl-3: NOTRUN -> [SKIP][7] ([i915#7828]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/bat-jsl-3/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#1845] / [i915#5354]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html Possible fixes * igt@gem_exec_suspend@basic-s0@smem: - bat-jsl-3: [ABORT][9] ([i915#5122]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@guc: - bat-rpls-2: [DMESG-WARN][11] ([i915#7852]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rpls-2/igt@i915_selftest@l...@guc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/bat-rpls-2/igt@i915_selftest@l...@guc.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [DMESG-WARN][13] ([i915#7699]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-dg2-11/igt@i915_selftest@l...@migrate.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@i915_suspend@basic-s3-without-i915: - bat-jsl-3: [FAIL][15] ([fdo#103375]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html Warnings * igt@i915_selftest@live@requests: - bat-mtlp-6: [DMESG-FAIL][17] ([i915#8497]) -> [ABORT][18] ([i915#7982] / [i915#8865]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-mtlp-6/igt@i915_selftest@l...@requests.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122426v1/bat-mtlp-6/igt@i915_selftest@l...@requests.html [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461 [i915#76
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix Kconfig error for CONFIG_DRM_I915
== Series Details == Series: drm/i915: Fix Kconfig error for CONFIG_DRM_I915 URL : https://patchwork.freedesktop.org/series/122415/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13516_full -> Patchwork_122415v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_122415v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122415v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122415v1_full: ### IGT changes ### Possible regressions * igt@gem_exec_flush@basic-batch-kernel-default-wb: - shard-mtlp: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-mtlp-8/igt@gem_exec_fl...@basic-batch-kernel-default-wb.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/shard-mtlp-4/igt@gem_exec_fl...@basic-batch-kernel-default-wb.html * igt@kms_lease@master-vs-lease: - shard-dg2: [PASS][3] -> [TIMEOUT][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-dg2-6/igt@kms_le...@master-vs-lease.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/shard-dg2-12/igt@kms_le...@master-vs-lease.html Warnings * igt@gem_mmap_wc@write-cpu-read-wc-unflushed: - shard-dg2: [SKIP][5] ([i915#4083]) -> [TIMEOUT][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-dg2-6/igt@gem_mmap...@write-cpu-read-wc-unflushed.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/shard-dg2-12/igt@gem_mmap...@write-cpu-read-wc-unflushed.html * igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_rc_ccs: - shard-dg2: [SKIP][7] ([i915#5354]) -> [TIMEOUT][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-dg2-6/igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_rc_ccs.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/shard-dg2-12/igt@kms_ccs@pipe-a-crc-primary-basic-4_tiled_mtl_rc_ccs.html * igt@kms_frontbuffer_tracking@fbc-badstride: - shard-dg2: [FAIL][9] ([i915#6880]) -> [TIMEOUT][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/shard-dg2-6/igt@kms_frontbuffer_track...@fbc-badstride.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/shard-dg2-12/igt@kms_frontbuffer_track...@fbc-badstride.html Known issues Here are the changes found in Patchwork_122415v1_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@blit-reloc-purge-cache: - shard-dg2: NOTRUN -> [SKIP][11] ([i915#8411]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/shard-dg2-1/igt@api_intel...@blit-reloc-purge-cache.html * igt@api_intel_bb@render-ccs: - shard-dg2: NOTRUN -> [FAIL][12] ([i915#6122]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/shard-dg2-1/igt@api_intel...@render-ccs.html * igt@device_reset@cold-reset-bound: - shard-dg2: NOTRUN -> [SKIP][13] ([i915#7701]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/shard-dg2-10/igt@device_re...@cold-reset-bound.html * igt@device_reset@unbind-reset-rebind: - shard-dg1: NOTRUN -> [ABORT][14] ([i915#4983] / [i915#7461]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/shard-dg1-16/igt@device_re...@unbind-reset-rebind.html * igt@drm_fdinfo@busy-idle-check-all@vcs1: - shard-dg1: NOTRUN -> [SKIP][15] ([i915#8414]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/shard-dg1-17/igt@drm_fdinfo@busy-idle-check-...@vcs1.html * igt@drm_fdinfo@virtual-busy-all: - shard-dg2: NOTRUN -> [SKIP][16] ([i915#8414]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/shard-dg2-1/igt@drm_fdi...@virtual-busy-all.html * igt@feature_discovery@display-4x: - shard-dg1: NOTRUN -> [SKIP][17] ([i915#1839]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/shard-dg1-16/igt@feature_discov...@display-4x.html * igt@gem_basic@multigpu-create-close: - shard-dg2: NOTRUN -> [SKIP][18] ([i915#7697]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/shard-dg2-1/igt@gem_ba...@multigpu-create-close.html * igt@gem_ccs@block-copy-compressed: - shard-dg1: NOTRUN -> [SKIP][19] ([i915#3555] / [i915#5325]) [19]: https://intel-gfx-ci.01.org/tree/d
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: Remove Wa_15010599737
== Series Details == Series: drm/i915/dg2: Remove Wa_15010599737 URL : https://patchwork.freedesktop.org/series/122426/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Remove Wa_15010599737
== Series Details == Series: drm/i915/dg2: Remove Wa_15010599737 URL : https://patchwork.freedesktop.org/series/122426/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
Re: [Intel-gfx] [PATCH] drm/i915/dgfx: Enable d3cold at s2idle
On Mon, Aug 14, 2023 at 04:34:18PM +0530, Anshuman Gupta wrote:
> System wide suspend already has support for lmem save/restore during
> suspend therefore enabling d3cold for s2idle and keepng it disable for
> runtime PM.(Refer below commit for d3cold runtime PM disable justification)
> 'commit 66eb93e71a7a ("drm/i915/dgfx: Keep PCI autosuspend control
> 'on' by default on all dGPU")'
>
> It will reduce the DG2 Card power consumption to ~0 Watt
> for s2idle power KPI.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8755
> Cc: Rodrigo Vivi
> Signed-off-by: Anshuman Gupta
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_driver.c | 33 --
> 1 file changed, 18 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> index b870c0df081a..ec4d26b3c17c 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -443,7 +443,6 @@ static int i915_pcode_init(struct drm_i915_private *i915)
> static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
> {
> struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> - struct pci_dev *root_pdev;
> int ret;
>
> if (i915_inject_probe_failure(dev_priv))
> @@ -557,15 +556,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
> *dev_priv)
>
> intel_bw_init_hw(dev_priv);
>
> - /*
> - * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
> - * This should be totally removed when we handle the pci states properly
> - * on runtime PM and on s2idle cases.
> - */
> - root_pdev = pcie_find_root_port(pdev);
> - if (root_pdev)
> - pci_d3cold_disable(root_pdev);
> -
> return 0;
>
> err_opregion:
> @@ -591,7 +581,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
> *dev_priv)
> static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
> {
> struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> - struct pci_dev *root_pdev;
>
> i915_perf_fini(dev_priv);
>
> @@ -599,10 +588,6 @@ static void i915_driver_hw_remove(struct
> drm_i915_private *dev_priv)
>
> if (pdev->msi_enabled)
> pci_disable_msi(pdev);
> -
> - root_pdev = pcie_find_root_port(pdev);
> - if (root_pdev)
> - pci_d3cold_enable(root_pdev);
> }
>
> /**
> @@ -1519,6 +1504,8 @@ static int intel_runtime_suspend(struct device *kdev)
> {
> struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
> + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> + struct pci_dev *root_pdev;
> struct intel_gt *gt;
> int ret, i;
>
> @@ -1570,6 +1557,15 @@ static int intel_runtime_suspend(struct device *kdev)
> drm_err(&dev_priv->drm,
> "Unclaimed access detected prior to suspending\n");
>
> + /*
> + * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
> + * This should be totally removed when we handle the pci states properly
> + * on runtime PM.
> + */
> + root_pdev = pcie_find_root_port(pdev);
> + if (root_pdev)
> + pci_d3cold_disable(root_pdev);
> +
> rpm->suspended = true;
>
> /*
> @@ -1608,6 +1604,8 @@ static int intel_runtime_resume(struct device *kdev)
> {
> struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
> + struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> + struct pci_dev *root_pdev;
> struct intel_gt *gt;
> int ret, i;
>
> @@ -1621,6 +1619,11 @@ static int intel_runtime_resume(struct device *kdev)
>
> intel_opregion_notify_adapter(dev_priv, PCI_D0);
> rpm->suspended = false;
> +
> + root_pdev = pcie_find_root_port(pdev);
> + if (root_pdev)
> + pci_d3cold_enable(root_pdev);
> +
> if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
> drm_dbg(&dev_priv->drm,
> "Unclaimed access during suspend, bios?\n");
> --
> 2.25.1
>
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc/slpc: Restore efficient freq earlier (rev3)
On Fri, Aug 11, 2023 at 10:54:57AM -0700, Belgaumkar, Vinay wrote: > > On 8/10/2023 5:22 PM, Rodrigo Vivi wrote: > > On Wed, Aug 02, 2023 at 12:41:09AM +, Belgaumkar, Vinay wrote: > > > From: Patchwork > > > Sent: Thursday, July 27, 2023 6:59 PM > > > To: Belgaumkar, Vinay > > > Cc: intel-gfx@lists.freedesktop.org > > > Subject: ✗ Fi.CI.IGT: failure for drm/i915/guc/slpc: Restore efficient > > > freq earlier (rev3) > > > Patch Details > > > Series: drm/i915/guc/slpc: Restore efficient freq earlier (rev3) > > > URL: [1]https://patchwork.freedesktop.org/series/121150/ > > > State: failure > > > Details: > > > [2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121150v3/index.html > > > CI Bug Log - changes from CI_DRM_13432_full -> > > > Patchwork_121150v3_full > > > Summary > > > FAILURE > > > Serious unknown changes coming with Patchwork_121150v3_full absolutely > > > need to be > > > verified manually. > > > If you think the reported changes have nothing to do with the changes > > > introduced in Patchwork_121150v3_full, please notify your bug team to > > > allow them > > > to document this new failure mode, which will reduce false positives > > > in > > > CI. > > > Participating hosts (10 -> 10) > > > No changes in participating hosts > > > Possible new issues > > > Here are the unknown changes that may have been introduced in > > > Patchwork_121150v3_full: > > >IGT changes > > > Possible regressions > > > • igt@sysfs_timeslice_duration@invalid: > > > ◦ shard-mtlp: NOTRUN -> [3]TIMEOUT > > > Does not seem related to this patch. > > But i915_selftests@live@workarounds seems to fail on every platform after I > > cherry > > picked this patch to drm-intel-fixes: > > > > http://gfx-ci.igk.intel.com/tree/drm-intel-fixes/combined-alt.html? > > > > <5> [314.508910] i915 :00:02.0: [drm] Resetting chip for > > live_workarounds > > <6> [314.511971] i915 :00:02.0: [drm] GT0: GuC firmware > > i915/mtl_guc_70.bin version 70.8.0 > > <7> [314.523625] i915 :00:02.0: [drm:intel_guc_fw_upload [i915]] GT0: > > GUC: init took 8ms, freq = 2250MHz, before = 2250MHz, status = 0x8002F034, > > count = 0, ret = 0 > > <7> [314.526596] i915 :00:02.0: [drm:guc_enable_communication [i915]] > > GT0: GUC: communication enabled > > <6> [314.531291] i915 :00:02.0: [drm] GT0: GUC: submission enabled > > <6> [314.531324] i915 :00:02.0: [drm] GT0: GUC: SLPC enabled > > <6> [314.576597] i915: Running > > intel_workarounds_live_selftests/live_engine_reset_workarounds > > <7> [314.576715] MCR Steering: L3BANK steering: group=0x0, instance=0x0 > > <7> [314.576736] MCR Steering: DSS steering: group=0x0, instance=0x0 > > <7> [314.576751] MCR Steering: INSTANCE 0 steering: group=0x0, instance=0x0 > > <7> [314.576818] i915 :00:02.0: [drm:wa_init_finish [i915]] Initialized > > 5 GT_REF workarounds on global > > <7> [314.578192] i915 :00:02.0: [drm:wa_init_finish [i915]] Initialized > > 5 REF workarounds on rcs0 > > <7> [314.579454] i915 :00:02.0: [drm:wa_init_finish [i915]] Initialized > > 6 CTX_REF workarounds on rcs0 > > <7> [314.580487] i915 :00:02.0: [drm:wa_init_finish [i915]] Initialized > > 1 REF workarounds on bcs0 > > <7> [314.581449] i915 :00:02.0: [drm:wa_init_finish [i915]] Initialized > > 2 CTX_REF workarounds on bcs0 > > <7> [314.582206] i915 :00:02.0: [drm:wa_init_finish [i915]] Initialized > > 1 REF workarounds on ccs0 > > <7> [314.583122] i915 :00:02.0: [drm:wa_init_finish [i915]] Initialized > > 1 CTX_REF workarounds on ccs0 > > <6> [314.584067] Verifying after rcs0 reset... > > <7> [314.609843] i915 :00:02.0: > > [drm:intel_guc_context_reset_process_msg [i915]] GT0: GUC: Got context > > reset notification: 0x1002 on rcs0, exiting = no, banned = no > > <6> [314.777958] i915 :00:02.0: [drm] GPU HANG: ecode 12:0: > > <6> [314.792928] Verifying after bcs0 reset... > > <3> [325.082480] i915/intel_workarounds_live_selftests: > > live_engine_reset_workarounds failed with error -62 > > > > could you please help to understand what is going on here? > > Looks like this is a known bug and has been failing for months - > https://gitlab.freedesktop.org/drm/intel/-/issues/6763 I'm sorry for the noise. I don't understand why this only showed up now on the CI for our fixes branch, but I have confirmed that it is still there even without this patch. So I'm going to ignore this and I'm propagating this patch this week. Sorry and thanks for the help, Rodrigo. > > Thanks, > > Vinay. > > > > > Thanks, > > Rodrigo. > > > > > Thanks, > > > Vinay. > > > Known issues > > > Here are the changes found in Patchwork_121150v3_full that come from > > > known > > > issues: > > >IGT changes > > > Issues hit > > > • igt@drm_fdinfo@virtual-busy: > > > ◦ shard-dg1: NOTRUN -> [4]SKIP ([5]i915#8414) > > >
[Intel-gfx] ✗ Fi.CI.BAT: failure for Fix C10/C20 implementation w.r.t. owned PHY lanes (rev2)
== Series Details == Series: Fix C10/C20 implementation w.r.t. owned PHY lanes (rev2) URL : https://patchwork.freedesktop.org/series/121334/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13516 -> Patchwork_121334v2 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_121334v2 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_121334v2, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v2/index.html Participating hosts (41 -> 40) -- Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_121334v2: ### IGT changes ### Possible regressions * igt@core_hotunplug@unbind-rebind: - bat-mtlp-6: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-mtlp-6/igt@core_hotunp...@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v2/bat-mtlp-6/igt@core_hotunp...@unbind-rebind.html * igt@i915_pm_rpm@module-reload: - fi-apl-guc: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/fi-apl-guc/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v2/fi-apl-guc/igt@i915_pm_...@module-reload.html Known issues Here are the changes found in Patchwork_121334v2 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [PASS][5] -> [ABORT][6] ([i915#7911] / [i915#7913]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v2/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@reset: - bat-rpls-1: [PASS][7] -> [ABORT][8] ([i915#4983] / [i915#7461] / [i915#7981] / [i915#8347] / [i915#8384]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rpls-1/igt@i915_selftest@l...@reset.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v2/bat-rpls-1/igt@i915_selftest@l...@reset.html * igt@i915_selftest@live@slpc: - bat-rpls-2: [PASS][9] -> [DMESG-WARN][10] ([i915#6367]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rpls-2/igt@i915_selftest@l...@slpc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v2/bat-rpls-2/igt@i915_selftest@l...@slpc.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#1845] / [i915#5354]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v2/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_psr@sprite_plane_onoff: - bat-rplp-1: NOTRUN -> [ABORT][12] ([i915#8442] / [i915#8668] / [i915#8712]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v2/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html Possible fixes * igt@i915_selftest@live@guc: - bat-rpls-2: [DMESG-WARN][13] ([i915#7852]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rpls-2/igt@i915_selftest@l...@guc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v2/bat-rpls-2/igt@i915_selftest@l...@guc.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [DMESG-WARN][15] ([i915#7699]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-dg2-11/igt@i915_selftest@l...@migrate.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v2/bat-dg2-11/igt@i915_selftest@l...@migrate.html Warnings * igt@i915_module_load@load: - bat-adlp-11:[DMESG-WARN][17] ([i915#4423]) -> [ABORT][18] ([i915#4423]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-adlp-11/igt@i915_module_l...@load.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v2/bat-adlp-11/igt@i915_module_l...@load.html * igt@kms_psr@cursor_plane_move: - bat-rplp-1: [ABORT][19] ([i915#8469] / [i915#8668]) -> [SKIP][20] ([i915#1072]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rplp-1/igt@kms_psr@cursor_plane_move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v2/bat-rplp-1/igt@kms_psr@cursor_plane_move.html [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#4423]: https://gitlab.freedesktop.org/drm/i
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fix C10/C20 implementation w.r.t. owned PHY lanes (rev2)
== Series Details == Series: Fix C10/C20 implementation w.r.t. owned PHY lanes (rev2) URL : https://patchwork.freedesktop.org/series/121334/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix C10/C20 implementation w.r.t. owned PHY lanes (rev2)
== Series Details == Series: Fix C10/C20 implementation w.r.t. owned PHY lanes (rev2) URL : https://patchwork.freedesktop.org/series/121334/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI (rev3)
== Series Details == Series: drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI (rev3) URL : https://patchwork.freedesktop.org/series/122108/ State : success == Summary == CI Bug Log - changes from CI_DRM_13516 -> Patchwork_122108v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/index.html Participating hosts (41 -> 39) -- Missing(2): fi-snb-2520m fi-pnv-d510 Known issues Here are the changes found in Patchwork_122108v3 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@slpc: - bat-mtlp-6: [PASS][1] -> [DMESG-WARN][2] ([i915#6367]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-mtlp-6/igt@i915_selftest@l...@slpc.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/bat-mtlp-6/igt@i915_selftest@l...@slpc.html - bat-rpls-2: [PASS][3] -> [DMESG-WARN][4] ([i915#6367]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rpls-2/igt@i915_selftest@l...@slpc.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/bat-rpls-2/igt@i915_selftest@l...@slpc.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-jsl-3: NOTRUN -> [SKIP][5] ([i915#7828]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/bat-jsl-3/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#1845] / [i915#5354]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_psr@primary_mmap_gtt: - bat-rplp-1: NOTRUN -> [SKIP][7] ([i915#1072]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html * igt@kms_setmode@basic-clone-single-crtc: - bat-rplp-1: NOTRUN -> [ABORT][8] ([i915#8260] / [i915#8668]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html Possible fixes * igt@gem_exec_suspend@basic-s0@smem: - bat-jsl-3: [ABORT][9] ([i915#5122]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: [DMESG-FAIL][11] ([i915#7059]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@guc: - bat-rpls-2: [DMESG-WARN][13] ([i915#7852]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rpls-2/igt@i915_selftest@l...@guc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/bat-rpls-2/igt@i915_selftest@l...@guc.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [DMESG-WARN][15] ([i915#7699]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-dg2-11/igt@i915_selftest@l...@migrate.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@requests: - bat-mtlp-6: [DMESG-FAIL][17] ([i915#8497]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-mtlp-6/igt@i915_selftest@l...@requests.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/bat-mtlp-6/igt@i915_selftest@l...@requests.html * igt@i915_suspend@basic-s3-without-i915: - bat-jsl-3: [FAIL][19] ([fdo#103375]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html Warnings * igt@i915_module_load@load: - bat-adlp-11:[DMESG-WARN][21] ([i915#4423]) -> [ABORT][22] ([i915#4423]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-adlp-11/igt@i915_module_l...@load.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122108v3/bat-adlp-11/igt@i915_module_l...@load.html * igt@kms_psr@cursor_plane_move: - bat-rplp-1: [ABORT][23] ([i915#8469] / [i915#8668]) -> [SKIP][24] ([i915#1072]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rplp-1/igt@kms_psr@cursor_plane_move.html [24]: h
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI (rev3)
== Series Details == Series: drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI (rev3) URL : https://patchwork.freedesktop.org/series/122108/ State : warning == Summary == Error: dim sparse failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI (rev3)
== Series Details == Series: drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI (rev3) URL : https://patchwork.freedesktop.org/series/122108/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Remove Wa_15010599737
On Mon, Aug 14, 2023 at 08:32:15PM +0530, Shekhar Chauhan wrote: > Since this Wa is specific to DirectX, this is not required on Linux. > > Signed-off-by: Shekhar Chauhan Reviewed-by: Matt Roper Too bad the hardware teams didn't do a better job of documenting this so that we would have known earlier. Matt > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 --- > 2 files changed, 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 718cb2c80f79..15b82d37486b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -412,9 +412,6 @@ > > #define XEHP_CULLBIT1MCR_REG(0x6100) > > -#define CHICKEN_RASTER_1 MCR_REG(0x6204) > -#define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8) > - > #define CHICKEN_RASTER_2 MCR_REG(0x6208) > #define TBIMR_FAST_CLIPREG_BIT(5) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 01807a7dd2c1..5aa0d3f23c6b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -805,9 +805,6 @@ static void dg2_ctx_workarounds_init(struct > intel_engine_cs *engine, > IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > wa_mcr_masked_en(wal, XEHP_PSS_MODE2, > SCOREBOARD_STALL_FLUSH_CONTROL); > > - /* Wa_15010599737:dg2 */ > - wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > - > /* Wa_18019271663:dg2 */ > wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); > } > -- > 2.34.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
[Intel-gfx] [PATCH] drm/i915/dg2: Remove Wa_15010599737
Since this Wa is specific to DirectX, this is not required on Linux. Signed-off-by: Shekhar Chauhan --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 --- 2 files changed, 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 718cb2c80f79..15b82d37486b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -412,9 +412,6 @@ #define XEHP_CULLBIT1 MCR_REG(0x6100) -#define CHICKEN_RASTER_1 MCR_REG(0x6204) -#define DIS_SF_ROUND_NEAREST_EVENREG_BIT(8) - #define CHICKEN_RASTER_2 MCR_REG(0x6208) #define TBIMR_FAST_CLIP REG_BIT(5) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 01807a7dd2c1..5aa0d3f23c6b 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -805,9 +805,6 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); - /* Wa_15010599737:dg2 */ - wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); - /* Wa_18019271663:dg2 */ wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); } -- 2.34.1
[Intel-gfx] ✓ Fi.CI.BAT: success for video/hdmi: convert *_infoframe_init() functions to void
== Series Details == Series: video/hdmi: convert *_infoframe_init() functions to void URL : https://patchwork.freedesktop.org/series/122417/ State : success == Summary == CI Bug Log - changes from CI_DRM_13516 -> Patchwork_122417v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/index.html Participating hosts (41 -> 40) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_122417v1 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#7911] / [i915#7920] / [i915#7982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rpls-1/igt@i915_selftest@l...@requests.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/bat-rpls-1/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@slpc: - bat-mtlp-6: [PASS][3] -> [DMESG-WARN][4] ([i915#6367]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-mtlp-6/igt@i915_selftest@l...@slpc.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/bat-mtlp-6/igt@i915_selftest@l...@slpc.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-jsl-3: NOTRUN -> [SKIP][5] ([i915#7828]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/bat-jsl-3/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#1845] / [i915#5354]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_psr@sprite_plane_onoff: - bat-rplp-1: NOTRUN -> [ABORT][7] ([i915#8442] / [i915#8712]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html Possible fixes * igt@gem_exec_suspend@basic-s0@smem: - bat-jsl-3: [ABORT][8] ([i915#5122]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@guc: - bat-rpls-2: [DMESG-WARN][10] ([i915#7852]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rpls-2/igt@i915_selftest@l...@guc.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/bat-rpls-2/igt@i915_selftest@l...@guc.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [DMESG-WARN][12] ([i915#7699]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-dg2-11/igt@i915_selftest@l...@migrate.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@requests: - bat-mtlp-6: [DMESG-FAIL][14] ([i915#8497]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-mtlp-6/igt@i915_selftest@l...@requests.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/bat-mtlp-6/igt@i915_selftest@l...@requests.html * igt@i915_suspend@basic-s3-without-i915: - bat-jsl-3: [FAIL][16] ([fdo#103375]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html Warnings * igt@i915_module_load@load: - bat-adlp-11:[DMESG-WARN][18] ([i915#4423]) -> [ABORT][19] ([i915#4423]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-adlp-11/igt@i915_module_l...@load.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/bat-adlp-11/igt@i915_module_l...@load.html * igt@kms_psr@cursor_plane_move: - bat-rplp-1: [ABORT][20] ([i915#8469] / [i915#8668]) -> [SKIP][21] ([i915#1072]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rplp-1/igt@kms_psr@cursor_plane_move.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122417v1/bat-rplp-1/igt@kms_psr@cursor_plane_move.html [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423 [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6367]: https:
Re: [Intel-gfx] [REGRESSION] HDMI connector detection broken in 6.3 on Intel(R) Celeron(R) N3060 integrated graphics
On Sun, Aug 13, 2023 at 03:41:30PM +0200, Linux regression tracking (Thorsten Leemhuis) wrote: Hi, > On 11.08.23 20:10, Mikhail Rudenko wrote: > > On 2023-08-11 at 08:45 +02, Thorsten Leemhuis > > wrote: > >> On 10.08.23 21:33, Mikhail Rudenko wrote: > >>> The following is a copy an issue I posted to drm/i915 gitlab [1] two > >>> months ago. I repost it to the mailing lists in hope that it will help > >>> the right people pay attention to it. > >> > >> Thx for your report. Wonder why Dmitry (who authored a4e771729a51) or > >> Thomas (who committed it) it didn't look into this, but maybe the i915 > >> devs didn't forward the report to them. > > For the record: they did, and Jani mentioned already. Sorry, should have > phrased this differently. > > >> Let's see if these mails help. Just wondering: does reverting > >> a4e771729a51 from 6.5-rc5 or drm-tip help as well? > > > > I've redone my tests with 6.5-rc5, and here are the results: > > (1) 6.5-rc5 -> still affected > > (2) 6.5-rc5 + revert a4e771729a51 -> not affected > > (3) 6.5-rc5 + two patches [1][2] suggested on i915 gitlab by @ideak -> not > > affected (!) > > > > Should we somehow tell regzbot about (3)? > > That's good to know, thx. But the more important things are: > > * When will those be merged? They are not yet in next yet afaics, so it > might take some time to mainline them, especially at this point of the > devel cycle. Imre, could you try to prod the right people so that these > are ideally upstreamed rather sooner than later, as they fix a regression? I think the patches ([1] and [2]) could be merged via the drm-intel-next (drm-intel-fixes) tree Cc'ing also stable. Jani, is this ok? > * They if possible ideally should be tagged for backporting to 6.4, as > this is a regression from the 6.3 cycle. > > But yes, let's tell regzbot that fixes are available, too: > > #regzbot fix: drm/i915: Fix HPD polling, reenabling the output poll work > as needed > > (for the record: that's the second of two patches apparently needed) > > Ciao, Thorsten (wearing his 'the Linux kernel's regression tracker' hat) > -- > Everything you wanna know about Linux kernel regression tracking: > https://linux-regtracking.leemhuis.info/about/#tldr > If I did something stupid, please tell me, as explained on that page. > > >> BTW, there was an earlier report about a problem with a4e771729a51 that > >> afaics was never addressed, but it might be unrelated. > >> https://lore.kernel.org/all/20230328023129.3596968-1-zhouzong...@kylinos.cn/ > > [1] https://patchwork.freedesktop.org/patch/548590/?series=121050&rev=1 > > [2] https://patchwork.freedesktop.org/patch/548591/?series=121050&rev=1 >
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for video/hdmi: convert *_infoframe_init() functions to void
== Series Details == Series: video/hdmi: convert *_infoframe_init() functions to void URL : https://patchwork.freedesktop.org/series/122417/ State : warning == Summary == Error: dim sparse failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for video/hdmi: convert *_infoframe_init() functions to void
== Series Details == Series: video/hdmi: convert *_infoframe_init() functions to void URL : https://patchwork.freedesktop.org/series/122417/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
Re: [Intel-gfx] [PATCH v2] drm/i915/display: Dual refresh rate fastset fixes with VRR fastset
Hi Manasi,
> -Original Message-
> From: Intel-gfx On Behalf Of Manasi
> Navare
> Sent: 12 August 2023 02:35
> To: intel-gfx@lists.freedesktop.org
> Cc: Drew Davenport ; Sean Paul
>
> Subject: [Intel-gfx] [PATCH v2] drm/i915/display: Dual refresh rate fastset
> fixes
> with VRR fastset
>
> Dual refresh rate (DRR) fastset seamlessly lets refresh rate throttle without
> needing a full modeset.
> However with the recent VRR fastset patches that got merged this logic was
> broken. This is broken because now with VRR fastset VRR parameters are
> calculated by default at the nominal refresh rate say 120Hz.
> Now when DRR throttle happens to switch refresh rate to 60Hz, crtc clock
> changes and this throws a mismatch in VRR parameters and fastset logic for
> DRR gets thrown off and full modeset is indicated.
>
> This patch fixes this by ignoring the pipe mismatch for VRR parameters in the
> case of DRR and when VRR is not enabled. With this fix, DRR will still
> throttle
> seamlessly as long as VRR is not enabled.
>
> This will still need a full modeset for both DRR and VRR operating together
> during the refresh rate throttle and then enabling VRR since now VRR
> parameters need to be recomputed with new crtc clock and written to HW.
>
> This DRR + VRR fastset in conjunction needs more work in the driver and will
> be fixed in later patches.
>
> v2:
> Check for pipe config mismatch in crtc clock whenever VRR is enabled
>
> Cc: Drew Davenport
> Cc: Ville Syrjälä
> Cc: Sean Paul
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 14 --
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 763ab569d8f3..efc407e11d8e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5352,7 +5352,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
> PIPE_CONF_CHECK_I(pipe_bpp);
>
> - if (!fastset || !pipe_config->seamless_m_n) {
> + if (!fastset || !pipe_config->seamless_m_n || pipe_config->vrr.enable)
> +{
> PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> }
> @@ -5387,11 +5387,13 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>
> if (!fastset)
> PIPE_CONF_CHECK_BOOL(vrr.enable);
> - PIPE_CONF_CHECK_I(vrr.vmin);
> - PIPE_CONF_CHECK_I(vrr.vmax);
> - PIPE_CONF_CHECK_I(vrr.flipline);
> - PIPE_CONF_CHECK_I(vrr.pipeline_full);
> - PIPE_CONF_CHECK_I(vrr.guardband);
> + if ((!fastset && !pipe_config->seamless_m_n) || pipe_config-
> >vrr.enable) {
> + PIPE_CONF_CHECK_I(vrr.vmin);
> + PIPE_CONF_CHECK_I(vrr.vmax);
> + PIPE_CONF_CHECK_I(vrr.flipline);
> + PIPE_CONF_CHECK_I(vrr.pipeline_full);
> + PIPE_CONF_CHECK_I(vrr.guardband);
> + }
It appears that when switching to the fixed refresh rate mode, such as the 60HZ
mode, the vrr.* parameters are also being changed.
However after implementing the change above, a pipe state mismatch occurs
during the 'intel_modeset_verify_crtc' process. I think
this occurs because we are avoiding 'PIPE_CONF_CHECK' to prevent a complete
modeset ?
Considering this would it be feasible to skip checking the aforementioned pipe
configuration during fixed refresh rate mode and only
compare them when we enable VRR ?
>
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> --
> 2.41.0.640.ga95def55d0-goog
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dgfx: Enable d3cold at s2idle
== Series Details == Series: drm/i915/dgfx: Enable d3cold at s2idle URL : https://patchwork.freedesktop.org/series/122413/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13515_full -> Patchwork_122413v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_122413v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122413v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122413v1_full: ### IGT changes ### Possible regressions * igt@gem_softpin@noreloc-s3: - shard-rkl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-rkl-4/igt@gem_soft...@noreloc-s3.html Known issues Here are the changes found in Patchwork_122413v1_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@blit-reloc-keep-cache: - shard-dg2: NOTRUN -> [SKIP][2] ([i915#8411]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-dg2-6/igt@api_intel...@blit-reloc-keep-cache.html * igt@drm_fdinfo@most-busy-check-all@bcs0: - shard-dg2: NOTRUN -> [SKIP][3] ([i915#8414]) +19 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-dg2-10/igt@drm_fdinfo@most-busy-check-...@bcs0.html * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [PASS][4] -> [FAIL][5] ([i915#7742]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/shard-rkl-7/igt@drm_fdinfo@most-busy-check-...@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-rkl-7/igt@drm_fdinfo@most-busy-check-...@rcs0.html * igt@drm_fdinfo@virtual-busy: - shard-mtlp: NOTRUN -> [SKIP][6] ([i915#8414]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-mtlp-2/igt@drm_fdi...@virtual-busy.html * igt@feature_discovery@display-2x: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#1839]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-dg2-11/igt@feature_discov...@display-2x.html * igt@gem_caching@writes: - shard-mtlp: NOTRUN -> [SKIP][8] ([i915#4873]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-mtlp-4/igt@gem_cach...@writes.html * igt@gem_ccs@ctrl-surf-copy: - shard-mtlp: NOTRUN -> [SKIP][9] ([i915#5325]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-mtlp-4/igt@gem_...@ctrl-surf-copy.html * igt@gem_close_race@multigpu-basic-threads: - shard-dg2: NOTRUN -> [SKIP][10] ([i915#7697]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-dg2-6/igt@gem_close_r...@multigpu-basic-threads.html * igt@gem_create@create-ext-set-pat: - shard-dg2: NOTRUN -> [SKIP][11] ([i915#8562]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-dg2-10/igt@gem_cre...@create-ext-set-pat.html * igt@gem_ctx_param@set-priority-not-supported: - shard-dg2: NOTRUN -> [SKIP][12] ([fdo#109314]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-dg2-6/igt@gem_ctx_pa...@set-priority-not-supported.html * igt@gem_ctx_persistence@legacy-engines-mixed-process: - shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-snb4/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html * igt@gem_ctx_sseu@invalid-sseu: - shard-dg2: NOTRUN -> [SKIP][14] ([i915#280]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-dg2-10/igt@gem_ctx_s...@invalid-sseu.html * igt@gem_eio@in-flight-contexts-10ms: - shard-mtlp: [PASS][15] -> [ABORT][16] ([i915#7941]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/shard-mtlp-4/igt@gem_...@in-flight-contexts-10ms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-mtlp-8/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_exec_capture@pi@ccs0: - shard-mtlp: [PASS][17] -> [FAIL][18] ([i915#7765]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/shard-mtlp-3/igt@gem_exec_capture@p...@ccs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/shard-mtlp-5/igt@gem_exec_capture@p...@ccs0.html * igt@gem_exec_fair@basic-none: - shard-dg2: NOTRUN -> [SKIP][19] ([i915#3539] / [i915#4852]) [19]: https://inte
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix Kconfig error for CONFIG_DRM_I915
== Series Details == Series: drm/i915: Fix Kconfig error for CONFIG_DRM_I915 URL : https://patchwork.freedesktop.org/series/122415/ State : success == Summary == CI Bug Log - changes from CI_DRM_13516 -> Patchwork_122415v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/index.html Participating hosts (41 -> 39) -- Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_122415v1 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gt_mocs: - bat-mtlp-6: [PASS][1] -> [DMESG-FAIL][2] ([i915#7059]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@requests: - bat-rpls-1: [PASS][3] -> [ABORT][4] ([i915#7911] / [i915#7920] / [i915#7982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rpls-1/igt@i915_selftest@l...@requests.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/bat-rpls-1/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@reset: - bat-rpls-2: [PASS][5] -> [ABORT][6] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#8347]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rpls-2/igt@i915_selftest@l...@reset.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/bat-rpls-2/igt@i915_selftest@l...@reset.html * igt@i915_selftest@live@slpc: - bat-mtlp-8: [PASS][7] -> [DMESG-WARN][8] ([i915#6367]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-mtlp-8/igt@i915_selftest@l...@slpc.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/bat-mtlp-8/igt@i915_selftest@l...@slpc.html - bat-adlm-1: [PASS][9] -> [DMESG-WARN][10] ([i915#6367]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-adlm-1/igt@i915_selftest@l...@slpc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/bat-adlm-1/igt@i915_selftest@l...@slpc.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-jsl-3: NOTRUN -> [SKIP][11] ([i915#7828]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/bat-jsl-3/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#1845] / [i915#5354]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1: - bat-rplp-1: [PASS][13] -> [ABORT][14] ([i915#8442] / [i915#8668]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html Possible fixes * igt@gem_exec_suspend@basic-s0@smem: - bat-jsl-3: [ABORT][15] ([i915#5122]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@requests: - bat-mtlp-6: [DMESG-FAIL][17] ([i915#8497]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-mtlp-6/igt@i915_selftest@l...@requests.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/bat-mtlp-6/igt@i915_selftest@l...@requests.html * igt@i915_suspend@basic-s3-without-i915: - bat-jsl-3: [FAIL][19] ([fdo#103375]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13516/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v1/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059 [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issu
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gmch: fix build error var set but not used
== Series Details == Series: drm/i915/gmch: fix build error var set but not used URL : https://patchwork.freedesktop.org/series/122416/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/122416/revisions/1/mbox/ not applied Applying: drm/i915/gmch: fix build error var set but not used Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/soc/intel_gmch.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/soc/intel_gmch.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/soc/intel_gmch.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm/i915/gmch: fix build error var set but not used When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix Kconfig error for CONFIG_DRM_I915
== Series Details == Series: drm/i915: Fix Kconfig error for CONFIG_DRM_I915 URL : https://patchwork.freedesktop.org/series/122415/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix Kconfig error for CONFIG_DRM_I915
== Series Details == Series: drm/i915: Fix Kconfig error for CONFIG_DRM_I915 URL : https://patchwork.freedesktop.org/series/122415/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] [PATCH v2 3/4] drm/i915/cx0: Enable/disable TX only for owned PHY lanes
Display must not enable or disable transmitters for not-owned PHY lanes.
BSpec: 64539
Reviewed-by: Mika Kahola
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 2b112ed78943..93d3a63fe89a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2607,10 +2607,11 @@ static void intel_cx0_program_phy_lane(struct
drm_i915_private *i915,
int i;
u8 disables;
bool dp_alt_mode =
intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
+ u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
enum port port = encoder->port;
if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
- intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
+ intel_cx0_rmw(i915, port, owned_lane_mask,
PHY_C10_VDR_CONTROL(1), 0,
C10_VDR_CTRL_MSGBUS_ACCESS,
MB_WRITE_COMMITTED);
@@ -2625,11 +2626,13 @@ static void intel_cx0_program_phy_lane(struct
drm_i915_private *i915,
disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
}
- /* TODO: DP-alt MFD case where only one PHY lane should be programmed.
*/
for (i = 0; i < 4; i++) {
int tx = i % 2 + 1;
u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
+ if (!(owned_lane_mask & lane_mask))
+ continue;
+
intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
CONTROL2_DISABLE_SINGLE_TX,
disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX :
0,
@@ -2637,7 +2640,7 @@ static void intel_cx0_program_phy_lane(struct
drm_i915_private *i915,
}
if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
- intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
+ intel_cx0_rmw(i915, port, owned_lane_mask,
PHY_C10_VDR_CONTROL(1), 0,
C10_VDR_CTRL_UPDATE_CFG,
MB_WRITE_COMMITTED);
--
2.41.0
[Intel-gfx] [PATCH v2 4/4] drm/i915/cx0: Program vswing only for owned lanes
According to the BSpec, voltage swing programming should be done for
owned PHY lanes. Do not program a not-owned PHY lane.
BSpec: 74103, 74104
Reviewed-by: Mika Kahola
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25 +++-
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 93d3a63fe89a..26e256165b80 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -375,6 +375,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder
*encoder,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_ddi_buf_trans *trans;
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
intel_wakeref_t wakeref;
int n_entries, ln;
@@ -387,13 +388,13 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder
*encoder,
}
if (intel_is_c10phy(i915, phy)) {
- intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
PHY_C10_VDR_CONTROL(1),
+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
PHY_C10_VDR_CONTROL(1),
0, C10_VDR_CTRL_MSGBUS_ACCESS,
MB_WRITE_COMMITTED);
- intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
PHY_C10_VDR_CMN(3),
+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
PHY_C10_VDR_CMN(3),
C10_CMN3_TXVBOOST_MASK,
C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
MB_WRITE_UNCOMMITTED);
- intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
PHY_C10_VDR_TX(1),
+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
PHY_C10_VDR_TX(1),
C10_TX1_TERMCTL_MASK,
C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),
MB_WRITE_COMMITTED);
@@ -401,32 +402,34 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder
*encoder,
for (ln = 0; ln < crtc_state->lane_count; ln++) {
int level = intel_ddi_level(encoder, crtc_state, ln);
- int lane, tx;
+ int lane = ln / 2;
+ int tx = ln % 2;
+ u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
- lane = ln / 2;
- tx = ln % 2;
+ if (!(lane_mask & owned_lane_mask))
+ continue;
- intel_cx0_rmw(i915, encoder->port, BIT(lane),
PHY_CX0_VDROVRD_CTL(lane, tx, 0),
+ intel_cx0_rmw(i915, encoder->port, lane_mask,
PHY_CX0_VDROVRD_CTL(lane, tx, 0),
C10_PHY_OVRD_LEVEL_MASK,
C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),
MB_WRITE_COMMITTED);
- intel_cx0_rmw(i915, encoder->port, BIT(lane),
PHY_CX0_VDROVRD_CTL(lane, tx, 1),
+ intel_cx0_rmw(i915, encoder->port, lane_mask,
PHY_CX0_VDROVRD_CTL(lane, tx, 1),
C10_PHY_OVRD_LEVEL_MASK,
C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing),
MB_WRITE_COMMITTED);
- intel_cx0_rmw(i915, encoder->port, BIT(lane),
PHY_CX0_VDROVRD_CTL(lane, tx, 2),
+ intel_cx0_rmw(i915, encoder->port, lane_mask,
PHY_CX0_VDROVRD_CTL(lane, tx, 2),
C10_PHY_OVRD_LEVEL_MASK,
C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor),
MB_WRITE_COMMITTED);
}
/* Write Override enables in 0xD71 */
- intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
PHY_C10_VDR_OVRD,
+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_OVRD,
0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
MB_WRITE_COMMITTED);
if (intel_is_c10phy(i915, phy))
- intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
PHY_C10_VDR_CONTROL(1),
+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
PHY_C10_VDR_CONTROL(1),
0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
intel_cx0_phy_transaction_end(encoder, wakeref);
--
2.41.0
[Intel-gfx] [PATCH v2 2/4] drm/i915: Simplify intel_cx0_program_phy_lane() with loop
It is possible to generalize the "disable" value for the transmitters to
be a bit mask based on the port width and the port reversal boolean,
with a small exception for DP-alt mode with "x1" port width.
Simplify the code by using such a mask and a for-loop instead of using
switch-case statements.
v2:
- Use (i < 2) instead of (i / 2 == 0) for PHY lane mask selection.
(Jani)
BSpec: 64539
Cc: Jani Nikula
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 79 +---
1 file changed, 20 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b903ceb0b56a..2b112ed78943 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2604,7 +2604,8 @@ static void intel_cx0_program_phy_lane(struct
drm_i915_private *i915,
struct intel_encoder *encoder, int
lane_count,
bool lane_reversal)
{
- u8 l0t1, l0t2, l1t1, l1t2;
+ int i;
+ u8 disables;
bool dp_alt_mode =
intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
enum port port = encoder->port;
@@ -2614,66 +2615,26 @@ static void intel_cx0_program_phy_lane(struct
drm_i915_private *i915,
C10_VDR_CTRL_MSGBUS_ACCESS,
MB_WRITE_COMMITTED);
- /* TODO: DP-alt MFD case where only one PHY lane should be programmed.
*/
- l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0,
PHY_CX0_TX_CONTROL(1, 2));
- l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0,
PHY_CX0_TX_CONTROL(2, 2));
- l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1,
PHY_CX0_TX_CONTROL(1, 2));
- l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1,
PHY_CX0_TX_CONTROL(2, 2));
-
- l0t1 |= CONTROL2_DISABLE_SINGLE_TX;
- l0t2 |= CONTROL2_DISABLE_SINGLE_TX;
- l1t1 |= CONTROL2_DISABLE_SINGLE_TX;
- l1t2 |= CONTROL2_DISABLE_SINGLE_TX;
-
- if (lane_reversal) {
- switch (lane_count) {
- case 4:
- l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
- fallthrough;
- case 3:
- l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
- fallthrough;
- case 2:
- l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
- fallthrough;
- case 1:
- l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
- break;
- default:
- MISSING_CASE(lane_count);
- }
- } else {
- switch (lane_count) {
- case 4:
- l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
- fallthrough;
- case 3:
- l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
- fallthrough;
- case 2:
- l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
- l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
- break;
- case 1:
- if (dp_alt_mode)
- l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
- else
- l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
- break;
- default:
- MISSING_CASE(lane_count);
- }
+ if (lane_reversal)
+ disables = REG_GENMASK8(3, 0) >> lane_count;
+ else
+ disables = REG_GENMASK8(3, 0) << lane_count;
+
+ if (dp_alt_mode && lane_count == 1) {
+ disables &= ~REG_GENMASK8(1, 0);
+ disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
}
- /* disable MLs */
- intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
- l0t1, MB_WRITE_COMMITTED);
- intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
- l0t2, MB_WRITE_COMMITTED);
- intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
- l1t1, MB_WRITE_COMMITTED);
- intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
- l1t2, MB_WRITE_COMMITTED);
+ /* TODO: DP-alt MFD case where only one PHY lane should be programmed.
*/
+ for (i = 0; i < 4; i++) {
+ int tx = i % 2 + 1;
+ u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
+
+ intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
+ CONTROL2_DISABLE_SINGLE_TX,
+ disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX :
0,
+ MB_WRITE_COMMITTED);
+ }
if (intel_is_c10phy(i915, intel_port_to_
[Intel-gfx] [PATCH v2 1/4] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
There are more parts of C10/C20 programming that need to take owned
lanes into account. Define the function intel_cx0_get_owned_lane_mask()
and use it. There will be new users of that function in upcoming
changes.
BSpec: 64539
Reviewed-by: Mika Kahola
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 44
1 file changed, 27 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1b00ef2c6185..b903ceb0b56a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -46,6 +46,22 @@ static int lane_mask_to_lane(u8 lane_mask)
return ilog2(lane_mask);
}
+static u8 intel_cx0_get_owned_lane_mask(struct drm_i915_private *i915,
+ struct intel_encoder *encoder)
+{
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+ if (!intel_tc_port_in_dp_alt_mode(dig_port))
+ return INTEL_CX0_BOTH_LANES;
+
+ /*
+* In DP-alt with pin assignment D, only PHY lane 0 is owned
+* by display and lane 1 is owned by USB.
+*/
+ return intel_tc_port_fia_max_lane_count(dig_port) > 2
+ ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
+}
+
static void
assert_dc_off(struct drm_i915_private *i915)
{
@@ -2534,17 +2550,15 @@ static void intel_cx0_phy_lane_reset(struct
drm_i915_private *i915,
{
enum port port = encoder->port;
enum phy phy = intel_port_to_phy(i915, port);
- bool both_lanes =
intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2;
- u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 :
- INTEL_CX0_LANE0;
- u32 lane_pipe_reset = both_lanes ?
- XELPDP_LANE_PIPE_RESET(0) |
- XELPDP_LANE_PIPE_RESET(1) :
- XELPDP_LANE_PIPE_RESET(0);
- u32 lane_phy_current_status = both_lanes ?
- XELPDP_LANE_PHY_CURRENT_STATUS(0) |
- XELPDP_LANE_PHY_CURRENT_STATUS(1) :
- XELPDP_LANE_PHY_CURRENT_STATUS(0);
+ u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
+ u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;
+ u32 lane_pipe_reset = owned_lane_mask == INTEL_CX0_BOTH_LANES
+ ? XELPDP_LANE_PIPE_RESET(0) |
XELPDP_LANE_PIPE_RESET(1)
+ : XELPDP_LANE_PIPE_RESET(0);
+ u32 lane_phy_current_status = owned_lane_mask == INTEL_CX0_BOTH_LANES
+ ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) |
+ XELPDP_LANE_PHY_CURRENT_STATUS(1))
+ : XELPDP_LANE_PHY_CURRENT_STATUS(0);
if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
XELPDP_PORT_BUF_SOC_PHY_READY,
@@ -2564,15 +2578,11 @@ static void intel_cx0_phy_lane_reset(struct
drm_i915_private *i915,
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
-intel_cx0_get_pclk_refclk_request(both_lanes ?
- INTEL_CX0_BOTH_LANES :
- INTEL_CX0_LANE0),
+intel_cx0_get_pclk_refclk_request(owned_lane_mask),
intel_cx0_get_pclk_refclk_request(lane_mask));
if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
-
intel_cx0_get_pclk_refclk_ack(both_lanes ?
-
INTEL_CX0_BOTH_LANES :
-
INTEL_CX0_LANE0),
+
intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
intel_cx0_get_pclk_refclk_ack(lane_mask),
XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0,
NULL))
drm_warn(&i915->drm, "PHY %c failed to request refclk after
%dus.\n",
--
2.41.0
[Intel-gfx] [PATCH v2 0/4] Fix C10/C20 implementation w.r.t. owned PHY lanes
While 619a06dba6fa ("drm/i915/mtl: Reset only one lane in case of MFD")
fixes the problem for lane reset logic, there are also more parts of the
implementation that need to take owned PHY lanes into consideration.
This series provides fixes for such places. The changes to the logic
have been tested on a machine with a Type-C connection in DP-Alt mode
using pin assignment D. In that mode, only PHY lane 0 is owned by
display and, without these fixes, we get message bus timeout errors
because we try to perform reads/writes on registers for the not-owned
PHY.
v2:
- Make condition for selecing PHY lane mask more clear in patch #2.
(Jani)
Gustavo Sousa (4):
drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
drm/i915: Simplify intel_cx0_program_phy_lane() with loop
drm/i915/cx0: Enable/disable TX only for owned PHY lanes
drm/i915/cx0: Program vswing only for owned lanes
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 155 ---
1 file changed, 66 insertions(+), 89 deletions(-)
--
2.41.0
Re: [Intel-gfx] [PATCH] drm/i915/vdsc: Fix first_line_bpg_offset calculation
> > On Fri, 04 Aug 2023, Suraj Kandpal wrote: > > On checking DSC1.1 Errata and DSC 1.2 spec the current formula we were > > using was incorrect to calculate first_line_bpg_offset. > > The new fixed formula is derived from C model. > > > > --v2 > > -Use clamp function in linux/minmax.h [Ankit] > > > > --v3 > > -remove linux/minmax.h header > > > > Signed-off-by: Suraj Kandpal > > Reviewed-by: Ankit Nautiyal > > Should this be: > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9102 > Hi Jani, Actually this does not close the issue when we were looking into this issue we found this discrepancy between cmodel and our code fixed it and hoped it would even fix the above issue but it seems the first_line_bpg_offset value clamps to 14 now instead of 12 which would be required in the above bug to work. I am actually looking for your input on another patch I have floated that fixes this issue. I have added the conditional for first_line_bpg_offset to be 12 incase dsc version is 1.1 and made It dsi but not sure if that is the right approach, had to do this as it seems some panels were made with the first DSC 1.1 spec where first_line_bpg_offset recommended value was 12 in mind but then this was changed in the Errata more info in the patch link below https://patchwork.freedesktop.org/series/122108/ Regards, Suraj Kandpal > > --- > > drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +--- > > 1 file changed, 9 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > > b/drivers/gpu/drm/i915/display/intel_vdsc.c > > index 9d76c2756784..e4c395b4dc46 100644 > > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > > @@ -80,13 +80,19 @@ calculate_rc_params(struct drm_dsc_config > *vdsc_cfg) > > int bpc = vdsc_cfg->bits_per_component; > > int bpp = vdsc_cfg->bits_per_pixel >> 4; > > int qp_bpc_modifier = (bpc - 8) * 2; > > + int uncompressed_bpg_rate; > > + int first_line_bpg_offset; > > u32 res, buf_i, bpp_i; > > > > if (vdsc_cfg->slice_height >= 8) > > - vdsc_cfg->first_line_bpg_offset = > > - 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg- > >slice_height - 8)), 100); > > + first_line_bpg_offset = > > + 12 + (9 * min(34, vdsc_cfg->slice_height - 8)) / 100; > > else > > - vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - > 1); > > + first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); > > + > > + uncompressed_bpg_rate = (3 * bpc + (vdsc_cfg->convert_rgb ? 0 : 2)) > * 3; > > + vdsc_cfg->first_line_bpg_offset = clamp(first_line_bpg_offset, 0, > > + uncompressed_bpg_rate - 3 * > bpp); > > > > /* > > * According to DSC 1.2 spec in Section 4.1 if native_420 is set: > > -- > Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH] drm/i915/dsi: Explicit first_line_bpg_offset assignment for DSI
Assign explicit value of 12 at 8bpp as per Table E2 of DSC 1.1 for DSI panels even though we already use calculations from CModel for first_line_bpg_offset. The reason being some DSI monitors may have not have added the change in errata for the calculation of first_line_bpg_offset. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9102 Signed-off-by: Suraj Kandpal Tested-by: William Tseng --- drivers/gpu/drm/i915/display/icl_dsi.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index ad6488e9c2b2..4646e00187c1 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1586,6 +1586,11 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, if (ret) return ret; + /* From Table E-2 in DSC 1.1*/ + if (vdsc_cfg->dsc_version_minor == 1 && + vdsc_cfg->bits_per_pixel == 128) + vdsc_cfg->first_line_bpg_offset = 12; + /* DSI specific sanity checks on the common code */ drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); -- 2.25.1
[Intel-gfx] [PATCH] video/hdmi: convert *_infoframe_init() functions to void
Four hdmi_*_infoframe_init() functions that initialize different
types of hdmi infoframes only return the default 0 value, contrary to
their descriptions. Yet these functions are still unnecessarily checked
against possible errors in case of failure.
Remove redundant error checks in calls to following functions:
- hdmi_spd_infoframe_init
- hdmi_audio_infoframe_init
- hdmi_vendor_infoframe_init
- hdmi_drm_infoframe_init
Also, convert these functions to 'void' and fix their descriptions.
Fixes: 2c676f378edb ("[media] hdmi: added unpack and logging functions for
InfoFrames")
Signed-off-by: Nikita Zhandarovich
---
drivers/gpu/drm/display/drm_hdmi_helper.c | 5 +---
drivers/gpu/drm/drm_edid.c| 5 +---
drivers/gpu/drm/i915/display/intel_hdmi.c | 7 ++---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 14 ++
drivers/gpu/drm/radeon/r600_hdmi.c| 6 +---
drivers/gpu/drm/sti/sti_hdmi.c| 6 +---
drivers/gpu/drm/tegra/hdmi.c | 7 +
drivers/gpu/drm/tegra/sor.c | 6 +---
drivers/gpu/drm/vc4/vc4_hdmi.c| 7 +
drivers/video/hdmi.c | 46 ++-
include/linux/hdmi.h | 10 +++
11 files changed, 25 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_hdmi_helper.c
b/drivers/gpu/drm/display/drm_hdmi_helper.c
index faf5e9efa7d3..ce7038a3a183 100644
--- a/drivers/gpu/drm/display/drm_hdmi_helper.c
+++ b/drivers/gpu/drm/display/drm_hdmi_helper.c
@@ -27,7 +27,6 @@ int drm_hdmi_infoframe_set_hdr_metadata(struct
hdmi_drm_infoframe *frame,
{
struct drm_connector *connector;
struct hdr_output_metadata *hdr_metadata;
- int err;
if (!frame || !conn_state)
return -EINVAL;
@@ -47,9 +46,7 @@ int drm_hdmi_infoframe_set_hdr_metadata(struct
hdmi_drm_infoframe *frame,
connector->hdr_sink_metadata.hdmi_type1.eotf))
DRM_DEBUG_KMS("Unknown EOTF %d\n",
hdr_metadata->hdmi_metadata_type1.eotf);
- err = hdmi_drm_infoframe_init(frame);
- if (err < 0)
- return err;
+ hdmi_drm_infoframe_init(frame);
frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index e0dbd9140726..d4933f215675 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -7235,7 +7235,6 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct
hdmi_vendor_infoframe *frame,
*/
bool has_hdmi_infoframe = connector ?
connector->display_info.has_hdmi_infoframe : false;
- int err;
if (!frame || !mode)
return -EINVAL;
@@ -7243,9 +7242,7 @@ drm_hdmi_vendor_infoframe_from_display_mode(struct
hdmi_vendor_infoframe *frame,
if (!has_hdmi_infoframe)
return -EINVAL;
- err = hdmi_vendor_infoframe_init(frame);
- if (err < 0)
- return err;
+ hdmi_vendor_infoframe_init(frame);
/*
* Even if it's not absolutely necessary to send the infoframe
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7ac5e6c5e00d..8b58127bca37 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -763,12 +763,9 @@ intel_hdmi_compute_spd_infoframe(struct intel_encoder
*encoder,
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
if (IS_DGFX(i915))
- ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
+ hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
else
- ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
-
- if (drm_WARN_ON(encoder->base.dev, ret))
- return false;
+ hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
frame->sdi = HDMI_SPD_SDI_PC;
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 0a8e0a13f516..75899e4a011f 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -995,12 +995,7 @@ static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi
*hdmi,
u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
ssize_t err;
- err = hdmi_spd_infoframe_init(&frame, vendor, product);
- if (err < 0) {
- dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
- err);
- return err;
- }
+ hdmi_spd_infoframe_init(&frame, vendor, product);
err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
if (err < 0) {
@@ -1018,12 +1013,7 @@ static int mtk_hdmi_setup_audio_infoframe(struct
mtk_hdmi *hdmi)
u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HD
Re: [Intel-gfx] [PATCH] video/hdmi: convert *_infoframe_init() functions to void
Hello,
On 8/10/23 01:13, Maxime Ripard wrote:
> Hi,
>
> On Tue, Aug 08, 2023 at 11:02:45AM -0700, Nikita Zhandarovich wrote:
>> Four hdmi_*_infoframe_init() functions that initialize different
>> types of hdmi infoframes only return the default 0 value, contrary to
>> their descriptions. Yet these functions are still unnecessarily checked
>> against possible errors in case of failure.
>>
>> Remove redundant error checks in calls to following functions:
>> - hdmi_spd_infoframe_init
>> - hdmi_audio_infoframe_init
>> - hdmi_vendor_infoframe_init
>> - hdmi_drm_infoframe_init
>> Also, convert these functions to 'void' and fix their descriptions.
>
> I'm not sure what value it actually adds. None of them return any
> errors, but very well might if we started to be a bit serious about it.
>
> Since the error handling is already there, then I'd rather leave it
> there.
There is definitely no particular urgency to this change.
Since these functions don't perform anything complex and aren't updated
regularly, my main goal was to remove unnecessary (at the moment) checks
and fix up their somewhat misleading descriptions. Cleaning up, in other
words. But I understand your point of view.
If you don't think this patch is warranted at this point, I totally
understand.
>
>> Fixes: 2c676f378edb ("[media] hdmi: added unpack and logging functions for
>> InfoFrames")
>
> I'm confused about that part. What does it fix exactly?
>
> Maxime
I added the 'Fixes:' tag mostly as a requirement for patch's
description. Once again, it doesn't "fix" anything broken as much as it
cleans up stuff.
Best regards,
Nikita
[Intel-gfx] [REGRESSION] HDMI connector detection broken in 6.3 on Intel(R) Celeron(R) N3060 integrated graphics
The following is a copy an issue I posted to drm/i915 gitlab [1] two
months ago. I repost it to the mailing lists in hope that it will help
the right people pay attention to it.
After kernel upgrade from 6.2.13 to 6.3 HDMI connector detection is
broken for me. Issue is 100% reproducible:
1. Start system as usual with HDMI connected.
2. Disconnect HDMI
3. Connect HDMI back
4. Get "no signal" on display, connector status in sysfs is disconnected
Curiously, running xrandr over ssh like
ssh qnap251.local env DISPLAY=:0 xrandr
makes display come back. drm-tip tip is affected as well (last test
2023-08-02).
Bisecting points at a4e771729a51 ("drm/probe_helper: sort out poll_running vs
poll_enabled").
Reverting that commit on top of 6.3 fixes the issue for me.
System information:
* System architecture: x86_64
* Kernel version: 6.3.arch1
* Linux distribution: Arch Linux
* Machine: QNAP TS-251A, CPU: Intel(R) Celeron(R) CPU N3060 @ 1.60GHz
* Display connector: single HDMI display
* dmesg with debug information (captured on drm-tip, following above 4 steps):
[2]
* xrandr output:
Screen 0: minimum 320 x 200, current 1920 x 1080, maximum 16384 x 16384
DP-1 disconnected (normal left inverted right x axis y axis)
HDMI-1 connected primary 1920x1080+0+0 (normal left inverted right x axis y
axis) 708mm x 398mm
1920x1080 60.00*+ 50.0059.9430.0025.0024.00
29.9723.98
1920x1080i60.0050.0059.94
1360x768 59.80
1280x768 60.35
1280x720 60.0050.0059.94
1024x768 75.0370.0760.00
832x624 74.55
800x600 75.0060.32
720x576 50.00
720x480 60.0059.94
640x480 75.0060.0059.94
720x400 70.08
DP-2 disconnected (normal left inverted right x axis y axis)
HDMI-2 disconnected (normal left inverted right x axis y axis)```
I'm willing to provide additional information and/or test fixes.
[1] https://gitlab.freedesktop.org/drm/intel/-/issues/8451
[2]
https://gitlab.freedesktop.org/drm/intel/uploads/fda7aff0b13ef20962856c2c7be51544/dmesg.txt
#regzbot introduced: a4e771729a51
--
Best regards,
Mikhail Rudenko
Re: [Intel-gfx] [PATCH] drm/i915: Fix Kconfig error for CONFIG_DRM_I915
On Mon, Aug 14, 2023 at 10:26:45AM +0300, Jani Nikula wrote: > On Sat, 12 Aug 2023, Wang Jinchao wrote: > > When CONFIG_DRM_I915 is set to 'y' and CONFIG_BACKLIGHT_CLASS_DEVICE > > is set to 'm', we encountered an ld.lld error during the build process: > > > > ld.lld: error: undefined symbol: backlight_device_get_by_name > > >>> referenced by intel_backlight.c:955 > > >>> vmlinux.o:(intel_backlight_device_register) > > > > ld.lld: error: undefined symbol: backlight_device_register > > >>> referenced by intel_backlight.c:971 > > >>> vmlinux.o:(intel_backlight_device_register) > > > > ld.lld: error: undefined symbol: backlight_device_unregister > > >>> referenced by intel_backlight.c:999 > > >>> vmlinux.o:(intel_backlight_device_unregister) > > > > This issue occurred because intel_backlight_device_register and > > intel_backlight_device_unregister were enclosed within > > However, according to Kconfig, CONFIG_DRM_I915 will select > > BACKLIGHT_CLASS_DEVICE only if ACPI is enabled. > > This led to an error, which can be resolved by removing the > > conditional statements related to ACPI. > > The real fix is to use > > depends on BACKLIGHT_CLASS_DEVICE || BACKLIGHT_CLASS_DEVICE=n it works. > > but in order to do that, you need to change a lot of places to depend Why, what are the other places? > on, not select BACKLIGHT_CLASS_DEVICE, because otherwise you end up with got it. > other dependency issues. > > BR, > Jani. > > > > > Signed-off-by: Wang Jinchao > > --- > > drivers/gpu/drm/i915/Kconfig | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig > > index 01b5a8272a27..5003de921bf7 100644 > > --- a/drivers/gpu/drm/i915/Kconfig > > +++ b/drivers/gpu/drm/i915/Kconfig > > @@ -24,7 +24,7 @@ config DRM_I915 > > select IRQ_WORK > > # i915 depends on ACPI_VIDEO when ACPI is enabled > > # but for select to work, need to select ACPI_VIDEO's dependencies, ick > > - select BACKLIGHT_CLASS_DEVICE if ACPI > > + select BACKLIGHT_CLASS_DEVICE > > select INPUT if ACPI > > select X86_PLATFORM_DEVICES if ACPI > > select ACPI_WMI if ACPI > > -- > Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH v2] drm/i915: Fix Kconfig error for CONFIG_DRM_I915
When CONFIG_DRM_I915 is set to 'y' and CONFIG_BACKLIGHT_CLASS_DEVICE is set to 'm', we encountered an ld.lld error during the build process: ld.lld: error: undefined symbol: backlight_device_get_by_name >>> referenced by intel_backlight.c:955 >>> vmlinux.o:(intel_backlight_device_register) ld.lld: error: undefined symbol: backlight_device_register >>> referenced by intel_backlight.c:971 >>> vmlinux.o:(intel_backlight_device_register) ld.lld: error: undefined symbol: backlight_device_unregister >>> referenced by intel_backlight.c:999 >>> vmlinux.o:(intel_backlight_device_unregister) This issue occurred because intel_backlight_device_register and intel_backlight_device_unregister were enclosed within \#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) and #endif directives. However, according to Kconfig, CONFIG_DRM_I915 will select BACKLIGHT_CLASS_DEVICE only if ACPI is enabled. This led to an error, which can be resolved by removing the conditional statements related to ACPI. v2: Add a line starting with # Signed-off-by: Wang Jinchao --- drivers/gpu/drm/i915/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 01b5a8272a27..5003de921bf7 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -24,7 +24,7 @@ config DRM_I915 select IRQ_WORK # i915 depends on ACPI_VIDEO when ACPI is enabled # but for select to work, need to select ACPI_VIDEO's dependencies, ick - select BACKLIGHT_CLASS_DEVICE if ACPI + select BACKLIGHT_CLASS_DEVICE select INPUT if ACPI select X86_PLATFORM_DEVICES if ACPI select ACPI_WMI if ACPI -- 2.40.0
[Intel-gfx] [PATCH] drm/i915/gmch: fix build error var set but not used
When CONFIG_PNP is not defined, i915 will fail to compile with error bellow:
drivers/gpu/drm/i915/soc/intel_gmch.c:43:13: error: variable
‘mchbar_addr’ set but not used
Fix it by surrounding variable declaration and assignment with ifdef
Signed-off-by: Wang Jinchao
---
drivers/gpu/drm/i915/soc/intel_gmch.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_gmch.c
b/drivers/gpu/drm/i915/soc/intel_gmch.c
index 6d0204942f7a..d2c442b0b4eb 100644
--- a/drivers/gpu/drm/i915/soc/intel_gmch.c
+++ b/drivers/gpu/drm/i915/soc/intel_gmch.c
@@ -38,16 +38,17 @@ intel_alloc_mchbar_resource(struct drm_i915_private *i915)
{
int reg = GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp_lo, temp_hi = 0;
- u64 mchbar_addr;
int ret;
-
+#ifdef CONFIG_PNP
+ u64 mchbar_addr;
+#endif
if (GRAPHICS_VER(i915) >= 4)
pci_read_config_dword(i915->gmch.pdev, reg + 4, &temp_hi);
pci_read_config_dword(i915->gmch.pdev, reg, &temp_lo);
- mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
/* If ACPI doesn't have it, assume we need to allocate it ourselves */
#ifdef CONFIG_PNP
+ mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
if (mchbar_addr &&
pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
return 0;
--
2.40.0
Re: [Intel-gfx] [REGRESSION] HDMI connector detection broken in 6.3 on Intel(R) Celeron(R) N3060 integrated graphics
Hi, Thorsten! On 2023-08-11 at 08:45 +02, Thorsten Leemhuis wrote: > [CCing the i915 maintainers and the dri maintainers] > > Hi, Thorsten here, the Linux kernel's regression tracker. > > On 10.08.23 21:33, Mikhail Rudenko wrote: >> The following is a copy an issue I posted to drm/i915 gitlab [1] two >> months ago. I repost it to the mailing lists in hope that it will help >> the right people pay attention to it. > > Thx for your report. Wonder why Dmitry (who authored a4e771729a51) or > Thomas (who committed it) it didn't look into this, but maybe the i915 > devs didn't forward the report to them. > > Let's see if these mails help. Just wondering: does reverting > a4e771729a51 from 6.5-rc5 or drm-tip help as well? I've redone my tests with 6.5-rc5, and here are the results: (1) 6.5-rc5 -> still affected (2) 6.5-rc5 + revert a4e771729a51 -> not affected (3) 6.5-rc5 + two patches [1][2] suggested on i915 gitlab by @ideak -> not affected (!) Should we somehow tell regzbot about (3)? > BTW, there was an earlier report about a problem with a4e771729a51 that > afaics was never addressed, but it might be unrelated. > > https://lore.kernel.org/all/20230328023129.3596968-1-zhouzong...@kylinos.cn/ > > Ciao, Thorsten [1] https://patchwork.freedesktop.org/patch/548590/?series=121050&rev=1 [2] https://patchwork.freedesktop.org/patch/548591/?series=121050&rev=1 -- Best regards, Mikhail Rudenko
Re: [Intel-gfx] [PATCH] drm/i915: Fix Kconfig error for CONFIG_DRM_I915
On Mon, 14 Aug 2023, Wang Jinchao wrote: > On Mon, Aug 14, 2023 at 10:26:45AM +0300, Jani Nikula wrote: >> On Sat, 12 Aug 2023, Wang Jinchao wrote: >> > When CONFIG_DRM_I915 is set to 'y' and CONFIG_BACKLIGHT_CLASS_DEVICE >> > is set to 'm', we encountered an ld.lld error during the build process: >> > >> >ld.lld: error: undefined symbol: backlight_device_get_by_name >> >>>> referenced by intel_backlight.c:955 >> >>>> vmlinux.o:(intel_backlight_device_register) >> > >> >ld.lld: error: undefined symbol: backlight_device_register >> >>>> referenced by intel_backlight.c:971 >> >>>> vmlinux.o:(intel_backlight_device_register) >> > >> >ld.lld: error: undefined symbol: backlight_device_unregister >> >>>> referenced by intel_backlight.c:999 >> >>>> vmlinux.o:(intel_backlight_device_unregister) >> > >> > This issue occurred because intel_backlight_device_register and >> > intel_backlight_device_unregister were enclosed within >> > However, according to Kconfig, CONFIG_DRM_I915 will select >> > BACKLIGHT_CLASS_DEVICE only if ACPI is enabled. >> > This led to an error, which can be resolved by removing the >> > conditional statements related to ACPI. >> >> The real fix is to use >> >> depends on BACKLIGHT_CLASS_DEVICE || BACKLIGHT_CLASS_DEVICE=n > it works. >> >> but in order to do that, you need to change a lot of places to depend > Why, what are the other places? Generally when you have a mixture of depends on and select on a kconfig symbol, you'll eventually end up with dependency problems. BR, Jani. >> on, not select BACKLIGHT_CLASS_DEVICE, because otherwise you end up with > got it. >> other dependency issues. >> >> BR, >> Jani. >> >> > >> > Signed-off-by: Wang Jinchao >> > --- >> > drivers/gpu/drm/i915/Kconfig | 2 +- >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> > >> > diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig >> > index 01b5a8272a27..5003de921bf7 100644 >> > --- a/drivers/gpu/drm/i915/Kconfig >> > +++ b/drivers/gpu/drm/i915/Kconfig >> > @@ -24,7 +24,7 @@ config DRM_I915 >> >select IRQ_WORK >> ># i915 depends on ACPI_VIDEO when ACPI is enabled >> ># but for select to work, need to select ACPI_VIDEO's dependencies, ick >> > - select BACKLIGHT_CLASS_DEVICE if ACPI >> > + select BACKLIGHT_CLASS_DEVICE >> >select INPUT if ACPI >> >select X86_PLATFORM_DEVICES if ACPI >> >select ACPI_WMI if ACPI >> >> -- >> Jani Nikula, Intel Open Source Graphics Center -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dgfx: Enable d3cold at s2idle
== Series Details == Series: drm/i915/dgfx: Enable d3cold at s2idle URL : https://patchwork.freedesktop.org/series/122413/ State : success == Summary == CI Bug Log - changes from CI_DRM_13515 -> Patchwork_122413v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/index.html Participating hosts (41 -> 39) -- Missing(2): bat-dg2-8 fi-snb-2520m Known issues Here are the changes found in Patchwork_122413v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0@lmem0: - bat-dg2-9: [PASS][1] -> [INCOMPLETE][2] ([i915#8011]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: [PASS][3] -> [DMESG-FAIL][4] ([i915#7059]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [PASS][5] -> [DMESG-WARN][6] ([i915#7699]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/bat-dg2-11/igt@i915_selftest@l...@migrate.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [PASS][7] -> [DMESG-FAIL][8] ([i915#8497]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/bat-mtlp-8/igt@i915_selftest@l...@requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@slpc: - bat-mtlp-8: [PASS][9] -> [DMESG-WARN][10] ([i915#6367]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/bat-mtlp-8/igt@i915_selftest@l...@slpc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/bat-mtlp-8/igt@i915_selftest@l...@slpc.html - bat-rpls-1: NOTRUN -> [DMESG-WARN][11] ([i915#6367]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html * igt@i915_suspend@basic-s3-without-i915: - bat-rpls-1: NOTRUN -> [ABORT][12] ([i915#6687] / [i915#7978] / [i915#8668]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][13] ([i915#1845] / [i915#5354]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1: - bat-rplp-1: [PASS][14] -> [ABORT][15] ([i915#8442] / [i915#8668]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-d-edp-1.html Possible fixes * igt@gem_exec_suspend@basic-s3@smem: - fi-rkl-11600: [FAIL][16] ([fdo#103375]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html * igt@gem_tiled_fence_blits@basic: - fi-kbl-soraka: [INCOMPLETE][18] -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/fi-kbl-soraka/igt@gem_tiled_fence_bl...@basic.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/fi-kbl-soraka/igt@gem_tiled_fence_bl...@basic.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [DMESG-FAIL][20] ([i915#5334] / [i915#7872]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_mocs: - bat-rpls-2: [DMESG-FAIL][22] ([i915#7059]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/bat-rpls-2/igt@i915_selftest@live@gt_mocs.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122413v1/bat-rpls-2/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@mman: - bat-rpls-2: [TIMEOUT][24
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dgfx: Enable d3cold at s2idle
== Series Details == Series: drm/i915/dgfx: Enable d3cold at s2idle URL : https://patchwork.freedesktop.org/series/122413/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dgfx: Enable d3cold at s2idle
== Series Details == Series: drm/i915/dgfx: Enable d3cold at s2idle URL : https://patchwork.freedesktop.org/series/122413/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
Re: [Intel-gfx] [PATCH] drm/i915/vdsc: Fix first_line_bpg_offset calculation
On Fri, 04 Aug 2023, Suraj Kandpal wrote: > On checking DSC1.1 Errata and DSC 1.2 spec the current formula > we were using was incorrect to calculate first_line_bpg_offset. > The new fixed formula is derived from C model. > > --v2 > -Use clamp function in linux/minmax.h [Ankit] > > --v3 > -remove linux/minmax.h header > > Signed-off-by: Suraj Kandpal > Reviewed-by: Ankit Nautiyal Should this be: Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9102 > --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 9d76c2756784..e4c395b4dc46 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -80,13 +80,19 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg) > int bpc = vdsc_cfg->bits_per_component; > int bpp = vdsc_cfg->bits_per_pixel >> 4; > int qp_bpc_modifier = (bpc - 8) * 2; > + int uncompressed_bpg_rate; > + int first_line_bpg_offset; > u32 res, buf_i, bpp_i; > > if (vdsc_cfg->slice_height >= 8) > - vdsc_cfg->first_line_bpg_offset = > - 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - > 8)), 100); > + first_line_bpg_offset = > + 12 + (9 * min(34, vdsc_cfg->slice_height - 8)) / 100; > else > - vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - > 1); > + first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1); > + > + uncompressed_bpg_rate = (3 * bpc + (vdsc_cfg->convert_rgb ? 0 : 2)) * 3; > + vdsc_cfg->first_line_bpg_offset = clamp(first_line_bpg_offset, 0, > + uncompressed_bpg_rate - 3 * > bpp); > > /* >* According to DSC 1.2 spec in Section 4.1 if native_420 is set: -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH] drm/i915/dgfx: Enable d3cold at s2idle
System wide suspend already has support for lmem save/restore during
suspend therefore enabling d3cold for s2idle and keepng it disable for
runtime PM.(Refer below commit for d3cold runtime PM disable justification)
'commit 66eb93e71a7a ("drm/i915/dgfx: Keep PCI autosuspend control
'on' by default on all dGPU")'
It will reduce the DG2 Card power consumption to ~0 Watt
for s2idle power KPI.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8755
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_driver.c | 33 --
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index b870c0df081a..ec4d26b3c17c 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -443,7 +443,6 @@ static int i915_pcode_init(struct drm_i915_private *i915)
static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
{
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
- struct pci_dev *root_pdev;
int ret;
if (i915_inject_probe_failure(dev_priv))
@@ -557,15 +556,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
intel_bw_init_hw(dev_priv);
- /*
-* FIXME: Temporary hammer to avoid freezing the machine on our DGFX
-* This should be totally removed when we handle the pci states properly
-* on runtime PM and on s2idle cases.
-*/
- root_pdev = pcie_find_root_port(pdev);
- if (root_pdev)
- pci_d3cold_disable(root_pdev);
-
return 0;
err_opregion:
@@ -591,7 +581,6 @@ static int i915_driver_hw_probe(struct drm_i915_private
*dev_priv)
static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
{
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
- struct pci_dev *root_pdev;
i915_perf_fini(dev_priv);
@@ -599,10 +588,6 @@ static void i915_driver_hw_remove(struct drm_i915_private
*dev_priv)
if (pdev->msi_enabled)
pci_disable_msi(pdev);
-
- root_pdev = pcie_find_root_port(pdev);
- if (root_pdev)
- pci_d3cold_enable(root_pdev);
}
/**
@@ -1519,6 +1504,8 @@ static int intel_runtime_suspend(struct device *kdev)
{
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct pci_dev *root_pdev;
struct intel_gt *gt;
int ret, i;
@@ -1570,6 +1557,15 @@ static int intel_runtime_suspend(struct device *kdev)
drm_err(&dev_priv->drm,
"Unclaimed access detected prior to suspending\n");
+ /*
+* FIXME: Temporary hammer to avoid freezing the machine on our DGFX
+* This should be totally removed when we handle the pci states properly
+* on runtime PM.
+*/
+ root_pdev = pcie_find_root_port(pdev);
+ if (root_pdev)
+ pci_d3cold_disable(root_pdev);
+
rpm->suspended = true;
/*
@@ -1608,6 +1604,8 @@ static int intel_runtime_resume(struct device *kdev)
{
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct pci_dev *root_pdev;
struct intel_gt *gt;
int ret, i;
@@ -1621,6 +1619,11 @@ static int intel_runtime_resume(struct device *kdev)
intel_opregion_notify_adapter(dev_priv, PCI_D0);
rpm->suspended = false;
+
+ root_pdev = pcie_find_root_port(pdev);
+ if (root_pdev)
+ pci_d3cold_enable(root_pdev);
+
if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
drm_dbg(&dev_priv->drm,
"Unclaimed access during suspend, bios?\n");
--
2.25.1
Re: [Intel-gfx] [PATCH v3 4/9] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
On Fri, 11 Aug 2023, Matt Roper wrote:
> On Fri, Aug 11, 2023 at 10:32:14AM +0300, Jani Nikula wrote:
>> On Thu, 10 Aug 2023, Matt Roper wrote:
>> > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
>> > of these workarounds are actually tied to MTL as a platform; they only
>> > relate to the Xe_LPG graphics IP, regardless of what platform it appears
>> > in. At the moment MTL is the only platform that uses Xe_LPG with IP
>> > versions 12.70 and 12.71, but we can't count on this being true in the
>> > future. Switch these to use a new IS_GFX_GT_IP_STEP() macro instead
>> > that is purely based on IP version. IS_GFX_GT_IP_STEP() is also
>> > GT-based rather than device-based, which will help prevent mistakes
>> > where we accidentally try to apply Xe_LPG graphics workarounds to the
>> > Xe_LPM+ media GT and vice-versa.
>> >
>> > v2:
>> > - Switch to a more generic and shorter IS_GT_IP_STEP macro that can be
>> >used for both graphics and media IP (and any other kind of GTs that
>> >show up in the future).
>> > v3:
>> > - Switch back to long-form IS_GFX_GT_IP_STEP macro. (Jani)
>> > - Move macro to intel_gt.h. (Andi)
>> >
>> > Cc: Gustavo Sousa
>> > Cc: Tvrtko Ursulin
>> > Cc: Andi Shyti
>> > Cc: Jani Nikula
>> > Signed-off-by: Matt Roper
>> > ---
>> > .../drm/i915/display/skl_universal_plane.c| 5 +-
>> > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 11 ++--
>> > drivers/gpu/drm/i915/gt/intel_gt.h| 20 +++
>> > drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 7 ++-
>> > drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
>> > drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
>> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 52 ++-
>> > drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +-
>> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
>> > drivers/gpu/drm/i915/i915_drv.h | 4 --
>> > 10 files changed, 64 insertions(+), 45 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> > index ffc15d278a39..d557ecd4e1eb 100644
>> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> > @@ -20,6 +20,7 @@
>> > #include "skl_scaler.h"
>> > #include "skl_universal_plane.h"
>> > #include "skl_watermark.h"
>> > +#include "gt/intel_gt.h"
>> > #include "pxp/intel_pxp.h"
>> >
>> > static const u32 skl_plane_formats[] = {
>> > @@ -2169,8 +2170,8 @@ static bool skl_plane_has_rc_ccs(struct
>> > drm_i915_private *i915,
>> > enum pipe pipe, enum plane_id plane_id)
>> > {
>> >/* Wa_14017240301 */
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> > + if (IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> > + IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
>> >return false;
>> >
>> >/* Wa_22011186057 */
>> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> > b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> > index a4ff55aa5e55..6187b25b67ab 100644
>> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> > @@ -4,9 +4,9 @@
>> > */
>> >
>> > #include "gen8_engine_cs.h"
>> > -#include "i915_drv.h"
>> > #include "intel_engine_regs.h"
>> > #include "intel_gpu_commands.h"
>> > +#include "intel_gt.h"
>> > #include "intel_lrc.h"
>> > #include "intel_ring.h"
>> >
>> > @@ -226,8 +226,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs
>> > *engine, u32 *cs)
>> > static int mtl_dummy_pipe_control(struct i915_request *rq)
>> > {
>> >/* Wa_14016712196 */
>> > - if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
>> > + if (IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0)
>> > ||
>> > + IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0,
>> > STEP_B0)) {
>> >u32 *cs;
>> >
>> >/* dummy PIPE_CONTROL + depth flush */
>> > @@ -799,6 +799,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct
>> > i915_request *rq, u32 *cs)
>> > u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>> > {
>> >struct drm_i915_private *i915 = rq->i915;
>> > + struct intel_gt *gt = rq->engine->gt;
>> >u32 flags = (PIPE_CONTROL_CS_STALL |
>> > PIPE_CONTROL_TLB_INVALIDATE |
>> > PIPE_CONTROL_TILE_CACHE_FLUSH |
>> > @@ -809,8 +810,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct
>> > i915_request *rq, u32 *cs)
>> > PIPE_CONTROL_FLUSH_ENABLE);
>> >
>> >/* Wa_14016712196 */
>> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>> > + if (IS_GFX_GT_IP_STEP(gt, IP_
Re: [Intel-gfx] [PATCH 4/4] drm/i915/cx0: Program vswing only for owned lanes
> -Original Message-
> From: Sousa, Gustavo
> Sent: Wednesday, July 26, 2023 12:27 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika ; Sripada, Radhakrishna
> ; Taylor, Clinton A
>
> Subject: [PATCH 4/4] drm/i915/cx0: Program vswing only for owned lanes
>
> According to the BSpec, voltage swing programming should be done for owned
> PHY lanes. Do not program a not-owned PHY
> lane.
>
> BSpec: 74103, 74104
Reviewed-by: Mika Kahola
> Signed-off-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25 +++-
> 1 file changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 236124786631..cfb2093feb3b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -375,6 +375,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder
> *encoder,
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> const struct intel_ddi_buf_trans *trans;
> enum phy phy = intel_port_to_phy(i915, encoder->port);
> + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
> intel_wakeref_t wakeref;
> int n_entries, ln;
>
> @@ -387,13 +388,13 @@ void intel_cx0_phy_set_signal_levels(struct
> intel_encoder *encoder,
> }
>
> if (intel_is_c10phy(i915, phy)) {
> - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> + intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
> +PHY_C10_VDR_CONTROL(1),
> 0, C10_VDR_CTRL_MSGBUS_ACCESS,
> MB_WRITE_COMMITTED);
> - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CMN(3),
> + intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
> +PHY_C10_VDR_CMN(3),
> C10_CMN3_TXVBOOST_MASK,
>
> C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
> MB_WRITE_UNCOMMITTED);
> - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_TX(1),
> + intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
> +PHY_C10_VDR_TX(1),
> C10_TX1_TERMCTL_MASK,
>
> C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),
> MB_WRITE_COMMITTED);
> @@ -401,32 +402,34 @@ void intel_cx0_phy_set_signal_levels(struct
> intel_encoder *encoder,
>
> for (ln = 0; ln < crtc_state->lane_count; ln++) {
> int level = intel_ddi_level(encoder, crtc_state, ln);
> - int lane, tx;
> + int lane = ln / 2;
> + int tx = ln % 2;
> + u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
>
> - lane = ln / 2;
> - tx = ln % 2;
> + if (!(lane_mask & owned_lane_mask))
> + continue;
>
> - intel_cx0_rmw(i915, encoder->port, BIT(lane),
> PHY_CX0_VDROVRD_CTL(lane, tx, 0),
> + intel_cx0_rmw(i915, encoder->port, lane_mask,
> +PHY_CX0_VDROVRD_CTL(lane, tx, 0),
> C10_PHY_OVRD_LEVEL_MASK,
>
> C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),
> MB_WRITE_COMMITTED);
> - intel_cx0_rmw(i915, encoder->port, BIT(lane),
> PHY_CX0_VDROVRD_CTL(lane, tx, 1),
> + intel_cx0_rmw(i915, encoder->port, lane_mask,
> +PHY_CX0_VDROVRD_CTL(lane, tx, 1),
> C10_PHY_OVRD_LEVEL_MASK,
>
> C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing),
> MB_WRITE_COMMITTED);
> - intel_cx0_rmw(i915, encoder->port, BIT(lane),
> PHY_CX0_VDROVRD_CTL(lane, tx, 2),
> + intel_cx0_rmw(i915, encoder->port, lane_mask,
> +PHY_CX0_VDROVRD_CTL(lane, tx, 2),
> C10_PHY_OVRD_LEVEL_MASK,
>
> C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor),
> MB_WRITE_COMMITTED);
> }
>
> /* Write Override enables in 0xD71 */
> - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_OVRD,
> + intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_OVRD,
> 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
> MB_WRITE_COMMITTED);
>
> if (intel_is_c10phy(i915, phy))
> - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> + intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
> +PHY_C10_VDR_CONTROL(1),
> 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
>
> intel_cx0_phy_transaction_end(encoder, wakeref);
> --
> 2.41.0
Re: [Intel-gfx] [PATCH 3/4] drm/i915/cx0: Enable/disable TX only for owned PHY lanes
> -Original Message-
> From: Sousa, Gustavo
> Sent: Wednesday, July 26, 2023 12:27 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika ; Sripada, Radhakrishna
> ; Taylor, Clinton A
>
> Subject: [PATCH 3/4] drm/i915/cx0: Enable/disable TX only for owned PHY lanes
>
> Display must not enable or disable transmitters for not-owned PHY lanes.
>
> BSpec: 64539
Reviewed-by: Mika Kahola
> Signed-off-by: Gustavo Sousa
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f10ebdfd696a..236124786631 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2607,10 +2607,11 @@ static void intel_cx0_program_phy_lane(struct
> drm_i915_private *i915,
> int i;
> u8 disables;
> bool dp_alt_mode =
> intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
> + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
> enum port port = encoder->port;
>
> if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
> - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> + intel_cx0_rmw(i915, port, owned_lane_mask,
> PHY_C10_VDR_CONTROL(1), 0,
> C10_VDR_CTRL_MSGBUS_ACCESS,
> MB_WRITE_COMMITTED);
> @@ -2625,11 +2626,13 @@ static void intel_cx0_program_phy_lane(struct
> drm_i915_private *i915,
> disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
> }
>
> - /* TODO: DP-alt MFD case where only one PHY lane should be programmed.
> */
> for (i = 0; i < 4; i++) {
> int tx = i % 2 + 1;
> u8 lane_mask = i / 2 == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
>
> + if (!(owned_lane_mask & lane_mask))
> + continue;
> +
> intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
> CONTROL2_DISABLE_SINGLE_TX,
> disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX :
> 0, @@ -2637,7 +2640,7 @@ static void
> intel_cx0_program_phy_lane(struct drm_i915_private *i915,
> }
>
> if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
> - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> + intel_cx0_rmw(i915, port, owned_lane_mask,
> PHY_C10_VDR_CONTROL(1), 0,
> C10_VDR_CTRL_UPDATE_CFG,
> MB_WRITE_COMMITTED);
> --
> 2.41.0
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Swap ggtt_vma during legacy cursor update
== Series Details == Series: series starting with [1/2] drm/i915: Swap ggtt_vma during legacy cursor update URL : https://patchwork.freedesktop.org/series/122401/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13515_full -> Patchwork_122401v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_122401v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122401v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122401v1_full: ### IGT changes ### Possible regressions * igt@gem_exec_create@madvise@smem: - shard-tglu: [PASS][1] -> [ABORT][2] +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/shard-tglu-6/igt@gem_exec_create@madv...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/shard-tglu-9/igt@gem_exec_create@madv...@smem.html * igt@gem_exec_schedule@deep@ccs2: - shard-dg2: [PASS][3] -> [ABORT][4] +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/shard-dg2-11/igt@gem_exec_schedule@d...@ccs2.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/shard-dg2-10/igt@gem_exec_schedule@d...@ccs2.html * igt@gem_lmem_swapping@verify@lmem0: - shard-dg1: [PASS][5] -> [ABORT][6] +7 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/shard-dg1-14/igt@gem_lmem_swapping@ver...@lmem0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/shard-dg1-18/igt@gem_lmem_swapping@ver...@lmem0.html * igt@gem_softpin@noreloc-s3: - shard-rkl: NOTRUN -> [INCOMPLETE][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/shard-rkl-4/igt@gem_soft...@noreloc-s3.html * igt@kms_busy@extended-modeset-hang-oldfb@pipe-a: - shard-dg2: [PASS][8] -> [DMESG-WARN][9] +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/shard-dg2-10/igt@kms_busy@extended-modeset-hang-ol...@pipe-a.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/shard-dg2-10/igt@kms_busy@extended-modeset-hang-ol...@pipe-a.html * igt@kms_busy@extended-modeset-hang-oldfb@pipe-d: - shard-mtlp: [PASS][10] -> [DMESG-WARN][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/shard-mtlp-8/igt@kms_busy@extended-modeset-hang-ol...@pipe-d.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/shard-mtlp-4/igt@kms_busy@extended-modeset-hang-ol...@pipe-d.html * igt@kms_cursor_crc@cursor-offscreen-128x128@pipe-d-hdmi-a-1: - shard-tglu: [PASS][12] -> [DMESG-WARN][13] +7 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/shard-tglu-7/igt@kms_cursor_crc@cursor-offscreen-128x...@pipe-d-hdmi-a-1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/shard-tglu-8/igt@kms_cursor_crc@cursor-offscreen-128x...@pipe-d-hdmi-a-1.html * igt@kms_cursor_crc@cursor-offscreen-256x256@pipe-a-vga-1: - shard-snb: [PASS][14] -> [INCOMPLETE][15] +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/shard-snb7/igt@kms_cursor_crc@cursor-offscreen-256x...@pipe-a-vga-1.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/shard-snb2/igt@kms_cursor_crc@cursor-offscreen-256x...@pipe-a-vga-1.html * igt@kms_cursor_edge_walk@128x128-left-edge@pipe-a-hdmi-a-4: - shard-dg1: [PASS][16] -> [DMESG-WARN][17] +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/shard-dg1-16/igt@kms_cursor_edge_walk@128x128-left-e...@pipe-a-hdmi-a-4.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/shard-dg1-17/igt@kms_cursor_edge_walk@128x128-left-e...@pipe-a-hdmi-a-4.html * igt@kms_cursor_edge_walk@128x128-left-edge@pipe-c-dp-1: - shard-apl: [PASS][18] -> [DMESG-WARN][19] +9 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/shard-apl3/igt@kms_cursor_edge_walk@128x128-left-e...@pipe-c-dp-1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/shard-apl4/igt@kms_cursor_edge_walk@128x128-left-e...@pipe-c-dp-1.html * igt@kms_cursor_edge_walk@128x128-right-edge@pipe-a-hdmi-a-4: - shard-dg1: [PASS][20] -> [INCOMPLETE][21] +2 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/shard-dg1-17/igt@kms_cursor_edge_walk@128x128-right-e...@pipe-a-hdmi-a-4.html [21]: https://intel-gfx-ci.01.org/tree/drm-ti
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Swap ggtt_vma during legacy cursor update
== Series Details == Series: series starting with [1/2] drm/i915: Swap ggtt_vma during legacy cursor update URL : https://patchwork.freedesktop.org/series/122401/ State : success == Summary == CI Bug Log - changes from CI_DRM_13515 -> Patchwork_122401v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/index.html Participating hosts (41 -> 40) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_122401v1 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-guc: [PASS][1] -> [DMESG-FAIL][2] ([i915#5334] / [i915#7872]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/fi-kbl-guc/igt@i915_selftest@live@gt_heartbeat.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/fi-kbl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: [PASS][3] -> [DMESG-FAIL][4] ([i915#7059]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html - bat-mtlp-6: [PASS][5] -> [DMESG-FAIL][6] ([i915#7059]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@requests: - fi-kbl-soraka: [PASS][7] -> [ABORT][8] ([i915#7913]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/fi-kbl-soraka/igt@i915_selftest@l...@requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/fi-kbl-soraka/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@reset: - bat-rpls-2: NOTRUN -> [ABORT][9] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#8347]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/bat-rpls-2/igt@i915_selftest@l...@reset.html * igt@i915_selftest@live@slpc: - bat-mtlp-6: [PASS][10] -> [DMESG-WARN][11] ([i915#6367]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/bat-mtlp-6/igt@i915_selftest@l...@slpc.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/bat-mtlp-6/igt@i915_selftest@l...@slpc.html - bat-mtlp-8: [PASS][12] -> [DMESG-WARN][13] ([i915#6367]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/bat-mtlp-8/igt@i915_selftest@l...@slpc.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/bat-mtlp-8/igt@i915_selftest@l...@slpc.html - bat-rpls-1: NOTRUN -> [DMESG-WARN][14] ([i915#6367]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html * igt@i915_suspend@basic-s3-without-i915: - bat-rpls-1: NOTRUN -> [ABORT][15] ([i915#6687] / [i915#7978] / [i915#8668]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_setmode@basic-clone-single-crtc: - bat-rplp-1: NOTRUN -> [ABORT][16] ([i915#8260] / [i915#8668]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/bat-rplp-1/igt@kms_setm...@basic-clone-single-crtc.html Possible fixes * igt@gem_exec_suspend@basic-s3@smem: - fi-rkl-11600: [FAIL][17] ([fdo#103375]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html * igt@gem_tiled_fence_blits@basic: - fi-kbl-soraka: [INCOMPLETE][19] -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/fi-kbl-soraka/igt@gem_tiled_fence_bl...@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/fi-kbl-soraka/igt@gem_tiled_fence_bl...@basic.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: [DMESG-FAIL][21] ([i915#5334] / [i915#7872]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_mocs: - bat-rpls-2: [DMESG-FAIL][23] ([i915#7059]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13515/bat-rpls-2/igt@i915_selftest@live@gt_mocs.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122401v1/bat-rpls-2/igt@i915_selftest@live@gt_
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Swap ggtt_vma during legacy cursor update
== Series Details == Series: series starting with [1/2] drm/i915: Swap ggtt_vma during legacy cursor update URL : https://patchwork.freedesktop.org/series/122401/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Swap ggtt_vma during legacy cursor update
== Series Details == Series: series starting with [1/2] drm/i915: Swap ggtt_vma during legacy cursor update URL : https://patchwork.freedesktop.org/series/122401/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
Re: [Intel-gfx] [PATCH] drm/i915: Fix Kconfig error for CONFIG_DRM_I915
On Sat, 12 Aug 2023, Wang Jinchao wrote: > When CONFIG_DRM_I915 is set to 'y' and CONFIG_BACKLIGHT_CLASS_DEVICE > is set to 'm', we encountered an ld.lld error during the build process: > > ld.lld: error: undefined symbol: backlight_device_get_by_name > >>> referenced by intel_backlight.c:955 > >>> vmlinux.o:(intel_backlight_device_register) > > ld.lld: error: undefined symbol: backlight_device_register > >>> referenced by intel_backlight.c:971 > >>> vmlinux.o:(intel_backlight_device_register) > > ld.lld: error: undefined symbol: backlight_device_unregister > >>> referenced by intel_backlight.c:999 > >>> vmlinux.o:(intel_backlight_device_unregister) > > This issue occurred because intel_backlight_device_register and > intel_backlight_device_unregister were enclosed within > However, according to Kconfig, CONFIG_DRM_I915 will select > BACKLIGHT_CLASS_DEVICE only if ACPI is enabled. > This led to an error, which can be resolved by removing the > conditional statements related to ACPI. The real fix is to use depends on BACKLIGHT_CLASS_DEVICE || BACKLIGHT_CLASS_DEVICE=n but in order to do that, you need to change a lot of places to depend on, not select BACKLIGHT_CLASS_DEVICE, because otherwise you end up with other dependency issues. BR, Jani. > > Signed-off-by: Wang Jinchao > --- > drivers/gpu/drm/i915/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig > index 01b5a8272a27..5003de921bf7 100644 > --- a/drivers/gpu/drm/i915/Kconfig > +++ b/drivers/gpu/drm/i915/Kconfig > @@ -24,7 +24,7 @@ config DRM_I915 > select IRQ_WORK > # i915 depends on ACPI_VIDEO when ACPI is enabled > # but for select to work, need to select ACPI_VIDEO's dependencies, ick > - select BACKLIGHT_CLASS_DEVICE if ACPI > + select BACKLIGHT_CLASS_DEVICE > select INPUT if ACPI > select X86_PLATFORM_DEVICES if ACPI > select ACPI_WMI if ACPI -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH i-g-t] tests/i915_pm_freq_api: Ignore zero register value
Hi Vinay
On 8/9/2023 6:20 AM, Vinay Belgaumkar wrote:
Register read for requested_freq can return 0 when system is
in runtime_pm. Make allowance for this case.
Link: https://gitlab.freedesktop.org/drm/intel/issues/8736
Link: https://gitlab.freedesktop.org/drm/intel/issues/8989
Signed-off-by: Vinay Belgaumkar
---
tests/i915/i915_pm_freq_api.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/tests/i915/i915_pm_freq_api.c b/tests/i915/i915_pm_freq_api.c
index cf21cc936..9c71411ee 100644
--- a/tests/i915/i915_pm_freq_api.c
+++ b/tests/i915/i915_pm_freq_api.c
@@ -88,6 +88,7 @@ static void test_freq_basic_api(int dirfd, int gt)
static void test_reset(int i915, int dirfd, int gt, int count)
{
uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ);
+ uint32_t req_freq;
int fd;
for (int i = 0; i < count; i++) {
@@ -95,14 +96,18 @@ static void test_reset(int i915, int dirfd, int gt, int
count)
igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0);
igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0);
usleep(ACT_FREQ_LATENCY_US);
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
Is there anything else that can cause req_freq to be zero?
To differentiate can we assert only when runtime_status is active
(igt_get_runtime_pm_status() == IGT_RUNTIME_PM_STATUS_ACTIVE) ?
Thanks
Riana Tauro
/* Manually trigger a GT reset */
fd = igt_debugfs_gt_open(i915, gt, "reset", O_WRONLY);
igt_require(fd >= 0);
igt_ignore_warn(write(fd, "1\n", 2));
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
}
close(fd);
}
@@ -110,17 +115,22 @@ static void test_reset(int i915, int dirfd, int gt, int
count)
static void test_suspend(int i915, int dirfd, int gt)
{
uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ);
+ uint32_t req_freq;
igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0);
igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0);
usleep(ACT_FREQ_LATENCY_US);
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
/* Manually trigger a suspend */
igt_system_suspend_autoresume(SUSPEND_STATE_S3,
SUSPEND_TEST_NONE);
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
}
int i915 = -1;
