Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Reset message bus after each read/write operation (rev4)

[Kahola, Mika]

From: Patchwork 
Sent: Tuesday, October 17, 2023 5:28 AM
To: Kahola, Mika 
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for drm/i915/display: Reset message bus after 
each read/write operation (rev4)

Patch Details
Series:
drm/i915/display: Reset message bus after each read/write operation (rev4)
URL:
https://patchwork.freedesktop.org/series/124602/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/index.html
CI Bug Log - changes from CI_DRM_13763 -> Patchwork_124602v4
Summary

FAILURE

Serious unknown changes coming with Patchwork_124602v4 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_124602v4, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/index.html

Participating hosts (33 -> 31)

Additional (1): fi-kbl-guc
Missing (3): fi-kbl-7567u bat-jsl-1 bat-jsl-3

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_124602v4:

IGT changes
Possible regressions

  *   igt@i915_module_load@load:

 *   bat-kbl-2: 
PASS
 -> 
INCOMPLETE
Unrelated as the patch touches only mtl not kbl.
Known issues

Here are the changes found in Patchwork_124602v4 that come from known issues:

IGT changes
Issues hit

  *   igt@fbdev@info:

 *   fi-kbl-guc: NOTRUN -> 
SKIP
 (fdo#109271 / 
i915#1849)

  *   igt@gem_exec_suspend@basic-s3@lmem0:

 *   bat-atsm-1: NOTRUN -> 
DMESG-WARN
 (i915#8841) +4 other 
tests dmesg-warn

  *   igt@gem_exec_suspend@basic-s3@smem:

 *   fi-rkl-11600: 
PASS
 -> 
FAIL
 (fdo#103375)

  *   igt@gem_lmem_swapping@basic:

 *   fi-kbl-soraka: NOTRUN -> 
SKIP
 (fdo#109271 / 
i915#4613) +3 other tests 
skip

  *   igt@gem_lmem_swapping@verify-random:

 *   fi-kbl-guc: NOTRUN -> 
SKIP
 (fdo#109271 / 
i915#4613) +3 other tests 
skip

  *   igt@i915_selftest@live@gt_pm:

 *   fi-kbl-soraka: NOTRUN -> 
DMESG-FAIL
 (i915#1886)

  *   igt@i915_selftest@live@mman:

 *   bat-rpls-1: 
PASS
 -> 
TIMEOUT
 (i915#6794 / 
i915#7392)

  *   igt@i915_suspend@basic-s2idle-without-i915:

 *   bat-rpls-1: 
PASS
 -> 
WARN
 (i915#8747)

  *   igt@i915_suspend@basic-s3-without-i915:

 *   bat-atsm-1: NOTRUN -> 
SKIP
 (i915#6645)

  *   igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:

 *   fi-kbl-guc: NOTRUN -> 
SKIP
 (fdo#109271 / 
i915#1845

Re: [Intel-gfx] [PATCH] drm/i915/mtl: avoid stringop-overflow warning

[Arnd Bergmann]

On Tue, Oct 17, 2023, at 00:10, Andi Shyti wrote:
> Hi Arnd,
>
>>  static void rc6_res_reg_init(struct intel_rc6 *rc6)
>>  {
>> -memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg));
>
> This is a complex initialization, indeed... how about just
>
>memset(rc6->res_reg, 0, sizeof(rc6->res_reg));
>
>> +i915_reg_t res_reg[INTEL_RC6_RES_MAX] = {
>> +[0 ... INTEL_RC6_RES_MAX - 1] = INVALID_MMIO_REG,
>> +};
>
> This is basically a
>
>i915_reg_t res_reg[INTEL_RC6_RES_MAX] = { };
>
> Don't know which one is clearer.

Right, the original code went out of its way to use INVALID_MMIO_REG
instead of assuming it is zero, so I tried to preserve that for
consistency.

Arnd

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: avoid stringop-overflow warning (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: avoid stringop-overflow warning (rev3)
URL   : https://patchwork.freedesktop.org/series/125198/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13763 -> Patchwork_125198v3


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_125198v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_125198v3, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/index.html

Participating hosts (33 -> 31)
--

  Additional (1): fi-kbl-guc 
  Missing(3): fi-kbl-soraka fi-kbl-7567u bat-jsl-1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_125198v3:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@load:
- bat-kbl-2:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-kbl-2/igt@i915_module_l...@load.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/bat-kbl-2/igt@i915_module_l...@load.html

  
Known issues


  Here are the changes found in Patchwork_125198v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-jsl-3:  NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- fi-kbl-guc: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1849])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/fi-kbl-guc/igt@fb...@info.html

  * igt@gem_exec_suspend@basic-s3@lmem0:
- bat-atsm-1: NOTRUN -> [DMESG-WARN][5] ([i915#8841]) +4 other 
tests dmesg-warn
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@gem_huc_copy@huc-copy:
- bat-jsl-3:  NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/bat-jsl-3/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- bat-jsl-3:  NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/bat-jsl-3/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-guc: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/fi-kbl-guc/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-atsm-1: NOTRUN -> [SKIP][9] ([i915#6645])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/bat-atsm-1/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-3:  NOTRUN -> [SKIP][10] ([i915#4103]) +1 other test skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/bat-jsl-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-kbl-guc: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1845]) +8 
other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/fi-kbl-guc/igt@kms_cursor_leg...@basic-flip-before-cursor-varying-size.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-jsl-3:  NOTRUN -> [SKIP][12] ([fdo#109285])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/bat-jsl-3/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-c-dp-5:
- bat-adlp-11:[PASS][13] -> [ABORT][14] ([i915#8668] / [i915#9451])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-c-dp-5.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-c-dp-5.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-kbl-guc: NOTRUN -> [SKIP][15] ([fdo#109271]) +25 other tests 
skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/fi-kbl-guc/igt@kms_pipe_crc_ba...@suspend-read-crc.html
- bat-atsm-1: NOTRUN -> [SKIP][16] ([i915#1836])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125198v3/bat-atsm-1/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-jsl-3:  NOTRUN -> [SKIP][17] ([i915#3555]) +1 other test skip
   [17]: 
https://intel

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: avoid stringop-overflow warning (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: avoid stringop-overflow warning (rev3)
URL   : https://patchwork.freedesktop.org/series/125198/
State : warning

== Summary ==

Error: dim checkpatch failed
2de375bf1f63 drm/i915/mtl: avoid stringop-overflow warning
-:6: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible 
unwrapped commit description?)
#6: 
The newly added memset() causes a warning for some reason I could not figure 
out:

-:23: WARNING:BAD_FIXES_TAG: Please use correct Fixes: style 'Fixes: <12 chars 
of sha1> ("")' - ie: 'Fixes: 4bb9ca7ee074 ("drm/i915/mtl: C6 
residency and C state type for MTL SAMedia")'
#23: 
Fixes: 4bb9ca7ee0745 ("drm/i915/mtl: C6 residency and C state type for MTL 
SAMedia")

total: 0 errors, 2 warnings, 0 checks, 29 lines checked

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Define and use GuC and CTB TLB invalidation routines (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines (rev3)
URL   : https://patchwork.freedesktop.org/series/125177/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13763 -> Patchwork_125177v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/index.html

Participating hosts (33 -> 30)
--

  Additional (1): fi-kbl-guc 
  Missing(4): fi-kbl-soraka fi-kbl-7567u fi-cfl-8109u bat-dg1-5 

Known issues


  Here are the changes found in Patchwork_125177v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-jsl-3:  NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- fi-kbl-guc: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1849])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/fi-kbl-guc/igt@fb...@info.html

  * igt@gem_exec_suspend@basic-s3@lmem0:
- bat-atsm-1: NOTRUN -> [DMESG-WARN][3] ([i915#8841]) +4 other 
tests dmesg-warn
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@gem_huc_copy@huc-copy:
- bat-jsl-3:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/bat-jsl-3/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- bat-jsl-3:  NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/bat-jsl-3/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/fi-kbl-guc/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@mman:
- bat-rpls-1: [PASS][7] -> [TIMEOUT][8] ([i915#6794] / [i915#7392])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-rpls-1/igt@i915_selftest@l...@mman.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/bat-rpls-1/igt@i915_selftest@l...@mman.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-1: [PASS][9] -> [WARN][10] ([i915#8747])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-rpls-1/igt@i915_susp...@basic-s2idle-without-i915.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/bat-rpls-1/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-atsm-1: NOTRUN -> [SKIP][11] ([i915#6645])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/bat-atsm-1/igt@i915_susp...@basic-s3-without-i915.html
- bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#6645])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/bat-mtlp-8/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-3:  NOTRUN -> [SKIP][13] ([i915#4103]) +1 other test skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/bat-jsl-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-kbl-guc: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1845]) +8 
other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/fi-kbl-guc/igt@kms_cursor_leg...@basic-flip-before-cursor-varying-size.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-jsl-3:  NOTRUN -> [SKIP][15] ([fdo#109285])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/bat-jsl-3/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: NOTRUN -> [FAIL][16] ([IGT#3])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-adlp-9: NOTRUN -> [SKIP][17] ([i915#3546]) +2 other tests skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/bat-adlp-9/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-c-dp-5:
- bat-adlp-11:[PASS][18] -> [ABORT][19] ([i915#8668] / [i915#9451])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-c-dp-5.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v3/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-c-dp-5.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines (rev3)
URL   : https://patchwork.freedesktop.org/series/125177/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines (rev3)
URL   : https://patchwork.freedesktop.org/series/125177/
State : warning

== Summary ==

Error: dim checkpatch failed
163a738cf408 drm/i915: Add GuC TLB Invalidation device info flags
2804b180223e drm/i915/guc: Add CT size delay helper
14d8ddbdeb5a drm/i915: Define and use GuC and CTB TLB invalidation routines
-:284: WARNING:MISORDERED_TYPE: type 'long unsigned int' should be specified in 
[[un]signed] [short|int|long|long long] order
#284: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1929:
+   long unsigned int i;

-:284: WARNING:UNNECESSARY_INT: Prefer 'unsigned long' over 'long unsigned int' 
as the int is unnecessary
#284: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1929:
+   long unsigned int i;

-:447: WARNING:MEMORY_BARRIER: memory barrier without comment
#447: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4741:
+   smp_store_mb(wq_entry->flags, wq_entry->flags & ~WQ_FLAG_WOKEN);

total: 0 errors, 3 warnings, 0 checks, 441 lines checked
a0058d3ed125 drm/i915: No TLB invalidation on suspended GT
4dba4b8f32dd drm/i915: No TLB invalidation on wedged GT
cef5feff285e drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
-:32: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see 
Documentation/timers/timers-howto.rst
#32: FILE: drivers/gpu/drm/i915/gt/selftest_tlb.c:146:
+   msleep(10);

total: 0 errors, 1 warnings, 0 checks, 17 lines checked
91f0a2161fce drm/i915: Enable GuC TLB invalidations for MTL

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: Optimize mmio_offset_compare() for efficiency (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: Optimize mmio_offset_compare() for efficiency (rev3)
URL   : https://patchwork.freedesktop.org/series/125181/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13763 -> Patchwork_125181v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/index.html

Participating hosts (33 -> 29)
--

  Additional (2): bat-dg2-9 fi-kbl-guc 
  Missing(6): fi-kbl-soraka fi-rkl-11600 fi-skl-guc fi-ilk-650 fi-cfl-8109u 
bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_125181v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-jsl-3:  NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- fi-kbl-guc: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1849])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/fi-kbl-guc/igt@fb...@info.html

  * igt@gem_exec_suspend@basic-s3@lmem0:
- bat-atsm-1: NOTRUN -> [DMESG-WARN][3] ([i915#8841]) +4 other 
tests dmesg-warn
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@gem_huc_copy@huc-copy:
- bat-jsl-3:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-jsl-3/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- bat-jsl-3:  NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-jsl-3/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/fi-kbl-guc/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][7] ([i915#4083])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][10] ([i915#6621])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gt_lrc:
- bat-adlp-9: [PASS][11] -> [INCOMPLETE][12] ([i915#9413])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-adlp-9/igt@i915_selftest@live@gt_lrc.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-adlp-9/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-atsm-1: NOTRUN -> [SKIP][13] ([i915#6645])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-atsm-1/igt@i915_susp...@basic-s3-without-i915.html
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#6645])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-mtlp-8/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][15] ([i915#5190])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][16] ([i915#4215] / [i915#5190])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#4212]) +6 other tests skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9:  NOTRUN -> [SKIP][18] ([i915#4212] / [i915#5608])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125181v3/bat-dg2-9/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_busy@basic@modeset:
- bat-adlp-11:[PASS][19] -> [DMESG-WARN][20] ([i915#6868])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-adlp-11/igt@kms_busy@ba...@modeset.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Prevent potential null-ptr-deref in engine_init_common (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: Prevent potential null-ptr-deref in engine_init_common (rev6)
URL   : https://patchwork.freedesktop.org/series/124971/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13763 -> Patchwork_124971v6


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/index.html

Participating hosts (33 -> 34)
--

  Additional (2): bat-dg2-8 bat-dg2-9 
  Missing(1): fi-kbl-soraka 

Known issues


  Here are the changes found in Patchwork_124971v6 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-jsl-3:  NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_exec_suspend@basic-s0@smem:
- bat-dg2-8:  NOTRUN -> [INCOMPLETE][2] ([i915#8797] / [i915#9275])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-8/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_exec_suspend@basic-s3@lmem0:
- bat-atsm-1: NOTRUN -> [DMESG-WARN][3] ([i915#8841]) +4 other 
tests dmesg-warn
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@gem_huc_copy@huc-copy:
- bat-jsl-3:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-jsl-3/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- bat-jsl-3:  NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-jsl-3/igt@gem_lmem_swapp...@basic.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][6] ([i915#4083])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-9/igt@gem_m...@basic.html
- bat-dg2-8:  NOTRUN -> [SKIP][7] ([i915#4083])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-8/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-9/igt@gem_mmap_...@basic.html
- bat-dg2-8:  NOTRUN -> [SKIP][9] ([i915#4077]) +2 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-8/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][10] ([i915#4079]) +1 other test skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg2-8:  NOTRUN -> [SKIP][11] ([i915#4079]) +1 other test skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-8/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][12] ([i915#6621])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-9/igt@i915_pm_...@basic-api.html
- bat-dg2-8:  NOTRUN -> [SKIP][13] ([i915#6621])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-8/igt@i915_pm_...@basic-api.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-atsm-1: NOTRUN -> [SKIP][14] ([i915#6645])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-atsm-1/igt@i915_susp...@basic-s3-without-i915.html
- bat-dg2-8:  NOTRUN -> [SKIP][15] ([i915#6645])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-8/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][16] ([i915#5190])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
- bat-dg2-8:  NOTRUN -> [SKIP][17] ([i915#5190])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][18] ([i915#4215] / [i915#5190])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
- bat-dg2-8:  NOTRUN -> [SKIP][19] ([i915#4215] / [i915#5190])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9:  NOTRUN -> [SKIP][20] ([i915#4212]) +6 other tests skip
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124971v6/bat-dg2-9/igt@kms_addfb_ba

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Reset message bus after each read/write operation (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Reset message bus after each read/write operation 
(rev4)
URL   : https://patchwork.freedesktop.org/series/124602/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13763 -> Patchwork_124602v4


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_124602v4 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_124602v4, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/index.html

Participating hosts (33 -> 31)
--

  Additional (1): fi-kbl-guc 
  Missing(3): fi-kbl-7567u bat-jsl-1 bat-jsl-3 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_124602v4:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@load:
- bat-kbl-2:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-kbl-2/igt@i915_module_l...@load.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/bat-kbl-2/igt@i915_module_l...@load.html

  
Known issues


  Here are the changes found in Patchwork_124602v4 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@fbdev@info:
- fi-kbl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1849])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/fi-kbl-guc/igt@fb...@info.html

  * igt@gem_exec_suspend@basic-s3@lmem0:
- bat-atsm-1: NOTRUN -> [DMESG-WARN][4] ([i915#8841]) +4 other 
tests dmesg-warn
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600:   [PASS][5] -> [FAIL][6] ([fdo#103375])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-guc: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/fi-kbl-guc/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][9] ([i915#1886])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@mman:
- bat-rpls-1: [PASS][10] -> [TIMEOUT][11] ([i915#6794] / 
[i915#7392])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-rpls-1/igt@i915_selftest@l...@mman.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/bat-rpls-1/igt@i915_selftest@l...@mman.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-1: [PASS][12] -> [WARN][13] ([i915#8747])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-rpls-1/igt@i915_susp...@basic-s2idle-without-i915.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/bat-rpls-1/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-atsm-1: NOTRUN -> [SKIP][14] ([i915#6645])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/bat-atsm-1/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-kbl-guc: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#1845]) +8 
other tests skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/fi-kbl-guc/igt@kms_cursor_leg...@basic-flip-before-cursor-varying-size.html

  * igt@kms_dsc@dsc-basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][16] ([fdo#109271]) +5 other tests 
skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/fi-kbl-soraka/igt@kms_...@dsc-basic.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: NOTRUN -> [FAIL][17] ([IGT#3])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124602v4/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-c-dp-5:
- bat-adlp-11:[PASS][18] -> [ABORT][19] ([i915#8668] / [i915#9451])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-adlp-11/igt@km

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Move the g45 PEG band gap HPD workaround to the HPD code (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Move the g45 PEG band gap HPD workaround to the HPD code 
(rev4)
URL   : https://patchwork.freedesktop.org/series/125053/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13763 -> Patchwork_125053v4


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_125053v4 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_125053v4, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/index.html

Participating hosts (33 -> 33)
--

  Additional (1): fi-kbl-guc 
  Missing(1): fi-cfl-guc 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_125053v4:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_parallel@engines@fds:
- bat-kbl-2:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-kbl-2/igt@gem_exec_parallel@engi...@fds.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/bat-kbl-2/igt@gem_exec_parallel@engi...@fds.html

  
Known issues


  Here are the changes found in Patchwork_125053v4 that come from known issues:

### CI changes ###

 Issues hit 

  * boot:
- fi-kbl-soraka:  [PASS][3] -> [FAIL][4] ([i915#8293])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/fi-kbl-soraka/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/fi-kbl-soraka/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-jsl-3:  NOTRUN -> [SKIP][5] ([i915#9318])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- fi-kbl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1849])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/fi-kbl-guc/igt@fb...@info.html

  * igt@gem_exec_suspend@basic-s3@lmem0:
- bat-atsm-1: NOTRUN -> [DMESG-WARN][7] ([i915#8841]) +4 other 
tests dmesg-warn
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@gem_huc_copy@huc-copy:
- bat-jsl-3:  NOTRUN -> [SKIP][8] ([i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/bat-jsl-3/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- bat-jsl-3:  NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/bat-jsl-3/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-guc: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/fi-kbl-guc/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-atsm-1: NOTRUN -> [SKIP][11] ([i915#6645])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/bat-atsm-1/igt@i915_susp...@basic-s3-without-i915.html
- bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#6645])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/bat-mtlp-8/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-3:  NOTRUN -> [SKIP][13] ([i915#4103]) +1 other test skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/bat-jsl-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- fi-kbl-guc: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1845]) +8 
other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/fi-kbl-guc/igt@kms_cursor_leg...@basic-flip-before-cursor-varying-size.html

  * igt@kms_force_connector_basic@force-load-detect:
- bat-jsl-3:  NOTRUN -> [SKIP][15] ([fdo#109285])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/bat-jsl-3/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: NOTRUN -> [FAIL][16] ([IGT#3])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125053v4/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-c-dp-5:
- bat-adlp-11:[PASS][17] -> [ABORT][18] ([i915#8668] / [i915#9451])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc-frame-seque...@pipe-c-dp-5.html
   [18]: 
htt

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/bios: Clamp VBT HDMI level shift on BDW (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: Clamp VBT HDMI level shift on BDW (rev3)
URL   : https://patchwork.freedesktop.org/series/125120/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13763 -> Patchwork_125120v3


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_125120v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_125120v3, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/index.html

Participating hosts (33 -> 33)
--

  Additional (2): bat-dg2-9 fi-kbl-guc 
  Missing(2): fi-kbl-soraka bat-dg1-5 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_125120v3:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@gt_lrc:
- bat-dg2-11: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/bat-dg2-11/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@reset:
- fi-cfl-8109u:   [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/fi-cfl-8109u/igt@i915_selftest@l...@reset.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/fi-cfl-8109u/igt@i915_selftest@l...@reset.html

  
Known issues


  Here are the changes found in Patchwork_125120v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-jsl-3:  NOTRUN -> [SKIP][5] ([i915#9318])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- fi-kbl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1849])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/fi-kbl-guc/igt@fb...@info.html

  * igt@gem_exec_suspend@basic-s3@lmem0:
- bat-atsm-1: NOTRUN -> [DMESG-WARN][7] ([i915#8841]) +4 other 
tests dmesg-warn
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@gem_exec_suspend@basic-s3@smem:
- bat-mtlp-8: NOTRUN -> [ABORT][8] ([i915#8213] / [i915#9262])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/bat-mtlp-8/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_huc_copy@huc-copy:
- bat-jsl-3:  NOTRUN -> [SKIP][9] ([i915#2190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/bat-jsl-3/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- bat-jsl-3:  NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/bat-jsl-3/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-guc: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/fi-kbl-guc/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][12] ([i915#4083])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/bat-dg2-9/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([i915#4077]) +2 other tests skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/bat-dg2-9/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][14] ([i915#4079]) +1 other test skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][15] ([i915#6621])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/bat-dg2-9/igt@i915_pm_...@basic-api.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-atsm-1: NOTRUN -> [SKIP][16] ([i915#6645])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/bat-atsm-1/igt@i915_susp...@basic-s3-without-i915.html
- bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#6645])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/bat-mtlp-8/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9:  NOTRUN -> [SKIP][18] ([i915#5190])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125120v3/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Define and use GuC and CTB TLB invalidation routines (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines (rev2)
URL   : https://patchwork.freedesktop.org/series/125177/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13763 -> Patchwork_125177v2


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_125177v2 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_125177v2, please notify your bug team 
(lgci.bug.fil...@intel.com) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/index.html

Participating hosts (33 -> 34)
--

  Additional (3): bat-dg2-8 bat-dg2-9 fi-kbl-guc 
  Missing(2): fi-kbl-soraka fi-blb-e6850 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_125177v2:

### IGT changes ###

 Warnings 

  * igt@kms_hdmi_inject@inject-audio:
- bat-adlp-11:[SKIP][1] ([i915#4369]) -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-adlp-11/igt@kms_hdmi_inj...@inject-audio.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-adlp-11/igt@kms_hdmi_inj...@inject-audio.html

  
Known issues


  Here are the changes found in Patchwork_125177v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-jsl-3:  NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- fi-kbl-guc: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1849])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/fi-kbl-guc/igt@fb...@info.html

  * igt@gem_exec_suspend@basic-s3@lmem0:
- bat-atsm-1: NOTRUN -> [DMESG-WARN][5] ([i915#8841]) +4 other 
tests dmesg-warn
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@gem_huc_copy@huc-copy:
- bat-jsl-3:  NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-jsl-3/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- bat-jsl-3:  NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-jsl-3/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- fi-kbl-guc: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/fi-kbl-guc/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][9] ([i915#4083])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-dg2-9/igt@gem_m...@basic.html
- bat-dg2-8:  NOTRUN -> [SKIP][10] ([i915#4083])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-dg2-8/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-dg2-9/igt@gem_mmap_...@basic.html
- bat-dg2-8:  NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-dg2-8/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-dg2-9:  NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg2-8:  NOTRUN -> [SKIP][14] ([i915#4079]) +1 other test skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-dg2-8/igt@gem_tiled_pread_basic.html

  * igt@i915_hangman@error-state-basic:
- bat-mtlp-6: [PASS][15] -> [ABORT][16] ([i915#9414])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13763/bat-mtlp-6/igt@i915_hang...@error-state-basic.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-mtlp-6/igt@i915_hang...@error-state-basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg2-9:  NOTRUN -> [SKIP][17] ([i915#6621])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-dg2-9/igt@i915_pm_...@basic-api.html
- bat-dg2-8:  NOTRUN -> [SKIP][18] ([i915#6621])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125177v2/bat-dg2-8/igt@i915_pm_...@basic-api.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-atsm-1: NOTRUN -> [SKIP][19] ([i915#6645])
   [19]: 
https://i

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines (rev2)
URL   : https://patchwork.freedesktop.org/series/125177/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Define and use GuC and CTB TLB invalidation routines (rev2)
URL   : https://patchwork.freedesktop.org/series/125177/
State : warning

== Summary ==

Error: dim checkpatch failed
acdcc1363f96 drm/i915: Add GuC TLB Invalidation device info flags
e74140ccddc9 drm/i915/guc: Add CT size delay helper
c585f1b7affa drm/i915: Define and use GuC and CTB TLB invalidation routines
-:284: WARNING:MISORDERED_TYPE: type 'long unsigned int' should be specified in 
[[un]signed] [short|int|long|long long] order
#284: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1929:
+   long unsigned int i;

-:284: WARNING:UNNECESSARY_INT: Prefer 'unsigned long' over 'long unsigned int' 
as the int is unnecessary
#284: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1929:
+   long unsigned int i;

-:447: WARNING:MEMORY_BARRIER: memory barrier without comment
#447: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:4741:
+   smp_store_mb(wq_entry->flags, wq_entry->flags & ~WQ_FLAG_WOKEN);

total: 0 errors, 3 warnings, 0 checks, 441 lines checked
31ecf7ee34c3 drm/i915: No TLB invalidation on suspended GT
72b07a838a25 drm/i915: No TLB invalidation on wedged GT
b390ba705588 drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
-:32: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see 
Documentation/timers/timers-howto.rst
#32: FILE: drivers/gpu/drm/i915/gt/selftest_tlb.c:146:
+   msleep(10);

total: 0 errors, 1 warnings, 0 checks, 17 lines checked
e24b9d8c0325 drm/i915: Enable GuC TLB invalidations for MTL

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3

[Belgaumkar, Vinay]

On 10/16/2023 4:24 PM, John Harrison wrote:

On 10/16/2023 15:55, Vinay Belgaumkar wrote:

This bit does not cause an explicit L3 flush. We already use
At all? Or only on newer hardware? And as a genuine spec change or as 
a bug / workaround?


If the hardware has re-purposed the bit then it is probably worth at 
least adding a comment to the bit definition to say that it is only 
valid up to IP version 12.70.
At this point, this is a bug on MTL since this bit is not related to L3 
flushes as per spec. Regarding older platforms, still checking the 
reason why this was added (i.e if it fixed something and will regress if 
removed). If not, we can extend the change for others as well in a 
separate patch. On older platforms, this bit seems to cause an implicit 
flush at best.



PIPE_CONTROL_DC_FLUSH_ENABLE for that purpose.

Cc: Nirmoy Das 
Cc: Mikka Kuoppala 
Signed-off-by: Vinay Belgaumkar 
---
  drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8 ++--
  1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c

index ba4c2422b340..abbc02f3e66e 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -247,6 +247,7 @@ static int mtl_dummy_pipe_control(struct 
i915_request *rq)

  int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
  {
  struct intel_engine_cs *engine = rq->engine;
+    struct intel_gt *gt = rq->engine->gt;
    /*
   * On Aux CCS platforms the invalidation of the Aux
@@ -278,7 +279,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, 
u32 mode)

   * deals with Protected Memory which is not needed for
   * AUX CCS invalidation and lead to unwanted side effects.
   */
-    if (mode & EMIT_FLUSH)
+    if ((mode & EMIT_FLUSH) &&
+    !(IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71
Why stop at 12.71? Is the meaning only changed for 12.70 and the 
old/correct version will be restored in later hardware?


Was trying to keep this limited to MTL for now until the above 
statements are verified.


Thanks,

Vinay.



John.



  bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
    bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
@@ -812,12 +814,14 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct 
i915_request *rq, u32 *cs)

  u32 flags = (PIPE_CONTROL_CS_STALL |
   PIPE_CONTROL_TLB_INVALIDATE |
   PIPE_CONTROL_TILE_CACHE_FLUSH |
- PIPE_CONTROL_FLUSH_L3 |
   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
   PIPE_CONTROL_DC_FLUSH_ENABLE |
   PIPE_CONTROL_FLUSH_ENABLE);
  +    if (!(IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71
+    flags |= PIPE_CONTROL_FLUSH_L3;
+
  /* Wa_14016712196 */
  if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || 
IS_DG2(i915))

  /* dummy PIPE_CONTROL + depth flush */

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3

[John Harrison]

On 10/16/2023 15:55, Vinay Belgaumkar wrote:

This bit does not cause an explicit L3 flush. We already use
At all? Or only on newer hardware? And as a genuine spec change or as a 
bug / workaround?


If the hardware has re-purposed the bit then it is probably worth at 
least adding a comment to the bit definition to say that it is only 
valid up to IP version 12.70.



PIPE_CONTROL_DC_FLUSH_ENABLE for that purpose.

Cc: Nirmoy Das 
Cc: Mikka Kuoppala 
Signed-off-by: Vinay Belgaumkar 
---
  drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8 ++--
  1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index ba4c2422b340..abbc02f3e66e 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -247,6 +247,7 @@ static int mtl_dummy_pipe_control(struct i915_request *rq)
  int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
  {
struct intel_engine_cs *engine = rq->engine;
+   struct intel_gt *gt = rq->engine->gt;
  
  	/*

 * On Aux CCS platforms the invalidation of the Aux
@@ -278,7 +279,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 * deals with Protected Memory which is not needed for
 * AUX CCS invalidation and lead to unwanted side effects.
 */
-   if (mode & EMIT_FLUSH)
+   if ((mode & EMIT_FLUSH) &&
+   !(IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71
Why stop at 12.71? Is the meaning only changed for 12.70 and the 
old/correct version will be restored in later hardware?


John.



bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
  
  		bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;

@@ -812,12 +814,14 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request 
*rq, u32 *cs)
u32 flags = (PIPE_CONTROL_CS_STALL |
 PIPE_CONTROL_TLB_INVALIDATE |
 PIPE_CONTROL_TILE_CACHE_FLUSH |
-PIPE_CONTROL_FLUSH_L3 |
 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 PIPE_CONTROL_DC_FLUSH_ENABLE |
 PIPE_CONTROL_FLUSH_ENABLE);
  
+	if (!(IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71

+   flags |= PIPE_CONTROL_FLUSH_L3;
+
/* Wa_14016712196 */
if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || 
IS_DG2(i915))
/* dummy PIPE_CONTROL + depth flush */

[Intel-gfx] [PATCH] drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3

[Vinay Belgaumkar]

This bit does not cause an explicit L3 flush. We already use
PIPE_CONTROL_DC_FLUSH_ENABLE for that purpose.

Cc: Nirmoy Das 
Cc: Mikka Kuoppala 
Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c 
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index ba4c2422b340..abbc02f3e66e 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -247,6 +247,7 @@ static int mtl_dummy_pipe_control(struct i915_request *rq)
 int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 {
struct intel_engine_cs *engine = rq->engine;
+   struct intel_gt *gt = rq->engine->gt;
 
/*
 * On Aux CCS platforms the invalidation of the Aux
@@ -278,7 +279,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 * deals with Protected Memory which is not needed for
 * AUX CCS invalidation and lead to unwanted side effects.
 */
-   if (mode & EMIT_FLUSH)
+   if ((mode & EMIT_FLUSH) &&
+   !(IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71
bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
 
bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
@@ -812,12 +814,14 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request 
*rq, u32 *cs)
u32 flags = (PIPE_CONTROL_CS_STALL |
 PIPE_CONTROL_TLB_INVALIDATE |
 PIPE_CONTROL_TILE_CACHE_FLUSH |
-PIPE_CONTROL_FLUSH_L3 |
 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 PIPE_CONTROL_DC_FLUSH_ENABLE |
 PIPE_CONTROL_FLUSH_ENABLE);
 
+   if (!(IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71
+   flags |= PIPE_CONTROL_FLUSH_L3;
+
/* Wa_14016712196 */
if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || 
IS_DG2(i915))
/* dummy PIPE_CONTROL + depth flush */
-- 
2.38.1

Re: [Intel-gfx] [PATCH] drm/i915/mtl: avoid stringop-overflow warning

[Andi Shyti]

Hi Arnd,

>  static void rc6_res_reg_init(struct intel_rc6 *rc6)
>  {
> - memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg));

This is a complex initialization, indeed... how about just

   memset(rc6->res_reg, 0, sizeof(rc6->res_reg));

> + i915_reg_t res_reg[INTEL_RC6_RES_MAX] = {
> + [0 ... INTEL_RC6_RES_MAX - 1] = INVALID_MMIO_REG,
> + };

This is basically a

   i915_reg_t res_reg[INTEL_RC6_RES_MAX] = { };

Don't know which one is clearer.

Andi

[Intel-gfx] [PATCH] drm/i915/mtl: avoid stringop-overflow warning

[Arnd Bergmann]

From: Arnd Bergmann 

The newly added memset() causes a warning for some reason I could not figure 
out:

In file included from arch/x86/include/asm/string.h:3,
 from drivers/gpu/drm/i915/gt/intel_rc6.c:6:
In function 'rc6_res_reg_init',
inlined from 'intel_rc6_init' at drivers/gpu/drm/i915/gt/intel_rc6.c:610:2:
arch/x86/include/asm/string_32.h:195:29: error: '__builtin_memset' writing 16 
bytes into a region of size 0 overflows the destination 
[-Werror=stringop-overflow=]
  195 | #define memset(s, c, count) __builtin_memset(s, c, count)
  | ^
drivers/gpu/drm/i915/gt/intel_rc6.c:584:9: note: in expansion of macro 'memset'
  584 | memset(rc6->res_reg, INVALID_MMIO_REG.reg, 
sizeof(rc6->res_reg));
  | ^~
In function 'intel_rc6_init':

Change it to an normal initializer and an added memcpy() that does not have
this problem.

Fixes: 4bb9ca7ee0745 ("drm/i915/mtl: C6 residency and C state type for MTL 
SAMedia")
Signed-off-by: Arnd Bergmann 
---
 drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++--
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c 
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 8b67abd720be8..7090e4be29cb6 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -581,19 +581,23 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
 
 static void rc6_res_reg_init(struct intel_rc6 *rc6)
 {
-   memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg));
+   i915_reg_t res_reg[INTEL_RC6_RES_MAX] = {
+   [0 ... INTEL_RC6_RES_MAX - 1] = INVALID_MMIO_REG,
+   };
 
switch (rc6_to_gt(rc6)->type) {
case GT_MEDIA:
-   rc6->res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6;
+   res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6;
break;
default:
-   rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
-   rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
-   rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
-   rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
+   res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
+   res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
+   res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
+   res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
break;
}
+
+   memcpy(rc6->res_reg, res_reg, sizeof(res_reg));
 }
 
 void intel_rc6_init(struct intel_rc6 *rc6)
-- 
2.39.2

Re: [Intel-gfx] [PATCH v3] drm/i915/display: Reset message bus after each read/write operation

[Rodrigo Vivi]

On Mon, Oct 16, 2023 at 03:55:44PM +0300, Mika Kahola wrote:
> Every know and then we receive the following error when running
> for example IGT test kms_flip.
> 
> [drm] *ERROR* PHY G Read 0d80 failed after 3 retries.
> [drm] *ERROR* PHY G Write 0d81 failed after 3 retries.
> 
> Since the error is sporadic in nature, the patch proposes
> to reset the message bus after every successful or unsuccessful
> read or write operation.
> 
> v2: Add FIXME's to indicate the experimental nature of
> this workaround (Rodrigo)
> v3: Dropping the additional delay as moving reset to *_read_once()
> and *_write_once() functions seem unnecessary delay
> 
> Signed-off-by: Mika Kahola 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 ++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 6e6a1818071e..9e24f820d4cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -206,6 +206,13 @@ static int __intel_cx0_read_once(struct drm_i915_private 
> *i915, enum port port,
>  
>   intel_clear_response_ready_flag(i915, port, lane);
>  
> + /*
> +  * FIXME: Workaround to let HW to settle
> +  * down and let the message bus to end up
> +  * in a known state
> +  */
> + intel_cx0_bus_reset(i915, port, lane);
> +
>   return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
>  }
>  
> @@ -285,6 +292,13 @@ static int __intel_cx0_write_once(struct 
> drm_i915_private *i915, enum port port,
>  
>   intel_clear_response_ready_flag(i915, port, lane);
>  
> + /*
> +  * FIXME: Workaround to let HW to settle
> +  * down and let the message bus to end up
> +  * in a known state
> +  */
> + intel_cx0_bus_reset(i915, port, lane);
> +
>   return 0;
>  }
>  
> -- 
> 2.34.1
> 

Re: [Intel-gfx] [PATCH] drm/i915/gem: Allow users to disable waitboost

[Rodrigo Vivi]

On Mon, Oct 16, 2023 at 09:02:38AM +0100, Tvrtko Ursulin wrote:
> 
> On 13/10/2023 21:51, Rodrigo Vivi wrote:
> > On Thu, Sep 28, 2023 at 01:48:34PM +0100, Tvrtko Ursulin wrote:
> > > 
> > > On 27/09/2023 20:34, Belgaumkar, Vinay wrote:
> > > > 
> > > > On 9/21/2023 3:41 AM, Tvrtko Ursulin wrote:
> > > > > 
> > > > > On 20/09/2023 22:56, Vinay Belgaumkar wrote:
> > > > > > Provide a bit to disable waitboost while waiting on a gem object.
> > > > > > Waitboost results in increased power consumption by requesting RP0
> > > > > > while waiting for the request to complete. Add a bit in the 
> > > > > > gem_wait()
> > > > > > IOCTL where this can be disabled.
> > > > > > 
> > > > > > This is related to the libva API change here -
> > > > > > Link: 
> > > > > > https://github.com/XinfengZhang/libva/commit/3d90d18c67609a73121bb71b20ee4776b54b61a7
> > > > > 
> > > > > This link does not appear to lead to userspace code using this uapi?
> > > > We have asked Carl (cc'd) to post a patch for the same.
> > > 
> > > Ack.
> > 
> > I'm glad to see that we will have the end-to-end flow of the high-level API.
> > 
> > > 
> > > > > > Cc: Rodrigo Vivi 
> > > > > > Signed-off-by: Vinay Belgaumkar 
> > > > > > ---
> > > > > >    drivers/gpu/drm/i915/gem/i915_gem_wait.c | 9 ++---
> > > > > >    drivers/gpu/drm/i915/i915_request.c  | 3 ++-
> > > > > >    drivers/gpu/drm/i915/i915_request.h  | 1 +
> > > > > >    include/uapi/drm/i915_drm.h  | 1 +
> > > > > >    4 files changed, 10 insertions(+), 4 deletions(-)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
> > > > > > b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
> > > > > > index d4b918fb11ce..955885ec859d 100644
> > > > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
> > > > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
> > > > > > @@ -72,7 +72,8 @@ i915_gem_object_wait_reservation(struct
> > > > > > dma_resv *resv,
> > > > > >    struct dma_fence *fence;
> > > > > >    long ret = timeout ?: 1;
> > > > > >    -    i915_gem_object_boost(resv, flags);
> > > > > > +    if (!(flags & I915_WAITBOOST_DISABLE))
> > > > > > +    i915_gem_object_boost(resv, flags);
> > > > > >      dma_resv_iter_begin(&cursor, resv,
> > > > > >    dma_resv_usage_rw(flags & I915_WAIT_ALL));
> > > > > > @@ -236,7 +237,7 @@ i915_gem_wait_ioctl(struct drm_device *dev,
> > > > > > void *data, struct drm_file *file)
> > > > > >    ktime_t start;
> > > > > >    long ret;
> > > > > >    -    if (args->flags != 0)
> > > > > > +    if (args->flags != 0 || args->flags != 
> > > > > > I915_GEM_WAITBOOST_DISABLE)
> > > > > >    return -EINVAL;
> > > > > >      obj = i915_gem_object_lookup(file, args->bo_handle);
> > > > > > @@ -248,7 +249,9 @@ i915_gem_wait_ioctl(struct drm_device *dev,
> > > > > > void *data, struct drm_file *file)
> > > > > >    ret = i915_gem_object_wait(obj,
> > > > > >   I915_WAIT_INTERRUPTIBLE |
> > > > > >   I915_WAIT_PRIORITY |
> > > > > > -   I915_WAIT_ALL,
> > > > > > +   I915_WAIT_ALL |
> > > > > > +   (args->flags & I915_GEM_WAITBOOST_DISABLE ?
> > > > > > +    I915_WAITBOOST_DISABLE : 0),
> > > > > >   to_wait_timeout(args->timeout_ns));
> > > > > >      if (args->timeout_ns > 0) {
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_request.c
> > > > > > b/drivers/gpu/drm/i915/i915_request.c
> > > > > > index f59081066a19..2957409b4b2a 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_request.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_request.c
> > > > > > @@ -2044,7 +2044,8 @@ long i915_request_wait_timeout(struct
> > > > > > i915_request *rq,
> > > > > >     * but at a cost of spending more power processing the 
> > > > > > workload
> > > > > >     * (bad for battery).
> > > > > >     */
> > > > > > -    if (flags & I915_WAIT_PRIORITY && !i915_request_started(rq))
> > > > > > +    if (!(flags & I915_WAITBOOST_DISABLE) && (flags &
> > > > > > I915_WAIT_PRIORITY) &&
> > > > > > +    !i915_request_started(rq))
> > > > > >    intel_rps_boost(rq);
> > > > > >      wait.tsk = current;
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_request.h
> > > > > > b/drivers/gpu/drm/i915/i915_request.h
> > > > > > index 0ac55b2e4223..3cc00e8254dc 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_request.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_request.h
> > > > > > @@ -445,6 +445,7 @@ long i915_request_wait(struct i915_request *rq,
> > > > > >    #define I915_WAIT_INTERRUPTIBLE    BIT(0)
> > > > > >    #define I915_WAIT_PRIORITY    BIT(1) /* small priority bump
> > > > > > for the request */
> > > > > >    #define I915_WAIT_ALL    BIT(2) /* used by
> > > > > > i915_gem_object_wait() */
> > > > > > +#define I915_WAITBOOST_DISABLE    BIT(3) /* used by
> > 
> > maybe name it I915_WAIT_NO_BOOST to align a bit better with t

[Intel-gfx] [PATCH v2] drm/i915/gvt: Optimize mmio_offset_compare() for efficiency

[Kuan-Wei Chiu]

The original code used conditional branching in the mmio_offset_compare
function to compare two values and return -1, 1, or 0 based on the
result. However, the list_sort comparison function only needs results
<0, >0, or =0. This patch optimizes the code to make the comparison
branchless, improving efficiency and reducing code size. This change
reduces the number of comparison operations from 1-2 to a single
subtraction operation, thereby saving the number of instructions.

Signed-off-by: Kuan-Wei Chiu 
---
v1 -> v2:
- Add explicit type cast in case the sizes of u32 and int differ.

 drivers/gpu/drm/i915/gvt/debugfs.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/debugfs.c 
b/drivers/gpu/drm/i915/gvt/debugfs.c
index baccbf1761b7..d85d8a3b5ae5 100644
--- a/drivers/gpu/drm/i915/gvt/debugfs.c
+++ b/drivers/gpu/drm/i915/gvt/debugfs.c
@@ -48,11 +48,7 @@ static int mmio_offset_compare(void *priv,
 
ma = container_of(a, struct diff_mmio, node);
mb = container_of(b, struct diff_mmio, node);
-   if (ma->offset < mb->offset)
-   return -1;
-   else if (ma->offset > mb->offset)
-   return 1;
-   return 0;
+   return (int)ma->offset - (int)mb->offset;
 }
 
 static inline int mmio_diff_handler(struct intel_gvt *gvt,
-- 
2.25.1

[Intel-gfx] [PATCH] drm/i915/gvt: Optimize mmio_offset_compare() for efficiency

[Kuan-Wei Chiu]

The original code used conditional branching in the mmio_offset_compare
function to compare two values and return -1, 1, or 0 based on the
result. However, the list_sort comparison function only needs results
<0, >0, or =0. This patch optimizes the code to make the comparison
branchless, improving efficiency and reducing code size. This change
reduces the number of comparison operations from 1-2 to a single
subtraction operation, thereby saving the number of instructions.

Signed-off-by: Kuan-Wei Chiu 
---
 drivers/gpu/drm/i915/gvt/debugfs.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/debugfs.c 
b/drivers/gpu/drm/i915/gvt/debugfs.c
index baccbf1761b7..998d82a259c8 100644
--- a/drivers/gpu/drm/i915/gvt/debugfs.c
+++ b/drivers/gpu/drm/i915/gvt/debugfs.c
@@ -48,11 +48,7 @@ static int mmio_offset_compare(void *priv,
 
ma = container_of(a, struct diff_mmio, node);
mb = container_of(b, struct diff_mmio, node);
-   if (ma->offset < mb->offset)
-   return -1;
-   else if (ma->offset > mb->offset)
-   return 1;
-   return 0;
+   return ma->offset - mb->offset;
 }
 
 static inline int mmio_diff_handler(struct intel_gvt *gvt,
-- 
2.25.1

Re: [Intel-gfx] [PATCH] drm/i915: Retry gtt fault when out of fence register

[Ville Syrjälä]

On Thu, Oct 12, 2023 at 06:12:26PM +0200, Greg KH wrote:
> On Thu, Oct 12, 2023 at 04:53:38PM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 12, 2023 at 03:40:08PM +0200, Greg KH wrote:
> > > On Thu, Oct 12, 2023 at 04:28:01PM +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä 
> > > > 
> > > > If we can't find a free fence register to handle a fault in the GMADR
> > > > range just return VM_FAULT_NOPAGE without populating the PTE so that
> > > > userspace will retry the access and trigger another fault. Eventually
> > > > we should find a free fence and the fault will get properly handled.
> > > > 
> > > > A further improvement idea might be to reserve a fence (or one per CPU?)
> > > > for the express purpose of handling faults without having to retry. But
> > > > that would require some additional work.
> > > > 
> > > > Looks like this may have gotten broken originally by
> > > > commit 39965b376601 ("drm/i915: don't trash the gtt when running out of 
> > > > fences")
> > > > as that changed the errno to -EDEADLK which wasn't handle by the gtt
> > > > fault code either. But later in commit 2feeb52859fc ("drm/i915/gt: Fix
> > > > -EDEADLK handling regression") I changed it again to -ENOBUFS as 
> > > > -EDEADLK
> > > > was now getting used for the ww mutex dance. So this fix only makes
> > > > sense after that last commit.
> > > > 
> > > > Cc: sta...@vger.kernel.org
> > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9479
> > > > Fixes: 2feeb52859fc ("drm/i915/gt: Fix -EDEADLK handling regression")
> > > > Signed-off-by: Ville Syrjälä 
> > > > ---
> > > >  drivers/gpu/drm/i915/gem/i915_gem_mman.c | 1 +
> > > >  1 file changed, 1 insertion(+)
> > > > 
> > > 
> > > 
> > > 
> > > This is not the correct way to submit patches for inclusion in the
> > > stable kernel tree.  Please read:
> > > 
> > > https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html
> > > for how to do this properly.
> > > 
> > > 
> > 
> > Say what now?
> 
> Sorry, my bot thought this was a patch sent only to stable, I've kicked
> it a bit and it shouldn't do that again...

Ah OK, thanks.

I was a bit worried that my reading comprehension had deterirated enough
that I couldn't figure iut what new requirement in the process I had
violated :)

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH] drm/i915: Retry gtt fault when out of fence register

[Ville Syrjälä]

On Fri, Oct 13, 2023 at 12:53:59PM +0200, Andi Shyti wrote:
> Hi Ville,
> 
> > If we can't find a free fence register to handle a fault in the GMADR
> > range just return VM_FAULT_NOPAGE without populating the PTE so that
> > userspace will retry the access and trigger another fault. Eventually
> > we should find a free fence and the fault will get properly handled.
> > 
> > A further improvement idea might be to reserve a fence (or one per CPU?)
> > for the express purpose of handling faults without having to retry. But
> > that would require some additional work.
> > 
> > Looks like this may have gotten broken originally by
> > commit 39965b376601 ("drm/i915: don't trash the gtt when running out of 
> > fences")
> > as that changed the errno to -EDEADLK which wasn't handle by the gtt
> > fault code either. But later in commit 2feeb52859fc ("drm/i915/gt: Fix
> > -EDEADLK handling regression") I changed it again to -ENOBUFS as -EDEADLK
> > was now getting used for the ww mutex dance. So this fix only makes
> > sense after that last commit.
> > 
> > Cc: sta...@vger.kernel.org
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9479
> > Fixes: 2feeb52859fc ("drm/i915/gt: Fix -EDEADLK handling regression")
> > Signed-off-by: Ville Syrjälä 
> 
> Reviewed-by: Andi Shyti  

Thanks. Pushed to gt-next.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH v16 0/7] drm/i915: Define and use GuC and CTB TLB invalidation routines

[Cavitt, Jonathan]

-Original Message-
From: Cavitt, Jonathan  
Sent: Monday, October 16, 2023 7:51 AM
To: intel-gfx@lists.freedesktop.org
Cc: Gupta, saurabhg ; Cavitt, Jonathan 
; chris.p.wil...@linux.intel.com; Iddamsetty, 
Aravind ; Yang, Fei ; Shyti, 
Andi ; Harrison, John C ; Das, 
Nirmoy ; Krzysztofik, Janusz 
; Roper, Matthew D ; 
tvrtko.ursu...@linux.intel.com; jani.nik...@linux.intel.com
Subject: [PATCH v16 0/7] drm/i915: Define and use GuC and CTB TLB invalidation 
routines
> 
> Implement GuC-based TLB invalidations and use them on MTL.
> 
> Some complexity in the implementation was introduced early on
> and will be required for range-based TLB invalidations.
> RFC: https://patchwork.freedesktop.org/series/124922/
> 
> v2:
> - Add missing supporting patches.
> 
> v3:
> - Split suspend/resume changes and multi-gt support into separate
>   patches.
> - Only perform GuC TLB invalidation functions when supported.
> - Move intel_guc_is_enabled check function to usage location.
> - Address comments.
> 
> v4:
> - Change conditions for GuC-based tlb invalidation support
>   to a pci tag that's only active for MTL.
> - Address some FIXMEs and formatting issues.
> - Move suspend/resume changes to helper functions in intel_gt.h
> - Improve comment for ct_handle_event change.
> - Use cleaner if-else conditions.
> - Address comments.
> 
> v5:
> - Reintroduce missing change to selftest msleep duration
> - Move suspend/resume loops from intel_gt.h to intel_tlb.c,
>   making them no longer static inlines.
> - Remove superfluous blocking and error checks.
> - Move ct_handle_event exception to general case in
>   ct_process_request.
> - Explain usage of xa_alloc_cyclic_irq.
> - Modify explanation of purpose of
>   OUTSTANDING_GUC_TIMEOUT_PERIOD macro.
> - Explain purpose of performing tlb invalidation twice in
>   intel_gt_tlb_resume_all.
> 
> v6:
> - Add this cover letter.
> - Fix explanation of purpose of
>   OUTSTANDING_GUC_TIMEOUT_PERIOD macro again.
> - s/pci tags/pci flags
> - Enable GuC TLB Invalidations separately from adding the
>   flags to do so.
> 
> v7:
> - Eliminate pci terminology from patches.
> - Order new device info flag correctly.
> - Run gen8_ggtt_invalidate in more cases, specifically when
>   GuC-based TLB invalidation is not supported.
> - Use intel_uncore_write_fw instead of intel_uncore_write
>   during guc_ggtt_invalidate.
> - Remove duplicate request message clear in ct_process_request.
> - Remove faulty tag from series.
> 
> v8:
> - Simplify cover letter contents.
> - Fix miscellaneous formatting and typos.
> - Reorder device info flags and defines.
> - Reword commit message.
> - Rename TLB invalidation enums and functions.
> - Add comments explaining confusing points.
> - Add helper function getting expected delay of CT buffer.
> - Simplify intel_guc_tlb_invalidation_done by passing computed
>   values.
> - Remove helper functions for tlb suspend and resume.
> - Move tlb suspend and resume paths to uc.
> - Split suspend/resume and wedged into two patches.
> - Clarify purpose of sleep change in tlb selftest.
> 
> v9:
> - Explain complexity of GuC TLB invalidations as required for
>   range-based TLB invalidations, which will be platformed later.
> - Fix CHECKPATCH issues.
> - Explain intel_guc_is_ready tlb invalidation skip in
>   intel_gt_invalidate_tlb_full.
> - Reword comment for unlocked xa_for_each loop in
>   intel_guc_submission_reset.
> - Report all errors in init_tlb_lookup.
> - Remove debug message from fini_tlb_lookup.
> - Use standardized interface for
>   intel_guc_tlb_invalidation_done
> - Remove spurious changes.
> - Move wake_up_all_tlb_invalidate on wedge to correct patch.
> 
> v10:
> - Add lock to tlb_lookup on guc submission reset.
> - Add comment about why timeout increased from 10 ms to 20 ms
>   by default in gt_tlb selftest.
> - Remove spurious changes.
> 
> v11:
> - Update CT size delay helper to be clearer.
> - Reorder some function declarations.
> - Clarify some comments.
> - Produce error message if attempting to free a busy wait
>   during fini_tlb_lookup.
> - Revert default sleep back to 10 ms.
> - Link to RFC.
> 
> v12:
> - Add helper for checking if GuC TLB invalidation is
>   supported and guc is ready.
> - Prevent suspend/resume actions involving GuC TLB
>   invalidations if guc is not ready.
> - Add path for INTEL_GUC_ACTION_TLB_INVALIDATION_DONE
>   to immediately process in ct_process_request after
>   it is submitted to ct_handle_event.
> 
> v13:
> - Re-add error check in intel_guc_tlb_invalidation_done
>   for invalid length.
> - Remove intel_guc_is_ready requirement from
>   wake_up_all_tlb_invalidate.
> - Align patches 3 and 4 by adding a check for GuC
>   TLB invalidation support to the former that was
>   added in the latter.
> 
> v14:
> - Re-add intel_guc_is_ready requirement to
>   wake_up_all_tlb_invalidate.
> - Move wake_up_all_tlb_invalidate from
>   intel_guc_submission_reset to the end of
>   __uc_hw_init.
> - Remove gen8_ggtt_invalidate changes, as

[Intel-gfx] [PATCH v16 7/7] drm/i915: Enable GuC TLB invalidations for MTL

[Jonathan Cavitt]

Enable GuC TLB invalidations for MTL.  Though more platforms than just
MTL support GuC TLB invalidations, MTL is presently the only platform
that requires it for any purpose, so only enable it there for now to
minimize cross-platform impact.

Signed-off-by: Jonathan Cavitt 
Reviewed-by: Andi Shyti 
Acked-by: Tvrtko Ursulin 
Reviewed-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index df7c261410f79..d4b51ececbb12 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -829,6 +829,7 @@ static const struct intel_device_info mtl_info = {
.has_flat_ccs = 0,
.has_gmd_id = 1,
.has_guc_deprivilege = 1,
+   .has_guc_tlb_invalidation = 1,
.has_llc = 0,
.has_mslice_steering = 0,
.has_snoop = 1,
-- 
2.25.1

[Intel-gfx] [PATCH v16 3/7] drm/i915: Define and use GuC and CTB TLB invalidation routines

[Jonathan Cavitt]

From: Prathap Kumar Valsan 

The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation.  We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tlb, invalidating
the GuC TLBs and falling back to GT invalidation when the GuC is
disabled.
The invalidation is done by sending a request directly to the GuC
tlb_lookup that invalidates the table.  The invalidation is submitted as
a wait request and is performed in the CT event handler.  This means we
cannot perform this TLB invalidation path if the CT is not enabled.
If the request isn't fulfilled in two seconds, this would constitute
an error in the invalidation as that would constitute either a lost
request or a severe GuC overload.

With this new invalidation routine, we can perform GuC-based GGTT
invalidations.  GuC-based GGTT invalidation is incompatible with
MMIO invalidation so we should not perform MMIO invalidation when
GuC-based GGTT invalidation is expected.

The additional complexity incurred in this patch will be necessary for
range-based tlb invalidations, which will be platformed in the future.

Signed-off-by: Prathap Kumar Valsan 
Signed-off-by: Bruce Chang 
Signed-off-by: Chris Wilson 
Signed-off-by: Umesh Nerlige Ramappa 
Signed-off-by: Jonathan Cavitt 
Signed-off-by: Aravind Iddamsetty 
Signed-off-by: Fei Yang 
CC: Andi Shyti 
Reviewed-by: Andi Shyti 
Acked-by: Tvrtko Ursulin 
Acked-by: Nirmoy Das 
Reviewed-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c  |  30 ++-
 drivers/gpu/drm/i915/gt/intel_tlb.c   |  16 +-
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  33 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  22 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |  11 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   1 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 197 +-
 7 files changed, 299 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 4d7d88b92632b..1c93e84278a03 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -206,22 +206,36 @@ static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 }
 
+static void guc_ggtt_ct_invalidate(struct intel_gt *gt)
+{
+   struct intel_uncore *uncore = gt->uncore;
+   intel_wakeref_t wakeref;
+
+   with_intel_runtime_pm_if_active(uncore->rpm, wakeref) {
+   struct intel_guc *guc = >->uc.guc;
+
+   intel_guc_invalidate_tlb_guc(guc);
+   }
+}
+
 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
 {
struct drm_i915_private *i915 = ggtt->vm.i915;
+   struct intel_gt *gt;
 
gen8_ggtt_invalidate(ggtt);
 
-   if (GRAPHICS_VER(i915) >= 12) {
-   struct intel_gt *gt;
-
-   list_for_each_entry(gt, &ggtt->gt_list, ggtt_link)
+   list_for_each_entry(gt, &ggtt->gt_list, ggtt_link) {
+   if (intel_guc_tlb_invalidation_is_available(>->uc.guc)) {
+   guc_ggtt_ct_invalidate(gt);
+   } else if (GRAPHICS_VER(i915) >= 12) {
intel_uncore_write_fw(gt->uncore,
  GEN12_GUC_TLB_INV_CR,
  GEN12_GUC_TLB_INV_CR_INVALIDATE);
-   } else {
-   intel_uncore_write_fw(ggtt->vm.gt->uncore,
- GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+   } else {
+   intel_uncore_write_fw(gt->uncore,
+ GEN8_GTCR, GEN8_GTCR_INVALIDATE);
+   }
}
 }
 
@@ -1243,7 +1257,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.raw_insert_page = gen8_ggtt_insert_page;
}
 
-   if (intel_uc_wants_guc(&ggtt->vm.gt->uc))
+   if (intel_uc_wants_guc_submission(&ggtt->vm.gt->uc))
ggtt->invalidate = guc_ggtt_invalidate;
else
ggtt->invalidate = gen8_ggtt_invalidate;
diff --git a/drivers/gpu/drm/i915/gt/intel_tlb.c 
b/drivers/gpu/drm/i915/gt/intel_tlb.c
index 139608c30d978..4bb13d1890e37 100644
--- a/drivers/gpu/drm/i915/gt/intel_tlb.c
+++ b/drivers/gpu/drm/i915/gt/intel_tlb.c
@@ -12,6 +12,7 @@
 #include "intel_gt_print.h"
 #include "intel_gt_regs.h"
 #include "intel_tlb.h"
+#include "uc/intel_guc.h"
 
 /*
  * HW architecture suggest typical invalidation time at 40us,
@@ -131,11 +132,24 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, 
u32 seqno)
return;
 
with_intel_gt_pm_if_awake(gt, wakeref) {
+   struct intel_guc *guc = >->uc.guc;
+
mutex_lock(>->tlb.invalidate_lock);
if (tlb_seqno_passed(gt, seqno))
goto unlock;
 
-   mmio_invalidate_

[Intel-gfx] [PATCH v16 0/7] drm/i915: Define and use GuC and CTB TLB invalidation routines

[Jonathan Cavitt]

Implement GuC-based TLB invalidations and use them on MTL.

Some complexity in the implementation was introduced early on
and will be required for range-based TLB invalidations.
RFC: https://patchwork.freedesktop.org/series/124922/

v2:
- Add missing supporting patches.

v3:
- Split suspend/resume changes and multi-gt support into separate
  patches.
- Only perform GuC TLB invalidation functions when supported.
- Move intel_guc_is_enabled check function to usage location.
- Address comments.

v4:
- Change conditions for GuC-based tlb invalidation support
  to a pci tag that's only active for MTL.
- Address some FIXMEs and formatting issues.
- Move suspend/resume changes to helper functions in intel_gt.h
- Improve comment for ct_handle_event change.
- Use cleaner if-else conditions.
- Address comments.

v5:
- Reintroduce missing change to selftest msleep duration
- Move suspend/resume loops from intel_gt.h to intel_tlb.c,
  making them no longer static inlines.
- Remove superfluous blocking and error checks.
- Move ct_handle_event exception to general case in
  ct_process_request.
- Explain usage of xa_alloc_cyclic_irq.
- Modify explanation of purpose of
  OUTSTANDING_GUC_TIMEOUT_PERIOD macro.
- Explain purpose of performing tlb invalidation twice in
  intel_gt_tlb_resume_all.

v6:
- Add this cover letter.
- Fix explanation of purpose of
  OUTSTANDING_GUC_TIMEOUT_PERIOD macro again.
- s/pci tags/pci flags
- Enable GuC TLB Invalidations separately from adding the
  flags to do so.

v7:
- Eliminate pci terminology from patches.
- Order new device info flag correctly.
- Run gen8_ggtt_invalidate in more cases, specifically when
  GuC-based TLB invalidation is not supported.
- Use intel_uncore_write_fw instead of intel_uncore_write
  during guc_ggtt_invalidate.
- Remove duplicate request message clear in ct_process_request.
- Remove faulty tag from series.

v8:
- Simplify cover letter contents.
- Fix miscellaneous formatting and typos.
- Reorder device info flags and defines.
- Reword commit message.
- Rename TLB invalidation enums and functions.
- Add comments explaining confusing points.
- Add helper function getting expected delay of CT buffer.
- Simplify intel_guc_tlb_invalidation_done by passing computed
  values.
- Remove helper functions for tlb suspend and resume.
- Move tlb suspend and resume paths to uc.
- Split suspend/resume and wedged into two patches.
- Clarify purpose of sleep change in tlb selftest.

v9:
- Explain complexity of GuC TLB invalidations as required for
  range-based TLB invalidations, which will be platformed later.
- Fix CHECKPATCH issues.
- Explain intel_guc_is_ready tlb invalidation skip in
  intel_gt_invalidate_tlb_full.
- Reword comment for unlocked xa_for_each loop in
  intel_guc_submission_reset.
- Report all errors in init_tlb_lookup.
- Remove debug message from fini_tlb_lookup.
- Use standardized interface for
  intel_guc_tlb_invalidation_done
- Remove spurious changes.
- Move wake_up_all_tlb_invalidate on wedge to correct patch.

v10:
- Add lock to tlb_lookup on guc submission reset.
- Add comment about why timeout increased from 10 ms to 20 ms
  by default in gt_tlb selftest.
- Remove spurious changes.

v11:
- Update CT size delay helper to be clearer.
- Reorder some function declarations.
- Clarify some comments.
- Produce error message if attempting to free a busy wait
  during fini_tlb_lookup.
- Revert default sleep back to 10 ms.
- Link to RFC.

v12:
- Add helper for checking if GuC TLB invalidation is
  supported and guc is ready.
- Prevent suspend/resume actions involving GuC TLB
  invalidations if guc is not ready.
- Add path for INTEL_GUC_ACTION_TLB_INVALIDATION_DONE
  to immediately process in ct_process_request after
  it is submitted to ct_handle_event.

v13:
- Re-add error check in intel_guc_tlb_invalidation_done
  for invalid length.
- Remove intel_guc_is_ready requirement from
  wake_up_all_tlb_invalidate.
- Align patches 3 and 4 by adding a check for GuC
  TLB invalidation support to the former that was
  added in the latter.

v14:
- Re-add intel_guc_is_ready requirement to
  wake_up_all_tlb_invalidate.
- Move wake_up_all_tlb_invalidate from
  intel_guc_submission_reset to the end of
  __uc_hw_init.
- Remove gen8_ggtt_invalidate changes, as they
  aren't related to GuC TLB invalidation.
- Add missing newline.

v15:
- Move wake_up_all_tlb_invalidate from __uc_hw_init
  to intel_guc_submission_reset_finish.
- Change structure of wake_up_all_tlb_invalidate back to
  the way it was in v12, since it looks better and is
  functionally equivalent.
- s/readd/re-add

v16:
- Swap must_wait_woken and intel_gt_is_enabled checks
  in guc_send_invalidate_tlb.

Jonathan Cavitt (6):
  drm/i915: Add GuC TLB Invalidation device info flags
  drm/i915/guc: Add CT size delay helper
  drm/i915: No TLB invalidation on suspended GT
  drm/i915: No TLB invalidation on wedged GT
  drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
  drm/i915: Enable GuC TLB invalidations for M

[Intel-gfx] [PATCH v16 6/7] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck

[Jonathan Cavitt]

For the gt_tlb live selftest, when operating on the GSC engine,
increase the timeout from 10 ms to 200 ms because the GSC
engine is a bit slower than the rest.

Signed-off-by: Jonathan Cavitt 
Reviewed-by: Andi Shyti 
Acked-by: Tvrtko Ursulin 
Reviewed-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/gt/selftest_tlb.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c 
b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 7e41f69fc818f..00b872b6380b1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -136,8 +136,15 @@ pte_tlbinv(struct intel_context *ce,
i915_request_get(rq);
i915_request_add(rq);
 
-   /* Short sleep to sanitycheck the batch is spinning before we begin */
-   msleep(10);
+   /*
+* Short sleep to sanitycheck the batch is spinning before we begin.
+* FIXME: Why is GSC so slow?
+*/
+   if (ce->engine->class == OTHER_CLASS)
+   msleep(200);
+   else
+   msleep(10);
+
if (va == vb) {
if (!i915_request_completed(rq)) {
pr_err("%s(%s): Semaphore sanitycheck failed %llx, with 
alignment %llx, using PTE size %x (phys %x, sg %x)\n",
-- 
2.25.1

[Intel-gfx] [PATCH v16 5/7] drm/i915: No TLB invalidation on wedged GT

[Jonathan Cavitt]

It is not an error for GuC TLB invalidations to fail when the GT is
wedged or disabled, so do not process a wait failure as one in
guc_send_invalidate_tlb.

Signed-off-by: Fei Yang 
Signed-off-by: Jonathan Cavitt 
CC: John Harrison 
Reviewed-by: Andi Shyti 
Acked-by: Tvrtko Ursulin 
Acked-by: Nirmoy Das 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c  | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 1b04b1692e48d..893659cf6e009 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -32,6 +32,7 @@
 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "i915_irq.h"
 #include "i915_trace.h"
 
 /**
@@ -1935,6 +1936,12 @@ void intel_guc_submission_cancel_requests(struct 
intel_guc *guc)
 
/* GuC is blown away, drop all references to contexts */
xa_destroy(&guc->context_lookup);
+
+   /*
+* Wedged GT won't respond to any TLB invalidation request. Simply
+* release all the blocked waiters.
+*/
+   wake_up_all_tlb_invalidate(guc);
 }
 
 void intel_guc_submission_reset_finish(struct intel_guc *guc)
@@ -4749,6 +4756,14 @@ static long must_wait_woken(struct wait_queue_entry 
*wq_entry, long timeout)
return timeout;
 }
 
+static bool intel_gt_is_enabled(const struct intel_gt *gt)
+{
+   /* Check if GT is wedged or suspended */
+   if (intel_gt_is_wedged(gt) || !intel_irqs_enabled(gt->i915))
+   return false;
+   return true;
+}
+
 static int guc_send_invalidate_tlb(struct intel_guc *guc,
   enum intel_guc_tlb_invalidation_type type)
 {
@@ -4798,7 +4813,8 @@ static int guc_send_invalidate_tlb(struct intel_guc *guc,
if (err)
goto out;
 
-   if (!must_wait_woken(&wait, intel_guc_ct_max_queue_time_jiffies())) {
+   if (!must_wait_woken(&wait, intel_guc_ct_max_queue_time_jiffies()) &&
+   intel_gt_is_enabled(guc_to_gt(guc))) {
guc_err(guc,
"TLB invalidation response timed out for seqno %u\n", 
seqno);
err = -ETIME;
-- 
2.25.1

[Intel-gfx] [PATCH v16 4/7] drm/i915: No TLB invalidation on suspended GT

[Jonathan Cavitt]

In case of GT is suspended, don't allow submission of new TLB invalidation
request and cancel all pending requests. The TLB entries will be
invalidated either during GuC reload or on system resume.

Signed-off-by: Fei Yang 
Signed-off-by: Jonathan Cavitt 
CC: John Harrison 
Reviewed-by: Andi Shyti 
Acked-by: Tvrtko Ursulin 
Acked-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  1 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 24 ---
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  7 ++
 3 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 0949628d69f8b..2b6dfe62c8f2a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -537,4 +537,5 @@ int intel_guc_invalidate_tlb_engines(struct intel_guc *guc);
 int intel_guc_invalidate_tlb_guc(struct intel_guc *guc);
 int intel_guc_tlb_invalidation_done(struct intel_guc *guc,
const u32 *payload, u32 len);
+void wake_up_all_tlb_invalidate(struct intel_guc *guc);
 #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9ec6e80b258c4..1b04b1692e48d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1796,6 +1796,20 @@ static void __guc_reset_context(struct intel_context 
*ce, intel_engine_mask_t st
intel_context_put(parent);
 }
 
+void wake_up_all_tlb_invalidate(struct intel_guc *guc)
+{
+   struct intel_guc_tlb_wait *wait;
+   unsigned long i;
+
+   if (!intel_guc_tlb_invalidation_is_available(guc))
+   return;
+
+   xa_lock_irq(&guc->tlb_lookup);
+   xa_for_each(&guc->tlb_lookup, i, wait)
+   wake_up(&wait->wq);
+   xa_unlock_irq(&guc->tlb_lookup);
+}
+
 void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t 
stalled)
 {
struct intel_context *ce;
@@ -1925,9 +1939,6 @@ void intel_guc_submission_cancel_requests(struct 
intel_guc *guc)
 
 void intel_guc_submission_reset_finish(struct intel_guc *guc)
 {
-   struct intel_guc_tlb_wait *wait;
-   long unsigned int i;
-
/* Reset called during driver load or during wedge? */
if (unlikely(!guc_submission_initialized(guc) ||
 intel_gt_is_wedged(guc_to_gt(guc {
@@ -1951,12 +1962,7 @@ void intel_guc_submission_reset_finish(struct intel_guc 
*guc)
 * The full GT reset will have cleared the TLB caches and flushed the
 * G2H message queue; we can release all the blocked waiters.
 */
-   if (intel_guc_tlb_invalidation_is_available(guc)) {
-   xa_lock_irq(&guc->tlb_lookup);
-   xa_for_each(&guc->tlb_lookup, i, wait)
-   wake_up(&wait->wq);
-   xa_unlock_irq(&guc->tlb_lookup);
-   }
+   wake_up_all_tlb_invalidate(guc);
 }
 
 static void destroyed_worker_func(struct work_struct *w);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 98b103375b7ab..27f6561dd7319 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -688,6 +688,8 @@ void intel_uc_suspend(struct intel_uc *uc)
/* flush the GSC worker */
intel_gsc_uc_flush_work(&uc->gsc);
 
+   wake_up_all_tlb_invalidate(guc);
+
if (!intel_guc_is_ready(guc)) {
guc->interrupts.enabled = false;
return;
@@ -736,6 +738,11 @@ static int __uc_resume(struct intel_uc *uc, bool 
enable_communication)
 
intel_gsc_uc_resume(&uc->gsc);
 
+   if (intel_guc_tlb_invalidation_is_available(guc)) {
+   intel_guc_invalidate_tlb_engines(guc);
+   intel_guc_invalidate_tlb_guc(guc);
+   }
+
return 0;
 }
 
-- 
2.25.1

[Intel-gfx] [PATCH v16 2/7] drm/i915/guc: Add CT size delay helper

[Jonathan Cavitt]

As of now, there is no mechanism for tracking a given request's
progress through the queue.  Instead, add a helper that returns
an estimated maximum time the queue should take to drain if
completely full.

Suggested-by: John Harrison 
Signed-off-by: Jonathan Cavitt 
Reviewed-by: Andi Shyti 
Acked-by: Tvrtko Ursulin 
Reviewed-by: Nirmoy Das 
Reviewed-by: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 27 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h |  2 ++
 2 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index c33210ead1ef7..03b616ba4ebb7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -103,6 +103,33 @@ enum { CTB_SEND = 0, CTB_RECV = 1 };
 
 enum { CTB_OWNER_HOST = 0 };
 
+/*
+ * Some H2G commands involve a synchronous response that the driver needs
+ * to wait for. In such cases, a timeout is required to prevent the driver
+ * from waiting forever in the case of an error (either no error response
+ * is defined in the protocol or something has died and requires a reset).
+ * The specific command may be defined as having a time bound response but
+ * the CT is a queue and that time guarantee only starts from the point
+ * when the command reaches the head of the queue and is processed by GuC.
+ *
+ * Ideally there would be a helper to report the progress of a given
+ * command through the CT. However, that would require a significant
+ * amount of work in the CT layer. In the meantime, provide a reasonable
+ * estimation of the worst case latency it should take for the entire
+ * queue to drain. And therefore, how long a caller should wait before
+ * giving up on their request. The current estimate is based on empirical
+ * measurement of a test that fills the buffer with context creation and
+ * destruction requests as they seem to be the slowest operation.
+ */
+long intel_guc_ct_max_queue_time_jiffies(void)
+{
+   /*
+* A 4KB buffer full of context destroy commands takes a little
+* over a second to process so bump that to 2s to be super safe.
+*/
+   return (CTB_H2G_BUFFER_SIZE * HZ) / SZ_2K;
+}
+
 static void ct_receive_tasklet_func(struct tasklet_struct *t);
 static void ct_incoming_request_worker_func(struct work_struct *w);
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
index 58e42901ff498..2c4bb9a941be6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
@@ -104,6 +104,8 @@ struct intel_guc_ct {
 #endif
 };
 
+long intel_guc_ct_max_queue_time_jiffies(void);
+
 void intel_guc_ct_init_early(struct intel_guc_ct *ct);
 int intel_guc_ct_init(struct intel_guc_ct *ct);
 void intel_guc_ct_fini(struct intel_guc_ct *ct);
-- 
2.25.1

[Intel-gfx] [PATCH v16 1/7] drm/i915: Add GuC TLB Invalidation device info flags

[Jonathan Cavitt]

Add device info flags for if GuC TLB Invalidation is enabled.

Signed-off-by: Jonathan Cavitt 
Reviewed-by: Andi Shyti 
Acked-by: Tvrtko Ursulin 
Reviewed-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/i915_drv.h  | 2 ++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cb60fc9cf8737..6a2a78c61f212 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -794,6 +794,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_GUC_DEPRIVILEGE(i915) \
(INTEL_INFO(i915)->has_guc_deprivilege)
 
+#define HAS_GUC_TLB_INVALIDATION(i915) 
(INTEL_INFO(i915)->has_guc_tlb_invalidation)
+
 #define HAS_3D_PIPELINE(i915)  (INTEL_INFO(i915)->has_3d_pipeline)
 
 #define HAS_ONE_EU_PER_FUSE_BIT(i915)  
(INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 39817490b13fd..eba2f0b919c87 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -153,6 +153,7 @@ enum intel_ppgtt_type {
func(has_heci_pxp); \
func(has_heci_gscfi); \
func(has_guc_deprivilege); \
+   func(has_guc_tlb_invalidation); \
func(has_l3_ccs_read); \
func(has_l3_dpf); \
func(has_llc); \
-- 
2.25.1

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Store DSC DPCD capabilities in the connector (rev9)

[Imre Deak]

On Sat, Oct 14, 2023 at 05:20:12AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Store DSC DPCD capabilities in the connector (rev9)
> URL   : https://patchwork.freedesktop.org/series/124723/
> State : failure

Thanks for the reviews, I pushed the patchset.

The failure is unrelated, see below.

> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_13751_full -> Patchwork_124723v9_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_124723v9_full absolutely need 
> to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_124723v9_full, please notify your bug team 
> (lgci.bug.fil...@intel.com) to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (10 -> 10)
> --
> 
>   No changes in participating hosts
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_124723v9_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
> - shard-apl:  NOTRUN -> [FAIL][1]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v9/shard-apl6/igt@kms_hdr@bpc-switch-susp...@pipe-a-dp-1.html

The connected sink has a DPCD version 1.2, so DSC is not supported on it
and the DPCD caps for it are not read out, both before and after this
change. So can't see how the problem (CRC mismatch) would be related to
the changes.

The same happened on another APL before:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13750/shard-apl7/igt@kms_hdr@bpc-switch-susp...@pipe-a-dp-1.html

and also on re-dg2-12 in CI_DRM_13741 and re-mtlp-11 in CI_DRM_13755.

> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_124723v9_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@drm_fdinfo@virtual-busy:
> - shard-mtlp: NOTRUN -> [SKIP][2] ([i915#8414])
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v9/shard-mtlp-8/igt@drm_fdi...@virtual-busy.html
> 
>   * igt@gem_ccs@block-copy-compressed:
> - shard-mtlp: NOTRUN -> [SKIP][3] ([i915#3555])
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v9/shard-mtlp-2/igt@gem_...@block-copy-compressed.html
> 
>   * igt@gem_ctx_exec@basic-nohangcheck:
> - shard-rkl:  [PASS][4] -> [FAIL][5] ([i915#6268])
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13751/shard-rkl-3/igt@gem_ctx_e...@basic-nohangcheck.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v9/shard-rkl-2/igt@gem_ctx_e...@basic-nohangcheck.html
> 
>   * igt@gem_ctx_freq@sysfs@gt0:
> - shard-dg2:  NOTRUN -> [FAIL][6] ([i915#6786])
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v9/shard-dg2-7/igt@gem_ctx_freq@sy...@gt0.html
> 
>   * igt@gem_ctx_persistence@heartbeat-hang:
> - shard-dg2:  NOTRUN -> [SKIP][7] ([i915#8555])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v9/shard-dg2-11/igt@gem_ctx_persiste...@heartbeat-hang.html
> 
>   * igt@gem_exec_balancer@bonded-dual:
> - shard-mtlp: NOTRUN -> [SKIP][8] ([i915#4771])
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v9/shard-mtlp-2/igt@gem_exec_balan...@bonded-dual.html
> 
>   * igt@gem_exec_balancer@bonded-true-hang:
> - shard-dg2:  NOTRUN -> [SKIP][9] ([i915#4812])
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v9/shard-dg2-11/igt@gem_exec_balan...@bonded-true-hang.html
> 
>   * igt@gem_exec_balancer@noheartbeat:
> - shard-mtlp: NOTRUN -> [SKIP][10] ([i915#8555])
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v9/shard-mtlp-8/igt@gem_exec_balan...@noheartbeat.html
> 
>   * igt@gem_exec_capture@capture-invisible@lmem0:
> - shard-dg2:  NOTRUN -> [SKIP][11] ([i915#6334]) +1 other test 
> skip
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v9/shard-dg2-11/igt@gem_exec_capture@capture-invisi...@lmem0.html
> 
>   * igt@gem_exec_fair@basic-flow@rcs0:
> - shard-tglu: [PASS][12] -> [FAIL][13] ([i915#2842])
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13751/shard-tglu-2/igt@gem_exec_fair@basic-f...@rcs0.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v9/shard-tglu-2/igt@gem_exec_fair@basic-f...@rcs0.html
> 
>   * igt@gem_exec_fair@basic-sync:
> - shard-dg2:  NOTRUN -> [SKIP][14] ([i915#3539]) +2 other tests 
> skip
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124723v9/shard-dg2-7/igt@gem_exec_f...@basic-sync.html
> 
>   * igt@gem_exec_fence@submit67:
> - shard-mtlp:   

[Intel-gfx] [PATCH v3] drm/i915/display: Reset message bus after each read/write operation

[Mika Kahola]

Every know and then we receive the following error when running
for example IGT test kms_flip.

[drm] *ERROR* PHY G Read 0d80 failed after 3 retries.
[drm] *ERROR* PHY G Write 0d81 failed after 3 retries.

Since the error is sporadic in nature, the patch proposes
to reset the message bus after every successful or unsuccessful
read or write operation.

v2: Add FIXME's to indicate the experimental nature of
this workaround (Rodrigo)
v3: Dropping the additional delay as moving reset to *_read_once()
and *_write_once() functions seem unnecessary delay

Signed-off-by: Mika Kahola 
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6e6a1818071e..9e24f820d4cf 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -206,6 +206,13 @@ static int __intel_cx0_read_once(struct drm_i915_private 
*i915, enum port port,
 
intel_clear_response_ready_flag(i915, port, lane);
 
+   /*
+* FIXME: Workaround to let HW to settle
+* down and let the message bus to end up
+* in a known state
+*/
+   intel_cx0_bus_reset(i915, port, lane);
+
return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
 }
 
@@ -285,6 +292,13 @@ static int __intel_cx0_write_once(struct drm_i915_private 
*i915, enum port port,
 
intel_clear_response_ready_flag(i915, port, lane);
 
+   /*
+* FIXME: Workaround to let HW to settle
+* down and let the message bus to end up
+* in a known state
+*/
+   intel_cx0_bus_reset(i915, port, lane);
+
return 0;
 }
 
-- 
2.34.1

[Intel-gfx] ✓ Fi.CI.BAT: success for Framework for display parameters (rev3)

[Patchwork]

== Series Details ==

Series: Framework for display parameters (rev3)
URL   : https://patchwork.freedesktop.org/series/124645/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13758 -> Patchwork_124645v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/index.html

Participating hosts (32 -> 32)
--

  Additional (3): fi-cfl-8109u bat-atsm-1 fi-elk-e7500 
  Missing(3): fi-kbl-soraka bat-dg2-9 fi-pnv-d510 

Known issues


  Here are the changes found in Patchwork_124645v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3@lmem0:
- bat-atsm-1: NOTRUN -> [DMESG-WARN][1] ([i915#8841]) +4 other 
tests dmesg-warn
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html

  * igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u:   NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u:   NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-atsm-1: NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/bat-atsm-1/igt@gem_m...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-atsm-1: NOTRUN -> [SKIP][5] ([i915#4077]) +2 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/bat-atsm-1/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-atsm-1: NOTRUN -> [SKIP][6] ([i915#4079]) +1 other test skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/bat-atsm-1/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-atsm-1: NOTRUN -> [SKIP][7] ([i915#6621])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/bat-atsm-1/igt@i915_pm_...@basic-api.html

  * igt@i915_suspend@basic-s3-without-i915:
- bat-atsm-1: NOTRUN -> [SKIP][8] ([i915#6645])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/bat-atsm-1/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_addfb_basic@size-max:
- bat-atsm-1: NOTRUN -> [SKIP][9] ([i915#6077]) +36 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/bat-atsm-1/igt@kms_addfb_ba...@size-max.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-atsm-1: NOTRUN -> [SKIP][10] ([i915#5608] / [i915#6077])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/bat-atsm-1/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-atsm-1: NOTRUN -> [SKIP][11] ([i915#5608] / [i915#6078]) +1 
other test skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/bat-atsm-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
- fi-cfl-8109u:   NOTRUN -> [SKIP][12] ([fdo#109271]) +10 other tests 
skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/fi-cfl-8109u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- bat-atsm-1: NOTRUN -> [SKIP][13] ([i915#6078]) +8 other tests skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/bat-atsm-1/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html

  * igt@kms_flip@basic-plain-flip:
- bat-atsm-1: NOTRUN -> [SKIP][14] ([i915#6166]) +3 other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/bat-atsm-1/igt@kms_f...@basic-plain-flip.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-atsm-1: NOTRUN -> [SKIP][15] ([i915#6093]) +4 other tests skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/bat-atsm-1/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-bsw-nick:[PASS][16] -> [FAIL][17] ([i915#9276])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13758/fi-bsw-nick/igt@kms_frontbuffer_track...@basic.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/fi-bsw-nick/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24:
- bat-atsm-1: NOTRUN -> [SKIP][18] ([i915#1836]) +7 other tests skip
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_124645v3/bat-atsm-1/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-xr24.html

  * igt@kms_prop_blob@b

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Framework for display parameters (rev3)

[Patchwork]

== Series Details ==

Series: Framework for display parameters (rev3)
URL   : https://patchwork.freedesktop.org/series/124645/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Framework for display parameters (rev3)

[Patchwork]

== Series Details ==

Series: Framework for display parameters (rev3)
URL   : https://patchwork.freedesktop.org/series/124645/
State : warning

== Summary ==

Error: dim checkpatch failed
b5f879154dd6 drm/i915/display: Add framework to add parameters specific to 
display
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#79: 
new file mode 100644

-:207: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#207: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:124:
+intel_display_debugfs_create_int(const char *name, umode_t mode,
+   struct dentry *parent, int *value)

-:216: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#216: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:133:
+intel_display_debugfs_create_uint(const char *name, umode_t mode,
+struct dentry *parent, unsigned int *value)

-:223: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mode' - possible 
side-effects?
#223: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:140:
+#define _intel_display_param_create_file(parent, name, mode, valp) \
+   do {\
+   if (mode)   \
+   _Generic(valp,  \
+bool * : debugfs_create_bool,  \
+int * : intel_display_debugfs_create_int, \
+unsigned int * : 
intel_display_debugfs_create_uint, \
+unsigned long * : debugfs_create_ulong, \
+char ** : debugfs_create_str) \
+   (name, mode, parent, valp); \
+   } while (0)

-:223: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'valp' - possible 
side-effects?
#223: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:140:
+#define _intel_display_param_create_file(parent, name, mode, valp) \
+   do {\
+   if (mode)   \
+   _Generic(valp,  \
+bool * : debugfs_create_bool,  \
+int * : intel_display_debugfs_create_int, \
+unsigned int * : 
intel_display_debugfs_create_uint, \
+unsigned long * : debugfs_create_ulong, \
+char ** : debugfs_create_str) \
+   (name, mode, parent, valp); \
+   } while (0)

-:226: CHECK:CAMELCASE: Avoid CamelCase: <_Generic>
#226: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:143:
+   _Generic(valp,  \

-:231: CHECK:SPACING: spaces preferred around that '*' (ctx:WxO)
#231: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:148:
+char ** : debugfs_create_str) \
  ^

-:231: ERROR:SPACING: space prohibited after that '*' (ctx:OxW)
#231: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:148:
+char ** : debugfs_create_str) \
   ^

-:255: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#255: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs_params.c:172:
+#define REGISTER(T, x, unused, mode, ...) _intel_display_param_create_file( \
+   dir, #x, mode, &i915->display.params.x);

-:332: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible 
side-effects?
#332: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:9:
+#define intel_display_param_named(name, T, perm, desc) \
+   module_param_named(name, intel_display_modparams.name, T, perm); \
+   MODULE_PARM_DESC(name, desc)

-:335: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible 
side-effects?
#335: FILE: drivers/gpu/drm/i915/display/intel_display_params.c:12:
+#define intel_display_param_named_unsafe(name, T, perm, desc) \
+   module_param_named_unsafe(name, intel_display_modparams.name, T, perm); 
\
+   MODULE_PARM_DESC(name, desc)

-:344: CHECK:LINE_SPACING: Please use a blank line after 
functi

Re: [Intel-gfx] [PATCH v2] drm/i915/display: Reset message bus after each read/write operation

[Kahola, Mika]

> -Original Message-
> From: Vivi, Rodrigo 
> Sent: Friday, October 13, 2023 11:22 PM
> To: Kahola, Mika 
> Cc: intel-gfx@lists.freedesktop.org; Sousa, Gustavo 
> Subject: Re: [PATCH v2] drm/i915/display: Reset message bus after each 
> read/write operation
> 
> On Fri, Oct 13, 2023 at 09:55:32AM +0300, Mika Kahola wrote:
> > Every know and then we receive the following error when running for
> > example IGT test kms_flip.
> >
> > [drm] *ERROR* PHY G Read 0d80 failed after 3 retries.
> > [drm] *ERROR* PHY G Write 0d81 failed after 3 retries.
> >
> > Since the error is sporadic in nature, the patch proposes to reset the
> > message bus after every successful or unsuccessful read or write
> > operation. However, the testing revealed that this alone is not
> > sufficient method and therefore an additional delay is introduced
> > anything from 200us to 300us to let HW to settle down. This delay is
> > experimental value and has no specification to back it up.
> >
> > v2: Add FIXME's to indicate the experimental nature of
> > this workaround (Rodrigo)
> >
> > Signed-off-by: Mika Kahola 
> > ---
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 16 
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 6e6a1818071e..7c48ec5e54bd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -221,6 +221,14 @@ static u8 __intel_cx0_read(struct drm_i915_private 
> > *i915, enum port port,
> > for (i = 0; i < 3; i++) {
> > status = __intel_cx0_read_once(i915, port, lane, addr);
> >
> > +   /*
> > +* FIXME: Workaround to let HW to settle
> > +* down and let the message bus to end up
> > +* in a known state
> > +*/
> > +   intel_cx0_bus_reset(i915, port, lane);
> > +   usleep_range(200, 300);
> > +
> > if (status >= 0)
> > return status;
> > }
> > @@ -300,6 +308,14 @@ static void __intel_cx0_write(struct drm_i915_private 
> > *i915, enum port port,
> > for (i = 0; i < 3; i++) {
> > status = __intel_cx0_write_once(i915, port, lane, addr, data,
> > committed);
> >
> > +   /*
> > +* FIXME: Workaround to let HW to settle
> > +* down and let the message bus to end up
> > +* in a known state
> > +*/
> > +   intel_cx0_bus_reset(i915, port, lane);
> > +   usleep_range(200, 300);
> 
> what cases trigger these paths?
I have noticed this when executing IGT test kms_flip with 4k monitors and eDP 
connected. Specially with 2x- cases.

> and how many calls in the modset case?
I haven't put any counters for this but quite a few anyways. This surely 
introduces additional delay.

> what about suspend/resume cylces?
> 
> if we do a single rmw we are introducing at least 400us of delay here.
> have we measured the overall final impact of these extra sleeps on the resume 
> and modeset latencies?
We haven't measured overall impact. I did some further testing and 200-300us 
delay is an overkill solution. I tested with 1-10us delay and with my test 
vehicle, I didn't see any issue to use that. 

In fact, I moved the bus reset routine to be part of *_read_once() and 
*_write_once() functions and to me despite it looks more cleaner solution I can 
get rid of the delay. It must be noted that my test vehicle has changed to 
different MTL. Anyway, I will float the patch with revised function placement 
and delay drop. We can continue discussion from there.

Thanks!

-Mika-  

> 
> > +
> > if (status == 0)
> > return;
> > }
> > --
> > 2.34.1
> >

[Intel-gfx] [PATCH v2 20/24] drm/i915/display: Use device parameters instead of module in I915_STATE_WARN

[Jouni Högander]

Also make module parameter as non writable.

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display.h | 2 +-
 drivers/gpu/drm/i915/i915_params.c   | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
b/drivers/gpu/drm/i915/display/intel_display.h
index 0e5dffe8f018..ba3548f9768d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -552,7 +552,7 @@ bool assert_port_valid(struct drm_i915_private *i915, enum 
port port);
struct drm_device *drm = &(__i915)->drm;\
int __ret_warn_on = !!(condition);  \
if (unlikely(__ret_warn_on))\
-   if (!drm_WARN(drm, i915_modparams.verbose_state_checks, 
format)) \
+   if (!drm_WARN(drm, __i915->params.verbose_state_checks, 
format)) \
drm_err(drm, format);   \
unlikely(__ret_warn_on);\
 })
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 3205c6b62670..4e8c088c69fd 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -93,8 +93,7 @@ i915_param_named(mmio_debug, int, 0400,
"Enable the MMIO debug code for the first N failures (default: off). "
"This may negatively affect performance.");
 
-/* Special case writable file */
-i915_param_named(verbose_state_checks, bool, 0600,
+i915_param_named(verbose_state_checks, bool, 0400,
"Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state 
conditions.");
 
 i915_param_named_unsafe(nuclear_pageflip, bool, 0400,
-- 
2.34.1

[Intel-gfx] [PATCH v2 22/24] drm/i915/display: Move nuclear_pageflip under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
 drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/i915_params.c  | 3 ---
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c 
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 50841818fb59..0b522c6a8d6f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1113,7 +1113,7 @@ void intel_display_device_info_runtime_init(struct 
drm_i915_private *i915)
}
 
/* Disable nuclear pageflip by default on pre-g4x */
-   if (!i915->params.nuclear_pageflip &&
+   if (!i915->display.params.nuclear_pageflip &&
DISPLAY_VER(i915) < 5 && !IS_G4X(i915))
i915->drm.driver_features &= ~DRIVER_ATOMIC;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index e86766639396..3045a1b9b704 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -90,6 +90,9 @@ intel_display_param_named(disable_display, bool, 0400,
 intel_display_param_named(verbose_state_checks, bool, 0400,
"Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state 
conditions.");
 
+intel_display_param_named_unsafe(nuclear_pageflip, bool, 0400,
+   "Force enable atomic functionality on platforms that don't have full 
support yet.");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index b35443f51375..d25e17f88a78 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -40,6 +40,7 @@ struct drm_i915_private;
param(bool, force_reset_modeset_test, false, 0600) \
param(bool, disable_display, false, 0400) \
param(bool, verbose_state_checks, true, 0) \
+   param(bool, nuclear_pageflip, false, 0400) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 72614c139222..18424873442d 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -93,9 +93,6 @@ i915_param_named(mmio_debug, int, 0400,
"Enable the MMIO debug code for the first N failures (default: off). "
"This may negatively affect performance.");
 
-i915_param_named_unsafe(nuclear_pageflip, bool, 0400,
-   "Force enable atomic functionality on platforms that don't have full 
support yet.");
-
 i915_param_named_unsafe(enable_guc, int, 0400,
"Enable GuC load for GuC submission and/or HuC load. "
"Required functionality can be selected using bitmask values. "
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 4b543beb17ca..c7fff571db2c 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -64,7 +64,6 @@ struct drm_printer;
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, error_capture, true, 
IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \
-   param(bool, nuclear_pageflip, false, 0400) \
param(bool, enable_dp_mst, true, 0600) \
param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 
0)
 
-- 
2.34.1

[Intel-gfx] [PATCH v2 24/24] drm/i915/display: Use same permissions for enable_sagv as for rest

[Jouni Högander]

Generally we have writable device parameters in debugfs. No need
to allow writing module parameters.

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 8e6353c1c25e..077f2dee2975 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -50,7 +50,7 @@ intel_display_param_named_unsafe(enable_dc, int, 0400,
 intel_display_param_named_unsafe(enable_dpt, bool, 0400,
"Enable display page table (DPT) (default: true)");
 
-intel_display_param_named_unsafe(enable_sagv, bool, 0600,
+intel_display_param_named_unsafe(enable_sagv, bool, 0400,
"Enable system agent voltage/frequency scaling (SAGV) (default: true)");
 
 intel_display_param_named_unsafe(disable_power_well, int, 0400,
-- 
2.34.1

[Intel-gfx] [PATCH v2 21/24] drm/i915/display: Move verbose_state_checks under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display.h| 2 +-
 drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/i915_params.c  | 3 ---
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
b/drivers/gpu/drm/i915/display/intel_display.h
index ba3548f9768d..bc95fb377386 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -552,7 +552,7 @@ bool assert_port_valid(struct drm_i915_private *i915, enum 
port port);
struct drm_device *drm = &(__i915)->drm;\
int __ret_warn_on = !!(condition);  \
if (unlikely(__ret_warn_on))\
-   if (!drm_WARN(drm, __i915->params.verbose_state_checks, 
format)) \
+   if (!drm_WARN(drm, __i915->display.params.verbose_state_checks, 
format)) \
drm_err(drm, format);   \
unlikely(__ret_warn_on);\
 })
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 06e68c7fec1c..e86766639396 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -87,6 +87,9 @@ intel_display_param_named_unsafe(force_reset_modeset_test, 
bool, 0400,
 intel_display_param_named(disable_display, bool, 0400,
"Disable display (default: false)");
 
+intel_display_param_named(verbose_state_checks, bool, 0400,
+   "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state 
conditions.");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 60d9c3d59fe4..b35443f51375 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -39,6 +39,7 @@ struct drm_i915_private;
param(bool, load_detect_test, false, 0600) \
param(bool, force_reset_modeset_test, false, 0600) \
param(bool, disable_display, false, 0400) \
+   param(bool, verbose_state_checks, true, 0) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 4e8c088c69fd..72614c139222 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -93,9 +93,6 @@ i915_param_named(mmio_debug, int, 0400,
"Enable the MMIO debug code for the first N failures (default: off). "
"This may negatively affect performance.");
 
-i915_param_named(verbose_state_checks, bool, 0400,
-   "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state 
conditions.");
-
 i915_param_named_unsafe(nuclear_pageflip, bool, 0400,
"Force enable atomic functionality on platforms that don't have full 
support yet.");
 
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 8bce7d057634..4b543beb17ca 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -64,7 +64,6 @@ struct drm_printer;
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, error_capture, true, 
IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \
-   param(bool, verbose_state_checks, true, 0) \
param(bool, nuclear_pageflip, false, 0400) \
param(bool, enable_dp_mst, true, 0600) \
param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 
0)
-- 
2.34.1

[Intel-gfx] [PATCH v2 23/24] drm/i915/display: Move enable_dp_mst under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/display/intel_dp.c | 6 +++---
 drivers/gpu/drm/i915/i915_params.c  | 3 ---
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 3045a1b9b704..8e6353c1c25e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -93,6 +93,9 @@ intel_display_param_named(verbose_state_checks, bool, 0400,
 intel_display_param_named_unsafe(nuclear_pageflip, bool, 0400,
"Force enable atomic functionality on platforms that don't have full 
support yet.");
 
+intel_display_param_named_unsafe(enable_dp_mst, bool, 0400,
+   "Enable multi-stream transport (MST) for new DisplayPort sinks. 
(default: true)");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index d25e17f88a78..83c4429ada35 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -41,6 +41,7 @@ struct drm_i915_private;
param(bool, disable_display, false, 0400) \
param(bool, verbose_state_checks, true, 0) \
param(bool, nuclear_pageflip, false, 0400) \
+   param(bool, enable_dp_mst, true, 0600) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4f6835a7578e..f90d8cace6a6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3749,7 +3749,7 @@ intel_dp_can_mst(struct intel_dp *intel_dp)
 {
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
-   return i915->params.enable_dp_mst &&
+   return i915->display.params.enable_dp_mst &&
intel_dp_mst_source_support(intel_dp) &&
drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
 }
@@ -3767,13 +3767,13 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
encoder->base.base.id, encoder->base.name,
str_yes_no(intel_dp_mst_source_support(intel_dp)),
str_yes_no(sink_can_mst),
-   str_yes_no(i915->params.enable_dp_mst));
+   str_yes_no(i915->display.params.enable_dp_mst));
 
if (!intel_dp_mst_source_support(intel_dp))
return;
 
intel_dp->is_mst = sink_can_mst &&
-   i915->params.enable_dp_mst;
+   i915->display.params.enable_dp_mst;
 
drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
intel_dp->is_mst);
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 18424873442d..de43048543e8 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -114,9 +114,6 @@ i915_param_named_unsafe(dmc_firmware_path, charp, 0400,
 i915_param_named_unsafe(gsc_firmware_path, charp, 0400,
"GSC firmware path to use instead of the default one");
 
-i915_param_named_unsafe(enable_dp_mst, bool, 0400,
-   "Enable multi-stream transport (MST) for new DisplayPort sinks. 
(default: true)");
-
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
 i915_param_named_unsafe(inject_probe_failure, uint, 0400,
"Force an error after a number of failure check points (0:disabled 
(default), N:force failure at the Nth failure check point)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c7fff571db2c..1315d7fac850 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -64,7 +64,6 @@ struct drm_printer;
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, error_capture, true, 
IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \
-   param(bool, enable_dp_mst, true, 0600) \
param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 
0)
 
 #define MEMBER(T, member, ...) T member;
-- 
2.34.1

[Intel-gfx] [PATCH v2 09/24] drm/i915/display: Move enable_dc module parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display_params.c | 5 +
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/display/intel_display_power.c  | 2 +-
 drivers/gpu/drm/i915/i915_params.c  | 5 -
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 6a5be37ec3af..7a528e72c970 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -42,6 +42,11 @@ intel_display_param_named_unsafe(vbt_sdvo_panel_type, int, 
0400,
"Override/Ignore selection of SDVO panel mode in the VBT "
"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 
+intel_display_param_named_unsafe(enable_dc, int, 0400,
+   "Enable power-saving display C-states. "
+   "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
+   "3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index c40a3cd57ffc..8721179b3f09 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -28,6 +28,7 @@ struct drm_i915_private;
param(int, lvds_channel_mode, 0, 0400) \
param(int, panel_use_ssc, -1, 0600) \
param(int, vbt_sdvo_panel_type, -1, 0400) \
+   param(int, enable_dc, -1, 0400) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index e25785ae1c20..4832eb8da080 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1020,7 +1020,7 @@ int intel_power_domains_init(struct drm_i915_private 
*dev_priv)
sanitize_disable_power_well_option(dev_priv,
   
dev_priv->params.disable_power_well);
power_domains->allowed_dc_mask =
-   get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
+   get_allowed_dc_mask(dev_priv, 
dev_priv->display.params.enable_dc);
 
power_domains->target_dc_state =
sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index d0abcbd526a7..3d370e43df3c 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -67,11 +67,6 @@ i915_param_named(modeset, int, 0400,
"Use kernel modesetting [KMS] (0=disable, "
"1=on, -1=force vga console preference [default])");
 
-i915_param_named_unsafe(enable_dc, int, 0400,
-   "Enable power-saving display C-states. "
-   "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
-   "3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
-
 i915_param_named_unsafe(reset, uint, 0400,
"Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset 
[default])");
 
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 1ea332dfbb5d..c3487b9d6937 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,6 @@ struct drm_printer;
  */
 #define I915_PARAMS_FOR_EACH(param) \
param(int, modeset, -1, 0400) \
-   param(int, enable_dc, -1, 0400) \
param(bool, enable_dpt, true, 0400) \
param(bool, enable_sagv, true, 0600) \
param(int, disable_power_well, -1, 0400) \
-- 
2.34.1

[Intel-gfx] [PATCH v2 19/24] drm/i915/display: Move disable_display parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 3 ++-
 drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/i915_params.c  | 3 ---
 drivers/gpu/drm/i915/i915_params.h  | 2 --
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c 
b/drivers/gpu/drm/i915/display/intel_display_device.c
index e80842d1e7c7..50841818fb59 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1153,5 +1153,6 @@ bool intel_display_device_enabled(struct drm_i915_private 
*i915)
/* Only valid when HAS_DISPLAY() is true */
drm_WARN_ON(&i915->drm, !HAS_DISPLAY(i915));
 
-   return !i915->params.disable_display && 
!intel_opregion_headless_sku(i915);
+   return !i915->display.params.disable_display &&
+   !intel_opregion_headless_sku(i915);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 7f330a5e1188..06e68c7fec1c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -84,6 +84,9 @@ intel_display_param_named_unsafe(force_reset_modeset_test, 
bool, 0400,
"Force a modeset during gpu reset for testing (default:false). "
"For developers only.");
 
+intel_display_param_named(disable_display, bool, 0400,
+   "Disable display (default: false)");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 25f238e63ff8..60d9c3d59fe4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -38,6 +38,7 @@ struct drm_i915_private;
param(int, enable_dpcd_backlight, -1, 0600) \
param(bool, load_detect_test, false, 0600) \
param(bool, force_reset_modeset_test, false, 0600) \
+   param(bool, disable_display, false, 0400) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 497e39b1dcfb..3205c6b62670 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -86,9 +86,6 @@ i915_param_named_unsafe(force_probe, charp, 0400,
"Force probe options for specified supported devices. "
"See CONFIG_DRM_I915_FORCE_PROBE for details.");
 
-i915_param_named(disable_display, bool, 0400,
-   "Disable display (default: false)");
-
 i915_param_named(memtest, bool, 0400,
"Perform a read/write test of all device memory on module load 
(default: off)");
 
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 5fa77ecb8d31..8bce7d057634 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -63,9 +63,7 @@ struct drm_printer;
param(unsigned int, lmem_bar_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
-   param(bool, force_reset_modeset_test, false, 0600)  \
param(bool, error_capture, true, 
IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \
-   param(bool, disable_display, false, 0400) \
param(bool, verbose_state_checks, true, 0) \
param(bool, nuclear_pageflip, false, 0400) \
param(bool, enable_dp_mst, true, 0600) \
-- 
2.34.1

[Intel-gfx] [PATCH v2 10/24] drm/i915/display: Move enable_dpt module parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/display/intel_dpt.c| 6 --
 drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
 drivers/gpu/drm/i915/display/skl_universal_plane.c  | 2 +-
 drivers/gpu/drm/i915/i915_params.c  | 3 ---
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 7 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 7a528e72c970..8f222b5bfd8d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -47,6 +47,9 @@ intel_display_param_named_unsafe(enable_dc, int, 0400,
"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
"3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
 
+intel_display_param_named_unsafe(enable_dpt, bool, 0400,
+   "Enable display page table (DPT) (default: true)");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 8721179b3f09..c67ed16670c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -29,6 +29,7 @@ struct drm_i915_private;
param(int, panel_use_ssc, -1, 0600) \
param(int, vbt_sdvo_panel_type, -1, 0400) \
param(int, enable_dc, -1, 0400) \
+   param(bool, enable_dpt, true, 0400) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c 
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 48582b31b7f7..2b067cb952f0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -332,11 +332,13 @@ void intel_dpt_configure(struct intel_crtc *crtc)
 
intel_de_rmw(i915, PLANE_CHICKEN(pipe, plane_id),
 PLANE_CHICKEN_DISABLE_DPT,
-i915->params.enable_dpt ? 0 : 
PLANE_CHICKEN_DISABLE_DPT);
+i915->display.params.enable_dpt ? 0 :
+PLANE_CHICKEN_DISABLE_DPT);
}
} else if (DISPLAY_VER(i915) == 13) {
intel_de_rmw(i915, CHICKEN_MISC_2,
 CHICKEN_MISC_DISABLE_DPT,
-i915->params.enable_dpt ? 0 : 
CHICKEN_MISC_DISABLE_DPT);
+i915->display.params.enable_dpt ? 0 :
+CHICKEN_MISC_DISABLE_DPT);
}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c 
b/drivers/gpu/drm/i915/display/intel_fb.c
index 19b35ece31f1..9a48eb7dcf8b 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -764,7 +764,7 @@ bool intel_fb_modifier_uses_dpt(struct drm_i915_private 
*i915, u64 modifier)
 
 bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
 {
-   return fb && to_i915(fb->dev)->params.enable_dpt &&
+   return fb && to_i915(fb->dev)->display.params.enable_dpt &&
intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
 }
 
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 245a64332cc7..6fb5612bff2b 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2489,7 +2489,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
goto error;
}
 
-   if (!dev_priv->params.enable_dpt &&
+   if (!dev_priv->display.params.enable_dpt &&
intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) {
drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial 
FB\n");
goto error;
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 3d370e43df3c..773a0a709fc6 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -95,9 +95,6 @@ i915_param_named_unsafe(disable_power_well, int, 0400,
 
 i915_param_named_unsafe(enable_ips, int, 0400, "Enable IPS (default: true)");
 
-i915_param_named_unsafe(enable_dpt, bool, 0400,
-   "Enable display page table (DPT) (default: true)");
-
 i915_param_named_unsafe(load_detect_test, bool, 0400,
"Force-enable the VGA load detect code for testing (default:false). "
"For developers only.");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c34

[Intel-gfx] [PATCH v2 14/24] drm/i915/display: Move invert_brightness module parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_backlight.c  | 9 +
 drivers/gpu/drm/i915/display/intel_display_params.c | 9 -
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/i915_params.c  | 7 ---
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 5 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c 
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 2e8f17c04522..612d4cd9dacb 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -88,10 +88,10 @@ u32 intel_backlight_invert_pwm_level(struct intel_connector 
*connector, u32 val)
 
drm_WARN_ON(&i915->drm, panel->backlight.pwm_level_max == 0);
 
-   if (i915->params.invert_brightness < 0)
+   if (i915->display.params.invert_brightness < 0)
return val;
 
-   if (i915->params.invert_brightness > 0 ||
+   if (i915->display.params.invert_brightness > 0 ||
intel_has_quirk(i915, QUIRK_INVERT_BRIGHTNESS)) {
return panel->backlight.pwm_level_max - val + 
panel->backlight.pwm_level_min;
}
@@ -132,8 +132,9 @@ u32 intel_backlight_level_from_pwm(struct intel_connector 
*connector, u32 val)
drm_WARN_ON_ONCE(&i915->drm,
 panel->backlight.max == 0 || 
panel->backlight.pwm_level_max == 0);
 
-   if (i915->params.invert_brightness > 0 ||
-   (i915->params.invert_brightness == 0 && intel_has_quirk(i915, 
QUIRK_INVERT_BRIGHTNESS)))
+   if (i915->display.params.invert_brightness > 0 ||
+   (i915->display.params.invert_brightness == 0 &&
+intel_has_quirk(i915, QUIRK_INVERT_BRIGHTNESS)))
val = panel->backlight.pwm_level_max - (val - 
panel->backlight.pwm_level_min);
 
return scale(val, panel->backlight.pwm_level_min, 
panel->backlight.pwm_level_max,
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index c2399e11203c..8d8050a22bf7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -57,7 +57,14 @@ intel_display_param_named_unsafe(disable_power_well, int, 
0400,
"Disable display power wells when possible "
"(-1=auto [default], 0=power wells always on, 1=power wells disabled 
when possible)");
 
-i915_param_named_unsafe(enable_ips, int, 0400, "Enable IPS (default: true)");
+intel_display_param_named_unsafe(enable_ips, int, 0400, "Enable IPS (default: 
true)");
+
+intel_display_param_named_unsafe(invert_brightness, int, 0400,
+   "Invert backlight brightness "
+   "(-1 force normal, 0 machine defaults, 1 force inversion), please "
+   "report PCI device ID, subsystem vendor and subsystem device ID "
+   "to dri-de...@lists.freedesktop.org, if your machine needs it. "
+   "It will then be included in an upcoming module version.");
 
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 11c21a3a3124..23fa03ea38c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -33,6 +33,7 @@ struct drm_i915_private;
param(bool, enable_sagv, true, 0600) \
param(int, disable_power_well, -1, 0400) \
param(int, enable_ips, 1, 0600) \
+   param(int, invert_brightness, 0, 0600) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 54dcce97da2a..423fe54484e1 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -94,13 +94,6 @@ i915_param_named_unsafe(force_reset_modeset_test, bool, 0400,
"Force a modeset during gpu reset for testing (default:false). "
"For developers only.");
 
-i915_param_named_unsafe(invert_brightness, int, 0400,
-   "Invert backlight brightness "
-   "(-1 force normal, 0 machine defaults, 1 force inversion), please "
-   "report PCI device ID, subsystem vendor and subsystem device ID "
-   "to dri-de...@lists.freedesktop.org, if your machine needs it. "
-   "It will then be included in an upcoming module version.");
-
 i915_param_named(disable_display, bool, 0400,
"Disable display (default: false)");
 
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 18bb8a93e0e8..ae0873443a65 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,6 @@ struct drm_printer;
  */
 #define I915_PARAMS_

[Intel-gfx] [PATCH v2 17/24] drm/i915/display: Move load_detect_test parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_crt.c| 4 ++--
 drivers/gpu/drm/i915/display/intel_display_params.c | 4 
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/i915_params.c  | 4 
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c 
b/drivers/gpu/drm/i915/display/intel_crt.c
index 913e5d230a4d..0e33a0523a75 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -841,7 +841,7 @@ intel_crt_detect(struct drm_connector *connector,
if (!intel_display_device_enabled(dev_priv))
return connector_status_disconnected;
 
-   if (dev_priv->params.load_detect_test) {
+   if (dev_priv->display.params.load_detect_test) {
wakeref = intel_display_power_get(dev_priv,
  intel_encoder->power_domain);
goto load_detect;
@@ -901,7 +901,7 @@ intel_crt_detect(struct drm_connector *connector,
else if (DISPLAY_VER(dev_priv) < 4)
status = intel_crt_load_detect(crt,
to_intel_crtc(connector->state->crtc)->pipe);
-   else if (dev_priv->params.load_detect_test)
+   else if (dev_priv->display.params.load_detect_test)
status = connector_status_disconnected;
else
status = connector_status_unknown;
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 01b732819aab..3c0e93934ac2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -76,6 +76,10 @@ intel_display_param_named(enable_dpcd_backlight, int, 0400,
"Enable support for DPCD backlight control"
"(-1=use per-VBT LFP backlight type setting [default], 0=disabled, 
1=enable, 2=force VESA interface, 3=force Intel interface)");
 
+intel_display_param_named_unsafe(load_detect_test, bool, 0400,
+   "Force-enable the VGA load detect code for testing (default:false). "
+   "For developers only.");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 6c08ed07bb58..8b36b73437b2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -36,6 +36,7 @@ struct drm_i915_private;
param(int, invert_brightness, 0, 0600) \
param(int, edp_vswing, 0, 0400) \
param(int, enable_dpcd_backlight, -1, 0600) \
+   param(bool, load_detect_test, false, 0600) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index e15cd8491c7f..cb56973a2394 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -86,10 +86,6 @@ i915_param_named_unsafe(force_probe, charp, 0400,
"Force probe options for specified supported devices. "
"See CONFIG_DRM_I915_FORCE_PROBE for details.");
 
-i915_param_named_unsafe(load_detect_test, bool, 0400,
-   "Force-enable the VGA load detect code for testing (default:false). "
-   "For developers only.");
-
 i915_param_named_unsafe(force_reset_modeset_test, bool, 0400,
"Force a modeset during gpu reset for testing (default:false). "
"For developers only.");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 8169234338b1..cf5448bbc087 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -63,7 +63,6 @@ struct drm_printer;
param(unsigned int, lmem_bar_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
-   param(bool, load_detect_test, false, 0600) \
param(bool, force_reset_modeset_test, false, 0600) \
param(bool, error_capture, true, 
IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \
param(bool, disable_display, false, 0400) \
-- 
2.34.1

[Intel-gfx] [PATCH v2 18/24] drm/i915/display: Move force_reset_modeset_test parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display_params.c | 4 
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/display/intel_display_reset.c  | 2 +-
 drivers/gpu/drm/i915/i915_params.c  | 4 
 drivers/gpu/drm/i915/i915_params.h  | 2 +-
 5 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 3c0e93934ac2..7f330a5e1188 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -80,6 +80,10 @@ intel_display_param_named_unsafe(load_detect_test, bool, 
0400,
"Force-enable the VGA load detect code for testing (default:false). "
"For developers only.");
 
+intel_display_param_named_unsafe(force_reset_modeset_test, bool, 0400,
+   "Force a modeset during gpu reset for testing (default:false). "
+   "For developers only.");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 8b36b73437b2..25f238e63ff8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -37,6 +37,7 @@ struct drm_i915_private;
param(int, edp_vswing, 0, 0400) \
param(int, enable_dpcd_backlight, -1, 0600) \
param(bool, load_detect_test, false, 0600) \
+   param(bool, force_reset_modeset_test, false, 0600) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c 
b/drivers/gpu/drm/i915/display/intel_display_reset.c
index 17178d5d7788..c2c347b22448 100644
--- a/drivers/gpu/drm/i915/display/intel_display_reset.c
+++ b/drivers/gpu/drm/i915/display/intel_display_reset.c
@@ -29,7 +29,7 @@ void intel_display_reset_prepare(struct drm_i915_private 
*dev_priv)
return;
 
/* reset doesn't touch the display */
-   if (!dev_priv->params.force_reset_modeset_test &&
+   if (!dev_priv->display.params.force_reset_modeset_test &&
!gpu_reset_clobbers_display(dev_priv))
return;
 
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index cb56973a2394..497e39b1dcfb 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -86,10 +86,6 @@ i915_param_named_unsafe(force_probe, charp, 0400,
"Force probe options for specified supported devices. "
"See CONFIG_DRM_I915_FORCE_PROBE for details.");
 
-i915_param_named_unsafe(force_reset_modeset_test, bool, 0400,
-   "Force a modeset during gpu reset for testing (default:false). "
-   "For developers only.");
-
 i915_param_named(disable_display, bool, 0400,
"Disable display (default: false)");
 
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index cf5448bbc087..5fa77ecb8d31 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -63,7 +63,7 @@ struct drm_printer;
param(unsigned int, lmem_bar_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
-   param(bool, force_reset_modeset_test, false, 0600) \
+   param(bool, force_reset_modeset_test, false, 0600)  \
param(bool, error_capture, true, 
IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \
param(bool, disable_display, false, 0400) \
param(bool, verbose_state_checks, true, 0) \
-- 
2.34.1

[Intel-gfx] [PATCH v2 12/24] drm/i915/display: Move disable_power_well module parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display_params.c |  4 
 drivers/gpu/drm/i915/display/intel_display_params.h |  1 +
 drivers/gpu/drm/i915/display/intel_display_power.c  | 12 ++--
 drivers/gpu/drm/i915/i915_params.c  |  4 
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 5 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index efc311837ff1..86b46cff1718 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -53,6 +53,10 @@ intel_display_param_named_unsafe(enable_dpt, bool, 0400,
 intel_display_param_named_unsafe(enable_sagv, bool, 0600,
"Enable system agent voltage/frequency scaling (SAGV) (default: true)");
 
+intel_display_param_named_unsafe(disable_power_well, int, 0400,
+   "Disable display power wells when possible "
+   "(-1=auto [default], 0=power wells always on, 1=power wells disabled 
when possible)");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 06e920c9aa36..998f99a2857c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -31,6 +31,7 @@ struct drm_i915_private;
param(int, enable_dc, -1, 0400) \
param(bool, enable_dpt, true, 0400) \
param(bool, enable_sagv, true, 0600) \
+   param(int, disable_power_well, -1, 0400) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4832eb8da080..e390595d7341 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -967,7 +967,7 @@ static u32 get_allowed_dc_mask(const struct 
drm_i915_private *dev_priv,
DISPLAY_VER(dev_priv) >= 11 ?
   DC_STATE_EN_DC9 : 0;
 
-   if (!dev_priv->params.disable_power_well)
+   if (!dev_priv->display.params.disable_power_well)
max_dc = 0;
 
if (enable_dc >= 0 && enable_dc <= max_dc) {
@@ -1016,9 +1016,9 @@ int intel_power_domains_init(struct drm_i915_private 
*dev_priv)
 {
struct i915_power_domains *power_domains = 
&dev_priv->display.power.domains;
 
-   dev_priv->params.disable_power_well =
+   dev_priv->display.params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
-  
dev_priv->params.disable_power_well);
+  
dev_priv->display.params.disable_power_well);
power_domains->allowed_dc_mask =
get_allowed_dc_mask(dev_priv, 
dev_priv->display.params.enable_dc);
 
@@ -1950,7 +1950,7 @@ void intel_power_domains_init_hw(struct drm_i915_private 
*i915, bool resume)
intel_display_power_get(i915, POWER_DOMAIN_INIT);
 
/* Disable power support if the user asked so. */
-   if (!i915->params.disable_power_well) {
+   if (!i915->display.params.disable_power_well) {
drm_WARN_ON(&i915->drm, power_domains->disable_wakeref);
i915->display.power.domains.disable_wakeref = 
intel_display_power_get(i915,

  POWER_DOMAIN_INIT);
@@ -1977,7 +1977,7 @@ void intel_power_domains_driver_remove(struct 
drm_i915_private *i915)
fetch_and_zero(&i915->display.power.domains.init_wakeref);
 
/* Remove the refcount we took to keep power well support disabled. */
-   if (!i915->params.disable_power_well)
+   if (!i915->display.params.disable_power_well)
intel_display_power_put(i915, POWER_DOMAIN_INIT,

fetch_and_zero(&i915->display.power.domains.disable_wakeref));
 
@@ -2096,7 +2096,7 @@ void intel_power_domains_suspend(struct drm_i915_private 
*i915, bool s2idle)
 * Even if power well support was disabled we still want to disable
 * power wells if power domains must be deinitialized for suspend.
 */
-   if (!i915->params.disable_power_well)
+   if (!i915->display.params.disable_power_well)
intel_display_power_put(i915, POWER_DOMAIN_INIT,

fetch_and_zero(&i915->display.power.domains.disable_wakeref));
 
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 51e706f6e57e..eab02f71

[Intel-gfx] [PATCH v2 08/24] drm/i915/display: Move vbt_sdvo_panel_type module parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_bios.c   | 2 +-
 drivers/gpu/drm/i915/display/intel_display_params.c | 4 
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/i915_params.c  | 4 
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 4e8f1e91bb08..70c0491aac42 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1116,7 +1116,7 @@ parse_sdvo_panel_data(struct drm_i915_private *i915,
struct drm_display_mode *panel_fixed_mode;
int index;
 
-   index = i915->params.vbt_sdvo_panel_type;
+   index = i915->display.params.vbt_sdvo_panel_type;
if (index == -2) {
drm_dbg_kms(&i915->drm,
"Ignore SDVO panel mode from BIOS VBT tables.\n");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index e25d70653c0f..6a5be37ec3af 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -38,6 +38,10 @@ intel_display_param_named_unsafe(panel_use_ssc, int, 0400,
"Use Spread Spectrum Clock with panels [LVDS/eDP] "
"(default: auto from VBT)");
 
+intel_display_param_named_unsafe(vbt_sdvo_panel_type, int, 0400,
+   "Override/Ignore selection of SDVO panel mode in the VBT "
+   "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 4b326baf146f..c40a3cd57ffc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -27,6 +27,7 @@ struct drm_i915_private;
param(char *, vbt_firmware, NULL, 0400) \
param(int, lvds_channel_mode, 0, 0400) \
param(int, panel_use_ssc, -1, 0600) \
+   param(int, vbt_sdvo_panel_type, -1, 0400) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 4123424b2c2e..d0abcbd526a7 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -72,10 +72,6 @@ i915_param_named_unsafe(enable_dc, int, 0400,
"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
"3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
 
-i915_param_named_unsafe(vbt_sdvo_panel_type, int, 0400,
-   "Override/Ignore selection of SDVO panel mode in the VBT "
-   "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
-
 i915_param_named_unsafe(reset, uint, 0400,
"Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset 
[default])");
 
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 0bd365889e73..1ea332dfbb5d 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,6 @@ struct drm_printer;
  */
 #define I915_PARAMS_FOR_EACH(param) \
param(int, modeset, -1, 0400) \
-   param(int, vbt_sdvo_panel_type, -1, 0400) \
param(int, enable_dc, -1, 0400) \
param(bool, enable_dpt, true, 0400) \
param(bool, enable_sagv, true, 0600) \
-- 
2.34.1

[Intel-gfx] [PATCH v2 15/24] drm/i915/display: Move edp_vswing module parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_bios.c   | 4 ++--
 drivers/gpu/drm/i915/display/intel_display_params.c | 6 ++
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/i915_params.c  | 6 --
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 70c0491aac42..69db1a3a1499 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1514,9 +1514,9 @@ parse_edp(struct drm_i915_private *i915,
u8 vswing;
 
/* Don't read from VBT if module parameter has valid value*/
-   if (i915->params.edp_vswing) {
+   if (i915->display.params.edp_vswing) {
panel->vbt.edp.low_vswing =
-   i915->params.edp_vswing == 1;
+   i915->display.params.edp_vswing == 1;
} else {
vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) 
& 0xF;
panel->vbt.edp.low_vswing = vswing == 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 8d8050a22bf7..a16adfa36b64 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -66,6 +66,12 @@ intel_display_param_named_unsafe(invert_brightness, int, 
0400,
"to dri-de...@lists.freedesktop.org, if your machine needs it. "
"It will then be included in an upcoming module version.");
 
+/* WA to get away with the default setting in VBT for early platforms.Will be 
removed */
+intel_display_param_named_unsafe(edp_vswing, int, 0400,
+   "Ignore/Override vswing pre-emph table selection from VBT "
+   "(0=use value from vbt [default], 1=low power swing(200mV),"
+   "2=default swing(400mV))");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 23fa03ea38c9..9e749ea97707 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -34,6 +34,7 @@ struct drm_i915_private;
param(int, disable_power_well, -1, 0400) \
param(int, enable_ips, 1, 0600) \
param(int, invert_brightness, 0, 0600) \
+   param(int, edp_vswing, 0, 0400) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 423fe54484e1..6b9df9f9d842 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -111,12 +111,6 @@ i915_param_named(verbose_state_checks, bool, 0600,
 i915_param_named_unsafe(nuclear_pageflip, bool, 0400,
"Force enable atomic functionality on platforms that don't have full 
support yet.");
 
-/* WA to get away with the default setting in VBT for early platforms.Will be 
removed */
-i915_param_named_unsafe(edp_vswing, int, 0400,
-   "Ignore/Override vswing pre-emph table selection from VBT "
-   "(0=use value from vbt [default], 1=low power swing(200mV),"
-   "2=default swing(400mV))");
-
 i915_param_named_unsafe(enable_guc, int, 0400,
"Enable GuC load for GuC submission and/or HuC load. "
"Required functionality can be selected using bitmask values. "
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index ae0873443a65..c33edaee5032 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -55,7 +55,6 @@ struct drm_printer;
param(char *, gsc_firmware_path, NULL, 0400) \
param(bool, memtest, false, 0400) \
param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \
-   param(int, edp_vswing, 0, 0400) \
param(unsigned int, reset, 3, 0600) \
param(unsigned int, inject_probe_failure, 0, 0) \
param(int, enable_dpcd_backlight, -1, 0600) \
-- 
2.34.1

[Intel-gfx] [PATCH v2 16/24] drm/i915/display: Move enable_dpcd_backlightmodule parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display_params.c   | 4 
 drivers/gpu/drm/i915/display/intel_display_params.h   | 1 +
 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 4 ++--
 drivers/gpu/drm/i915/i915_params.c| 4 
 drivers/gpu/drm/i915/i915_params.h| 1 -
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index a16adfa36b64..01b732819aab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -72,6 +72,10 @@ intel_display_param_named_unsafe(edp_vswing, int, 0400,
"(0=use value from vbt [default], 1=low power swing(200mV),"
"2=default swing(400mV))");
 
+intel_display_param_named(enable_dpcd_backlight, int, 0400,
+   "Enable support for DPCD backlight control"
+   "(-1=use per-VBT LFP backlight type setting [default], 0=disabled, 
1=enable, 2=force VESA interface, 3=force Intel interface)");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 9e749ea97707..6c08ed07bb58 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -35,6 +35,7 @@ struct drm_i915_private;
param(int, enable_ips, 1, 0600) \
param(int, invert_brightness, 0, 0600) \
param(int, edp_vswing, 0, 0400) \
+   param(int, enable_dpcd_backlight, -1, 0600) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 95cc5251843e..1c2912ce59a5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -146,7 +146,7 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector 
*connector)
 * HDR static metadata we need to start maintaining table of
 * ranges for such panels.
 */
-   if (i915->params.enable_dpcd_backlight != 
INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL &&
+   if (i915->display.params.enable_dpcd_backlight != 
INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL &&
!(connector->base.hdr_sink_metadata.hdmi_type1.metadata_type &
  BIT(HDMI_STATIC_METADATA_TYPE1))) {
drm_info(&i915->drm,
@@ -489,7 +489,7 @@ int intel_dp_aux_init_backlight_funcs(struct 
intel_connector *connector)
/* Check the VBT and user's module parameters to figure out which
 * interfaces to probe
 */
-   switch (i915->params.enable_dpcd_backlight) {
+   switch (i915->display.params.enable_dpcd_backlight) {
case INTEL_DP_AUX_BACKLIGHT_OFF:
return -ENODEV;
case INTEL_DP_AUX_BACKLIGHT_AUTO:
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 6b9df9f9d842..e15cd8491c7f 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -140,10 +140,6 @@ i915_param_named_unsafe(inject_probe_failure, uint, 0400,
"Force an error after a number of failure check points (0:disabled 
(default), N:force failure at the Nth failure check point)");
 #endif
 
-i915_param_named(enable_dpcd_backlight, int, 0400,
-   "Enable support for DPCD backlight control"
-   "(-1=use per-VBT LFP backlight type setting [default], 0=disabled, 
1=enable, 2=force VESA interface, 3=force Intel interface)");
-
 #if IS_ENABLED(CONFIG_DRM_I915_GVT)
 i915_param_named(enable_gvt, bool, 0400,
"Enable support for Intel GVT-g graphics virtualization host 
support(default:false)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index c33edaee5032..8169234338b1 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -57,7 +57,6 @@ struct drm_printer;
param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \
param(unsigned int, reset, 3, 0600) \
param(unsigned int, inject_probe_failure, 0, 0) \
-   param(int, enable_dpcd_backlight, -1, 0600) \
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms, 
CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
param(unsigned int, lmem_size, 0, 0400) \
-- 
2.34.1

[Intel-gfx] [PATCH v2 11/24] drm/i915/display: Move enable_sagv module parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/display/skl_watermark.c| 5 +++--
 drivers/gpu/drm/i915/i915_params.c  | 3 ---
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 5 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 8f222b5bfd8d..efc311837ff1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -50,6 +50,9 @@ intel_display_param_named_unsafe(enable_dc, int, 0400,
 intel_display_param_named_unsafe(enable_dpt, bool, 0400,
"Enable display page table (DPT) (default: true)");
 
+intel_display_param_named_unsafe(enable_sagv, bool, 0600,
+   "Enable system agent voltage/frequency scaling (SAGV) (default: true)");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index c67ed16670c3..06e920c9aa36 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -30,6 +30,7 @@ struct drm_i915_private;
param(int, vbt_sdvo_panel_type, -1, 0400) \
param(int, enable_dc, -1, 0400) \
param(bool, enable_dpt, true, 0400) \
+   param(bool, enable_sagv, true, 0600) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c 
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 99b8ccdc3dfa..56588d6e24ae 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -412,7 +412,7 @@ static bool intel_crtc_can_enable_sagv(const struct 
intel_crtc_state *crtc_state
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
-   if (!i915->params.enable_sagv)
+   if (!i915->display.params.enable_sagv)
return false;
 
if (DISPLAY_VER(i915) >= 12)
@@ -3702,7 +3702,8 @@ static int intel_sagv_status_show(struct seq_file *m, 
void *unused)
};
 
seq_printf(m, "SAGV available: %s\n", str_yes_no(intel_has_sagv(i915)));
-   seq_printf(m, "SAGV modparam: %s\n", 
str_enabled_disabled(i915->params.enable_sagv));
+   seq_printf(m, "SAGV modparam: %s\n",
+  str_enabled_disabled(i915->display.params.enable_sagv));
seq_printf(m, "SAGV status: %s\n", 
sagv_status[i915->display.sagv.status]);
seq_printf(m, "SAGV block time: %d usec\n", 
i915->display.sagv.block_time_us);
 
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 773a0a709fc6..51e706f6e57e 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -82,9 +82,6 @@ i915_param_named_unsafe(enable_hangcheck, bool, 0400,
"WARNING: Disabling this can cause system wide hangs. "
"(default: true)");
 
-i915_param_named_unsafe(enable_sagv, bool, 0600,
-   "Enable system agent voltage/frequency scaling (SAGV) (default: true)");
-
 i915_param_named_unsafe(force_probe, charp, 0400,
"Force probe options for specified supported devices. "
"See CONFIG_DRM_I915_FORCE_PROBE for details.");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index b8728990cb8b..066f15783580 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,6 @@ struct drm_printer;
  */
 #define I915_PARAMS_FOR_EACH(param) \
param(int, modeset, -1, 0400) \
-   param(bool, enable_sagv, true, 0600) \
param(int, disable_power_well, -1, 0400) \
param(int, enable_ips, 1, 0600) \
param(int, invert_brightness, 0, 0600) \
-- 
2.34.1

[Intel-gfx] [PATCH v2 13/24] drm/i915/display: Move enable_ips module parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/hsw_ips.c  | 4 ++--
 drivers/gpu/drm/i915/display/intel_display_params.c | 2 ++
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/i915_params.c  | 2 --
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c 
b/drivers/gpu/drm/i915/display/hsw_ips.c
index 7dc38ac02092..611a7d6ef80c 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -193,7 +193,7 @@ bool hsw_crtc_state_ips_capable(const struct 
intel_crtc_state *crtc_state)
if (!hsw_crtc_supports_ips(crtc))
return false;
 
-   if (!i915->params.enable_ips)
+   if (!i915->display.params.enable_ips)
return false;
 
if (crtc_state->pipe_bpp > 24)
@@ -329,7 +329,7 @@ static int hsw_ips_debugfs_status_show(struct seq_file *m, 
void *unused)
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 
seq_printf(m, "Enabled by kernel parameter: %s\n",
-  str_yes_no(i915->params.enable_ips));
+  str_yes_no(i915->display.params.enable_ips));
 
if (DISPLAY_VER(i915) >= 8) {
seq_puts(m, "Currently: unknown\n");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 86b46cff1718..c2399e11203c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -57,6 +57,8 @@ intel_display_param_named_unsafe(disable_power_well, int, 
0400,
"Disable display power wells when possible "
"(-1=auto [default], 0=power wells always on, 1=power wells disabled 
when possible)");
 
+i915_param_named_unsafe(enable_ips, int, 0400, "Enable IPS (default: true)");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 998f99a2857c..11c21a3a3124 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -32,6 +32,7 @@ struct drm_i915_private;
param(bool, enable_dpt, true, 0400) \
param(bool, enable_sagv, true, 0600) \
param(int, disable_power_well, -1, 0400) \
+   param(int, enable_ips, 1, 0600) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index eab02f71a4e5..54dcce97da2a 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -86,8 +86,6 @@ i915_param_named_unsafe(force_probe, charp, 0400,
"Force probe options for specified supported devices. "
"See CONFIG_DRM_I915_FORCE_PROBE for details.");
 
-i915_param_named_unsafe(enable_ips, int, 0400, "Enable IPS (default: true)");
-
 i915_param_named_unsafe(load_detect_test, bool, 0400,
"Force-enable the VGA load detect code for testing (default:false). "
"For developers only.");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 060464df03c2..18bb8a93e0e8 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,6 @@ struct drm_printer;
  */
 #define I915_PARAMS_FOR_EACH(param) \
param(int, modeset, -1, 0400) \
-   param(int, enable_ips, 1, 0600) \
param(int, invert_brightness, 0, 0600) \
param(int, enable_guc, -1, 0400) \
param(int, guc_log_level, -1, 0400) \
-- 
2.34.1

[Intel-gfx] [PATCH v2 04/24] drm/i915/display: Move psr related module parameters under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 .../gpu/drm/i915/display/intel_display_params.c   | 15 +++
 .../gpu/drm/i915/display/intel_display_params.h   |  5 +
 drivers/gpu/drm/i915/display/intel_psr.c  | 14 +++---
 drivers/gpu/drm/i915/i915_params.c| 15 ---
 drivers/gpu/drm/i915/i915_params.h|  3 ---
 5 files changed, 27 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 330613cd64db..eac82deede4c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -31,6 +31,21 @@ intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
 
+intel_display_param_named_unsafe(enable_psr, int, 0400,
+   "Enable PSR "
+   "(0=disabled, 1=enable up to PSR1, 2=enable up to PSR2) "
+   "Default: -1 (use per-chip default)");
+
+intel_display_param_named(psr_safest_params, bool, 0400,
+   "Replace PSR VBT parameters by the safest and not optimal ones. This "
+   "is helpful to detect if PSR issues are related to bad values set in "
+   " VBT. (0=use VBT parameters, 1=use safest parameters)");
+
+intel_display_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400,
+   "Enable PSR2 selective fetch "
+   "(0=disabled, 1=enabled) "
+   "Default: 0");
+
 __maybe_unused
 static void _param_print_bool(struct drm_printer *p, const char *driver_name,
  const char *name, bool val)
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index f1bdf2c6e5cd..99b79bed9363 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -6,6 +6,8 @@
 #ifndef _INTEL_DISPLAY_PARAMS_H_
 #define _INTEL_DISPLAY_PARAMS_H_
 
+#include 
+
 struct drm_printer;
 struct drm_i915_private;
 
@@ -23,6 +25,9 @@ struct drm_i915_private;
  */
 #define INTEL_DISPLAY_PARAMS_FOR_EACH(param) \
param(int, enable_fbc, -1, 0600) \
+   param(int, enable_psr, -1, 0600) \
+   param(bool, psr_safest_params, false, 0400) \
+   param(bool, enable_psr2_sel_fetch, true, 0400) \
 
 #define MEMBER(T, member, ...) T member;
 struct intel_display_params {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 4f1f31fc9529..ecd24a0b86cb 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -179,9 +179,9 @@ static bool psr_global_enabled(struct intel_dp *intel_dp)
 
switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_DEFAULT:
-   if (i915->params.enable_psr == -1)
+   if (i915->display.params.enable_psr == -1)
return connector->panel.vbt.psr.enable;
-   return i915->params.enable_psr;
+   return i915->display.params.enable_psr;
case I915_PSR_DEBUG_DISABLE:
return false;
default:
@@ -198,7 +198,7 @@ static bool psr2_global_enabled(struct intel_dp *intel_dp)
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
default:
-   if (i915->params.enable_psr == 1)
+   if (i915->display.params.enable_psr == 1)
return false;
return true;
}
@@ -606,7 +606,7 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
if (DISPLAY_VER(dev_priv) >= 11)
val |= EDP_PSR_TP4_TIME_0us;
 
-   if (dev_priv->params.psr_safest_params) {
+   if (dev_priv->display.params.psr_safest_params) {
val |= EDP_PSR_TP1_TIME_2500us;
val |= EDP_PSR_TP2_TP3_TIME_2500us;
goto check_tp3_sel;
@@ -700,7 +700,7 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 val = 0;
 
-   if (dev_priv->params.psr_safest_params)
+   if (dev_priv->display.params.psr_safest_params)
return EDP_PSR2_TP2_TIME_2500us;
 
if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
@@ -943,7 +943,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct 
intel_dp *intel_dp,
 {
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-   if (!dev_priv->params.enable_psr2_sel_fetch &&
+   if (!dev_priv->display.params.enable_psr2_sel_fetch &&
intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
drm_dbg_kms(&dev_priv->drm,
"PSR2 sel fetch not enabled, disabled by 
parameter\n");
@@ -1056,7 +1056,7 @@ static bool _compute_psr2_wake_times(struct intel_dp 
*intel_dp,

[Intel-gfx] [PATCH v2 05/24] drm/i915/display: Move vbt_firmware module parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/display/intel_opregion.c   | 2 +-
 drivers/gpu/drm/i915/i915_params.c  | 3 ---
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index eac82deede4c..72f1782e27fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -27,6 +27,9 @@ static struct intel_display_params intel_display_modparams 
__read_mostly = {
  * debugfs mode to 0.
  */
 
+intel_display_param_named_unsafe(vbt_firmware, charp, 0400,
+   "Load VBT from specified file under /lib/firmware");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 99b79bed9363..a6f37c55523d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -24,6 +24,7 @@ struct drm_i915_private;
  *   debugfs file
  */
 #define INTEL_DISPLAY_PARAMS_FOR_EACH(param) \
+   param(char *, vbt_firmware, NULL, 0400) \
param(int, enable_fbc, -1, 0600) \
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
b/drivers/gpu/drm/i915/display/intel_opregion.c
index 84078fb82b2f..1ce785db6a5e 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -841,7 +841,7 @@ static int intel_load_vbt_firmware(struct drm_i915_private 
*dev_priv)
 {
struct intel_opregion *opregion = &dev_priv->display.opregion;
const struct firmware *fw = NULL;
-   const char *name = dev_priv->params.vbt_firmware;
+   const char *name = dev_priv->display.params.vbt_firmware;
int ret;
 
if (!name || !*name)
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index c65e3314ae48..9d0535d774c9 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -87,9 +87,6 @@ i915_param_named_unsafe(vbt_sdvo_panel_type, int, 0400,
 i915_param_named_unsafe(reset, uint, 0400,
"Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset 
[default])");
 
-i915_param_named_unsafe(vbt_firmware, charp, 0400,
-   "Load VBT from specified file under /lib/firmware");
-
 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 i915_param_named(error_capture, bool, 0400,
"Record the GPU state following a hang. "
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 47a05c4a8e89..37a1d31a233c 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -46,7 +46,6 @@ struct drm_printer;
  *   debugfs file
  */
 #define I915_PARAMS_FOR_EACH(param) \
-   param(char *, vbt_firmware, NULL, 0400) \
param(int, modeset, -1, 0400) \
param(int, lvds_channel_mode, 0, 0400) \
param(int, panel_use_ssc, -1, 0600) \
-- 
2.34.1

[Intel-gfx] [PATCH v2 06/24] drm/i915/display: Move lvds_channel_mode module parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display_params.c | 4 
 drivers/gpu/drm/i915/display/intel_display_params.h | 3 ++-
 drivers/gpu/drm/i915/display/intel_lvds.c   | 4 ++--
 drivers/gpu/drm/i915/i915_params.c  | 4 
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 72f1782e27fe..cdc42bc575b8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -30,6 +30,10 @@ static struct intel_display_params intel_display_modparams 
__read_mostly = {
 intel_display_param_named_unsafe(vbt_firmware, charp, 0400,
"Load VBT from specified file under /lib/firmware");
 
+intel_display_param_named_unsafe(lvds_channel_mode, int, 0400,
+"Specify LVDS channel mode "
+"(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index a6f37c55523d..a4988ef44837 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -25,7 +25,8 @@ struct drm_i915_private;
  */
 #define INTEL_DISPLAY_PARAMS_FOR_EACH(param) \
param(char *, vbt_firmware, NULL, 0400) \
-   param(int, enable_fbc, -1, 0600) \
+   param(int, lvds_channel_mode, 0, 0400) \
+   param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
param(bool, enable_psr2_sel_fetch, true, 0400) \
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c 
b/drivers/gpu/drm/i915/display/intel_lvds.c
index 2a4ca7e65775..4b114fde57b1 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -794,8 +794,8 @@ static bool compute_is_dual_link_lvds(struct 
intel_lvds_encoder *lvds_encoder)
unsigned int val;
 
/* use the module option value if specified */
-   if (i915->params.lvds_channel_mode > 0)
-   return i915->params.lvds_channel_mode == 2;
+   if (i915->display.params.lvds_channel_mode > 0)
+   return i915->display.params.lvds_channel_mode == 2;
 
/* single channel LVDS is limited to 112 MHz */
if (fixed_mode->clock > 112999)
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 9d0535d774c9..ea55cc2c4854 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -72,10 +72,6 @@ i915_param_named_unsafe(enable_dc, int, 0400,
"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
"3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
 
-i915_param_named_unsafe(lvds_channel_mode, int, 0400,
-"Specify LVDS channel mode "
-"(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
-
 i915_param_named_unsafe(panel_use_ssc, int, 0400,
"Use Spread Spectrum Clock with panels [LVDS/eDP] "
"(default: auto from VBT)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 37a1d31a233c..03ec2c2b589d 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,6 @@ struct drm_printer;
  */
 #define I915_PARAMS_FOR_EACH(param) \
param(int, modeset, -1, 0400) \
-   param(int, lvds_channel_mode, 0, 0400) \
param(int, panel_use_ssc, -1, 0600) \
param(int, vbt_sdvo_panel_type, -1, 0400) \
param(int, enable_dc, -1, 0400) \
-- 
2.34.1

[Intel-gfx] [PATCH v2 07/24] drm/i915/display: Move panel_use_ssc module parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_display_params.c | 4 
 drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
 drivers/gpu/drm/i915/display/intel_panel.c  | 4 ++--
 drivers/gpu/drm/i915/i915_params.c  | 4 
 drivers/gpu/drm/i915/i915_params.h  | 1 -
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index cdc42bc575b8..e25d70653c0f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -34,6 +34,10 @@ intel_display_param_named_unsafe(lvds_channel_mode, int, 
0400,
 "Specify LVDS channel mode "
 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
 
+intel_display_param_named_unsafe(panel_use_ssc, int, 0400,
+   "Use Spread Spectrum Clock with panels [LVDS/eDP] "
+   "(default: auto from VBT)");
+
 intel_display_param_named_unsafe(enable_fbc, int, 0400,
"Enable frame buffer compression for power savings "
"(default: -1 (use per-chip default))");
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index a4988ef44837..4b326baf146f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -26,6 +26,7 @@ struct drm_i915_private;
 #define INTEL_DISPLAY_PARAMS_FOR_EACH(param) \
param(char *, vbt_firmware, NULL, 0400) \
param(int, lvds_channel_mode, 0, 0400) \
+   param(int, panel_use_ssc, -1, 0600) \
param(int, enable_fbc, -1, 0600)\
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0400) \
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c 
b/drivers/gpu/drm/i915/display/intel_panel.c
index 483beedac5b8..0d8e5320a4f8 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -46,8 +46,8 @@
 
 bool intel_panel_use_ssc(struct drm_i915_private *i915)
 {
-   if (i915->params.panel_use_ssc >= 0)
-   return i915->params.panel_use_ssc != 0;
+   if (i915->display.params.panel_use_ssc >= 0)
+   return i915->display.params.panel_use_ssc != 0;
return i915->display.vbt.lvds_use_ssc &&
!intel_has_quirk(i915, QUIRK_LVDS_SSC_DISABLE);
 }
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index ea55cc2c4854..4123424b2c2e 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -72,10 +72,6 @@ i915_param_named_unsafe(enable_dc, int, 0400,
"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
"3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
 
-i915_param_named_unsafe(panel_use_ssc, int, 0400,
-   "Use Spread Spectrum Clock with panels [LVDS/eDP] "
-   "(default: auto from VBT)");
-
 i915_param_named_unsafe(vbt_sdvo_panel_type, int, 0400,
"Override/Ignore selection of SDVO panel mode in the VBT "
"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 03ec2c2b589d..0bd365889e73 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,6 @@ struct drm_printer;
  */
 #define I915_PARAMS_FOR_EACH(param) \
param(int, modeset, -1, 0400) \
-   param(int, panel_use_ssc, -1, 0600) \
param(int, vbt_sdvo_panel_type, -1, 0400) \
param(int, enable_dc, -1, 0400) \
param(bool, enable_dpt, true, 0400) \
-- 
2.34.1

[Intel-gfx] [PATCH v2 02/24] drm/i915/display: Dump also display parameters

[Jouni Högander]

GPU error dump contained all module parameters. If we are moving
display parameters to intel_display_params.[ch] they are not dumped
into GPU error dump. This patch is adding moved display parameters
back to GPU error dump. Display parameters are also included in
i915_capabilities

v2: Add parameters to i915_capabilities as well

Signed-off-by: Jouni Högander 
---
 .../drm/i915/display/intel_display_params.c   | 57 +++
 .../drm/i915/display/intel_display_params.h   |  3 +
 drivers/gpu/drm/i915/i915_debugfs.c   |  3 +
 drivers/gpu/drm/i915/i915_gpu_error.c |  3 +
 drivers/gpu/drm/i915/i915_gpu_error.h |  2 +
 5 files changed, 68 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 91953ae27144..11ee73a98b5b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -27,6 +27,63 @@ static struct intel_display_params intel_display_modparams 
__read_mostly = {
  * debugfs mode to 0.
  */
 
+__maybe_unused
+static void _param_print_bool(struct drm_printer *p, const char *driver_name,
+ const char *name, bool val)
+{
+   drm_printf(p, "%s.%s=%s\n", driver_name, name, str_yes_no(val));
+}
+
+__maybe_unused
+static void _param_print_int(struct drm_printer *p, const char *driver_name,
+const char *name, int val)
+{
+   drm_printf(p, "%s.%s=%d\n", driver_name, name, val);
+}
+
+__maybe_unused
+static void _param_print_uint(struct drm_printer *p, const char *driver_name,
+ const char *name, unsigned int val)
+{
+   drm_printf(p, "%s.%s=%u\n", driver_name, name, val);
+}
+
+__maybe_unused
+static void _param_print_ulong(struct drm_printer *p, const char *driver_name,
+  const char *name, unsigned long val)
+{
+   drm_printf(p, "%s.%s=%lu\n", driver_name, name, val);
+}
+
+__maybe_unused
+static void _param_print_charp(struct drm_printer *p, const char *driver_name,
+  const char *name, const char *val)
+{
+   drm_printf(p, "%s.%s=%s\n", driver_name, name, val);
+}
+
+#define _param_print(p, driver_name, name, val)\
+   _Generic(val,   \
+bool : _param_print_bool,  \
+int : _param_print_int,\
+unsigned int : _param_print_uint,  \
+unsigned long : _param_print_ulong,\
+char * : _param_print_charp)(p, driver_name, name, val)
+
+/**
+ * intel_display_params_dump - dump intel display modparams
+ * @i915: i915 device
+ * @p: the &drm_printer
+ *
+ * Pretty printer for i915 modparams.
+ */
+void intel_display_params_dump(struct drm_i915_private *i915, struct 
drm_printer *p)
+{
+#define PRINT(T, x, ...) _param_print(p, i915->drm.driver->name, #x, 
i915->display.params.x);
+   INTEL_DISPLAY_PARAMS_FOR_EACH(PRINT);
+#undef PRINT
+}
+
 __maybe_unused static void _param_dup_charp(char **valp)
 {
*valp = kstrdup(*valp ? *valp : "", GFP_ATOMIC);
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index 1b347365988c..a0fb3e1aa2f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -7,6 +7,7 @@
 #define _INTEL_DISPLAY_PARAMS_H_
 
 struct drm_printer;
+struct drm_i915_private;
 
 /*
  * Invoke param, a function-like macro, for each intel display param, with
@@ -28,6 +29,8 @@ struct intel_display_params {
 };
 #undef MEMBER
 
+void intel_display_params_dump(struct drm_i915_private *i915,
+  struct drm_printer *p);
 void intel_display_params_copy(struct intel_display_params *dest);
 void intel_display_params_free(struct intel_display_params *params);
 
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index e9b79c2c37d8..af0077f6a6d0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -32,6 +32,8 @@
 
 #include 
 
+#include "display/intel_display_params.h"
+
 #include "gem/i915_gem_context.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_buffer_pool.h"
@@ -74,6 +76,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
 
kernel_param_lock(THIS_MODULE);
i915_params_dump(&i915->params, &p);
+   intel_display_params_dump(i915, &p);
kernel_param_unlock(THIS_MODULE);
 
return 0;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index b4e31e59c799..8275f9b6a47d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -660,6 +660,7 @@ static void err_print_params(struct 
drm_i915_error_state_buf

[Intel-gfx] [PATCH v2 01/24] drm/i915/display: Add framework to add parameters specific to display

[Jouni Högander]

Currently all module parameters are handled by i915_param.c/h. This
is a problem for display parameters when Xe driver is used. Add
a mechanism to add parameters specific to the display. This is mainly
copied from i915_[debugfs]_params.[ch]. Parameters are not yet moved. This
is done by subsequent patches.

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/Makefile |   2 +
 .../gpu/drm/i915/display/intel_display_core.h |   2 +
 .../drm/i915/display/intel_display_debugfs.c  |   2 +
 .../display/intel_display_debugfs_params.c| 176 ++
 .../display/intel_display_debugfs_params.h|  14 ++
 .../drm/i915/display/intel_display_device.c   |   8 +
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_params.c   |  71 +++
 .../drm/i915/display/intel_display_params.h   |  34 
 drivers/gpu/drm/i915/i915_driver.c|   2 +
 10 files changed, 312 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_debugfs_params.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_params.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_params.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 88b2bb005014..3b9dcb606fc1 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -95,6 +95,7 @@ i915-$(CONFIG_DEBUG_FS) += \
i915_debugfs.o \
i915_debugfs_params.o \
display/intel_display_debugfs.o \
+   display/intel_display_debugfs_params.o \
display/intel_pipe_crc.o
 i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
 
@@ -257,6 +258,7 @@ i915-y += \
display/intel_display.o \
display/intel_display_driver.o \
display/intel_display_irq.o \
+   display/intel_display_params.o \
display/intel_display_power.o \
display/intel_display_power_map.o \
display/intel_display_power_well.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h 
b/drivers/gpu/drm/i915/display/intel_display_core.h
index ccfe27630fb6..aa8be02c9e54 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -19,6 +19,7 @@
 #include "intel_cdclk.h"
 #include "intel_display_device.h"
 #include "intel_display_limits.h"
+#include "intel_display_params.h"
 #include "intel_display_power.h"
 #include "intel_dpll_mgr.h"
 #include "intel_fbc.h"
@@ -520,6 +521,7 @@ struct intel_display {
struct intel_hotplug hotplug;
struct intel_opregion opregion;
struct intel_overlay *overlay;
+   struct intel_display_params params;
struct intel_vbt_data vbt;
struct intel_wm wm;
 };
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index fbe75d47a165..e219034d9c3d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -17,6 +17,7 @@
 #include "intel_de.h"
 #include "intel_crtc_state_dump.h"
 #include "intel_display_debugfs.h"
+#include "intel_display_debugfs_params.h"
 #include "intel_display_power.h"
 #include "intel_display_power_well.h"
 #include "intel_display_types.h"
@@ -1098,6 +1099,7 @@ void intel_display_debugfs_register(struct 
drm_i915_private *i915)
intel_hpd_debugfs_register(i915);
intel_psr_debugfs_register(i915);
intel_wm_debugfs_register(i915);
+   intel_display_debugfs_params(i915);
 }
 
 static int i915_panel_show(struct seq_file *m, void *data)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
new file mode 100644
index ..b7e68eb62452
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include 
+
+#include 
+
+#include "intel_display_debugfs_params.h"
+#include "i915_drv.h"
+#include "intel_display_params.h"
+
+/* int param */
+static int intel_display_param_int_show(struct seq_file *m, void *data)
+{
+   int *value = m->private;
+
+   seq_printf(m, "%d\n", *value);
+
+   return 0;
+}
+
+static int intel_display_param_int_open(struct inode *inode, struct file *file)
+{
+   return single_open(file, intel_display_param_int_show, 
inode->i_private);
+}
+
+static ssize_t intel_display_param_int_write(struct file *file,
+const char __user *ubuf, size_t 
len,
+loff_t *offp)
+{
+   struct seq_file *m = file->private_data;
+   int *value = m->private;
+   int ret;
+
+   ret = kstrtoint_from_user(ubuf, len, 0, value);
+   if (ret) {
+   /* support boolean values too */
+   bool 

[Intel-gfx] [PATCH v2 03/24] drm/i915/display: Move enable_fbc module parameter under display

[Jouni Högander]

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/i9xx_wm.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_display_params.c |  4 
 drivers/gpu/drm/i915/display/intel_display_params.h |  3 ++-
 drivers/gpu/drm/i915/display/intel_fbc.c| 10 +-
 drivers/gpu/drm/i915/i915_params.c  |  4 
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 6 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c 
b/drivers/gpu/drm/i915/display/i9xx_wm.c
index af0c79a4c9a4..b37c0d02d500 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -2993,7 +2993,7 @@ static void ilk_wm_merge(struct drm_i915_private 
*dev_priv,
 
/* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
if (DISPLAY_VER(dev_priv) == 5 && HAS_FBC(dev_priv) &&
-   dev_priv->params.enable_fbc && !merged->fbc_wm_enabled) {
+   dev_priv->display.params.enable_fbc && !merged->fbc_wm_enabled) {
for (level = 2; level < num_levels; level++) {
struct intel_wm_level *wm = &merged->wm[level];
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c 
b/drivers/gpu/drm/i915/display/intel_display_params.c
index 11ee73a98b5b..330613cd64db 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.c
+++ b/drivers/gpu/drm/i915/display/intel_display_params.c
@@ -27,6 +27,10 @@ static struct intel_display_params intel_display_modparams 
__read_mostly = {
  * debugfs mode to 0.
  */
 
+intel_display_param_named_unsafe(enable_fbc, int, 0400,
+   "Enable frame buffer compression for power savings "
+   "(default: -1 (use per-chip default))");
+
 __maybe_unused
 static void _param_print_bool(struct drm_printer *p, const char *driver_name,
  const char *name, bool val)
diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h 
b/drivers/gpu/drm/i915/display/intel_display_params.h
index a0fb3e1aa2f5..f1bdf2c6e5cd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_params.h
+++ b/drivers/gpu/drm/i915/display/intel_display_params.h
@@ -21,7 +21,8 @@ struct drm_i915_private;
  * mode: debugfs file permissions, one of {0400, 0600, 0}, use 0 to not create
  *   debugfs file
  */
-#define INTEL_DISPLAY_PARAMS_FOR_EACH(param)
+#define INTEL_DISPLAY_PARAMS_FOR_EACH(param) \
+   param(int, enable_fbc, -1, 0600) \
 
 #define MEMBER(T, member, ...) T member;
 struct intel_display_params {
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 4820d21cc942..bde12fe62275 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1174,7 +1174,7 @@ static int intel_fbc_check_plane(struct 
intel_atomic_state *state,
return 0;
}
 
-   if (!i915->params.enable_fbc) {
+   if (!i915->display.params.enable_fbc) {
plane_state->no_fbc_reason = "disabled per module param or by 
default";
return 0;
}
@@ -1751,8 +1751,8 @@ void intel_fbc_handle_fifo_underrun_irq(struct 
drm_i915_private *i915)
  */
 static int intel_sanitize_fbc_option(struct drm_i915_private *i915)
 {
-   if (i915->params.enable_fbc >= 0)
-   return !!i915->params.enable_fbc;
+   if (i915->display.params.enable_fbc >= 0)
+   return !!i915->display.params.enable_fbc;
 
if (!HAS_FBC(i915))
return 0;
@@ -1824,9 +1824,9 @@ void intel_fbc_init(struct drm_i915_private *i915)
if (need_fbc_vtd_wa(i915))
DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
 
-   i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
+   i915->display.params.enable_fbc = intel_sanitize_fbc_option(i915);
drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
-   i915->params.enable_fbc);
+   i915->display.params.enable_fbc);
 
for_each_fbc_id(i915, fbc_id)
i915->display.fbc[fbc_id] = intel_fbc_create(i915, fbc_id);
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 036c4c3ed6ed..42700b854b79 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -72,10 +72,6 @@ i915_param_named_unsafe(enable_dc, int, 0400,
"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
"3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
 
-i915_param_named_unsafe(enable_fbc, int, 0400,
-   "Enable frame buffer compression for power savings "
-   "(default: -1 (use per-chip default))");
-
 i915_param_named_unsafe(lvds_channel_mode, int, 0400,
 "Specify LVDS channel mode "
 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index d5194b039aab.

[Intel-gfx] [PATCH v2 00/24] Framework for display parameters

[Jouni Högander]

Currently all module parameters are handled by i915_param.c/h. This
is a problem for display parameters when Xe driver is used.

This patch set adds a mechanism to add parameters specific to the
display. This is mainly copied from existing i915 parameters
implementation with some naming changes and taking into account
varying driver name.

Also all display specific module parameters are moved under display and the
module parameter are all converted as non-writable. This should be ok
as we have writable device parameters under debugfs.

v2:
  - Drop fastboot parameter
  - Include display parameters into i915_capabilities debugfs interface

Cc: Jani Nikula 
Cc: Uma Shankar 
Cc: Maarten Lankhorst 
Cc: Ville Syrjälä 
Cc: Rodrigo Vivi 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 

Jouni Högander (24):
  drm/i915/display: Add framework to add parameters specific to display
  drm/i915/display: Dump also display parameters
  drm/i915/display: Move enable_fbc module parameter under display
  drm/i915/display: Move psr related module parameters under display
  drm/i915/display: Move vbt_firmware module parameter under display
  drm/i915/display: Move lvds_channel_mode module parameter under
display
  drm/i915/display: Move panel_use_ssc module parameter under display
  drm/i915/display: Move vbt_sdvo_panel_type module parameter under
display
  drm/i915/display: Move enable_dc module parameter under display
  drm/i915/display: Move enable_dpt module parameter under display
  drm/i915/display: Move enable_sagv module parameter under display
  drm/i915/display: Move disable_power_well module parameter under
display
  drm/i915/display: Move enable_ips module parameter under display
  drm/i915/display: Move invert_brightness module parameter under
display
  drm/i915/display: Move edp_vswing module parameter under display
  drm/i915/display: Move enable_dpcd_backlightmodule parameter under
display
  drm/i915/display: Move load_detect_test parameter under display
  drm/i915/display: Move force_reset_modeset_test parameter under
display
  drm/i915/display: Move disable_display parameter under display
  drm/i915/display: Use device parameters instead of module in
I915_STATE_WARN
  drm/i915/display: Move verbose_state_checks under display
  drm/i915/display: Move nuclear_pageflip under display
  drm/i915/display: Move enable_dp_mst under display
  drm/i915/display: Use same permissions for enable_sagv as for rest

 drivers/gpu/drm/i915/Makefile |   2 +
 drivers/gpu/drm/i915/display/hsw_ips.c|   4 +-
 drivers/gpu/drm/i915/display/i9xx_wm.c|   2 +-
 .../gpu/drm/i915/display/intel_backlight.c|   9 +-
 drivers/gpu/drm/i915/display/intel_bios.c |   6 +-
 drivers/gpu/drm/i915/display/intel_crt.c  |   4 +-
 drivers/gpu/drm/i915/display/intel_display.h  |   2 +-
 .../gpu/drm/i915/display/intel_display_core.h |   2 +
 .../drm/i915/display/intel_display_debugfs.c  |   2 +
 .../display/intel_display_debugfs_params.c| 176 ++
 .../display/intel_display_debugfs_params.h|  14 ++
 .../drm/i915/display/intel_display_device.c   |  13 +-
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_params.c   | 216 ++
 .../drm/i915/display/intel_display_params.h   |  61 +
 .../drm/i915/display/intel_display_power.c|  14 +-
 .../drm/i915/display/intel_display_reset.c|   2 +-
 drivers/gpu/drm/i915/display/intel_dp.c   |   6 +-
 .../drm/i915/display/intel_dp_aux_backlight.c |   4 +-
 drivers/gpu/drm/i915/display/intel_dpt.c  |   6 +-
 drivers/gpu/drm/i915/display/intel_fb.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_fbc.c  |  10 +-
 drivers/gpu/drm/i915/display/intel_lvds.c |   4 +-
 drivers/gpu/drm/i915/display/intel_opregion.c |   2 +-
 drivers/gpu/drm/i915/display/intel_panel.c|   4 +-
 drivers/gpu/drm/i915/display/intel_psr.c  |  14 +-
 .../drm/i915/display/skl_universal_plane.c|   2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c  |   5 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |   3 +
 drivers/gpu/drm/i915/i915_driver.c|   2 +
 drivers/gpu/drm/i915/i915_gpu_error.c |   3 +
 drivers/gpu/drm/i915/i915_gpu_error.h |   2 +
 drivers/gpu/drm/i915/i915_params.c|  89 
 drivers/gpu/drm/i915/i915_params.h|  22 --
 34 files changed, 548 insertions(+), 162 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_debugfs_params.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_debugfs_params.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_params.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_params.h

-- 
2.34.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence

[Patchwork]

== Series Details ==

Series: drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence
URL   : https://patchwork.freedesktop.org/series/125160/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13756 -> Patchwork_125160v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v1/index.html

Participating hosts (34 -> 22)
--

  Additional (1): fi-apl-guc 
  Missing(13): fi-kbl-7567u fi-rkl-11600 bat-dg2-14 bat-dg2-8 bat-adlm-1 
bat-dg2-9 bat-adlp-6 fi-snb-2520m fi-bsw-nick fi-cfl-8109u fi-pnv-d510 
bat-rplp-1 bat-jsl-3 

Known issues


  Here are the changes found in Patchwork_125160v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 
other tests skip
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@kms_hdmi_inject@inject-audio:
- fi-apl-guc: NOTRUN -> [SKIP][2] ([fdo#109271]) +16 other tests 
skip
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v1/fi-apl-guc/igt@kms_hdmi_inj...@inject-audio.html

  
 Possible fixes 

  * igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [FAIL][3] ([IGT#3]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13756/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v1/fi-kbl-guc/igt@kms_hdmi_inj...@inject-audio.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613


Build changes
-

  * Linux: CI_DRM_13756 -> Patchwork_125160v1

  CI-20190529: 20190529
  CI_DRM_13756: c8e15d10895c44b271894850429c74500511cd1c @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7539: 08e87a32fa113a9b6f30cbd9766fec346b53faac @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_125160v1: c8e15d10895c44b271894850429c74500511cd1c @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

2fdff34d550f drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125160v1/index.html

Re: [Intel-gfx] [PATCH 06/10] drm/i915/spi: spi register with mtd

[Miquel Raynal]

Hi Alexander,

> +static int i915_spi_init_mtd(struct i915_spi *spi, struct device *device,
> +  unsigned int nparts)
> +{
> + unsigned int i;
> + unsigned int n;
> + struct mtd_partition *parts = NULL;
> + int ret;
> +
> + dev_dbg(device, "registering with mtd\n");
> +
> + spi->mtd.owner = THIS_MODULE;
> + spi->mtd.dev.parent = device;
> + spi->mtd.flags = MTD_CAP_NORFLASH | MTD_WRITEABLE;
> + spi->mtd.type = MTD_DATAFLASH;
> + spi->mtd.priv = spi;
> + spi->mtd._write = i915_spi_write;
> + spi->mtd._read = i915_spi_read;
> + spi->mtd._erase = i915_spi_erase;
> + spi->mtd._get_device = i915_spi_get_device;
> + spi->mtd._put_device = i915_spi_put_device;
> + spi->mtd.writesize = SZ_1; /* 1 byte granularity */

You say writesize should be aligned with 4 in your next patch?

> + spi->mtd.erasesize = SZ_4K; /* 4K bytes granularity */
> + spi->mtd.size = spi->size;
> +
> + parts = kcalloc(spi->nregions, sizeof(*parts), GFP_KERNEL);
> + if (!parts)
> + return -ENOMEM;
> +
> + for (i = 0, n = 0; i < spi->nregions && n < nparts; i++) {
> + if (!spi->regions[i].is_readable)
> + continue;
> + parts[n].name = spi->regions[i].name;
> + parts[n].offset  = spi->regions[i].offset;
> + parts[n].size = spi->regions[i].size;
> + if (!spi->regions[i].is_writable)
> + parts[n].mask_flags = MTD_WRITEABLE;
> + n++;
> + }
> +
> + ret = mtd_device_register(&spi->mtd, parts, n);
> +
> + kfree(parts);
> +
> + return ret;
> +}
> +

Thanks,
Miquèl

[Intel-gfx] [PATCH] drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence

[Jouni Högander]

We are preparing for Xe driver. Xe driver doesn't have i915_sw_fence
implementation. Lets drop i915_sw_fence usage from display code and
use dma_fence interfaces directly.

For this purpose stack dma fences from related objects into old and new
plane states using drm_gem_plane_helper_prepare_fb. Then wait for these
stacked fences during atomic commit.

There is no be need for separate GPU reset handling in
intel_atomic_commit_fence_wait as the fences are signaled when GPU hang is
detected and GPU is being reset.

Cc: Ville Syrjälä 
Cc: Maarten Lankhorst 
Cc: José Roberto de Souza 

Signed-off-by: Jouni Högander 
---
 drivers/gpu/drm/i915/display/intel_atomic.c   |  3 -
 .../gpu/drm/i915/display/intel_atomic_plane.c | 49 +++-
 drivers/gpu/drm/i915/display/intel_display.c  | 78 ++-
 .../drm/i915/display/intel_display_types.h|  2 -
 4 files changed, 37 insertions(+), 95 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c 
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 5d18145da279..ec0d5168b503 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -331,9 +331,6 @@ void intel_atomic_state_free(struct drm_atomic_state 
*_state)
 
drm_atomic_state_default_release(&state->base);
kfree(state->global_objs);
-
-   i915_sw_fence_fini(&state->commit_ready);
-
kfree(state);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index b1074350616c..d4f9168ec42c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -32,6 +32,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 
@@ -1035,7 +1036,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
struct intel_atomic_state *state =
to_intel_atomic_state(new_plane_state->uapi.state);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-   const struct intel_plane_state *old_plane_state =
+   struct intel_plane_state *old_plane_state =
intel_atomic_get_old_plane_state(state, plane);
struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
struct drm_i915_gem_object *old_obj = 
intel_fb_obj(old_plane_state->hw.fb);
@@ -1057,56 +1058,30 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
 * This should only fail upon a hung GPU, in which case we
 * can safely continue.
 */
-   if (new_crtc_state && intel_crtc_needs_modeset(new_crtc_state)) 
{
-   ret = 
i915_sw_fence_await_reservation(&state->commit_ready,
- 
old_obj->base.resv,
- false, 0,
- GFP_KERNEL);
+   if (new_crtc_state && intel_crtc_needs_modeset(new_crtc_state) 
&&
+   !dma_resv_test_signaled(old_obj->base.resv,
+   dma_resv_usage_rw(false))) {
+   ret = drm_gem_plane_helper_prepare_fb(_plane, 
&old_plane_state->uapi);
if (ret < 0)
return ret;
}
}
 
-   if (new_plane_state->uapi.fence) { /* explicit fencing */
-   i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
-&attr);
-   ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
-   new_plane_state->uapi.fence,
-   
i915_fence_timeout(dev_priv),
-   GFP_KERNEL);
-   if (ret < 0)
-   return ret;
-   }
-
if (!obj)
return 0;
 
-
ret = intel_plane_pin_fb(new_plane_state);
if (ret)
return ret;
 
-   i915_gem_object_wait_priority(obj, 0, &attr);
-
-   if (!new_plane_state->uapi.fence) { /* implicit fencing */
-   struct dma_resv_iter cursor;
-   struct dma_fence *fence;
+   ret = drm_gem_plane_helper_prepare_fb(_plane, &new_plane_state->uapi);
+   if (ret < 0)
+   goto unpin_fb;
 
-   ret = i915_sw_fence_await_reservation(&state->commit_ready,
- obj->base.resv, false,
- 
i915_fence_timeout(dev_priv),
- GFP_KERNEL);
-   if (ret < 0)
-   goto unpin_fb;
+   if (new_plane_state->uapi.fence) {
+   i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
+&attr);
 
-  

Re: [Intel-gfx] [PATCH] drm/i915/gem: Allow users to disable waitboost

[Tvrtko Ursulin]

On 13/10/2023 21:51, Rodrigo Vivi wrote:

On Thu, Sep 28, 2023 at 01:48:34PM +0100, Tvrtko Ursulin wrote:


On 27/09/2023 20:34, Belgaumkar, Vinay wrote:


On 9/21/2023 3:41 AM, Tvrtko Ursulin wrote:


On 20/09/2023 22:56, Vinay Belgaumkar wrote:

Provide a bit to disable waitboost while waiting on a gem object.
Waitboost results in increased power consumption by requesting RP0
while waiting for the request to complete. Add a bit in the gem_wait()
IOCTL where this can be disabled.

This is related to the libva API change here -
Link: 
https://github.com/XinfengZhang/libva/commit/3d90d18c67609a73121bb71b20ee4776b54b61a7


This link does not appear to lead to userspace code using this uapi?

We have asked Carl (cc'd) to post a patch for the same.


Ack.


I'm glad to see that we will have the end-to-end flow of the high-level API.




Cc: Rodrigo Vivi 
Signed-off-by: Vinay Belgaumkar 
---
   drivers/gpu/drm/i915/gem/i915_gem_wait.c | 9 ++---
   drivers/gpu/drm/i915/i915_request.c  | 3 ++-
   drivers/gpu/drm/i915/i915_request.h  | 1 +
   include/uapi/drm/i915_drm.h  | 1 +
   4 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
index d4b918fb11ce..955885ec859d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c
@@ -72,7 +72,8 @@ i915_gem_object_wait_reservation(struct
dma_resv *resv,
   struct dma_fence *fence;
   long ret = timeout ?: 1;
   -    i915_gem_object_boost(resv, flags);
+    if (!(flags & I915_WAITBOOST_DISABLE))
+    i915_gem_object_boost(resv, flags);
     dma_resv_iter_begin(&cursor, resv,
   dma_resv_usage_rw(flags & I915_WAIT_ALL));
@@ -236,7 +237,7 @@ i915_gem_wait_ioctl(struct drm_device *dev,
void *data, struct drm_file *file)
   ktime_t start;
   long ret;
   -    if (args->flags != 0)
+    if (args->flags != 0 || args->flags != I915_GEM_WAITBOOST_DISABLE)
   return -EINVAL;
     obj = i915_gem_object_lookup(file, args->bo_handle);
@@ -248,7 +249,9 @@ i915_gem_wait_ioctl(struct drm_device *dev,
void *data, struct drm_file *file)
   ret = i915_gem_object_wait(obj,
  I915_WAIT_INTERRUPTIBLE |
  I915_WAIT_PRIORITY |
-   I915_WAIT_ALL,
+   I915_WAIT_ALL |
+   (args->flags & I915_GEM_WAITBOOST_DISABLE ?
+    I915_WAITBOOST_DISABLE : 0),
  to_wait_timeout(args->timeout_ns));
     if (args->timeout_ns > 0) {
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index f59081066a19..2957409b4b2a 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -2044,7 +2044,8 @@ long i915_request_wait_timeout(struct
i915_request *rq,
    * but at a cost of spending more power processing the workload
    * (bad for battery).
    */
-    if (flags & I915_WAIT_PRIORITY && !i915_request_started(rq))
+    if (!(flags & I915_WAITBOOST_DISABLE) && (flags &
I915_WAIT_PRIORITY) &&
+    !i915_request_started(rq))
   intel_rps_boost(rq);
     wait.tsk = current;
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index 0ac55b2e4223..3cc00e8254dc 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -445,6 +445,7 @@ long i915_request_wait(struct i915_request *rq,
   #define I915_WAIT_INTERRUPTIBLE    BIT(0)
   #define I915_WAIT_PRIORITY    BIT(1) /* small priority bump
for the request */
   #define I915_WAIT_ALL    BIT(2) /* used by
i915_gem_object_wait() */
+#define I915_WAITBOOST_DISABLE    BIT(3) /* used by


maybe name it I915_WAIT_NO_BOOST to align a bit better with the existent ones?


I thought it would be better to not mention wait boost in the uapi, but 
leave it as implementation detail.


My suggestion was along the lines of I915_GEM_WAIT_BACKGROUND/IDLE.

In essence saying allowing userspace to say this is not an important 
wait. Yes, it implies that other waits are (more) important, but I think 
this is still better than starting to mention wait boost in the uapi. 
Since that would kind of cement it exists, while we always just viewed 
it as an "go faster" driver internal heuristics and could freely decide 
not to employ it even for default waits.


Historically even we had a period when waits were getting elevated 
scheduling priority. We removed it, would have to dig through git and 
email history to remember exactly why, but probably along the lines that 
it is not always justified. Same as waitboost is not always justified 
and can be harmful.


So I think a generic name for the uapi leaves more freedom for the 
driver. Might be a wrong name that I am suggesting and should be 
something else, not sure.


[Comes back later.]

eec39e441c29 ("drm/i915: Remove wait priority boosting")

Re: [Intel-gfx] [PATCH v2] drm/i915: Flush WC GGTT only on required platforms

[Nirmoy Das]

Hi Andi,

On 10/14/2023 10:51 AM, Andi Shyti wrote:

Hi Nirmoy,

On Fri, Oct 13, 2023 at 03:44:39PM +0200, Nirmoy Das wrote:

gen8_ggtt_invalidate() is only needed for limited set of platforms
where GGTT is mapped as WC otherwise this can cause unwanted
side-effects on XE_HP platforms where GFX_FLSH_CNTL_GEN6 is not
valid.

v2: Add a func to detect wc ggtt detection (Ville)

Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Cc: Rodrigo Vivi 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
Cc: Jani Nikula 
Cc: Jonathan Cavitt 
Cc: John Harrison 
Cc: Andi Shyti 
Cc: Ville Syrjälä 
Cc:  # v6.2+
Suggested-by: Matt Roper 
Signed-off-by: Nirmoy Das 
Acked-by: Andi Shyti 

I took some time to look at this and you can swap the a-b with
an r-b:

Reviewed-by: Andi Shyti 


Thanks! Going to resend one more rev with commit that is started using 
this register for WC mapping.



Regards,

Nirmoy



Thanks,
Andi

Re: [Intel-gfx] [PATCH] drm/i915: Flush WC GGTT only on required platforms

[Nirmoy Das]

On 10/13/2023 6:15 PM, Daniel Vetter wrote:

On Fri, Oct 13, 2023 at 02:28:21PM +0200, Nirmoy Das wrote:

Hi Ville,

On 10/13/2023 12:50 PM, Ville Syrjälä wrote:

On Fri, Oct 13, 2023 at 12:31:40PM +0200, Nirmoy Das wrote:

gen8_ggtt_invalidate() is only needed for limitted set of platforms
where GGTT is mapped as WC

I know there is supposed to be some kind hw snooping of the ggtt
pte writes to invalidate the tlb, but are we sure GFX_FLSH_CNTL
has no other side effects we depend on?

I spent some time searching through the gfxspec. This GFX_FLSH_CNTL register
only seems to be for

invalidating TLB for GUnit  and (from git log ) we started to do that to
enable WC based GGTT updates.

Might be good to cite the relevant git commits in the commit message to
make this clear.


Yes, I should. It took me a while to find it. Going to add that and 
resend the patch.



Thanks,

Nirmoy


-Sima



So if I am not missing anything obvious then this should be safe.


Regards,

Nirmoy


otherwise this can cause unwanted
side-effects on XE_HP platforms where GFX_FLSH_CNTL_GEN6 is not
valid.

Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Cc: Rodrigo Vivi 
Cc: Tvrtko Ursulin 
Cc: Joonas Lahtinen 
Cc: Jani Nikula 
Cc: Jonathan Cavitt 
Cc: John Harrison 
Cc: Andi Shyti 
Cc:  # v6.2+
Suggested-by: Matt Roper 
Signed-off-by: Nirmoy Das 
---
   drivers/gpu/drm/i915/gt/intel_ggtt.c | 6 +-
   1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c 
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 4d7d88b92632..c2858d434bce 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -197,13 +197,17 @@ void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
   static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
   {
+   struct drm_i915_private *i915 = ggtt->vm.i915;
struct intel_uncore *uncore = ggtt->vm.gt->uncore;
/*
 * Note that as an uncached mmio write, this will flush the
 * WCB of the writes into the GGTT before it triggers the invalidate.
+*
+* Only perform this when GGTT is mapped as WC, see ggtt_probe_common().
 */
-   intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
+   if (!IS_GEN9_LP(i915) && GRAPHICS_VER(i915) < 11)
+   intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, 
GFX_FLSH_CNTL_EN);
   }
   static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
--
2.41.0