Re: [PATCH 3/6] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP
On 2/16/2024 7:50 PM, Mitul Golani wrote:
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]
--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 95 ++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 12 ++-
drivers/gpu/drm/i915/i915_reg.h | 8 ++
include/drm/display/drm_dp.h | 2 +-
include/drm/display/drm_dp_helper.h | 2 +
5 files changed, 114 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 217196196e50..d68fb9d45054 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -95,7 +95,6 @@
#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
-
/* Constants for DP DSC configurations */
static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
@@ -4089,6 +4088,34 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
return false;
}
+static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
+ struct dp_sdp *sdp, size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ /* Prepare AS (Adaptive Sync) SDP Header */
+ sdp->sdp_header.HB0 = 0;
+ sdp->sdp_header.HB1 = as_sdp->sdp_type;
+ sdp->sdp_header.HB2 = 0x02;
+ sdp->sdp_header.HB3 = as_sdp->length;
+
+ /* Fill AS (Adaptive Sync) SDP Payload */
+ sdp->db[1] = 0x0;
+ sdp->db[1] = as_sdp->vtotal & 0xFF;
+ sdp->db[2] = (as_sdp->vtotal >> 8) & 0xF;
+ sdp->db[3] = 0x0;
+ sdp->db[4] = 0x0;
+ sdp->db[7] = 0x0;
+ sdp->db[8] = 0x0;
+
+ return length;
+}
+
static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
struct dp_sdp *sdp, size_t size)
{
@@ -4256,6 +4283,10 @@ static void intel_write_dp_sdp(struct intel_encoder
*encoder,
_state->infoframes.drm.drm,
,
sizeof(sdp));
break;
+ case DP_SDP_ADAPTIVE_SYNC:
+ len = intel_dp_as_sdp_pack(_state->infoframes.as_sdp, ,
+ sizeof(sdp));
+ break;
default:
MISSING_CASE(type);
return;
@@ -4276,7 +4307,8 @@ void intel_dp_set_infoframes(struct intel_encoder
*encoder,
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
-VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
+VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
+VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
@@ -4298,6 +4330,40 @@ void intel_dp_set_infoframes(struct intel_encoder
*encoder,
intel_write_dp_sdp(encoder, crtc_state,
HDMI_PACKET_TYPE_GAMUT_METADATA);
}
+static
+int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
+ const void *buffer, size_t size)
+{
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ memset(as_sdp, 0, sizeof(*as_sdp));
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB2 != 0x02)
+ return -EINVAL;
+
+ if ((sdp->sdp_header.HB3 & 0x3F) != 9)
+ return -EINVAL;
+
+ if ((sdp->db[0] & AS_SDP_OP_MODE) != 0x0)
+ return -EINVAL;
+
+ as_sdp->vtotal = ((u64)sdp->db[2] << 32) | (u64)sdp->db[1];
+ as_sdp->target_rr = 0;
+ as_sdp->duration_incr_ms = 0;
+ as_sdp->duration_decr_ms = 0;
+
+ return 0;
+}
+
static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
const void *buffer, size_t size)
{
@@ -4368,6 +4434,27 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp
*vsc,
return 0;
}
+static int
Re: [PATCH 6/6] drm/i915/display: Read/Write AS sdp only when sink/source has enabled
On 2/16/2024 7:50 PM, Mitul Golani wrote:
Write/Read Adaptive sync SDP only when Sink and Source is enabled
for the same. Also along with write TRANS_VRR_VSYNC values.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4
.../gpu/drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 15 +++
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 7 +++
5 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bea441590204..68cd49193d03 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3926,6 +3926,7 @@ static void intel_ddi_get_config(struct intel_encoder
*encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
/* XXX: DSI transcoder paranoia */
if (drm_WARN_ON(_priv->drm, transcoder_is_dsi(cpu_transcoder)))
@@ -3972,6 +3973,9 @@ static void intel_ddi_get_config(struct intel_encoder
*encoder,
intel_read_dp_sdp(encoder, pipe_config,
HDMI_PACKET_TYPE_GAMUT_METADATA);
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
+ if (HAS_AS_SDP(dev_priv) && intel_dp_sink_as_sdp_supported(intel_dp))
+ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
+
intel_audio_codec_get_config(encoder, pipe_config);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index fe4268813786..6399fbc6c738 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -68,6 +68,7 @@ struct drm_printer;
#define HAS_TRANSCODER(i915, trans)
((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
BIT(trans)) != 0)
#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
+#define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13)
#define INTEL_NUM_PIPES(i915)
(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
#define I915_HAS_HOTPLUG(i915)
(DISPLAY_INFO(i915)->has_hotplug)
#define OVERLAY_NEEDS_PHYSICAL(i915)
(DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0759266e7bfb..5bd99fa8f200 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -119,6 +119,17 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
return dig_port->base.type == INTEL_OUTPUT_EDP;
}
+bool
+intel_dp_sink_as_sdp_supported(struct intel_dp *intel_dp)
+{
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+
+ if (drm_dp_read_dpcd_caps(_dp->aux, dpcd))
+ return -EIO;
+
This is already read in intel_dp->dpcd, we can use that.
+ return drm_dp_as_sdp_supported(_dp->aux, dpcd);
+}
+
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
/* Is link rate UHBR and thus 128b/132b? */
@@ -4330,6 +4341,7 @@ void intel_dp_set_infoframes(struct intel_encoder
*encoder,
VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
if (!enable && HAS_DSC(dev_priv))
@@ -4347,6 +4359,9 @@ void intel_dp_set_infoframes(struct intel_encoder
*encoder,
intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
+ if (HAS_AS_SDP(dev_priv) && intel_dp_sink_as_sdp_supported(intel_dp))
+ intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
+
intel_write_dp_sdp(encoder, crtc_state,
HDMI_PACKET_TYPE_GAMUT_METADATA);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 530cc97bc42f..09ab313af896 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -180,5 +180,6 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp
*intel_dp,
struct link_config_limits *limits);
void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
+bool intel_dp_sink_as_sdp_supported(struct intel_dp *intel_dp);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 2fa0004d00c7..86729e145991 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -192,6 +192,9 @@ void
Re: [PATCH 5/6] drm/i915/display: Compute vrr_vsync params
On 2/16/2024 7:50 PM, Mitul Golani wrote:
Compute vrr_vsync_start/end which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit)
- Update bit fields of VRR_VSYNC_START/END.(Ankit)
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h| 11 +++
3 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index a6991bc3f07b..015ed846b896 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1414,6 +1414,7 @@ struct intel_crtc_state {
bool enable, in_range;
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
+ u32 vsync_end, vsync_start;
} vrr;
/* Stream Splitter for eDP MSO */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5d905f932cb4..2fa0004d00c7 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -149,6 +149,13 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
+ crtc_state->vrr.vsync_start =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+
VRR_VSYNC_START(crtc_state->hw.adjusted_mode.vsync_start));
+ crtc_state->vrr.vsync_end =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+ (VRR_VSYNC_END(crtc_state->hw.adjusted_mode.vsync_end)
>> 16));
+
/*
* For XE_LPD+, we use guardband and pipeline override
* is deprecated.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c02ea07af4c2..f73e95b18819 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1955,6 +1955,10 @@
#define VSYNC_END(vsync_end)REG_FIELD_PREP(VSYNC_END_MASK,
(vsync_end))
#define VSYNC_START_MASKREG_GENMASK(15, 0)
#define VSYNC_START(vsync_start)REG_FIELD_PREP(VSYNC_START_MASK,
(vsync_start))
+#define VSYNC_END_MASK REG_GENMASK(31, 16)
+#define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK,
(vsync_end))
+#define VSYNC_START_MASK REG_GENMASK(15, 0)
+#define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK,
(vsync_start))
I think this is typo, we really dont need to touch these.
#define _TRANS_EXITLINE_A 0x60018
#define _PIPEASRC 0x6001c
#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
@@ -2007,7 +2011,9 @@
#define _TRANS_VRR_CTL_B 0x61420
#define _TRANS_VRR_CTL_C 0x62420
#define _TRANS_VRR_CTL_D 0x63420
+#define _TRANS_VRR_VSYNC_A 0x60078
#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans,
_TRANS_VRR_CTL_A)
+#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(trans,
_TRANS_VRR_VSYNC_A)
#define VRR_CTL_VRR_ENABLE REG_BIT(31)
#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
#define VRR_CTL_FLIP_LINE_ENREG_BIT(29)
@@ -2087,6 +2093,11 @@
#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans,
_TRANS_VRR_STATUS2_A)
#define VRR_STATUS2_VERT_LN_CNT_MASKREG_GENMASK(19, 0)
+#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
+#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK,
(vsync_end))
+#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
+#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK,
(vsync_start))
Here too, we need to use the correct VRR_VSYNC_STAR/END_MASK
Regards,
Ankit
+
#define _TRANS_PUSH_A 0x60A70
#define _TRANS_PUSH_B 0x61A70
#define _TRANS_PUSH_C 0x62A70
Re: [PATCH 4/6] drm/i915/display: Compute and Enable AS SDP
On 2/16/2024 7:50 PM, Mitul Golani wrote:
Add necessary functions definitions to enable
and compute AS SDP data. The new `intel_dp_compute_as_sdp`
function computes AS SDP values based on the display
configuration, ensuring proper handling of Variable Refresh
Rate (VRR).
--v2:
- Add DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit]
- separate patch for intel_read/write_dp_sdp [Ankit].
- _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward [Ankit]
- To fix indentation [Ankit]
--v3:
- Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes.
--v4:
- Add HAS_VRR check before write as sdp.
--v5:
- Add missed HAS_VRR check before read as sdp.
--v6:
Use Adaptive Sync sink status, which can be
used as a check for read/write sdp. (Ankit)
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index d68fb9d45054..0759266e7bfb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2617,6 +2617,25 @@ static void intel_dp_compute_vsc_colorimetry(const
struct intel_crtc_state *crtc
vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
}
+static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state)
+{
+ struct drm_dp_as_sdp *as_sdp = _state->infoframes.as_sdp;
+ struct intel_connector *connector = intel_dp->attached_connector;
+ const struct drm_display_mode *adjusted_mode =
+ _state->hw.adjusted_mode;
+ int vrefresh = drm_mode_vrefresh(adjusted_mode);
+
+ if (!intel_vrr_is_in_range(connector, vrefresh))
+ return;
I think there should be 2 variables in crtc_state->vrras_sdp_enable and
as_sdp_mode.
as_sdp_enable to track, if we really need to send the as_sdp and the
as_sdp_mode to track which mode we want (AVT/FAVT)
We fill these in vrr_compute_config, along with other members like trans
vrr_sync_start/end.
Here we can check if as_sdp_enable is set, if not we return early.
+
+ crtc_state->infoframes.enable |=
intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
+ as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
+ as_sdp->length = 0x9;
+ as_sdp->vtotal = adjusted_mode->vtotal;
Here the as_sdp->operation_mode should be set which is computed in
vrr_compute_config, as mentioned above.
Other fields will depend on mode that is selected.
Regards,
Ankit
+}
+
static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -2942,6 +2961,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
g4x_dp_set_clock(encoder, pipe_config);
intel_vrr_compute_config(pipe_config, conn_state);
+ intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
✓ Fi.CI.BAT: success for HDCP MST Type1 fixes (rev3)
== Series Details ==
Series: HDCP MST Type1 fixes (rev3)
URL : https://patchwork.freedesktop.org/series/129925/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14298 -> Patchwork_129925v3
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/index.html
Participating hosts (37 -> 36)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_129925v3 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-6: NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: [PASS][2] -> [CRASH][3] ([i915#9947])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14298/fi-kbl-7567u/igt@i915_pm_...@module-reload.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/fi-kbl-7567u/igt@i915_pm_...@module-reload.html
* igt@i915_pm_rps@basic-api:
- bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#6621])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/bat-mtlp-6/igt@i915_pm_...@basic-api.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-mtlp-6: NOTRUN -> [SKIP][5] ([fdo#109285] / [i915#9792])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/bat-mtlp-6/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-6: NOTRUN -> [SKIP][6] ([i915#5274] / [i915#9792])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/bat-mtlp-6/igt@kms_force_connector_ba...@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][7] ([i915#4342] / [i915#5354] /
[i915#9792])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/bat-mtlp-6/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- bat-mtlp-6: NOTRUN -> [SKIP][8] ([i915#9792]) +6 other tests skip
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/bat-mtlp-6/igt@kms_pipe_crc_ba...@hang-read-crc.html
* igt@kms_pm_backlight@basic-brightness:
- bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#5354] / [i915#9792])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/bat-mtlp-6/igt@kms_pm_backli...@basic-brightness.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#8809] /
[i915#9792])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/bat-mtlp-6/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-mtlp-6: NOTRUN -> [SKIP][11] ([i915#3708] / [i915#9792])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/bat-mtlp-6/igt@prime_v...@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-mtlp-6: NOTRUN -> [SKIP][12] ([i915#3708] / [i915#4077]) +1
other test skip
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/bat-mtlp-6/igt@prime_v...@basic-fence-mmap.html
* igt@prime_vgem@basic-write:
- bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#3708]) +2 other tests skip
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/bat-mtlp-6/igt@prime_v...@basic-write.html
Possible fixes
* igt@i915_selftest@live@mman:
- bat-dg2-8: [DMESG-WARN][14] ([i915#10014]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14298/bat-dg2-8/igt@i915_selftest@l...@mman.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129925v3/bat-dg2-8/igt@i915_selftest@l...@mman.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#10014]: https://gitlab.freedesktop.org/drm/intel/issues/10014
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
✗ Fi.CI.SPARSE: warning for HDCP MST Type1 fixes (rev3)
== Series Details == Series: HDCP MST Type1 fixes (rev3) URL : https://patchwork.freedesktop.org/series/129925/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
Re: [PATCH 3/6] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP
On 2/16/2024 7:50 PM, Mitul Golani wrote:
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]
--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 95 ++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 12 ++-
drivers/gpu/drm/i915/i915_reg.h | 8 ++
include/drm/display/drm_dp.h | 2 +-
include/drm/display/drm_dp_helper.h | 2 +
5 files changed, 114 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 217196196e50..d68fb9d45054 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -95,7 +95,6 @@
#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
-
/* Constants for DP DSC configurations */
static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
@@ -4089,6 +4088,34 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
return false;
}
+static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
+ struct dp_sdp *sdp, size_t size)
+{
+ size_t length = sizeof(struct dp_sdp);
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(sdp, 0, size);
+
+ /* Prepare AS (Adaptive Sync) SDP Header */
+ sdp->sdp_header.HB0 = 0;
+ sdp->sdp_header.HB1 = as_sdp->sdp_type;
+ sdp->sdp_header.HB2 = 0x02;
+ sdp->sdp_header.HB3 = as_sdp->length;
+
+ /* Fill AS (Adaptive Sync) SDP Payload */
+ sdp->db[1] = 0x0;
Operation_mode, target_rr etc should be filled from as_sdp struct.
+ sdp->db[1] = as_sdp->vtotal & 0xFF;
+ sdp->db[2] = (as_sdp->vtotal >> 8) & 0xF;
+ sdp->db[3] = 0x0;
+ sdp->db[4] = 0x0;
+ sdp->db[7] = 0x0;
+ sdp->db[8] = 0x0;
+
+ return length;
+}
+
static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
struct dp_sdp *sdp, size_t size)
{
@@ -4256,6 +4283,10 @@ static void intel_write_dp_sdp(struct intel_encoder
*encoder,
_state->infoframes.drm.drm,
,
sizeof(sdp));
break;
+ case DP_SDP_ADAPTIVE_SYNC:
+ len = intel_dp_as_sdp_pack(_state->infoframes.as_sdp, ,
+ sizeof(sdp));
+ break;
default:
MISSING_CASE(type);
return;
@@ -4276,7 +4307,8 @@ void intel_dp_set_infoframes(struct intel_encoder
*encoder,
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
-VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
+VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
+VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
@@ -4298,6 +4330,40 @@ void intel_dp_set_infoframes(struct intel_encoder
*encoder,
intel_write_dp_sdp(encoder, crtc_state,
HDMI_PACKET_TYPE_GAMUT_METADATA);
}
+static
+int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
+ const void *buffer, size_t size)
+{
+ const struct dp_sdp *sdp = buffer;
+
+ if (size < sizeof(struct dp_sdp))
+ return -EINVAL;
+
+ memset(as_sdp, 0, sizeof(*as_sdp));
+
+ if (sdp->sdp_header.HB0 != 0)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
+ return -EINVAL;
+
+ if (sdp->sdp_header.HB2 != 0x02)
+ return -EINVAL;
+
+ if ((sdp->sdp_header.HB3 & 0x3F) != 9)
+ return -EINVAL;
+
+ if ((sdp->db[0] & AS_SDP_OP_MODE) != 0x0)
+ return -EINVAL;
lets not check this thing here, but fill as_sdp->operation_mode, read
from the sdp.
Checking should be done in intel_pipe_config_compare, perhaps need to
add a new PIPE_CONF_CHECK_ for adaptive sync SDP.
+
+ as_sdp->vtotal = ((u64)sdp->db[2] << 32) | (u64)sdp->db[1];
+ as_sdp->target_rr = 0;
+ as_sdp->duration_incr_ms = 0;
+ as_sdp->duration_decr_ms = 0;
+
Re: [PATCH 2/6] drm: Add Adaptive Sync SDP logging
On 2/16/2024 7:50 PM, Mitul Golani wrote:
Add structure representing Adaptive Sync Secondary Data
Packet (AS SDP). Also, add Adaptive Sync SDP logging in
drm_dp_helper.c to facilitate debugging.
--v2:
- Update logging. [Jani, Ankit]
- use as_sdp instead of async [Ankit]
- Correct define placeholders to where it is being actually used. [Jani]
- Update members in as_sdp structure and make it uniform. [Jani]
--v3:
- Add changes dri-devel mail list. No code changes.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/display/drm_dp_helper.c | 12
.../drm/i915/display/intel_crtc_state_dump.c | 12
.../drm/i915/display/intel_display_types.h| 1 +
include/drm/display/drm_dp.h | 2 ++
include/drm/display/drm_dp_helper.h | 30 +++
5 files changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
b/drivers/gpu/drm/display/drm_dp_helper.c
index 81c5507928f5..5911b20de2ea 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2913,6 +2913,18 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const
struct drm_dp_vsc_sdp *vsc)
}
EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
+void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp)
+{
+ drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n",
+ as_sdp->revision, as_sdp->length);
+ drm_printf(p, "vtotal: %d\n", as_sdp->vtotal);
+ drm_printf(p, "target_rr: %d\n", as_sdp->target_rr);
+ drm_printf(p, "duration_incr_ms: %d\n", as_sdp->duration_incr_ms);
+ drm_printf(p, "duration_decr_ms: %d\n", as_sdp->duration_decr_ms);
+ drm_printf(p, "operation_mode: %d\n", as_sdp->operation_mode);
+}
+EXPORT_SYMBOL(drm_dp_as_sdp_log);
+
/**
* drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
* @aux: DisplayPort AUX channel
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 4bcf446c75f4..26d77c2934e8 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -60,6 +60,15 @@ intel_dump_dp_vsc_sdp(struct drm_i915_private *i915,
drm_dp_vsc_sdp_log(, vsc);
}
+static void
+intel_dump_dp_as_sdp(struct drm_i915_private *i915,
+const struct drm_dp_as_sdp *as_sdp)
+{
+ struct drm_printer p = drm_dbg_printer(>drm, DRM_UT_KMS,
"AS_SDP");
+
+ drm_dp_as_sdp_log(, as_sdp);
+}
+
static void
intel_dump_buffer(struct drm_i915_private *i915,
const char *prefix, const u8 *buf, size_t len)
@@ -299,6 +308,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state
*pipe_config,
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
intel_dump_infoframe(i915, _config->infoframes.drm);
+ if (pipe_config->infoframes.enable &
+ intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
+ intel_dump_dp_as_sdp(i915, _config->infoframes.as_sdp);
if (pipe_config->infoframes.enable &
intel_hdmi_infoframe_enable(DP_SDP_VSC))
intel_dump_dp_vsc_sdp(i915, _config->infoframes.vsc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0d4012097db1..a6991bc3f07b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1332,6 +1332,7 @@ struct intel_crtc_state {
union hdmi_infoframe hdmi;
union hdmi_infoframe drm;
struct drm_dp_vsc_sdp vsc;
+ struct drm_dp_as_sdp as_sdp;
} infoframes;
u8 eld[MAX_ELD_BYTES];
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 281afff6ee4e..af6790fb4791 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1578,10 +1578,12 @@ enum drm_dp_phy {
#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
#define DP_SDP_ISRC 0x06 /* DP 1.2 */
#define DP_SDP_VSC0x07 /* DP 1.2 */
+#define DP_SDP_ADAPTIVE_SYNC0x22 /* DP 1.4 */
#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
#define DP_SDP_PPS0x10 /* DP 1.4 */
#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
#define DP_SDP_VSC_EXT_CEA0x21 /* DP 1.4 */
+
/* 0x80+ CEA-861 infoframe types */
#define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display/drm_dp_helper.h
index a0356721de0f..8a692a86d8d6 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -98,6 +98,36 @@ struct drm_dp_vsc_sdp {
enum dp_content_type content_type;
};
+/**
+ * struct
Re: Re: [PATCH v3 2/3] bits: Introduce fixed-type BIT
On Fri, Feb 09, 2024 at 08:53:25AM -0800, Yury Norov wrote: On Wed, Feb 07, 2024 at 11:45:20PM -0800, Lucas De Marchi wrote: Implement fixed-type BIT() to help drivers add stricter checks, like was done for GENMASK. Signed-off-by: Lucas De Marchi Acked-by: Jani Nikula So I get v1 from Jan.23 in my mailbox, and this one is v3. Did I miss a v2? Anyways, please bear my reviewed-by from v1 for this patch. Jan 23 was actually the v2 and I missed the subject prefix. My understanding was that you were going to apply this through some bitmap tree, but checking MAINTAINERS now it seems there's no git tree associated. So I will just add your r-b and merge this through drm-xe. thanks Lucas De Marchi Thanks, Yury --- include/linux/bits.h | 17 + 1 file changed, 17 insertions(+) diff --git a/include/linux/bits.h b/include/linux/bits.h index bd56f32de44e..811846ce110e 100644 --- a/include/linux/bits.h +++ b/include/linux/bits.h @@ -24,12 +24,16 @@ #define GENMASK_INPUT_CHECK(h, l) \ (BUILD_BUG_ON_ZERO(__builtin_choose_expr( \ __is_constexpr((l) > (h)), (l) > (h), 0))) +#define BIT_INPUT_CHECK(type, b) \ + ((BUILD_BUG_ON_ZERO(__builtin_choose_expr( \ + __is_constexpr(b), (b) >= BITS_PER_TYPE(type), 0 #else /* * BUILD_BUG_ON_ZERO is not available in h files included from asm files, * disable the input check if that is the case. */ #define GENMASK_INPUT_CHECK(h, l) 0 +#define BIT_INPUT_CHECK(type, b) 0 #endif /* @@ -54,4 +58,17 @@ #define GENMASK_U32(h, l) __GENMASK(u32, h, l) #define GENMASK_U64(h, l) __GENMASK(u64, h, l) +/* + * Fixed-type variants of BIT(), with additional checks like __GENMASK(). The + * following examples generate compiler warnings due to shift-count-overflow: + * + * - BIT_U8(8) + * - BIT_U32(-1) + * - BIT_U32(40) + */ +#define BIT_U8(b) ((u8)(BIT_INPUT_CHECK(u8, b) + BIT(b))) +#define BIT_U16(b) ((u16)(BIT_INPUT_CHECK(u16, b) + BIT(b))) +#define BIT_U32(b) ((u32)(BIT_INPUT_CHECK(u32, b) + BIT(b))) +#define BIT_U64(b) ((u64)(BIT_INPUT_CHECK(u64, b) + BIT(b))) + #endif /* __LINUX_BITS_H */ -- 2.43.0
[PATCH 12/13] drm/i915/hdcp: Allocate stream id after HDCP AKE stage
Allocate stream id after HDCP AKE stage and not before so that it
can also be done during link integrity check.
Right now for MST scenarios LIC fails after hdcp enablement for this
reason.
--v2
-no need for else block in prepare_streams function [Ankit]
--v3
-remove intel_hdcp argument from required_content_stream function
[Ankit]
Signed-off-by: Suraj Kandpal
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 137 ++
1 file changed, 65 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index ad05ab899706..ea9b26b0f06b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -30,7 +30,7 @@
#define KEY_LOAD_TRIES 5
#define HDCP2_LC_RETRY_CNT 3
-static int intel_conn_to_vcpi(struct drm_atomic_state *state,
+static int intel_conn_to_vcpi(struct intel_atomic_state *state,
struct intel_connector *connector)
{
struct drm_dp_mst_topology_mgr *mgr;
@@ -43,7 +43,7 @@ static int intel_conn_to_vcpi(struct drm_atomic_state *state,
return 0;
mgr = connector->port->mgr;
- drm_modeset_lock(>base.lock, state->acquire_ctx);
+ drm_modeset_lock(>base.lock, state->base.acquire_ctx);
mst_state = to_drm_dp_mst_topology_state(mgr->base.state);
payload = drm_atomic_get_mst_payload_state(mst_state, connector->port);
if (drm_WARN_ON(mgr->dev, !payload))
@@ -68,19 +68,51 @@ static int intel_conn_to_vcpi(struct drm_atomic_state
*state,
* DP MST topology. Though it is not compulsory, security fw should change its
* policy to mark different content_types for different streams.
*/
-static void
-intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
+static int
+intel_hdcp_required_content_stream(struct intel_atomic_state *state,
+ struct intel_digital_port *dig_port)
{
+ struct drm_connector_list_iter conn_iter;
+ struct intel_digital_port *conn_dig_port;
+ struct intel_connector *connector;
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct hdcp_port_data *data = _port->hdcp_port_data;
bool enforce_type0 = false;
int k;
if (dig_port->hdcp_auth_status)
- return;
+ return 0;
+
+ data->k = 0;
if (!dig_port->hdcp_mst_type1_capable)
enforce_type0 = true;
+ drm_connector_list_iter_begin(>drm, _iter);
+ for_each_intel_connector_iter(connector, _iter) {
+ if (connector->base.status == connector_status_disconnected)
+ continue;
+
+ if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
+ continue;
+
+ conn_dig_port = intel_attached_dig_port(connector);
+ if (conn_dig_port != dig_port)
+ continue;
+
+ data->streams[data->k].stream_id =
+ intel_conn_to_vcpi(state, connector);
+ data->k++;
+
+ /* if there is only one active stream */
+ if (dig_port->dp.active_mst_links <= 1)
+ break;
+ }
+ drm_connector_list_iter_end(_iter);
+
+ if (drm_WARN_ON(>drm, data->k > INTEL_NUM_PIPES(i915) || data->k
== 0))
+ return -EINVAL;
+
/*
* Apply common protection level across all streams in DP MST Topology.
* Use highest supported content type for all streams in DP MST
Topology.
@@ -88,19 +120,25 @@ intel_hdcp_required_content_stream(struct
intel_digital_port *dig_port)
for (k = 0; k < data->k; k++)
data->streams[k].stream_type =
enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 :
DRM_MODE_HDCP_CONTENT_TYPE1;
+
+ return 0;
}
-static void intel_hdcp_prepare_streams(struct intel_connector *connector)
+static int intel_hdcp_prepare_streams(struct intel_atomic_state *state,
+ struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct hdcp_port_data *data = _port->hdcp_port_data;
struct intel_hdcp *hdcp = >hdcp;
- if (!intel_encoder_is_mst(intel_attached_encoder(connector))) {
- data->streams[0].stream_type = hdcp->content_type;
- } else {
- intel_hdcp_required_content_stream(dig_port);
- }
+ if (intel_encoder_is_mst(intel_attached_encoder(connector)))
+ return intel_hdcp_required_content_stream(state, dig_port);
+
+ data->k = 1;
+ data->streams[0].stream_id = 0;
+ data->streams[0].stream_type = hdcp->content_type;
+
+ return 0;
}
static
@@ -1895,7 +1933,8 @@ hdcp2_propagate_stream_management_info(struct
Re: linux-next: build failure after merge of the drm-misc tree
Hi all,
On Mon, 12 Feb 2024 15:15:54 +0200 Jani Nikula
wrote:
>
> On Tue, 06 Feb 2024, Stephen Rothwell wrote:
> >
> > After merging the drm-misc tree, today's linux-next build (i386 defconfig)
> > failed like this:
> >
> > In function 'i915_ttm_placement_from_obj',
> > inlined from 'i915_ttm_get_pages' at
> > drivers/gpu/drm/i915/gem/i915_gem_ttm.c:847:2:
> > drivers/gpu/drm/i915/gem/i915_gem_ttm.c:165:18: error: 'places[0].flags' is
> > used uninitialized [-Werror=uninitialized]
> > 165 | places[0].flags |= TTM_PL_FLAG_DESIRED;
> > | ~^~
> > drivers/gpu/drm/i915/gem/i915_gem_ttm.c: In function 'i915_ttm_get_pages':
> > drivers/gpu/drm/i915/gem/i915_gem_ttm.c:837:26: note: 'places' declared here
> > 837 | struct ttm_place places[I915_TTM_MAX_PLACEMENTS + 1];
> > | ^~
> >
> > Caused by commit
> >
> > a78a8da51b36 ("drm/ttm: replace busy placement with flags v6")
>
> Cc: more people.
>
> >
> > I applied the following hack for today:
> >
> > From: Stephen Rothwell
> > Date: Tue, 6 Feb 2024 15:17:54 +1100
> > Subject: [PATCH] drm/ttm: initialise places
> >
> > Signed-off-by: Stephen Rothwell
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> > index 80c6cafc8887..34e699e67c25 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> > @@ -834,7 +834,7 @@ static int __i915_ttm_get_pages(struct
> > drm_i915_gem_object *obj,
> >
> > static int i915_ttm_get_pages(struct drm_i915_gem_object *obj)
> > {
> > - struct ttm_place places[I915_TTM_MAX_PLACEMENTS + 1];
> > + struct ttm_place places[I915_TTM_MAX_PLACEMENTS + 1] = {};
> > struct ttm_placement placement;
> >
> > /* restricted by sg_alloc_table */
> > --
> > 2.43.0
I am still applying the above patch ...
--
Cheers,
Stephen Rothwell
pgpIRyeKbrwaj.pgp
Description: OpenPGP digital signature
✗ Fi.CI.IGT: failure for drm/i915: check before removing mm notifier (rev2)
== Series Details == Series: drm/i915: check before removing mm notifier (rev2) URL : https://patchwork.freedesktop.org/series/101170/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14296_full -> Patchwork_101170v2_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_101170v2_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_101170v2_full, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (8 -> 8) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_101170v2_full: ### IGT changes ### Possible regressions * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt: - shard-dg2: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-dg2-5/igt@kms_frontbuffer_track...@fbc-1p-primscrn-indfb-pgflip-blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101170v2/shard-dg2-6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-indfb-pgflip-blt.html Warnings * igt@gem_media_fill@media-fill: - shard-dg2: [SKIP][3] ([i915#8289]) -> [TIMEOUT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-dg2-5/igt@gem_media_f...@media-fill.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101170v2/shard-dg2-6/igt@gem_media_f...@media-fill.html * igt@kms_ccs@pipe-a-random-ccs-data-4-tiled-mtl-mc-ccs: - shard-dg2: [SKIP][5] ([i915#5354]) -> [TIMEOUT][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-dg2-5/igt@kms_...@pipe-a-random-ccs-data-4-tiled-mtl-mc-ccs.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101170v2/shard-dg2-6/igt@kms_...@pipe-a-random-ccs-data-4-tiled-mtl-mc-ccs.html Known issues Here are the changes found in Patchwork_101170v2_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-rkl: ([PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30]) -> ([PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [FAIL][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53]) ([i915#8293]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-1/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-1/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-1/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-1/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-1/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-2/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-2/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-3/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-3/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-4/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-4/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-4/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-4/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-5/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-5/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-5/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-5/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-6/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-6/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-7/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-7/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/shard-rkl-7/boot.html [30]:
Re: [PATCH v3] drm/i915/guc: Simplify/extend platform check for Wa_14018913170
On Fri, Feb 16, 2024 at 10:38:41AM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The above w/a is required for every platform that the i915 driver
> supports. It is fixed on the latest platforms but they are only
> supported by Xe instead of i915. So just remove the platform check
> completely and keep the code simple.
Well, I was going to say that I would prefer a GMD version greater-than
check to be future proof. However if this code gets used in some other
new platform a new specific guc support would likely need to be added
as well right?
Perhaps at least adding a comment in the code?
with that
Reviewed-by: Rodrigo Vivi
>
> Signed-off-by: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 2b450c43bbd7f..a3662edb42032 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -321,8 +321,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>
> /* Wa_14018913170 */
> if (GUC_FIRMWARE_VER(guc) >= MAKE_GUC_VER(70, 7, 0)) {
> - if (IS_DG2(gt->i915) || IS_METEORLAKE(gt->i915) ||
> IS_PONTEVECCHIO(gt->i915))
> - flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6;
> + flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6;
> }
>
> return flags;
> --
> 2.43.0
>
✓ Fi.CI.BAT: success for drm/i915: Add some boring kerneldoc
== Series Details ==
Series: drm/i915: Add some boring kerneldoc
URL : https://patchwork.freedesktop.org/series/130082/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14297 -> Patchwork_130082v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130082v1/index.html
Participating hosts (36 -> 36)
--
Additional (1): bat-kbl-2
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_130082v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@fbdev@info:
- bat-kbl-2: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1849])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130082v1/bat-kbl-2/igt@fb...@info.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2: NOTRUN -> [SKIP][2] ([fdo#109271]) +35 other tests
skip
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130082v1/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
Build changes
-
* Linux: CI_DRM_14297 -> Patchwork_130082v1
CI-20190529: 20190529
CI_DRM_14297: 52bdc58b3b2bd7b77710f0d6710c1b9dbaee1af9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7718: 40e8b9122853f455c84afcfa56469a6bc9a0d564 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_130082v1: 52bdc58b3b2bd7b77710f0d6710c1b9dbaee1af9 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
631959f4536d drm/i915: Add some boring kerneldoc
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130082v1/index.html
✗ Fi.CI.SPARSE: warning for drm/i915: Add some boring kerneldoc
== Series Details == Series: drm/i915: Add some boring kerneldoc URL : https://patchwork.freedesktop.org/series/130082/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add some boring kerneldoc
== Series Details == Series: drm/i915: Add some boring kerneldoc URL : https://patchwork.freedesktop.org/series/130082/ State : warning == Summary == Error: dim checkpatch failed 27589b86618e drm/i915: Add some boring kerneldoc -:14: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report #14: Reported-by: Stephen Rothwell Cc: Jose Souza total: 0 errors, 1 warnings, 0 checks, 13 lines checked
Re: [PATCH] drm/i915/display: Allow tighter hblank span
On Sun, Feb 18, 2024 at 07:12:24PM +0100, Bas S wrote:
>I ran into an issue with the i915 driver not being able to drive a display
>
>with this specific modeline:
>
Could you please file a bug on this?
https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html
The limits below are per platform/display-architecture and probably forgotten
to get updates for newer platforms. But having more information about your
platform would be very helpful.
Thanks,
Rodrigo.
>
>
>[drm]] Modeline "1920x720": 60 120980 1920 1932 1936 1948 720 723 733 1035
>
>0x48 0x9
>
>[drm:drm_mode_prune_invalid [drm]] Not using 1920x720 mode: H_ILLEGAL
>
>
>
>After some investigation I found that intel_mode_valid (and in newer
>
>kernels, intel_cpu_transcoder_mode_valid) returns MODE_H_ILLEGAL due to
>
>(htotal - hdisplay) being lower than 32.
>
>The modeline in question indeed does not satisfy this constraint, as
>
>HTOTAL(1948) - HDISPLAY(1920) equals 28.
>
>Changing the driver code to allow for a hblank span of 28 pixels or lower
>
>resulted in the driver successfully rendering to the display.
>
>As such I propose this patch to allow for a tighter hblank span.
>
>
>
>Nb: I am uncertain if the hblank span of 32 pixels has been chosen
>
>deliberately and what the side-effects could be of lowering this value.
>
>Any insights into this or alternative solutions would be very much
>
>appreciated! I also considered introducing a kernel module parameter to
>
>optionally loosen these mode constraints.
>
>
>
>The referenced modeline is present in a line of ultrawide signage displays
>
>and has been known to work on other graphics drivers/OSes.
>
>
>
>Signed-off-by: Sebastiaan Schalbroeck <[1]schalbro...@gmail.com>
>
>---
>
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>
>b/drivers/gpu/drm/i915/display/intel_display.c
>
>index b10aad1..f6aba1d 100644
>
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>
>@@ -7745,13 +7745,13 @@ enum drm_mode_status
>
>intel_cpu_transcoder_mode_valid(struct drm_i915_private *de
>
> */
>
> if (DISPLAY_VER(dev_priv) >= 5) {
>
> if (mode->hdisplay < 64 ||
>
>- mode->htotal - mode->hdisplay < 32)
>
>+ mode->htotal - mode->hdisplay < 28)
>
> return MODE_H_ILLEGAL;
>
>
>
> if (mode->vtotal - mode->vdisplay < 5)
>
> return MODE_V_ILLEGAL;
>
> } else {
>
>- if (mode->htotal - mode->hdisplay < 32)
>
>+ if (mode->htotal - mode->hdisplay < 28)
>
> return MODE_H_ILLEGAL;
>
>
>
> if (mode->vtotal - mode->vdisplay < 3)
>
>
>
>--
Re: [PATCH] drm/i915: check before removing mm notifier
On Mon, Feb 19, 2024 at 01:50:47PM +0100, Nirmoy Das wrote:
> Error in mmu_interval_notifier_insert() can leave a NULL
> notifier.mm pointer. Catch that and return early.
>
> Cc: Andi Shyti
> Cc: Shawn Lee
> Signed-off-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> index 0e21ce9d3e5a..61abfb505766 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> @@ -349,6 +349,9 @@ i915_gem_userptr_release(struct drm_i915_gem_object *obj)
> {
> GEM_WARN_ON(obj->userptr.page_ref);
>
> + if (!obj->userptr.notifier.mm)
> + return;
> +
hmmm... right, it looks that we need this protection. But...
I mean, feel free to use
Reviewed-by: Rodrigo Vivi
for this patch,
but I believe that if this mmu insert failed we might have other
deeper problems like when checking i915_gem_object_is_userptr() ?
No?!
> mmu_interval_notifier_remove(>userptr.notifier);
> obj->userptr.notifier.mm = NULL;
> }
> --
> 2.42.0
>
Re: [PATCH] drm/i915/cdclk: Document CDCLK components
On Fri, Feb 16, 2024 at 01:45:25PM -0300, Gustavo Sousa wrote: > Improve documentation by giving an overview of the components involved > in the generation of the CDCLK. > > Signed-off-by: Gustavo Sousa Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 25 ++ > 1 file changed, 25 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 30dae4fef6cb..ef1660f94e46 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -63,6 +63,31 @@ > * DMC will not change the active CDCLK frequency however, so that part > * will still be performed by the driver directly. > * > + * There are multiple components involved in the generation of the CDCLK > + * frequency: > + * - We have the CDCLK PLL, which generates an output clock based on a > + * reference clock and a ratio parameter. > + * - The CD2X Divider, which divides the output of the PLL based on a > + * divisor selected from a set of pre-defined choices. > + * - The CD2X Squasher, which further divides the output based on a > + * waveform represented as a sequence of bits where each zero > + * "squashes out" a clock cycle. > + * - And, finally, a fixed divider that divides the output frequency by 2. > + * > + * As such, the resulting CDCLK frequency can be calculated with the > + * following formula: > + * > + * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 > + * > + * , where vco is the frequency generated by the PLL; cd2x_div > + * represents the CD2X Divider; sq_len and sq_div are the bit length > + * and the number of high bits for the CD2X Squasher waveform, respectively; > + * and 2 represents the fixed divider. > + * > + * Note that some older platforms do not contain the CD2X Divider > + * and/or CD2X Squasher, in which case we can ignore their respective > + * factors in the formula above. > + * > * Several methods exist to change the CDCLK frequency, which ones are > * supported depends on the platform: > * - Full PLL disable + re-enable with new VCO frequency. Pipes must be > inactive. > -- > 2.43.0 -- Ville Syrjälä Intel
Re: [PATCH] drm/i915: Fix possible null pointer dereference after drm_dbg_printer conversion
On Mon, Feb 19, 2024 at 01:14:23PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Request can be NULL if no guilty request was identified so simply use
> engine->i915 instead.
>
> Signed-off-by: Tvrtko Ursulin
> Fixes: d50892a9554c ("drm/i915: switch from drm_debug_printer() to device
> specific drm_dbg_printer()")
> Reported-by: Dan Carpenter
> Cc: Jani Nikula
> Cc: Luca Coelho
> Cc: Maxime Ripard
> Cc: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
> b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
> index 5f8d86e25993..8d4bb95f8424 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
> @@ -96,8 +96,8 @@ static void heartbeat_commit(struct i915_request *rq,
> static void show_heartbeat(const struct i915_request *rq,
> struct intel_engine_cs *engine)
> {
> - struct drm_printer p = drm_dbg_printer(>i915->drm, DRM_UT_DRIVER,
> -"heartbeat");
> + struct drm_printer p =
> + drm_dbg_printer(>i915->drm, DRM_UT_DRIVER, "heartbeat");
>
> if (!rq) {
> intel_engine_dump(engine, ,
> --
> 2.40.1
>
✓ Fi.CI.BAT: success for drm/i915: Fix possible null pointer dereference after drm_dbg_printer conversion
== Series Details ==
Series: drm/i915: Fix possible null pointer dereference after drm_dbg_printer
conversion
URL : https://patchwork.freedesktop.org/series/130080/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14297 -> Patchwork_130080v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130080v1/index.html
Participating hosts (36 -> 36)
--
Additional (1): bat-kbl-2
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_130080v1 that come from known issues:
### CI changes ###
Issues hit
* boot:
- bat-jsl-1: [PASS][1] -> [FAIL][2] ([i915#8293])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14297/bat-jsl-1/boot.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130080v1/bat-jsl-1/boot.html
- fi-cfl-8109u: [PASS][3] -> [FAIL][4] ([i915#8293])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14297/fi-cfl-8109u/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130080v1/fi-cfl-8109u/boot.html
### IGT changes ###
Issues hit
* igt@fbdev@info:
- bat-kbl-2: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1849])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130080v1/bat-kbl-2/igt@fb...@info.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2: NOTRUN -> [SKIP][6] ([fdo#109271]) +35 other tests
skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130080v1/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][7] -> [ABORT][8] ([i915#7911])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14297/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130080v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#10194]: https://gitlab.freedesktop.org/drm/intel/issues/10194
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
Build changes
-
* Linux: CI_DRM_14297 -> Patchwork_130080v1
CI-20190529: 20190529
CI_DRM_14297: 52bdc58b3b2bd7b77710f0d6710c1b9dbaee1af9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7718: 40e8b9122853f455c84afcfa56469a6bc9a0d564 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_130080v1: 52bdc58b3b2bd7b77710f0d6710c1b9dbaee1af9 @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
c6715af47a3f drm/i915: Fix possible null pointer dereference after
drm_dbg_printer conversion
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130080v1/index.html
✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix possible null pointer dereference after drm_dbg_printer conversion
== Series Details == Series: drm/i915: Fix possible null pointer dereference after drm_dbg_printer conversion URL : https://patchwork.freedesktop.org/series/130080/ State : warning == Summary == Error: dim checkpatch failed ef035cbfb4b9 drm/i915: Fix possible null pointer dereference after drm_dbg_printer conversion -:12: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report #12: Reported-by: Dan Carpenter Cc: Jani Nikula total: 0 errors, 1 warnings, 0 checks, 10 lines checked
Re: [PATCH v5] drm/dp: add an API to indicate if sink supports VSC SDP
Hi DRM maintainers
Gentle ping for reviews on this one.
Since the dependent series is mostly complete, would like to get your
reviews on this one to land it.
Thanks
Abhinav
On 2/15/2024 11:15 AM, Abhinav Kumar wrote:
From: Paloma Arellano
YUV420 format is supported only in the VSC SDP packet and not through
MSA. Hence add an API which indicates the sink support which can be used
by the rest of the DP programming.
changes in v5:
- rebased on top of drm-tip
changes in v4:
- bail out early if dpcd rev check fails
changes in v3:
- fix the commit title prefix to drm/dp
- get rid of redundant !!
- break out this change from series [1] to get acks from drm core
maintainers
Changes in v2:
- Move VSC SDP support check API from dp_panel.c to
drm_dp_helper.c
[1]: https://patchwork.freedesktop.org/series/129180/
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Paloma Arellano
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/display/drm_dp_helper.c | 23 +++
include/drm/display/drm_dp_helper.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
b/drivers/gpu/drm/display/drm_dp_helper.c
index 8d6ce46471ae..61b11cb45245 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2913,6 +2913,29 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const
struct drm_dp_vsc_sdp *vsc)
}
EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
+/**
+ * drm_dp_vsc_sdp_supported() - check if vsc sdp is supported
+ * @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
+ *
+ * Returns true if vsc sdp is supported, else returns false
+ */
+bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8
dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ u8 rx_feature;
+
+ if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
+ return false;
+
+ if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
_feature) != 1) {
+ drm_dbg_dp(aux->drm_dev, "failed to read
DP_DPRX_FEATURE_ENUMERATION_LIST\n");
+ return false;
+ }
+
+ return (rx_feature & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
+}
+EXPORT_SYMBOL(drm_dp_vsc_sdp_supported);
+
/**
* drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
* @dpcd: DisplayPort configuration data
diff --git a/include/drm/display/drm_dp_helper.h
b/include/drm/display/drm_dp_helper.h
index d02014a87f12..36351f3cdba9 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -100,6 +100,8 @@ struct drm_dp_vsc_sdp {
void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc);
+bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
+
int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
static inline int
✓ Fi.CI.BAT: success for drm/i915: check before removing mm notifier (rev2)
== Series Details ==
Series: drm/i915: check before removing mm notifier (rev2)
URL : https://patchwork.freedesktop.org/series/101170/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14296 -> Patchwork_101170v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101170v2/index.html
Participating hosts (35 -> 36)
--
Additional (2): fi-glk-j4005 bat-kbl-2
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_101170v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@fbdev@info:
- bat-kbl-2: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1849])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101170v2/bat-kbl-2/igt@fb...@info.html
* igt@gem_huc_copy@huc-copy:
- fi-glk-j4005: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101170v2/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-glk-j4005: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3
other tests skip
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101170v2/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2: NOTRUN -> [SKIP][4] ([fdo#109271]) +35 other tests
skip
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101170v2/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-glk-j4005: NOTRUN -> [SKIP][5] ([fdo#109271]) +6 other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101170v2/fi-glk-j4005/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
Possible fixes
* igt@i915_selftest@live@gt_engines:
- {bat-adls-6}: [TIMEOUT][6] ([i915#10026]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/bat-adls-6/igt@i915_selftest@live@gt_engines.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101170v2/bat-adls-6/igt@i915_selftest@live@gt_engines.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#10026]: https://gitlab.freedesktop.org/drm/intel/issues/10026
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
Build changes
-
* Linux: CI_DRM_14296 -> Patchwork_101170v2
CI-20190529: 20190529
CI_DRM_14296: f12bce6493b6443870b55f36b1462d65e450d29d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7716: 7716
Patchwork_101170v2: f12bce6493b6443870b55f36b1462d65e450d29d @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
41493371cc92 drm/i915: check before removing mm notifier
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101170v2/index.html
✓ Fi.CI.BAT: success for drm/i915/cdclk: Rename intel_cdclk_needs_modeset to intel_cdclk_clock_changed (rev2)
== Series Details ==
Series: drm/i915/cdclk: Rename intel_cdclk_needs_modeset to
intel_cdclk_clock_changed (rev2)
URL : https://patchwork.freedesktop.org/series/129908/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14296 -> Patchwork_129908v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129908v2/index.html
Participating hosts (35 -> 35)
--
Additional (1): bat-kbl-2
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_129908v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@fbdev@info:
- bat-kbl-2: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1849])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129908v2/bat-kbl-2/igt@fb...@info.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2: NOTRUN -> [SKIP][2] ([fdo#109271]) +35 other tests
skip
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129908v2/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_module_load@reload:
- fi-skl-6600u: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/fi-skl-6600u/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129908v2/fi-skl-6600u/igt@i915_module_l...@reload.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#9197]) +1 other test skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129908v2/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html
Possible fixes
* igt@i915_selftest@live@gt_engines:
- {bat-adls-6}: [TIMEOUT][6] ([i915#10026]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/bat-adls-6/igt@i915_selftest@live@gt_engines.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129908v2/bat-adls-6/igt@i915_selftest@live@gt_engines.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#10026]: https://gitlab.freedesktop.org/drm/intel/issues/10026
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#9197]: https://gitlab.freedesktop.org/drm/intel/issues/9197
Build changes
-
* Linux: CI_DRM_14296 -> Patchwork_129908v2
CI-20190529: 20190529
CI_DRM_14296: f12bce6493b6443870b55f36b1462d65e450d29d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7716: 7716
Patchwork_129908v2: f12bce6493b6443870b55f36b1462d65e450d29d @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
738af3891e9d drm/i915/cdclk: Rename intel_cdclk_needs_modeset to
intel_cdclk_clock_changed
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129908v2/index.html
✗ Fi.CI.BUILD: failure for drm/i915/display: Allow tighter hblank span
== Series Details == Series: drm/i915/display: Allow tighter hblank span URL : https://patchwork.freedesktop.org/series/130071/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/130071/revisions/1/mbox/ not applied Applying: drm/i915/display: Allow tighter hblank span error: git diff header lacks filename information when removing 1 leading pathname component (line 11) error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm/i915/display: Allow tighter hblank span When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
✗ Fi.CI.SPARSE: warning for drm/i915/cdclk: Rename intel_cdclk_needs_modeset to intel_cdclk_clock_changed (rev2)
== Series Details == Series: drm/i915/cdclk: Rename intel_cdclk_needs_modeset to intel_cdclk_clock_changed (rev2) URL : https://patchwork.freedesktop.org/series/129908/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.BAT: failure for QGV/SAGV related fixes (rev6)
== Series Details == Series: QGV/SAGV related fixes (rev6) URL : https://patchwork.freedesktop.org/series/126962/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14296 -> Patchwork_126962v6 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_126962v6 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_126962v6, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v6/index.html Participating hosts (35 -> 34) -- Additional (1): bat-kbl-2 Missing(2): bat-mtlp-8 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_126962v6: ### IGT changes ### Possible regressions * igt@core_hotunplug@unbind-rebind: - fi-blb-e6850: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v6/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html - fi-elk-e7500: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/fi-elk-e7500/igt@core_hotunp...@unbind-rebind.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v6/fi-elk-e7500/igt@core_hotunp...@unbind-rebind.html * igt@i915_module_load@load: - fi-elk-e7500: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/fi-elk-e7500/igt@i915_module_l...@load.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v6/fi-elk-e7500/igt@i915_module_l...@load.html * igt@i915_pm_rpm@module-reload: - bat-kbl-2: NOTRUN -> [DMESG-WARN][7] +40 other tests dmesg-warn [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v6/bat-kbl-2/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@client: - bat-dg2-8: [PASS][8] -> [DMESG-WARN][9] +40 other tests dmesg-warn [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/bat-dg2-8/igt@i915_selftest@l...@client.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v6/bat-dg2-8/igt@i915_selftest@l...@client.html - fi-kbl-guc: [PASS][10] -> [DMESG-WARN][11] +40 other tests dmesg-warn [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/fi-kbl-guc/igt@i915_selftest@l...@client.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v6/fi-kbl-guc/igt@i915_selftest@l...@client.html * igt@i915_selftest@live@coherency: - bat-dg2-9: [PASS][12] -> [DMESG-WARN][13] +40 other tests dmesg-warn [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/bat-dg2-9/igt@i915_selftest@l...@coherency.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v6/bat-dg2-9/igt@i915_selftest@l...@coherency.html * igt@i915_selftest@live@gem: - fi-rkl-11600: [PASS][14] -> [DMESG-WARN][15] +40 other tests dmesg-warn [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/fi-rkl-11600/igt@i915_selftest@l...@gem.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v6/fi-rkl-11600/igt@i915_selftest@l...@gem.html - fi-pnv-d510:[PASS][16] -> [ABORT][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/fi-pnv-d510/igt@i915_selftest@l...@gem.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v6/fi-pnv-d510/igt@i915_selftest@l...@gem.html * igt@i915_selftest@live@gem_contexts: - fi-cfl-guc: [PASS][18] -> [DMESG-WARN][19] +40 other tests dmesg-warn [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v6/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html - fi-skl-6600u: [PASS][20] -> [DMESG-WARN][21] +38 other tests dmesg-warn [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v6/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html * igt@i915_selftest@live@gt_contexts: - fi-ilk-650: [PASS][22] -> [DMESG-WARN][23] +39 other tests dmesg-warn [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14296/fi-ilk-650/igt@i915_selftest@live@gt_contexts.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126962v6/fi-ilk-650/igt@i915_selftest@live@gt_contexts.html * igt@i915_selftest@live@gt_pm: - fi-tgl-1115g4: [PASS][24] -> [DMESG-WARN][25] +40 other tests
✗ Fi.CI.SPARSE: warning for QGV/SAGV related fixes (rev6)
== Series Details == Series: QGV/SAGV related fixes (rev6) URL : https://patchwork.freedesktop.org/series/126962/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./drivers/gpu/drm/i915/intel_uncore.h:346:1: warning: trying to copy expression type 31 +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val' +./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning:
✗ Fi.CI.CHECKPATCH: warning for QGV/SAGV related fixes (rev6)
== Series Details ==
Series: QGV/SAGV related fixes (rev6)
URL : https://patchwork.freedesktop.org/series/126962/
State : warning
== Summary ==
Error: dim checkpatch failed
e14a10f2859f drm/i915: Add meaningful traces for QGV point info error handling
aa498440ab05 drm/i915: Extract code required to calculate max qgv/psf gv point
e7e9a465da87 drm/i915: Disable SAGV on bw init, to force QGV point recalculation
-:12: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line
(possible unwrapped commit description?)
#12:
(i.e all points allowed), however in reality we might get them all restricted,
-:45: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/display/intel_bw.c:165:
+ drm_err(_priv->drm, "Failed to disable qgv points (%x)
points: 0x%x\n", ret, points_mask);
-:87: CHECK:BRACES: braces {} should be used on all arms of this statement
#87: FILE: drivers/gpu/drm/i915/display/intel_bw.c:871:
+ if (max_data_rate > max_bw) {
[...]
+ } else if (max_data_rate == max_bw)
[...]
-:108: CHECK:SPACING: space preferred before that '|' (ctx:VxE)
#108: FILE: drivers/gpu/drm/i915/display/intel_bw.c:892:
+ bw_state->qgv_points_mask = ~(ICL_PCODE_REQ_QGV_PT(qgv_points)|
^
-:121: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#121: FILE: drivers/gpu/drm/i915/display/intel_bw.c:905:
+
+}
total: 0 errors, 2 warnings, 3 checks, 98 lines checked
Re: [PATCH] drm/i915: Add some boring kerneldoc
On Mon, 2024-02-19 at 13:25 +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Tooling appears very strict so lets pacify it by adding some comments,
> even if fields are completely self-explanatory.
>
Reviewed-by: José Roberto de Souza
> Signed-off-by: Tvrtko Ursulin
> Fixes: b11236486749 ("drm/i915: Add GuC submission interface version query")
> Reported-by: Stephen Rothwell
> Cc: Jose Souza
> ---
> include/uapi/drm/i915_drm.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index bd87386a8243..2ee338860b7e 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -3572,9 +3572,13 @@ struct drm_i915_query_memory_regions {
> * struct drm_i915_query_guc_submission_version - query GuC submission
> interface version
> */
> struct drm_i915_query_guc_submission_version {
> + /** @branch: Firmware branch version. */
> __u32 branch;
> + /** @major: Firmware major version. */
> __u32 major;
> + /** @minor: Firmware minor version. */
> __u32 minor;
> + /** @patch: Firmware patch version. */
> __u32 patch;
> };
>
[PATCH] drm/i915: Add some boring kerneldoc
From: Tvrtko Ursulin
Tooling appears very strict so lets pacify it by adding some comments,
even if fields are completely self-explanatory.
Signed-off-by: Tvrtko Ursulin
Fixes: b11236486749 ("drm/i915: Add GuC submission interface version query")
Reported-by: Stephen Rothwell
Cc: Jose Souza
---
include/uapi/drm/i915_drm.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index bd87386a8243..2ee338860b7e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3572,9 +3572,13 @@ struct drm_i915_query_memory_regions {
* struct drm_i915_query_guc_submission_version - query GuC submission
interface version
*/
struct drm_i915_query_guc_submission_version {
+ /** @branch: Firmware branch version. */
__u32 branch;
+ /** @major: Firmware major version. */
__u32 major;
+ /** @minor: Firmware minor version. */
__u32 minor;
+ /** @patch: Firmware patch version. */
__u32 patch;
};
--
2.40.1
[PATCH] drm/i915: Fix possible null pointer dereference after drm_dbg_printer conversion
From: Tvrtko Ursulin
Request can be NULL if no guilty request was identified so simply use
engine->i915 instead.
Signed-off-by: Tvrtko Ursulin
Fixes: d50892a9554c ("drm/i915: switch from drm_debug_printer() to device
specific drm_dbg_printer()")
Reported-by: Dan Carpenter
Cc: Jani Nikula
Cc: Luca Coelho
Cc: Maxime Ripard
Cc: Jani Nikula
---
drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index 5f8d86e25993..8d4bb95f8424 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -96,8 +96,8 @@ static void heartbeat_commit(struct i915_request *rq,
static void show_heartbeat(const struct i915_request *rq,
struct intel_engine_cs *engine)
{
- struct drm_printer p = drm_dbg_printer(>i915->drm, DRM_UT_DRIVER,
- "heartbeat");
+ struct drm_printer p =
+ drm_dbg_printer(>i915->drm, DRM_UT_DRIVER, "heartbeat");
if (!rq) {
intel_engine_dump(engine, ,
--
2.40.1
[PATCH] drm/i915: check before removing mm notifier
Error in mmu_interval_notifier_insert() can leave a NULL
notifier.mm pointer. Catch that and return early.
Cc: Andi Shyti
Cc: Shawn Lee
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 0e21ce9d3e5a..61abfb505766 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -349,6 +349,9 @@ i915_gem_userptr_release(struct drm_i915_gem_object *obj)
{
GEM_WARN_ON(obj->userptr.page_ref);
+ if (!obj->userptr.notifier.mm)
+ return;
+
mmu_interval_notifier_remove(>userptr.notifier);
obj->userptr.notifier.mm = NULL;
}
--
2.42.0
Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
On 19/02/2024 11:16, Tvrtko Ursulin wrote:
On 15/02/2024 13:59, Andi Shyti wrote:
Since CCS automatic load balancing is disabled, we will impose a
fixed balancing policy that involves setting all the CCS engines
to work together on the same load.
Simultaneously, the user will see only 1 CCS rather than the
actual number. As of now, this change affects only DG2.
Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: # v6.2+
---
drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 17 +
drivers/gpu/drm/i915/i915_query.c | 5 +++--
4 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index a425db5ed3a2..e19df4ef47f6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt)
}
}
+static void intel_gt_apply_ccs_mode(struct intel_gt *gt)
+{
+ if (!IS_DG2(gt->i915))
+ return;
+
+ intel_uncore_write(gt->uncore, XEHP_CCS_MODE, 0);
+}
+
int intel_gt_init_hw(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)
intel_gt_init_swizzling(gt);
+ /* Configure CCS mode */
+ intel_gt_apply_ccs_mode(gt);
+
/*
* At least 830 can leave some of the unused rings
* "active" (ie. head != tail) after resume which
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index cf709f6c05ae..c148113770ea 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1605,6 +1605,8 @@
#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
+#define XEHP_CCS_MODE _MMIO(0x14804)
+
#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
#define GEN12_HECI_2 (30)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index e81b3b2858ac..0853ffd3cb8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct
drm_i915_private *i915)
(engine__); \
(engine__) =
rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
+/*
+ * Exclude unavailable engines.
+ *
+ * Only the first CCS engine is utilized due to the disabling of CCS
auto load
+ * balancing. As a result, all CCS engines operate collectively,
functioning
+ * essentially as a single CCS engine, hence the count of active CCS
engines is
+ * considered '1'.
+ * Currently, this applies to platforms with more than one CCS engine,
+ * specifically DG2.
+ */
+#define for_each_available_uabi_engine(engine__, i915__) \
+ for_each_uabi_engine(engine__, i915__) \
+ if ((IS_DG2(i915__)) && \
+ ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \
+ ((engine__)->uabi_instance)) { } \
+ else
+
If you don't want userspace to see some engines, just don't add them to
the uabi list in intel_engines_driver_register or thereabouts?
Similar as we do for gsc which uses I915_NO_UABI_CLASS, although for ccs
you can choose a different approach, whatever is more elegant.
That is also needed for i915->engine_uabi_class_count to be right, so
userspace stats which rely on it are correct.
I later realized it is more than that - everything that uses
intel_engine_lookup_user to look up class instance passed in from
userspace relies on the engine not being on the user list otherwise
userspace could bypass the fact engine query does not list it. Like PMU,
Perf/POA, context engine map and SSEU context query.
Regards,
Tvrtko
Regards,
Tvrtko
#define INTEL_INFO(i915) ((i915)->__info)
#define RUNTIME_INFO(i915) (&(i915)->__runtime)
#define DRIVER_CAPS(i915) (&(i915)->caps)
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index fa3e937ed3f5..2d41bda626a6 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -124,6 +124,7 @@ static int query_geometry_subslices(struct
drm_i915_private *i915,
return fill_topology_info(sseu, query_item,
sseu->geometry_subslice_mask);
}
+
static int
query_engine_info(struct drm_i915_private *i915,
struct drm_i915_query_item *query_item)
@@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,
if (query_item->flags)
return -EINVAL;
- for_each_uabi_engine(engine, i915)
+ for_each_available_uabi_engine(engine, i915)
num_uabi_engines++;
len =
Re: PR for new GuC v70.20.0 binaries
On Fri, Feb 16, 2024 at 4:16 PM wrote: > > The following changes since commit fbef4d381e3d0143427e1a8c924be8e738c0fc2d: > > Merge branch 'main' into 'main' (2024-02-08 12:24:01 +) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-firmware guc_70.20.0 Merged and pushed out. https://gitlab.com/kernel-firmware/linux-firmware/-/merge_requests/156 josh > > for you to fetch changes up to 28c2472d37d089edb56c75e3af83511babaa756c: > > xe: First GuC release for LNL and Xe (2024-02-14 16:28:32 -0800) > > > John Harrison (2): > i915: Add GuC v70.20.0 for ADL-P, DG1, DG2, MTL and TGL > xe: First GuC release for LNL and Xe > > LICENSE.xe | 39 +++ > WHENCE | 20 ++-- > i915/adlp_guc_70.bin | Bin 342848 -> 347584 bytes > i915/dg1_guc_70.bin | Bin 272512 -> 321472 bytes > i915/dg2_guc_70.bin | Bin 443200 -> 410368 bytes > i915/mtl_guc_70.bin | Bin 365376 -> 332544 bytes > i915/tgl_guc_70.bin | Bin 330304 -> 335168 bytes > xe/lnl_guc_70.bin| Bin 0 -> 336640 bytes > 8 files changed, 53 insertions(+), 6 deletions(-) > create mode 100644 LICENSE.xe > create mode 100644 xe/lnl_guc_70.bin
Re: [PATCH 17/28] drm/i915: Define segmented Lut and add capabilities to colorop
On Mon, 19 Feb 2024 10:34:19 +
"Shankar, Uma" wrote:
> > -Original Message-
> > From: Pekka Paalanen
> > Sent: Wednesday, February 14, 2024 2:34 PM
> > To: Shankar, Uma
> > Cc: ville.syrj...@linux.intel.com; intel-gfx@lists.freedesktop.org; dri-
> > de...@lists.freedesktop.org; cont...@emersion.fr; harry.wentl...@amd.com;
> > m...@igalia.com; jad...@redhat.com; sebastian.w...@redhat.com;
> > shashank.sha...@amd.com; ago...@nvidia.com; jos...@froggi.es;
> > mdaen...@redhat.com; aleix...@kde.org; xaver.h...@gmail.com;
> > victo...@system76.com; dan...@ffwll.ch; quic_nas...@quicinc.com;
> > quic_cbr...@quicinc.com; quic_abhin...@quicinc.com; arthurgri...@riseup.net;
> > mar...@marcan.st; liviu.du...@arm.com; sashamcint...@google.com;
> > s...@poorly.run
> > Subject: Re: [PATCH 17/28] drm/i915: Define segmented Lut and add
> > capabilities
> > to colorop
> >
> > On Wed, 14 Feb 2024 07:28:37 +
> > "Shankar, Uma" wrote:
> >
> > > > -Original Message-
> > > > From: dri-devel On Behalf
> > > > Of Pekka Paalanen
> > > > Sent: Tuesday, February 13, 2024 3:07 PM
> > > > To: Shankar, Uma
> > > > Cc: intel-gfx@lists.freedesktop.org;
> > > > dri-de...@lists.freedesktop.org; ville.syrj...@linux.intel.com;
> > > > cont...@emersion.fr; harry.wentl...@amd.com; m...@igalia.com;
> > > > jad...@redhat.com; sebastian.w...@redhat.com;
> > > > shashank.sha...@amd.com; ago...@nvidia.com; jos...@froggi.es;
> > > > mdaen...@redhat.com; aleix...@kde.org; xaver.h...@gmail.com;
> > > > victo...@system76.com; dan...@ffwll.ch; quic_nas...@quicinc.com;
> > > > quic_cbr...@quicinc.com; quic_abhin...@quicinc.com;
> > > > arthurgri...@riseup.net; mar...@marcan.st; liviu.du...@arm.com;
> > > > sashamcint...@google.com; s...@poorly.run
> > > > Subject: Re: [PATCH 17/28] drm/i915: Define segmented Lut and add
> > > > capabilities to colorop
> > > >
> > > > On Tue, 13 Feb 2024 12:18:24 +0530
> > > > Uma Shankar wrote:
> > > >
> > > > > This defines the lut segments and create the color pipeline
> > > > >
> > > > > Signed-off-by: Uma Shankar
> > > > > Signed-off-by: Chaitanya Kumar Borah
> > > > >
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_color.c | 109
> > > > > +
> > > > > 1 file changed, 109 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > > > > b/drivers/gpu/drm/i915/display/intel_color.c
> > > > > index e223edbe4c13..223cd1ff7291 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > > > > @@ -3811,6 +3811,105 @@ static const struct intel_color_funcs
> > > > ilk_color_funcs = {
> > > > > .get_config = ilk_get_config,
> > > > > };
> > > > >
> > > > > +static const struct drm_color_lut_range xelpd_degamma_hdr[] = {
> > > > > + /* segment 1 */
> > > > > + {
> > > > > + .flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
> > > > > + DRM_MODE_LUT_INTERPOLATE |
> > > > > + DRM_MODE_LUT_NON_DECREASING),
> > > >
> > > > Hi Uma,
> > > >
> > > > is it a good idea to have these flags per-segment?
> > > >
> > > > I would find it very strange, unusable really, if REFLECT_NEGATIVE
> > > > applied on some but not all segments, for example. Is such
> > > > flexibility really necessary in the hardware description?
> > >
> > > Hi Pekka,
> > > Idea to have these flags is to just have some option in case there are
> > > some differences across segments. Most cases this should not be the
> > > case, just helps to future proof the implementation.
> > >
> > > Based on how the community feels on the usability of it, we can take a
> > > call on the flags and the expected interpretation for the same. We are
> > > open for
> > suggestions on the same.
> > >
> > > >
> > > > > + .count = 128,
> > > > > + .input_bpc = 24, .output_bpc = 16,
> > > >
> > > > The same question about input_bpc and output_bpc.
> > >
> > > Same for these as well, userspace can just ignore these if no usage.
> > > However, for some clients it may help in Lut computations.
> > > The original idea for the structure came from Ville (missed to mention
> > > that in cover letter, will get that updated in next version).
> > >
> > > @ville.syrj...@linux.intel.com Please share your inputs on the usability
> > > of these
> > attributes.
> >
> > Userspace will always need to evaluate whether each segment is good enough
> > individually, so maybe it's not that big deal.
> >
> > Ignoring these is not an option for userspace, because that would mean
> > userspace
> > does not know what it is getting. If UAPI contains a parameter, then the
> > onus is on
> > userspace to ensure the value is acceptable.
>
> Got your point, the parameters, and expectations with it should be clearly
> defined.
> Here it just means what is the bpc which is fed to the color block and at
> what bpc
> results
[PATCH] drm/i915/display: Allow tighter hblank span
I ran into an issue with the i915 driver not being able to drive a display
with this specific modeline:
[drm]] Modeline "1920x720": 60 120980 1920 1932 1936 1948 720 723 733 1035
0x48 0x9
[drm:drm_mode_prune_invalid [drm]] Not using 1920x720 mode: H_ILLEGAL
After some investigation I found that intel_mode_valid (and in newer
kernels, intel_cpu_transcoder_mode_valid) returns MODE_H_ILLEGAL due to
(htotal - hdisplay) being lower than 32.
The modeline in question indeed does not satisfy this constraint, as
HTOTAL(1948) - HDISPLAY(1920) equals 28.
Changing the driver code to allow for a hblank span of 28 pixels or lower
resulted in the driver successfully rendering to the display.
As such I propose this patch to allow for a tighter hblank span.
Nb: I am uncertain if the hblank span of 32 pixels has been chosen
deliberately and what the side-effects could be of lowering this value.
Any insights into this or alternative solutions would be very much
appreciated! I also considered introducing a kernel module parameter to
optionally loosen these mode constraints.
The referenced modeline is present in a line of ultrawide signage displays
and has been known to work on other graphics drivers/OSes.
Signed-off-by: Sebastiaan Schalbroeck
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b10aad1..f6aba1d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7745,13 +7745,13 @@ enum drm_mode_status
intel_cpu_transcoder_mode_valid(struct drm_i915_private *de
*/
if (DISPLAY_VER(dev_priv) >= 5) {
if (mode->hdisplay < 64 ||
- mode->htotal - mode->hdisplay < 32)
+ mode->htotal - mode->hdisplay < 28)
return MODE_H_ILLEGAL;
if (mode->vtotal - mode->vdisplay < 5)
return MODE_V_ILLEGAL;
} else {
- if (mode->htotal - mode->hdisplay < 32)
+ if (mode->htotal - mode->hdisplay < 28)
return MODE_H_ILLEGAL;
if (mode->vtotal - mode->vdisplay < 3)
--
2.39.2
Linux 6.7 fails to boot on Core Ultra 155H with "i915 GT1 GSC proxy" error
Hi, I've first filled the bug in openSUSE Tumbleweed bugtracker (https://bugzilla.opensuse.org/show_bug.cgi?id=1219899) and then found Intel GFX CI and that it reliably triggers the same error in Arrow Lake BAT runs. Don't know what else to say, so yeah, system does not boot. Is it expected? I'm trying to install other distributions now to see if there is something different in their kernels.
Re: [PATCH 2/2] drm/i915/gt: Set default CCS mode '1'
On 15/02/2024 13:59, Andi Shyti wrote:
Since CCS automatic load balancing is disabled, we will impose a
fixed balancing policy that involves setting all the CCS engines
to work together on the same load.
Simultaneously, the user will see only 1 CCS rather than the
actual number. As of now, this change affects only DG2.
Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: # v6.2+
---
drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 17 +
drivers/gpu/drm/i915/i915_query.c | 5 +++--
4 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index a425db5ed3a2..e19df4ef47f6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -168,6 +168,14 @@ static void init_unused_rings(struct intel_gt *gt)
}
}
+static void intel_gt_apply_ccs_mode(struct intel_gt *gt)
+{
+ if (!IS_DG2(gt->i915))
+ return;
+
+ intel_uncore_write(gt->uncore, XEHP_CCS_MODE, 0);
+}
+
int intel_gt_init_hw(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -195,6 +203,9 @@ int intel_gt_init_hw(struct intel_gt *gt)
intel_gt_init_swizzling(gt);
+ /* Configure CCS mode */
+ intel_gt_apply_ccs_mode(gt);
+
/*
* At least 830 can leave some of the unused rings
* "active" (ie. head != tail) after resume which
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index cf709f6c05ae..c148113770ea 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1605,6 +1605,8 @@
#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
+#define XEHP_CCS_MODE _MMIO(0x14804)
+
#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
#define GEN12_HECI_2(30)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e81b3b2858ac..0853ffd3cb8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -396,6 +396,23 @@ static inline struct intel_gt *to_gt(const struct
drm_i915_private *i915)
(engine__); \
(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
+/*
+ * Exclude unavailable engines.
+ *
+ * Only the first CCS engine is utilized due to the disabling of CCS auto load
+ * balancing. As a result, all CCS engines operate collectively, functioning
+ * essentially as a single CCS engine, hence the count of active CCS engines is
+ * considered '1'.
+ * Currently, this applies to platforms with more than one CCS engine,
+ * specifically DG2.
+ */
+#define for_each_available_uabi_engine(engine__, i915__) \
+ for_each_uabi_engine(engine__, i915__) \
+ if ((IS_DG2(i915__)) && \
+ ((engine__)->uabi_class == I915_ENGINE_CLASS_COMPUTE) && \
+ ((engine__)->uabi_instance)) { } \
+ else
+
If you don't want userspace to see some engines, just don't add them to
the uabi list in intel_engines_driver_register or thereabouts?
Similar as we do for gsc which uses I915_NO_UABI_CLASS, although for ccs
you can choose a different approach, whatever is more elegant.
That is also needed for i915->engine_uabi_class_count to be right, so
userspace stats which rely on it are correct.
Regards,
Tvrtko
#define INTEL_INFO(i915) ((i915)->__info)
#define RUNTIME_INFO(i915)(&(i915)->__runtime)
#define DRIVER_CAPS(i915) (&(i915)->caps)
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index fa3e937ed3f5..2d41bda626a6 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -124,6 +124,7 @@ static int query_geometry_subslices(struct drm_i915_private
*i915,
return fill_topology_info(sseu, query_item,
sseu->geometry_subslice_mask);
}
+
static int
query_engine_info(struct drm_i915_private *i915,
struct drm_i915_query_item *query_item)
@@ -140,7 +141,7 @@ query_engine_info(struct drm_i915_private *i915,
if (query_item->flags)
return -EINVAL;
- for_each_uabi_engine(engine, i915)
+ for_each_available_uabi_engine(engine, i915)
num_uabi_engines++;
len = struct_size(query_ptr, engines, num_uabi_engines);
@@ -155,7 +156,7 @@ query_engine_info(struct drm_i915_private *i915,
info_ptr = _ptr->engines[0];
- for_each_uabi_engine(engine, i915) {
+ for_each_available_uabi_engine(engine, i915) {
Re: [PATCH 05/13] drm/i915/hdcp: Rename hdcp capable functions
On 2/15/2024 4:29 PM, Suraj Kandpal wrote:
Rename hdcp_capable and hdcp_2_2_capable to hdcp_get_capability
and hdcp_2_2_get_capability to properly reflect what these functions
are doing.
Signed-off-by: Suraj Kandpal
LGTM.
Reviewed-by: Ankit Nautiyal
---
.../drm/i915/display/intel_display_debugfs.c | 4 ++--
.../drm/i915/display/intel_display_types.h| 8 +++
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 22 +--
drivers/gpu/drm/i915/display/intel_hdcp.c | 18 +++
drivers/gpu/drm/i915/display/intel_hdcp.h | 4 ++--
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 ++---
6 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 6f2d13c8ccf7..676ad082f0f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -197,8 +197,8 @@ static void intel_hdcp_info(struct seq_file *m,
goto out;
}
- hdcp_cap = intel_hdcp_capable(intel_connector);
- hdcp2_cap = intel_hdcp2_capable(intel_connector);
+ hdcp_cap = intel_hdcp_get_capability(intel_connector);
+ hdcp2_cap = intel_hdcp2_get_capability(intel_connector);
if (hdcp_cap)
seq_puts(m, "HDCP1.4 ");
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index ae2e8cff9d69..b77070d0897c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -499,15 +499,15 @@ struct intel_hdcp_shim {
struct intel_connector *connector);
/* Detects panel's hdcp capability. This is optional for HDMI. */
- int (*hdcp_capable)(struct intel_digital_port *dig_port,
- bool *hdcp_capable);
+ int (*hdcp_get_capability)(struct intel_digital_port *dig_port,
+ bool *hdcp_capable);
/* HDCP adaptation(DP/HDMI) required on the port */
enum hdcp_wired_protocol protocol;
/* Detects whether sink is HDCP2.2 capable */
- int (*hdcp_2_2_capable)(struct intel_connector *connector,
- bool *capable);
+ int (*hdcp_2_2_get_capability)(struct intel_connector *connector,
+ bool *capable);
/* Write HDCP2.2 messages */
int (*write_2_2_msg)(struct intel_connector *connector,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index ef1a4c90c225..91736c7e3c83 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -266,8 +266,8 @@ bool intel_dp_hdcp_check_link(struct intel_digital_port
*dig_port,
}
static
-int intel_dp_hdcp_capable(struct intel_digital_port *dig_port,
- bool *hdcp_capable)
+int intel_dp_hdcp_get_capability(struct intel_digital_port *dig_port,
+bool *hdcp_capable)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
ssize_t ret;
@@ -638,8 +638,8 @@ int intel_dp_hdcp2_check_link(struct intel_digital_port
*dig_port,
}
static
-int _intel_dp_hdcp2_capable(struct drm_dp_aux *aux,
- bool *capable)
+int _intel_dp_hdcp2_get_capability(struct drm_dp_aux *aux,
+ bool *capable)
{
u8 rx_caps[3];
int ret;
@@ -659,13 +659,13 @@ int _intel_dp_hdcp2_capable(struct drm_dp_aux *aux,
}
static
-int intel_dp_hdcp2_capable(struct intel_connector *connector,
- bool *capable)
+int intel_dp_hdcp2_get_capability(struct intel_connector *connector,
+ bool *capable)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_dp_aux *aux = _port->dp.aux;
- return _intel_dp_hdcp2_capable(aux, capable);
+ return _intel_dp_hdcp2_get_capability(aux, capable);
}
static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
@@ -679,12 +679,12 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
.read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
.toggle_signalling = intel_dp_hdcp_toggle_signalling,
.check_link = intel_dp_hdcp_check_link,
- .hdcp_capable = intel_dp_hdcp_capable,
+ .hdcp_get_capability = intel_dp_hdcp_get_capability,
.write_2_2_msg = intel_dp_hdcp2_write_msg,
.read_2_2_msg = intel_dp_hdcp2_read_msg,
.config_stream_type = intel_dp_hdcp2_config_stream_type,
.check_2_2_link = intel_dp_hdcp2_check_link,
- .hdcp_2_2_capable = intel_dp_hdcp2_capable,
+ .hdcp_2_2_get_capability = intel_dp_hdcp2_get_capability,
.protocol = HDCP_PROTOCOL_DP,
};
RE: [PATCH 00/28] Plane Color Pipeline support for Intel platforms
> -Original Message- > From: Harry Wentland > Sent: Saturday, February 17, 2024 3:17 AM > To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; > dri- > de...@lists.freedesktop.org > Cc: ville.syrj...@linux.intel.com; pekka.paala...@collabora.com; > cont...@emersion.fr; m...@igalia.com; jad...@redhat.com; > sebastian.w...@redhat.com; shashank.sha...@amd.com; ago...@nvidia.com; > jos...@froggi.es; mdaen...@redhat.com; aleix...@kde.org; > xaver.h...@gmail.com; victo...@system76.com; dan...@ffwll.ch; > quic_nas...@quicinc.com; quic_cbr...@quicinc.com; > quic_abhin...@quicinc.com; arthurgri...@riseup.net; mar...@marcan.st; > liviu.du...@arm.com; sashamcint...@google.com; s...@poorly.run; Borah, > Chaitanya Kumar > Subject: Re: [PATCH 00/28] Plane Color Pipeline support for Intel platforms > > > > On 2024-02-13 01:48, Uma Shankar wrote: > > This series intends to add support for Plane Color Management for > > Intel platforms. This is based on the design which has been agreed > > upon by the community. Series implementing the design for generic DRM > > core has been sent out by Harry Wentland and is under review > > below: > > https://patchwork.freedesktop.org/series/123446/ > > > > The base work of above series is squashed under 1 patch and support > > for Intel platform is added on top of it. > > Any reviews on the original core design is expected to be done in > > Harry's series to avoid any forking of the discussion. > > > > We have added some changes/fixes to the Harry's core DRM changes, > > being put up as separate patches on top of squashed patch. These are > > expected to get included in the main series from Harry once agreed upon. > > > > Changes added on core design: > > 1. Below patches implement some fixes on original series > > drm: Add missing function declarations > > drm: handle NULL next colorop in drm_colorop_set_next_property > > drm: Fix error logging in set Color Pipeline > > > > 2. Implemented a HW capability property to expose segmented luts. > > drm: Add Color lut range attributes > > drm: Add Color ops capability property > > drm: Define helper to create color ops capability property > > drm: Define helper for adding capability property for 1D LUT > > > > This helps in generically defining the hardware lut capabilities, lut > > distribution, precision, segmented or PWL LUTS. > > > > 3. Added support for enhanced prescision, 3x3 matrix and 1d LUT: > > drm: Add Enhanced LUT precision structure > > drm: Add support for 3x3 CTM > > drm: Add 1D LUT color op > > > > On top of this base work for DRM core plane color pipeline design, > > implementation is done for Intel hardware platforms. Below patches > > include the same: > > > > drm/i915: Add identifiers for intel color blocks > > drm/i915: Add intel_color_op > > drm/i915/color: Add helper to allocate intel colorop > > drm/i915/color: Add helper to create intel colorop > > drm/i915/color: Create a transfer function color pipeline > > drm/i915/color: Add and attach COLORPIPELINE plane property > > drm/i915/color: Add framework to set colorop > > drm/i915/color: Add callbacks to set plane CTM > > drm/i915/color: Add framework to program PRE/POST CSC LUT > > FIXME: force disable legacy plane color properties for TGL and beyond > > drm/i915/color: Enable Plane Color Pipelines > > drm/i915: Define segmented Lut and add capabilities to colorop > > drm/i915/color: Add plane CTM callback for TGL and beyond > > drm/i915: Add register definitions for Plane Degamma > > drm/i915: Add register definitions for Plane Post CSC > > drm/i915/color: Program Pre-CSC registers > > drm/i915/xelpd: Program Plane Post CSC Registers > > > > Bhanu from Intel will be sending out the igt changes to help test the > > color pipeline implementation based on the current igt changes sent > > out by Harry. > > https://patchwork.freedesktop.org/series/123448/ > > > > Planned Next Steps: > > 1. Work with Harry and community and get DRM core changes for color > > pipeline merged. > > We'll need a userspace to implement support before merging, but we're working > to enabling all color properties gamescope currently uses for the SteamDeck > color > management to the Color Pipeline API, which should help us get there. It's > still a > journey but I think the path is clear. Yeah, thanks Harry for driving it. > I'll send a new version of my patch series next week, including some AMD > implementation (not the entire AMD pipeline yet). Oh ok, Nice. One more input which can be considered: Currently this is plane level color management (pre blending), can we make names of function also like that ? We can later work on pipe level color (post blending) on top of it without any major rework. Eventually this support will be needed for post blending as well (current properties will fall short on modern hardware). > We're also adding a 1D_LUT type that's much simpler, basically a copy of what > the > drm_crtc currently uses. One option is to keep both types, another
RE: [PATCH 17/28] drm/i915: Define segmented Lut and add capabilities to colorop
> -Original Message-
> From: Pekka Paalanen
> Sent: Wednesday, February 14, 2024 2:34 PM
> To: Shankar, Uma
> Cc: ville.syrj...@linux.intel.com; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; cont...@emersion.fr; harry.wentl...@amd.com;
> m...@igalia.com; jad...@redhat.com; sebastian.w...@redhat.com;
> shashank.sha...@amd.com; ago...@nvidia.com; jos...@froggi.es;
> mdaen...@redhat.com; aleix...@kde.org; xaver.h...@gmail.com;
> victo...@system76.com; dan...@ffwll.ch; quic_nas...@quicinc.com;
> quic_cbr...@quicinc.com; quic_abhin...@quicinc.com; arthurgri...@riseup.net;
> mar...@marcan.st; liviu.du...@arm.com; sashamcint...@google.com;
> s...@poorly.run
> Subject: Re: [PATCH 17/28] drm/i915: Define segmented Lut and add capabilities
> to colorop
>
> On Wed, 14 Feb 2024 07:28:37 +
> "Shankar, Uma" wrote:
>
> > > -Original Message-
> > > From: dri-devel On Behalf
> > > Of Pekka Paalanen
> > > Sent: Tuesday, February 13, 2024 3:07 PM
> > > To: Shankar, Uma
> > > Cc: intel-gfx@lists.freedesktop.org;
> > > dri-de...@lists.freedesktop.org; ville.syrj...@linux.intel.com;
> > > cont...@emersion.fr; harry.wentl...@amd.com; m...@igalia.com;
> > > jad...@redhat.com; sebastian.w...@redhat.com;
> > > shashank.sha...@amd.com; ago...@nvidia.com; jos...@froggi.es;
> > > mdaen...@redhat.com; aleix...@kde.org; xaver.h...@gmail.com;
> > > victo...@system76.com; dan...@ffwll.ch; quic_nas...@quicinc.com;
> > > quic_cbr...@quicinc.com; quic_abhin...@quicinc.com;
> > > arthurgri...@riseup.net; mar...@marcan.st; liviu.du...@arm.com;
> > > sashamcint...@google.com; s...@poorly.run
> > > Subject: Re: [PATCH 17/28] drm/i915: Define segmented Lut and add
> > > capabilities to colorop
> > >
> > > On Tue, 13 Feb 2024 12:18:24 +0530
> > > Uma Shankar wrote:
> > >
> > > > This defines the lut segments and create the color pipeline
> > > >
> > > > Signed-off-by: Uma Shankar
> > > > Signed-off-by: Chaitanya Kumar Borah
> > > >
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_color.c | 109
> > > > +
> > > > 1 file changed, 109 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > > > b/drivers/gpu/drm/i915/display/intel_color.c
> > > > index e223edbe4c13..223cd1ff7291 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > > > @@ -3811,6 +3811,105 @@ static const struct intel_color_funcs
> > > ilk_color_funcs = {
> > > > .get_config = ilk_get_config,
> > > > };
> > > >
> > > > +static const struct drm_color_lut_range xelpd_degamma_hdr[] = {
> > > > + /* segment 1 */
> > > > + {
> > > > + .flags = (DRM_MODE_LUT_REFLECT_NEGATIVE |
> > > > + DRM_MODE_LUT_INTERPOLATE |
> > > > + DRM_MODE_LUT_NON_DECREASING),
> > >
> > > Hi Uma,
> > >
> > > is it a good idea to have these flags per-segment?
> > >
> > > I would find it very strange, unusable really, if REFLECT_NEGATIVE
> > > applied on some but not all segments, for example. Is such
> > > flexibility really necessary in the hardware description?
> >
> > Hi Pekka,
> > Idea to have these flags is to just have some option in case there are
> > some differences across segments. Most cases this should not be the
> > case, just helps to future proof the implementation.
> >
> > Based on how the community feels on the usability of it, we can take a
> > call on the flags and the expected interpretation for the same. We are open
> > for
> suggestions on the same.
> >
> > >
> > > > + .count = 128,
> > > > + .input_bpc = 24, .output_bpc = 16,
> > >
> > > The same question about input_bpc and output_bpc.
> >
> > Same for these as well, userspace can just ignore these if no usage.
> > However, for some clients it may help in Lut computations.
> > The original idea for the structure came from Ville (missed to mention
> > that in cover letter, will get that updated in next version).
> >
> > @ville.syrj...@linux.intel.com Please share your inputs on the usability of
> > these
> attributes.
>
> Userspace will always need to evaluate whether each segment is good enough
> individually, so maybe it's not that big deal.
>
> Ignoring these is not an option for userspace, because that would mean
> userspace
> does not know what it is getting. If UAPI contains a parameter, then the onus
> is on
> userspace to ensure the value is acceptable.
Got your point, the parameters, and expectations with it should be clearly
defined.
Here it just means what is the bpc which is fed to the color block and at what
bpc
results come out after rounding and truncation. This information may help in
computing the LUT co-efficients and get better accuracy.
Having said that, we are not using it as of now in the IGT tests. We can
discuss the
usability and usefulness of this attribute for userspace, based on
recommendation
we
Re: [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS
On Mon, Feb 19, 2024 at 11:17:33AM +0100, Andi Shyti wrote: > On Thu, Feb 15, 2024 at 08:55:41AM -0800, Matt Roper wrote: > > On Thu, Feb 15, 2024 at 02:59:23PM +0100, Andi Shyti wrote: > > > The hardware should not dynamically balance the load between CCS > > > engines. Wa_16016805146 recommends disabling it across all > > > > Is this the right workaround number? When I check the database, this > > workaround was rejected on both DG2-G10 and DG2-G11, and doesn't even > > have an entry for DG2-G12. > > > > There are other workarounds that sound somewhat related to load > > balancing (e.g., part 3 of Wa_14019159160), but what's asked there is > > more involved than just setting one register bit and conflicts a bit > > with the second patch of this series. > > thanks for checking it. Indeed the WA I mentioned is limited to > a specific platform. This recommendation comes in different WA, > e.g. this one: Wa_14019186972 (3rd point). Will start using that > as a reference. actually you are right, I checked with Joonas and I will use Wa_14019159160. Thanks, Andi
Re: [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS
Hi Matt,
On Thu, Feb 15, 2024 at 08:55:41AM -0800, Matt Roper wrote:
> On Thu, Feb 15, 2024 at 02:59:23PM +0100, Andi Shyti wrote:
> > The hardware should not dynamically balance the load between CCS
> > engines. Wa_16016805146 recommends disabling it across all
>
> Is this the right workaround number? When I check the database, this
> workaround was rejected on both DG2-G10 and DG2-G11, and doesn't even
> have an entry for DG2-G12.
>
> There are other workarounds that sound somewhat related to load
> balancing (e.g., part 3 of Wa_14019159160), but what's asked there is
> more involved than just setting one register bit and conflicts a bit
> with the second patch of this series.
thanks for checking it. Indeed the WA I mentioned is limited to
a specific platform. This recommendation comes in different WA,
e.g. this one: Wa_14019186972 (3rd point). Will start using that
as a reference.
Thank you.
Andi
>
>
> Matt
>
> > platforms.
> >
> > Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> > Signed-off-by: Andi Shyti
> > Cc: Chris Wilson
> > Cc: Joonas Lahtinen
> > Cc: Matt Roper
> > Cc: # v6.2+
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
> > 2 files changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 50962cfd1353..cf709f6c05ae 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -1478,6 +1478,7 @@
> >
> > #define GEN12_RCU_MODE _MMIO(0x14800)
> > #define GEN12_RCU_MODE_CCS_ENABLEREG_BIT(0)
> > +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
> >
> > #define CHV_FUSE_GT_MMIO(VLV_GUNIT_BASE +
> > 0x2168)
> > #define CHV_FGT_DISABLE_SS0 (1 << 10)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index d67d44611c28..7f42c8015f71 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct
> > intel_engine_cs *engine, struct i915_wa_li
> > wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> > GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
> > }
> > +
> > + /*
> > +* Wa_16016805146: disable the CCS load balancing
> > +* indiscriminately for all the platforms
> > +*/
> > + wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
> > }
> >
> > static void
> > --
> > 2.43.0
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
Re: [PATCH 2/2] drm/i915/lnl: Program PKGC_LATENCY register
On Mon, 2024-02-19 at 12:06 +0530, Suraj Kandpal wrote:
> If fixed refresh rate program the PKGC_LATENCY register
> with the highest latency from level 1 and above LP registers
> and program ADDED_WAKE_TIME = DSB execution time.
> else program PKGC_LATENCY with all 1's and ADDED_WAKE_TIME as 0.
> This is used to improve package C residency by sending the highest
> latency tolerance requirement (LTR) when the planes are done with the
> frame until the next frame programming window (set context latency,
> window 2) starts.
> Bspec: 68986
>
> --v2
> -Fix indentation [Chaitanya]
>
> --v3
> -Take into account if fixed refrersh rate or not [Vinod]
> -Added wake time dependengt on DSB execution time [Vinod]
> -Use REG_FIELD_PREP [Jani]
> -Call program_pkgc_latency from appropriate place [Jani]
> -no need for the ~0 while setting max latency [Jani]
> -change commit message to add the new changes made in.
>
> --v4
> -Remove extra blank line [Vinod]
> -move the vrr.enable check to previous loop [Vinod]
>
> Signed-off-by: Suraj Kandpal
> Reviewed-by: Chaitanya Kumar Borah
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c | 2 +-
> drivers/gpu/drm/i915/display/skl_watermark.c | 54 +++-
> drivers/gpu/drm/i915/display/skl_watermark.h | 4 +-
> 3 files changed, 55 insertions(+), 5 deletions(-)
Reviewed-by: Vinod Govindapillai
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index a6c7122fd671..d62e050185e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -325,7 +325,7 @@ static int intel_dsb_dewake_scanline(const struct
> intel_crtc_state
> *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> const struct drm_display_mode *adjusted_mode =
> _state->hw.adjusted_mode;
> - unsigned int latency = skl_watermark_max_latency(i915);
> + unsigned int latency = skl_watermark_max_latency(i915, 0);
> int vblank_start;
>
> if (crtc_state->vrr.enable) {
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 614f319d754e..c6b9be80d83c 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -23,6 +23,12 @@
> #include "skl_watermark.h"
> #include "skl_watermark_regs.h"
>
> +/*It is expected that DSB can do posted writes to every register in
> + * the pipe and planes within 100us. For flip queue use case, the
> + * recommended DSB execution time is 100us + one SAGV block time.
> + */
> +#define DSB_EXE_TIME 100
> +
> static void skl_sagv_disable(struct drm_i915_private *i915);
>
> /* Stores plane specific WM parameters */
> @@ -2904,12 +2910,51 @@ static int skl_wm_add_affected_planes(struct
> intel_atomic_state *state,
> return 0;
> }
>
> +/*
> + * If Fixed Refresh Rate:
> + * Program DEEP PKG_C_LATENCY Pkg C with highest valid latency from
> + * watermark level1 and up and above. If watermark level 1 is
> + * invalid program it with all 1's.
> + * Program PKG_C_LATENCY Added Wake Time = DSB execution time
> + * If Variable Refresh Rate:
> + * Program DEEP PKG_C_LATENCY Pkg C with all 1's.
> + * Program PKG_C_LATENCY Added Wake Time = 0
> + */
> +static void
> +skl_program_dpkgc_latency(struct drm_i915_private *i915, bool vrr_enabled)
> +{
> + u32 max_latency = 0;
> + u32 clear = 0, val = 0;
> + u32 added_wake_time = 0;
> +
> + if (DISPLAY_VER(i915) < 20)
> + return;
> +
> + if (vrr_enabled) {
> + max_latency = LNL_PKG_C_LATENCY_MASK;
> + added_wake_time = 0;
> + } else {
> + max_latency = skl_watermark_max_latency(i915, 1);
> + if (max_latency == 0)
> + max_latency = LNL_PKG_C_LATENCY_MASK;
> + added_wake_time = DSB_EXE_TIME +
> + i915->display.sagv.block_time_us;
> + }
> +
> + clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
> + val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency);
> + val |= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time);
> +
> + intel_uncore_rmw(>uncore, LNL_PKG_C_LATENCY, clear, val);
> +}
> +
> static int
> skl_compute_wm(struct intel_atomic_state *state)
> {
> struct intel_crtc *crtc;
> struct intel_crtc_state __maybe_unused *new_crtc_state;
> int ret, i;
> + bool vrr_enabled = false;
>
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> ret = skl_build_pipe_wm(state, crtc);
> @@ -2934,8 +2979,13 @@ skl_compute_wm(struct intel_atomic_state *state)
> ret = skl_wm_add_affected_planes(state, crtc);
> if (ret)
> return ret;
> +
> + if (new_crtc_state->vrr.enable)
> +
[PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point
We need that in order to force disable SAGV in next patch.
Also it is beneficial to separate that code, as in majority cases,
when SAGV is enabled, we don't even need those calculations.
Also we probably need to determine max PSF GV point as well, however
currently we don't do that when we disable SAGV, which might be
actually causing some issues in that case.
v2: - Introduce helper adl_qgv_bw(counterpart to adl_psf_bw)
(Ville Syrjälä)
- Don't restrict psf gv points for SAGV disable case
(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 81 -
1 file changed, 53 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 77886cc21211..7baa1c13eccd 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -652,15 +652,31 @@ static unsigned int tgl_max_bw_index(struct
drm_i915_private *dev_priv,
return 0;
}
-static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
+static unsigned int adl_psf_bw(struct drm_i915_private *i915,
int psf_gv_point)
{
const struct intel_bw_info *bi =
- _priv->display.bw.max[0];
+ >display.bw.max[0];
return bi->psf_bw[psf_gv_point];
}
+static unsigned int adl_qgv_bw(struct drm_i915_private *i915,
+ int qgv_point, int num_active_planes)
+{
+ unsigned int idx;
+
+ if (DISPLAY_VER(i915) > 11)
+ idx = tgl_max_bw_index(i915, num_active_planes, qgv_point);
+ else
+ idx = icl_max_bw_index(i915, num_active_planes, qgv_point);
+
+ if (idx >= ARRAY_SIZE(i915->display.bw.max))
+ return 0;
+
+ return i915->display.bw.max[idx].deratedbw[qgv_point];
+}
+
void intel_bw_init_hw(struct drm_i915_private *dev_priv)
{
if (!HAS_DISPLAY(dev_priv))
@@ -806,6 +822,36 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
return to_intel_bw_state(bw_state);
}
+static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915,
+int num_active_planes)
+{
+ unsigned int max_bw_point = 0;
+ unsigned int max_bw = 0;
+ unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
+ int i;
+
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int max_data_rate;
+
+ max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
+
+ /*
+* We need to know which qgv point gives us
+* maximum bandwidth in order to disable SAGV
+* if we find that we exceed SAGV block time
+* with watermarks. By that moment we already
+* have those, as it is calculated earlier in
+* intel_atomic_check,
+*/
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ }
+
+ return max_bw_point;
+}
+
static int mtl_find_qgv_points(struct drm_i915_private *i915,
unsigned int data_rate,
unsigned int num_active_planes,
@@ -883,8 +929,6 @@ static int icl_find_qgv_points(struct drm_i915_private
*i915,
const struct intel_bw_state *old_bw_state,
struct intel_bw_state *new_bw_state)
{
- unsigned int max_bw_point = 0;
- unsigned int max_bw = 0;
unsigned int num_psf_gv_points =
i915->display.bw.max[0].num_psf_gv_points;
unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
u16 psf_points = 0;
@@ -897,31 +941,10 @@ static int icl_find_qgv_points(struct drm_i915_private
*i915,
return ret;
for (i = 0; i < num_qgv_points; i++) {
- unsigned int idx;
unsigned int max_data_rate;
- if (DISPLAY_VER(i915) >= 12)
- idx = tgl_max_bw_index(i915, num_active_planes, i);
- else
- idx = icl_max_bw_index(i915, num_active_planes, i);
-
- if (idx >= ARRAY_SIZE(i915->display.bw.max))
- continue;
-
- max_data_rate = i915->display.bw.max[idx].deratedbw[i];
+ max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
- /*
-* We need to know which qgv point gives us
-* maximum bandwidth in order to disable SAGV
-* if we find that we exceed SAGV block time
-* with watermarks. By that moment we already
-* have those, as it is calculated earlier in
-* intel_atomic_check,
-*/
- if (max_data_rate
[PATCH 3/3] drm/i915: Disable SAGV on bw init, to force QGV point recalculation
Problem is that on some platforms, we do get QGV point mask in wrong
state on boot. However driver assumes it is set to 0
(i.e all points allowed), however in reality we might get them all restricted,
causing issues.
Lets disable SAGV initially to force proper QGV point state.
If more QGV points are available, driver will recalculate and update
those then after next commit.
v2: - Added trace to see which QGV/PSF GV point is used when SAGV is
disabled.
v3: - Move force disable function to intel_bw_init in order to initialize
bw state as well, so that hw/sw are immediately in sync after init.
v4: - Don't try sending PCode request, seems like it is not possible at
intel_bw_init, however assigning bw->state to be restricted as if
SAGV is off, still forces driveer to send PCode request anyway on
next modeset, so the solution still works.
However we still need to address the case, when no display is connected,
which anyway requires much more changes.
v5: - Put PCode request back and apply temporary hack to make the
request succeed(in case if there 2 PSF GV points with same BW, PCode
accepts only if both points are restricted/unrestricted same time)
- Fix argument sequence for adl_qgv_bw(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 63 +++--
1 file changed, 59 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 7baa1c13eccd..d9f34dc66a83 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -162,7 +162,7 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private
*dev_priv,
1);
if (ret < 0) {
- drm_err(_priv->drm, "Failed to disable qgv points (%d)
points: 0x%x\n", ret, points_mask);
+ drm_err(_priv->drm, "Failed to disable qgv points (%x)
points: 0x%x\n", ret, points_mask);
return ret;
}
@@ -662,7 +662,7 @@ static unsigned int adl_psf_bw(struct drm_i915_private
*i915,
}
static unsigned int adl_qgv_bw(struct drm_i915_private *i915,
- int qgv_point, int num_active_planes)
+ int num_active_planes, int qgv_point)
{
unsigned int idx;
@@ -833,7 +833,7 @@ static unsigned int icl_max_bw_qgv_point(struct
drm_i915_private *i915,
for (i = 0; i < num_qgv_points; i++) {
unsigned int max_data_rate;
- max_data_rate = adl_qgv_bw(i915, i, num_active_planes);
+ max_data_rate = adl_qgv_bw(i915, num_active_planes, i);
/*
* We need to know which qgv point gives us
@@ -852,6 +852,58 @@ static unsigned int icl_max_bw_qgv_point(struct
drm_i915_private *i915,
return max_bw_point;
}
+/*
+ * Due to some strange reason, we have to use a mask of PSF GV
+ * points, instead of finding the one which provides the highest bandwidth,
+ * this is because PCode rejects the request, if 2 PSF GV points, which have
+ * same bandwidth are not set/cleared same time.
+ */
+static unsigned int icl_max_bw_psf_gv_point_mask(struct drm_i915_private *i915)
+{
+ unsigned int num_psf_gv_points =
i915->display.bw.max[0].num_psf_gv_points;
+ unsigned int max_bw = 0;
+ unsigned int max_bw_point_mask = 0;
+ int i;
+
+ for (i = 0; i < num_psf_gv_points; i++) {
+ unsigned int max_data_rate = adl_psf_bw(i915, i);
+
+ if (max_data_rate > max_bw) {
+ max_bw_point_mask = BIT(i);
+ max_bw = max_data_rate;
+ } else if (max_data_rate == max_bw)
+ max_bw_point_mask |= BIT(i);
+ }
+
+ return max_bw_point_mask;
+}
+
+static void icl_force_disable_sagv(struct drm_i915_private *i915, struct
intel_bw_state *bw_state)
+{
+ unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, 0);
+ unsigned int max_bw_psf_gv_point_mask =
icl_max_bw_psf_gv_point_mask(i915);
+ unsigned int qgv_points;
+ unsigned int psf_points;
+ int ret;
+
+ qgv_points = BIT(max_bw_qgv_point);
+ psf_points = max_bw_psf_gv_point_mask;
+
+ bw_state->qgv_points_mask = ~(ICL_PCODE_REQ_QGV_PT(qgv_points)|
+ ADLS_PCODE_REQ_PSF_PT(psf_points)) &
+ icl_qgv_points_mask(i915);
+
+ drm_dbg_kms(>drm, "Forcing SAGV disable: mask %x\n",
bw_state->qgv_points_mask);
+
+ ret = icl_pcode_restrict_qgv_points(i915, bw_state->qgv_points_mask);
+
+ if (ret)
+ drm_dbg_kms(>drm, "Restricting GV points failed: %x\n",
ret);
+ else
+ drm_dbg_kms(>drm, "Restricting GV points succeeded\n");
+
+}
+
static int mtl_find_qgv_points(struct drm_i915_private *i915,
[PATCH 1/3] drm/i915: Add meaningful traces for QGV point info error handling
For debug purposes we need those - error path won't flood the log,
however there has been already numerous cases, when due to lack
of debugs, we couldn't immediately tell what was the problem on
customer machine, which slowed down the investigation, requiring
to get access to target device and adding those traces manually.
v2: - Make the debug more generic and move it to intel_dram_detect
(Gustavo Sousa)
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 +++-
drivers/gpu/drm/i915/soc/intel_dram.c | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 7f2a50b4f494..77886cc21211 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -290,8 +290,10 @@ static int icl_get_qgv_points(struct drm_i915_private
*dev_priv,
struct intel_qgv_point *sp = >points[i];
ret = intel_read_qgv_point_info(dev_priv, sp, i);
- if (ret)
+ if (ret) {
+ drm_dbg_kms(_priv->drm, "Could not read QGV %d
info\n", i);
return ret;
+ }
drm_dbg_kms(_priv->drm,
"QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d
tRC=%d\n",
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index 15492b69f698..e957be5bfb35 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -681,6 +681,8 @@ void intel_dram_detect(struct drm_i915_private *i915)
if (ret)
return;
+ drm_dbg_kms(>drm, "Num qgv points %d\n",
dram_info->num_qgv_points);
+
drm_dbg_kms(>drm, "DRAM channels: %u\n", dram_info->num_channels);
drm_dbg_kms(>drm, "Watermark level 0 adjustment needed: %s\n",
--
2.37.3
[PATCH 0/3] QGV/SAGV related fixes
We have couple of customer issues, related to SAGV/QGV point calculation. Those patches contain fixes plus some additional debugs for those issues. Stanislav Lisovskiy (3): drm/i915: Add meaningful traces for QGV point info error handling drm/i915: Extract code required to calculate max qgv/psf gv point drm/i915: Disable SAGV on bw init, to force QGV point recalculation drivers/gpu/drm/i915/display/intel_bw.c | 142 +++- drivers/gpu/drm/i915/soc/intel_dram.c | 2 + 2 files changed, 114 insertions(+), 30 deletions(-) -- 2.37.3
[bug report] drm/i915: switch from drm_debug_printer() to device specific drm_dbg_printer()
Hello Jani Nikula,
This is a semi-automatic email about new static checker warnings.
drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:102 show_heartbeat()
warn: variable dereferenced before check 'rq' (see line 99)
drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
98 {
99 struct drm_printer p = drm_dbg_printer(>i915->drm,
DRM_UT_DRIVER,
^^
The patch adds an unchecked dereference
100 "heartbeat");
101
102 if (!rq) {
^^^
Previously we assumed "rq" could be NULL.
103 intel_engine_dump(engine, ,
104"%s heartbeat not ticking\n",
regards,
dan carpenter
Re: [PATCH 06/10] drm/i915/spi: spi register with mtd
Hi Alexander, alexander.usys...@intel.com wrote on Wed, 14 Feb 2024 12:16:00 +: > Hi Miquel > > Intel Gfx in infinite wisdom decided to create another driver - Xe and > the spi driver part of this series should be moved to some common location. > Should it be drivers/mtd or drivers/spi, or some other place? It probably depends on the framework they decided to register into. I'm sorry but I interacted in this thread more than 3 months ago, I no longer remember most of the details. If this is a driver for a spi controller (even a limited one) then it should be drivers/spi/ I guess. Thanks, Miquèl
✓ Fi.CI.IGT: success for drm/i915/scaler: Update Pipe src size check for DISPLAY_VER >= 12
== Series Details == Series: drm/i915/scaler: Update Pipe src size check for DISPLAY_VER >= 12 URL : https://patchwork.freedesktop.org/series/130061/ State : success == Summary == CI Bug Log - changes from CI_DRM_14288_full -> Patchwork_130061v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (8 -> 8) -- Additional (1): shard-glk-0 Missing(1): pig-kbl-iris New tests - New tests have been introduced between CI_DRM_14288_full and Patchwork_130061v1_full: ### New IGT tests (19) ### * igt@kms_cursor_edge_walk@256x256-left-edge@pipe-a-hdmi-a-3: - Statuses : 1 pass(s) - Exec time: [3.31] s * igt@kms_cursor_edge_walk@256x256-left-edge@pipe-d-hdmi-a-3: - Statuses : 1 pass(s) - Exec time: [3.20] s * igt@kms_cursor_edge_walk@256x256-right-edge@pipe-a-hdmi-a-3: - Statuses : 1 pass(s) - Exec time: [3.32] s * igt@kms_cursor_edge_walk@256x256-right-edge@pipe-d-hdmi-a-3: - Statuses : 1 pass(s) - Exec time: [3.20] s * igt@kms_cursor_edge_walk@64x64-right-edge@pipe-a-hdmi-a-3: - Statuses : 1 pass(s) - Exec time: [3.30] s * igt@kms_cursor_edge_walk@64x64-right-edge@pipe-d-hdmi-a-3: - Statuses : 1 pass(s) - Exec time: [3.20] s * igt@kms_flip@basic-flip-vs-dpms@d-hdmi-a3: - Statuses : 1 pass(s) - Exec time: [0.69] s * igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a3: - Statuses : 1 pass(s) - Exec time: [16.54] s * igt@kms_flip@flip-vs-wf_vblank-interruptible@d-hdmi-a3: - Statuses : 1 pass(s) - Exec time: [0.93] s * igt@kms_flip@modeset-vs-vblank-race-interruptible@d-hdmi-a3: - Statuses : 1 pass(s) - Exec time: [2.95] s * igt@kms_flip@plain-flip-fb-recreate-interruptible@d-hdmi-a3: - Statuses : 1 pass(s) - Exec time: [7.93] s * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a-hdmi-a-4: - Statuses : 1 skip(s) - Exec time: [0.01] s * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-4: - Statuses : 1 skip(s) - Exec time: [0.02] s * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-c-hdmi-a-4: - Statuses : 1 skip(s) - Exec time: [0.02] s * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-4: - Statuses : 1 skip(s) - Exec time: [0.02] s * igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-a-hdmi-a-2: - Statuses : 1 pass(s) - Exec time: [0.15] s * igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-hdmi-a-2: - Statuses : 1 pass(s) - Exec time: [0.12] s * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-a-hdmi-a-2: - Statuses : 1 pass(s) - Exec time: [0.14] s * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20@pipe-b-hdmi-a-2: - Statuses : 1 pass(s) - Exec time: [0.11] s Known issues Here are the changes found in Patchwork_130061v1_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-snb: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [FAIL][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#8293]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14288/shard-snb1/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14288/shard-snb1/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14288/shard-snb1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14288/shard-snb1/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14288/shard-snb1/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14288/shard-snb2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14288/shard-snb2/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14288/shard-snb2/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14288/shard-snb2/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14288/shard-snb4/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14288/shard-snb4/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14288/shard-snb4/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14288/shard-snb4/boot.html [14]:
