Re: [PATCH v2 1/6] drm/ci: uprev mesa version
Hi Dmitry,
On 23/05/24 15:29, Dmitry Baryshkov wrote:
On Thu, 23 May 2024 at 09:07, Vignesh Raman wrote:
Hi Dmitry,
On 20/05/24 16:13, Dmitry Baryshkov wrote:
On Fri, May 17, 2024 at 02:54:57PM +0530, Vignesh Raman wrote:
zlib.net is not allowing tarball download anymore and results
in below error in kernel+rootfs_arm32 container build,
urllib.error.HTTPError: HTTP Error 403: Forbidden
urllib.error.HTTPError: HTTP Error 415: Unsupported Media Type
Uprev mesa to latest version which includes a fix for this issue.
https://gitlab.freedesktop.org/mesa/mesa/-/commit/908f444e
Use id_tokens for JWT authentication. Since s3 bucket is migrated to
mesa-rootfs, update the variables accordingly. Also copy helper scripts
to install, so that the ci jobs can use these scripts for logging.
Signed-off-by: Vignesh Raman
---
v2:
- Uprev to recent version and use id_tokens for JWT authentication
---
drivers/gpu/drm/ci/build-igt.sh | 2 +-
drivers/gpu/drm/ci/build.sh | 6 +++--
drivers/gpu/drm/ci/container.yml | 12 +++--
drivers/gpu/drm/ci/gitlab-ci.yml | 44 +--
drivers/gpu/drm/ci/image-tags.yml | 2 +-
drivers/gpu/drm/ci/lava-submit.sh | 4 +--
drivers/gpu/drm/ci/test.yml | 2 ++
7 files changed, 44 insertions(+), 28 deletions(-)
[skipped]
diff --git a/drivers/gpu/drm/ci/test.yml b/drivers/gpu/drm/ci/test.yml
index 8bc63912fddb..612c9ede3507 100644
--- a/drivers/gpu/drm/ci/test.yml
+++ b/drivers/gpu/drm/ci/test.yml
@@ -150,6 +150,8 @@ msm:sdm845:
BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/cheza-kernel
GPU_VERSION: sdm845
RUNNER_TAG: google-freedreno-cheza
+DEVICE_TYPE: sdm845-cheza-r3
+FARM: google
I see that this is the only user of the FARM: tag. Is it correct?
No, we need to add FARM variable for other jobs as well.
Why? Even if we have to, we don't have them now and the change doesn't
seem to be related to the uprev'ing of mesa. So this probably should
go to a separate commit.
I will move them to separate commit.
Regards,
Vignesh
Also we miss DEVICE_TYPE for several other boards. Should we be adding
them?
Yes, device type needs to be added for msm:apq8016, msm:apq8096, virtio_gpu.
I will add this. Thanks.
I'd guess, separate commit too.
Regards,
Vignesh
script:
- ./install/bare-metal/cros-servo.sh
--
2.40.1
Re: [PATCH v2 01/17] drm/i915/psr: Store pr_dpcd in intel_dp
On Fri, 2024-05-24 at 05:55 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Tuesday, May 21, 2024 2:17 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh ; Kahola, Mika
> > ; Hogander, Jouni
> > Subject: [PATCH v2 01/17] drm/i915/psr: Store pr_dpcd in intel_dp
> >
> > We need pr_dpcd contents for early transport validity check on eDP
> > Panel
> > Replay and in debugfs interface to dump out panel early transport
> > capability.
> >
> > Signed-off-by: Jouni Högander
> > ---
> > .../drm/i915/display/intel_display_types.h | 1 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 19 ++-
> >
> > 2 files changed, 7 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 9678c2b157f6..6fbfe8a18f45 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1743,6 +1743,7 @@ struct intel_dp {
> > bool use_max_params;
> > u8 dpcd[DP_RECEIVER_CAP_SIZE];
> > u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> > + u8 pr_dpcd;
> > u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> > u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> > u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index d18baeb971bb..ba92f71b82d9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -559,20 +559,10 @@ static void
> > intel_dp_get_su_granularity(struct
> > intel_dp *intel_dp) static void _panel_replay_init_dpcd(struct
> > intel_dp
> > *intel_dp) {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > - u8 pr_dpcd = 0;
> > -
> > - intel_dp->psr.sink_panel_replay_support = false;
> > - drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> > &pr_dpcd);
> > -
> > - if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
> > - drm_dbg_kms(&i915->drm,
> > - "Panel replay is not supported by
> > panel\n");
>
> Panel Replat not supported print are we removing purposefully or
> missed somehow in refactoring?
I removed it purposefully. We do not have that for PSR either. I don't
see that as a reasonable to printout what features panel is not
supporting. Having debug printout saying if it's supported is enough to
my opinion. Do you agree or do you want to keep it?
BR,
Jouni Högander
>
> Regards,
> Animesh
> > - return;
> > - }
> >
> > intel_dp->psr.sink_panel_replay_support = true;
> >
> > - if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> > + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> > intel_dp->psr.sink_panel_replay_su_support = true;
> >
> > drm_dbg_kms(&i915->drm,
> > @@ -630,10 +620,13 @@ static void _psr_init_dpcd(struct intel_dp
> > *intel_dp)
> >
> > void intel_psr_init_dpcd(struct intel_dp *intel_dp) {
> > - _panel_replay_init_dpcd(intel_dp);
> > -
> > drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp-
> > > psr_dpcd,
> > sizeof(intel_dp->psr_dpcd));
> > + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> > + &intel_dp->pr_dpcd);
> > +
> > + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT)
> > + _panel_replay_init_dpcd(intel_dp);
> >
> > if (intel_dp->psr_dpcd[0])
> > _psr_init_dpcd(intel_dp);
> > --
> > 2.34.1
>
RE: [PATCH v2 04/17] drm/i915/psr: Move printing PSR mode to own function
> -Original Message-
> From: Hogander, Jouni
> Sent: Tuesday, May 21, 2024 2:17 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v2 04/17] drm/i915/psr: Move printing PSR mode to own
> function
>
> intel_psr_status has grown and is about to grow even. Let's split it a bit
> and move printing PSR mode to an own function.
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 26
> 1 file changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2ae5cdca5786..de0ce5f3a32c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3605,13 +3605,28 @@ static void intel_psr_sink_capability(struct
> intel_dp *intel_dp,
> str_yes_no(psr->sink_panel_replay_su_support));
> }
>
> +static void intel_psr_psr_mode(struct intel_dp *intel_dp,
> +struct seq_file *m)
psr kerword repeating twice, how about intel_psr_print_mode()?
Regards,
Animesh
> +{
> + struct intel_psr *psr = &intel_dp->psr;
> + const char *status;
> +
> + if (psr->panel_replay_enabled)
> + status = psr->sel_update_enabled ? "Panel Replay Selective
> Update Enabled" :
> + "Panel Replay Enabled";
> + else if (psr->enabled)
> + status = psr->sel_update_enabled ? "PSR2" : "PSR1";
> + else
> + status = "disabled";
> + seq_printf(m, "PSR mode: %s\n", status);
> +}
> +
> static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> struct intel_psr *psr = &intel_dp->psr;
> intel_wakeref_t wakeref;
> - const char *status;
> bool enabled;
> u32 val;
>
> @@ -3623,14 +3638,7 @@ static int intel_psr_status(struct seq_file *m,
> struct intel_dp *intel_dp)
> wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> mutex_lock(&psr->lock);
>
> - if (psr->panel_replay_enabled)
> - status = psr->sel_update_enabled ? "Panel Replay Selective
> Update Enabled" :
> - "Panel Replay Enabled";
> - else if (psr->enabled)
> - status = psr->sel_update_enabled ? "PSR2" : "PSR1";
> - else
> - status = "disabled";
> - seq_printf(m, "PSR mode: %s\n", status);
> + intel_psr_psr_mode(intel_dp, m);
>
> if (!psr->enabled) {
> seq_printf(m, "PSR sink not reliable: %s\n",
> --
> 2.34.1
RE: [PATCH v2 01/17] drm/i915/psr: Store pr_dpcd in intel_dp
> -Original Message-
> From: Hogander, Jouni
> Sent: Tuesday, May 21, 2024 2:17 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v2 01/17] drm/i915/psr: Store pr_dpcd in intel_dp
>
> We need pr_dpcd contents for early transport validity check on eDP Panel
> Replay and in debugfs interface to dump out panel early transport capability.
>
> Signed-off-by: Jouni Högander
> ---
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 19 ++-
> 2 files changed, 7 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9678c2b157f6..6fbfe8a18f45 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1743,6 +1743,7 @@ struct intel_dp {
> bool use_max_params;
> u8 dpcd[DP_RECEIVER_CAP_SIZE];
> u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> + u8 pr_dpcd;
> u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index d18baeb971bb..ba92f71b82d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -559,20 +559,10 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp) static void _panel_replay_init_dpcd(struct intel_dp
> *intel_dp) {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - u8 pr_dpcd = 0;
> -
> - intel_dp->psr.sink_panel_replay_support = false;
> - drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> &pr_dpcd);
> -
> - if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
> - drm_dbg_kms(&i915->drm,
> - "Panel replay is not supported by panel\n");
Panel Replat not supported print are we removing purposefully or missed somehow
in refactoring?
Regards,
Animesh
> - return;
> - }
>
> intel_dp->psr.sink_panel_replay_support = true;
>
> - if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> intel_dp->psr.sink_panel_replay_su_support = true;
>
> drm_dbg_kms(&i915->drm,
> @@ -630,10 +620,13 @@ static void _psr_init_dpcd(struct intel_dp
> *intel_dp)
>
> void intel_psr_init_dpcd(struct intel_dp *intel_dp) {
> - _panel_replay_init_dpcd(intel_dp);
> -
> drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp-
> >psr_dpcd,
>sizeof(intel_dp->psr_dpcd));
> + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> + &intel_dp->pr_dpcd);
> +
> + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT)
> + _panel_replay_init_dpcd(intel_dp);
>
> if (intel_dp->psr_dpcd[0])
> _psr_init_dpcd(intel_dp);
> --
> 2.34.1
RE: [PATCH v2 00/17] Panel Replay eDP support
> -Original Message- > From: Hogander, Jouni > Sent: Tuesday, May 21, 2024 2:17 PM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh ; Kahola, Mika > ; Hogander, Jouni > Subject: [PATCH v2 00/17] Panel Replay eDP support > > This patch set is implementing eDP1.5 Panel Replay for Intel hw. Also Region > Early Transport information is added into debugfs interface and patch to > disable Region Early Transport by default is reverted as it is needed by eDP > Panel Replay. > > v2: > - printout "Selective Update enabled (Early Transport)" instead of > "Selective Update Early Transport enabled" > - ensure that fastset is performed when the disable bit changes > > Jouni Högander (17): > drm/i915/psr: Store pr_dpcd in intel_dp > drm/panel replay: Add edp1.5 Panel Replay bits and register > drm/i915/psr: Move printing sink PSR support to own function > drm/i915/psr: Move printing PSR mode to own function > drm/i915/psr: modify psr status debugfs to support eDP Panel Replay > drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid > drm/i915/psr: Add Early Transport into psr debugfs interface > drm/display: Add missing aux less alpm wake related bits > drm/i915/psr: Check panel ALPM capability for eDP Panel Replay > drm/i915/psr: Inform Panel Replay source support on eDP as well > drm/i915/psr: enable sink for eDP1.5 Panel Replay > drm/i915/psr: Check panel Early Transport capability for eDP PR > drm/i915/psr: Perfrom psr2 checks related to ALPM for Panel Replay > drm/i915/psr: Check Early Transport for Panel Replay as well > drm/i915/psr: Modify dg2_activate_panel_replay to support eDP > drm/i915/psr: Add new debug bit to disable Panel Replay > Revert "drm/i915/psr: Disable early transport by default" Some restrictions we may have to add for before enabling eDP Panel Replay. 1. With HDCP enable cannot enable panel replay. 2. With 8b/10b encoding only panel replay can be supported, not for 128b/132b encoding. Regards, Animesh > > .../drm/i915/display/intel_display_types.h| 2 + > drivers/gpu/drm/i915/display/intel_psr.c | 294 -- > include/drm/display/drm_dp.h | 19 +- > 3 files changed, 213 insertions(+), 102 deletions(-) > > -- > 2.34.1
✓ Fi.CI.BAT: success for drm/i915: Increase FLR timeout from 3s to 9s
== Series Details == Series: drm/i915: Increase FLR timeout from 3s to 9s URL : https://patchwork.freedesktop.org/series/133994/ State : success == Summary == CI Bug Log - changes from CI_DRM_14813 -> Patchwork_133994v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133994v1/index.html Participating hosts (43 -> 41) -- Additional (1): fi-elk-e7500 Missing(3): bat-dg2-11 bat-mtlp-9 fi-snb-2520m Known issues Here are the changes found in Patchwork_133994v1 that come from known issues: ### IGT changes ### Issues hit * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-1: - fi-elk-e7500: NOTRUN -> [SKIP][1] +24 other tests skip [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133994v1/fi-elk-e7500/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-a-hdmi-a-1.html Possible fixes * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-8: [FAIL][2] ([i915#10378]) -> [PASS][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14813/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133994v1/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [ABORT][4] ([i915#10594]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14813/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133994v1/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378 [i915#10594]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10594 Build changes - * Linux: CI_DRM_14813 -> Patchwork_133994v1 CI-20190529: 20190529 CI_DRM_14813: 1385623a20ad940dab90bfaa4bc01fe599506e09 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7870: ad1cea5f9b4ce0f4a036cbda2da3d8979fb1ce15 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_133994v1: 1385623a20ad940dab90bfaa4bc01fe599506e09 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133994v1/index.html
[PATCH v2] drm/i915: Increase FLR timeout from 3s to 9s
Following the guidelines it takes 3 seconds to perform an FLR
reset. Let's give it a bit more slack because this time can
change depending on the platform and on the firmware
Signed-off-by: Andi Shyti
---
Hi,
In this second version I removed patch 2 that was ignoring the
FLR reset timeouts, until we develop a proper patch.
This first patch is basically the same as v1. Thanks Nirmoy for
your review.
Andi
drivers/gpu/drm/i915/intel_uncore.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 729409a4bada..2eba289d88ad 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2614,11 +2614,18 @@ void intel_uncore_prune_engine_fw_domains(struct
intel_uncore *uncore,
static void driver_initiated_flr(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore->i915;
- const unsigned int flr_timeout_ms = 3000; /* specs recommend a 3s wait
*/
+ unsigned int flr_timeout_ms;
int ret;
drm_dbg(&i915->drm, "Triggering Driver-FLR\n");
+ /*
+* The specification recommends a 3 seconds FLR reset timeout. To be
+* cautious, we will extend this to 9 seconds, three times the specified
+* timeout.
+*/
+ flr_timeout_ms = 9000;
+
/*
* Make sure any pending FLR requests have cleared by waiting for the
* FLR trigger bit to go to zero. Also clear GU_DEBUG's DRIVERFLR_STATUS
--
2.45.1
Re: [PATCH] drm/i915: 2 GiB of relocations ought to be enough for anybody*
On Tue, May 21, 2024 at 11:12:01AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Kernel test robot reports i915 can hit a warn in kvmalloc_node which has
> a purpose of dissalowing crazy size kernel allocations. This was added in
> 7661809d493b ("mm: don't allow oversized kvmalloc() calls"):
>
>/* Don't even allow crazy sizes */
>if (WARN_ON_ONCE(size > INT_MAX))
>return NULL;
>
> This would be kind of okay since i915 at one point dropped the need for
> making a shadow copy of the relocation list, but then it got re-added in
> fd1500fcd442 ("Revert "drm/i915/gem: Drop relocation slowpath".") a year
> after Linus added the above warning.
>
> It is plausible that the issue was not seen until now because to trigger
> gem_exec_reloc test requires a combination of an relatively older
> generation hardware but with at least 8GiB of RAM installed. Probably even
> more depending on runtime checks.
>
> Lets cap what we allow userspace to pass in using the matching limit.
> There should be no issue for real userspace since we are talking about
> "crazy" number of relocations which have no practical purpose.
>
> *) Well IGT tests might get upset but they can be easily adjusted.
>
> Signed-off-by: Tvrtko Ursulin
Thanks for fixing this!
Reviewed-by: Kees Cook
--
Kees Cook
Re: [PATCH v2] drm/i915/mtl: Update workaround 14018778641
On Fri, May 24, 2024 at 12:31:26AM +0200, Andi Shyti wrote: > Hi Angus, > > On Mon, May 13, 2024 at 02:19:17PM +, Chen, Angus wrote: > > The WA should be extended to cover VDBOX engine. We found that > > 28-channels 1080p VP9 encoding may hit this issue. > > > > Signed-off-by: Chen, Angus > > --- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index d1ab560fcdfc..da0a481a375e 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -1586,6 +1586,9 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, > > struct i915_wa_list *wal) > > */ > > wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); > > > > + /* Wa_14018778641 */ I realize that the comment farther up in the code is wrong, but there's no such workaround as "Wa_14018778641." 14018778641 is just an internal database ID that isn't meaningful for tracking workarounds in code. Workarounds are always identified by their "lineage" number, which is the number that will identify the workaround in a consistent manner across multiple platforms. In this case it sounds like the expected workaround number was actually Wa_14018575942. > > + wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); > > Wa_14018778641 says that we need to disable the FTLB for Compute, > Render, GSC, VDBox and VEBox engines, but here we are doing it > only for GSC and VDBox, why? Wa_14018575942 (which is a follow-up to an older Wa_18018781329), was originally supposed to apply to all engines. But after some investigation, the hardware teams decided that it was _probably_ only needed on the CCS engines so they suggested dropping the workaround from other engine types to reclaim performance unless we started seeing functional issues when doing so. At some point someone did report some functional issues with the RCS engine, so the workaround got restored there. Based on this patch, it sounds like the media team is now reporting that they also see functional failures on the VD engines without the workaround, so it also needs to be restored there now. > > Besides, in MTL we have the media GT where the MOD_CTRL family > has address 0x38cf34. Should this be checked and included, as > well? The gt pointer passed into xelpmp_gt_workarounds_init() is always the media GT. And the GSI offset of 0x38 gets added into the register offset automatically so you don't need to worry about doing so manually. Matt > > Thanks, > Andi > > > /* Wa_22016670082 */ > > wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE); > > > > -- > > 2.34.1 -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
✓ Fi.CI.BAT: success for drm/i915/display: Expand runtime_pm protection to atomic commit work
== Series Details ==
Series: drm/i915/display: Expand runtime_pm protection to atomic commit work
URL : https://patchwork.freedesktop.org/series/133991/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14813 -> Patchwork_133991v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133991v1/index.html
Participating hosts (43 -> 35)
--
Additional (1): fi-kbl-8809g
Missing(9): bat-kbl-2 fi-tgl-1115g4 fi-snb-2520m fi-glk-j4005
fi-cfl-8109u bat-jsl-3 bat-dg2-11 bat-jsl-1 bat-mtlp-6
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_133991v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@read-crc-frame-sequence:
- {bat-apl-1}:NOTRUN -> [FAIL][1] +13 other tests fail
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133991v1/bat-apl-1/igt@kms_pipe_crc_ba...@read-crc-frame-sequence.html
* igt@kms_pm_backlight@basic-brightness:
- {bat-apl-1}:[SKIP][2] -> [FAIL][3] +17 other tests fail
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14813/bat-apl-1/igt@kms_pm_backli...@basic-brightness.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133991v1/bat-apl-1/igt@kms_pm_backli...@basic-brightness.html
* igt@vgem_basic@second-client:
- {bat-apl-1}:[PASS][4] -> [FAIL][5] +79 other tests fail
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14813/bat-apl-1/igt@vgem_ba...@second-client.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133991v1/bat-apl-1/igt@vgem_ba...@second-client.html
Known issues
Here are the changes found in Patchwork_133991v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][6] ([i915#2190])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133991v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-8809g: NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133991v1/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-8809g: NOTRUN -> [SKIP][8] +30 other tests skip
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133991v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-load-detect.html
Possible fixes
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-8: [FAIL][9] ([i915#10378]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14813/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133991v1/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [ABORT][11] ([i915#10594]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14813/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133991v1/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@kms_flip@basic-flip-vs-modeset@d-dp7:
- {bat-mtlp-9}: [FAIL][13] ([i915#6121]) -> [PASS][14] +4 other tests
pass
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14813/bat-mtlp-9/igt@kms_flip@basic-flip-vs-mode...@d-dp7.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133991v1/bat-mtlp-9/igt@kms_flip@basic-flip-vs-mode...@d-dp7.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-a-dp-6:
- {bat-mtlp-9}: [DMESG-FAIL][15] ([i915#11009]) -> [PASS][16] +1
other test pass
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14813/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-a-dp-6.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133991v1/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-a-dp-6.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10594]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10594
[i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#6121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6121
Build changes
-
* Linux: CI_DRM_14813 -> Patchwork_133991v1
CI-20190529: 20190529
CI
✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Expand runtime_pm protection to atomic commit work
== Series Details == Series: drm/i915/display: Expand runtime_pm protection to atomic commit work URL : https://patchwork.freedesktop.org/series/133991/ State : warning == Summary == Error: dim checkpatch failed 1305d1256d13 drm/i915/display: Expand runtime_pm protection to atomic commit work -:16: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?) #16: <4> [274.905391] drm_atomic_helper_cleanup_planes+0x49/0x70 [drm_kms_helper] total: 0 errors, 1 warnings, 0 checks, 31 lines checked
Re: [PATCH v2] drm/i915/mtl: Update workaround 14018778641
Hi Angus, On Mon, May 13, 2024 at 02:19:17PM +, Chen, Angus wrote: > The WA should be extended to cover VDBOX engine. We found that > 28-channels 1080p VP9 encoding may hit this issue. > > Signed-off-by: Chen, Angus > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index d1ab560fcdfc..da0a481a375e 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1586,6 +1586,9 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct > i915_wa_list *wal) >*/ > wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); > > + /* Wa_14018778641 */ > + wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); Wa_14018778641 says that we need to disable the FTLB for Compute, Render, GSC, VDBox and VEBox engines, but here we are doing it only for GSC and VDBox, why? Besides, in MTL we have the media GT where the MOD_CTRL family has address 0x38cf34. Should this be checked and included, as well? Thanks, Andi > /* Wa_22016670082 */ > wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE); > > -- > 2.34.1
[PATCH] drm/i915/display: Expand runtime_pm protection to atomic commit work
Xe memory management relies on outer bound callers of runtime PM
protection and it will warn us when some is missing:
<4> [274.904535] xe :00:02.0: Missing outer runtime PM protection
<4> [274.905051] ? xe_pm_runtime_get_noresume+0x48/0x60 [xe]
<4> [274.905118] xe_ggtt_remove_node+0x28/0x90 [xe]
<4> [274.905164] __xe_unpin_fb_vma+0x91/0x120 [xe]
<4> [274.905234] intel_plane_unpin_fb+0x19/0x30 [xe]
<4> [274.905306] intel_cleanup_plane_fb+0x3d/0x50 [xe]
<4> [274.905391] drm_atomic_helper_cleanup_planes+0x49/0x70 [drm_kms_helper]
<4> [274.905407] intel_atomic_cleanup_work+0x69/0xd0 [xe]
The atomic commit helpers in i915 display are already protected.
However, they return the wakeref right before scheduling the thread
work items, what can lead to unprotected memory accesses.
Hence, expand the protections to the work items.
An alternative way would be to keep the state->wakeref, returning
them only at the workers. But this could lead in unbalanced scenarios
if workers gets canceled. So, the preference was to keep it simple
and get a new reference inside the thread.
Cc: Matthew Auld
Cc: Francois Dugast
Cc: Imre Deak
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1e8e2fd52cf6..03a0abc589fd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7172,14 +7172,19 @@ static void intel_atomic_cleanup_work(struct
work_struct *work)
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *old_crtc_state;
struct intel_crtc *crtc;
+ intel_wakeref_t wakeref;
int i;
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+
for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
intel_color_cleanup_commit(old_crtc_state);
drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
drm_atomic_helper_commit_cleanup_done(&state->base);
drm_atomic_state_put(&state->base);
+
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
}
static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state
*state)
@@ -7453,8 +7458,12 @@ static void intel_atomic_commit_work(struct work_struct
*work)
{
struct intel_atomic_state *state =
container_of(work, struct intel_atomic_state, base.commit_work);
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ intel_wakeref_t wakeref;
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
intel_atomic_commit_tail(state);
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
}
static void intel_atomic_track_fbs(struct intel_atomic_state *state)
--
2.45.1
✓ Fi.CI.BAT: success for drm/i915: intel_color_check() cleanup
== Series Details ==
Series: drm/i915: intel_color_check() cleanup
URL : https://patchwork.freedesktop.org/series/133985/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14813 -> Patchwork_133985v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133985v1/index.html
Participating hosts (43 -> 42)
--
Additional (1): fi-kbl-8809g
Missing(2): bat-jsl-1 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_133985v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][1] ([i915#2190])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133985v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133985v1/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_module_load@load:
- bat-arls-3: [PASS][3] -> [ABORT][4] ([i915#11041])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14813/bat-arls-3/igt@i915_module_l...@load.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133985v1/bat-arls-3/igt@i915_module_l...@load.html
* igt@kms_dsc@dsc-basic:
- fi-kbl-8809g: NOTRUN -> [SKIP][5] +30 other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133985v1/fi-kbl-8809g/igt@kms_...@dsc-basic.html
Possible fixes
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-8: [FAIL][6] ([i915#10378]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14813/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133985v1/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [ABORT][8] ([i915#10594]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14813/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133985v1/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@kms_flip@basic-flip-vs-modeset@c-dp6:
- {bat-mtlp-9}: [DMESG-FAIL][10] ([i915#11009]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14813/bat-mtlp-9/igt@kms_flip@basic-flip-vs-mode...@c-dp6.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133985v1/bat-mtlp-9/igt@kms_flip@basic-flip-vs-mode...@c-dp6.html
* igt@kms_flip@basic-flip-vs-modeset@d-dp6:
- {bat-mtlp-9}: [FAIL][12] ([i915#6121]) -> [PASS][13] +4 other tests
pass
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14813/bat-mtlp-9/igt@kms_flip@basic-flip-vs-mode...@d-dp6.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133985v1/bat-mtlp-9/igt@kms_flip@basic-flip-vs-mode...@d-dp6.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10594]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10594
[i915#10979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10979
[i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
[i915#11041]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11041
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#6121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6121
Build changes
-
* Linux: CI_DRM_14813 -> Patchwork_133985v1
CI-20190529: 20190529
CI_DRM_14813: 1385623a20ad940dab90bfaa4bc01fe599506e09 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7870: ad1cea5f9b4ce0f4a036cbda2da3d8979fb1ce15 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133985v1: 1385623a20ad940dab90bfaa4bc01fe599506e09 @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133985v1/index.html
✗ Fi.CI.SPARSE: warning for drm/i915: intel_color_check() cleanup
== Series Details == Series: drm/i915: intel_color_check() cleanup URL : https://patchwork.freedesktop.org/series/133985/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +drivers/gpu/drm/i915/display/intel_de.h:105:15: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/display/intel_display_types.h:2064:16: warning: tr
Re: [PATCH 05/10] drm/i915/display: add platform descriptors
On Wed, May 22, 2024 at 08:33:42PM +0300, Jani Nikula wrote:
> We'll need to start identifying the platforms independently in display
> code in order to break free from the i915 and xe IS_()
> macros. This is fairly straightforward, as we already identify most
> platforms by PCI ID in display probe anyway.
>
> As the first step, add platform descriptors with pointers to display
> info. We'll have more platforms than display info, so minimize
> duplication:
>
> - Add separate skl/kbl/cfl/cml descriptors while they share the display
> info.
>
> - Add separate jsl/ehl descriptors while they share the display info.
>
> Identify ADL-P (and derivatives) and DG2 descriptors by their names even
> though their display info is Xe LPD or HPD.
>
> Signed-off-by: Jani Nikula
> ---
> .../drm/i915/display/intel_display_device.c | 558 ++
> 1 file changed, 326 insertions(+), 232 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 56b27546d1b3..d1e03437abb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -20,6 +20,10 @@
> __diag_push();
> __diag_ignore_all("-Woverride-init", "Allow field initialization overrides
> for display info");
>
> +struct platform_desc {
> + const struct intel_display_device_info *info;
> +};
I had to jump to the latest patch to understand why this single item
in a new struct... later it makes sense...
> +
> static const struct intel_display_device_info no_display = {};
>
> #define PIPE_A_OFFSET0x7
> @@ -200,33 +204,41 @@ static const struct intel_display_device_info
> no_display = {};
> .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
> .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
>
> -static const struct intel_display_device_info i830_display = {
> - I830_DISPLAY,
> +static const struct platform_desc i830_desc = {
> + .info = &(const struct intel_display_device_info) {
> + I830_DISPLAY,
>
> - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
> BIT(PORT_C), /* DVO A/B/C */
> + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
> BIT(PORT_C), /* DVO A/B/C */
> + },
> };
>
> -static const struct intel_display_device_info i845_display = {
> - I845_DISPLAY,
> +static const struct platform_desc i845_desc = {
> + .info = &(const struct intel_display_device_info) {
> + I845_DISPLAY,
>
> - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
> + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /*
> DVO B/C */
> + },
> };
>
> -static const struct intel_display_device_info i85x_display = {
> - I830_DISPLAY,
> +static const struct platform_desc i85x_desc = {
> + .info = &(const struct intel_display_device_info) {
> + I830_DISPLAY,
>
> - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /*
> DVO B/C */
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> + },
> };
>
> -static const struct intel_display_device_info i865g_display = {
> - I845_DISPLAY,
> +static const struct platform_desc i865g_desc = {
> + .info = &(const struct intel_display_device_info) {
> + I845_DISPLAY,
>
> - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
> - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /*
> DVO B/C */
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> + },
> };
>
> -#define GEN3_DISPLAY \
> +#define GEN3_DISPLAY \
I had noticed a trend in all of your recent series, to replace the long tab
or space before '\' with a single space. But then here you change the single
space to multiple spaces. Intentional?
> .has_gmch = 1, \
> .has_overlay = 1, \
> I9XX_PIPE_OFFSETS, \
> @@ -238,52 +250,64 @@ static const struct intel_display_device_info
> i865g_display = {
> BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
>
> -static const struct intel_display_device_info i915g_display = {
> - GEN3_DISPLAY,
> - I845_COLORS,
> - .cursor_needs_physical = 1,
> - .overlay_needs_physical = 1,
> +static const struct platform_desc i915g_desc = {
> + .info = &(const struct intel_display_device_info) {
> + GEN3_DISPLAY,
> + I845_COLORS,
> + .cursor_needs_physical = 1,
> + .overlay_needs_physical = 1,
> + },
> };
>
> -static const struct intel_display_device_info i915gm_display = {
> - GEN3_DISPLAY,
> -
[PULL] drm-misc-fixes
Hi Dave, Sima, here's the weekly PR for drm-misc-fixes. There's one important patch included, which fixes a kernel panic that can be triggered from userspace. Best regards Thomas drm-misc-fixes-2024-05-23: Short summary of fixes pull: buddy: - stop using PAGE_SIZE shmem-helper: - avoid kernel panic in mmap() tests: - buddy: fix PAGE_SIZE dependency The following changes since commit 6897204ea3df808d342c8e4613135728bc538bcd: drm/connector: Add \n to message about demoting connector force-probes (2024-05-07 09:17:07 -0700) are available in the Git repository at: https://gitlab.freedesktop.org/drm/misc/kernel.git tags/drm-misc-fixes-2024-05-23 for you to fetch changes up to 39bc27bd688066a63e56f7f64ad34fae03fbe3b8: drm/shmem-helper: Fix BUG_ON() on mmap(PROT_WRITE, MAP_PRIVATE) (2024-05-21 14:38:51 +0200) Short summary of fixes pull: buddy: - stop using PAGE_SIZE shmem-helper: - avoid kernel panic in mmap() tests: - buddy: fix PAGE_SIZE dependency Matthew Auld (2): drm/buddy: stop using PAGE_SIZE drm/tests/buddy: stop using PAGE_SIZE Mohamed Ahmed (1): drm/nouveau: use tile_mode and pte_kind for VM_BIND bo allocations Wachowski, Karol (1): drm/shmem-helper: Fix BUG_ON() on mmap(PROT_WRITE, MAP_PRIVATE) drivers/gpu/drm/drm_buddy.c | 2 +- drivers/gpu/drm/drm_gem_shmem_helper.c | 3 +++ drivers/gpu/drm/nouveau/nouveau_abi16.c | 3 +++ drivers/gpu/drm/nouveau/nouveau_bo.c| 44 ++--- drivers/gpu/drm/tests/drm_buddy_test.c | 42 +++ include/drm/drm_buddy.h | 6 ++--- include/uapi/drm/nouveau_drm.h | 7 ++ 7 files changed, 57 insertions(+), 50 deletions(-) -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Frankenstrasse 146, 90461 Nuernberg, Germany GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman HRB 36809 (AG Nuernberg)
Re: [PATCH 07/10] drm/i915/display: change display probe to identify GMD ID based platforms
On Wed, May 22, 2024 at 08:33:44PM +0300, Jani Nikula wrote:
> We'll need to identify all platforms, including the ones that have
> display defined by GMD ID. Add MTL and LNL. Their display info will
> still be probed via GMD ID.
Reviewed-by: Rodrigo Vivi
>
> Signed-off-by: Jani Nikula
> ---
> .../drm/i915/display/intel_display_device.c | 44 +++
> 1 file changed, 26 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index d1e03437abb3..416853ed50df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -21,7 +21,7 @@ __diag_push();
> __diag_ignore_all("-Woverride-init", "Allow field initialization overrides
> for display info");
>
> struct platform_desc {
> - const struct intel_display_device_info *info;
> + const struct intel_display_device_info *info; /* NULL for GMD ID */
> };
>
> static const struct intel_display_device_info no_display = {};
> @@ -871,6 +871,17 @@ static const struct intel_display_device_info
> xe2_hpd_display = {
> BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
> };
>
> +/*
> + * Do not initialize the .info member of the platform desc for GMD ID based
> + * platforms. Their display will be probed automatically based on the IP
> version
> + * reported by the hardware.
> + */
> +static const struct platform_desc mtl_desc = {
> +};
> +
> +static const struct platform_desc lnl_desc = {
> +};
> +
> __diag_pop();
>
> /*
> @@ -937,12 +948,8 @@ static const struct {
> INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc),
> INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc),
> INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &dg2_desc),
> -
> - /*
> - * Do not add any GMD_ID-based platforms to this list. They will
> - * be probed automatically based on the IP version reported by
> - * the hardware.
> - */
> + INTEL_MTL_IDS(INTEL_DISPLAY_DEVICE, &mtl_desc),
> + INTEL_LNL_IDS(INTEL_DISPLAY_DEVICE, &lnl_desc),
> };
>
> static const struct {
> @@ -995,20 +1002,15 @@ probe_gmdid_display(struct drm_i915_private *i915,
> struct intel_display_ip_ver *
> return NULL;
> }
>
> -static const struct intel_display_device_info *
> -probe_display(struct drm_i915_private *i915)
> +static const struct platform_desc *find_platform_desc(struct pci_dev *pdev)
> {
> - struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> int i;
>
> for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
> if (intel_display_ids[i].devid == pdev->device)
> - return intel_display_ids[i].desc->info;
> + return intel_display_ids[i].desc;
> }
>
> - drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling
> display.\n",
> - pdev->device);
> -
> return NULL;
> }
>
> @@ -1017,6 +1019,7 @@ void intel_display_device_probe(struct drm_i915_private
> *i915)
> struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> const struct intel_display_device_info *info;
> struct intel_display_ip_ver ip_ver = {};
> + const struct platform_desc *desc;
>
> /* Add drm device backpointer as early as possible. */
> i915->display.drm = &i915->drm;
> @@ -1028,12 +1031,17 @@ void intel_display_device_probe(struct
> drm_i915_private *i915)
> goto no_display;
> }
>
> - if (HAS_GMD_ID(i915))
> - info = probe_gmdid_display(i915, &ip_ver);
> - else
> - info = probe_display(i915);
> + desc = find_platform_desc(pdev);
> + if (!desc) {
> + drm_dbg_kms(&i915->drm, "Unknown device ID %04x; disabling
> display.\n",
> + pdev->device);
> + goto no_display;
> + }
>
> + info = desc->info;
> if (!info)
> + info = probe_gmdid_display(i915, &ip_ver);
> +if (!info)
> goto no_display;
>
> DISPLAY_INFO(i915) = info;
> --
> 2.39.2
>
Re: [PATCH 08/10] drm/i915/display: identify platforms with enum and name
On Wed, May 22, 2024 at 08:33:45PM +0300, Jani Nikula wrote:
> Add enum intel_display_platform and add that and name to all platform
> descriptors.
Reviewed-by: Rodrigo Vivi
>
> Signed-off-by: Jani Nikula
> ---
> .../drm/i915/display/intel_display_device.c | 48 +++
> .../drm/i915/display/intel_display_device.h | 58 +++
> 2 files changed, 106 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 416853ed50df..7c5cead1fe15 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -21,9 +21,15 @@ __diag_push();
> __diag_ignore_all("-Woverride-init", "Allow field initialization overrides
> for display info");
>
> struct platform_desc {
> + enum intel_display_platform platform;
> + const char *name;
> const struct intel_display_device_info *info; /* NULL for GMD ID */
> };
>
> +#define PLATFORM(_platform) \
> + .platform = (INTEL_DISPLAY_##_platform), \
> + .name = #_platform
> +
> static const struct intel_display_device_info no_display = {};
>
> #define PIPE_A_OFFSET0x7
> @@ -205,6 +211,7 @@ static const struct intel_display_device_info no_display
> = {};
> .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
>
> static const struct platform_desc i830_desc = {
> + PLATFORM(I830),
> .info = &(const struct intel_display_device_info) {
> I830_DISPLAY,
>
> @@ -213,6 +220,7 @@ static const struct platform_desc i830_desc = {
> };
>
> static const struct platform_desc i845_desc = {
> + PLATFORM(I845G),
> .info = &(const struct intel_display_device_info) {
> I845_DISPLAY,
>
> @@ -221,6 +229,7 @@ static const struct platform_desc i845_desc = {
> };
>
> static const struct platform_desc i85x_desc = {
> + PLATFORM(I85X),
> .info = &(const struct intel_display_device_info) {
> I830_DISPLAY,
>
> @@ -230,6 +239,7 @@ static const struct platform_desc i85x_desc = {
> };
>
> static const struct platform_desc i865g_desc = {
> + PLATFORM(I865G),
> .info = &(const struct intel_display_device_info) {
> I845_DISPLAY,
>
> @@ -251,6 +261,7 @@ static const struct platform_desc i865g_desc = {
> .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
>
> static const struct platform_desc i915g_desc = {
> + PLATFORM(I915G),
> .info = &(const struct intel_display_device_info) {
> GEN3_DISPLAY,
> I845_COLORS,
> @@ -260,6 +271,7 @@ static const struct platform_desc i915g_desc = {
> };
>
> static const struct platform_desc i915gm_desc = {
> + PLATFORM(I915GM),
> .info = &(const struct intel_display_device_info) {
> GEN3_DISPLAY,
> I9XX_COLORS,
> @@ -272,6 +284,7 @@ static const struct platform_desc i915gm_desc = {
> };
>
> static const struct platform_desc i945g_desc = {
> + PLATFORM(I945G),
> .info = &(const struct intel_display_device_info) {
> GEN3_DISPLAY,
> I845_COLORS,
> @@ -282,6 +295,7 @@ static const struct platform_desc i945g_desc = {
> };
>
> static const struct platform_desc i945gm_desc = {
> + PLATFORM(I915GM),
> .info = &(const struct intel_display_device_info) {
> GEN3_DISPLAY,
> I9XX_COLORS,
> @@ -295,6 +309,7 @@ static const struct platform_desc i945gm_desc = {
> };
>
> static const struct platform_desc g33_desc = {
> + PLATFORM(G33),
> .info = &(const struct intel_display_device_info) {
> GEN3_DISPLAY,
> I845_COLORS,
> @@ -303,6 +318,7 @@ static const struct platform_desc g33_desc = {
> };
>
> static const struct platform_desc pnv_desc = {
> + PLATFORM(PINEVIEW),
> .info = &(const struct intel_display_device_info) {
> GEN3_DISPLAY,
> I9XX_COLORS,
> @@ -323,6 +339,7 @@ static const struct platform_desc pnv_desc = {
> BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
>
> static const struct platform_desc i965g_desc = {
> + PLATFORM(I965G),
> .info = &(const struct intel_display_device_info) {
> GEN4_DISPLAY,
> .has_overlay = 1,
> @@ -332,6 +349,7 @@ static const struct platform_desc i965g_desc = {
> };
>
> static const struct platform_desc i965gm_desc = {
> + PLATFORM(I965GM),
> .info = &(const struct intel_display_device_info) {
> GEN4_DISPLAY,
> .has_overlay = 1,
> @@ -343,6 +361,7 @@ static const struct platform_desc i965gm_desc = {
> };
>
> static const struct platform_desc g45_desc = {
> + PLATFORM(G45),
> .info = &(const struct intel_display_device_info) {
> GEN4_DISPLAY,
>
> @@ -351,6 +370,7 @@ static const struct platform_desc
Re: [PATCH 09/10] drm/i915/display: add support for subplatforms
On Wed, May 22, 2024 at 08:33:46PM +0300, Jani Nikula wrote:
> Add support for subplatforms. This is similar to what the xe driver is
> doing. The subplatform is an enum and it's exclusive, i.e. only one
> subplatform can match, and it completely identifies the platform and
> subplatform. This is different from i915 core, and is notable in the
> handling of ULT/ULX and RPL/RPL-U.
Only used to print information in the next patch?
But I guess other future use in mind as well?
anyway it is a good organization by itself.
Reviewed-by: Rodrigo Vivi
>
> Signed-off-by: Jani Nikula
> ---
> .../drm/i915/display/intel_display_device.c | 204 ++
> .../drm/i915/display/intel_display_device.h | 26 +++
> 2 files changed, 230 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 7c5cead1fe15..59b8ca174ef8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -20,9 +20,16 @@
> __diag_push();
> __diag_ignore_all("-Woverride-init", "Allow field initialization overrides
> for display info");
>
> +struct subplatform_desc {
> + enum intel_display_subplatform subplatform;
> + const char *name;
> + const u16 *pciidlist;
> +};
> +
> struct platform_desc {
> enum intel_display_platform platform;
> const char *name;
> + const struct subplatform_desc *subplatforms;
> const struct intel_display_device_info *info; /* NULL for GMD ID */
> };
>
> @@ -30,6 +37,8 @@ struct platform_desc {
> .platform = (INTEL_DISPLAY_##_platform), \
> .name = #_platform
>
> +#define ID(id) (id)
> +
> static const struct intel_display_device_info no_display = {};
>
> #define PIPE_A_OFFSET0x7
> @@ -460,8 +469,26 @@ static const struct platform_desc vlv_desc = {
> },
> };
>
> +static const u16 hsw_ult_ids[] = {
> + INTEL_HSW_ULT_GT1_IDS(ID),
> + INTEL_HSW_ULT_GT2_IDS(ID),
> + INTEL_HSW_ULT_GT3_IDS(ID),
> + 0
> +};
> +
> +static const u16 hsw_ulx_ids[] = {
> + INTEL_HSW_ULX_GT1_IDS(ID),
> + INTEL_HSW_ULX_GT2_IDS(ID),
> + 0
> +};
> +
> static const struct platform_desc hsw_desc = {
> PLATFORM(HASWELL),
> + .subplatforms = (const struct subplatform_desc[]) {
> + { INTEL_DISPLAY_HASWELL_ULT, "ULT", hsw_ult_ids },
> + { INTEL_DISPLAY_HASWELL_ULX, "ULX", hsw_ulx_ids },
> + {},
> + },
> .info = &(const struct intel_display_device_info) {
> .has_ddi = 1,
> .has_dp_mst = 1,
> @@ -483,8 +510,29 @@ static const struct platform_desc hsw_desc = {
> },
> };
>
> +static const u16 bdw_ult_ids[] = {
> + INTEL_BDW_ULT_GT1_IDS(ID),
> + INTEL_BDW_ULT_GT2_IDS(ID),
> + INTEL_BDW_ULT_GT3_IDS(ID),
> + INTEL_BDW_ULT_RSVD_IDS(ID),
> + 0
> +};
> +
> +static const u16 bdw_ulx_ids[] = {
> + INTEL_BDW_ULX_GT1_IDS(ID),
> + INTEL_BDW_ULX_GT2_IDS(ID),
> + INTEL_BDW_ULX_GT3_IDS(ID),
> + INTEL_BDW_ULX_RSVD_IDS(ID),
> + 0
> +};
> +
> static const struct platform_desc bdw_desc = {
> PLATFORM(BROADWELL),
> + .subplatforms = (const struct subplatform_desc[]) {
> + { INTEL_DISPLAY_BROADWELL_ULT, "ULT", bdw_ult_ids },
> + { INTEL_DISPLAY_BROADWELL_ULX, "ULX", bdw_ulx_ids },
> + {},
> + },
> .info = &(const struct intel_display_device_info) {
> .has_ddi = 1,
> .has_dp_mst = 1,
> @@ -549,23 +597,89 @@ static const struct intel_display_device_info
> skl_display = {
> .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
> };
>
> +static const u16 skl_ult_ids[] = {
> + INTEL_SKL_ULT_GT1_IDS(ID),
> + INTEL_SKL_ULT_GT2_IDS(ID),
> + INTEL_SKL_ULT_GT3_IDS(ID),
> + 0
> +};
> +
> +static const u16 skl_ulx_ids[] = {
> + INTEL_SKL_ULX_GT1_IDS(ID),
> + INTEL_SKL_ULX_GT2_IDS(ID),
> + 0
> +};
> +
> static const struct platform_desc skl_desc = {
> PLATFORM(SKYLAKE),
> + .subplatforms = (const struct subplatform_desc[]) {
> + { INTEL_DISPLAY_SKYLAKE_ULT, "ULT", skl_ult_ids },
> + { INTEL_DISPLAY_SKYLAKE_ULX, "ULX", skl_ulx_ids },
> + {},
> + },
> .info = &skl_display,
> };
>
> +static const u16 kbl_ult_ids[] = {
> + INTEL_KBL_ULT_GT1_IDS(ID),
> + INTEL_KBL_ULT_GT2_IDS(ID),
> + INTEL_KBL_ULT_GT3_IDS(ID),
> + 0
> +};
> +
> +static const u16 kbl_ulx_ids[] = {
> + INTEL_KBL_ULX_GT1_IDS(ID),
> + INTEL_KBL_ULX_GT2_IDS(ID),
> + INTEL_AML_KBL_GT2_IDS(ID),
> + 0
> +};
> +
> static const struct platform_desc kbl_desc = {
> PLATFORM(KABYLAKE),
> + .subplatforms = (const struct subplatform_desc[]) {
> + { INTEL_DISPLAY_KABYLAKE_ULT, "ULT", kbl_ult_ids },
> + { INTEL_DISPLAY_KABYLAKE_ULX, "ULX", kbl_ulx_ids },
> + {},
> + },
Re: [PATCH 10/10] drm/i915/display: add probe message
On Wed, May 22, 2024 at 08:33:47PM +0300, Jani Nikula wrote: > Add an info message about which display device was probed. Reviewed-by: Rodrigo Vivi > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_display_device.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c > b/drivers/gpu/drm/i915/display/intel_display_device.c > index 59b8ca174ef8..5b6dfb5032e7 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.c > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c > @@ -1305,6 +1305,11 @@ void intel_display_device_probe(struct > drm_i915_private *i915) > if (ip_ver.ver || ip_ver.rel || ip_ver.step) > DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; > > + drm_info(&i915->drm, "Found %s%s%s (device ID %04x) display version > %u.%02u\n", > + desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "", > + pdev->device, DISPLAY_RUNTIME_INFO(i915)->ip.ver, > + DISPLAY_RUNTIME_INFO(i915)->ip.rel); > + > return; > > no_display: > -- > 2.39.2 >
Re: [PATCH 06/10] drm/i915: add LNL PCI IDs
On Wed, May 22, 2024 at 08:33:43PM +0300, Jani Nikula wrote: > Although not supported by i915 core, the display code needs to know the > LNL PCI IDs. perhaps we should add a comment in the header near the IDs? > > Long term, xe and i915 should probably share the file defining PCI IDs. although it might get harder to distinguish the intersection, this might be a good idea indeed. Reviewed-by: Rodrigo Vivi > > Signed-off-by: Jani Nikula > --- > include/drm/i915_pciids.h | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > index 3e39d644ebaa..7ae7ee11ef38 100644 > --- a/include/drm/i915_pciids.h > +++ b/include/drm/i915_pciids.h > @@ -783,4 +783,10 @@ > MACRO__(0x7DD1, ## __VA_ARGS__), \ > MACRO__(0x7DD5, ## __VA_ARGS__) > > +/* LNL */ > +#define INTEL_LNL_IDS(MACRO__, ...) \ > + MACRO__(0x6420, ## __VA_ARGS__), \ > + MACRO__(0x64A0, ## __VA_ARGS__), \ > + MACRO__(0x64B0, ## __VA_ARGS__) > + > #endif /* _I915_PCIIDS_H */ > -- > 2.39.2 >
[PATCH 3/3] drm/i915: Bury c8_planes_changed() in intel_color_check()
From: Ville Syrjälä
The c8_planes_changed() check in the high level atomic code is
a bit of an eyesore. Push it inside intel_color_check() so the
high level code doesn't have to care about this stuff.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 11 ++-
drivers/gpu/drm/i915/display/intel_display.c | 18 --
2 files changed, 10 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index a2ddce100fcc..a9d526ab107a 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1986,9 +1986,18 @@ int intel_color_check(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
- const struct intel_crtc_state *new_crtc_state =
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ /*
+* May need to update pipe gamma enable bits
+* when C8 planes are getting enabled/disabled.
+*/
+ if (!old_crtc_state->c8_planes != !new_crtc_state->c8_planes)
+ new_crtc_state->uapi.color_mgmt_changed = true;
+
if (!intel_crtc_needs_color_update(new_crtc_state))
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 84f46370c88d..c3f142495d0b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4138,17 +4138,6 @@ static int icl_check_nv12_planes(struct intel_crtc_state
*crtc_state)
return 0;
}
-static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
- struct intel_atomic_state *state =
- to_intel_atomic_state(new_crtc_state->uapi.state);
- const struct intel_crtc_state *old_crtc_state =
- intel_atomic_get_old_crtc_state(state, crtc);
-
- return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
-}
-
static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
{
const struct drm_display_mode *pipe_mode =
@@ -4247,13 +4236,6 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
return ret;
}
- /*
-* May need to update pipe gamma enable bits
-* when C8 planes are getting enabled/disabled.
-*/
- if (c8_planes_changed(crtc_state))
- crtc_state->uapi.color_mgmt_changed = true;
-
ret = intel_color_check(state, crtc);
if (ret)
return ret;
--
2.44.1
[PATCH 2/3] drm/i915: Hide the intel_crtc_needs_color_update() inside intel_color_check()
From: Ville Syrjälä
Move the intel_crtc_needs_color_update() into intel_color_check()
so that the caller doesn't have to care about this. This will
also enable us to hide the c8_planes_changed() thing better.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 5 +
drivers/gpu/drm/i915/display/intel_display.c | 8 +++-
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index ede628b58a5c..a2ddce100fcc 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1986,6 +1986,11 @@ int intel_color_check(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (!intel_crtc_needs_color_update(new_crtc_state))
+ return 0;
return i915->display.funcs.color->color_check(state, crtc);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 3b2765b371f8..84f46370c88d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4254,11 +4254,9 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
if (c8_planes_changed(crtc_state))
crtc_state->uapi.color_mgmt_changed = true;
- if (intel_crtc_needs_color_update(crtc_state)) {
- ret = intel_color_check(state, crtc);
- if (ret)
- return ret;
- }
+ ret = intel_color_check(state, crtc);
+ if (ret)
+ return ret;
ret = intel_compute_pipe_wm(state, crtc);
if (ret) {
--
2.44.1
[PATCH 1/3] drm/i915: Plumb the entire atomic state into intel_color_check()
From: Ville Syrjälä
Bunch of stuff in intel_color_check() needs to look at both the
old and new crtc states. Currently we do that by digging the
full atomic state via the crtc_state->state pointer. That thing
is a total footgun if I ever saw one, as it's only valid during
specific parts of the atomic flow. A lot of people have been
bitten by this thing in the past when trying to use it after
it's no longer valid.
Take a small step towards elimination of the footgun by not
using it in the inte_color_check(). Instead we plumb in the
entire atomic state all the way from the top.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 111 +++
drivers/gpu/drm/i915/display/intel_color.h | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
3 files changed, 69 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 82b155708422..ede628b58a5c 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -30,7 +30,8 @@
#include "intel_dsb.h"
struct intel_color_funcs {
- int (*color_check)(struct intel_crtc_state *crtc_state);
+ int (*color_check)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
/*
* Program non-arming double buffered color management registers
* before vblank evasion. The registers should then latch after
@@ -1942,11 +1943,9 @@ bool intel_color_uses_dsb(const struct intel_crtc_state
*crtc_state)
return crtc_state->dsb;
}
-static bool intel_can_preload_luts(const struct intel_crtc_state
*new_crtc_state)
+static bool intel_can_preload_luts(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
- struct intel_atomic_state *state =
- to_intel_atomic_state(new_crtc_state->uapi.state);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
@@ -1954,11 +1953,9 @@ static bool intel_can_preload_luts(const struct
intel_crtc_state *new_crtc_state
!old_crtc_state->pre_csc_lut;
}
-static bool vlv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
+static bool vlv_can_preload_luts(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
- struct intel_atomic_state *state =
- to_intel_atomic_state(new_crtc_state->uapi.state);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
@@ -1966,13 +1963,13 @@ static bool vlv_can_preload_luts(const struct
intel_crtc_state *new_crtc_state)
!old_crtc_state->post_csc_lut;
}
-static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
+static bool chv_can_preload_luts(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
- struct intel_atomic_state *state =
- to_intel_atomic_state(new_crtc_state->uapi.state);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
/*
* CGM_PIPE_MODE is itself single buffered. We'd have to
@@ -1982,14 +1979,15 @@ static bool chv_can_preload_luts(const struct
intel_crtc_state *new_crtc_state)
if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)
return false;
- return vlv_can_preload_luts(new_crtc_state);
+ return vlv_can_preload_luts(state, crtc);
}
-int intel_color_check(struct intel_crtc_state *crtc_state)
+int intel_color_check(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
- return i915->display.funcs.color->color_check(crtc_state);
+ return i915->display.funcs.color->color_check(state, crtc);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
@@ -2039,14 +2037,14 @@ static bool need_plane_update(struct intel_plane *plane,
}
static int
-intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state)
+intel_color_add_affected_planes(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- struct intel_atomic_state *
[PATCH 0/3] drm/i915: intel_color_check() cleanup
From: Ville Syrjälä Eliminate the crtc_state->state footgun from intel_color_check(), and hide some mundane C8 plane details inside it. Ville Syrjälä (3): drm/i915: Plumb the entire atomic state into intel_color_check() drm/i915: Hide the intel_crtc_needs_color_update() inside intel_color_check() drm/i915: Bury c8_planes_changed() in intel_color_check() drivers/gpu/drm/i915/display/intel_color.c | 125 --- drivers/gpu/drm/i915/display/intel_color.h | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 26 +--- 3 files changed, 85 insertions(+), 70 deletions(-) -- 2.44.1
Re: [PATCH v2 14/21] drm/i915/dp: Disable link retraining after the last fallback step
On Thu, May 23, 2024 at 06:28:12PM +0300, Ville Syrjälä wrote:
> On Mon, May 20, 2024 at 09:58:12PM +0300, Imre Deak wrote:
> > After a link training failure if the link parameters can't be further
> > reduced, there is no point in trying to retrain the link in the driver.
> > This avoids excessive retrain attempts after detecting a bad link, for
> > instance while handling MST HPD IRQs, which is likely redundant as the
> > link training failed already twice with the same minimum link
> > parameters. Userspace can still try to retrain the link with these
> > parameters via a modeset.
> >
> > While at it make the error message more accurate and emit instead a
> > debug message if the link training failure was only forced for testing
> > purposes.
> >
> > Signed-off-by: Imre Deak
> > ---
> > .../drm/i915/display/intel_display_types.h| 1 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 4
> > .../drm/i915/display/intel_dp_link_training.c | 22 +--
> > 3 files changed, 20 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index bde518c843468..eb0cac3e27acf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1765,6 +1765,7 @@ struct intel_dp {
> > int max_lane_count;
> > /* Max rate for the current link */
> > int max_rate;
> > + bool retrain_disabled;
> > /* Sequential link training failures after a passing LT */
> > int seq_train_failures;
> > } link;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index b72dbd7becb74..34d64fe3302ef 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2950,6 +2950,7 @@ static void intel_dp_reset_link_params(struct
> > intel_dp *intel_dp)
> > {
> > intel_dp->link.max_lane_count =
> > intel_dp_max_common_lane_count(intel_dp);
> > intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
> > + intel_dp->link.retrain_disabled = false;
> > intel_dp->link.seq_train_failures = 0;
> > }
> >
> > @@ -5061,6 +5062,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
> > intel_dp->lane_count))
> > return false;
> >
> > + if (intel_dp->link.retrain_disabled)
> > + return false;
> > +
> > if (intel_dp->link.seq_train_failures)
> > return true;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index 97d499e4b6ef7..375f59afd4dec 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -1165,10 +1165,8 @@ static int
> > intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> > new_link_rate = intel_dp_max_common_rate(intel_dp);
> > }
> >
> > - if (new_lane_count < 0) {
> > - drm_err(&i915->drm, "Link Training Unsuccessful\n");
> > + if (new_lane_count < 0)
> > return -1;
> > - }
> >
> > if (intel_dp_is_edp(intel_dp) &&
> > !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate,
> > new_lane_count)) {
> > @@ -1187,7 +1185,7 @@ static int
> > intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> > return 0;
> > }
> >
> > -static void intel_dp_schedule_fallback_link_training(struct
> > intel_atomic_state *state,
> > +static bool intel_dp_schedule_fallback_link_training(struct
> > intel_atomic_state *state,
> > struct intel_dp *intel_dp,
> > const struct
> > intel_crtc_state *crtc_state)
> > {
> > @@ -1195,7 +1193,7 @@ static void
> > intel_dp_schedule_fallback_link_training(struct intel_atomic_state *
> >
> > if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
> > lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on
> > disconnected sink.\n");
> > - return;
> > + return true;
> > }
> >
> > if (intel_dp->hobl_active) {
> > @@ -1203,11 +1201,13 @@ static void
> > intel_dp_schedule_fallback_link_training(struct intel_atomic_state *
> >"Link Training failed with HOBL active, not enabling it
> > from now on\n");
> > intel_dp->hobl_failed = true;
> > } else if (intel_dp_get_link_train_fallback_values(intel_dp,
> > crtc_state)) {
> > - return;
> > + return false;
> > }
> >
> > /* Schedule a Hotplug Uevent to userspace to start modeset */
> > intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
> > +
> > + return true;
> > }
> >
> >
Re: [PATCH v2 19/21] drm/i915/dp: Add debugfs entry to force link training failure
On Thu, May 23, 2024 at 06:29:34PM +0300, Ville Syrjälä wrote:
> On Mon, May 20, 2024 at 09:58:17PM +0300, Imre Deak wrote:
> > Add a connector debugfs entry to force a failure during the following
> > 1-2 link training. The entry will auto-reset after the specified link
> > training events are complete.
> >
> > v2: Add the entry from intel_dp_link_training.c (Jani)
> >
> > Cc: Jani Nikula
> > Signed-off-by: Imre Deak
> > ---
> > .../drm/i915/display/intel_display_types.h| 1 +
> > .../drm/i915/display/intel_dp_link_training.c | 52 ++-
> > 2 files changed, 52 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index e1c41cece249d..dbe1468fe471d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1770,6 +1770,7 @@ struct intel_dp {
> > bool retrain_disabled;
> > /* Sequential link training failures after a passing LT */
> > int seq_train_failures;
> > + int force_train_failure;
> > } link;
> > bool reset_link_params;
> > int mso_link_count;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index 764187bc42ff9..b40148a42f442 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -1489,7 +1489,10 @@ void intel_dp_start_link_train(struct
> > intel_atomic_state *state,
> > else
> > passed = intel_dp_link_train_all_phys(intel_dp, crtc_state,
> > lttpr_count);
> >
> > - if (passed) {
> > + if (intel_dp->link.force_train_failure) {
> > + intel_dp->link.force_train_failure--;
> > + lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training
> > failure\n");
> > + } else if (passed) {
> > intel_dp->link.seq_train_failures = 0;
> > intel_ddi_queue_link_check(dig_port, 2000);
> > return;
> > @@ -1799,6 +1802,50 @@ static int i915_dp_max_lane_count_show(void *data,
> > u64 *val)
> > }
> > DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops,
> > i915_dp_max_lane_count_show, NULL, "%llu\n");
> >
> > +static int i915_dp_force_link_training_failure_show(void *data, u64 *val)
> > +{
> > + struct intel_connector *connector = to_intel_connector(data);
> > + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > + struct intel_dp *intel_dp;
> > + int err;
> > +
> > + err =
> > drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> > + if (err)
> > + return err;
> > +
> > + intel_dp = intel_connector_to_intel_dp(connector);
> > + *val = intel_dp->link.force_train_failure;
> > +
> > + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> > +
> > + return 0;
> > +}
> > +
> > +static int i915_dp_force_link_training_failure_write(void *data, u64 val)
> > +{
> > + struct intel_connector *connector = to_intel_connector(data);
> > + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > + struct intel_dp *intel_dp;
> > + int err;
> > +
> > + if (val > 2)
>
> Why 2 specifically?
There are 2 back-to-back link trainings that can fail after a modeset or
later after detecting a bad link state, the initial one and a second
with the same LT parameters. That's followed by reducing the LT
parameters and probably a modeset changing the mode.
> > + return -EINVAL;
> > +
> > + err =
> > drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> > + if (err)
> > + return err;
> > +
> > + intel_dp = intel_connector_to_intel_dp(connector);
> > + intel_dp->link.force_train_failure = val;
> > +
> > + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> > +
> > + return 0;
> > +}
> > +DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops,
> > +i915_dp_force_link_training_failure_show,
> > +i915_dp_force_link_training_failure_write, "%llu\n");
> > +
> > void intel_dp_link_training_debugfs_add(struct intel_connector *connector)
> > {
> > struct dentry *root = connector->base.debugfs_entry;
> > @@ -1818,4 +1865,7 @@ void intel_dp_link_training_debugfs_add(struct
> > intel_connector *connector)
> >
> > debugfs_create_file("i915_dp_max_lane_count", 0444, root,
> > connector, &i915_dp_max_lane_count_fops);
> > +
> > + debugfs_create_file("i915_dp_force_link_training_failure", 0644, root,
> > + connector,
> > &i915_dp_force_link_training_failure_fops);
> > }
> > --
> > 2.43.3
>
> --
> Ville Syrjälä
> Intel
Re: [PATCH v2 17/21] drm/i915/dp: Add debugfs entries to set a target link rate/lane count
On Thu, May 23, 2024 at 06:25:08PM +0300, Ville Syrjälä wrote:
> On Mon, May 20, 2024 at 09:58:15PM +0300, Imre Deak wrote:
> > Add connector debugfs entries to set a target link rate/lane count to be
> > used by a link training afterwards. After setting a target link
> > rate/lane count reset the link training parameters and for a non-auto
> > target disable reducing the link parameters via the fallback logic. The
> > former one can be used after testing link training failure scenarios
> > - via debugfs entries added later - to reset the reduced link parameters
> > after the test.
> >
> > v2:
> > - Add the entries from intel_dp_link_training.c (Jani)
> > - Rename the entries to i915_dp_set_link_rate/lane_count.
> >
> > Cc: Jani Nikula
> > Signed-off-by: Imre Deak
> > ---
> > .../drm/i915/display/intel_display_debugfs.c | 2 +
> > .../drm/i915/display/intel_display_types.h| 2 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 63 -
> > drivers/gpu/drm/i915/display/intel_dp.h | 2 +
> > .../drm/i915/display/intel_dp_link_training.c | 230 ++
> > .../drm/i915/display/intel_dp_link_training.h | 4 +
> > 6 files changed, 294 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 35f9f86ef70f4..f83ffa2534925 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -23,6 +23,7 @@
> > #include "intel_display_types.h"
> > #include "intel_dmc.h"
> > #include "intel_dp.h"
> > +#include "intel_dp_link_training.h"
> > #include "intel_dp_mst.h"
> > #include "intel_drrs.h"
> > #include "intel_fbc.h"
> > @@ -1515,6 +1516,7 @@ void intel_connector_debugfs_add(struct
> > intel_connector *connector)
> > intel_drrs_connector_debugfs_add(connector);
> > intel_pps_connector_debugfs_add(connector);
> > intel_psr_connector_debugfs_add(connector);
> > + intel_dp_link_training_debugfs_add(connector);
> >
> > if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> > connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index eb0cac3e27acf..e1c41cece249d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1765,6 +1765,8 @@ struct intel_dp {
> > int max_lane_count;
> > /* Max rate for the current link */
> > int max_rate;
> > + int requested_lane_count;
> > + int requested_rate;
>
> "requested" is perhaps a bit weak. Maybe "force" or "override"
> although perhaps those might give the impression that it ignores
> the sink limits or something?
It determines the rate/lane count within the valid common range. Can
rename it to force.
>
> > bool retrain_disabled;
> > /* Sequential link training failures after a passing LT */
> > int seq_train_failures;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index c8d940a2ef7af..cf4a768fccd15 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -345,7 +345,7 @@ int intel_dp_max_common_rate(struct intel_dp *intel_dp)
> > return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
> > }
> >
> > -static int intel_dp_max_source_lane_count(struct intel_digital_port
> > *dig_port)
> > +int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
> > {
> > int vbt_max_lanes =
> > intel_bios_dp_max_lane_count(dig_port->base.devdata);
> > int max_lanes = dig_port->max_lanes;
> > @@ -371,19 +371,39 @@ int intel_dp_max_common_lane_count(struct intel_dp
> > *intel_dp)
> > return min3(source_max, sink_max, lane_max);
> > }
> >
> > +static int requested_lane_count(struct intel_dp *intel_dp)
> > +{
> > + return clamp(intel_dp->link.requested_lane_count, 1,
> > intel_dp_max_common_lane_count(intel_dp));
> > +}
> > +
> > int intel_dp_max_lane_count(struct intel_dp *intel_dp)
> > {
> > - switch (intel_dp->link.max_lane_count) {
> > + int lane_count;
> > +
> > + if (intel_dp->link.requested_lane_count)
> > + lane_count = requested_lane_count(intel_dp);
> > + else
> > + lane_count = intel_dp->link.max_lane_count;
> > +
> > + switch (lane_count) {
> > case 1:
> > case 2:
> > case 4:
> > - return intel_dp->link.max_lane_count;
> > + return lane_count;
> > default:
> > - MISSING_CASE(intel_dp->link.max_lane_count);
> > + MISSING_CASE(lane_count);
> > return 1;
> > }
> > }
> >
> > +static int intel_dp_min_lane_count(struct intel_dp *intel_dp)
> > +{
> > + if (intel
Re: [PATCH v2 12/21] drm/i915/dp: Use check link state work in the detect handler
On Thu, May 23, 2024 at 06:43:40PM +0300, Ville Syrjälä wrote:
> On Thu, May 23, 2024 at 06:29:21PM +0300, Imre Deak wrote:
> > On Thu, May 23, 2024 at 06:08:40PM +0300, Ville Syrjälä wrote:
> > > On Mon, May 20, 2024 at 09:58:10PM +0300, Imre Deak wrote:
> > > > Simplify things by retraining a DP link if a bad link is detected in the
> > > > connector detect handler from the encoder's check link state work,
> > > > similarly to how this is done after a modeset link training failure.
> > > >
> > > > Signed-off-by: Imre Deak
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
> > > > 1 file changed, 2 insertions(+), 5 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index ff4ed6bb520d8..70b00e5ae7ad7 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -5863,11 +5863,8 @@ intel_dp_detect(struct drm_connector *connector,
> > > > * Some external monitors do not signal loss of link
> > > > synchronization
> > > > * with an IRQ_HPD, so force a link status check.
> > > > */
> > > > - if (!intel_dp_is_edp(intel_dp)) {
> > > > - ret = intel_dp_retrain_link(encoder, ctx);
> > > > - if (ret)
> > > > - return ret;
> > > > - }
> > > > + if (!intel_dp_is_edp(intel_dp))
> > > > + intel_dp_check_link_state(intel_dp);
> > >
> > > I would like to see this hack nuked entirely. But that
> > > could be a followup.
> >
> > Okay. This tries to keep the current behavior, but can add a note that
> > the above workaround can be removed after the link state is checked
> > after modesets.
> >
> > I also wondered about the link state check in the hotplug handler. If
> > that's only a way to defer doing this from the HPD IRQ handler - which
> > is now changed by patch 13 - that could be also removed eventually?
>
> Not sure which one you want to removed exactly. I presume there
> are still at least these cases we need to handle:
> - long HDP dropped and came back without any userspace
> initiated modeset in between
> -> kick off a retrain from the long HPD handler
I meant this one, but didn't think of the case where the link can be
actually retrained after a long HPD. I guess with a full modeset it
works, so should continue doing that.
> - short HPD indicated some link badness
> -> kick off a retrain from the short HDP handler
> - link dropped on its own soon after modeset without
> any HPD for some reason
> -> kick off a retrain from the post modeset link check
>
> And the one we should remove:
> - something weird happened to the link and no one noticed,
> and for some random reason userspace just happens to do
> a getconnector() which ends up randomly fixing things
Yes, this is clear.
> Did I miss anything else?
>
> --
> Ville Syrjälä
> Intel
Re: [PATCH v2 04/21] drm/i915/dp: Sanitize intel_dp_get_link_train_fallback_values()
On Wed, 22 May 2024, Ville Syrjälä wrote:
> On Mon, May 20, 2024 at 09:58:02PM +0300, Imre Deak wrote:
>> Reduce the indentation in intel_dp_get_link_train_fallback_values() by
>> adding separate helpers to reduce the link rate and lane count. Also
>> simplify things by passing crtc_state to the function.
>>
>> This also prepares for later patches in the patchset adding a limitation
>> on how the link params are reduced.
>>
>> Signed-off-by: Imre Deak
>> ---
>> .../drm/i915/display/intel_dp_link_training.c | 82 ---
>> 1 file changed, 51 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 4db293f256896..edc970036866a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -1109,11 +1109,37 @@ static bool
>> intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
>> return true;
>> }
>>
>> +static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate)
>> +{
>> +int rate_index;
>> +int new_rate;
>> +
>> +rate_index = intel_dp_rate_index(intel_dp->common_rates,
>> + intel_dp->num_common_rates,
>> + current_rate);
>> +
>> +if (rate_index <= 0)
>> +return -1;
>> +
>> +new_rate = intel_dp_common_rate(intel_dp, rate_index - 1);
>> +
>> +return new_rate;
>
> This is structured as
>
> if (bad)
> fail;
> success;
>
>> +}
>> +
>> +static int reduce_lane_count(struct intel_dp *intel_dp, int
>> current_lane_count)
>> +{
>> +if (current_lane_count > 1)
>> +return current_lane_count >> 1;
>> +
>> +return -1;
>
> whereas this is
>
> if (ok)
> success;
> fail;
>
> I'd rearrange one of them so the logic is the same way around in both.
Usually failures in if branches with early returns and happy day
scenario with the least indentation.
BR,
Jani.
>
> Otherwise lgtm
> Reviewed-by: Ville Syrjälä
>
>> +}
>> +
>> static int intel_dp_get_link_train_fallback_values(struct intel_dp
>> *intel_dp,
>> - int link_rate, u8 lane_count)
>> + const struct
>> intel_crtc_state *crtc_state)
>> {
>> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> -int index;
>> +int new_link_rate;
>> +int new_lane_count;
>>
>> /*
>> * TODO: Enable fallback on MST links once MST link compute can handle
>> @@ -1131,36 +1157,32 @@ static int
>> intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
>> return 0;
>> }
>>
>> -index = intel_dp_rate_index(intel_dp->common_rates,
>> -intel_dp->num_common_rates,
>> -link_rate);
>> -if (index > 0) {
>> -if (intel_dp_is_edp(intel_dp) &&
>> -!intel_dp_can_link_train_fallback_for_edp(intel_dp,
>> -
>> intel_dp_common_rate(intel_dp, index - 1),
>> - lane_count)) {
>> -drm_dbg_kms(&i915->drm,
>> -"Retrying Link training for eDP with same
>> parameters\n");
>> -return 0;
>> -}
>> -intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index
>> - 1);
>> -intel_dp->link.max_lane_count = lane_count;
>> -} else if (lane_count > 1) {
>> -if (intel_dp_is_edp(intel_dp) &&
>> -!intel_dp_can_link_train_fallback_for_edp(intel_dp,
>> -
>> intel_dp_max_common_rate(intel_dp),
>> - lane_count >> 1))
>> {
>> -drm_dbg_kms(&i915->drm,
>> -"Retrying Link training for eDP with same
>> parameters\n");
>> -return 0;
>> -}
>> -intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
>> -intel_dp->link.max_lane_count = lane_count >> 1;
>> -} else {
>> +new_lane_count = crtc_state->lane_count;
>> +new_link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock);
>> +if (new_link_rate < 0) {
>> +new_lane_count = reduce_lane_count(intel_dp,
>> crtc_state->lane_count);
>> +new_link_rate = intel_dp_max_common_rate(intel_dp);
>> +}
>> +
>> +if (new_lane_count < 0) {
>> drm_err(&i915->drm, "Link Training Unsuccessful\n");
>> return -1;
>> }
>>
>> +if (intel_dp_is_edp(intel_dp) &&
>> +!intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate,
>> new_lane_count)) {
>> +drm_dbg_kms(&i915->drm,
>> +
✓ Fi.CI.BAT: success for drm/i915/display: Add comparison for pipe config for MTL+ >
== Series Details ==
Series: drm/i915/display: Add comparison for pipe config for MTL+ >
URL : https://patchwork.freedesktop.org/series/133968/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14809 -> Patchwork_133968v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/index.html
Participating hosts (43 -> 40)
--
Additional (2): fi-glk-j4005 bat-jsl-3
Missing(5): fi-bsw-n3050 fi-snb-2520m fi-cfl-8109u bat-dg2-11 bat-arls-3
Known issues
Here are the changes found in Patchwork_133968v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-jsl-3: NOTRUN -> [SKIP][1] ([i915#9318])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- bat-jsl-3: NOTRUN -> [SKIP][2] ([i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/bat-jsl-3/igt@gem_huc_c...@huc-copy.html
- fi-glk-j4005: NOTRUN -> [SKIP][3] ([i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- bat-jsl-3: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/bat-jsl-3/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-glk-j4005: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/fi-glk-j4005/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-3: NOTRUN -> [SKIP][6] ([i915#4103]) +1 other test skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/bat-jsl-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-jsl-3: NOTRUN -> [SKIP][7] ([i915#3555] / [i915#9886])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/bat-jsl-3/igt@kms_...@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-jsl-3: NOTRUN -> [SKIP][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/bat-jsl-3/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_psr@psr-primary-page-flip:
- fi-glk-j4005: NOTRUN -> [SKIP][9] +10 other tests skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/fi-glk-j4005/igt@kms_...@psr-primary-page-flip.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-jsl-3: NOTRUN -> [SKIP][10] ([i915#3555])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/bat-jsl-3/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_module_load@load:
- bat-dg2-8: [DMESG-WARN][11] ([i915#10014]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/bat-dg2-8/igt@i915_module_l...@load.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/bat-dg2-8/igt@i915_module_l...@load.html
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-c-dp-6:
- {bat-mtlp-9}: [DMESG-FAIL][13] ([i915#11009]) -> [PASS][14] +2
other tests pass
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/bat-mtlp-9/igt@kms_pipe_crc_basic@hang-read-...@pipe-c-dp-6.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/bat-mtlp-9/igt@kms_pipe_crc_basic@hang-read-...@pipe-c-dp-6.html
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-d-dp-6:
- {bat-mtlp-9}: [FAIL][15] -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/bat-mtlp-9/igt@kms_pipe_crc_basic@hang-read-...@pipe-d-dp-6.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133968v1/bat-mtlp-9/igt@kms_pipe_crc_basic@hang-read-...@pipe-d-dp-6.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10014]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10014
[i915#10580]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10580
[i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#6121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6121
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-
Re: [PATCH v2 12/21] drm/i915/dp: Use check link state work in the detect handler
On Thu, May 23, 2024 at 06:29:21PM +0300, Imre Deak wrote:
> On Thu, May 23, 2024 at 06:08:40PM +0300, Ville Syrjälä wrote:
> > On Mon, May 20, 2024 at 09:58:10PM +0300, Imre Deak wrote:
> > > Simplify things by retraining a DP link if a bad link is detected in the
> > > connector detect handler from the encoder's check link state work,
> > > similarly to how this is done after a modeset link training failure.
> > >
> > > Signed-off-by: Imre Deak
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
> > > 1 file changed, 2 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index ff4ed6bb520d8..70b00e5ae7ad7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -5863,11 +5863,8 @@ intel_dp_detect(struct drm_connector *connector,
> > >* Some external monitors do not signal loss of link synchronization
> > >* with an IRQ_HPD, so force a link status check.
> > >*/
> > > - if (!intel_dp_is_edp(intel_dp)) {
> > > - ret = intel_dp_retrain_link(encoder, ctx);
> > > - if (ret)
> > > - return ret;
> > > - }
> > > + if (!intel_dp_is_edp(intel_dp))
> > > + intel_dp_check_link_state(intel_dp);
> >
> > I would like to see this hack nuked entirely. But that
> > could be a followup.
>
> Okay. This tries to keep the current behavior, but can add a note that
> the above workaround can be removed after the link state is checked
> after modesets.
>
> I also wondered about the link state check in the hotplug handler. If
> that's only a way to defer doing this from the HPD IRQ handler - which
> is now changed by patch 13 - that could be also removed eventually?
Not sure which one you want to removed exactly. I presume there
are still at least these cases we need to handle:
- long HDP dropped and came back without any userspace
initiated modeset in between
-> kick off a retrain from the long HPD handler
- short HPD indicated some link badness
-> kick off a retrain from the short HDP handler
- link dropped on its own soon after modeset without
any HPD for some reason
-> kick off a retrain from the post modeset link check
And the one we should remove:
- something weird happened to the link and no one noticed,
and for some random reason userspace just happens to do
a getconnector() which ends up randomly fixing things
Did I miss anything else?
--
Ville Syrjälä
Intel
✗ Fi.CI.SPARSE: warning for drm/i915/display: Add comparison for pipe config for MTL+ >
== Series Details == Series: drm/i915/display: Add comparison for pipe config for MTL+ > URL : https://patchwork.freedesktop.org/series/133968/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Add comparison for pipe config for MTL+ >
== Series Details ==
Series: drm/i915/display: Add comparison for pipe config for MTL+ >
URL : https://patchwork.freedesktop.org/series/133968/
State : warning
== Summary ==
Error: dim checkpatch failed
840f16a219ec drm/i915/display: Revert "drm/i915/display: Skip C10 state
verification in case of fastset"
7fe52b8d3995 drm/i915/display: Add compare config for MTL+ platforms
-:133: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#133: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3328:
+{
+
-:208: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible
side-effects?
#208: FILE: drivers/gpu/drm/i915/display/intel_display.c:5128:
+#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
+ if (!intel_cx0pll_compare_hw_state(¤t_config->name, \
+ &pipe_config->name)) { \
+ pipe_config_cx0pll_mismatch(&p, fastset, crtc,
__stringify(name), \
+ ¤t_config->name, \
+ &pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
-:208: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as
'(name)' to avoid precedence issues
#208: FILE: drivers/gpu/drm/i915/display/intel_display.c:5128:
+#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
+ if (!intel_cx0pll_compare_hw_state(¤t_config->name, \
+ &pipe_config->name)) { \
+ pipe_config_cx0pll_mismatch(&p, fastset, crtc,
__stringify(name), \
+ ¤t_config->name, \
+ &pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
total: 0 errors, 0 warnings, 3 checks, 195 lines checked
Re: [PATCH v2 19/21] drm/i915/dp: Add debugfs entry to force link training failure
On Mon, May 20, 2024 at 09:58:17PM +0300, Imre Deak wrote:
> Add a connector debugfs entry to force a failure during the following
> 1-2 link training. The entry will auto-reset after the specified link
> training events are complete.
>
> v2: Add the entry from intel_dp_link_training.c (Jani)
>
> Cc: Jani Nikula
> Signed-off-by: Imre Deak
> ---
> .../drm/i915/display/intel_display_types.h| 1 +
> .../drm/i915/display/intel_dp_link_training.c | 52 ++-
> 2 files changed, 52 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e1c41cece249d..dbe1468fe471d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1770,6 +1770,7 @@ struct intel_dp {
> bool retrain_disabled;
> /* Sequential link training failures after a passing LT */
> int seq_train_failures;
> + int force_train_failure;
> } link;
> bool reset_link_params;
> int mso_link_count;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 764187bc42ff9..b40148a42f442 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1489,7 +1489,10 @@ void intel_dp_start_link_train(struct
> intel_atomic_state *state,
> else
> passed = intel_dp_link_train_all_phys(intel_dp, crtc_state,
> lttpr_count);
>
> - if (passed) {
> + if (intel_dp->link.force_train_failure) {
> + intel_dp->link.force_train_failure--;
> + lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training
> failure\n");
> + } else if (passed) {
> intel_dp->link.seq_train_failures = 0;
> intel_ddi_queue_link_check(dig_port, 2000);
> return;
> @@ -1799,6 +1802,50 @@ static int i915_dp_max_lane_count_show(void *data, u64
> *val)
> }
> DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops,
> i915_dp_max_lane_count_show, NULL, "%llu\n");
>
> +static int i915_dp_force_link_training_failure_show(void *data, u64 *val)
> +{
> + struct intel_connector *connector = to_intel_connector(data);
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_dp *intel_dp;
> + int err;
> +
> + err =
> drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> + if (err)
> + return err;
> +
> + intel_dp = intel_connector_to_intel_dp(connector);
> + *val = intel_dp->link.force_train_failure;
> +
> + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> +
> + return 0;
> +}
> +
> +static int i915_dp_force_link_training_failure_write(void *data, u64 val)
> +{
> + struct intel_connector *connector = to_intel_connector(data);
> + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_dp *intel_dp;
> + int err;
> +
> + if (val > 2)
Why 2 specifically?
> + return -EINVAL;
> +
> + err =
> drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> + if (err)
> + return err;
> +
> + intel_dp = intel_connector_to_intel_dp(connector);
> + intel_dp->link.force_train_failure = val;
> +
> + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> +
> + return 0;
> +}
> +DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops,
> + i915_dp_force_link_training_failure_show,
> + i915_dp_force_link_training_failure_write, "%llu\n");
> +
> void intel_dp_link_training_debugfs_add(struct intel_connector *connector)
> {
> struct dentry *root = connector->base.debugfs_entry;
> @@ -1818,4 +1865,7 @@ void intel_dp_link_training_debugfs_add(struct
> intel_connector *connector)
>
> debugfs_create_file("i915_dp_max_lane_count", 0444, root,
> connector, &i915_dp_max_lane_count_fops);
> +
> + debugfs_create_file("i915_dp_force_link_training_failure", 0644, root,
> + connector,
> &i915_dp_force_link_training_failure_fops);
> }
> --
> 2.43.3
--
Ville Syrjälä
Intel
Re: [PATCH v2 12/21] drm/i915/dp: Use check link state work in the detect handler
On Thu, May 23, 2024 at 06:08:40PM +0300, Ville Syrjälä wrote:
> On Mon, May 20, 2024 at 09:58:10PM +0300, Imre Deak wrote:
> > Simplify things by retraining a DP link if a bad link is detected in the
> > connector detect handler from the encoder's check link state work,
> > similarly to how this is done after a modeset link training failure.
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
> > 1 file changed, 2 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index ff4ed6bb520d8..70b00e5ae7ad7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5863,11 +5863,8 @@ intel_dp_detect(struct drm_connector *connector,
> > * Some external monitors do not signal loss of link synchronization
> > * with an IRQ_HPD, so force a link status check.
> > */
> > - if (!intel_dp_is_edp(intel_dp)) {
> > - ret = intel_dp_retrain_link(encoder, ctx);
> > - if (ret)
> > - return ret;
> > - }
> > + if (!intel_dp_is_edp(intel_dp))
> > + intel_dp_check_link_state(intel_dp);
>
> I would like to see this hack nuked entirely. But that
> could be a followup.
Okay. This tries to keep the current behavior, but can add a note that
the above workaround can be removed after the link state is checked
after modesets.
I also wondered about the link state check in the hotplug handler. If
that's only a way to defer doing this from the HPD IRQ handler - which
is now changed by patch 13 - that could be also removed eventually?
>
> >
> > /*
> > * Clearing NACK and defer counts to get their exact values
> > --
> > 2.43.3
>
> --
> Ville Syrjälä
> Intel
Re: [PATCH v2 14/21] drm/i915/dp: Disable link retraining after the last fallback step
On Mon, May 20, 2024 at 09:58:12PM +0300, Imre Deak wrote:
> After a link training failure if the link parameters can't be further
> reduced, there is no point in trying to retrain the link in the driver.
> This avoids excessive retrain attempts after detecting a bad link, for
> instance while handling MST HPD IRQs, which is likely redundant as the
> link training failed already twice with the same minimum link
> parameters. Userspace can still try to retrain the link with these
> parameters via a modeset.
>
> While at it make the error message more accurate and emit instead a
> debug message if the link training failure was only forced for testing
> purposes.
>
> Signed-off-by: Imre Deak
> ---
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 4
> .../drm/i915/display/intel_dp_link_training.c | 22 +--
> 3 files changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index bde518c843468..eb0cac3e27acf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1765,6 +1765,7 @@ struct intel_dp {
> int max_lane_count;
> /* Max rate for the current link */
> int max_rate;
> + bool retrain_disabled;
> /* Sequential link training failures after a passing LT */
> int seq_train_failures;
> } link;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index b72dbd7becb74..34d64fe3302ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2950,6 +2950,7 @@ static void intel_dp_reset_link_params(struct intel_dp
> *intel_dp)
> {
> intel_dp->link.max_lane_count =
> intel_dp_max_common_lane_count(intel_dp);
> intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
> + intel_dp->link.retrain_disabled = false;
> intel_dp->link.seq_train_failures = 0;
> }
>
> @@ -5061,6 +5062,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
> intel_dp->lane_count))
> return false;
>
> + if (intel_dp->link.retrain_disabled)
> + return false;
> +
> if (intel_dp->link.seq_train_failures)
> return true;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 97d499e4b6ef7..375f59afd4dec 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1165,10 +1165,8 @@ static int
> intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> new_link_rate = intel_dp_max_common_rate(intel_dp);
> }
>
> - if (new_lane_count < 0) {
> - drm_err(&i915->drm, "Link Training Unsuccessful\n");
> + if (new_lane_count < 0)
> return -1;
> - }
>
> if (intel_dp_is_edp(intel_dp) &&
> !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate,
> new_lane_count)) {
> @@ -1187,7 +1185,7 @@ static int
> intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> return 0;
> }
>
> -static void intel_dp_schedule_fallback_link_training(struct
> intel_atomic_state *state,
> +static bool intel_dp_schedule_fallback_link_training(struct
> intel_atomic_state *state,
>struct intel_dp *intel_dp,
>const struct
> intel_crtc_state *crtc_state)
> {
> @@ -1195,7 +1193,7 @@ static void
> intel_dp_schedule_fallback_link_training(struct intel_atomic_state *
>
> if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
> lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on
> disconnected sink.\n");
> - return;
> + return true;
> }
>
> if (intel_dp->hobl_active) {
> @@ -1203,11 +1201,13 @@ static void
> intel_dp_schedule_fallback_link_training(struct intel_atomic_state *
> "Link Training failed with HOBL active, not enabling it
> from now on\n");
> intel_dp->hobl_failed = true;
> } else if (intel_dp_get_link_train_fallback_values(intel_dp,
> crtc_state)) {
> - return;
> + return false;
> }
>
> /* Schedule a Hotplug Uevent to userspace to start modeset */
> intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
> +
> + return true;
> }
>
> /* Perform the link training on all LTTPRs and the DPRX on a link. */
> @@ -1518,7 +1518,15 @@ void intel_dp_start_link_train(struct
> intel_atomic_state *state,
> return;
> }
>
> - int
Re: [PATCH v2 17/21] drm/i915/dp: Add debugfs entries to set a target link rate/lane count
On Mon, May 20, 2024 at 09:58:15PM +0300, Imre Deak wrote:
> Add connector debugfs entries to set a target link rate/lane count to be
> used by a link training afterwards. After setting a target link
> rate/lane count reset the link training parameters and for a non-auto
> target disable reducing the link parameters via the fallback logic. The
> former one can be used after testing link training failure scenarios
> - via debugfs entries added later - to reset the reduced link parameters
> after the test.
>
> v2:
> - Add the entries from intel_dp_link_training.c (Jani)
> - Rename the entries to i915_dp_set_link_rate/lane_count.
>
> Cc: Jani Nikula
> Signed-off-by: Imre Deak
> ---
> .../drm/i915/display/intel_display_debugfs.c | 2 +
> .../drm/i915/display/intel_display_types.h| 2 +
> drivers/gpu/drm/i915/display/intel_dp.c | 63 -
> drivers/gpu/drm/i915/display/intel_dp.h | 2 +
> .../drm/i915/display/intel_dp_link_training.c | 230 ++
> .../drm/i915/display/intel_dp_link_training.h | 4 +
> 6 files changed, 294 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 35f9f86ef70f4..f83ffa2534925 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -23,6 +23,7 @@
> #include "intel_display_types.h"
> #include "intel_dmc.h"
> #include "intel_dp.h"
> +#include "intel_dp_link_training.h"
> #include "intel_dp_mst.h"
> #include "intel_drrs.h"
> #include "intel_fbc.h"
> @@ -1515,6 +1516,7 @@ void intel_connector_debugfs_add(struct intel_connector
> *connector)
> intel_drrs_connector_debugfs_add(connector);
> intel_pps_connector_debugfs_add(connector);
> intel_psr_connector_debugfs_add(connector);
> + intel_dp_link_training_debugfs_add(connector);
>
> if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index eb0cac3e27acf..e1c41cece249d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1765,6 +1765,8 @@ struct intel_dp {
> int max_lane_count;
> /* Max rate for the current link */
> int max_rate;
> + int requested_lane_count;
> + int requested_rate;
"requested" is perhaps a bit weak. Maybe "force" or "override"
although perhaps those might give the impression that it ignores
the sink limits or something?
> bool retrain_disabled;
> /* Sequential link training failures after a passing LT */
> int seq_train_failures;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index c8d940a2ef7af..cf4a768fccd15 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -345,7 +345,7 @@ int intel_dp_max_common_rate(struct intel_dp *intel_dp)
> return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
> }
>
> -static int intel_dp_max_source_lane_count(struct intel_digital_port
> *dig_port)
> +int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
> {
> int vbt_max_lanes =
> intel_bios_dp_max_lane_count(dig_port->base.devdata);
> int max_lanes = dig_port->max_lanes;
> @@ -371,19 +371,39 @@ int intel_dp_max_common_lane_count(struct intel_dp
> *intel_dp)
> return min3(source_max, sink_max, lane_max);
> }
>
> +static int requested_lane_count(struct intel_dp *intel_dp)
> +{
> + return clamp(intel_dp->link.requested_lane_count, 1,
> intel_dp_max_common_lane_count(intel_dp));
> +}
> +
> int intel_dp_max_lane_count(struct intel_dp *intel_dp)
> {
> - switch (intel_dp->link.max_lane_count) {
> + int lane_count;
> +
> + if (intel_dp->link.requested_lane_count)
> + lane_count = requested_lane_count(intel_dp);
> + else
> + lane_count = intel_dp->link.max_lane_count;
> +
> + switch (lane_count) {
> case 1:
> case 2:
> case 4:
> - return intel_dp->link.max_lane_count;
> + return lane_count;
> default:
> - MISSING_CASE(intel_dp->link.max_lane_count);
> + MISSING_CASE(lane_count);
> return 1;
> }
> }
>
> +static int intel_dp_min_lane_count(struct intel_dp *intel_dp)
> +{
> + if (intel_dp->link.requested_lane_count)
> + return requested_lane_count(intel_dp);
> +
> + return 1;
> +}
> +
> /*
> * The required data bandwidth for a mode with given pixel clock and bpp.
> This
> * is the required net bandwidth independent of the data bandwidth
> efficiency.
> @@ -1306,16 +1326,38
✓ Fi.CI.BAT: success for amd, i915, xe: drop redundant warnings from driver makefiles
== Series Details ==
Series: amd, i915, xe: drop redundant warnings from driver makefiles
URL : https://patchwork.freedesktop.org/series/133965/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14809 -> Patchwork_133965v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/index.html
Participating hosts (43 -> 39)
--
Additional (2): fi-glk-j4005 bat-jsl-3
Missing(6): fi-kbl-7567u fi-snb-2520m fi-kbl-8809g fi-cfl-8109u
fi-elk-e7500 bat-arls-3
Known issues
Here are the changes found in Patchwork_133965v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-jsl-3: NOTRUN -> [SKIP][1] ([i915#9318])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/bat-jsl-3/igt@debugfs_t...@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- bat-jsl-3: NOTRUN -> [SKIP][2] ([i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/bat-jsl-3/igt@gem_huc_c...@huc-copy.html
- fi-glk-j4005: NOTRUN -> [SKIP][3] ([i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- bat-jsl-3: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/bat-jsl-3/igt@gem_lmem_swapp...@basic.html
- fi-glk-j4005: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-glk-j4005: NOTRUN -> [SKIP][6] +10 other tests skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/fi-glk-j4005/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-3: NOTRUN -> [SKIP][7] ([i915#4103]) +1 other test skip
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/bat-jsl-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-jsl-3: NOTRUN -> [SKIP][8] ([i915#3555] / [i915#9886])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/bat-jsl-3/igt@kms_...@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-jsl-3: NOTRUN -> [SKIP][9]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/bat-jsl-3/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-jsl-3: NOTRUN -> [SKIP][10] ([i915#3555])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/bat-jsl-3/igt@kms_setm...@basic-clone-single-crtc.html
Possible fixes
* igt@i915_module_load@load:
- bat-dg2-8: [DMESG-WARN][11] ([i915#10014]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/bat-dg2-8/igt@i915_module_l...@load.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/bat-dg2-8/igt@i915_module_l...@load.html
* igt@i915_pm_rpm@module-reload:
- {bat-mtlp-9}: [CRASH][13] ([i915#10911]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/bat-mtlp-9/igt@i915_pm_...@module-reload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/bat-mtlp-9/igt@i915_pm_...@module-reload.html
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-c-dp-6:
- {bat-mtlp-9}: [DMESG-FAIL][15] ([i915#11009]) -> [PASS][16] +2
other tests pass
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/bat-mtlp-9/igt@kms_pipe_crc_basic@hang-read-...@pipe-c-dp-6.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/bat-mtlp-9/igt@kms_pipe_crc_basic@hang-read-...@pipe-c-dp-6.html
* igt@kms_pipe_crc_basic@hang-read-crc@pipe-d-dp-6:
- {bat-mtlp-9}: [FAIL][17] -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/bat-mtlp-9/igt@kms_pipe_crc_basic@hang-read-...@pipe-d-dp-6.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133965v1/bat-mtlp-9/igt@kms_pipe_crc_basic@hang-read-...@pipe-d-dp-6.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10014]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10014
[i915#10911]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10911
[i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#3555]: https://gitlab.freedesktop
Re: [PATCH v2 12/21] drm/i915/dp: Use check link state work in the detect handler
On Mon, May 20, 2024 at 09:58:10PM +0300, Imre Deak wrote:
> Simplify things by retraining a DP link if a bad link is detected in the
> connector detect handler from the encoder's check link state work,
> similarly to how this is done after a modeset link training failure.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 7 ++-
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index ff4ed6bb520d8..70b00e5ae7ad7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5863,11 +5863,8 @@ intel_dp_detect(struct drm_connector *connector,
>* Some external monitors do not signal loss of link synchronization
>* with an IRQ_HPD, so force a link status check.
>*/
> - if (!intel_dp_is_edp(intel_dp)) {
> - ret = intel_dp_retrain_link(encoder, ctx);
> - if (ret)
> - return ret;
> - }
> + if (!intel_dp_is_edp(intel_dp))
> + intel_dp_check_link_state(intel_dp);
I would like to see this hack nuked entirely. But that
could be a followup.
>
> /*
>* Clearing NACK and defer counts to get their exact values
> --
> 2.43.3
--
Ville Syrjälä
Intel
✗ Fi.CI.SPARSE: warning for amd, i915, xe: drop redundant warnings from driver makefiles
== Series Details == Series: amd, i915, xe: drop redundant warnings from driver makefiles URL : https://patchwork.freedesktop.org/series/133965/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [PATCH v2 09/21] drm/i915/dp: Pass atomic state to link training function
On Thu, May 23, 2024 at 05:54:10PM +0300, Ville Syrjälä wrote: > On Thu, May 23, 2024 at 05:47:36PM +0300, Imre Deak wrote: > > On Thu, May 23, 2024 at 05:41:17PM +0300, Ville Syrjälä wrote: > > > On Mon, May 20, 2024 at 09:58:07PM +0300, Imre Deak wrote: > > > > From: Imre Deak > > > > > > > > The next patch adds sending a modeset-retry uevent after a link training > > > > failure to all MST connectors on link. This requires the atomic state, > > > > so pass it to intel_dp_start_link_train(). In case of SST where > > > > retraining still happens by calling this function directly instead of a > > > > modeset commit the atomic state is not available and NULL is passed > > > > instead. This is ok, since in this case the encoder's only DP connector > > > > is available from intel_dp->attached_connector not requiring the atomic > > > > state. > > > > > > > > Signed-off-by: Imre Deak > > > > --- > > > > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +- > > > > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- > > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > > > > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 4 +++- > > > > drivers/gpu/drm/i915/display/intel_dp_link_training.h | 4 +++- > > > > 5 files changed, 11 insertions(+), 7 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c > > > > b/drivers/gpu/drm/i915/display/g4x_dp.c > > > > index 4363e32a834df..0d7424a7581e6 100644 > > > > --- a/drivers/gpu/drm/i915/display/g4x_dp.c > > > > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c > > > > @@ -707,7 +707,7 @@ static void intel_enable_dp(struct > > > > intel_atomic_state *state, > > > > intel_dp_configure_protocol_converter(intel_dp, pipe_config); > > > > intel_dp_check_frl_training(intel_dp); > > > > intel_dp_pcon_dsc_configure(intel_dp, pipe_config); > > > > - intel_dp_start_link_train(intel_dp, pipe_config); > > > > + intel_dp_start_link_train(state, intel_dp, pipe_config); > > > > intel_dp_stop_link_train(intel_dp, pipe_config); > > > > } > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > index 86358ec27e685..58e57a7704811 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > @@ -2586,7 +2586,7 @@ static void mtl_ddi_pre_enable_dp(struct > > > > intel_atomic_state *state, > > > > * Pattern, wait for 5 idle patterns (DP_TP_STATUS > > > > Min_Idles_Sent) > > > > * (timeout after 800 us) > > > > */ > > > > - intel_dp_start_link_train(intel_dp, crtc_state); > > > > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > > > > > > > /* 6.n Set DP_TP_CTL link training to Normal */ > > > > if (!is_trans_port_sync_mode(crtc_state)) > > > > @@ -2728,7 +2728,7 @@ static void tgl_ddi_pre_enable_dp(struct > > > > intel_atomic_state *state, > > > > * Pattern, wait for 5 idle patterns (DP_TP_STATUS > > > > Min_Idles_Sent) > > > > * (timeout after 800 us) > > > > */ > > > > - intel_dp_start_link_train(intel_dp, crtc_state); > > > > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > > > > > > > /* 7.k Set DP_TP_CTL link training to Normal */ > > > > if (!is_trans_port_sync_mode(crtc_state)) > > > > @@ -2795,7 +2795,7 @@ static void hsw_ddi_pre_enable_dp(struct > > > > intel_atomic_state *state, > > > > > > > > to_intel_connector(conn_state->connector), > > > >crtc_state); > > > > intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); > > > > - intel_dp_start_link_train(intel_dp, crtc_state); > > > > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > > > if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && > > > > !is_trans_port_sync_mode(crtc_state)) > > > > intel_dp_stop_link_train(intel_dp, crtc_state); > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > > index 7c824c5a13346..1f0b7cceea2dc 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > @@ -5214,7 +5214,7 @@ int intel_dp_retrain_link(struct intel_encoder > > > > *encoder, > > > > > > > > intel_dp_check_frl_training(intel_dp); > > > > intel_dp_pcon_dsc_configure(intel_dp, crtc_state); > > > > - intel_dp_start_link_train(intel_dp, crtc_state); > > > > + intel_dp_start_link_train(NULL, intel_dp, crtc_state); > > > > > > I was going to suggest s/crtc_state/crtc/ for this, but the state==NULL > > > definitiely makes that impossible. I think we need to document each and
Re: [PATCH v2 09/21] drm/i915/dp: Pass atomic state to link training function
On Thu, May 23, 2024 at 05:54:10PM +0300, Ville Syrjälä wrote: > On Thu, May 23, 2024 at 05:47:36PM +0300, Imre Deak wrote: > > On Thu, May 23, 2024 at 05:41:17PM +0300, Ville Syrjälä wrote: > > > On Mon, May 20, 2024 at 09:58:07PM +0300, Imre Deak wrote: > > > > From: Imre Deak > > > > > > > > The next patch adds sending a modeset-retry uevent after a link training > > > > failure to all MST connectors on link. This requires the atomic state, > > > > so pass it to intel_dp_start_link_train(). In case of SST where > > > > retraining still happens by calling this function directly instead of a > > > > modeset commit the atomic state is not available and NULL is passed > > > > instead. This is ok, since in this case the encoder's only DP connector > > > > is available from intel_dp->attached_connector not requiring the atomic > > > > state. > > > > > > > > Signed-off-by: Imre Deak > > > > --- > > > > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +- > > > > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- > > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > > > > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 4 +++- > > > > drivers/gpu/drm/i915/display/intel_dp_link_training.h | 4 +++- > > > > 5 files changed, 11 insertions(+), 7 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c > > > > b/drivers/gpu/drm/i915/display/g4x_dp.c > > > > index 4363e32a834df..0d7424a7581e6 100644 > > > > --- a/drivers/gpu/drm/i915/display/g4x_dp.c > > > > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c > > > > @@ -707,7 +707,7 @@ static void intel_enable_dp(struct > > > > intel_atomic_state *state, > > > > intel_dp_configure_protocol_converter(intel_dp, pipe_config); > > > > intel_dp_check_frl_training(intel_dp); > > > > intel_dp_pcon_dsc_configure(intel_dp, pipe_config); > > > > - intel_dp_start_link_train(intel_dp, pipe_config); > > > > + intel_dp_start_link_train(state, intel_dp, pipe_config); > > > > intel_dp_stop_link_train(intel_dp, pipe_config); > > > > } > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > index 86358ec27e685..58e57a7704811 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > @@ -2586,7 +2586,7 @@ static void mtl_ddi_pre_enable_dp(struct > > > > intel_atomic_state *state, > > > > * Pattern, wait for 5 idle patterns (DP_TP_STATUS > > > > Min_Idles_Sent) > > > > * (timeout after 800 us) > > > > */ > > > > - intel_dp_start_link_train(intel_dp, crtc_state); > > > > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > > > > > > > /* 6.n Set DP_TP_CTL link training to Normal */ > > > > if (!is_trans_port_sync_mode(crtc_state)) > > > > @@ -2728,7 +2728,7 @@ static void tgl_ddi_pre_enable_dp(struct > > > > intel_atomic_state *state, > > > > * Pattern, wait for 5 idle patterns (DP_TP_STATUS > > > > Min_Idles_Sent) > > > > * (timeout after 800 us) > > > > */ > > > > - intel_dp_start_link_train(intel_dp, crtc_state); > > > > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > > > > > > > /* 7.k Set DP_TP_CTL link training to Normal */ > > > > if (!is_trans_port_sync_mode(crtc_state)) > > > > @@ -2795,7 +2795,7 @@ static void hsw_ddi_pre_enable_dp(struct > > > > intel_atomic_state *state, > > > > > > > > to_intel_connector(conn_state->connector), > > > >crtc_state); > > > > intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); > > > > - intel_dp_start_link_train(intel_dp, crtc_state); > > > > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > > > if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && > > > > !is_trans_port_sync_mode(crtc_state)) > > > > intel_dp_stop_link_train(intel_dp, crtc_state); > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > > index 7c824c5a13346..1f0b7cceea2dc 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > @@ -5214,7 +5214,7 @@ int intel_dp_retrain_link(struct intel_encoder > > > > *encoder, > > > > > > > > intel_dp_check_frl_training(intel_dp); > > > > intel_dp_pcon_dsc_configure(intel_dp, crtc_state); > > > > - intel_dp_start_link_train(intel_dp, crtc_state); > > > > + intel_dp_start_link_train(NULL, intel_dp, crtc_state); > > > > > > I was going to suggest s/crtc_state/crtc/ for this, but the state==NULL > > > definitiely makes that impossible. I think we need to document each and
Re: [PATCH v2 09/21] drm/i915/dp: Pass atomic state to link training function
On Thu, May 23, 2024 at 05:47:36PM +0300, Imre Deak wrote: > On Thu, May 23, 2024 at 05:41:17PM +0300, Ville Syrjälä wrote: > > On Mon, May 20, 2024 at 09:58:07PM +0300, Imre Deak wrote: > > > From: Imre Deak > > > > > > The next patch adds sending a modeset-retry uevent after a link training > > > failure to all MST connectors on link. This requires the atomic state, > > > so pass it to intel_dp_start_link_train(). In case of SST where > > > retraining still happens by calling this function directly instead of a > > > modeset commit the atomic state is not available and NULL is passed > > > instead. This is ok, since in this case the encoder's only DP connector > > > is available from intel_dp->attached_connector not requiring the atomic > > > state. > > > > > > Signed-off-by: Imre Deak > > > --- > > > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +- > > > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > > > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 4 +++- > > > drivers/gpu/drm/i915/display/intel_dp_link_training.h | 4 +++- > > > 5 files changed, 11 insertions(+), 7 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c > > > b/drivers/gpu/drm/i915/display/g4x_dp.c > > > index 4363e32a834df..0d7424a7581e6 100644 > > > --- a/drivers/gpu/drm/i915/display/g4x_dp.c > > > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c > > > @@ -707,7 +707,7 @@ static void intel_enable_dp(struct intel_atomic_state > > > *state, > > > intel_dp_configure_protocol_converter(intel_dp, pipe_config); > > > intel_dp_check_frl_training(intel_dp); > > > intel_dp_pcon_dsc_configure(intel_dp, pipe_config); > > > - intel_dp_start_link_train(intel_dp, pipe_config); > > > + intel_dp_start_link_train(state, intel_dp, pipe_config); > > > intel_dp_stop_link_train(intel_dp, pipe_config); > > > } > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index 86358ec27e685..58e57a7704811 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -2586,7 +2586,7 @@ static void mtl_ddi_pre_enable_dp(struct > > > intel_atomic_state *state, > > >* Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) > > >* (timeout after 800 us) > > >*/ > > > - intel_dp_start_link_train(intel_dp, crtc_state); > > > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > > > > > /* 6.n Set DP_TP_CTL link training to Normal */ > > > if (!is_trans_port_sync_mode(crtc_state)) > > > @@ -2728,7 +2728,7 @@ static void tgl_ddi_pre_enable_dp(struct > > > intel_atomic_state *state, > > >* Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) > > >* (timeout after 800 us) > > >*/ > > > - intel_dp_start_link_train(intel_dp, crtc_state); > > > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > > > > > /* 7.k Set DP_TP_CTL link training to Normal */ > > > if (!is_trans_port_sync_mode(crtc_state)) > > > @@ -2795,7 +2795,7 @@ static void hsw_ddi_pre_enable_dp(struct > > > intel_atomic_state *state, > > > > > > to_intel_connector(conn_state->connector), > > > crtc_state); > > > intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); > > > - intel_dp_start_link_train(intel_dp, crtc_state); > > > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > > if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && > > > !is_trans_port_sync_mode(crtc_state)) > > > intel_dp_stop_link_train(intel_dp, crtc_state); > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > index 7c824c5a13346..1f0b7cceea2dc 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -5214,7 +5214,7 @@ int intel_dp_retrain_link(struct intel_encoder > > > *encoder, > > > > > > intel_dp_check_frl_training(intel_dp); > > > intel_dp_pcon_dsc_configure(intel_dp, crtc_state); > > > - intel_dp_start_link_train(intel_dp, crtc_state); > > > + intel_dp_start_link_train(NULL, intel_dp, crtc_state); > > > > I was going to suggest s/crtc_state/crtc/ for this, but the state==NULL > > definitiely makes that impossible. I think we need to document each and > > every function where the atomic state may be NULL and thus needs to be > > passed the crtc_state as well. Otherwise someone (probably me) is likely > > going to attempt some cleanups which will then explode, or someone will > > just attempt to dig out something from the full atomic state (eg. > > state->base.dev). > > This is meant to be a temporary solution, for maybe a few weeks after > this gets merged after which retraining should be swi
✓ Fi.CI.BAT: success for drm/i915: dev_priv fixes for i9xx_plane_regs.h/intel_color_regs.h
== Series Details ==
Series: drm/i915: dev_priv fixes for i9xx_plane_regs.h/intel_color_regs.h
URL : https://patchwork.freedesktop.org/series/133961/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14809 -> Patchwork_133961v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133961v1/index.html
Participating hosts (43 -> 38)
--
Missing(5): fi-snb-2520m fi-cfl-8109u fi-elk-e7500 fi-kbl-8809g
bat-arls-3
Known issues
Here are the changes found in Patchwork_133961v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-11: [PASS][1] -> [FAIL][2] ([i915#10378])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/bat-dg2-11/igt@gem_lmem_swapping@ba...@lmem0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133961v1/bat-dg2-11/igt@gem_lmem_swapping@ba...@lmem0.html
- bat-dg2-8: [PASS][3] -> [FAIL][4] ([i915#10378])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133961v1/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: [PASS][5] -> [DMESG-WARN][6] ([i915#1982] /
[i915#8585])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/fi-kbl-7567u/igt@i915_pm_...@module-reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133961v1/fi-kbl-7567u/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-7567u: [PASS][7] -> [DMESG-WARN][8] ([i915#10900]) +31 other
tests dmesg-warn
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133961v1/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_pm_rpm@basic-pci-d3-state:
- fi-kbl-7567u: [PASS][9] -> [DMESG-WARN][10] ([i915#8585]) +82 other
tests dmesg-warn
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/fi-kbl-7567u/igt@kms_pm_...@basic-pci-d3-state.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133961v1/fi-kbl-7567u/igt@kms_pm_...@basic-pci-d3-state.html
Possible fixes
* igt@i915_module_load@load:
- bat-dg2-8: [DMESG-WARN][11] ([i915#10014]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/bat-dg2-8/igt@i915_module_l...@load.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133961v1/bat-dg2-8/igt@i915_module_l...@load.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1:
- bat-mtlp-8: [DMESG-WARN][13] ([i915#9157]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14809/bat-mtlp-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-b-edp-1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133961v1/bat-mtlp-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-b-edp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10014]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10014
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10900]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10900
[i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#6121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6121
[i915#8585]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8585
[i915#9157]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9157
Build changes
-
* Linux: CI_DRM_14809 -> Patchwork_133961v1
CI-20190529: 20190529
CI_DRM_14809: 8e768c3e813ab5519a85997b622edc9a2f79c083 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7869: e43892a30d594f8bcbcbd42ccffe298313479215 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133961v1: 8e768c3e813ab5519a85997b622edc9a2f79c083 @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133961v1/index.html
Re: [PATCH v2 09/21] drm/i915/dp: Pass atomic state to link training function
On Thu, May 23, 2024 at 05:41:17PM +0300, Ville Syrjälä wrote: > On Mon, May 20, 2024 at 09:58:07PM +0300, Imre Deak wrote: > > From: Imre Deak > > > > The next patch adds sending a modeset-retry uevent after a link training > > failure to all MST connectors on link. This requires the atomic state, > > so pass it to intel_dp_start_link_train(). In case of SST where > > retraining still happens by calling this function directly instead of a > > modeset commit the atomic state is not available and NULL is passed > > instead. This is ok, since in this case the encoder's only DP connector > > is available from intel_dp->attached_connector not requiring the atomic > > state. > > > > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +- > > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 4 +++- > > drivers/gpu/drm/i915/display/intel_dp_link_training.h | 4 +++- > > 5 files changed, 11 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c > > b/drivers/gpu/drm/i915/display/g4x_dp.c > > index 4363e32a834df..0d7424a7581e6 100644 > > --- a/drivers/gpu/drm/i915/display/g4x_dp.c > > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c > > @@ -707,7 +707,7 @@ static void intel_enable_dp(struct intel_atomic_state > > *state, > > intel_dp_configure_protocol_converter(intel_dp, pipe_config); > > intel_dp_check_frl_training(intel_dp); > > intel_dp_pcon_dsc_configure(intel_dp, pipe_config); > > - intel_dp_start_link_train(intel_dp, pipe_config); > > + intel_dp_start_link_train(state, intel_dp, pipe_config); > > intel_dp_stop_link_train(intel_dp, pipe_config); > > } > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 86358ec27e685..58e57a7704811 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -2586,7 +2586,7 @@ static void mtl_ddi_pre_enable_dp(struct > > intel_atomic_state *state, > > * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) > > * (timeout after 800 us) > > */ > > - intel_dp_start_link_train(intel_dp, crtc_state); > > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > > > /* 6.n Set DP_TP_CTL link training to Normal */ > > if (!is_trans_port_sync_mode(crtc_state)) > > @@ -2728,7 +2728,7 @@ static void tgl_ddi_pre_enable_dp(struct > > intel_atomic_state *state, > > * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) > > * (timeout after 800 us) > > */ > > - intel_dp_start_link_train(intel_dp, crtc_state); > > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > > > /* 7.k Set DP_TP_CTL link training to Normal */ > > if (!is_trans_port_sync_mode(crtc_state)) > > @@ -2795,7 +2795,7 @@ static void hsw_ddi_pre_enable_dp(struct > > intel_atomic_state *state, > > > > to_intel_connector(conn_state->connector), > >crtc_state); > > intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); > > - intel_dp_start_link_train(intel_dp, crtc_state); > > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && > > !is_trans_port_sync_mode(crtc_state)) > > intel_dp_stop_link_train(intel_dp, crtc_state); > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index 7c824c5a13346..1f0b7cceea2dc 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5214,7 +5214,7 @@ int intel_dp_retrain_link(struct intel_encoder > > *encoder, > > > > intel_dp_check_frl_training(intel_dp); > > intel_dp_pcon_dsc_configure(intel_dp, crtc_state); > > - intel_dp_start_link_train(intel_dp, crtc_state); > > + intel_dp_start_link_train(NULL, intel_dp, crtc_state); > > I was going to suggest s/crtc_state/crtc/ for this, but the state==NULL > definitiely makes that impossible. I think we need to document each and > every function where the atomic state may be NULL and thus needs to be > passed the crtc_state as well. Otherwise someone (probably me) is likely > going to attempt some cleanups which will then explode, or someone will > just attempt to dig out something from the full atomic state (eg. > state->base.dev). This is meant to be a temporary solution, for maybe a few weeks after this gets merged after which retraining should be switched over to be a modeset in all cases; but agreed it's better to document that in intel_dp_start_link_train(), will add that. > > > intel_dp_stop_link_train(intel_dp, crtc
Re: [PATCH v2 09/21] drm/i915/dp: Pass atomic state to link training function
On Mon, May 20, 2024 at 09:58:07PM +0300, Imre Deak wrote: > From: Imre Deak > > The next patch adds sending a modeset-retry uevent after a link training > failure to all MST connectors on link. This requires the atomic state, > so pass it to intel_dp_start_link_train(). In case of SST where > retraining still happens by calling this function directly instead of a > modeset commit the atomic state is not available and NULL is passed > instead. This is ok, since in this case the encoder's only DP connector > is available from intel_dp->attached_connector not requiring the atomic > state. > > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +- > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 4 +++- > drivers/gpu/drm/i915/display/intel_dp_link_training.h | 4 +++- > 5 files changed, 11 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c > b/drivers/gpu/drm/i915/display/g4x_dp.c > index 4363e32a834df..0d7424a7581e6 100644 > --- a/drivers/gpu/drm/i915/display/g4x_dp.c > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c > @@ -707,7 +707,7 @@ static void intel_enable_dp(struct intel_atomic_state > *state, > intel_dp_configure_protocol_converter(intel_dp, pipe_config); > intel_dp_check_frl_training(intel_dp); > intel_dp_pcon_dsc_configure(intel_dp, pipe_config); > - intel_dp_start_link_train(intel_dp, pipe_config); > + intel_dp_start_link_train(state, intel_dp, pipe_config); > intel_dp_stop_link_train(intel_dp, pipe_config); > } > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 86358ec27e685..58e57a7704811 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -2586,7 +2586,7 @@ static void mtl_ddi_pre_enable_dp(struct > intel_atomic_state *state, >* Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) >* (timeout after 800 us) >*/ > - intel_dp_start_link_train(intel_dp, crtc_state); > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > /* 6.n Set DP_TP_CTL link training to Normal */ > if (!is_trans_port_sync_mode(crtc_state)) > @@ -2728,7 +2728,7 @@ static void tgl_ddi_pre_enable_dp(struct > intel_atomic_state *state, >* Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) >* (timeout after 800 us) >*/ > - intel_dp_start_link_train(intel_dp, crtc_state); > + intel_dp_start_link_train(state, intel_dp, crtc_state); > > /* 7.k Set DP_TP_CTL link training to Normal */ > if (!is_trans_port_sync_mode(crtc_state)) > @@ -2795,7 +2795,7 @@ static void hsw_ddi_pre_enable_dp(struct > intel_atomic_state *state, > > to_intel_connector(conn_state->connector), > crtc_state); > intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); > - intel_dp_start_link_train(intel_dp, crtc_state); > + intel_dp_start_link_train(state, intel_dp, crtc_state); > if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && > !is_trans_port_sync_mode(crtc_state)) > intel_dp_stop_link_train(intel_dp, crtc_state); > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 7c824c5a13346..1f0b7cceea2dc 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5214,7 +5214,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, > > intel_dp_check_frl_training(intel_dp); > intel_dp_pcon_dsc_configure(intel_dp, crtc_state); > - intel_dp_start_link_train(intel_dp, crtc_state); > + intel_dp_start_link_train(NULL, intel_dp, crtc_state); I was going to suggest s/crtc_state/crtc/ for this, but the state==NULL definitiely makes that impossible. I think we need to document each and every function where the atomic state may be NULL and thus needs to be passed the crtc_state as well. Otherwise someone (probably me) is likely going to attempt some cleanups which will then explode, or someone will just attempt to dig out something from the full atomic state (eg. state->base.dev). > intel_dp_stop_link_train(intel_dp, crtc_state); > break; > } > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index e804f0b801c02..4f60daa97407d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -1453,6 +1453,7 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp, > > /** > * intel_
✗ Fi.CI.SPARSE: warning for drm/i915: dev_priv fixes for i9xx_plane_regs.h/intel_color_regs.h
== Series Details == Series: drm/i915: dev_priv fixes for i9xx_plane_regs.h/intel_color_regs.h URL : https://patchwork.freedesktop.org/series/133961/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unrepl
✗ Fi.CI.CHECKPATCH: warning for drm/i915: dev_priv fixes for i9xx_plane_regs.h/intel_color_regs.h
== Series Details == Series: drm/i915: dev_priv fixes for i9xx_plane_regs.h/intel_color_regs.h URL : https://patchwork.freedesktop.org/series/133961/ State : warning == Summary == Error: dim checkpatch failed c6ca7406f7f7 drm/i915: pass dev_priv explicitly to DSPADDR_VLV f3e2cda96093 drm/i915: pass dev_priv explicitly to DSPCNTR d200ecb0dabd drm/i915: pass dev_priv explicitly to DSPADDR 26f159f76eb9 drm/i915: pass dev_priv explicitly to DSPLINOFF 86586f314608 drm/i915: pass dev_priv explicitly to DSPSTRIDE 84bf2fe7719e drm/i915: pass dev_priv explicitly to DSPPOS 50e20395f963 drm/i915: pass dev_priv explicitly to DSPSIZE 14cc75f5e8bb drm/i915: pass dev_priv explicitly to DSPSURF 22c27f81f743 drm/i915: pass dev_priv explicitly to DSPTILEOFF e9250cd74599 drm/i915: pass dev_priv explicitly to DSPOFFSET e6da8f36eeeb drm/i915: pass dev_priv explicitly to DSPSURFLIVE 94ef1395cf13 drm/i915: pass dev_priv explicitly to DSPGAMC -:20: WARNING:LONG_LINE: line length of 132 exceeds 100 columns #20: FILE: drivers/gpu/drm/i915/display/i9xx_plane_regs.h:87: +#define DSPGAMC(dev_priv, plane, i)_MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ total: 0 errors, 1 warnings, 0 checks, 8 lines checked b077c7fdcc89 drm/i915: pass dev_priv explicitly to PRIMPOS cc98490d42de drm/i915: pass dev_priv explicitly to PRIMSIZE 70ee81fa5acd drm/i915: pass dev_priv explicitly to PRIMCNSTALPHA 287db389c945 drm/i915: pass dev_priv explicitly to PIPEGCMAX -:40: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #40: FILE: drivers/gpu/drm/i915/display/intel_color.c:3243: + lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0))); -:41: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #41: FILE: drivers/gpu/drm/i915/display/intel_color.c:3244: + lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1))); -:42: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #42: FILE: drivers/gpu/drm/i915/display/intel_color.c:3245: + lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2))); -:59: WARNING:LONG_LINE_COMMENT: line length of 102 exceeds 100 columns #59: FILE: drivers/gpu/drm/i915/display/intel_color_regs.h:42: +#define PIPEGCMAX(dev_priv, pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ total: 0 errors, 4 warnings, 0 checks, 37 lines checked
Re: [PATCH v2 07/21] drm/i915/dp: Recheck link state after modeset
On Thu, May 23, 2024 at 04:58:38PM +0300, Ville Syrjälä wrote:
> On Thu, May 23, 2024 at 04:46:30PM +0300, Imre Deak wrote:
> > On Thu, May 23, 2024 at 04:30:18PM +0300, Ville Syrjälä wrote:
> > > On Mon, May 20, 2024 at 09:58:05PM +0300, Imre Deak wrote:
> > > > Recheck the link state after a passing link training, with a 2 sec delay
> > > > to account for cases where the link goes bad following the link training
> > > > and the sink doesn't report this via an HPD IRQ.
> > > >
> > > > The delayed work added here will be also used by a later patch after a
> > > > failed link training to try to retrain the link with unchanged link
> > > > params before reducing the link params.
> > > >
> > > > v2: Don't flush an uninitialized delayed work (on HDMI-only DDI ports).
> > > > v3: Add the work to intel_digital_port instead of intel_dp.
> > > >
> > > > Signed-off-by: Imre Deak
> > > > ---
> > > > drivers/gpu/drm/i915/display/g4x_dp.c | 7
> > > > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++
> > > > drivers/gpu/drm/i915/display/intel_ddi.h | 4 +++
> > > > .../drm/i915/display/intel_display_types.h| 3 ++
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> > > > .../drm/i915/display/intel_dp_link_training.c | 12 +--
> > > > 6 files changed, 58 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> > > > b/drivers/gpu/drm/i915/display/g4x_dp.c
> > > > index 06ec04e667e32..4363e32a834df 100644
> > > > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> > > > @@ -20,6 +20,7 @@
> > > > #include "intel_dp_aux.h"
> > > > #include "intel_dp_link_training.h"
> > > > #include "intel_dpio_phy.h"
> > > > +#include "intel_ddi.h"
> > > > #include "intel_fifo_underrun.h"
> > > > #include "intel_hdmi.h"
> > > > #include "intel_hotplug.h"
> > > > @@ -1241,6 +1242,10 @@ static bool ilk_digital_port_connected(struct
> > > > intel_encoder *encoder)
> > > >
> > > > static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
> > > > {
> > > > + struct intel_digital_port *dig_port =
> > > > enc_to_dig_port(to_intel_encoder(encoder));
> > > > +
> > > > + intel_ddi_flush_link_check_work(dig_port);
> > > > +
> > > > intel_dp_encoder_flush_work(encoder);
> > > >
> > > > drm_encoder_cleanup(encoder);
> > > > @@ -1309,6 +1314,8 @@ bool g4x_dp_init(struct drm_i915_private
> > > > *dev_priv,
> > > >
> > > > dig_port->aux_ch = AUX_CH_NONE;
> > > >
> > > > + intel_ddi_init_link_check_work(dig_port);
> > >
> > > Using "ddi" for pre-ddi platforms is confusing. The implementation
> > > is also in intel_ddi.c for some reason.
> >
> > Yes. It's a generic encoder or digital port functionality, neither of
> > which have its own file. How about moving them to intel_display.c and
> > the intel_display_link_{init_work, queue_work, flush_work, work_fn}
> > names?
>
> We could add some new file for this kind of generic encoder stuff.
> intel_encoder.c or intel_dig_port.c maybe?
Ok, there seems to be more encoder functions that could be moved there,
so I'll add intel_encoder.c.
> > > > +
> > > > intel_connector = intel_connector_alloc();
> > > > if (!intel_connector)
> > > > goto err_connector_alloc;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > index 170ba01786cf8..86358ec27e685 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > @@ -4360,6 +4360,7 @@ static void intel_ddi_encoder_destroy(struct
> > > > drm_encoder *encoder)
> > > > struct drm_i915_private *i915 = to_i915(encoder->dev);
> > > > struct intel_digital_port *dig_port =
> > > > enc_to_dig_port(to_intel_encoder(encoder));
> > > >
> > > > + intel_ddi_flush_link_check_work(dig_port);
> > > > intel_dp_encoder_flush_work(encoder);
> > > > if (intel_encoder_is_tc(&dig_port->base))
> > > > intel_tc_port_cleanup(dig_port);
> > > > @@ -4441,6 +4442,37 @@ intel_ddi_init_dp_connector(struct
> > > > intel_digital_port *dig_port)
> > > > return connector;
> > > > }
> > > >
> > > > +static void intel_ddi_link_check_work_fn(struct work_struct *work)
> > > > +{
> > > > + struct intel_digital_port *dig_port =
> > > > + container_of(work, typeof(*dig_port),
> > > > check_link_work.work);
> > > > + struct intel_encoder *encoder = &dig_port->base;
> > > > + struct drm_modeset_acquire_ctx ctx;
> > > > + int ret;
> > > > +
> > > > + intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
> > > > + if (dig_port->dp.attached_connector)
> > > > + ret = intel_dp_retrain_link(encoder, &ctx);
> > > > +}
> > > > +
> > > > +void intel_ddi_init_link_check_work(struct intel_
✗ Fi.CI.IGT: failure for drm/i915: identify all platforms in display probe
== Series Details == Series: drm/i915: identify all platforms in display probe URL : https://patchwork.freedesktop.org/series/133932/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14804_full -> Patchwork_133932v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_133932v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_133932v1_full, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_133932v1_full: ### IGT changes ### Possible regressions * igt@fbdev@write: - shard-snb: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-snb5/igt@fb...@write.html * igt@gem_mmap_offset@open-flood: - shard-dg2: [PASS][2] -> [INCOMPLETE][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14804/shard-dg2-4/igt@gem_mmap_off...@open-flood.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-dg2-5/igt@gem_mmap_off...@open-flood.html New tests - New tests have been introduced between CI_DRM_14804_full and Patchwork_133932v1_full: ### New IGT tests (1) ### * igt@kms_flip@dpms-vs-vblank-race@d-hdmi-a3: - Statuses : 1 pass(s) - Exec time: [2.91] s Known issues Here are the changes found in Patchwork_133932v1_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_fdinfo@all-busy-check-all: - shard-dg2: NOTRUN -> [SKIP][4] ([i915#8414]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-dg2-3/igt@drm_fdi...@all-busy-check-all.html * igt@drm_fdinfo@busy-check-all@bcs0: - shard-dg1: NOTRUN -> [SKIP][5] ([i915#8414]) +4 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-dg1-16/igt@drm_fdinfo@busy-check-...@bcs0.html * igt@gem_bad_reloc@negative-reloc-lut: - shard-rkl: NOTRUN -> [SKIP][6] ([i915#3281]) +7 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-rkl-3/igt@gem_bad_re...@negative-reloc-lut.html * igt@gem_ccs@block-copy-compressed: - shard-dg1: NOTRUN -> [SKIP][7] ([i915#3555] / [i915#9323]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-dg1-16/igt@gem_...@block-copy-compressed.html * igt@gem_ccs@suspend-resume: - shard-tglu: NOTRUN -> [SKIP][8] ([i915#9323]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-tglu-8/igt@gem_...@suspend-resume.html * igt@gem_create@create-ext-set-pat: - shard-rkl: NOTRUN -> [SKIP][9] ([i915#8562]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-rkl-5/igt@gem_cre...@create-ext-set-pat.html * igt@gem_ctx_persistence@heartbeat-hang: - shard-dg1: NOTRUN -> [SKIP][10] ([i915#8555]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-dg1-16/igt@gem_ctx_persiste...@heartbeat-hang.html * igt@gem_ctx_persistence@heartbeat-stop: - shard-mtlp: NOTRUN -> [SKIP][11] ([i915#8555]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-mtlp-4/igt@gem_ctx_persiste...@heartbeat-stop.html * igt@gem_ctx_sseu@invalid-sseu: - shard-dg2: NOTRUN -> [SKIP][12] ([i915#280]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-dg2-3/igt@gem_ctx_s...@invalid-sseu.html - shard-rkl: NOTRUN -> [SKIP][13] ([i915#280]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-rkl-3/igt@gem_ctx_s...@invalid-sseu.html * igt@gem_exec_balancer@parallel-bb-first: - shard-rkl: NOTRUN -> [SKIP][14] ([i915#4525]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-rkl-3/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_capture@capture-invisible@smem0: - shard-glk: NOTRUN -> [SKIP][15] ([i915#6334]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-glk8/igt@gem_exec_capture@capture-invisi...@smem0.html * igt@gem_exec_capture@capture-recoverable: - shard-tglu: NOTRUN -> [SKIP][16] ([i915#6344]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133932v1/shard-tglu-9/igt@gem_exec_capt...@capture-recoverable.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-rkl: NOTRUN -> [FAIL][17] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1339
[linux-next:master] BUILD REGRESSION 3689b0ef08b70e4e03b82ebd37730a03a672853a
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: 3689b0ef08b70e4e03b82ebd37730a03a672853a Add linux-next specific files for 20240523 Unverified Error/Warning (likely false positive, please contact us if interested): drivers/gpu/drm/xe/xe_drm_client.c:272 show_runtime() error: uninitialized symbol 'hwe'. drivers/gpu/drm/xe/xe_drm_client.c:292 show_runtime() error: uninitialized symbol 'gpu_timestamp'. Error/Warning ids grouped by kconfigs: gcc_recent_errors |-- alpha-allyesconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arc-allmodconfig | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arc-allyesconfig | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arc-randconfig-002-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arm-allmodconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arm-allyesconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arm-randconfig-004-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arm64-randconfig-002-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- arm64-randconfig-004-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- csky-allmodconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- csky-allyesconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- csky-randconfig-001-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- csky-randconfig-002-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-allmodconfig | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-allyesconfig | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-011-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-014-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-015-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-016-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-053-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- i386-randconfig-054-20240523 | `-- drivers-regulator-rtq2208-regulator.c:warning:rtq2208_regulator_ldo_ops-defined-but-not-used |-- loongarch-allmodconfig | |-- drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and | |-- drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size | `-
Re: [PATCH v2 07/21] drm/i915/dp: Recheck link state after modeset
On Thu, May 23, 2024 at 04:46:30PM +0300, Imre Deak wrote:
> On Thu, May 23, 2024 at 04:30:18PM +0300, Ville Syrjälä wrote:
> > On Mon, May 20, 2024 at 09:58:05PM +0300, Imre Deak wrote:
> > > Recheck the link state after a passing link training, with a 2 sec delay
> > > to account for cases where the link goes bad following the link training
> > > and the sink doesn't report this via an HPD IRQ.
> > >
> > > The delayed work added here will be also used by a later patch after a
> > > failed link training to try to retrain the link with unchanged link
> > > params before reducing the link params.
> > >
> > > v2: Don't flush an uninitialized delayed work (on HDMI-only DDI ports).
> > > v3: Add the work to intel_digital_port instead of intel_dp.
> > >
> > > Signed-off-by: Imre Deak
> > > ---
> > > drivers/gpu/drm/i915/display/g4x_dp.c | 7
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++
> > > drivers/gpu/drm/i915/display/intel_ddi.h | 4 +++
> > > .../drm/i915/display/intel_display_types.h| 3 ++
> > > drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> > > .../drm/i915/display/intel_dp_link_training.c | 12 +--
> > > 6 files changed, 58 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> > > b/drivers/gpu/drm/i915/display/g4x_dp.c
> > > index 06ec04e667e32..4363e32a834df 100644
> > > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> > > @@ -20,6 +20,7 @@
> > > #include "intel_dp_aux.h"
> > > #include "intel_dp_link_training.h"
> > > #include "intel_dpio_phy.h"
> > > +#include "intel_ddi.h"
> > > #include "intel_fifo_underrun.h"
> > > #include "intel_hdmi.h"
> > > #include "intel_hotplug.h"
> > > @@ -1241,6 +1242,10 @@ static bool ilk_digital_port_connected(struct
> > > intel_encoder *encoder)
> > >
> > > static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
> > > {
> > > + struct intel_digital_port *dig_port =
> > > enc_to_dig_port(to_intel_encoder(encoder));
> > > +
> > > + intel_ddi_flush_link_check_work(dig_port);
> > > +
> > > intel_dp_encoder_flush_work(encoder);
> > >
> > > drm_encoder_cleanup(encoder);
> > > @@ -1309,6 +1314,8 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
> > >
> > > dig_port->aux_ch = AUX_CH_NONE;
> > >
> > > + intel_ddi_init_link_check_work(dig_port);
> >
> > Using "ddi" for pre-ddi platforms is confusing. The implementation
> > is also in intel_ddi.c for some reason.
>
> Yes. It's a generic encoder or digital port functionality, neither of
> which have its own file. How about moving them to intel_display.c and
> the intel_display_link_{init_work, queue_work, flush_work, work_fn}
> names?
We could add some new file for this kind of generic encoder stuff.
intel_encoder.c or intel_dig_port.c maybe?
>
> > > +
> > > intel_connector = intel_connector_alloc();
> > > if (!intel_connector)
> > > goto err_connector_alloc;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 170ba01786cf8..86358ec27e685 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -4360,6 +4360,7 @@ static void intel_ddi_encoder_destroy(struct
> > > drm_encoder *encoder)
> > > struct drm_i915_private *i915 = to_i915(encoder->dev);
> > > struct intel_digital_port *dig_port =
> > > enc_to_dig_port(to_intel_encoder(encoder));
> > >
> > > + intel_ddi_flush_link_check_work(dig_port);
> > > intel_dp_encoder_flush_work(encoder);
> > > if (intel_encoder_is_tc(&dig_port->base))
> > > intel_tc_port_cleanup(dig_port);
> > > @@ -4441,6 +4442,37 @@ intel_ddi_init_dp_connector(struct
> > > intel_digital_port *dig_port)
> > > return connector;
> > > }
> > >
> > > +static void intel_ddi_link_check_work_fn(struct work_struct *work)
> > > +{
> > > + struct intel_digital_port *dig_port =
> > > + container_of(work, typeof(*dig_port), check_link_work.work);
> > > + struct intel_encoder *encoder = &dig_port->base;
> > > + struct drm_modeset_acquire_ctx ctx;
> > > + int ret;
> > > +
> > > + intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
> > > + if (dig_port->dp.attached_connector)
> > > + ret = intel_dp_retrain_link(encoder, &ctx);
> > > +}
> > > +
> > > +void intel_ddi_init_link_check_work(struct intel_digital_port *dig_port)
> > > +{
> > > + INIT_DELAYED_WORK(&dig_port->check_link_work,
> > > intel_ddi_link_check_work_fn);
> > > +}
> > > +
> > > +void intel_ddi_flush_link_check_work(struct intel_digital_port *dig_port)
> > > +{
> > > + cancel_delayed_work_sync(&dig_port->check_link_work);
> > > +}
> > > +
> > > +void intel_ddi_queue_link_check(struct intel_digital_port *dig_port, int
> > > delay_ms)
> > > +{
> > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > +
> > > + mod_delayed_work(i915->un
[PATCH v2 2/2] drm/i915/display: Add compare config for MTL+ platforms
Currently, we may bump into pll mismatch errors during the
state verification stage. This happens when we try to use
fastset instead of full modeset. Hence, we would need to add
a check for pipe configuration to ensure that the sw and the
hw configuration will match. In case of hw and sw mismatch,
we would need to disable fastset and use full modeset instead.
v2: Fix C10 error on PLL comparison (BAT)
Use memcmp instead of fixed loops for pll config
comparison (Jani)
Clean up and use intel_cx0pll_dump_hw_state() to dump
pll information (Jani)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 77 +--
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
drivers/gpu/drm/i915/display/intel_display.c | 33
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
4 files changed, 109 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index c9e5bb6ecfd7..41f684c970dc 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2038,6 +2038,7 @@ static int intel_c10pll_calc_state(struct
intel_crtc_state *crtc_state,
if (crtc_state->port_clock == tables[i]->clock) {
crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i];
intel_c10pll_update_pll(crtc_state, encoder);
+ crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
return 0;
}
@@ -2105,8 +2106,8 @@ static void intel_c10_pll_program(struct drm_i915_private
*i915,
MB_WRITE_COMMITTED);
}
-void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
- const struct intel_c10pll_state *hw_state)
+static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
+ const struct intel_c10pll_state
*hw_state)
{
bool fracen;
int i;
@@ -2277,6 +2278,7 @@ static int intel_c20pll_calc_state(struct
intel_crtc_state *crtc_state,
for (i = 0; tables[i]; i++) {
if (crtc_state->port_clock == tables[i]->clock) {
crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i];
+ crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
return 0;
}
}
@@ -2410,8 +2412,8 @@ static void intel_c20pll_readout_hw_state(struct
intel_encoder *encoder,
intel_cx0_phy_transaction_end(encoder, wakeref);
}
-void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
- const struct intel_c20pll_state *hw_state)
+static void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
+ const struct intel_c20pll_state
*hw_state)
{
int i;
@@ -2430,6 +2432,15 @@ void intel_c20pll_dump_hw_state(struct drm_i915_private
*i915,
}
}
+void intel_cx0pll_dump_hw_state(struct drm_i915_private *i915,
+ const struct intel_cx0pll_state *hw_state)
+{
+ if (hw_state->use_c10)
+ intel_c10pll_dump_hw_state(i915, &hw_state->c10);
+ else
+ intel_c20pll_dump_hw_state(i915, &hw_state->c20);
+}
+
static u8 intel_c20_get_dp_rate(u32 clock)
{
switch (clock) {
@@ -3266,10 +3277,64 @@ static void intel_c10pll_state_verify(const struct
intel_crtc_state *state,
void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
struct intel_cx0pll_state *pll_state)
{
- if (intel_encoder_is_c10phy(encoder))
+ pll_state->use_c10 = false;
+
+ if (intel_encoder_is_c10phy(encoder)) {
intel_c10pll_readout_hw_state(encoder, &pll_state->c10);
- else
+ pll_state->use_c10 = true;
+ } else {
intel_c20pll_readout_hw_state(encoder, &pll_state->c20);
+ }
+}
+
+static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a,
+const struct intel_c10pll_state *b)
+{
+ if (a->tx != b->tx)
+ return false;
+
+ if (a->cmn != b->cmn)
+ return false;
+
+ if (memcmp(&a->pll, &b->pll, sizeof(a->pll)) != 0)
+ return false;
+
+ return true;
+}
+
+static bool mtl_compare_hw_state_c20(const struct intel_c20pll_state *a,
+const struct intel_c20pll_state *b)
+{
+ if (memcmp(&a->tx, &b->tx, sizeof(a->tx)) != 0)
+ return false;
+
+ if (memcmp(&a->cmn, &b->cmn, sizeof(a->cmn)) != 0)
+ return false;
+
+ if (a->tx[0] & C20_PHY_USE_MPLLB) {
+ if (memcmp(&a->mpllb, &b->mpllb, sizeof(a->mpllb)) != 0)
+ return false;
+ } else {
+ if (memcmp(&a->mplla, &b->mplla, sizeof(a->mplla)) != 0)
+
[PATCH v2 1/2] drm/i915/display: Revert "drm/i915/display: Skip C10 state verification in case of fastset"
This reverts commit a1d91c6e989d0e66b89aa911f2cd459d7bdebbe5.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1b1ebafa49e8..c9e5bb6ecfd7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3243,9 +3243,6 @@ static void intel_c10pll_state_verify(const struct
intel_crtc_state *state,
const struct intel_c10pll_state *mpllb_sw_state =
&state->dpll_hw_state.cx0pll.c10;
int i;
- if (intel_crtc_needs_fastset(state))
- return;
-
for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {
u8 expected = mpllb_sw_state->pll[i];
--
2.34.1
[PATCH v2 0/2] drm/i915/display: Add comparison for pipe config for MTL+ >
Currently, we may bump into pll mismatch errors during the state verification stage. This happens when we try to use fastset instead of full modeset. Hence, we would need to add a check for pipe configuration to ensure that the sw and the hw configuration will match. In case of hw and sw mismatch, we would need to disable fastset and use full modeset instead. However, first we need to revert the patch that disables fastset for C10. v2: Fix C10 error on PLL comparison (BAT) Use memcmp instead of fixed loops for pll config comparison (Jani) Clean up and use intel_cx0pll_dump_hw_state() to dump pll information (Jani) Signed-off-by: Mika Kahola Mika Kahola (2): drm/i915/display: Revert "drm/i915/display: Skip C10 state verification in case of fastset" drm/i915/display: Add compare config for MTL+ platforms drivers/gpu/drm/i915/display/intel_cx0_phy.c | 80 --- drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +- drivers/gpu/drm/i915/display/intel_display.c | 33 drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + 4 files changed, 109 insertions(+), 13 deletions(-) -- 2.34.1
Re: [PATCH] drm/i915/dpt: Make DPT object unshrinkable
On Thu, May 23, 2024 at 02:14:56PM +0100, Tvrtko Ursulin wrote:
>
> On 23/05/2024 13:24, Ville Syrjälä wrote:
> > On Thu, May 23, 2024 at 01:07:24PM +0100, Tvrtko Ursulin wrote:
> >>
> >> On 23/05/2024 12:19, Ville Syrjälä wrote:
> >>> On Thu, May 23, 2024 at 09:25:45AM +0100, Tvrtko Ursulin wrote:
>
> On 22/05/2024 16:29, Vidya Srinivas wrote:
> > In some scenarios, the DPT object gets shrunk but
> > the actual framebuffer did not and thus its still
> > there on the DPT's vm->bound_list. Then it tries to
> > rewrite the PTEs via a stale CPU mapping. This causes panic.
> >
> > Suggested-by: Ville Syrjala
> > Cc: sta...@vger.kernel.org
> > Fixes: 0dc987b699ce ("drm/i915/display: Add smem fallback allocation
> > for dpt")
> > Signed-off-by: Vidya Srinivas
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > index 3560a062d287..e6b485fc54d4 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > @@ -284,7 +284,8 @@ bool i915_gem_object_has_iomem(const struct
> > drm_i915_gem_object *obj);
> > static inline bool
> > i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
> > {
> > - return i915_gem_object_type_has(obj,
> > I915_GEM_OBJECT_IS_SHRINKABLE);
> > + return i915_gem_object_type_has(obj,
> > I915_GEM_OBJECT_IS_SHRINKABLE) &&
> > + !obj->is_dpt;
>
> Is there a reason i915_gem_object_make_unshrinkable() cannot be used to
> mark the object at a suitable place?
> >>>
> >>> Do you have a suitable place in mind?
> >>> i915_gem_object_make_unshrinkable() contains some magic
> >>> ingredients so doesn't look like it can be called willy
> >>> nilly.
> >>
> >> After it is created in intel_dpt_create?
> >>
> >> I don't see that helper couldn't be called. It is called from madvise
> >> and tiling for instance without any apparent special considerations.
> >
> > Did you actually read through i915_gem_object_make_unshrinkable()?
>
> Briefly, and also looked around how it is used. I don't immediately
> understand which part concerns you and it is also quite possible I am
> missing something.
The shrink_pin magic says you can't use this willy nilly.
>
> But see for example how it is used in intel_context.c+intel_lrc.c to
> protect the context state object from the shrinker while it is in use by
> the GPU. It does not appear any black magic is required.
>
> Question also is does that kind of lifetime aligns with the DPT use case.
>
> >> Also, there is no mention of this angle in the commit message so I
> >> assumed it wasn't considered. If it was, then it should have been
> >> mentioned why hacky solution was chosen instead...
> >
> > I suppose.
> >
> >>
> >>> Anyways, looks like I forgot to reply that I already pushed this
> >>> with this extra comment added:
> >>> /* TODO: make DPT shrinkable when it has no bound vmas */
> >>
> >> ... becuase IMO the special case is quite ugly and out of place. :(
> >
> > Yeah, not the nicest. But there's already a is_dpt check in the
> > i915_gem_object_is_framebuffer() right next door, so it's not
> > *that* out of place.
>
> I also see who added that one! ;)
>
> > Another option maybe could be to manually clear
> > I915_GEM_OBJECT_IS_SHRINKABLE but I don't think that is
> > supposed to be mutable, so might also have other issues.
> > So a more proper solution with that approach would perhaps
> > need some kind of gem_create_shmem_unshrinkable() function.
> >
> >>
> >> I don't remember from the top of my head how DPT magic works but if
> >> shrinker protection needs to be tied with VMAs there is also
> >> i915_make_make(un)shrinkable to try.
> >
> > I presume you mistyped something there.
>
> Oops - i915_vma_make_(un)shrinkable.
That just calls the obj version of the function.
>
> Anyway, I think it is worth giving it a try if the DPT lifetimes makes
> it possible.
>
> Regards,
>
> Tvrtko
--
Ville Syrjälä
Intel
Re: [PATCH v2 07/21] drm/i915/dp: Recheck link state after modeset
On Thu, May 23, 2024 at 04:30:18PM +0300, Ville Syrjälä wrote:
> On Mon, May 20, 2024 at 09:58:05PM +0300, Imre Deak wrote:
> > Recheck the link state after a passing link training, with a 2 sec delay
> > to account for cases where the link goes bad following the link training
> > and the sink doesn't report this via an HPD IRQ.
> >
> > The delayed work added here will be also used by a later patch after a
> > failed link training to try to retrain the link with unchanged link
> > params before reducing the link params.
> >
> > v2: Don't flush an uninitialized delayed work (on HDMI-only DDI ports).
> > v3: Add the work to intel_digital_port instead of intel_dp.
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/g4x_dp.c | 7
> > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++
> > drivers/gpu/drm/i915/display/intel_ddi.h | 4 +++
> > .../drm/i915/display/intel_display_types.h| 3 ++
> > drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> > .../drm/i915/display/intel_dp_link_training.c | 12 +--
> > 6 files changed, 58 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> > b/drivers/gpu/drm/i915/display/g4x_dp.c
> > index 06ec04e667e32..4363e32a834df 100644
> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> > @@ -20,6 +20,7 @@
> > #include "intel_dp_aux.h"
> > #include "intel_dp_link_training.h"
> > #include "intel_dpio_phy.h"
> > +#include "intel_ddi.h"
> > #include "intel_fifo_underrun.h"
> > #include "intel_hdmi.h"
> > #include "intel_hotplug.h"
> > @@ -1241,6 +1242,10 @@ static bool ilk_digital_port_connected(struct
> > intel_encoder *encoder)
> >
> > static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
> > {
> > + struct intel_digital_port *dig_port =
> > enc_to_dig_port(to_intel_encoder(encoder));
> > +
> > + intel_ddi_flush_link_check_work(dig_port);
> > +
> > intel_dp_encoder_flush_work(encoder);
> >
> > drm_encoder_cleanup(encoder);
> > @@ -1309,6 +1314,8 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
> >
> > dig_port->aux_ch = AUX_CH_NONE;
> >
> > + intel_ddi_init_link_check_work(dig_port);
>
> Using "ddi" for pre-ddi platforms is confusing. The implementation
> is also in intel_ddi.c for some reason.
Yes. It's a generic encoder or digital port functionality, neither of
which have its own file. How about moving them to intel_display.c and
the intel_display_link_{init_work, queue_work, flush_work, work_fn}
names?
> > +
> > intel_connector = intel_connector_alloc();
> > if (!intel_connector)
> > goto err_connector_alloc;
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 170ba01786cf8..86358ec27e685 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4360,6 +4360,7 @@ static void intel_ddi_encoder_destroy(struct
> > drm_encoder *encoder)
> > struct drm_i915_private *i915 = to_i915(encoder->dev);
> > struct intel_digital_port *dig_port =
> > enc_to_dig_port(to_intel_encoder(encoder));
> >
> > + intel_ddi_flush_link_check_work(dig_port);
> > intel_dp_encoder_flush_work(encoder);
> > if (intel_encoder_is_tc(&dig_port->base))
> > intel_tc_port_cleanup(dig_port);
> > @@ -4441,6 +4442,37 @@ intel_ddi_init_dp_connector(struct
> > intel_digital_port *dig_port)
> > return connector;
> > }
> >
> > +static void intel_ddi_link_check_work_fn(struct work_struct *work)
> > +{
> > + struct intel_digital_port *dig_port =
> > + container_of(work, typeof(*dig_port), check_link_work.work);
> > + struct intel_encoder *encoder = &dig_port->base;
> > + struct drm_modeset_acquire_ctx ctx;
> > + int ret;
> > +
> > + intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
> > + if (dig_port->dp.attached_connector)
> > + ret = intel_dp_retrain_link(encoder, &ctx);
> > +}
> > +
> > +void intel_ddi_init_link_check_work(struct intel_digital_port *dig_port)
> > +{
> > + INIT_DELAYED_WORK(&dig_port->check_link_work,
> > intel_ddi_link_check_work_fn);
> > +}
> > +
> > +void intel_ddi_flush_link_check_work(struct intel_digital_port *dig_port)
> > +{
> > + cancel_delayed_work_sync(&dig_port->check_link_work);
> > +}
> > +
> > +void intel_ddi_queue_link_check(struct intel_digital_port *dig_port, int
> > delay_ms)
> > +{
> > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > +
> > + mod_delayed_work(i915->unordered_wq,
> > +&dig_port->check_link_work,
> > msecs_to_jiffies(delay_ms));
> > +}
> > +
> > static int intel_hdmi_reset_link(struct intel_encoder *encoder,
> > struct drm_modeset_acquire_ctx *ctx)
> > {
> > @@ -4911,6 +4943,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> >
> >
[PATCH 2/3] drm/xe: drop redundant W=1 warnings from Makefile
Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
across the subsystem"), most of the extra warnings in the driver
Makefile are redundant. Remove them.
Note that -Wmissing-declarations and -Wmissing-prototypes are always
enabled by default in scripts/Makefile.extrawarn.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/Makefile | 25 +
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index c9f067b8f54d..f4366cb958be 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -3,31 +3,8 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-# Unconditionally enable W=1 warnings locally
-# --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn
-subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
-subdir-ccflags-y += -Wmissing-declarations
-subdir-ccflags-y += $(call cc-option, -Wrestrict)
-subdir-ccflags-y += -Wmissing-format-attribute
-subdir-ccflags-y += -Wmissing-prototypes
-subdir-ccflags-y += -Wold-style-definition
-subdir-ccflags-y += -Wmissing-include-dirs
-subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
-subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
-subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned)
-subdir-ccflags-y += $(call cc-option, -Wformat-overflow)
+# Enable W=1 warnings not enabled in drm subsystem Makefile
subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
-subdir-ccflags-y += $(call cc-option, -Wstringop-truncation)
-# The following turn off the warnings enabled by -Wextra
-ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),)
-subdir-ccflags-y += -Wno-missing-field-initializers
-subdir-ccflags-y += -Wno-type-limits
-subdir-ccflags-y += -Wno-shift-negative-value
-endif
-ifeq ($(findstring 3, $(KBUILD_EXTRA_WARN)),)
-subdir-ccflags-y += -Wno-sign-compare
-endif
-# --- end copy-paste
# Enable -Werror in CI and development
subdir-ccflags-$(CONFIG_DRM_XE_WERROR) += -Werror
--
2.39.2
[PATCH 3/3] drm/amdgpu: drop redundant W=1 warnings from Makefile
Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
across the subsystem"), most of the extra warnings in the driver
Makefile are redundant. Remove them.
Note that -Wmissing-declarations and -Wmissing-prototypes are always
enabled by default in scripts/Makefile.extrawarn.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/amd/amdgpu/Makefile | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 1f6b56ec99f6..9508d0b5708e 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -39,23 +39,7 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \
-I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \
-I$(FULL_AMD_PATH)/amdkfd
-subdir-ccflags-y := -Wextra
-subdir-ccflags-y += -Wunused
-subdir-ccflags-y += -Wmissing-prototypes
-subdir-ccflags-y += -Wmissing-declarations
-subdir-ccflags-y += -Wmissing-include-dirs
-subdir-ccflags-y += -Wold-style-definition
-subdir-ccflags-y += -Wmissing-format-attribute
-# Need this to avoid recursive variable evaluation issues
-cond-flags := $(call cc-option, -Wunused-but-set-variable) \
- $(call cc-option, -Wunused-const-variable) \
- $(call cc-option, -Wstringop-truncation) \
- $(call cc-option, -Wpacked-not-aligned)
-subdir-ccflags-y += $(cond-flags)
-subdir-ccflags-y += -Wno-unused-parameter
-subdir-ccflags-y += -Wno-type-limits
-subdir-ccflags-y += -Wno-sign-compare
-subdir-ccflags-y += -Wno-missing-field-initializers
+# Locally disable W=1 warnings enabled in drm subsystem Makefile
subdir-ccflags-y += -Wno-override-init
subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror
--
2.39.2
[PATCH 1/3] drm/i915: drop redundant W=1 warnings from Makefile
Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default
across the subsystem"), most of the extra warnings in the driver
Makefile are redundant. Remove them.
Note that -Wmissing-declarations and -Wmissing-prototypes are always
enabled by default in scripts/Makefile.extrawarn.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 25 +
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7cad944b825c..a70d95a8fd7a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -3,31 +3,8 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-# Unconditionally enable W=1 warnings locally
-# --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn
-subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
-subdir-ccflags-y += -Wmissing-declarations
-subdir-ccflags-y += $(call cc-option, -Wrestrict)
-subdir-ccflags-y += -Wmissing-format-attribute
-subdir-ccflags-y += -Wmissing-prototypes
-subdir-ccflags-y += -Wold-style-definition
-subdir-ccflags-y += -Wmissing-include-dirs
-subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable)
-subdir-ccflags-y += $(call cc-option, -Wunused-const-variable)
-subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned)
-subdir-ccflags-y += $(call cc-option, -Wformat-overflow)
+# Enable W=1 warnings not enabled in drm subsystem Makefile
subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
-subdir-ccflags-y += $(call cc-option, -Wstringop-truncation)
-# The following turn off the warnings enabled by -Wextra
-ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),)
-subdir-ccflags-y += -Wno-missing-field-initializers
-subdir-ccflags-y += -Wno-type-limits
-subdir-ccflags-y += -Wno-shift-negative-value
-endif
-ifeq ($(findstring 3, $(KBUILD_EXTRA_WARN)),)
-subdir-ccflags-y += -Wno-sign-compare
-endif
-# --- end copy-paste
# Enable -Werror in CI and development
subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
--
2.39.2
[PATCH 0/3] amd, i915, xe: drop redundant warnings from driver makefiles
I'm sending these together, as they're related, and almost identical, but I expect them to be merged individually to each driver. BR, Jani. Jani Nikula (3): drm/i915: drop redundant W=1 warnings from Makefile drm/xe: drop redundant W=1 warnings from Makefile drm/amdgpu: drop redundant W=1 warnings from Makefile drivers/gpu/drm/amd/amdgpu/Makefile | 18 +- drivers/gpu/drm/i915/Makefile | 25 + drivers/gpu/drm/xe/Makefile | 25 + 3 files changed, 3 insertions(+), 65 deletions(-) -- 2.39.2
Re: [PATCH v2 07/21] drm/i915/dp: Recheck link state after modeset
On Mon, May 20, 2024 at 09:58:05PM +0300, Imre Deak wrote:
> Recheck the link state after a passing link training, with a 2 sec delay
> to account for cases where the link goes bad following the link training
> and the sink doesn't report this via an HPD IRQ.
>
> The delayed work added here will be also used by a later patch after a
> failed link training to try to retrain the link with unchanged link
> params before reducing the link params.
>
> v2: Don't flush an uninitialized delayed work (on HDMI-only DDI ports).
> v3: Add the work to intel_digital_port instead of intel_dp.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/g4x_dp.c | 7
> drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++
> drivers/gpu/drm/i915/display/intel_ddi.h | 4 +++
> .../drm/i915/display/intel_display_types.h| 3 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> .../drm/i915/display/intel_dp_link_training.c | 12 +--
> 6 files changed, 58 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 06ec04e667e32..4363e32a834df 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -20,6 +20,7 @@
> #include "intel_dp_aux.h"
> #include "intel_dp_link_training.h"
> #include "intel_dpio_phy.h"
> +#include "intel_ddi.h"
> #include "intel_fifo_underrun.h"
> #include "intel_hdmi.h"
> #include "intel_hotplug.h"
> @@ -1241,6 +1242,10 @@ static bool ilk_digital_port_connected(struct
> intel_encoder *encoder)
>
> static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
> {
> + struct intel_digital_port *dig_port =
> enc_to_dig_port(to_intel_encoder(encoder));
> +
> + intel_ddi_flush_link_check_work(dig_port);
> +
> intel_dp_encoder_flush_work(encoder);
>
> drm_encoder_cleanup(encoder);
> @@ -1309,6 +1314,8 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
>
> dig_port->aux_ch = AUX_CH_NONE;
>
> + intel_ddi_init_link_check_work(dig_port);
Using "ddi" for pre-ddi platforms is confusing. The implementation
is also in intel_ddi.c for some reason.
> +
> intel_connector = intel_connector_alloc();
> if (!intel_connector)
> goto err_connector_alloc;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 170ba01786cf8..86358ec27e685 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4360,6 +4360,7 @@ static void intel_ddi_encoder_destroy(struct
> drm_encoder *encoder)
> struct drm_i915_private *i915 = to_i915(encoder->dev);
> struct intel_digital_port *dig_port =
> enc_to_dig_port(to_intel_encoder(encoder));
>
> + intel_ddi_flush_link_check_work(dig_port);
> intel_dp_encoder_flush_work(encoder);
> if (intel_encoder_is_tc(&dig_port->base))
> intel_tc_port_cleanup(dig_port);
> @@ -4441,6 +4442,37 @@ intel_ddi_init_dp_connector(struct intel_digital_port
> *dig_port)
> return connector;
> }
>
> +static void intel_ddi_link_check_work_fn(struct work_struct *work)
> +{
> + struct intel_digital_port *dig_port =
> + container_of(work, typeof(*dig_port), check_link_work.work);
> + struct intel_encoder *encoder = &dig_port->base;
> + struct drm_modeset_acquire_ctx ctx;
> + int ret;
> +
> + intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
> + if (dig_port->dp.attached_connector)
> + ret = intel_dp_retrain_link(encoder, &ctx);
> +}
> +
> +void intel_ddi_init_link_check_work(struct intel_digital_port *dig_port)
> +{
> + INIT_DELAYED_WORK(&dig_port->check_link_work,
> intel_ddi_link_check_work_fn);
> +}
> +
> +void intel_ddi_flush_link_check_work(struct intel_digital_port *dig_port)
> +{
> + cancel_delayed_work_sync(&dig_port->check_link_work);
> +}
> +
> +void intel_ddi_queue_link_check(struct intel_digital_port *dig_port, int
> delay_ms)
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +
> + mod_delayed_work(i915->unordered_wq,
> + &dig_port->check_link_work,
> msecs_to_jiffies(delay_ms));
> +}
> +
> static int intel_hdmi_reset_link(struct intel_encoder *encoder,
>struct drm_modeset_acquire_ctx *ctx)
> {
> @@ -4911,6 +4943,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
>
> dig_port->aux_ch = AUX_CH_NONE;
>
> + intel_ddi_init_link_check_work(dig_port);
> +
> encoder = &dig_port->base;
> encoder->devdata = devdata;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
> b/drivers/gpu/drm/i915/display/intel_ddi.h
> index 434de7196875a..b67714483f3cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -15,6 +15,7 @@ struct intel_bios_encode
Re: [PATCH v2 07/21] drm/i915/dp: Recheck link state after modeset
On Thu, May 23, 2024 at 04:23:44PM +0300, Ville Syrjälä wrote:
> On Wed, May 22, 2024 at 04:38:54PM +0300, Imre Deak wrote:
> > On Mon, May 20, 2024 at 09:58:05PM +0300, Imre Deak wrote:
> > > [...]
> > > +static void intel_ddi_link_check_work_fn(struct work_struct *work)
> > > +{
> > > + struct intel_digital_port *dig_port =
> > > + container_of(work, typeof(*dig_port), check_link_work.work);
> > > + struct intel_encoder *encoder = &dig_port->base;
> > > + struct drm_modeset_acquire_ctx ctx;
> > > + int ret;
> > > +
> > > + intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
> > > + if (dig_port->dp.attached_connector)
> > > + ret = intel_dp_retrain_link(encoder, &ctx);
> >
> > ret should not be let here uninited making the loop spin forever. This
> > can't actually happen since the work won't get schedule w/o
> > dp.attached_connector, but the above check should be also just an assert
> > at this point (at least until handling HDMI is also added).
>
> Hmm. Why are we actually initializing ret=-EDEADLK in
> _intel_modeset_lock_begin()?
answer: so that _drm_modeset_lock_loop() actually works
>
> >
> > > +}
> > > +
> > > +void intel_ddi_init_link_check_work(struct intel_digital_port *dig_port)
> > > +{
> > > + INIT_DELAYED_WORK(&dig_port->check_link_work,
> > > intel_ddi_link_check_work_fn);
> > > +}
> > > +
> > > +void intel_ddi_flush_link_check_work(struct intel_digital_port *dig_port)
> > > +{
> > > + cancel_delayed_work_sync(&dig_port->check_link_work);
> > > +}
> > > +
> > > +void intel_ddi_queue_link_check(struct intel_digital_port *dig_port, int
> > > delay_ms)
> > > +{
> > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > +
> > > + mod_delayed_work(i915->unordered_wq,
> > > + &dig_port->check_link_work,
> > > msecs_to_jiffies(delay_ms));
> > > +}
> > > +
> > > static int intel_hdmi_reset_link(struct intel_encoder *encoder,
> > >struct drm_modeset_acquire_ctx *ctx)
> > > {
> > > @@ -4911,6 +4943,8 @@ void intel_ddi_init(struct drm_i915_private
> > > *dev_priv,
> > >
> > > dig_port->aux_ch = AUX_CH_NONE;
> > >
> > > + intel_ddi_init_link_check_work(dig_port);
> > > +
> > > encoder = &dig_port->base;
> > > encoder->devdata = devdata;
> > >
>
> --
> Ville Syrjälä
> Intel
--
Ville Syrjälä
Intel
Re: [PATCH v2 06/21] drm/i915/dp: Use a commit modeset for link retraining MST links
On Thu, May 23, 2024 at 03:58:30PM +0300, Ville Syrjälä wrote:
> On Mon, May 20, 2024 at 09:58:04PM +0300, Imre Deak wrote:
> > Instead of direct calls to the link train functions, retrain the link
> > via a commit modeset. The direct call means that the output port will be
> > disabled/re-enabled while the rest of the pipeline (transcoder) is
> > active, which doesn't seem to work on MST at least. It leads to
> > underruns and black screen, presumedly because the transcoder is not
> > disabled/re-enabled along the port.
> >
> > Leave switching to a commit modeset on SST for a later patchset, as that
> > seems to work ok currently (though better to using a commit there too,
> > due to the suppressed underruns).
> >
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 25 +++--
> > 1 file changed, 19 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 81e620dd33bb7..120f7b420807b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5147,6 +5147,7 @@ int intel_dp_retrain_link(struct intel_encoder
> > *encoder,
> > struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > struct intel_crtc *crtc;
> > u8 pipe_mask;
> > + bool mst_output = false;
>
> nit: maybe move that up one line to maintain a bit more of a steady slope
Ok.
> > int ret;
> >
> > if (!intel_dp_is_connected(intel_dp))
> > @@ -5177,6 +5178,11 @@ int intel_dp_retrain_link(struct intel_encoder
> > *encoder,
> > const struct intel_crtc_state *crtc_state =
> > to_intel_crtc_state(crtc->base.state);
> >
> > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
> > + mst_output = true;
> > + break;
> > + }
>
> I was pondering if we need a bit more care to make sure all
> the pipes agree, but I suppose if that wasn't the case
> check_digital_port_conflicts() would have a failed at its
> job. So this seems fine.
Yes, mixed SST/MST CRTCs connected to the same encoder is what you
mean I guess. It would have caused a failure elsewhere or make the
commit added here fail during atomic check.
> Reviewed-by: Ville Syrjälä
>
> > +
> > /* Suppress underruns caused by re-training */
> > intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe,
> > false);
> > if (crtc_state->has_pch_encoder)
> > @@ -5184,16 +5190,23 @@ int intel_dp_retrain_link(struct intel_encoder
> > *encoder,
> >
> > intel_crtc_pch_transcoder(crtc), false);
> > }
> >
> > + /* TODO: use a modeset for SST as well. */
> > + if (mst_output) {
> > + ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx);
> > +
> > + if (ret && ret != -EDEADLK)
> > + drm_dbg_kms(&dev_priv->drm,
> > + "[ENCODER:%d:%s] link retraining failed:
> > %pe\n",
> > + encoder->base.base.id, encoder->base.name,
> > + ERR_PTR(ret));
> > +
> > + return ret;
> > + }
> > +
> > for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
> > const struct intel_crtc_state *crtc_state =
> > to_intel_crtc_state(crtc->base.state);
> >
> > - /* retrain on the MST master transcoder */
> > - if (DISPLAY_VER(dev_priv) >= 12 &&
> > - intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
> > - !intel_dp_mst_is_master_trans(crtc_state))
> > - continue;
> > -
> > intel_dp_check_frl_training(intel_dp);
> > intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
> > intel_dp_start_link_train(intel_dp, crtc_state);
> > --
> > 2.43.3
>
> --
> Ville Syrjälä
> Intel
Re: [PATCH v2 07/21] drm/i915/dp: Recheck link state after modeset
On Wed, May 22, 2024 at 04:38:54PM +0300, Imre Deak wrote:
> On Mon, May 20, 2024 at 09:58:05PM +0300, Imre Deak wrote:
> > [...]
> > +static void intel_ddi_link_check_work_fn(struct work_struct *work)
> > +{
> > + struct intel_digital_port *dig_port =
> > + container_of(work, typeof(*dig_port), check_link_work.work);
> > + struct intel_encoder *encoder = &dig_port->base;
> > + struct drm_modeset_acquire_ctx ctx;
> > + int ret;
> > +
> > + intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
> > + if (dig_port->dp.attached_connector)
> > + ret = intel_dp_retrain_link(encoder, &ctx);
>
> ret should not be let here uninited making the loop spin forever. This
> can't actually happen since the work won't get schedule w/o
> dp.attached_connector, but the above check should be also just an assert
> at this point (at least until handling HDMI is also added).
Hmm. Why are we actually initializing ret=-EDEADLK in
_intel_modeset_lock_begin()?
>
> > +}
> > +
> > +void intel_ddi_init_link_check_work(struct intel_digital_port *dig_port)
> > +{
> > + INIT_DELAYED_WORK(&dig_port->check_link_work,
> > intel_ddi_link_check_work_fn);
> > +}
> > +
> > +void intel_ddi_flush_link_check_work(struct intel_digital_port *dig_port)
> > +{
> > + cancel_delayed_work_sync(&dig_port->check_link_work);
> > +}
> > +
> > +void intel_ddi_queue_link_check(struct intel_digital_port *dig_port, int
> > delay_ms)
> > +{
> > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > +
> > + mod_delayed_work(i915->unordered_wq,
> > +&dig_port->check_link_work,
> > msecs_to_jiffies(delay_ms));
> > +}
> > +
> > static int intel_hdmi_reset_link(struct intel_encoder *encoder,
> > struct drm_modeset_acquire_ctx *ctx)
> > {
> > @@ -4911,6 +4943,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> >
> > dig_port->aux_ch = AUX_CH_NONE;
> >
> > + intel_ddi_init_link_check_work(dig_port);
> > +
> > encoder = &dig_port->base;
> > encoder->devdata = devdata;
> >
--
Ville Syrjälä
Intel
Re: [PATCH 16/16] drm/i915: pass dev_priv explicitly to PIPEGCMAX
On Thu, 23 May 2024, Ville Syrjälä wrote: > On Thu, May 23, 2024 at 03:59:44PM +0300, Jani Nikula wrote: >> Avoid the implicit dev_priv local variable use, and pass dev_priv >> explicitly to the PIPEGCMAX register macro. >> >> Signed-off-by: Jani Nikula >> --- >> drivers/gpu/drm/i915/display/intel_color.c | 13 +++-- >> drivers/gpu/drm/i915/display/intel_color_regs.h | 6 +++--- >> 2 files changed, 10 insertions(+), 9 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_color.c >> b/drivers/gpu/drm/i915/display/intel_color.c >> index a83f41ee6834..da56d24eb933 100644 >> --- a/drivers/gpu/drm/i915/display/intel_color.c >> +++ b/drivers/gpu/drm/i915/display/intel_color.c >> @@ -1284,9 +1284,10 @@ static void i965_load_lut_10p6(struct intel_crtc >> *crtc, >>i965_lut_10p6_udw(&lut[i])); >> } >> >> -intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); >> -intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); >> -intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); >> +intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0), lut[i].red); >> +intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1), >> + lut[i].green); > > nit: the newline breaks the pattern in a somewhat ugly way It's all cocci's doing... sometimes it's smart, sometimes less so. > Series is > Reviewed-by: Ville Syrjälä Thanks! > >> +intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2), lut[i].blue); >> } >> >> static void i965_load_luts(const struct intel_crtc_state *crtc_state) >> @@ -3239,9 +3240,9 @@ static struct drm_property_blob >> *i965_read_lut_10p6(struct intel_crtc *crtc) >> i965_lut_10p6_pack(&lut[i], ldw, udw); >> } >> >> -lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >> PIPEGCMAX(pipe, 0))); >> -lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >> PIPEGCMAX(pipe, 1))); >> -lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >> PIPEGCMAX(pipe, 2))); >> +lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >> PIPEGCMAX(dev_priv, pipe, 0))); >> +lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >> PIPEGCMAX(dev_priv, pipe, 1))); >> +lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, >> PIPEGCMAX(dev_priv, pipe, 2))); >> >> return blob; >> } >> diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h >> b/drivers/gpu/drm/i915/display/intel_color_regs.h >> index 61c18b4a7fa5..8eb643cfead7 100644 >> --- a/drivers/gpu/drm/i915/display/intel_color_regs.h >> +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h >> @@ -37,9 +37,9 @@ >>(i) * 4) >> >> /* i965/g4x/vlv/chv */ >> -#define _PIPEAGCMAX 0x70010 >> -#define _PIPEBGCMAX 0x71010 >> -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + >> (i) * 4) /* u1.16 */ >> +#define _PIPEAGCMAX0x70010 >> +#define _PIPEBGCMAX0x71010 >> +#define PIPEGCMAX(dev_priv, pipe, i)_MMIO_PIPE2(dev_priv, pipe, >> _PIPEAGCMAX + (i) * 4) /* u1.16 */ >> >> /* ilk+ palette */ >> #define _LGC_PALETTE_A 0x4a000 >> -- >> 2.39.2 -- Jani Nikula, Intel
Re: [PATCH] drm/i915/dpt: Make DPT object unshrinkable
On 23/05/2024 13:24, Ville Syrjälä wrote:
On Thu, May 23, 2024 at 01:07:24PM +0100, Tvrtko Ursulin wrote:
On 23/05/2024 12:19, Ville Syrjälä wrote:
On Thu, May 23, 2024 at 09:25:45AM +0100, Tvrtko Ursulin wrote:
On 22/05/2024 16:29, Vidya Srinivas wrote:
In some scenarios, the DPT object gets shrunk but
the actual framebuffer did not and thus its still
there on the DPT's vm->bound_list. Then it tries to
rewrite the PTEs via a stale CPU mapping. This causes panic.
Suggested-by: Ville Syrjala
Cc: sta...@vger.kernel.org
Fixes: 0dc987b699ce ("drm/i915/display: Add smem fallback allocation for dpt")
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3560a062d287..e6b485fc54d4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -284,7 +284,8 @@ bool i915_gem_object_has_iomem(const struct
drm_i915_gem_object *obj);
static inline bool
i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
{
- return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE);
+ return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE) &&
+ !obj->is_dpt;
Is there a reason i915_gem_object_make_unshrinkable() cannot be used to
mark the object at a suitable place?
Do you have a suitable place in mind?
i915_gem_object_make_unshrinkable() contains some magic
ingredients so doesn't look like it can be called willy
nilly.
After it is created in intel_dpt_create?
I don't see that helper couldn't be called. It is called from madvise
and tiling for instance without any apparent special considerations.
Did you actually read through i915_gem_object_make_unshrinkable()?
Briefly, and also looked around how it is used. I don't immediately
understand which part concerns you and it is also quite possible I am
missing something.
But see for example how it is used in intel_context.c+intel_lrc.c to
protect the context state object from the shrinker while it is in use by
the GPU. It does not appear any black magic is required.
Question also is does that kind of lifetime aligns with the DPT use case.
Also, there is no mention of this angle in the commit message so I
assumed it wasn't considered. If it was, then it should have been
mentioned why hacky solution was chosen instead...
I suppose.
Anyways, looks like I forgot to reply that I already pushed this
with this extra comment added:
/* TODO: make DPT shrinkable when it has no bound vmas */
... becuase IMO the special case is quite ugly and out of place. :(
Yeah, not the nicest. But there's already a is_dpt check in the
i915_gem_object_is_framebuffer() right next door, so it's not
*that* out of place.
I also see who added that one! ;)
Another option maybe could be to manually clear
I915_GEM_OBJECT_IS_SHRINKABLE but I don't think that is
supposed to be mutable, so might also have other issues.
So a more proper solution with that approach would perhaps
need some kind of gem_create_shmem_unshrinkable() function.
I don't remember from the top of my head how DPT magic works but if
shrinker protection needs to be tied with VMAs there is also
i915_make_make(un)shrinkable to try.
I presume you mistyped something there.
Oops - i915_vma_make_(un)shrinkable.
Anyway, I think it is worth giving it a try if the DPT lifetimes makes
it possible.
Regards,
Tvrtko
Re: [PATCH 16/16] drm/i915: pass dev_priv explicitly to PIPEGCMAX
On Thu, May 23, 2024 at 03:59:44PM +0300, Jani Nikula wrote: > Avoid the implicit dev_priv local variable use, and pass dev_priv > explicitly to the PIPEGCMAX register macro. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_color.c | 13 +++-- > drivers/gpu/drm/i915/display/intel_color_regs.h | 6 +++--- > 2 files changed, 10 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > b/drivers/gpu/drm/i915/display/intel_color.c > index a83f41ee6834..da56d24eb933 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -1284,9 +1284,10 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc, > i965_lut_10p6_udw(&lut[i])); > } > > - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); > - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); > - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); > + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0), lut[i].red); > + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1), > + lut[i].green); nit: the newline breaks the pattern in a somewhat ugly way Series is Reviewed-by: Ville Syrjälä > + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2), lut[i].blue); > } > > static void i965_load_luts(const struct intel_crtc_state *crtc_state) > @@ -3239,9 +3240,9 @@ static struct drm_property_blob > *i965_read_lut_10p6(struct intel_crtc *crtc) > i965_lut_10p6_pack(&lut[i], ldw, udw); > } > > - lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, > PIPEGCMAX(pipe, 0))); > - lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, > PIPEGCMAX(pipe, 1))); > - lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, > PIPEGCMAX(pipe, 2))); > + lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, > PIPEGCMAX(dev_priv, pipe, 0))); > + lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, > PIPEGCMAX(dev_priv, pipe, 1))); > + lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, > PIPEGCMAX(dev_priv, pipe, 2))); > > return blob; > } > diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h > b/drivers/gpu/drm/i915/display/intel_color_regs.h > index 61c18b4a7fa5..8eb643cfead7 100644 > --- a/drivers/gpu/drm/i915/display/intel_color_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h > @@ -37,9 +37,9 @@ > (i) * 4) > > /* i965/g4x/vlv/chv */ > -#define _PIPEAGCMAX 0x70010 > -#define _PIPEBGCMAX 0x71010 > -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) > * 4) /* u1.16 */ > +#define _PIPEAGCMAX 0x70010 > +#define _PIPEBGCMAX 0x71010 > +#define PIPEGCMAX(dev_priv, pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX > + (i) * 4) /* u1.16 */ > > /* ilk+ palette */ > #define _LGC_PALETTE_A 0x4a000 > -- > 2.39.2 -- Ville Syrjälä Intel
Re: [RESEND 0/6] drm, nouveau/radeon/amdpgu: edid_blob_ptr cleanups
On Mon, 13 May 2024, Alex Deucher wrote: > On Mon, May 13, 2024 at 8:20 AM Jani Nikula wrote: >> >> On Fri, 10 May 2024, Alex Deucher wrote: >> > On Fri, May 10, 2024 at 11:17 AM Jani Nikula wrote: >> > Series is: >> > Acked-by: Alex Deucher >> >> Thanks, do you want to pick these up via your tree? And do you expect a >> proper R-b before merging? > > Feel free to take them via drm-misc if you'd prefer to land the whole > set together, otherwise, I can pick up the radeon/amdgpu patches. Thanks, merged everything to drm-misc-next. BR, Jani. -- Jani Nikula, Intel
[PATCH 14/16] drm/i915: pass dev_priv explicitly to PRIMSIZE
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PRIMSIZE register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 1cefcdd4f26a..82cb393a0a22 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -476,7 +476,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, PRIMPOS(dev_priv, i9xx_plane), PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); - intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), + intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane), PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 7f291b34f10a..8d45c879e74a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -94,8 +94,8 @@ #define PRIM_POS_X_MASK REG_GENMASK(15, 0) #define PRIM_POS_X(x)REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) -#define _PRIMSIZE_A0x60a0c -#define PRIMSIZE(plane)_MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) +#define _PRIMSIZE_A0x60a0c +#define PRIMSIZE(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) -- 2.39.2
[PATCH 06/16] drm/i915: pass dev_priv explicitly to DSPPOS
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPPOS register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 34760ecd5d34..b23135ed1a38 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -437,7 +437,7 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane, * generator but let's assume we still need to * program whatever is there. */ - intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), + intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane), DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 049114620d93..13a49550c456 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -53,7 +53,7 @@ #define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) #define _DSPAPOS 0x7018C /* pre-g4x */ -#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) +#define DSPPOS(dev_priv, plane)_MMIO_PIPE2(dev_priv, plane, _DSPAPOS) #define DISP_POS_Y_MASK REG_GENMASK(31, 16) #define DISP_POS_Y(y)REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) #define DISP_POS_X_MASK REG_GENMASK(15, 0) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 02c5dafc0c93..00dd2b647c83 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -168,7 +168,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPCNTR(dev_priv, PIPE_A)); MMIO_D(DSPADDR(dev_priv, PIPE_A)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_A)); - MMIO_D(DSPPOS(PIPE_A)); + MMIO_D(DSPPOS(dev_priv, PIPE_A)); MMIO_D(DSPSIZE(PIPE_A)); MMIO_D(DSPSURF(PIPE_A)); MMIO_D(DSPOFFSET(PIPE_A)); @@ -177,7 +177,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPCNTR(dev_priv, PIPE_B)); MMIO_D(DSPADDR(dev_priv, PIPE_B)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_B)); - MMIO_D(DSPPOS(PIPE_B)); + MMIO_D(DSPPOS(dev_priv, PIPE_B)); MMIO_D(DSPSIZE(PIPE_B)); MMIO_D(DSPSURF(PIPE_B)); MMIO_D(DSPOFFSET(PIPE_B)); @@ -186,7 +186,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPCNTR(dev_priv, PIPE_C)); MMIO_D(DSPADDR(dev_priv, PIPE_C)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_C)); - MMIO_D(DSPPOS(PIPE_C)); + MMIO_D(DSPPOS(dev_priv, PIPE_C)); MMIO_D(DSPSIZE(PIPE_C)); MMIO_D(DSPSURF(PIPE_C)); MMIO_D(DSPOFFSET(PIPE_C)); -- 2.39.2
[PATCH 05/16] drm/i915: pass dev_priv explicitly to DSPSTRIDE
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPSTRIDE register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++--
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++--
drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++---
5 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index ba76c952a656..34760ecd5d34 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -423,7 +423,7 @@ static void i9xx_plane_update_noarm(struct intel_plane
*plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
- intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane),
plane_state->view.color_plane[0].mapping_stride);
if (DISPLAY_VER(dev_priv) < 4) {
@@ -1055,7 +1055,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
- val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
+ val = intel_de_read(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane));
fb->pitches[0] = val & 0xffc0;
aligned_height = intel_fb_align_height(fb, 0, fb->height);
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index e222c0333d19..049114620d93 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -50,7 +50,7 @@
#define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPALINOFF)
#define _DSPASTRIDE0x70188
-#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASTRIDE)
+#define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASTRIDE)
#define _DSPAPOS 0x7018C /* pre-g4x */
#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAPOS)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 3b6529a6501b..7072d14d86cf 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1316,7 +1316,7 @@ static int gen8_decode_mi_display_flip(struct
parser_exec_state *s,
if (info->plane == PLANE_A) {
info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
- info->stride_reg = DSPSTRIDE(info->pipe);
+ info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
info->surf_reg = DSPSURF(info->pipe);
} else if (info->plane == PLANE_B) {
info->ctrl_reg = SPRCTL(info->pipe);
@@ -1382,7 +1382,7 @@ static int skl_decode_mi_display_flip(struct
parser_exec_state *s,
info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);
- info->stride_reg = DSPSTRIDE(info->pipe);
+ info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);
info->surf_reg = DSPSURF(info->pipe);
return 0;
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 48e3b6d8ed98..cf1cff3d1c4f 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -155,7 +155,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu,
int pipe,
{
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
- u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
+ u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(dev_priv, pipe)) &
stride_mask;
u32 stride = stride_reg;
if (GRAPHICS_VER(dev_priv) >= 9) {
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 944765fe22e7..02c5dafc0c93 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -167,7 +167,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x7009c));
MMIO_D(DSPCNTR(dev_priv, PIPE_A));
MMIO_D(DSPADDR(dev_priv, PIPE_A));
- MMIO_D(DSPSTRIDE(PIPE_A));
+ MMIO_D(DSPSTRIDE(dev_priv, PIPE_A));
MMIO_D(DSPPOS(PIPE_A));
MMIO_D(DSPSIZE(PIPE_A));
MMIO_D(DSPSURF(PIPE_A));
@@ -176,7 +176,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_B));
MMIO_D(DSPADDR(dev_priv, PIPE_B));
- MMIO_D(DSPSTRIDE(PIPE_B));
+ MM
[PATCH 13/16] drm/i915: pass dev_priv explicitly to PRIMPOS
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PRIMPOS register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 2026323d88ac..1cefcdd4f26a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -474,7 +474,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, int crtc_w = drm_rect_width(&plane_state->uapi.dst); int crtc_h = drm_rect_height(&plane_state->uapi.dst); - intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), + intel_de_write_fw(dev_priv, PRIMPOS(dev_priv, i9xx_plane), PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index f67c5a2bb6b9..7f291b34f10a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -87,8 +87,8 @@ #define DSPGAMC(dev_priv, plane, i)_MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ /* CHV pipe B primary plane */ -#define _PRIMPOS_A 0x60a08 -#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) +#define _PRIMPOS_A 0x60a08 +#define PRIMPOS(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) #define PRIM_POS_Y(y)REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) #define PRIM_POS_X_MASK REG_GENMASK(15, 0) -- 2.39.2
[PATCH 15/16] drm/i915: pass dev_priv explicitly to PRIMCNSTALPHA
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PRIMCNSTALPHA register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 3 ++-
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 82cb393a0a22..5c8778865156 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -478,7 +478,8 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x));
intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane),
PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w -
1));
- intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
+ intel_de_write_fw(dev_priv,
+ PRIMCNSTALPHA(dev_priv, i9xx_plane), 0);
}
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 8d45c879e74a..a2ba55fa2b30 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -101,8 +101,8 @@
#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
#define PRIM_WIDTH(w)REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
-#define _PRIMCNSTALPHA_A 0x60a10
-#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
+#define _PRIMCNSTALPHA_A 0x60a10
+#define PRIMCNSTALPHA(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane,
_PRIMCNSTALPHA_A)
#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
#define PRIM_CONST_ALPHA_MASKREG_GENMASK(7, 0)
#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK,
(alpha))
--
2.39.2
[PATCH 16/16] drm/i915: pass dev_priv explicitly to PIPEGCMAX
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPEGCMAX register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_color.c | 13 +++-- drivers/gpu/drm/i915/display/intel_color_regs.h | 6 +++--- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index a83f41ee6834..da56d24eb933 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1284,9 +1284,10 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc, i965_lut_10p6_udw(&lut[i])); } - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0), lut[i].red); + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1), + lut[i].green); + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2), lut[i].blue); } static void i965_load_luts(const struct intel_crtc_state *crtc_state) @@ -3239,9 +3240,9 @@ static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) i965_lut_10p6_pack(&lut[i], ldw, udw); } - lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 0))); - lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 1))); - lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 2))); + lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0))); + lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1))); + lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2))); return blob; } diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h index 61c18b4a7fa5..8eb643cfead7 100644 --- a/drivers/gpu/drm/i915/display/intel_color_regs.h +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h @@ -37,9 +37,9 @@ (i) * 4) /* i965/g4x/vlv/chv */ -#define _PIPEAGCMAX 0x70010 -#define _PIPEBGCMAX 0x71010 -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ +#define _PIPEAGCMAX 0x70010 +#define _PIPEBGCMAX 0x71010 +#define PIPEGCMAX(dev_priv, pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ /* ilk+ palette */ #define _LGC_PALETTE_A 0x4a000 -- 2.39.2
[PATCH 07/16] drm/i915: pass dev_priv explicitly to DSPSIZE
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPSIZE register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index b23135ed1a38..42175cb74d5d 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -439,7 +439,7 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane, */ intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane), DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); - intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), + intel_de_write_fw(dev_priv, DSPSIZE(dev_priv, i9xx_plane), DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); } } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 13a49550c456..5a1f45eceed4 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -60,7 +60,7 @@ #define DISP_POS_X(x)REG_FIELD_PREP(DISP_POS_X_MASK, (x)) #define _DSPASIZE 0x70190 /* pre-g4x */ -#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) +#define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) #define DISP_WIDTH_MASK REG_GENMASK(15, 0) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 00dd2b647c83..e047928c3ea0 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -169,7 +169,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPADDR(dev_priv, PIPE_A)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_A)); MMIO_D(DSPPOS(dev_priv, PIPE_A)); - MMIO_D(DSPSIZE(PIPE_A)); + MMIO_D(DSPSIZE(dev_priv, PIPE_A)); MMIO_D(DSPSURF(PIPE_A)); MMIO_D(DSPOFFSET(PIPE_A)); MMIO_D(DSPSURFLIVE(PIPE_A)); @@ -178,7 +178,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPADDR(dev_priv, PIPE_B)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_B)); MMIO_D(DSPPOS(dev_priv, PIPE_B)); - MMIO_D(DSPSIZE(PIPE_B)); + MMIO_D(DSPSIZE(dev_priv, PIPE_B)); MMIO_D(DSPSURF(PIPE_B)); MMIO_D(DSPOFFSET(PIPE_B)); MMIO_D(DSPSURFLIVE(PIPE_B)); @@ -187,7 +187,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPADDR(dev_priv, PIPE_C)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_C)); MMIO_D(DSPPOS(dev_priv, PIPE_C)); - MMIO_D(DSPSIZE(PIPE_C)); + MMIO_D(DSPSIZE(dev_priv, PIPE_C)); MMIO_D(DSPSURF(PIPE_C)); MMIO_D(DSPOFFSET(PIPE_C)); MMIO_D(DSPSURFLIVE(PIPE_C)); -- 2.39.2
[PATCH 10/16] drm/i915: pass dev_priv explicitly to DSPOFFSET
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPOFFSET register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 5 +++--
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++---
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 36225c2aa1c8..2026323d88ac 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -482,7 +482,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
}
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPOFFSET(dev_priv, i9xx_plane),
DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
} else if (DISPLAY_VER(dev_priv) >= 4) {
intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane),
@@ -1033,7 +1033,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
fb->format = drm_format_info(fourcc);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
+ offset = intel_de_read(dev_priv,
+ DSPOFFSET(dev_priv, i9xx_plane));
base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) &
DISP_ADDR_MASK;
} else if (DISPLAY_VER(dev_priv) >= 4) {
if (plane_config->tiling)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index baa3d348c77e..0930a76ccf3c 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -78,7 +78,7 @@
#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
#define _DSPAOFFSET0x701A4 /* hsw+ */
-#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAOFFSET)
+#define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAOFFSET)
#define _DSPASURFLIVE 0x701AC /* g4x+ */
#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASURFLIVE)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index a8be80bde2e7..50dfe1f81b99 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -171,7 +171,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPPOS(dev_priv, PIPE_A));
MMIO_D(DSPSIZE(dev_priv, PIPE_A));
MMIO_D(DSPSURF(dev_priv, PIPE_A));
- MMIO_D(DSPOFFSET(PIPE_A));
+ MMIO_D(DSPOFFSET(dev_priv, PIPE_A));
MMIO_D(DSPSURFLIVE(PIPE_A));
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_B));
@@ -180,7 +180,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPPOS(dev_priv, PIPE_B));
MMIO_D(DSPSIZE(dev_priv, PIPE_B));
MMIO_D(DSPSURF(dev_priv, PIPE_B));
- MMIO_D(DSPOFFSET(PIPE_B));
+ MMIO_D(DSPOFFSET(dev_priv, PIPE_B));
MMIO_D(DSPSURFLIVE(PIPE_B));
MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_C));
@@ -189,7 +189,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPPOS(dev_priv, PIPE_C));
MMIO_D(DSPSIZE(dev_priv, PIPE_C));
MMIO_D(DSPSURF(dev_priv, PIPE_C));
- MMIO_D(DSPOFFSET(PIPE_C));
+ MMIO_D(DSPOFFSET(dev_priv, PIPE_C));
MMIO_D(DSPSURFLIVE(PIPE_C));
MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY));
MMIO_D(SPRCTL(PIPE_A));
--
2.39.2
[PATCH 08/16] drm/i915: pass dev_priv explicitly to DSPSURF
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPSURF register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 12 ++--
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++--
drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c| 8
drivers/gpu/drm/i915/intel_clock_gating.c | 6 --
drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++---
8 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 42175cb74d5d..7adaf8cbd945 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -499,7 +499,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
if (DISPLAY_VER(dev_priv) >= 4)
- intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
else
intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane),
@@ -542,7 +542,7 @@ static void i9xx_plane_disable_arm(struct intel_plane
*plane,
intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
if (DISPLAY_VER(dev_priv) >= 4)
- intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
+ intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), 0);
else
intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0);
}
@@ -563,7 +563,7 @@ g4x_primary_async_flip(struct intel_plane *plane,
intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
- intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
}
@@ -1034,7 +1034,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
- base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) &
DISP_ADDR_MASK;
+ base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) &
DISP_ADDR_MASK;
} else if (DISPLAY_VER(dev_priv) >= 4) {
if (plane_config->tiling)
offset = intel_de_read(dev_priv,
@@ -1042,7 +1042,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
else
offset = intel_de_read(dev_priv,
DSPLINOFF(dev_priv, i9xx_plane));
- base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) &
DISP_ADDR_MASK;
+ base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) &
DISP_ADDR_MASK;
} else {
offset = 0;
base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane));
@@ -1094,7 +1094,7 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc
*crtc,
return false;
if (DISPLAY_VER(dev_priv) >= 4)
- intel_de_write(dev_priv, DSPSURF(i9xx_plane), base);
+ intel_de_write(dev_priv, DSPSURF(dev_priv, i9xx_plane), base);
else
intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base);
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 5a1f45eceed4..2771f2a7645b 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -67,7 +67,7 @@
#define DISP_WIDTH(w)REG_FIELD_PREP(DISP_WIDTH_MASK,
(w))
#define _DSPASURF 0x7019C /* i965+ */
-#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASURF)
+#define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASURF)
#define DISP_ADDR_MASK REG_GENMASK(31, 12)
#define _DSPATILEOFF 0x701A4 /* i965+ */
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index f46e01cad053..e9189a864f69 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -364,8 +364,8 @@ static void i965_fbc_nuke(struct intel_fbc *fbc)
enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
struct drm_i915_private *dev_priv = fbc->i915;
- intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
- intel_de_read_fw(dev_priv, D
[PATCH 12/16] drm/i915: pass dev_priv explicitly to DSPGAMC
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPGAMC register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 22a550c8b41a..f67c5a2bb6b9 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -84,7 +84,7 @@ #define DSPSURFLIVE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) #define _DSPAGAMC 0x701E0 /* pre-g4x */ -#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ +#define DSPGAMC(dev_priv, plane, i)_MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ /* CHV pipe B primary plane */ #define _PRIMPOS_A 0x60a08 -- 2.39.2
[PATCH 11/16] drm/i915: pass dev_priv explicitly to DSPSURFLIVE
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPSURFLIVE register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c| 4 ++--
drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++---
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 0930a76ccf3c..22a550c8b41a 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -81,7 +81,7 @@
#define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAOFFSET)
#define _DSPASURFLIVE 0x701AC /* g4x+ */
-#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASURFLIVE)
+#define DSPSURFLIVE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASURFLIVE)
#define _DSPAGAMC 0x701E0 /* pre-g4x */
#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane,
_DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index abcb8f0825e0..840fea160aa6 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1018,7 +1018,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu,
unsigned int offset,
int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
write_vreg(vgpu, offset, p_data, bytes);
- vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
+ vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu,
offset);
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
@@ -1061,7 +1061,7 @@ static int reg50080_mmio_write(struct intel_vgpu *vgpu,
write_vreg(vgpu, offset, p_data, bytes);
if (plane == PLANE_PRIMARY) {
- vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
+ vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) =
vgpu_vreg(vgpu, offset);
vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
} else {
vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 50dfe1f81b99..b4d5592b18df 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -172,7 +172,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSIZE(dev_priv, PIPE_A));
MMIO_D(DSPSURF(dev_priv, PIPE_A));
MMIO_D(DSPOFFSET(dev_priv, PIPE_A));
- MMIO_D(DSPSURFLIVE(PIPE_A));
+ MMIO_D(DSPSURFLIVE(dev_priv, PIPE_A));
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_B));
MMIO_D(DSPADDR(dev_priv, PIPE_B));
@@ -181,7 +181,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSIZE(dev_priv, PIPE_B));
MMIO_D(DSPSURF(dev_priv, PIPE_B));
MMIO_D(DSPOFFSET(dev_priv, PIPE_B));
- MMIO_D(DSPSURFLIVE(PIPE_B));
+ MMIO_D(DSPSURFLIVE(dev_priv, PIPE_B));
MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_C));
MMIO_D(DSPADDR(dev_priv, PIPE_C));
@@ -190,7 +190,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSIZE(dev_priv, PIPE_C));
MMIO_D(DSPSURF(dev_priv, PIPE_C));
MMIO_D(DSPOFFSET(dev_priv, PIPE_C));
- MMIO_D(DSPSURFLIVE(PIPE_C));
+ MMIO_D(DSPSURFLIVE(dev_priv, PIPE_C));
MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY));
MMIO_D(SPRCTL(PIPE_A));
MMIO_D(SPRLINOFF(PIPE_A));
--
2.39.2
[PATCH 09/16] drm/i915: pass dev_priv explicitly to DSPTILEOFF
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPTILEOFF register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++--
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 7adaf8cbd945..36225c2aa1c8 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -487,7 +487,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
} else if (DISPLAY_VER(dev_priv) >= 4) {
intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane),
linear_offset);
- intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPTILEOFF(dev_priv, i9xx_plane),
DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
}
@@ -1038,7 +1038,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
} else if (DISPLAY_VER(dev_priv) >= 4) {
if (plane_config->tiling)
offset = intel_de_read(dev_priv,
- DSPTILEOFF(i9xx_plane));
+ DSPTILEOFF(dev_priv,
i9xx_plane));
else
offset = intel_de_read(dev_priv,
DSPLINOFF(dev_priv, i9xx_plane));
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 2771f2a7645b..baa3d348c77e 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -71,7 +71,7 @@
#define DISP_ADDR_MASK REG_GENMASK(31, 12)
#define _DSPATILEOFF 0x701A4 /* i965+ */
-#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPATILEOFF)
+#define DSPTILEOFF(dev_priv, plane)_MMIO_PIPE2(dev_priv, plane,
_DSPATILEOFF)
#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 6c3a0f160bea..0afde865a7de 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -274,7 +274,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
_PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
plane->height += 1; /* raw height is one minus the real value */
- val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
+ val = vgpu_vreg_t(vgpu, DSPTILEOFF(dev_priv, pipe));
plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
_PRI_PLANE_X_OFF_SHIFT;
plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
--
2.39.2
[PATCH 04/16] drm/i915: pass dev_priv explicitly to DSPLINOFF
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPLINOFF register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++--
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 79280fe2662d..ba76c952a656 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -485,7 +485,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
} else if (DISPLAY_VER(dev_priv) >= 4) {
- intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane),
linear_offset);
intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
@@ -1041,7 +1041,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
DSPTILEOFF(i9xx_plane));
else
offset = intel_de_read(dev_priv,
- DSPLINOFF(i9xx_plane));
+ DSPLINOFF(dev_priv, i9xx_plane));
base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) &
DISP_ADDR_MASK;
} else {
offset = 0;
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index a68d7b228187..e222c0333d19 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -47,7 +47,7 @@
#define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAADDR)
#define _DSPALINOFF0x70184 /* i965+ */
-#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPALINOFF)
+#define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPALINOFF)
#define _DSPASTRIDE0x70188
#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPASTRIDE)
--
2.39.2
[PATCH 03/16] drm/i915: pass dev_priv explicitly to DSPADDR
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPADDR register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 8
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++---
4 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index ceb0a969357f..79280fe2662d 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -502,7 +502,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
else
- intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
}
@@ -544,7 +544,7 @@ static void i9xx_plane_disable_arm(struct intel_plane
*plane,
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
else
- intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
+ intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0);
}
static void
@@ -1045,7 +1045,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) &
DISP_ADDR_MASK;
} else {
offset = 0;
- base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
+ base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane));
}
plane_config->base = base;
@@ -1096,7 +1096,7 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc
*crtc,
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write(dev_priv, DSPSURF(i9xx_plane), base);
else
- intel_de_write(dev_priv, DSPADDR(i9xx_plane), base);
+ intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base);
return true;
}
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index d483569e4147..a68d7b228187 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -44,7 +44,7 @@
#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
#define _DSPAADDR 0x70184 /* pre-i965 */
-#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAADDR)
+#define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAADDR)
#define _DSPALINOFF0x70184 /* i965+ */
#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPALINOFF)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 680d7fc39503..f46e01cad053 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -327,8 +327,8 @@ static void i8xx_fbc_nuke(struct intel_fbc *fbc)
enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
struct drm_i915_private *dev_priv = fbc->i915;
- intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
- intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
+ intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane),
+ intel_de_read_fw(dev_priv, DSPADDR(dev_priv,
i9xx_plane)));
}
static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 909823d7ed1b..944765fe22e7 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -166,7 +166,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x70098));
MMIO_D(_MMIO(0x7009c));
MMIO_D(DSPCNTR(dev_priv, PIPE_A));
- MMIO_D(DSPADDR(PIPE_A));
+ MMIO_D(DSPADDR(dev_priv, PIPE_A));
MMIO_D(DSPSTRIDE(PIPE_A));
MMIO_D(DSPPOS(PIPE_A));
MMIO_D(DSPSIZE(PIPE_A));
@@ -175,7 +175,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSURFLIVE(PIPE_A));
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_B));
- MMIO_D(DSPADDR(PIPE_B));
+ MMIO_D(DSPADDR(dev_priv, PIPE_B));
MMIO_D(DSPSTRIDE(PIPE_B));
MMIO_D(DSPPOS(PIPE_B));
MMIO_D(DSPSIZE(PIPE_B));
@@ -184,7 +184,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSURFLIVE(PIPE_B));
MMIO_D(
[PATCH 02/16] drm/i915: pass dev_priv explicitly to DSPCNTR
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPCNTR register macro.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 10 +-
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/display/intel_color.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++--
drivers/gpu/drm/i915/gvt/display.c | 4 ++--
drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c| 2 +-
drivers/gpu/drm/i915/intel_clock_gating.c | 3 ++-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c| 6 +++---
10 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 4636523d7948..ceb0a969357f 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -496,7 +496,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
* disabled. Try to make the plane enable atomic by writing
* the control register just before the surface register.
*/
- intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+ intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
@@ -539,7 +539,7 @@ static void i9xx_plane_disable_arm(struct intel_plane
*plane,
*/
dspcntr = i9xx_plane_ctl_crtc(crtc_state);
- intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+ intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
@@ -561,7 +561,7 @@ g4x_primary_async_flip(struct intel_plane *plane,
if (async_flip)
dspcntr |= DISP_ASYNC_FLIP;
- intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+ intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
@@ -685,7 +685,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane
*plane,
if (!wakeref)
return false;
- val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
+ val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane));
ret = val & DISP_ENABLE;
@@ -1012,7 +1012,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
fb->dev = dev;
- val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
+ val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane));
if (DISPLAY_VER(dev_priv) >= 4) {
if (val & DISP_TILED) {
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 926da106f1a2..d483569e4147 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -12,7 +12,7 @@
#define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAADDR_VLV)
#define _DSPACNTR 0x70180
-#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPACNTR)
+#define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPACNTR)
#define DISP_ENABLE REG_BIT(31)
#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 82b155708422..a83f41ee6834 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1038,7 +1038,7 @@ static void i9xx_get_config(struct intel_crtc_state
*crtc_state)
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
u32 tmp;
- tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
+ tmp = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane));
if (tmp & DISP_PIPE_GAMMA_ENABLE)
crtc_state->gamma_enable = true;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1e8e2fd52cf6..58a4060f90b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8233,11 +8233,11 @@ void i830_disable_pipe(struct drm_i915_private
*dev_priv, enum pipe pipe)
pipe_name(pipe));
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_A)) &
DISP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(d
[PATCH 01/16] drm/i915: pass dev_priv explicitly to DSPADDR_VLV
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPADDR_VLV register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 1f05f9184cb2..4636523d7948 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -577,7 +577,7 @@ vlv_primary_async_flip(struct intel_plane *plane, u32 dspaddr_offset = plane_state->view.color_plane[0].offset; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane), + intel_de_write_fw(dev_priv, DSPADDR_VLV(dev_priv, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index d74a74d1f29a..926da106f1a2 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -9,7 +9,7 @@ #include "intel_display_reg_defs.h" #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ -#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) +#define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) #define _DSPACNTR 0x70180 #define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) -- 2.39.2
[PATCH 00/16] drm/i915: dev_priv fixes for i9xx_plane_regs.h/intel_color_regs.h
Pass dev_priv explicitly in i9xx_plane_regs.h/intel_color_regs.h. The main changes are scripted, with some manual indentation cleanups on top. BR, Jani. Jani Nikula (16): drm/i915: pass dev_priv explicitly to DSPADDR_VLV drm/i915: pass dev_priv explicitly to DSPCNTR drm/i915: pass dev_priv explicitly to DSPADDR drm/i915: pass dev_priv explicitly to DSPLINOFF drm/i915: pass dev_priv explicitly to DSPSTRIDE drm/i915: pass dev_priv explicitly to DSPPOS drm/i915: pass dev_priv explicitly to DSPSIZE drm/i915: pass dev_priv explicitly to DSPSURF drm/i915: pass dev_priv explicitly to DSPTILEOFF drm/i915: pass dev_priv explicitly to DSPOFFSET drm/i915: pass dev_priv explicitly to DSPSURFLIVE drm/i915: pass dev_priv explicitly to DSPGAMC drm/i915: pass dev_priv explicitly to PRIMPOS drm/i915: pass dev_priv explicitly to PRIMSIZE drm/i915: pass dev_priv explicitly to PRIMCNSTALPHA drm/i915: pass dev_priv explicitly to PIPEGCMAX drivers/gpu/drm/i915/display/i9xx_plane.c | 60 ++- .../gpu/drm/i915/display/i9xx_plane_regs.h| 36 +-- drivers/gpu/drm/i915/display/intel_color.c| 15 ++--- .../gpu/drm/i915/display/intel_color_regs.h | 6 +- drivers/gpu/drm/i915/display/intel_display.c | 6 +- drivers/gpu/drm/i915/display/intel_fbc.c | 8 +-- drivers/gpu/drm/i915/gvt/cmd_parser.c | 12 ++-- drivers/gpu/drm/i915/gvt/display.c| 4 +- drivers/gpu/drm/i915/gvt/fb_decoder.c | 8 +-- drivers/gpu/drm/i915/gvt/handlers.c | 14 ++--- drivers/gpu/drm/i915/intel_clock_gating.c | 9 ++- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 48 +++ 12 files changed, 116 insertions(+), 110 deletions(-) -- 2.39.2
Re: [PATCH v2 06/21] drm/i915/dp: Use a commit modeset for link retraining MST links
On Mon, May 20, 2024 at 09:58:04PM +0300, Imre Deak wrote:
> Instead of direct calls to the link train functions, retrain the link
> via a commit modeset. The direct call means that the output port will be
> disabled/re-enabled while the rest of the pipeline (transcoder) is
> active, which doesn't seem to work on MST at least. It leads to
> underruns and black screen, presumedly because the transcoder is not
> disabled/re-enabled along the port.
>
> Leave switching to a commit modeset on SST for a later patchset, as that
> seems to work ok currently (though better to using a commit there too,
> due to the suppressed underruns).
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 25 +++--
> 1 file changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 81e620dd33bb7..120f7b420807b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5147,6 +5147,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> struct intel_crtc *crtc;
> u8 pipe_mask;
> + bool mst_output = false;
nit: maybe move that up one line to maintain a bit more of a steady slope
> int ret;
>
> if (!intel_dp_is_connected(intel_dp))
> @@ -5177,6 +5178,11 @@ int intel_dp_retrain_link(struct intel_encoder
> *encoder,
> const struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
>
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
> + mst_output = true;
> + break;
> + }
I was pondering if we need a bit more care to make sure all
the pipes agree, but I suppose if that wasn't the case
check_digital_port_conflicts() would have a failed at its
job. So this seems fine.
Reviewed-by: Ville Syrjälä
> +
> /* Suppress underruns caused by re-training */
> intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe,
> false);
> if (crtc_state->has_pch_encoder)
> @@ -5184,16 +5190,23 @@ int intel_dp_retrain_link(struct intel_encoder
> *encoder,
>
> intel_crtc_pch_transcoder(crtc), false);
> }
>
> + /* TODO: use a modeset for SST as well. */
> + if (mst_output) {
> + ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx);
> +
> + if (ret && ret != -EDEADLK)
> + drm_dbg_kms(&dev_priv->drm,
> + "[ENCODER:%d:%s] link retraining failed:
> %pe\n",
> + encoder->base.base.id, encoder->base.name,
> + ERR_PTR(ret));
> +
> + return ret;
> + }
> +
> for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
> const struct intel_crtc_state *crtc_state =
> to_intel_crtc_state(crtc->base.state);
>
> - /* retrain on the MST master transcoder */
> - if (DISPLAY_VER(dev_priv) >= 12 &&
> - intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
> - !intel_dp_mst_is_master_trans(crtc_state))
> - continue;
> -
> intel_dp_check_frl_training(intel_dp);
> intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
> intel_dp_start_link_train(intel_dp, crtc_state);
> --
> 2.43.3
--
Ville Syrjälä
Intel
Re: [PATCH] drm/i915/dpt: Make DPT object unshrinkable
On Thu, May 23, 2024 at 01:07:24PM +0100, Tvrtko Ursulin wrote:
>
> On 23/05/2024 12:19, Ville Syrjälä wrote:
> > On Thu, May 23, 2024 at 09:25:45AM +0100, Tvrtko Ursulin wrote:
> >>
> >> On 22/05/2024 16:29, Vidya Srinivas wrote:
> >>> In some scenarios, the DPT object gets shrunk but
> >>> the actual framebuffer did not and thus its still
> >>> there on the DPT's vm->bound_list. Then it tries to
> >>> rewrite the PTEs via a stale CPU mapping. This causes panic.
> >>>
> >>> Suggested-by: Ville Syrjala
> >>> Cc: sta...@vger.kernel.org
> >>> Fixes: 0dc987b699ce ("drm/i915/display: Add smem fallback allocation for
> >>> dpt")
> >>> Signed-off-by: Vidya Srinivas
> >>> ---
> >>>drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 ++-
> >>>1 file changed, 2 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> >>> b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> >>> index 3560a062d287..e6b485fc54d4 100644
> >>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> >>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> >>> @@ -284,7 +284,8 @@ bool i915_gem_object_has_iomem(const struct
> >>> drm_i915_gem_object *obj);
> >>>static inline bool
> >>>i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
> >>>{
> >>> - return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE);
> >>> + return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE) &&
> >>> + !obj->is_dpt;
> >>
> >> Is there a reason i915_gem_object_make_unshrinkable() cannot be used to
> >> mark the object at a suitable place?
> >
> > Do you have a suitable place in mind?
> > i915_gem_object_make_unshrinkable() contains some magic
> > ingredients so doesn't look like it can be called willy
> > nilly.
>
> After it is created in intel_dpt_create?
>
> I don't see that helper couldn't be called. It is called from madvise
> and tiling for instance without any apparent special considerations.
Did you actually read through i915_gem_object_make_unshrinkable()?
>
> Also, there is no mention of this angle in the commit message so I
> assumed it wasn't considered. If it was, then it should have been
> mentioned why hacky solution was chosen instead...
I suppose.
>
> > Anyways, looks like I forgot to reply that I already pushed this
> > with this extra comment added:
> > /* TODO: make DPT shrinkable when it has no bound vmas */
>
> ... becuase IMO the special case is quite ugly and out of place. :(
Yeah, not the nicest. But there's already a is_dpt check in the
i915_gem_object_is_framebuffer() right next door, so it's not
*that* out of place.
Another option maybe could be to manually clear
I915_GEM_OBJECT_IS_SHRINKABLE but I don't think that is
supposed to be mutable, so might also have other issues.
So a more proper solution with that approach would perhaps
need some kind of gem_create_shmem_unshrinkable() function.
>
> I don't remember from the top of my head how DPT magic works but if
> shrinker protection needs to be tied with VMAs there is also
> i915_make_make(un)shrinkable to try.
I presume you mistyped something there.
--
Ville Syrjälä
Intel
Re: [PATCH] drm/i915/dpt: Make DPT object unshrinkable
On 23/05/2024 12:19, Ville Syrjälä wrote:
On Thu, May 23, 2024 at 09:25:45AM +0100, Tvrtko Ursulin wrote:
On 22/05/2024 16:29, Vidya Srinivas wrote:
In some scenarios, the DPT object gets shrunk but
the actual framebuffer did not and thus its still
there on the DPT's vm->bound_list. Then it tries to
rewrite the PTEs via a stale CPU mapping. This causes panic.
Suggested-by: Ville Syrjala
Cc: sta...@vger.kernel.org
Fixes: 0dc987b699ce ("drm/i915/display: Add smem fallback allocation for dpt")
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3560a062d287..e6b485fc54d4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -284,7 +284,8 @@ bool i915_gem_object_has_iomem(const struct
drm_i915_gem_object *obj);
static inline bool
i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
{
- return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE);
+ return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE) &&
+ !obj->is_dpt;
Is there a reason i915_gem_object_make_unshrinkable() cannot be used to
mark the object at a suitable place?
Do you have a suitable place in mind?
i915_gem_object_make_unshrinkable() contains some magic
ingredients so doesn't look like it can be called willy
nilly.
After it is created in intel_dpt_create?
I don't see that helper couldn't be called. It is called from madvise
and tiling for instance without any apparent special considerations.
Also, there is no mention of this angle in the commit message so I
assumed it wasn't considered. If it was, then it should have been
mentioned why hacky solution was chosen instead...
Anyways, looks like I forgot to reply that I already pushed this
with this extra comment added:
/* TODO: make DPT shrinkable when it has no bound vmas */
... becuase IMO the special case is quite ugly and out of place. :(
I don't remember from the top of my head how DPT magic works but if
shrinker protection needs to be tied with VMAs there is also
i915_make_make(un)shrinkable to try.
Regards,
Tvrtko
Re: [PATCH 06/13] drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()
On Thu, May 23, 2024 at 12:15:53PM +0300, Jani Nikula wrote: > On Thu, 16 May 2024, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Instead of that huge _PICK() let's use PICK_EVEN_2RANGES() > > for the SEL_FETCH_PLANE registers. A bit more tedious to have > > to define 8 raw register offsets for everything, but perhaps > > a bit easier to understand since we use a standard mechanism > > now instead of hand rolling the arithmetic. > > > > Also bloat-o-meter says: > > add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-326 (-326) > > Function old new delta > > icl_plane_update_arm 510 446 -64 > > icl_plane_disable_sel_fetch_arm.isra 158 54-104 > > icl_plane_update_noarm 18981740-158 > > Total: Before=2574502, After=2574176, chg -0.01% > > > > Signed-off-by: Ville Syrjälä > > I just don't understand the old one. > > Reviewed-by: Jani Nikula > > > > --- > > drivers/gpu/drm/i915/display/intel_psr_regs.h | 45 > > .../i915/display/skl_universal_plane_regs.h | 68 +++ > > 2 files changed, 68 insertions(+), 45 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > index f0bd0a726d7a..289c371c98d1 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > @@ -367,4 +378,61 @@ > > #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) > > #define PLANE_BUF_START(start) > > REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) > > > > +#define _SEL_FETCH_PLANE_CTL_1_A 0x70890 /* mtl+ */ I noticed I had these bogus mtl+ comments here too, so changed those to tgl+ while pushing. Entire series is in now. Thanks for slogging through it. -- Ville Syrjälä Intel
Re: [PATCH v8 7/7] drm/i915/display: Compute vrr vsync params
On 5/9/2024 1:28 PM, Mitul Golani wrote:
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index f5ba87fa00fe..3713e9b0829b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -239,6 +239,15 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
+ if (intel_dp_as_sdp_supported(intel_dp)) {
+ crtc_state->vrr.vsync_start =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+crtc_state->hw.adjusted_mode.vsync_start);
+ crtc_state->vrr.vsync_end =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+crtc_state->hw.adjusted_mode.vsync_end);
+ }
+
These lines are duplicated earlier in the: if
(crtc_state->uapi.vrr_enabled) block.
So lets remove from there.
Also I think need to re-organize the series so as to have the patch that
sets cmrr.enable as true is the last one.
Regards,
Ankit
/*
* For XE_LPD+, we use guardband and pipeline override
* is deprecated.
Re: [PATCH v8 5/7] drm/i915/display: Add support for pack and unpack
On 5/9/2024 1:28 PM, Mitul Golani wrote: Add support of pack and unpack for target_rr_divider. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_dp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 486361eb0070..523956193fbf 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4228,7 +4228,7 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, sdp->db[1] = as_sdp->vtotal & 0xFF; sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF; sdp->db[3] = as_sdp->target_rr & 0xFF; - sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; + sdp->db[4] = (as_sdp->target_rr >> 8) & 0x23; I think this is incorrect, this should be: sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; if (as_sdp->target_rr_divider) sdb->db[4] |= 0x20; Regards, Ankit return length; } @@ -4410,6 +4410,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); + as_sdp->target_rr_divider = sdp->db[4] & 0x20; return 0; }
Re: [PATCH v8 3/7] drm/i915: Compute CMRR and calculate vtotal
On 5/9/2024 1:28 PM, Mitul Golani wrote:
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Adaptive Sync Vtotal
mode (Legacy VRR) or not. Make CMRR as small subset of
As I understand what you mean is Variable refresh mode with VRR timing
generator or)VRR framework)
Lets not use legacy VRR term. This will create confusion with legacy
timing generator.
FAVT mode, when Panle is running on Fixed refresh rate
typo : panel
and on VRR framework then only enable CMRR to match with
actual refresh rate.
--v2:
- Update is_cmrr_frac_required function return as bool, not int. [Jani]
- Use signed int math instead of unsigned in cmrr_get_vtotal2. [Jani]
- Fix typo and usage of camel case in cmrr_get_vtotal. [Jani]
- Use do_div in cmrr_get_vtotalwhile calculating cmrr_m. [ Jani]
- Simplify cmrr and vrr compute config in intel_vrr_compute_config. [Jani]
- Correct valiable name usage in is_cmrr_frac_required. [Ville]
--v3:
- Removing RFC tag.
--v4:
- Added edp check to address edp usecase for now. (ville)
- Updated is_cmrr_fraction_required to more simplified calculation.
- on longterm goal to be worked upon uapi as suggestion from ville.
--v5:
- Correct vtotal paramas accuracy and add 2 digit precision.
- Avoid using DIV_ROUND_UP and improve scanline precision.
--v6:
- Make CMRR a small subset of FAVT mode.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 99 ---
3 files changed, 89 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4a5318ab017d..8a76db59c85f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5458,6 +5458,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_I(vrr.vsync_end);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
+ PIPE_CONF_CHECK_BOOL(cmrr.enable);
}
#undef PIPE_CONF_CHECK_X
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
index 17ddf82f0b6e..b372b1acc19b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -71,6 +71,7 @@ struct drm_printer;
BIT(trans)) != 0)
#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
#define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13)
+#define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20)
#define INTEL_NUM_PIPES(i915)
(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
#define I915_HAS_HOTPLUG(i915)
(DISPLAY_INFO(i915)->has_hotplug)
#define OVERLAY_NEEDS_PHYSICAL(i915)
(DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 83ae56d22b5f..f5ba87fa00fe 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -11,6 +11,9 @@
#include "intel_vrr.h"
#include "intel_dp.h"
+#define FIXED_POINT_PRECISION 100
+#define CMRR_PRECISION_TOLERANCE 10
+
bool intel_vrr_is_capable(struct intel_connector *connector)
{
const struct drm_display_info *info = &connector->base.display_info;
@@ -106,6 +109,59 @@ int intel_vrr_vmax_vblank_start(const struct
intel_crtc_state *crtc_state)
return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
}
+static bool
+is_cmrr_frac_required(struct intel_crtc_state *crtc_state, bool is_edp)
+{
+ int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+ if (!(HAS_CMRR(i915) && is_edp))
+ return false;
+
+ actual_refresh_k =
+ drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION;
+ pixel_clock_per_line =
+ adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
+ calculated_refresh_k =
+ pixel_clock_per_line * FIXED_POINT_PRECISION /
adjusted_mode->crtc_vtotal;
+
+ if ((actual_refresh_k - calculated_refresh_k) <
CMRR_PRECISION_TOLERANCE)
+ return false;
+
+ return true;
+}
+
+static unsigned int
+cmrr_get_vtotal(struct intel_crtc_state *crtc_state)
+{
+ int multiplier_m = 1, multiplier_n = 1, vtotal;
+ int actual_refresh_rate, desired_refresh_rate;
+ long long actual
Re: [PATCH] drm/i915/dpt: Make DPT object unshrinkable
On Thu, May 23, 2024 at 09:25:45AM +0100, Tvrtko Ursulin wrote:
>
> On 22/05/2024 16:29, Vidya Srinivas wrote:
> > In some scenarios, the DPT object gets shrunk but
> > the actual framebuffer did not and thus its still
> > there on the DPT's vm->bound_list. Then it tries to
> > rewrite the PTEs via a stale CPU mapping. This causes panic.
> >
> > Suggested-by: Ville Syrjala
> > Cc: sta...@vger.kernel.org
> > Fixes: 0dc987b699ce ("drm/i915/display: Add smem fallback allocation for
> > dpt")
> > Signed-off-by: Vidya Srinivas
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > index 3560a062d287..e6b485fc54d4 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > @@ -284,7 +284,8 @@ bool i915_gem_object_has_iomem(const struct
> > drm_i915_gem_object *obj);
> > static inline bool
> > i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
> > {
> > - return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE);
> > + return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE) &&
> > + !obj->is_dpt;
>
> Is there a reason i915_gem_object_make_unshrinkable() cannot be used to
> mark the object at a suitable place?
Do you have a suitable place in mind?
i915_gem_object_make_unshrinkable() contains some magic
ingredients so doesn't look like it can be called willy
nilly.
Anyways, looks like I forgot to reply that I already pushed this
with this extra comment added:
/* TODO: make DPT shrinkable when it has no bound vmas */
--
Ville Syrjälä
Intel
Re: [PATCH] drm/i915: Fix audio component initialization
On Thu, May 23, 2024 at 12:41:32PM +0300, Jani Nikula wrote:
> On Tue, 21 May 2024, Imre Deak wrote:
> > After registering the audio component in i915_audio_component_init()
> > the audio driver may call i915_audio_component_get_power() via the
> > component ops. This could program AUD_FREQ_CNTRL with an uninitialized
> > value if the latter function is called before display.audio.freq_cntrl
> > gets initialized. The get_power() function also does a modeset which in
> > the above case happens too early before the initialization step and
> > triggers the
> >
> > "Reject display access from task"
> >
> > error message added by the Fixes: commit below.
> >
> > Fix the above issue by registering the audio component only after the
> > initialization step.
> >
> > Fixes: bd738d859e71 ("drm/i915: Prevent modesets during driver
> > init/shutdown")
>
> I think the race condition exists before that commit, actually.
>
> Already commit 87c1694533c9 ("drm/i915: save AUD_FREQ_CNTRL state at
> audio domain suspend") adds freq_cntrl init after component register,
> and the order should be different, right?
The audio side initialization sequence has changed since 87c1694533c9,
but yes the incorrect (rare) sequence could've happened the same way
already at that point. I'll change the Fixes: line.
> > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10291
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_audio.c| 32 ---
> > drivers/gpu/drm/i915/display/intel_audio.h| 1 +
> > .../drm/i915/display/intel_display_driver.c | 2 ++
> > 3 files changed, 24 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> > b/drivers/gpu/drm/i915/display/intel_audio.c
> > index adde87900557f..4c031e97f9a55 100644
> > --- a/drivers/gpu/drm/i915/display/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> > @@ -1267,17 +1267,6 @@ static const struct component_ops
> > i915_audio_component_bind_ops = {
> > static void i915_audio_component_init(struct drm_i915_private *i915)
> > {
> > u32 aud_freq, aud_freq_init;
> > - int ret;
> > -
> > - ret = component_add_typed(i915->drm.dev,
> > - &i915_audio_component_bind_ops,
> > - I915_COMPONENT_AUDIO);
> > - if (ret < 0) {
> > - drm_err(&i915->drm,
> > - "failed to add audio component (%d)\n", ret);
> > - /* continue with reduced functionality */
> > - return;
> > - }
> >
> > if (DISPLAY_VER(i915) >= 9) {
> > aud_freq_init = intel_de_read(i915, AUD_FREQ_CNTRL);
> > @@ -1300,6 +1289,21 @@ static void i915_audio_component_init(struct
> > drm_i915_private *i915)
> >
> > /* init with current cdclk */
> > intel_audio_cdclk_change_post(i915);
> > +}
> > +
> > +static void i915_audio_component_register(struct drm_i915_private *i915)
> > +{
> > + int ret;
> > +
> > + ret = component_add_typed(i915->drm.dev,
> > + &i915_audio_component_bind_ops,
> > + I915_COMPONENT_AUDIO);
> > + if (ret < 0) {
> > + drm_err(&i915->drm,
> > + "failed to add audio component (%d)\n", ret);
> > + /* continue with reduced functionality */
> > + return;
> > + }
> >
> > i915->display.audio.component_registered = true;
> > }
> > @@ -1332,6 +1336,12 @@ void intel_audio_init(struct drm_i915_private *i915)
> > i915_audio_component_init(i915);
> > }
> >
> > +void intel_audio_register(struct drm_i915_private *i915)
> > +{
> > + if (!i915->display.audio.lpe.platdev)
> > + i915_audio_component_register(i915);
> > +}
> > +
> > /**
> > * intel_audio_deinit() - deinitialize the audio driver
> > * @i915: the i915 drm device private data
> > diff --git a/drivers/gpu/drm/i915/display/intel_audio.h
> > b/drivers/gpu/drm/i915/display/intel_audio.h
> > index 9327954b801e5..576c061d72a45 100644
> > --- a/drivers/gpu/drm/i915/display/intel_audio.h
> > +++ b/drivers/gpu/drm/i915/display/intel_audio.h
> > @@ -28,6 +28,7 @@ void intel_audio_codec_get_config(struct intel_encoder
> > *encoder,
> > void intel_audio_cdclk_change_pre(struct drm_i915_private *dev_priv);
> > void intel_audio_cdclk_change_post(struct drm_i915_private *dev_priv);
> > void intel_audio_init(struct drm_i915_private *dev_priv);
> > +void intel_audio_register(struct drm_i915_private *i915);
> > void intel_audio_deinit(struct drm_i915_private *dev_priv);
> > void intel_audio_sdp_split_update(const struct intel_crtc_state
> > *crtc_state);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > index 89bd032ed995e..794b4af380558 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > @@ -540,6 +
RE: [RESEND 6/6] drm/connector: update edid_blob_ptr documentation
> -Original Message-
> From: dri-devel On Behalf Of Jani
> Nikula
> Sent: Friday, May 10, 2024 8:38 PM
> To: dri-de...@lists.freedesktop.org
> Cc: amd-...@lists.freedesktop.org; nouv...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org; Nikula, Jani
> Subject: [RESEND 6/6] drm/connector: update edid_blob_ptr documentation
>
> Accessing the EDID via edid_blob_ptr causes chicken-and-egg problems. Keep
> edid_blob_ptr as the userspace interface that should be accessed via dedicated
> functions.
>
> Signed-off-by: Jani Nikula
LGTM
Reviewed-by: Chaitanya Kumar Borah
> ---
> include/drm/drm_connector.h | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index fe88d7fc6b8f..58ee9adf9091 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -1636,8 +1636,12 @@ struct drm_connector {
>
> /**
>* @edid_blob_ptr: DRM property containing EDID if present.
> Protected by
> - * &drm_mode_config.mutex. This should be updated only by calling
> + * &drm_mode_config.mutex.
> + *
> + * This must be updated only by calling drm_edid_connector_update()
> or
>* drm_connector_update_edid_property().
> + *
> + * This must not be used by drivers directly.
>*/
> struct drm_property_blob *edid_blob_ptr;
>
> --
> 2.39.2
RE: [RESEND 5/6] drm/edid: add a helper for EDID sysfs property show
> -Original Message-
> From: dri-devel On Behalf Of Jani
> Nikula
> Sent: Friday, May 10, 2024 8:38 PM
> To: dri-de...@lists.freedesktop.org
> Cc: amd-...@lists.freedesktop.org; nouv...@lists.freedesktop.org; intel-
> g...@lists.freedesktop.org; Nikula, Jani
> Subject: [RESEND 5/6] drm/edid: add a helper for EDID sysfs property show
>
> Add a helper to get the EDID property for sysfs property show. This hides all
> the edid_blob_ptr usage within drm_edid.c.
>
> Signed-off-by: Jani Nikula
LGTM,
Reviewed-by: Chaitanya Kumar Borah
> ---
> drivers/gpu/drm/drm_crtc_internal.h | 2 ++
> drivers/gpu/drm/drm_edid.c | 33 +
> drivers/gpu/drm/drm_sysfs.c | 24 ++---
> 3 files changed, 37 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_crtc_internal.h
> b/drivers/gpu/drm/drm_crtc_internal.h
> index 25aaae937ceb..20e9d7b206a2 100644
> --- a/drivers/gpu/drm/drm_crtc_internal.h
> +++ b/drivers/gpu/drm/drm_crtc_internal.h
> @@ -303,6 +303,8 @@ const u8 *drm_edid_find_extension(const struct
> drm_edid *drm_edid,
> int ext_id, int *ext_index);
> void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad); void
> drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad);
> +ssize_t drm_edid_connector_property_show(struct drm_connector
> *connector,
> + char *buf, loff_t off, size_t count);
>
> /* drm_edid_load.c */
> #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
> 4f54c91b31b2..97362dd2330b 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6969,6 +6969,39 @@ static int
> _drm_edid_connector_property_update(struct drm_connector *connector,
> return ret;
> }
>
> +/* For sysfs edid show implementation */ ssize_t
> +drm_edid_connector_property_show(struct drm_connector *connector,
> + char *buf, loff_t off, size_t count) {
> + const void *edid;
> + size_t size;
> + ssize_t ret = 0;
> +
> + mutex_lock(&connector->dev->mode_config.mutex);
> +
> + if (!connector->edid_blob_ptr)
> + goto unlock;
> +
> + edid = connector->edid_blob_ptr->data;
> + size = connector->edid_blob_ptr->length;
> + if (!edid)
> + goto unlock;
> +
> + if (off >= size)
> + goto unlock;
> +
> + if (off + count > size)
> + count = size - off;
> +
> + memcpy(buf, edid + off, count);
> +
> + ret = count;
> +unlock:
> + mutex_unlock(&connector->dev->mode_config.mutex);
> +
> + return ret;
> +}
> +
> /**
> * drm_edid_connector_update - Update connector information from EDID
> * @connector: Connector
> diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
> index bd9b8ab4f82b..fb3bbb6adcd1 100644
> --- a/drivers/gpu/drm/drm_sysfs.c
> +++ b/drivers/gpu/drm/drm_sysfs.c
> @@ -266,29 +266,9 @@ static ssize_t edid_show(struct file *filp, struct
> kobject *kobj, {
> struct device *connector_dev = kobj_to_dev(kobj);
> struct drm_connector *connector =
> to_drm_connector(connector_dev);
> - unsigned char *edid;
> - size_t size;
> - ssize_t ret = 0;
> + ssize_t ret;
>
> - mutex_lock(&connector->dev->mode_config.mutex);
> - if (!connector->edid_blob_ptr)
> - goto unlock;
> -
> - edid = connector->edid_blob_ptr->data;
> - size = connector->edid_blob_ptr->length;
> - if (!edid)
> - goto unlock;
> -
> - if (off >= size)
> - goto unlock;
> -
> - if (off + count > size)
> - count = size - off;
> - memcpy(buf, edid + off, count);
> -
> - ret = count;
> -unlock:
> - mutex_unlock(&connector->dev->mode_config.mutex);
> + ret = drm_edid_connector_property_show(connector, buf, off, count);
>
> return ret;
> }
> --
> 2.39.2
Re: [PATCH v2 1/6] drm/ci: uprev mesa version
On Thu, 23 May 2024 at 09:07, Vignesh Raman wrote:
>
> Hi Dmitry,
>
> On 20/05/24 16:13, Dmitry Baryshkov wrote:
> > On Fri, May 17, 2024 at 02:54:57PM +0530, Vignesh Raman wrote:
> >> zlib.net is not allowing tarball download anymore and results
> >> in below error in kernel+rootfs_arm32 container build,
> >> urllib.error.HTTPError: HTTP Error 403: Forbidden
> >> urllib.error.HTTPError: HTTP Error 415: Unsupported Media Type
> >>
> >> Uprev mesa to latest version which includes a fix for this issue.
> >> https://gitlab.freedesktop.org/mesa/mesa/-/commit/908f444e
> >>
> >> Use id_tokens for JWT authentication. Since s3 bucket is migrated to
> >> mesa-rootfs, update the variables accordingly. Also copy helper scripts
> >> to install, so that the ci jobs can use these scripts for logging.
> >>
> >> Signed-off-by: Vignesh Raman
> >> ---
> >>
> >> v2:
> >>- Uprev to recent version and use id_tokens for JWT authentication
> >>
> >> ---
> >> drivers/gpu/drm/ci/build-igt.sh | 2 +-
> >> drivers/gpu/drm/ci/build.sh | 6 +++--
> >> drivers/gpu/drm/ci/container.yml | 12 +++--
> >> drivers/gpu/drm/ci/gitlab-ci.yml | 44 +--
> >> drivers/gpu/drm/ci/image-tags.yml | 2 +-
> >> drivers/gpu/drm/ci/lava-submit.sh | 4 +--
> >> drivers/gpu/drm/ci/test.yml | 2 ++
> >> 7 files changed, 44 insertions(+), 28 deletions(-)
> >>
> >
> > [skipped]
> >
> >> diff --git a/drivers/gpu/drm/ci/test.yml b/drivers/gpu/drm/ci/test.yml
> >> index 8bc63912fddb..612c9ede3507 100644
> >> --- a/drivers/gpu/drm/ci/test.yml
> >> +++ b/drivers/gpu/drm/ci/test.yml
> >> @@ -150,6 +150,8 @@ msm:sdm845:
> >> BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/cheza-kernel
> >> GPU_VERSION: sdm845
> >> RUNNER_TAG: google-freedreno-cheza
> >> +DEVICE_TYPE: sdm845-cheza-r3
> >> +FARM: google
> >
> > I see that this is the only user of the FARM: tag. Is it correct?
>
> No, we need to add FARM variable for other jobs as well.
Why? Even if we have to, we don't have them now and the change doesn't
seem to be related to the uprev'ing of mesa. So this probably should
go to a separate commit.
>
> > Also we miss DEVICE_TYPE for several other boards. Should we be adding
> > them?
>
> Yes, device type needs to be added for msm:apq8016, msm:apq8096, virtio_gpu.
>
> I will add this. Thanks.
I'd guess, separate commit too.
>
> Regards,
> Vignesh
>
> >
> >> script:
> >> - ./install/bare-metal/cros-servo.sh
> >>
> >> --
> >> 2.40.1
> >>
> >
--
With best wishes
Dmitry
