[Intel-gfx] [CI 1/2] drm/i915/step: Add macro magic for handling steps
With the addition of stepping info for
all platforms, lets use macros for handling them
and autogenerating code for all steps at a time.
Suggested-by: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_step.c | 14
drivers/gpu/drm/i915/intel_step.h | 37 +++
2 files changed, 37 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 9fcf17708cc8..e9ec111d6232 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -182,3 +182,17 @@ void intel_step_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->step = step;
}
+
+#define STEP_NAME_CASE(name) \
+ case STEP_##name: \
+ return #name;
+
+const char *intel_step_name(enum intel_step step)
+{
+ switch (step) {
+ STEP_NAME_LIST(STEP_NAME_CASE);
+
+ default:
+ return "**";
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_step.h
b/drivers/gpu/drm/i915/intel_step.h
index 88a77159703e..f6641e2a3c77 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -15,30 +15,39 @@ struct intel_step_info {
u8 display_step;
};
+#define STEP_ENUM_VAL(name) STEP_##name,
+
+#define STEP_NAME_LIST(func) \
+ func(A0)\
+ func(A1)\
+ func(A2)\
+ func(B0)\
+ func(B1)\
+ func(B2)\
+ func(C0)\
+ func(C1)\
+ func(D0)\
+ func(D1)\
+ func(E0)\
+ func(F0)\
+ func(G0)\
+ func(H0)\
+ func(I0)\
+ func(I1)\
+ func(J0)
+
/*
* Symbolic steppings that do not match the hardware. These are valid both as
gt
* and display steppings as symbolic names.
*/
enum intel_step {
STEP_NONE = 0,
- STEP_A0,
- STEP_A2,
- STEP_B0,
- STEP_B1,
- STEP_C0,
- STEP_D0,
- STEP_D1,
- STEP_E0,
- STEP_F0,
- STEP_G0,
- STEP_H0,
- STEP_I0,
- STEP_I1,
- STEP_J0,
+ STEP_NAME_LIST(STEP_ENUM_VAL)
STEP_FUTURE,
STEP_FOREVER,
};
void intel_step_init(struct drm_i915_private *i915);
+const char *intel_step_name(enum intel_step step);
#endif /* __INTEL_STEP_H__ */
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/2] drm/i915/dmc: Change intel_get_stepping_info()
Lets use RUNTIME_INFO->step since all platforms now have their
stepping info in intel_step.c. This makes intel_get_stepping_info()
a lot simpler.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 50
1 file changed, 8 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index f8789d4543bf..1f6c32932331 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -247,50 +247,15 @@ bool intel_dmc_has_payload(struct drm_i915_private *i915)
return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
-static const struct stepping_info skl_stepping_info[] = {
- {'A', '0'}, {'B', '0'}, {'C', '0'},
- {'D', '0'}, {'E', '0'}, {'F', '0'},
- {'G', '0'}, {'H', '0'}, {'I', '0'},
- {'J', '0'}, {'K', '0'}
-};
-
-static const struct stepping_info bxt_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '1'}, {'B', '2'}
-};
-
-static const struct stepping_info icl_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '2'},
- {'C', '0'}
-};
-
-static const struct stepping_info no_stepping_info = { '*', '*' };
-
static const struct stepping_info *
-intel_get_stepping_info(struct drm_i915_private *dev_priv)
+intel_get_stepping_info(struct drm_i915_private *i915,
+ struct stepping_info *si)
{
- const struct stepping_info *si;
- unsigned int size;
-
- if (IS_ICELAKE(dev_priv)) {
- size = ARRAY_SIZE(icl_stepping_info);
- si = icl_stepping_info;
- } else if (IS_SKYLAKE(dev_priv)) {
- size = ARRAY_SIZE(skl_stepping_info);
- si = skl_stepping_info;
- } else if (IS_BROXTON(dev_priv)) {
- size = ARRAY_SIZE(bxt_stepping_info);
- si = bxt_stepping_info;
- } else {
- size = 0;
- si = NULL;
- }
-
- if (INTEL_REVID(dev_priv) < size)
- return si + INTEL_REVID(dev_priv);
+ const char *step_name =
intel_step_name(RUNTIME_INFO(i915)->step.display_step);
- return &no_stepping_info;
+ si->stepping = step_name[0];
+ si->substepping = step_name[1];
+ return si;
}
static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
@@ -616,7 +581,8 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
struct intel_dmc *dmc = &dev_priv->dmc;
- const struct stepping_info *si = intel_get_stepping_info(dev_priv);
+ struct stepping_info display_info = { '*', '*'};
+ const struct stepping_info *si = intel_get_stepping_info(dev_priv,
&display_info);
u32 readcount = 0;
u32 r, offset;
int id;
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/2] drm/i915/step: Add macro magic for handling steps
With the addition of stepping info for
all platforms, lets use macros for handling them
and autogenerating code for all steps at a time.
Suggested-by: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_step.c | 14
drivers/gpu/drm/i915/intel_step.h | 37 +++
2 files changed, 37 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 9fcf17708cc8..d150d138e889 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -182,3 +182,17 @@ void intel_step_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->step = step;
}
+
+#define STEP_NAME_CASE(name) \
+ (case STEP_##name: \
+ return #name)
+
+const char *intel_step_name(enum intel_step step)
+{
+ switch (step) {
+ STEP_NAME_LIST(STEP_NAME_CASE);
+
+ default:
+ return "**";
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_step.h
b/drivers/gpu/drm/i915/intel_step.h
index 88a77159703e..f6641e2a3c77 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -15,30 +15,39 @@ struct intel_step_info {
u8 display_step;
};
+#define STEP_ENUM_VAL(name) STEP_##name,
+
+#define STEP_NAME_LIST(func) \
+ func(A0)\
+ func(A1)\
+ func(A2)\
+ func(B0)\
+ func(B1)\
+ func(B2)\
+ func(C0)\
+ func(C1)\
+ func(D0)\
+ func(D1)\
+ func(E0)\
+ func(F0)\
+ func(G0)\
+ func(H0)\
+ func(I0)\
+ func(I1)\
+ func(J0)
+
/*
* Symbolic steppings that do not match the hardware. These are valid both as
gt
* and display steppings as symbolic names.
*/
enum intel_step {
STEP_NONE = 0,
- STEP_A0,
- STEP_A2,
- STEP_B0,
- STEP_B1,
- STEP_C0,
- STEP_D0,
- STEP_D1,
- STEP_E0,
- STEP_F0,
- STEP_G0,
- STEP_H0,
- STEP_I0,
- STEP_I1,
- STEP_J0,
+ STEP_NAME_LIST(STEP_ENUM_VAL)
STEP_FUTURE,
STEP_FOREVER,
};
void intel_step_init(struct drm_i915_private *i915);
+const char *intel_step_name(enum intel_step step);
#endif /* __INTEL_STEP_H__ */
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/2] drm/i915/dmc: Change intel_get_stepping_info()
Lets use RUNTIME_INFO->step since all platforms now have their
stepping info in intel_step.c. This makes intel_get_stepping_info()
a lot simpler.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 50
1 file changed, 8 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index f8789d4543bf..1f6c32932331 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -247,50 +247,15 @@ bool intel_dmc_has_payload(struct drm_i915_private *i915)
return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
-static const struct stepping_info skl_stepping_info[] = {
- {'A', '0'}, {'B', '0'}, {'C', '0'},
- {'D', '0'}, {'E', '0'}, {'F', '0'},
- {'G', '0'}, {'H', '0'}, {'I', '0'},
- {'J', '0'}, {'K', '0'}
-};
-
-static const struct stepping_info bxt_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '1'}, {'B', '2'}
-};
-
-static const struct stepping_info icl_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '2'},
- {'C', '0'}
-};
-
-static const struct stepping_info no_stepping_info = { '*', '*' };
-
static const struct stepping_info *
-intel_get_stepping_info(struct drm_i915_private *dev_priv)
+intel_get_stepping_info(struct drm_i915_private *i915,
+ struct stepping_info *si)
{
- const struct stepping_info *si;
- unsigned int size;
-
- if (IS_ICELAKE(dev_priv)) {
- size = ARRAY_SIZE(icl_stepping_info);
- si = icl_stepping_info;
- } else if (IS_SKYLAKE(dev_priv)) {
- size = ARRAY_SIZE(skl_stepping_info);
- si = skl_stepping_info;
- } else if (IS_BROXTON(dev_priv)) {
- size = ARRAY_SIZE(bxt_stepping_info);
- si = bxt_stepping_info;
- } else {
- size = 0;
- si = NULL;
- }
-
- if (INTEL_REVID(dev_priv) < size)
- return si + INTEL_REVID(dev_priv);
+ const char *step_name =
intel_step_name(RUNTIME_INFO(i915)->step.display_step);
- return &no_stepping_info;
+ si->stepping = step_name[0];
+ si->substepping = step_name[1];
+ return si;
}
static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
@@ -616,7 +581,8 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
struct intel_dmc *dmc = &dev_priv->dmc;
- const struct stepping_info *si = intel_get_stepping_info(dev_priv);
+ struct stepping_info display_info = { '*', '*'};
+ const struct stepping_info *si = intel_get_stepping_info(dev_priv,
&display_info);
u32 readcount = 0;
u32 r, offset;
int id;
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/2] drm/i915/step: Add macro magic for handling steps
With the addition of stepping info for
all platforms, lets use macros for handling them
and autogenerating code for all steps at a time.
Suggested-by: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_step.c | 14
drivers/gpu/drm/i915/intel_step.h | 37 +++
2 files changed, 37 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 9fcf17708cc8..d150d138e889 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -182,3 +182,17 @@ void intel_step_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->step = step;
}
+
+#define STEP_NAME_CASE(name) \
+ (case STEP_##name: \
+ return #name)
+
+const char *intel_step_name(enum intel_step step)
+{
+ switch (step) {
+ STEP_NAME_LIST(STEP_NAME_CASE);
+
+ default:
+ return "**";
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_step.h
b/drivers/gpu/drm/i915/intel_step.h
index 88a77159703e..dac4e94f 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -15,30 +15,39 @@ struct intel_step_info {
u8 display_step;
};
+#define STEP_ENUM_VAL(name) STEP_##name,
+
+#define STEP_NAME_LIST(func) \
+ (func(A0) \
+func(A1) \
+func(A2) \
+func(B0) \
+func(B1) \
+func(B2) \
+func(C0) \
+func(C1) \
+func(D0) \
+func(D1) \
+func(E0) \
+func(F0) \
+func(G0) \
+func(H0) \
+func(I0) \
+func(I1) \
+func(J0))
+
/*
* Symbolic steppings that do not match the hardware. These are valid both as
gt
* and display steppings as symbolic names.
*/
enum intel_step {
STEP_NONE = 0,
- STEP_A0,
- STEP_A2,
- STEP_B0,
- STEP_B1,
- STEP_C0,
- STEP_D0,
- STEP_D1,
- STEP_E0,
- STEP_F0,
- STEP_G0,
- STEP_H0,
- STEP_I0,
- STEP_I1,
- STEP_J0,
+ STEP_NAME_LIST(STEP_ENUM_VAL)
STEP_FUTURE,
STEP_FOREVER,
};
void intel_step_init(struct drm_i915_private *i915);
+const char *intel_step_name(enum intel_step step);
#endif /* __INTEL_STEP_H__ */
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 39/50] drm/i915/dg2: Don't read DRAM info
> -Original Message- > From: Roper, Matthew D > Sent: Tuesday, July 13, 2021 8:15 PM > To: intel-gfx@lists.freedesktop.org > Cc: Roper, Matthew D ; Srivatsa, Anusha > > Subject: [PATCH v2 39/50] drm/i915/dg2: Don't read DRAM info > > DG2 does not use system DRAM information for BW_BUDDY programming or > watermark workarounds, so there's no need to read this out at startup. > > Cc: Anusha Srivatsa > Signed-off-by: Matt Roper Reviewed-by: Anusha Srivatsa > --- > drivers/gpu/drm/i915/intel_dram.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dram.c > b/drivers/gpu/drm/i915/intel_dram.c > index 879b0f007be3..9675bb94b70b 100644 > --- a/drivers/gpu/drm/i915/intel_dram.c > +++ b/drivers/gpu/drm/i915/intel_dram.c > @@ -494,15 +494,15 @@ void intel_dram_detect(struct drm_i915_private > *i915) > struct dram_info *dram_info = &i915->dram_info; > int ret; > > + if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915)) > + return; > + > /* >* Assume level 0 watermark latency adjustment is needed until > proven >* otherwise, this w/a is not needed by bxt/glk. >*/ > dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915); > > - if (GRAPHICS_VER(i915) < 9 || !HAS_DISPLAY(i915)) > - return; > - > if (GRAPHICS_VER(i915) >= 12) > ret = gen12_get_dram_info(i915); > else if (GRAPHICS_VER(i915) >= 11) > -- > 2.25.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/dmc: Change intel_get_stepping_info()
Lets use RUNTIME_INFO->step since all platforms now have their
stepping info in intel_step.c. This makes intel_get_stepping_info()
a lot simpler.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 50
1 file changed, 8 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index f8789d4543bf..1f6c32932331 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -247,50 +247,15 @@ bool intel_dmc_has_payload(struct drm_i915_private *i915)
return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
-static const struct stepping_info skl_stepping_info[] = {
- {'A', '0'}, {'B', '0'}, {'C', '0'},
- {'D', '0'}, {'E', '0'}, {'F', '0'},
- {'G', '0'}, {'H', '0'}, {'I', '0'},
- {'J', '0'}, {'K', '0'}
-};
-
-static const struct stepping_info bxt_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '1'}, {'B', '2'}
-};
-
-static const struct stepping_info icl_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '2'},
- {'C', '0'}
-};
-
-static const struct stepping_info no_stepping_info = { '*', '*' };
-
static const struct stepping_info *
-intel_get_stepping_info(struct drm_i915_private *dev_priv)
+intel_get_stepping_info(struct drm_i915_private *i915,
+ struct stepping_info *si)
{
- const struct stepping_info *si;
- unsigned int size;
-
- if (IS_ICELAKE(dev_priv)) {
- size = ARRAY_SIZE(icl_stepping_info);
- si = icl_stepping_info;
- } else if (IS_SKYLAKE(dev_priv)) {
- size = ARRAY_SIZE(skl_stepping_info);
- si = skl_stepping_info;
- } else if (IS_BROXTON(dev_priv)) {
- size = ARRAY_SIZE(bxt_stepping_info);
- si = bxt_stepping_info;
- } else {
- size = 0;
- si = NULL;
- }
-
- if (INTEL_REVID(dev_priv) < size)
- return si + INTEL_REVID(dev_priv);
+ const char *step_name =
intel_step_name(RUNTIME_INFO(i915)->step.display_step);
- return &no_stepping_info;
+ si->stepping = step_name[0];
+ si->substepping = step_name[1];
+ return si;
}
static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
@@ -616,7 +581,8 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
struct intel_dmc *dmc = &dev_priv->dmc;
- const struct stepping_info *si = intel_get_stepping_info(dev_priv);
+ struct stepping_info display_info = { '*', '*'};
+ const struct stepping_info *si = intel_get_stepping_info(dev_priv,
&display_info);
u32 readcount = 0;
u32 r, offset;
int id;
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/step: Add macro magic for handling steps
With the addition of stepping info for
all platforms, lets use macros for handling them
and autogenerating code for all steps at a time.
Suggested-by: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_step.c | 14
drivers/gpu/drm/i915/intel_step.h | 37 +++
2 files changed, 37 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 9fcf17708cc8..26f6b1d376e1 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -182,3 +182,17 @@ void intel_step_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->step = step;
}
+
+#define STEP_NAME_CASE(name) \
+ case STEP_##name: \
+ return #name;
+
+const char *intel_step_name(enum intel_step step)
+{
+ switch(step) {
+ STEP_NAME_LIST(STEP_NAME_CASE);
+
+ default :
+ return "**";
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_step.h
b/drivers/gpu/drm/i915/intel_step.h
index 88a77159703e..f6641e2a3c77 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -15,30 +15,39 @@ struct intel_step_info {
u8 display_step;
};
+#define STEP_ENUM_VAL(name) STEP_##name,
+
+#define STEP_NAME_LIST(func) \
+ func(A0)\
+ func(A1)\
+ func(A2)\
+ func(B0)\
+ func(B1)\
+ func(B2)\
+ func(C0)\
+ func(C1)\
+ func(D0)\
+ func(D1)\
+ func(E0)\
+ func(F0)\
+ func(G0)\
+ func(H0)\
+ func(I0)\
+ func(I1)\
+ func(J0)
+
/*
* Symbolic steppings that do not match the hardware. These are valid both as
gt
* and display steppings as symbolic names.
*/
enum intel_step {
STEP_NONE = 0,
- STEP_A0,
- STEP_A2,
- STEP_B0,
- STEP_B1,
- STEP_C0,
- STEP_D0,
- STEP_D1,
- STEP_E0,
- STEP_F0,
- STEP_G0,
- STEP_H0,
- STEP_I0,
- STEP_I1,
- STEP_J0,
+ STEP_NAME_LIST(STEP_ENUM_VAL)
STEP_FUTURE,
STEP_FOREVER,
};
void intel_step_init(struct drm_i915_private *i915);
+const char *intel_step_name(enum intel_step step);
#endif /* __INTEL_STEP_H__ */
--
2.32.0
___
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Re: [Intel-gfx] [PATCH v3 10/12] drm/i915/dg1: Use revid->stepping tables
> -Original Message-
> From: Roper, Matthew D
> Sent: Tuesday, July 13, 2021 10:29 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Roper, Matthew D
>
> Subject: [PATCH v3 10/12] drm/i915/dg1: Use revid->stepping tables
>
> Switch DG1 to use a revid->stepping table as we're trying to do on all
> platforms going forward.
>
> This removes the last use of IS_REVID() and REVID_FOREVER, so remove
> those now-unused macros as well to prevent their accidental use on future
> platforms.
>
> v2:
> - Use COMMON_STEPPING() macro in table. (Anusha)
>
> Bspec: 44463
> Cc: Anusha Srivatsa
> Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
> ---
> .../gpu/drm/i915/display/intel_display_power.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_region_lmem.c| 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c| 10 +-
> drivers/gpu/drm/i915/i915_drv.h| 18 --
> drivers/gpu/drm/i915/intel_pm.c| 2 +-
> drivers/gpu/drm/i915/intel_step.c | 8
> 6 files changed, 20 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 285380079aab..975a7e25cea5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5799,7 +5799,7 @@ static void tgl_bw_buddy_init(struct
> drm_i915_private *dev_priv)
> int config, i;
>
> if (IS_ALDERLAKE_S(dev_priv) ||
> - IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> + IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> /* Wa_1409767108:tgl,dg1,adl-s */
> table = wa_1409767108_buddy_page_masks; diff --git
> a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index 1f43aba2e9e2..50d11a84e7a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt) static
> bool get_legacy_lowmem_region(struct intel_uncore *uncore,
>u64 *start, u32 *size)
> {
> - if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_B0))
> + if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
> return false;
>
> *start = 0;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4c0c15bbdac2..62321e9149db 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -,7 +,7 @@ dg1_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> gen12_gt_workarounds_init(i915, wal);
>
> /* Wa_1607087056:dg1 */
> - if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
> + if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
> wa_write_or(wal,
> SLICE_UNIT_LEVEL_CLKGATE,
> L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); @@ -
> 1522,7 +1522,7 @@ static void dg1_whitelist_build(struct intel_engine_cs
> *engine)
> tgl_whitelist_build(engine);
>
> /* GEN:BUG:1409280441:dg1 */
> - if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
> + if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
> (engine->class == RENDER_CLASS ||
>engine->class == COPY_ENGINE_CLASS))
> whitelist_reg_ext(w, RING_ID(engine->mmio_base), @@ -
> 1592,7 +1592,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal) {
> struct drm_i915_private *i915 = engine->i915;
>
> - if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> + if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
> IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
> /*
>* Wa_1607138336:tgl[a0],dg1[a0]
> @@ -1638,7 +1638,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> }
>
> if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
> - IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> + IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
> wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> @@ -1652,7 +1652,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list
Re: [Intel-gfx] [PATCH v2 04/12] drm/i915/kbl: Drop pre-production revision from stepping table
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Roper, Matthew D
>
> Subject: [PATCH v2 04/12] drm/i915/kbl: Drop pre-production revision from
> stepping table
>
> We're long past the point where we need to care about pre-production
> hardware, and we already warn the user and taint the kernel if we detect the
> driver is being loaded on pre-production hardware.
>
> Bspec: 18329
> Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/intel_step.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index 69c928b046e8..8987453aa172 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -33,7 +33,6 @@ static const struct intel_step_info skl_revids[] = { };
>
> static const struct intel_step_info kbl_revids[] = {
> - [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> [1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
> [2] = { .gt_step = STEP_C0, .display_step = STEP_B0 },
> [3] = { .gt_step = STEP_D0, .display_step = STEP_B0 },
> --
> 2.25.4
___
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Re: [Intel-gfx] [PATCH v2 02/12] drm/i915: Make pre-production detection use direct revid comparison
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Roper, Matthew D
>
> Subject: [PATCH v2 02/12] drm/i915: Make pre-production detection use
> direct revid comparison
>
> Although we're converting our workarounds to use a revid->stepping lookup
> table, the function that detects pre-production hardware should continue to
> compare against PCI revision ID values directly. These are listed in the
> bspec
> as integers, so it's easier to confirm their correctness if we just use an
> integer
> literal rather than a symbolic name anyway.
>
> Bspec: 13620, 19131, 13626, 18329
> Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915_drv.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c index 30d8cd8c69b1..90136995f5eb
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -271,10 +271,10 @@ static void intel_detect_preproduction_hw(struct
> drm_i915_private *dev_priv)
> bool pre = false;
>
> pre |= IS_HSW_EARLY_SDV(dev_priv);
> - pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
> - pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
> - pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
> - pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
> + pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
> + pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
> + pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> + pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
>
> if (pre) {
> drm_err(&dev_priv->drm, "This is a pre-production stepping.
> "
> --
> 2.25.4
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Re: [Intel-gfx] [PATCH v2 12/12] drm/i915/icl: Drop workarounds that only apply to pre-production steppings
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Roper, Matthew D
>
> Subject: [PATCH v2 12/12] drm/i915/icl: Drop workarounds that only apply to
> pre-production steppings
>
> We're past the point at which we usually drop workarounds that were never
> needed on production hardware. The driver will already print an error and
> apply taint if loaded on pre-production hardware.
>
> Signed-off-by: Matt Roper
Definitely cleans up the code.
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 -
> drivers/gpu/drm/i915/i915_drv.h | 3 --
> 2 files changed, 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 9b257a394305..5ace14cdfa85 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -517,21 +517,12 @@ static void cfl_ctx_workarounds_init(struct
> intel_engine_cs *engine, static void icl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>struct i915_wa_list *wal)
> {
> - struct drm_i915_private *i915 = engine->i915;
> -
> /* WaDisableBankHangMode:icl */
> wa_write(wal,
>GEN8_L3CNTLREG,
>intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
>GEN8_ERRDETBCTRL);
>
> - /* Wa_1604370585:icl (pre-prod)
> - * Formerly known as WaPushConstantDereferenceHoldDisable
> - */
> - if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> - PUSH_CONSTANT_DEREF_DISABLE);
> -
> /* WaForceEnableNonCoherent:icl
>* This is not the same workaround as in early Gen9 platforms, where
>* lacking this could cause system hangs, but coherency performance
> @@ -541,18 +532,6 @@ static void icl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>*/
> wa_masked_en(wal, ICL_HDC_MODE,
> HDC_FORCE_NON_COHERENT);
>
> - /* Wa_2006611047:icl (pre-prod)
> - * Formerly known as WaDisableImprovedTdlClkGating
> - */
> - if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> - GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
> -
> - /* Wa_2006665173:icl (pre-prod) */
> - if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
> - wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> - GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
> -
> /* WaEnableFloatBlendOptimization:icl */
> wa_write_clr_set(wal,
>GEN10_CACHE_MODE_SS,
> @@ -982,18 +961,6 @@ icl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> GEN8_GAMW_ECO_DEV_RW_IA,
> GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
>
> - /* Wa_1405779004:icl (pre-prod) */
> - if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0))
> - wa_write_or(wal,
> - SLICE_UNIT_LEVEL_CLKGATE,
> - MSCUNIT_CLKGATE_DIS);
> -
> - /* Wa_1406838659:icl (pre-prod) */
> - if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
> - wa_write_or(wal,
> - INF_UNIT_LEVEL_CLKGATE,
> - CGPSF_CLKGATE_DIS);
> -
> /* Wa_1406463099:icl
>* Formerly known as WaGamTlbPendError
>*/
> @@ -1669,12 +1636,6 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> PMFLUSH_GAPL3UNBLOCK |
> PMFLUSHDONE_LNEBLK);
>
> - /* Wa_1406609255:icl (pre-prod) */
> - if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0))
> - wa_write_or(wal,
> - GEN7_SARCHKMD,
> - GEN7_DISABLE_DEMAND_PREFETCH);
> -
> /* Wa_1606682166:icl */
> wa_write_or(wal,
> GEN7_SARCHKMD,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 8682a5f557c5..da5f230e2d4b
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1513,9 +1513,6 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915, #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
> (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since,
> until))
>
> -#define IS_ICL_GT_STEP(p, since, until) \
> -
Re: [Intel-gfx] [PATCH v2 10/12] drm/i915/dg1: Use revid->stepping tables
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Roper, Matthew D
>
> Subject: [PATCH v2 10/12] drm/i915/dg1: Use revid->stepping tables
>
> Switch DG1 to use a revid->stepping table as we're trying to do on all
> platforms going forward.
>
> This removes the last use of IS_REVID() and REVID_FOREVER, so remove
> those now-unused macros as well to prevent their accidental use on future
> platforms.
>
> Bspec: 44463
> Signed-off-by: Matt Roper
> ---
> .../gpu/drm/i915/display/intel_display_power.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_region_lmem.c| 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c| 10 +-
> drivers/gpu/drm/i915/i915_drv.h| 18 --
> drivers/gpu/drm/i915/intel_pm.c| 2 +-
> drivers/gpu/drm/i915/intel_step.c | 8
> 6 files changed, 20 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 285380079aab..975a7e25cea5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5799,7 +5799,7 @@ static void tgl_bw_buddy_init(struct
> drm_i915_private *dev_priv)
> int config, i;
>
> if (IS_ALDERLAKE_S(dev_priv) ||
> - IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> + IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> /* Wa_1409767108:tgl,dg1,adl-s */
> table = wa_1409767108_buddy_page_masks; diff --git
> a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index 1f43aba2e9e2..50d11a84e7a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt) static
> bool get_legacy_lowmem_region(struct intel_uncore *uncore,
>u64 *start, u32 *size)
> {
> - if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_B0))
> + if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
> return false;
>
> *start = 0;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4c0c15bbdac2..62321e9149db 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -,7 +,7 @@ dg1_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> gen12_gt_workarounds_init(i915, wal);
>
> /* Wa_1607087056:dg1 */
> - if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
> + if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
> wa_write_or(wal,
> SLICE_UNIT_LEVEL_CLKGATE,
> L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); @@ -
> 1522,7 +1522,7 @@ static void dg1_whitelist_build(struct intel_engine_cs
> *engine)
> tgl_whitelist_build(engine);
>
> /* GEN:BUG:1409280441:dg1 */
> - if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
> + if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
> (engine->class == RENDER_CLASS ||
>engine->class == COPY_ENGINE_CLASS))
> whitelist_reg_ext(w, RING_ID(engine->mmio_base), @@ -
> 1592,7 +1592,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal) {
> struct drm_i915_private *i915 = engine->i915;
>
> - if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> + if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
> IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
> /*
>* Wa_1607138336:tgl[a0],dg1[a0]
> @@ -1638,7 +1638,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> }
>
> if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
> - IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> + IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
> wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> @@ -1652,7 +1652,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> }
>
>
> - if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> + if (IS_DG1_GT_STEP(i915, ST
Re: [Intel-gfx] [PATCH v2 09/12] drm/i915/rkl: Use revid->stepping tables
> -Original Message-
> From: Roper, Matthew D
> Sent: Monday, July 12, 2021 3:56 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v2 09/12] drm/i915/rkl: Use revid->stepping tables
>
> On Mon, Jul 12, 2021 at 03:51:15PM -0700, Srivatsa, Anusha wrote:
> >
> >
> > > -Original Message-
> > > From: Roper, Matthew D
> > > Sent: Friday, July 9, 2021 8:37 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Srivatsa, Anusha ; Roper, Matthew D
> > >
> > > Subject: [PATCH v2 09/12] drm/i915/rkl: Use revid->stepping tables
> > >
> > > Switch RKL to use a revid->stepping table as we're trying to do on
> > > all platforms going forward.
> > >
> > > Bspec: 44501
> > > Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
> > > ---
> > > drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
> > > drivers/gpu/drm/i915/i915_drv.h | 8 ++--
> > > drivers/gpu/drm/i915/intel_step.c| 9 +
> > > 3 files changed, 13 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 9643624fe160..74b2aa3c2946 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -594,7 +594,7 @@ static void hsw_activate_psr2(struct intel_dp
> > > *intel_dp)
> > > if (intel_dp->psr.psr2_sel_fetch_enabled) {
> > > /* WA 1408330847 */
> > > if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> > > - IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> > > + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> > > intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > >DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > >DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> @@ -1342,7 +1342,7 @@
> > > static void intel_psr_disable_locked(struct intel_dp
> > > *intel_dp)
> > > /* WA 1408330847 */
> > > if (intel_dp->psr.psr2_sel_fetch_enabled &&
> > > (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> > > - IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> > > + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)))
> > > intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > >DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h index b3ce2b73a143..9195131cf90f
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1549,12 +1549,8 @@ IS_SUBPLATFORM(const struct
> drm_i915_private
> > > *i915,
> > > (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915))
> > > && \
> > >IS_GT_STEP(__i915, since, until))
> > >
> > > -#define RKL_REVID_A0 0x0
> > > -#define RKL_REVID_B0 0x1
> > > -#define RKL_REVID_C0 0x4
> > > -
> > > -#define IS_RKL_REVID(p, since, until) \
> > > - (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
> > > +#define IS_RKL_DISPLAY_STEP(p, since, until) \
> > > + (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
> > >
> >
> > If a platform has the same gt and display stepping, I wonder if we
> > should stick to using IS__GT_STEP while replacing
> > IS_REVID instances. The previous patches have
> > IS__GT_STEP.
> > Just a thought.
>
> No, we want to be very explicit about which IP block the stepping belongs to
> to avoid mistakes. Just because the steppings are equivalent right now
> doesn't mean a new revision won't show up in the future that has different
> GT vs display steppings. In that case it's easy to update the table, but we
> don't want to have to dig through the rest of the code looking for places
> where we used the wrong macro. Plus, intentionally using the wrong macro
> on a platform where it doesn't matter is going to lead to copy/paste errors
> when people add additional platforms to a workaround.
>
>
> Matt
>
> >
> > Anusha
> >
> > > #define DG1_REVID_A0 0x0
> > > #define DG1_REVID_B0 0x1
> > > diff --git a/drivers/gpu/drm/i915
Re: [Intel-gfx] [PATCH v3 08/12] drm/i915/jsl_ehl: Use revid->stepping tables
> -Original Message-
> From: Roper, Matthew D
> Sent: Tuesday, July 13, 2021 9:15 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Roper, Matthew D
>
> Subject: [PATCH v3 08/12] drm/i915/jsl_ehl: Use revid->stepping tables
>
> Switch JSL/EHL to use a revid->stepping table as we're trying to do on all
> platforms going forward.
>
> v2:
> - Use COMMON_STEPPING(). (Anusha)
>
> Bspec: 29153
> Cc: Anusha Srivatsa
> Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 9 -
> drivers/gpu/drm/i915/intel_step.c | 8
> 4 files changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 882bfd499e55..dfc31b682848 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2674,7 +2674,7 @@ static bool
> ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) {
> return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
> - IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER))
> ||
> + IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER))
> ||
>IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
>i915->dpll.ref_clks.nssc == 38400;
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e2d8acb8c1c9..4c0c15bbdac2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1043,7 +1043,7 @@ icl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
>
> /* Wa_1607087056:icl,ehl,jsl */
> if (IS_ICELAKE(i915) ||
> - IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0))
> + IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))
> wa_write_or(wal,
> SLICE_UNIT_LEVEL_CLKGATE,
> L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); diff --
> git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d4f705f06c73..b3ce2b73a143 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1532,11 +1532,10 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915, #define IS_ICL_GT_STEP(p, since, until) \
> (IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
>
> -#define EHL_REVID_A00x0
> -#define EHL_REVID_B00x1
> -
> -#define IS_JSL_EHL_REVID(p, since, until) \
> - (IS_JSL_EHL(p) && IS_REVID(p, since, until))
> +#define IS_JSL_EHL_GT_STEP(p, since, until) \
> + (IS_JSL_EHL(p) && IS_GT_STEP(p, since, until)) #define
> +IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
> + (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
>
> #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
> (IS_TIGERLAKE(__i915) && \
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index f8be464d1179..868606f8139f 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -57,6 +57,11 @@ static const struct intel_step_info icl_revids[] = {
> [7] = { COMMON_STEPPING(D0) },
> };
>
> +static const struct intel_step_info jsl_ehl_revids[] = {
> + [0] = { COMMON_STEPPING(A0) },
> + [1] = { COMMON_STEPPING(B0) },
> +};
> +
> static const struct intel_step_info tgl_uy_revids[] = {
> [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> [1] = { .gt_step = STEP_B0, .display_step = STEP_C0 }, @@ -104,6
> +109,9 @@ void intel_step_init(struct drm_i915_private *i915)
> } else if (IS_TIGERLAKE(i915)) {
> revids = tgl_revids;
> size = ARRAY_SIZE(tgl_revids);
> + } else if (IS_JSL_EHL(i915)) {
> + revids = jsl_ehl_revids;
> + size = ARRAY_SIZE(jsl_ehl_revids);
> } else if (IS_ICELAKE(i915)) {
> revids = icl_revids;
> size = ARRAY_SIZE(icl_revids);
> --
> 2.25.4
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 05/12] drm/i915/bxt: Use revid->stepping tables
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Roper, Matthew D
>
> Subject: [PATCH v2 05/12] drm/i915/bxt: Use revid->stepping tables
>
> Switch BXT to use a revid->stepping table as we're trying to do on all
> platforms going forward. Note that the REVID macros we had before
> weren't being used anywhere in the code and weren't even correct; the
> table values come from the bspec (and omits all the placeholder and
> preproduction revisions).
>
> Although nothing in the code is using the data from this table at the moment,
> we expect some upcoming DMC patches to start utilizing it.
>
> Bspec: 13620
> Cc: Anusha Srivatsa
> Signed-off-by: Matt Roper
Thanks for the patch,
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915_drv.h | 9 -
> drivers/gpu/drm/i915/intel_step.c | 10 ++
> 2 files changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index f30499ed6787..afb159f2a658
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1517,15 +1517,6 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
>
> #define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p,
> since, until))
>
> -#define BXT_REVID_A0 0x0
> -#define BXT_REVID_A1 0x1
> -#define BXT_REVID_B0 0x3
> -#define BXT_REVID_B_LAST 0x8
> -#define BXT_REVID_C0 0x9
> -
> -#define IS_BXT_REVID(dev_priv, since, until) \
> - (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
> -
> #define IS_KBL_GT_STEP(dev_priv, since, until) \
> (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
> #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \ diff --git
> a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
> index 8987453aa172..41e3904ae6e8 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -42,6 +42,13 @@ static const struct intel_step_info kbl_revids[] = {
> [7] = { .gt_step = STEP_G0, .display_step = STEP_C0 }, };
>
> +static const struct intel_step_info bxt_revids[] = {
> + [0xA] = { COMMON_STEPPING(C0) },
> + [0xB] = { COMMON_STEPPING(C0) },
> + [0xC] = { COMMON_STEPPING(D0) },
> + [0xD] = { COMMON_STEPPING(E0) },
> +};
> +
> static const struct intel_step_info tgl_uy_revids[] = {
> [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> [1] = { .gt_step = STEP_B0, .display_step = STEP_C0 }, @@ -89,6 +96,9
> @@ void intel_step_init(struct drm_i915_private *i915)
> } else if (IS_TIGERLAKE(i915)) {
> revids = tgl_revids;
> size = ARRAY_SIZE(tgl_revids);
> + } else if (IS_BROXTON(i915)) {
> + revids = bxt_revids;
> + size = ARRAY_SIZE(bxt_revids);
> } else if (IS_KABYLAKE(i915)) {
> revids = kbl_revids;
> size = ARRAY_SIZE(kbl_revids);
> --
> 2.25.4
___
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Re: [Intel-gfx] [PATCH v2 03/12] drm/i915/skl: Use revid->stepping tables
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Roper, Matthew D
>
> Subject: [PATCH v2 03/12] drm/i915/skl: Use revid->stepping tables
>
> Switch SKL to use a revid->stepping table as we're trying to do on all
> platforms going forward. Also drop the preproduction revisions and add the
> newer steppings we hadn't already handled.
>
> Note that SKL has a case where a newer revision ID corresponds to an older
> GT/disp stepping (0x9 -> STEP_J0, 0xA -> STEP_I1). Also, the lack of a
> revision
> ID 0x8 in the table is intentional and not an oversight.
> We'll re-write the KBL-specific comment to make it clear that these kind of
> quirks are expected.
>
> v2:
> - Since GT and display steppings are always identical on SKL use a
>macro to set both values at once in a more readable manner. (Anusha)
> - Drop preproduction steppings.
>
> Bspec: 13626
> Cc: Anusha Srivatsa
> Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 11 +---
> drivers/gpu/drm/i915/intel_step.c | 30 +
> drivers/gpu/drm/i915/intel_step.h | 4 +++
> 4 files changed, 31 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d9a5a445ceec..6dfd564e078f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -883,7 +883,7 @@ skl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
>
> /* WaInPlaceDecompressionHang:skl */
> - if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER))
> + if (IS_SKL_GT_STEP(i915, STEP_H0, STEP_FOREVER))
> wa_write_or(wal,
> GEN9_GAMT_ECO_REG_RW_IA,
> GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index c4747f4407ef..f30499ed6787
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1515,16 +1515,7 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915, #define IS_TGL_Y(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE,
> INTEL_SUBPLATFORM_ULX)
>
> -#define SKL_REVID_A0 0x0
> -#define SKL_REVID_B0 0x1
> -#define SKL_REVID_C0 0x2
> -#define SKL_REVID_D0 0x3
> -#define SKL_REVID_E0 0x4
> -#define SKL_REVID_F0 0x5
> -#define SKL_REVID_G0 0x6
> -#define SKL_REVID_H0 0x7
> -
> -#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since,
> until))
> +#define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p,
> +since, until))
>
> #define BXT_REVID_A0 0x0
> #define BXT_REVID_A1 0x1
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index 93ccd42f2514..69c928b046e8 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -7,14 +7,31 @@
> #include "intel_step.h"
>
> /*
> - * KBL revision ID ordering is bizarre; higher revision ID's map to lower
> - * steppings in some cases. So rather than test against the revision ID
> - * directly, let's map that into our own range of increasing ID's that we
> - * can test against in a regular manner.
> + * Some platforms have unusual ways of mapping PCI revision ID to
> + GT/display
> + * steppings. E.g., in some cases a higher PCI revision may translate
> + to a
> + * lower stepping of the GT and/or display IP. This file provides
> + lookup
> + * tables to map the PCI revision into a standard set of stepping
> + values that
> + * can be compared numerically.
> + *
> + * Also note that some revisions/steppings may have been set aside as
> + * placeholders but never materialized in real hardware; in those cases
> + there
> + * may be jumps in the revision IDs or stepping values in the tables below.
> */
>
> +/*
> + * Some platforms always have the same stepping value for GT and
> +display;
> + * use a macro to define these to make it easier to identify the
> +platforms
> + * where the two steppings can deviate.
> + */
> +#define COMMON_STEPPING(x) .gt_step = STEP_##x, .display_step =
> +STEP_##x
> +
> +static const struct intel_step_info skl_revids[] = {
> + [0x6] =
Re: [Intel-gfx] [PATCH v2 11/12] drm/i915/cnl: Drop all workarounds
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Roper, Matthew D
>
> Subject: [PATCH v2 11/12] drm/i915/cnl: Drop all workarounds
>
> All of the Cannon Lake hardware that came out had graphics fused off, and
> our userspace drivers have already dropped their support for the platform;
> CNL-specific code in i915 that isn't inherited by subsequent platforms is
> effectively dead code. Let's remove all of the CNL-specific workarounds as a
> quick and easy first step.
>
> References: https://gitlab.freedesktop.org/mesa/mesa/-
> /merge_requests/6899
> Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 55 -
> drivers/gpu/drm/i915/i915_drv.h | 7 ---
> 2 files changed, 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 62321e9149db..9b257a394305 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -514,35 +514,6 @@ static void cfl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> }
>
> -static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine,
> - struct i915_wa_list *wal)
> -{
> - /* WaForceContextSaveRestoreNonCoherent:cnl */
> - wa_masked_en(wal, CNL_HDC_CHICKEN0,
> -
> HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> -
> - /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
> - wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
> - GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> -
> - /* WaPushConstantDereferenceHoldDisable:cnl */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> PUSH_CONSTANT_DEREF_DISABLE);
> -
> - /* FtrEnableFastAnisoL1BankingFix:cnl */
> - wa_masked_en(wal, HALF_SLICE_CHICKEN3,
> CNL_FAST_ANISO_L1_BANKING_FIX);
> -
> - /* WaDisable3DMidCmdPreemption:cnl */
> - wa_masked_dis(wal, GEN8_CS_CHICKEN1,
> GEN9_PREEMPT_3D_OBJECT_LEVEL);
> -
> - /* WaDisableGPGPUMidCmdPreemption:cnl */
> - wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
> - GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> - GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
> -
> - /* WaDisableEarlyEOT:cnl */
> - wa_masked_en(wal, GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);
> -}
> -
> static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>struct i915_wa_list *wal)
> {
> @@ -704,8 +675,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs
> *engine,
> gen12_ctx_workarounds_init(engine, wal);
> else if (GRAPHICS_VER(i915) == 11)
> icl_ctx_workarounds_init(engine, wal);
> - else if (IS_CANNONLAKE(i915))
> - cnl_ctx_workarounds_init(engine, wal);
> else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
> cfl_ctx_workarounds_init(engine, wal);
> else if (IS_GEMINILAKE(i915))
> @@ -982,15 +951,6 @@ icl_wa_init_mcr(struct drm_i915_private *i915,
> struct i915_wa_list *wal)
> wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); }
>
> -static void
> -cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
> *wal) -{
> - /* WaInPlaceDecompressionHang:cnl */
> - wa_write_or(wal,
> - GEN9_GAMT_ECO_REG_RW_IA,
> - GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> -}
> -
> static void
> icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
> *wal) { @@ -1140,8 +1100,6 @@ gt_init_workarounds(struct
> drm_i915_private *i915, struct i915_wa_list *wal)
> gen12_gt_workarounds_init(i915, wal);
> else if (GRAPHICS_VER(i915) == 11)
> icl_gt_workarounds_init(i915, wal);
> - else if (IS_CANNONLAKE(i915))
> - cnl_gt_workarounds_init(i915, wal);
> else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
> cfl_gt_workarounds_init(i915, wal);
> else if (IS_GEMINILAKE(i915))
> @@ -1418,17 +1376,6 @@ static void cml_whitelist_build(struct
> intel_engine_cs *engine)
> cfl_whitelist_build(engine);
> }
>
> -static void cnl_whitelist_build(struct intel_engine_cs *engine) -{
> - struct i915_wa_list *w = &engine->whitelist;
> -
> - if (engine->class != RENDER_CLASS)
> - return;
> -
> - /* WaEnablePreemptionGranularityControlByUMD:cnl */
> - whitelist_reg(w,
Re: [Intel-gfx] [PATCH v2 09/12] drm/i915/rkl: Use revid->stepping tables
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Roper, Matthew D
>
> Subject: [PATCH v2 09/12] drm/i915/rkl: Use revid->stepping tables
>
> Switch RKL to use a revid->stepping table as we're trying to do on all
> platforms going forward.
>
> Bspec: 44501
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 8 ++--
> drivers/gpu/drm/i915/intel_step.c| 9 +
> 3 files changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9643624fe160..74b2aa3c2946 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -594,7 +594,7 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
> if (intel_dp->psr.psr2_sel_fetch_enabled) {
> /* WA 1408330847 */
> if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> - IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>DIS_RAM_BYPASS_PSR2_MAN_TRACK,
>DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> @@ -1342,7 +1342,7 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
> /* WA 1408330847 */
> if (intel_dp->psr.psr2_sel_fetch_enabled &&
> (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
> - IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index b3ce2b73a143..9195131cf90f
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1549,12 +1549,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915))
> && \
>IS_GT_STEP(__i915, since, until))
>
> -#define RKL_REVID_A0 0x0
> -#define RKL_REVID_B0 0x1
> -#define RKL_REVID_C0 0x4
> -
> -#define IS_RKL_REVID(p, since, until) \
> - (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
> +#define IS_RKL_DISPLAY_STEP(p, since, until) \
> + (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
>
If a platform has the same gt and display stepping, I wonder if we should stick
to using IS__GT_STEP while replacing IS_REVID instances.
The previous patches have IS__GT_STEP.
Just a thought.
Anusha
> #define DG1_REVID_A0 0x0
> #define DG1_REVID_B0 0x1
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index 6e1b132ecf38..21211649e6bb 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -75,6 +75,12 @@ static const struct intel_step_info tgl_revids[] = {
> [1] = { .gt_step = STEP_B0, .display_step = STEP_D0 }, };
>
> +static const struct intel_step_info rkl_revids[] = {
> + [0] = { COMMON_STEPPING(A0) },
> + [1] = { COMMON_STEPPING(B0) },
> + [4] = { COMMON_STEPPING(C0) },
> +};
> +
> static const struct intel_step_info adls_revids[] = {
> [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> [0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 }, @@ -103,6
> +109,9 @@ void intel_step_init(struct drm_i915_private *i915)
> } else if (IS_ALDERLAKE_S(i915)) {
> revids = adls_revids;
> size = ARRAY_SIZE(adls_revids);
> + } else if (IS_ROCKETLAKE(i915)) {
> + revids = rkl_revids;
> + size = ARRAY_SIZE(rkl_revids);
> } else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) {
> revids = tgl_uy_revids;
> size = ARRAY_SIZE(tgl_uy_revids);
> --
> 2.25.4
___
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Re: [Intel-gfx] [PATCH v2 08/12] drm/i915/jsl_ehl: Use revid->stepping tables
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Roper, Matthew D
>
> Subject: [PATCH v2 08/12] drm/i915/jsl_ehl: Use revid->stepping tables
>
> Switch JSL/EHL to use a revid->stepping table as we're trying to do on all
> platforms going forward.
>
> Bspec: 29153
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 9 -
> drivers/gpu/drm/i915/intel_step.c | 8
> 4 files changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 882bfd499e55..dfc31b682848 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2674,7 +2674,7 @@ static bool
> ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) {
> return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
> - IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER))
> ||
> + IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER))
> ||
>IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
>i915->dpll.ref_clks.nssc == 38400;
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e2d8acb8c1c9..4c0c15bbdac2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1043,7 +1043,7 @@ icl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
>
> /* Wa_1607087056:icl,ehl,jsl */
> if (IS_ICELAKE(i915) ||
> - IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0))
> + IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))
> wa_write_or(wal,
> SLICE_UNIT_LEVEL_CLKGATE,
> L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); diff --
> git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d4f705f06c73..b3ce2b73a143 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1532,11 +1532,10 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915, #define IS_ICL_GT_STEP(p, since, until) \
> (IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
>
> -#define EHL_REVID_A00x0
> -#define EHL_REVID_B00x1
> -
> -#define IS_JSL_EHL_REVID(p, since, until) \
> - (IS_JSL_EHL(p) && IS_REVID(p, since, until))
> +#define IS_JSL_EHL_GT_STEP(p, since, until) \
> + (IS_JSL_EHL(p) && IS_GT_STEP(p, since, until)) #define
> +IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
> + (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
>
> #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
> (IS_TIGERLAKE(__i915) && \
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index f8be464d1179..6e1b132ecf38 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -57,6 +57,11 @@ static const struct intel_step_info icl_revids[] = {
> [7] = { COMMON_STEPPING(D0) },
> };
>
> +static const struct intel_step_info jsl_ehl_revids[] = {
> + [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> + [1] = { .gt_step = STEP_B0, .display_step = STEP_B0 }, };
> +
Here COMMON_STEEPING can be used.
Anusha
> static const struct intel_step_info tgl_uy_revids[] = {
> [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> [1] = { .gt_step = STEP_B0, .display_step = STEP_C0 }, @@ -104,6
> +109,9 @@ void intel_step_init(struct drm_i915_private *i915)
> } else if (IS_TIGERLAKE(i915)) {
> revids = tgl_revids;
> size = ARRAY_SIZE(tgl_revids);
> + } else if (IS_JSL_EHL(i915)) {
> + revids = jsl_ehl_revids;
> + size = ARRAY_SIZE(jsl_ehl_revids);
> } else if (IS_ICELAKE(i915)) {
> revids = icl_revids;
> size = ARRAY_SIZE(icl_revids);
> --
> 2.25.4
___
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Re: [Intel-gfx] [PATCH v2 06/12] drm/i915/glk: Use revid->stepping tables
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, July 9, 2021 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha ; Roper, Matthew D
>
> Subject: [PATCH v2 06/12] drm/i915/glk: Use revid->stepping tables
>
> Switch GLK to use a revid->stepping table as we're trying to do on all
> platforms going forward. Pre-production and placeholder revisions are
> omitted.
>
> Although nothing in the code is using the data from this table at the moment,
> we expect some upcoming DMC patches to start utilizing it.
>
> Bspec: 19131
> Cc: Anusha Srivatsa
> Signed-off-by: Matt Roper
> ---
Reviewed-by: Anusha Srivatsa
> drivers/gpu/drm/i915/i915_drv.h | 8
> drivers/gpu/drm/i915/intel_step.c | 7 +++
> 2 files changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index afb159f2a658..dac9ed2dfca5
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1522,14 +1522,6 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915, #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
> (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since,
> until))
>
> -#define GLK_REVID_A0 0x0
> -#define GLK_REVID_A1 0x1
> -#define GLK_REVID_A2 0x2
> -#define GLK_REVID_B0 0x3
> -
> -#define IS_GLK_REVID(dev_priv, since, until) \
> - (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
> -
> #define CNL_REVID_A0 0x0
> #define CNL_REVID_B0 0x1
> #define CNL_REVID_C0 0x2
> diff --git a/drivers/gpu/drm/i915/intel_step.c
> b/drivers/gpu/drm/i915/intel_step.c
> index 41e3904ae6e8..7f8fe5e4c039 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -49,6 +49,10 @@ static const struct intel_step_info bxt_revids[] = {
> [0xD] = { COMMON_STEPPING(E0) },
> };
>
> +static const struct intel_step_info glk_revids[] = {
> + [3] = { COMMON_STEPPING(B0) },
> +};
> +
> static const struct intel_step_info tgl_uy_revids[] = {
> [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> [1] = { .gt_step = STEP_B0, .display_step = STEP_C0 }, @@ -96,6
> +100,9 @@ void intel_step_init(struct drm_i915_private *i915)
> } else if (IS_TIGERLAKE(i915)) {
> revids = tgl_revids;
> size = ARRAY_SIZE(tgl_revids);
> + } else if (IS_GEMINILAKE(i915)) {
> + revids = glk_revids;
> + size = ARRAY_SIZE(glk_revids);
> } else if (IS_BROXTON(i915)) {
> revids = bxt_revids;
> size = ARRAY_SIZE(bxt_revids);
> --
> 2.25.4
___
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Re: [Intel-gfx] [PATCH 1/7] drm/i915: Make pre-production detection use direct revid comparison
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, July 9, 2021 8:43 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Jani Nikula
> Subject: Re: [Intel-gfx] [PATCH 1/7] drm/i915: Make pre-production
> detection use direct revid comparison
>
> On Thu, Jul 08, 2021 at 11:08:46AM -0700, Srivatsa, Anusha wrote:
> >
> >
> > > -Original Message-
> > > From: Intel-gfx On Behalf
> > > Of Matt Roper
> > > Sent: Wednesday, July 7, 2021 10:38 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Subject: [Intel-gfx] [PATCH 1/7] drm/i915: Make pre-production
> > > detection use direct revid comparison
> > >
> > > Although we're converting our workarounds to use a revid->stepping
> > > lookup table, the function that detects pre-production hardware
> > > should continue to compare against PCI revision ID values directly.
> > > These are listed in the bspec as integers, so it's easier to confirm
> > > their correctness if we just use an integer literal rather than a symbolic
> name anyway.
> > >
> > > Since the BXT, GLK, and CNL revid macros were never used in any
> > > workaround code, just remove them completely.
> > >
> > > Bspec: 13620, 19131, 13626, 18329
> > > Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 8
> > > drivers/gpu/drm/i915/i915_drv.h | 24
> > > drivers/gpu/drm/i915/intel_step.h | 1 +
> > > 3 files changed, 5 insertions(+), 28 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > b/drivers/gpu/drm/i915/i915_drv.c index 30d8cd8c69b1..90136995f5eb
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -271,10 +271,10 @@ static void
> > > intel_detect_preproduction_hw(struct
> > > drm_i915_private *dev_priv)
> > > bool pre = false;
> > >
> > > pre |= IS_HSW_EARLY_SDV(dev_priv);
> > > - pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
> > > - pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
> > > - pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
> > > - pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
> > > + pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
> > > + pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
> > > + pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> > > + pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
> > >
> > > if (pre) {
> > > drm_err(&dev_priv->drm, "This is a pre-production stepping.
> > > "
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h index 6dff4ca01241..796e6838bc79
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1473,35 +1473,11 @@ IS_SUBPLATFORM(const struct
> drm_i915_private
> > > *i915,
> > >
> > > #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p,
> > > since,
> > > until))
> > >
> > > -#define BXT_REVID_A0 0x0
> > > -#define BXT_REVID_A1 0x1
> > > -#define BXT_REVID_B0 0x3
> > > -#define BXT_REVID_B_LAST 0x8
> > > -#define BXT_REVID_C0 0x9
> > > -
> > > -#define IS_BXT_REVID(dev_priv, since, until) \
> > > - (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
> >
> > Here, we can have IS_BXT_GT_STEP, similar to other platform and use in
> intel_detect_preproduction_hw() above.
> > Same for other platforms - SKL and GLK. KBL already uses IS_KBL_GT_STEP.
>
> Are you going to use that macro in your DMC code? If not, there's no need
> for it since we don't have any stepping-specific workarounds on BXT that
> would use the macro. For now I've only kept the GT and/or display stepping
> macros on platforms that will actually use them (like KBL).
>
> I just sent a v2 of the series that I think should be suitable for you to
> build
> your DMC work on top of (and I included one of the patches from your series
> at the beginning of mine). Note that I punted on adding tables for
> CFL/WHL/AML/CML because the steppings on those platforms are a bit
> weird and I'm not sure exactly what you'll ne
Re: [Intel-gfx] [PATCH 1/7] drm/i915: Make pre-production detection use direct revid comparison
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, July 9, 2021 8:43 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Jani Nikula
> Subject: Re: [Intel-gfx] [PATCH 1/7] drm/i915: Make pre-production
> detection use direct revid comparison
>
> On Thu, Jul 08, 2021 at 11:08:46AM -0700, Srivatsa, Anusha wrote:
> >
> >
> > > -Original Message-
> > > From: Intel-gfx On Behalf
> > > Of Matt Roper
> > > Sent: Wednesday, July 7, 2021 10:38 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Subject: [Intel-gfx] [PATCH 1/7] drm/i915: Make pre-production
> > > detection use direct revid comparison
> > >
> > > Although we're converting our workarounds to use a revid->stepping
> > > lookup table, the function that detects pre-production hardware
> > > should continue to compare against PCI revision ID values directly.
> > > These are listed in the bspec as integers, so it's easier to confirm
> > > their correctness if we just use an integer literal rather than a symbolic
> name anyway.
> > >
> > > Since the BXT, GLK, and CNL revid macros were never used in any
> > > workaround code, just remove them completely.
> > >
> > > Bspec: 13620, 19131, 13626, 18329
> > > Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 8
> > > drivers/gpu/drm/i915/i915_drv.h | 24
> > > drivers/gpu/drm/i915/intel_step.h | 1 +
> > > 3 files changed, 5 insertions(+), 28 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > b/drivers/gpu/drm/i915/i915_drv.c index 30d8cd8c69b1..90136995f5eb
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -271,10 +271,10 @@ static void
> > > intel_detect_preproduction_hw(struct
> > > drm_i915_private *dev_priv)
> > > bool pre = false;
> > >
> > > pre |= IS_HSW_EARLY_SDV(dev_priv);
> > > - pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
> > > - pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
> > > - pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
> > > - pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
> > > + pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
> > > + pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
> > > + pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> > > + pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
> > >
> > > if (pre) {
> > > drm_err(&dev_priv->drm, "This is a pre-production stepping.
> > > "
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h index 6dff4ca01241..796e6838bc79
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1473,35 +1473,11 @@ IS_SUBPLATFORM(const struct
> drm_i915_private
> > > *i915,
> > >
> > > #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p,
> > > since,
> > > until))
> > >
> > > -#define BXT_REVID_A0 0x0
> > > -#define BXT_REVID_A1 0x1
> > > -#define BXT_REVID_B0 0x3
> > > -#define BXT_REVID_B_LAST 0x8
> > > -#define BXT_REVID_C0 0x9
> > > -
> > > -#define IS_BXT_REVID(dev_priv, since, until) \
> > > - (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
> >
> > Here, we can have IS_BXT_GT_STEP, similar to other platform and use in
> intel_detect_preproduction_hw() above.
> > Same for other platforms - SKL and GLK. KBL already uses IS_KBL_GT_STEP.
>
> Are you going to use that macro in your DMC code? If not, there's no need
> for it since we don't have any stepping-specific workarounds on BXT that
> would use the macro. For now I've only kept the GT and/or display stepping
> macros on platforms that will actually use them (like KBL).
>
> I just sent a v2 of the series that I think should be suitable for you to
> build
> your DMC work on top of (and I included one of the patches from your series
> at the beginning of mine). Note that I punted on adding tables for
> CFL/WHL/AML/CML because the steppings on those platforms are a bit
> weird and I'm not sure exactly what you'll ne
Re: [Intel-gfx] [PATCH 09/10] drm/i915/step: Add intel_step_name() helper
> -Original Message-
> From: De Marchi, Lucas
> Sent: Friday, July 9, 2021 10:53 AM
> To: Roper, Matthew D
> Cc: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org; Jani Nikula
> Subject: Re: [Intel-gfx] [PATCH 09/10] drm/i915/step: Add intel_step_name()
> helper
>
> On Thu, Jul 08, 2021 at 09:16:16PM -0700, Matt Roper wrote:
> >On Thu, Jul 08, 2021 at 04:18:20PM -0700, Anusha Srivatsa wrote:
> >> Add a helper to convert the step info to string.
> >> This is specifically useful when we want to load a specific firmware
> >> for a given stepping/substepping combination.
> >
> >What if we use macros to generate the per-stepping code here as well as
> >the stepping values in the enum?
> >
> >In intel_step.h:
> >
> >#define STEPPING_NAME_LIST(func) \
> >func(A0)
> >func(A1)
> >func(A2)
> >func(B0)
> >...
> >
> >#define STEPPING_ENUM_VAL(name) STEP_##name,
> >
> >enum intel_step {
> >STEP_NONE = 0,
> >STEPPING_NAME_LIST(STEPPING_ENUM_VAL)
> >STEP_FUTURE,
> >STEP_FOREVER,
> >};
> >
> >and in intel_step.c:
> >
> >#define STEPPING_NAME_CASE(name)\
> >case STEP_##name: \
> >return #name; \
> >break;
> >
> >const char *intel_step_name(enum intel_step step) {
> >switch(step) {
> >STEPPING_NAME_LIST(STEPPING_NAME_CASE)
> >
> >default:
> >return "**";
> >}
> >}
> >
> >This has the advantage that anytime a new stepping is added (in
> >STEPPING_NAME_LIST) it will generate a new "STEP_XX" enum value and a
> >new case statement to return "XX" as the name; we won't have to
> >remember to update two separate places in the code.
>
> my other idea in the first iterations of this patch was to turn the stepping
> into
> u16 and then do something like (untested crap code below):
>
> #define make_step(a, b) ((a - 'A') << 8, (b - '0'))
>
> #define intel_step_name(s) ({
> char ret[3];
> ret[0] = ((s) >> 8) + 'A';
> ret[1] = ((s) & 0xff) + '0';
> ret[2] = '\0';
> ret;
> })
>
> enum intel_step {
> STEP_NONE = -1,
> STEP_A0 = make_step('A', '0'),
> ...
> }
>
> Or even not bother with the 'A'/'0' addition/subraction since 8 bits is enough
> for all the letters and numbers.
>
> If we keep it u8, then we are limited to step P7 (assuming we have 2
> reserved entries at the end),. It may or may not be sufficient (it currently
> is)
>
> better? worse?
I feel If Matt's solution is more scalable, better to go with it.
Anusha
> Lucas De Marchi
>
> >
> >
> >Matt
> >
> >>
> >> Suggested-by: Jani Nikula
> >> Signed-off-by: Anusha Srivatsa
> >> ---
> >> drivers/gpu/drm/i915/intel_step.c | 58
> >> +++
> drivers/gpu/drm/i915/intel_step.h |
> >> 1 +
> >> 2 files changed, 59 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_step.c
> >> b/drivers/gpu/drm/i915/intel_step.c
> >> index 99c0d3df001b..9af7f30b777e 100644
> >> --- a/drivers/gpu/drm/i915/intel_step.c
> >> +++ b/drivers/gpu/drm/i915/intel_step.c
> >> @@ -182,3 +182,61 @@ void intel_step_init(struct drm_i915_private
> >> *i915)
> >>
> >>RUNTIME_INFO(i915)->step = step;
> >> }
> >> +
> >> +const char *intel_step_name(enum intel_step step) {
> >> + switch (step) {
> >> + case STEP_A0:
> >> + return "A0";
> >> + break;
> >> + case STEP_A1:
> >> + return "A1";
> >> + break;
> >> + case STEP_A2:
> >> + return "A2";
> >> + break;
> >> + case STEP_B0:
> >> + return "B0";
> >> + break;
> >> + case STEP_B1:
> >> + return "B1";
> >> + break;
> >> + case S
[Intel-gfx] [PATCH 09/10] drm/i915/step: Add intel_step_name() helper
Add a helper to convert the step info to string.
This is specifically useful when we want to load a specific
firmware for a given stepping/substepping combination.
Suggested-by: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_step.c | 58 +++
drivers/gpu/drm/i915/intel_step.h | 1 +
2 files changed, 59 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 99c0d3df001b..9af7f30b777e 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -182,3 +182,61 @@ void intel_step_init(struct drm_i915_private *i915)
RUNTIME_INFO(i915)->step = step;
}
+
+const char *intel_step_name(enum intel_step step) {
+ switch (step) {
+ case STEP_A0:
+ return "A0";
+ break;
+ case STEP_A1:
+ return "A1";
+ break;
+ case STEP_A2:
+ return "A2";
+ break;
+ case STEP_B0:
+ return "B0";
+ break;
+ case STEP_B1:
+ return "B1";
+ break;
+ case STEP_B2:
+ return "B2";
+ break;
+ case STEP_C0:
+ return "C0";
+ break;
+ case STEP_C1:
+ return "C1";
+ break;
+ case STEP_D0:
+ return "D0";
+ break;
+ case STEP_D1:
+ return "D1";
+ break;
+ case STEP_E0:
+ return "E0";
+ break;
+ case STEP_F0:
+ return "F0";
+ break;
+ case STEP_G0:
+ return "G0";
+ break;
+ case STEP_H0:
+ return "H0";
+ break;
+ case STEP_I0:
+ return "I0";
+ break;
+ case STEP_I1:
+ return "I1";
+ break;
+ case STEP_J0:
+ return "J0";
+ break;
+ default:
+ return "**";
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_step.h
b/drivers/gpu/drm/i915/intel_step.h
index 3e8b2babd9da..2fbe51483472 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -43,5 +43,6 @@ enum intel_step {
};
void intel_step_init(struct drm_i915_private *i915);
+const char *intel_step_name(enum intel_step step);
#endif /* __INTEL_STEP_H__ */
--
2.32.0
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[Intel-gfx] [PATCH 07/10] drm/i915/cnl: Drop all workarounds
From: Matt Roper
All of the Cannon Lake hardware that came out had graphics fused off,
and our userspace drivers have already dropped their support for the
platform; CNL-specific code in i915 that isn't inherited by subsequent
platforms is effectively dead code. Let's remove all of the
CNL-specific workarounds as a quick and easy first step.
References: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6899
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 55 -
1 file changed, 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 62321e9149db..9b257a394305 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -514,35 +514,6 @@ static void cfl_ctx_workarounds_init(struct
intel_engine_cs *engine,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
}
-static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine,
-struct i915_wa_list *wal)
-{
- /* WaForceContextSaveRestoreNonCoherent:cnl */
- wa_masked_en(wal, CNL_HDC_CHICKEN0,
-HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
-
- /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
- wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
-GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
-
- /* WaPushConstantDereferenceHoldDisable:cnl */
- wa_masked_en(wal, GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
-
- /* FtrEnableFastAnisoL1BankingFix:cnl */
- wa_masked_en(wal, HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
-
- /* WaDisable3DMidCmdPreemption:cnl */
- wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
-
- /* WaDisableGPGPUMidCmdPreemption:cnl */
- wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
- GEN9_PREEMPT_GPGPU_LEVEL_MASK,
- GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
-
- /* WaDisableEarlyEOT:cnl */
- wa_masked_en(wal, GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT);
-}
-
static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
@@ -704,8 +675,6 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
gen12_ctx_workarounds_init(engine, wal);
else if (GRAPHICS_VER(i915) == 11)
icl_ctx_workarounds_init(engine, wal);
- else if (IS_CANNONLAKE(i915))
- cnl_ctx_workarounds_init(engine, wal);
else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
cfl_ctx_workarounds_init(engine, wal);
else if (IS_GEMINILAKE(i915))
@@ -982,15 +951,6 @@ icl_wa_init_mcr(struct drm_i915_private *i915, struct
i915_wa_list *wal)
wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
}
-static void
-cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
-{
- /* WaInPlaceDecompressionHang:cnl */
- wa_write_or(wal,
- GEN9_GAMT_ECO_REG_RW_IA,
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
-}
-
static void
icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
*wal)
{
@@ -1140,8 +1100,6 @@ gt_init_workarounds(struct drm_i915_private *i915, struct
i915_wa_list *wal)
gen12_gt_workarounds_init(i915, wal);
else if (GRAPHICS_VER(i915) == 11)
icl_gt_workarounds_init(i915, wal);
- else if (IS_CANNONLAKE(i915))
- cnl_gt_workarounds_init(i915, wal);
else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
cfl_gt_workarounds_init(i915, wal);
else if (IS_GEMINILAKE(i915))
@@ -1418,17 +1376,6 @@ static void cml_whitelist_build(struct intel_engine_cs
*engine)
cfl_whitelist_build(engine);
}
-static void cnl_whitelist_build(struct intel_engine_cs *engine)
-{
- struct i915_wa_list *w = &engine->whitelist;
-
- if (engine->class != RENDER_CLASS)
- return;
-
- /* WaEnablePreemptionGranularityControlByUMD:cnl */
- whitelist_reg(w, GEN8_CS_CHICKEN1);
-}
-
static void icl_whitelist_build(struct intel_engine_cs *engine)
{
struct i915_wa_list *w = &engine->whitelist;
@@ -1542,8 +1489,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs
*engine)
tgl_whitelist_build(engine);
else if (GRAPHICS_VER(i915) == 11)
icl_whitelist_build(engine);
- else if (IS_CANNONLAKE(i915))
- cnl_whitelist_build(engine);
else if (IS_COMETLAKE(i915))
cml_whitelist_build(engine);
else if (IS_COFFEELAKE(i915))
--
2.32.0
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[Intel-gfx] [PATCH 05/10] drm/i915/rkl: Use revid->stepping tables
From: Matt Roper
Switch RKL to use a revid->stepping table as we're trying to do on all
platforms going forward.
Bspec: 44501
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 8 ++--
drivers/gpu/drm/i915/intel_step.c| 9 +
3 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 9643624fe160..74b2aa3c2946 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -594,7 +594,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (intel_dp->psr.psr2_sel_fetch_enabled) {
/* WA 1408330847 */
if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
- IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
+ IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK,
DIS_RAM_BYPASS_PSR2_MAN_TRACK);
@@ -1342,7 +1342,7 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
/* WA 1408330847 */
if (intel_dp->psr.psr2_sel_fetch_enabled &&
(IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
-IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
+IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 78db92bbb1c6..592e7177202e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1536,12 +1536,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
IS_GT_STEP(__i915, since, until))
-#define RKL_REVID_A0 0x0
-#define RKL_REVID_B0 0x1
-#define RKL_REVID_C0 0x4
-
-#define IS_RKL_REVID(p, since, until) \
- (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
+#define IS_RKL_DISPLAY_STEP(p, since, until) \
+ (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
#define DG1_REVID_A0 0x0
#define DG1_REVID_B0 0x1
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 61666a3dd672..1593ab25f41a 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -69,6 +69,12 @@ static const struct intel_step_info tgl_revid_step_tbl[] = {
[1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },
};
+static const struct intel_step_info rkl_revid_step_tbl[] = {
+ [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+ [1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+ [4] = { .gt_step = STEP_C0, .display_step = STEP_C0 },
+};
+
static const struct intel_step_info adls_revid_step_tbl[] = {
[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
@@ -97,6 +103,9 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ALDERLAKE_S(i915)) {
revids = adls_revid_step_tbl;
size = ARRAY_SIZE(adls_revid_step_tbl);
+ } else if (IS_ROCKETLAKE(i915)) {
+ revids = rkl_revid_step_tbl;
+ size = ARRAY_SIZE(rkl_revid_step_tbl);
} else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) {
revids = tgl_uy_revid_step_tbl;
size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
--
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[Intel-gfx] [PATCH 10/10] drm/i915/dmc: Modify intel_get_stepping_info()
With all platforms having the tepping info in intel_step.c,
it makes no sense to maintain a separate lookup table
in intel_dmc.c Let modify intel_Get_stepping_info()
to grab stepping info from the central location towards
which everything is moving.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 51 +---
1 file changed, 9 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index f8789d4543bf..895bee8f9782 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -247,50 +247,16 @@ bool intel_dmc_has_payload(struct drm_i915_private *i915)
return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
-static const struct stepping_info skl_stepping_info[] = {
- {'A', '0'}, {'B', '0'}, {'C', '0'},
- {'D', '0'}, {'E', '0'}, {'F', '0'},
- {'G', '0'}, {'H', '0'}, {'I', '0'},
- {'J', '0'}, {'K', '0'}
-};
-
-static const struct stepping_info bxt_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '1'}, {'B', '2'}
-};
-
-static const struct stepping_info icl_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '2'},
- {'C', '0'}
-};
-
-static const struct stepping_info no_stepping_info = { '*', '*' };
-
static const struct stepping_info *
-intel_get_stepping_info(struct drm_i915_private *dev_priv)
+intel_get_stepping_info(struct drm_i915_private *dev_priv,
+ struct stepping_info *si)
{
- const struct stepping_info *si;
- unsigned int size;
-
- if (IS_ICELAKE(dev_priv)) {
- size = ARRAY_SIZE(icl_stepping_info);
- si = icl_stepping_info;
- } else if (IS_SKYLAKE(dev_priv)) {
- size = ARRAY_SIZE(skl_stepping_info);
- si = skl_stepping_info;
- } else if (IS_BROXTON(dev_priv)) {
- size = ARRAY_SIZE(bxt_stepping_info);
- si = bxt_stepping_info;
- } else {
- size = 0;
- si = NULL;
- }
-
- if (INTEL_REVID(dev_priv) < size)
- return si + INTEL_REVID(dev_priv);
+ struct intel_step_info step = RUNTIME_INFO(dev_priv)->step;
+ const char *step_name = intel_step_name(step.display_step);
- return &no_stepping_info;
+ si->stepping = step_name[0];
+si->substepping = step_name[1];
+ return si;
}
static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
@@ -616,7 +582,8 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
struct intel_dmc *dmc = &dev_priv->dmc;
- const struct stepping_info *si = intel_get_stepping_info(dev_priv);
+ struct stepping_info display_info = { '*', '*'};
+ const struct stepping_info *si = intel_get_stepping_info(dev_priv,
&display_info);
u32 readcount = 0;
u32 r, offset;
int id;
--
2.32.0
___
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[Intel-gfx] [PATCH 00/10] Get stepping info from RUNTIME_INFO->step
The changes are added on top of Matt's series: https://patchwork.freedesktop.org/series/92299/ This series modifies the way we get stepping indo for DMC to load the right firmware for the right stepping/substepping combinations. Since we have a lookup table for BXT in intel_dmc.c and BXT stepping changes were missing from Matt's series, I have added a patch for it. Anusha Srivatsa (3): drm/i915/bxt: Use revid->stepping tables drm/i915/step: Add intel_step_name() helper drm/i915/dmc: Modify intel_get_stepping_info() Matt Roper (7): drm/i915: Make pre-production detection use direct revid comparison drm/i915/skl: Use revid->stepping tables drm/i915/icl: Use revid->stepping tables drm/i915/jsl_ehl: Use revid->stepping tables drm/i915/rkl: Use revid->stepping tables drm/i915/dg1: Use revid->stepping tables drm/i915/cnl: Drop all workarounds .../drm/i915/display/intel_display_power.c| 2 +- drivers/gpu/drm/i915/display/intel_dmc.c | 51 ++- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 4 +- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 81 ++ drivers/gpu/drm/i915/i915_drv.c | 8 +- drivers/gpu/drm/i915/i915_drv.h | 80 ++ drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_step.c | 142 +- drivers/gpu/drm/i915/intel_step.h | 8 + 11 files changed, 187 insertions(+), 195 deletions(-) -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/10] drm/i915/jsl_ehl: Use revid->stepping tables
From: Matt Roper
Switch JSL/EHL to use a revid->stepping table as we're trying to do on
all platforms going forward.
Bspec: 29153
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 9 -
drivers/gpu/drm/i915/intel_step.c | 8
4 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 882bfd499e55..dfc31b682848 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2674,7 +2674,7 @@ static bool
ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
{
return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
-IS_JSL_EHL_REVID(i915, EHL_REVID_B0, REVID_FOREVER)) ||
+IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&
i915->dpll.ref_clks.nssc == 38400;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e2d8acb8c1c9..4c0c15bbdac2 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1043,7 +1043,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
/* Wa_1607087056:icl,ehl,jsl */
if (IS_ICELAKE(i915) ||
- IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0))
+ IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_A0))
wa_write_or(wal,
SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e26ff8624945..78db92bbb1c6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1519,11 +1519,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ICL_GT_STEP(p, since, until) \
(IS_ICELAKE(p) && IS_GT_STEP(p, since, until))
-#define EHL_REVID_A00x0
-#define EHL_REVID_B00x1
-
-#define IS_JSL_EHL_REVID(p, since, until) \
- (IS_JSL_EHL(p) && IS_REVID(p, since, until))
+#define IS_JSL_EHL_GT_STEP(p, since, until) \
+ (IS_JSL_EHL(p) && IS_GT_STEP(p, since, until))
+#define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
+ (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
#define IS_TGL_DISPLAY_STEP(__i915, since, until) \
(IS_TIGERLAKE(__i915) && \
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 4d8248cf67d3..61666a3dd672 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -51,6 +51,11 @@ static const struct intel_step_info icl_revid_step_tbl[] = {
[7] = { .gt_step = STEP_D0, .display_step = STEP_D0 },
};
+static const struct intel_step_info jsl_ehl_revid_step_tbl[] = {
+ [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+ [1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+};
+
static const struct intel_step_info tgl_uy_revid_step_tbl[] = {
[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
@@ -98,6 +103,9 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_TIGERLAKE(i915)) {
revids = tgl_revid_step_tbl;
size = ARRAY_SIZE(tgl_revid_step_tbl);
+ } else if (IS_JSL_EHL(i915)) {
+ revids = jsl_ehl_revid_step_tbl;
+ size = ARRAY_SIZE(jsl_ehl_revid_step_tbl);
} else if (IS_ICELAKE(i915)) {
revids = icl_revid_step_tbl;
size = ARRAY_SIZE(icl_revid_step_tbl);
--
2.32.0
___
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[Intel-gfx] [PATCH 08/10] drm/i915/bxt: Use revid->stepping tables
Switch BXT to use a revid->stepping table as we're trying to do on all
platforms going forward.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_step.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index c4ce02d22828..99c0d3df001b 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -31,6 +31,15 @@ static const struct intel_step_info skl_revid_step_tbl[] = {
[0xA] = { .gt_step = STEP_I1, .display_step = STEP_I1 },
};
+static const struct intel_step_info bxt_revids[] = {
+ [0] = { .gt_step = STEP_A0 },
+ [1] = { .gt_step = STEP_A1 },
+ [2] = { .gt_step = STEP_A2 },
+ [6] = { .gt_step = STEP_B0 },
+ [7] = { .gt_step = STEP_B1 },
+ [8] = { .gt_step = STEP_B2 },
+};
+
static const struct intel_step_info kbl_revid_step_tbl[] = {
[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
@@ -129,6 +138,9 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_KABYLAKE(i915)) {
revids = kbl_revid_step_tbl;
size = ARRAY_SIZE(kbl_revid_step_tbl);
+ } else if (IS_BROXTON(i915)) {
+ revids = bxt_revids;
+ size = ARRAY_SIZE(bxt_revids);
} else if (IS_SKYLAKE(i915)) {
revids = skl_revid_step_tbl;
size = ARRAY_SIZE(skl_revid_step_tbl);
--
2.32.0
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[Intel-gfx] [PATCH 06/10] drm/i915/dg1: Use revid->stepping tables
From: Matt Roper
Switch DG1 to use a revid->stepping table as we're trying to do on all
platforms going forward.
This removes the last use of IS_REVID() and REVID_FOREVER, so remove
those now-unused macros as well to prevent their accidental use on
future platforms.
Bspec: 44463
Signed-off-by: Matt Roper
---
.../gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/gt/intel_region_lmem.c| 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c| 10 +-
drivers/gpu/drm/i915/i915_drv.h| 18 --
drivers/gpu/drm/i915/intel_pm.c| 2 +-
drivers/gpu/drm/i915/intel_step.c | 8
6 files changed, 20 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 285380079aab..975a7e25cea5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5799,7 +5799,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private
*dev_priv)
int config, i;
if (IS_ALDERLAKE_S(dev_priv) ||
- IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
/* Wa_1409767108:tgl,dg1,adl-s */
table = wa_1409767108_buddy_page_masks;
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 1f43aba2e9e2..50d11a84e7a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
u64 *start, u32 *size)
{
- if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_B0))
+ if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
return false;
*start = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4c0c15bbdac2..62321e9149db 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -,7 +,7 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
gen12_gt_workarounds_init(i915, wal);
/* Wa_1607087056:dg1 */
- if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
+ if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
wa_write_or(wal,
SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1522,7 +1522,7 @@ static void dg1_whitelist_build(struct intel_engine_cs
*engine)
tgl_whitelist_build(engine);
/* GEN:BUG:1409280441:dg1 */
- if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
+ if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
(engine->class == RENDER_CLASS ||
engine->class == COPY_ENGINE_CLASS))
whitelist_reg_ext(w, RING_ID(engine->mmio_base),
@@ -1592,7 +1592,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
/*
* Wa_1607138336:tgl[a0],dg1[a0]
@@ -1638,7 +1638,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
}
if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
- IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
@@ -1652,7 +1652,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
}
- if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/*
* Wa_1607030317:tgl
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 592e7177202e..496c468229fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1317,19 +1317,10 @@ static inline struct drm_i915_private
*pdev_to_i915(struct pci_dev *pdev)
#define IS_DISPLAY_VER(i915, from, until) \
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
-#define REVID_FOREVER 0xff
#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
#define HAS_DSB(dev_priv) (INTEL_IN
[Intel-gfx] [PATCH 02/10] drm/i915/skl: Use revid->stepping tables
From: Matt Roper
Switch SKL to use a revid->stepping table as we're trying to do on all
platforms going forward. Also add some additional stepping definitions
for completeness, even if we don't have any workarounds tied to them.
Note that SKL has a case where a newer revision ID corresponds to an
older GT/disp stepping (0x9 -> STEP_J0, 0xA -> STEP_I1). Also, the lack
of a revision ID 0x8 in the table is intentional and not an oversight.
We'll re-write the KBL-specific comment to make it clear that these kind
of quirks are expected.
Finally, since we're already touching the KBL area too, let's rename the
KBL table to match the naming convention used by all of the other
platforms.
Bspec: 13626
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 11 +--
drivers/gpu/drm/i915/intel_step.c | 35 -
drivers/gpu/drm/i915/intel_step.h | 4 +++
4 files changed, 33 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d9a5a445ceec..6dfd564e078f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -883,7 +883,7 @@ skl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
/* WaInPlaceDecompressionHang:skl */
- if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER))
+ if (IS_SKL_GT_STEP(i915, STEP_H0, STEP_FOREVER))
wa_write_or(wal,
GEN9_GAMT_ECO_REG_RW_IA,
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4f2a61cb024a..775057626ee6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1509,16 +1509,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_TGL_Y(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
-#define SKL_REVID_A0 0x0
-#define SKL_REVID_B0 0x1
-#define SKL_REVID_C0 0x2
-#define SKL_REVID_D0 0x3
-#define SKL_REVID_E0 0x4
-#define SKL_REVID_F0 0x5
-#define SKL_REVID_G0 0x6
-#define SKL_REVID_H0 0x7
-
-#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since,
until))
+#define IS_SKL_GT_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GT_STEP(p, since,
until))
#define IS_KBL_GT_STEP(dev_priv, since, until) \
(IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index ba9479a67521..bfd63f56c200 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -7,15 +7,31 @@
#include "intel_step.h"
/*
- * KBL revision ID ordering is bizarre; higher revision ID's map to lower
- * steppings in some cases. So rather than test against the revision ID
- * directly, let's map that into our own range of increasing ID's that we
- * can test against in a regular manner.
+ * Some platforms have unusual ways of mapping PCI revision ID to GT/display
+ * steppings. E.g., in some cases a higher PCI revision may translate to a
+ * lower stepping of the GT and/or display IP. This file provides lookup
+ * tables to map the PCI revision into a standard set of stepping values that
+ * can be compared numerically.
+ *
+ * Also note that some revisions/steppings may have been set aside as
+ * placeholders but never materialized in real hardware; in those cases there
+ * may be jumps in the revision IDs or stepping values in the tables below.
*/
+static const struct intel_step_info skl_revid_step_tbl[] = {
+ [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+ [0x1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+ [0x2] = { .gt_step = STEP_C0, .display_step = STEP_C0 },
+ [0x3] = { .gt_step = STEP_D0, .display_step = STEP_D0 },
+ [0x4] = { .gt_step = STEP_E0, .display_step = STEP_E0 },
+ [0x5] = { .gt_step = STEP_F0, .display_step = STEP_F0 },
+ [0x6] = { .gt_step = STEP_G0, .display_step = STEP_G0 },
+ [0x7] = { .gt_step = STEP_H0, .display_step = STEP_H0 },
+ [0x9] = { .gt_step = STEP_J0, .display_step = STEP_J0 },
+ [0xA] = { .gt_step = STEP_I1, .display_step = STEP_I1 },
+};
-/* FIXME: what about REVID_E0 */
-static const struct intel_step_info kbl_revids[] = {
+static const struct intel_step_info kbl_revid_step_tbl[] = {
[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
[2] = { .gt_step = STEP_C0, .display_step = STEP_B0 },
@@ -74,8 +90,11 @@ void intel_step_init(struct drm_i915_private *i915)
revids = tgl_revid_step_tbl;
si
[Intel-gfx] [PATCH 03/10] drm/i915/icl: Use revid->stepping tables
From: Matt Roper Switch ICL to use a revid->stepping table as we're trying to do on all platforms going forward. While we're at it, let's include some additional steppings that have popped up, even if we don't yet have any workarounds tied to those steppings (we probably need to audit our workaround list soon to see if any of the bounds have moved or if new workarounds have appeared). Note that the current bspec table is missing information about how to map PCI revision ID to GT/display steppings; it only provides an SoC stepping. The mapping to GT/display steppings (which aren't always the same as the SoC stepping) used to be in the bspec, but was apparently dropped during an update in Nov 2019; I've made my changes here based on an older bspec snapshot that still had the necessary information. We've requested that the missing information be restored. Bspec: 21441 # pre-Nov 2019 snapshot Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++-- drivers/gpu/drm/i915/i915_drv.h | 10 ++ drivers/gpu/drm/i915/intel_step.c | 12 drivers/gpu/drm/i915/intel_step.h | 2 ++ 4 files changed, 22 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6dfd564e078f..e2d8acb8c1c9 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -557,7 +557,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, /* Wa_1604370585:icl (pre-prod) * Formerly known as WaPushConstantDereferenceHoldDisable */ - if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) + if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0)) wa_masked_en(wal, GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); @@ -573,12 +573,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, /* Wa_2006611047:icl (pre-prod) * Formerly known as WaDisableImprovedTdlClkGating */ - if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) + if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0)) wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN11_TDL_CLOCK_GATING_FIX_DISABLE); /* Wa_2006665173:icl (pre-prod) */ - if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) + if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0)) wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC); @@ -1023,13 +1023,13 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) GAMW_ECO_DEV_CTX_RELOAD_DISABLE); /* Wa_1405779004:icl (pre-prod) */ - if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) + if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_A0)) wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, MSCUNIT_CLKGATE_DIS); /* Wa_1406838659:icl (pre-prod) */ - if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) + if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0)) wa_write_or(wal, INF_UNIT_LEVEL_CLKGATE, CGPSF_CLKGATE_DIS); @@ -1725,7 +1725,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) PMFLUSHDONE_LNEBLK); /* Wa_1406609255:icl (pre-prod) */ - if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) + if (IS_ICL_GT_STEP(i915, STEP_A0, STEP_B0)) wa_write_or(wal, GEN7_SARCHKMD, GEN7_DISABLE_DEMAND_PREFETCH); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 775057626ee6..e26ff8624945 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1516,14 +1516,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \ (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until)) -#define ICL_REVID_A0 0x0 -#define ICL_REVID_A2 0x1 -#define ICL_REVID_B0 0x3 -#define ICL_REVID_B2 0x4 -#define ICL_REVID_C0 0x5 - -#define IS_ICL_REVID(p, since, until) \ - (IS_ICELAKE(p) && IS_REVID(p, since, until)) +#define IS_ICL_GT_STEP(p, since, until) \ + (IS_ICELAKE(p) && IS_GT_STEP(p, since, until)) #define EHL_REVID_A00x0 #define EHL_REVID_B00x1 diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index bfd63f56c200..4d8248cf67d3 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -42,6 +42,15 @@ static const struct intel_step_info kbl_revid_step_tbl[]
[Intel-gfx] [PATCH 01/10] drm/i915: Make pre-production detection use direct revid comparison
From: Matt Roper
Although we're converting our workarounds to use a revid->stepping
lookup table, the function that detects pre-production hardware should
continue to compare against PCI revision ID values directly. These are
listed in the bspec as integers, so it's easier to confirm their
correctness if we just use an integer literal rather than a symbolic
name anyway.
Since the BXT, GLK, and CNL revid macros were never used in any
workaround code, just remove them completely.
Bspec: 13620, 19131, 13626, 18329
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.c | 8
drivers/gpu/drm/i915/i915_drv.h | 24
drivers/gpu/drm/i915/intel_step.h | 1 +
3 files changed, 5 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 30d8cd8c69b1..90136995f5eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -271,10 +271,10 @@ static void intel_detect_preproduction_hw(struct
drm_i915_private *dev_priv)
bool pre = false;
pre |= IS_HSW_EARLY_SDV(dev_priv);
- pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
- pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
- pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
- pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
+ pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
+ pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
+ pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
+ pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
if (pre) {
drm_err(&dev_priv->drm, "This is a pre-production stepping. "
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d14cda2ff923..4f2a61cb024a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1520,35 +1520,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since,
until))
-#define BXT_REVID_A0 0x0
-#define BXT_REVID_A1 0x1
-#define BXT_REVID_B0 0x3
-#define BXT_REVID_B_LAST 0x8
-#define BXT_REVID_C0 0x9
-
-#define IS_BXT_REVID(dev_priv, since, until) \
- (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
-
#define IS_KBL_GT_STEP(dev_priv, since, until) \
(IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
#define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
(IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
-#define GLK_REVID_A0 0x0
-#define GLK_REVID_A1 0x1
-#define GLK_REVID_A2 0x2
-#define GLK_REVID_B0 0x3
-
-#define IS_GLK_REVID(dev_priv, since, until) \
- (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
-
-#define CNL_REVID_A0 0x0
-#define CNL_REVID_B0 0x1
-#define CNL_REVID_C0 0x2
-
-#define IS_CNL_REVID(p, since, until) \
- (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
-
#define ICL_REVID_A0 0x0
#define ICL_REVID_A2 0x1
#define ICL_REVID_B0 0x3
diff --git a/drivers/gpu/drm/i915/intel_step.h
b/drivers/gpu/drm/i915/intel_step.h
index 958a8bb5d677..8efacef6ab31 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -22,6 +22,7 @@ struct intel_step_info {
enum intel_step {
STEP_NONE = 0,
STEP_A0,
+ STEP_A1,
STEP_A2,
STEP_B0,
STEP_B1,
--
2.32.0
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Re: [Intel-gfx] [PATCH 0/7] Minor revid/stepping and workaround cleanup
> -Original Message- > From: Roper, Matthew D > Sent: Thursday, July 8, 2021 4:05 PM > To: Srivatsa, Anusha > Cc: Jani Nikula ; intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH 0/7] Minor revid/stepping and workaround cleanup > > On Thu, Jul 08, 2021 at 11:37:50AM -0700, Srivatsa, Anusha wrote: > > > > > > > -Original Message- > > > From: Jani Nikula > > > Sent: Thursday, July 8, 2021 12:33 AM > > > To: Roper, Matthew D ; intel- > > > g...@lists.freedesktop.org > > > Cc: Srivatsa, Anusha > > > Subject: Re: [PATCH 0/7] Minor revid/stepping and workaround cleanup > > > > > > On Wed, 07 Jul 2021, Matt Roper wrote: > > > > PCI revision IDs don't always map to GT and display IP steppings > > > > in an intuitive/sensible way. On many of our recent platforms > > > > we've switched to using revid->stepping lookup tables with the > > > > infrastructure in intel_step.c to handle stepping lookups and > > > > comparisons. Since it's confusing to have some of our platforms > > > > using the new lookup tables and some still using old revid > > > > comparisons, let's migrate all the old platforms over to the table > > > > approach since that's what we want to standardize on going > > > > forward. The only place that revision ID's should really get used > > > > directly now is when checking to see if we're running on pre-production > hardware. > > > > > > Anusha, Matt, please sort this out between the two of you. :) > > > > > > https://patchwork.freedesktop.org/series/92257/ > > > > > @Roper, Matthew D the series doesn't add the steeping table for BXT and > GLK. > > Right, that was intentional because we don't use the steppings for those > platforms anywhere in the code. But if that's changing with your DMC series, > I can add the tables for those two as well. > Yes, will need GLK and BXT Thanks Anusha > Matt > > > > > Anusha > > > BR, > > > Jani. > > > > > > > > > > > > > > Let's also take the opportunity to drop a bit of effectively dead > > > > code in the workarounds file too. > > > > > > > > Cc: Jani Nikula > > > > > > > > Matt Roper (7): > > > > drm/i915: Make pre-production detection use direct revid comparison > > > > drm/i915/skl: Use revid->stepping tables > > > > drm/i915/icl: Use revid->stepping tables > > > > drm/i915/jsl_ehl: Use revid->stepping tables > > > > drm/i915/rkl: Use revid->stepping tables > > > > drm/i915/dg1: Use revid->stepping tables > > > > drm/i915/cnl: Drop all workarounds > > > > > > > > .../drm/i915/display/intel_display_power.c| 2 +- > > > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- > > > > drivers/gpu/drm/i915/display/intel_psr.c | 4 +- > > > > drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +- > > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 81 +++ > > > > drivers/gpu/drm/i915/i915_drv.c | 8 +- > > > > drivers/gpu/drm/i915/i915_drv.h | 80 +++--- > > > > drivers/gpu/drm/i915/intel_pm.c | 2 +- > > > > drivers/gpu/drm/i915/intel_step.c | 72 +++-- > > > > drivers/gpu/drm/i915/intel_step.h | 7 ++ > > > > 10 files changed, 107 insertions(+), 153 deletions(-) > > > > > > -- > > > Jani Nikula, Intel Open Source Graphics Center > > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/7] Minor revid/stepping and workaround cleanup
> -Original Message- > From: Jani Nikula > Sent: Thursday, July 8, 2021 12:33 AM > To: Roper, Matthew D ; intel- > g...@lists.freedesktop.org > Cc: Srivatsa, Anusha > Subject: Re: [PATCH 0/7] Minor revid/stepping and workaround cleanup > > On Wed, 07 Jul 2021, Matt Roper wrote: > > PCI revision IDs don't always map to GT and display IP steppings in an > > intuitive/sensible way. On many of our recent platforms we've > > switched to using revid->stepping lookup tables with the > > infrastructure in intel_step.c to handle stepping lookups and > > comparisons. Since it's confusing to have some of our platforms using > > the new lookup tables and some still using old revid comparisons, > > let's migrate all the old platforms over to the table approach since > > that's what we want to standardize on going forward. The only place > > that revision ID's should really get used directly now is when > > checking to see if we're running on pre-production hardware. > > Anusha, Matt, please sort this out between the two of you. :) > > https://patchwork.freedesktop.org/series/92257/ > @Roper, Matthew D the series doesn't add the steeping table for BXT and GLK. Anusha > BR, > Jani. > > > > > > Let's also take the opportunity to drop a bit of effectively dead code > > in the workarounds file too. > > > > Cc: Jani Nikula > > > > Matt Roper (7): > > drm/i915: Make pre-production detection use direct revid comparison > > drm/i915/skl: Use revid->stepping tables > > drm/i915/icl: Use revid->stepping tables > > drm/i915/jsl_ehl: Use revid->stepping tables > > drm/i915/rkl: Use revid->stepping tables > > drm/i915/dg1: Use revid->stepping tables > > drm/i915/cnl: Drop all workarounds > > > > .../drm/i915/display/intel_display_power.c| 2 +- > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- > > drivers/gpu/drm/i915/display/intel_psr.c | 4 +- > > drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 81 +++ > > drivers/gpu/drm/i915/i915_drv.c | 8 +- > > drivers/gpu/drm/i915/i915_drv.h | 80 +++--- > > drivers/gpu/drm/i915/intel_pm.c | 2 +- > > drivers/gpu/drm/i915/intel_step.c | 72 +++-- > > drivers/gpu/drm/i915/intel_step.h | 7 ++ > > 10 files changed, 107 insertions(+), 153 deletions(-) > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/7] drm/i915/skl: Use revid->stepping tables
_step = STEP_F0, .display_step = STEP_F0 },
> + [0x6] = { .gt_step = STEP_G0, .display_step = STEP_G0 },
> + [0x7] = { .gt_step = STEP_H0, .display_step = STEP_H0 },
> + [0x9] = { .gt_step = STEP_J0, .display_step = STEP_J0 },
> + [0xA] = { .gt_step = STEP_I1, .display_step = STEP_I1 }, };
Feedback I received was to avoid adding .display_step if it is same as .gt_step
and have something like:
if (step.display_step == STEP_NONE)
+ step.display_step = step.gt_step;
In intel_step_init() below.
Anusha
> -/* FIXME: what about REVID_E0 */
> -static const struct intel_step_info kbl_revids[] = {
> +static const struct intel_step_info kbl_revid_step_tbl[] = {
> [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
> [1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
> [2] = { .gt_step = STEP_C0, .display_step = STEP_B0 }, @@ -74,8
> +90,11 @@ void intel_step_init(struct drm_i915_private *i915)
> revids = tgl_revid_step_tbl;
> size = ARRAY_SIZE(tgl_revid_step_tbl);
> } else if (IS_KABYLAKE(i915)) {
> - revids = kbl_revids;
> - size = ARRAY_SIZE(kbl_revids);
> + revids = kbl_revid_step_tbl;
> + size = ARRAY_SIZE(kbl_revid_step_tbl);
> + } else if (IS_SKYLAKE(i915)) {
> + revids = skl_revid_step_tbl;
> + size = ARRAY_SIZE(skl_revid_step_tbl);
> }
>
> /* Not using the stepping scheme for the platform yet. */ diff --git
> a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h
> index 8efacef6ab31..41567d9b7c35 100644
> --- a/drivers/gpu/drm/i915/intel_step.h
> +++ b/drivers/gpu/drm/i915/intel_step.h
> @@ -32,6 +32,10 @@ enum intel_step {
> STEP_E0,
> STEP_F0,
> STEP_G0,
> + STEP_H0,
> + STEP_I0,
> + STEP_I1,
> + STEP_J0,
> STEP_FUTURE,
> STEP_FOREVER,
> };
> --
> 2.25.4
>
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Re: [Intel-gfx] [PATCH 1/7] drm/i915: Make pre-production detection use direct revid comparison
> -Original Message-
> From: Intel-gfx On Behalf Of
> Matt Roper
> Sent: Wednesday, July 7, 2021 10:38 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 1/7] drm/i915: Make pre-production detection
> use direct revid comparison
>
> Although we're converting our workarounds to use a revid->stepping lookup
> table, the function that detects pre-production hardware should continue to
> compare against PCI revision ID values directly. These are listed in the
> bspec
> as integers, so it's easier to confirm their correctness if we just use an
> integer
> literal rather than a symbolic name anyway.
>
> Since the BXT, GLK, and CNL revid macros were never used in any
> workaround code, just remove them completely.
>
> Bspec: 13620, 19131, 13626, 18329
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_drv.c | 8
> drivers/gpu/drm/i915/i915_drv.h | 24
> drivers/gpu/drm/i915/intel_step.h | 1 +
> 3 files changed, 5 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c index 30d8cd8c69b1..90136995f5eb
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -271,10 +271,10 @@ static void intel_detect_preproduction_hw(struct
> drm_i915_private *dev_priv)
> bool pre = false;
>
> pre |= IS_HSW_EARLY_SDV(dev_priv);
> - pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
> - pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
> - pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
> - pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
> + pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
> + pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
> + pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> + pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
>
> if (pre) {
> drm_err(&dev_priv->drm, "This is a pre-production stepping.
> "
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 6dff4ca01241..796e6838bc79
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1473,35 +1473,11 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
>
> #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since,
> until))
>
> -#define BXT_REVID_A0 0x0
> -#define BXT_REVID_A1 0x1
> -#define BXT_REVID_B0 0x3
> -#define BXT_REVID_B_LAST 0x8
> -#define BXT_REVID_C0 0x9
> -
> -#define IS_BXT_REVID(dev_priv, since, until) \
> - (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
Here, we can have IS_BXT_GT_STEP, similar to other platform and use in
intel_detect_preproduction_hw() above.
Same for other platforms - SKL and GLK. KBL already uses IS_KBL_GT_STEP.
Anusha
> #define IS_KBL_GT_STEP(dev_priv, since, until) \
> (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
> #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
> (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since,
> until))
>
> -#define GLK_REVID_A0 0x0
> -#define GLK_REVID_A1 0x1
> -#define GLK_REVID_A2 0x2
> -#define GLK_REVID_B0 0x3
> -
> -#define IS_GLK_REVID(dev_priv, since, until) \
> - (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
> -
> -#define CNL_REVID_A0 0x0
> -#define CNL_REVID_B0 0x1
> -#define CNL_REVID_C0 0x2
> -
> -#define IS_CNL_REVID(p, since, until) \
> - (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
> -
> #define ICL_REVID_A0 0x0
> #define ICL_REVID_A2 0x1
> #define ICL_REVID_B0 0x3
> diff --git a/drivers/gpu/drm/i915/intel_step.h
> b/drivers/gpu/drm/i915/intel_step.h
> index 958a8bb5d677..8efacef6ab31 100644
> --- a/drivers/gpu/drm/i915/intel_step.h
> +++ b/drivers/gpu/drm/i915/intel_step.h
> @@ -22,6 +22,7 @@ struct intel_step_info { enum intel_step {
> STEP_NONE = 0,
> STEP_A0,
> + STEP_A1,
> STEP_A2,
> STEP_B0,
> STEP_B1,
> --
> 2.25.4
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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[Intel-gfx] [PATCH 7/8] drm/i915/rkl: s/IS_RKL_REVID/IS_RKL_GT_STEP
Add stepping info table for RKL.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 9 +++--
drivers/gpu/drm/i915/intel_step.c| 9 +
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 9643624fe160..818153007970 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -594,7 +594,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (intel_dp->psr.psr2_sel_fetch_enabled) {
/* WA 1408330847 */
if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
- IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
+ IS_RKL_GT_STEP(dev_priv, STEP_A0, STEP_A0))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK,
DIS_RAM_BYPASS_PSR2_MAN_TRACK);
@@ -1342,7 +1342,7 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
/* WA 1408330847 */
if (intel_dp->psr.psr2_sel_fetch_enabled &&
(IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) ||
-IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
+IS_RKL_GT_STEP(dev_priv, STEP_A0, STEP_A0)))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e9156d1a89a7..74a30d55fcb7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1511,12 +1511,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \
IS_GT_STEP(__i915, since, until))
-#define RKL_REVID_A0 0x0
-#define RKL_REVID_B0 0x1
-#define RKL_REVID_C0 0x4
-
-#define IS_RKL_REVID(p, since, until) \
- (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
+#define IS_RKL_GT_STEP(__i915, since, until) \
+ (IS_ROCKETLAKE(__i915) && \
+IS_GT_STEP(__i915, since, until))
#define DG1_REVID_A0 0x0
#define DG1_REVID_B0 0x1
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index a7144f24921e..2a97d1703e5a 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -76,6 +76,12 @@ static const struct intel_step_info tgl_revids[] = {
[1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },
};
+static const struct intel_step_info rkl_revids[] = {
+ [0x0] = { .gt_step = STEP_A0 },
+ [0x1] = { .gt_step = STEP_B0 },
+ [0x4] = { .gt_step = STEP_C0 },
+};
+
static const struct intel_step_info adls_revids[] = {
[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
@@ -107,6 +113,9 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) {
revids = tgl_uy_revids;
size = ARRAY_SIZE(tgl_uy_revids);
+ } else if (IS_ROCKETLAKE(i915)) {
+ revids = rkl_revids;
+ size = ARRAY_SIZE(rkl_revids);
} else if (IS_TIGERLAKE(i915)) {
revids = tgl_revids;
size = ARRAY_SIZE(tgl_revids);
--
2.32.0
___
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[Intel-gfx] [PATCH 8/8] drm/i915/dg1: s/IS_DG1_REVID/IS_DG1_GT_STEP
Add stepping info table for DG1
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/gt/intel_region_lmem.c| 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c| 10 +-
drivers/gpu/drm/i915/i915_drv.h| 8 +++-
drivers/gpu/drm/i915/intel_pm.c| 2 +-
drivers/gpu/drm/i915/intel_step.c | 8
6 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 285380079aab..b3187a866209 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5799,7 +5799,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private
*dev_priv)
int config, i;
if (IS_ALDERLAKE_S(dev_priv) ||
- IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_DG1_GT_STEP(dev_priv, STEP_A0, STEP_A0) ||
IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
/* Wa_1409767108:tgl,dg1,adl-s */
table = wa_1409767108_buddy_page_masks;
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 1f43aba2e9e2..50d11a84e7a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -157,7 +157,7 @@ intel_gt_setup_fake_lmem(struct intel_gt *gt)
static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
u64 *start, u32 *size)
{
- if (!IS_DG1_REVID(uncore->i915, DG1_REVID_A0, DG1_REVID_B0))
+ if (!IS_DG1_GT_STEP(uncore->i915, STEP_A0, STEP_B0))
return false;
*start = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e2d8acb8c1c9..51af2529e64c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -,7 +,7 @@ dg1_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
gen12_gt_workarounds_init(i915, wal);
/* Wa_1607087056:dg1 */
- if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
+ if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
wa_write_or(wal,
SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1522,7 +1522,7 @@ static void dg1_whitelist_build(struct intel_engine_cs
*engine)
tgl_whitelist_build(engine);
/* GEN:BUG:1409280441:dg1 */
- if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
+ if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_A0) &&
(engine->class == RENDER_CLASS ||
engine->class == COPY_ENGINE_CLASS))
whitelist_reg_ext(w, RING_ID(engine->mmio_base),
@@ -1592,7 +1592,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) {
/*
* Wa_1607138336:tgl[a0],dg1[a0]
@@ -1638,7 +1638,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
}
if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
- IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
@@ -1652,7 +1652,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
}
- if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+ if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/*
* Wa_1607030317:tgl
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 74a30d55fcb7..21fa79071f83 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1515,11 +1515,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_ROCKETLAKE(__i915) && \
IS_GT_STEP(__i915, since, until))
-#define DG1_REVID_A0 0x0
-#define DG1_REVID_B0 0x1
-
-#define IS_DG1_REVID(p, since, until) \
- (IS_DG1(p) && IS_REVID(p, since, until))
+#define IS_DG1_GT_STEP(__i915, since, until) \
+ (IS_DG1(__i915) && \
+IS_GT_STEP(__i915, since, until))
#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
(IS_ALDERLAKE_S(__i915)
[Intel-gfx] [PATCH 6/8] drm/i915/glk: s/IS_GLK_REVID/IS_GLK_GT_STEP
Add stepping info table for GLK.
Remove stepping info table from intel_dmc.c and
instead use the centralized stepping_info from
intel_step.c
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 9 +++--
drivers/gpu/drm/i915/intel_step.c | 10 ++
3 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index eaddb18e4762..9f433194c4e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -274,7 +274,7 @@ static void intel_detect_preproduction_hw(struct
drm_i915_private *dev_priv)
pre |= IS_SKL_GT_STEP(dev_priv, 0, STEP_F0);
pre |= IS_BXT_GT_STEP(dev_priv, 0, STEP_B2);
pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
- pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
+ pre |= IS_GLK_GT_STEP(dev_priv, 0, STEP_A2);
if (pre) {
drm_err(&dev_priv->drm, "This is a pre-production stepping. "
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 217c58c14a88..e9156d1a89a7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1476,13 +1476,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
(IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
-#define GLK_REVID_A0 0x0
-#define GLK_REVID_A1 0x1
-#define GLK_REVID_A2 0x2
-#define GLK_REVID_B0 0x3
+#define IS_GLK_GT_STEP(__i915, since, until) \
+ (IS_GEMINILAKE(__i915) && \
+ IS_GT_STEP(__i915, since, until))
-#define IS_GLK_REVID(dev_priv, since, until) \
- (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
#define CNL_REVID_A0 0x0
#define CNL_REVID_B0 0x1
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index e1e5698d4998..a7144f24921e 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -35,6 +35,13 @@ static const struct intel_step_info bxt_revids[] = {
[8] = { .gt_step = STEP_B2 },
};
+static const struct intel_step_info glk_revids[] = {
+ [0] = { .gt_step = STEP_A0 },
+ [1] = { .gt_step = STEP_A1 },
+ [2] = { .gt_step = STEP_A2 },
+ [3] = { .gt_step = STEP_B0 },
+};
+
static const struct intel_step_info icl_revids[] = {
[0] = { .gt_step = STEP_A0 },
[3] = { .gt_step = STEP_B0 },
@@ -112,6 +119,9 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_BROXTON(i915)) {
revids = bxt_revids;
size = ARRAY_SIZE(bxt_revids);
+ } else if (IS_GEMINILAKE(i915)) {
+ revids = glk_revids;
+ size = ARRAY_SIZE(glk_revids);
} else if (IS_ICELAKE(i915)) {
revids = icl_revids;
size = ARRAY_SIZE(icl_revids);
--
2.32.0
___
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[Intel-gfx] [PATCH 5/8] drm/i915/icl: s/IS_ICL_REVID/IS_ICL_GT_STEP
Add stepping info table for ICL.
Remove stepping info table from intel_dmc.c and
instead use the centralized stepping_info from
intel_step.c
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c| 153 +---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +-
drivers/gpu/drm/i915/i915_drv.h | 12 +-
drivers/gpu/drm/i915/intel_step.c | 12 ++
drivers/gpu/drm/i915/intel_step.h | 1 +
5 files changed, 92 insertions(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index a1fa44ec4ca8..783a3a2a3dd7 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -247,97 +247,82 @@ bool intel_dmc_has_payload(struct drm_i915_private *i915)
return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
-static const struct stepping_info icl_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '2'},
- {'C', '0'}
-};
-
-static const struct stepping_info no_stepping_info = { '*', '*' };
struct stepping_info *display_step;
static const struct stepping_info *
intel_get_stepping_info(struct drm_i915_private *dev_priv)
{
struct intel_step_info step = RUNTIME_INFO(dev_priv)->step;
- const struct stepping_info *si;
- unsigned int size;
- if (IS_ICELAKE(dev_priv)) {
- size = ARRAY_SIZE(icl_stepping_info);
- si = icl_stepping_info;
- }
-
- if (IS_ICELAKE(dev_priv))
- return INTEL_REVID(dev_priv) < size ? si +
INTEL_REVID(dev_priv) : &no_stepping_info;
-
- else {
- switch (step.display_step) {
- case STEP_A0:
- display_step->stepping = 'A';
- display_step->substepping = '0';
- break;
- case STEP_A1:
- display_step->stepping = 'A';
- display_step->substepping = '1';
- break;
- case STEP_A2:
- display_step->stepping = 'A';
- display_step->substepping = '2';
- break;
- case STEP_B0:
- display_step->stepping = 'B';
- display_step->substepping = '0';
- break;
- case STEP_B1:
- display_step->stepping = 'B';
- display_step->substepping = '1';
- break;
- case STEP_B2:
- display_step->stepping = 'B';
- display_step->substepping = '2';
- break;
- case STEP_C0:
- display_step->stepping = 'C';
- display_step->substepping = '0';
- break;
- case STEP_D0:
- display_step->stepping = 'D';
- display_step->substepping = '0';
- break;
- case STEP_D1:
- display_step->stepping = 'D';
- display_step->substepping = '1';
- break;
- case STEP_E0:
- display_step->stepping = 'E';
- display_step->substepping = '0';
- break;
- case STEP_F0:
- display_step->stepping = 'F';
- display_step->substepping = '0';
- break;
- case STEP_G0:
- display_step->stepping = 'G';
- display_step->substepping = '0';
- break;
- case STEP_H0:
- display_step->stepping = 'H';
- display_step->substepping = '0';
- break;
- case STEP_I0:
- display_step->stepping = 'I';
- display_step->substepping = '0';
- break;
- case STEP_J0:
- display_step->stepping = 'J';
- display_step->substepping = '0';
- break;
- default:
- display_step->stepping = '*';
- dis
[Intel-gfx] [PATCH 4/8] drm/i915/bxt: s/IS_BXT_REVID/IS_BXT_GT_STEP
Add stepping info table for BXT.
Remove stepping info table from intel_dmc.c and
instead use the centralized stepping_info from
intel_step.c
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 18 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 11 +++
drivers/gpu/drm/i915/intel_step.c| 12
drivers/gpu/drm/i915/intel_step.h| 2 ++
5 files changed, 27 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 19c8b9022370..a1fa44ec4ca8 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -247,11 +247,6 @@ bool intel_dmc_has_payload(struct drm_i915_private *i915)
return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
-static const struct stepping_info bxt_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '1'}, {'B', '2'}
-};
-
static const struct stepping_info icl_stepping_info[] = {
{'A', '0'}, {'A', '1'}, {'A', '2'},
{'B', '0'}, {'B', '2'},
@@ -271,12 +266,9 @@ intel_get_stepping_info(struct drm_i915_private *dev_priv)
if (IS_ICELAKE(dev_priv)) {
size = ARRAY_SIZE(icl_stepping_info);
si = icl_stepping_info;
- } else if (IS_BROXTON(dev_priv)) {
- size = ARRAY_SIZE(bxt_stepping_info);
- si = bxt_stepping_info;
}
- if (IS_ICELAKE(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_ICELAKE(dev_priv))
return INTEL_REVID(dev_priv) < size ? si +
INTEL_REVID(dev_priv) : &no_stepping_info;
else {
@@ -285,6 +277,10 @@ intel_get_stepping_info(struct drm_i915_private *dev_priv)
display_step->stepping = 'A';
display_step->substepping = '0';
break;
+ case STEP_A1:
+ display_step->stepping = 'A';
+ display_step->substepping = '1';
+ break;
case STEP_A2:
display_step->stepping = 'A';
display_step->substepping = '2';
@@ -297,6 +293,10 @@ intel_get_stepping_info(struct drm_i915_private *dev_priv)
display_step->stepping = 'B';
display_step->substepping = '1';
break;
+ case STEP_B2:
+ display_step->stepping = 'B';
+ display_step->substepping = '2';
+ break;
case STEP_C0:
display_step->stepping = 'C';
display_step->substepping = '0';
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9a4a623ad6d4..eaddb18e4762 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -272,7 +272,7 @@ static void intel_detect_preproduction_hw(struct
drm_i915_private *dev_priv)
pre |= IS_HSW_EARLY_SDV(dev_priv);
pre |= IS_SKL_GT_STEP(dev_priv, 0, STEP_F0);
- pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
+ pre |= IS_BXT_GT_STEP(dev_priv, 0, STEP_B2);
pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b4a7652d0c50..defa084ccd08 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1466,15 +1466,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_SKYLAKE(__i915) && \
IS_GT_STEP(__i915, since, until))
+#define IS_BXT_GT_STEP(__i915, since, until) \
+ (IS_BROXTON(__i915) && \
+IS_GT_STEP(__i915, since, until))
-#define BXT_REVID_A0 0x0
-#define BXT_REVID_A1 0x1
-#define BXT_REVID_B0 0x3
-#define BXT_REVID_B_LAST 0x8
-#define BXT_REVID_C0 0x9
-
-#define IS_BXT_REVID(dev_priv, since, until) \
- (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
#define IS_KBL_GT_STEP(dev_priv, since, until) \
(IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until))
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index 3f07b994d58a..b00c192c6c3d 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -26,6 +26,15 @@ static const s
[Intel-gfx] [PATCH 2/8] drm/i915/dmc: Use RUNTIME_INFO->step for DMC
Instead of adding new table for every new platform, lets ues
the stepping info from RUNTIME_INFO(dev_priv)->step
This patch uses RUNTIME_INFO->step only for recent
platforms.
Patches that follow this will address this change for
remaining platforms + missing platforms.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 61 +---
1 file changed, 54 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index f8789d4543bf..a38720f25910 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -266,10 +266,12 @@ static const struct stepping_info icl_stepping_info[] = {
};
static const struct stepping_info no_stepping_info = { '*', '*' };
+struct stepping_info *display_step;
static const struct stepping_info *
intel_get_stepping_info(struct drm_i915_private *dev_priv)
{
+ struct intel_step_info step = RUNTIME_INFO(dev_priv)->step;
const struct stepping_info *si;
unsigned int size;
@@ -282,15 +284,60 @@ intel_get_stepping_info(struct drm_i915_private *dev_priv)
} else if (IS_BROXTON(dev_priv)) {
size = ARRAY_SIZE(bxt_stepping_info);
si = bxt_stepping_info;
- } else {
- size = 0;
- si = NULL;
}
- if (INTEL_REVID(dev_priv) < size)
- return si + INTEL_REVID(dev_priv);
-
- return &no_stepping_info;
+ if (IS_ICELAKE(dev_priv) || IS_SKYLAKE(dev_priv) ||
IS_BROXTON(dev_priv))
+ return INTEL_REVID(dev_priv) < size ? si +
INTEL_REVID(dev_priv) : &no_stepping_info;
+
+ else {
+ switch (step.display_step) {
+ case STEP_A0:
+ display_step->stepping = 'A';
+ display_step->substepping = '0';
+ break;
+ case STEP_A2:
+ display_step->stepping = 'A';
+ display_step->substepping = '2';
+ break;
+ case STEP_B0:
+ display_step->stepping = 'B';
+ display_step->substepping = '0';
+ break;
+ case STEP_B1:
+ display_step->stepping = 'B';
+ display_step->substepping = '1';
+ break;
+ case STEP_C0:
+ display_step->stepping = 'C';
+ display_step->substepping = '0';
+ break;
+ case STEP_D0:
+ display_step->stepping = 'D';
+ display_step->substepping = '0';
+ break;
+ case STEP_D1:
+ display_step->stepping = 'D';
+ display_step->substepping = '1';
+ break;
+ case STEP_E0:
+ display_step->stepping = 'E';
+ display_step->substepping = '0';
+ break;
+ case STEP_F0:
+ display_step->stepping = 'F';
+ display_step->substepping = '0';
+ break;
+ case STEP_G0:
+ display_step->stepping = 'G';
+ display_step->substepping = '0';
+ break;
+ default:
+ display_step->stepping = '*';
+ display_step->substepping = '*';
+ break;
+ }
+ }
+ return display_step;
}
static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
--
2.32.0
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/8] drm/i915/skl: s/IS_SKL_REVID/IS_SKL_GT_STEP
Start using the latest STEP_ macro for all
purposes.
For SKL, GT step is same as display step, lets us
avoid initializing both
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c| 24 +++--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 14
drivers/gpu/drm/i915/intel_step.c | 18
drivers/gpu/drm/i915/intel_step.h | 3 +++
6 files changed, 40 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index a38720f25910..19c8b9022370 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -247,13 +247,6 @@ bool intel_dmc_has_payload(struct drm_i915_private *i915)
return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
-static const struct stepping_info skl_stepping_info[] = {
- {'A', '0'}, {'B', '0'}, {'C', '0'},
- {'D', '0'}, {'E', '0'}, {'F', '0'},
- {'G', '0'}, {'H', '0'}, {'I', '0'},
- {'J', '0'}, {'K', '0'}
-};
-
static const struct stepping_info bxt_stepping_info[] = {
{'A', '0'}, {'A', '1'}, {'A', '2'},
{'B', '0'}, {'B', '1'}, {'B', '2'}
@@ -278,15 +271,12 @@ intel_get_stepping_info(struct drm_i915_private *dev_priv)
if (IS_ICELAKE(dev_priv)) {
size = ARRAY_SIZE(icl_stepping_info);
si = icl_stepping_info;
- } else if (IS_SKYLAKE(dev_priv)) {
- size = ARRAY_SIZE(skl_stepping_info);
- si = skl_stepping_info;
} else if (IS_BROXTON(dev_priv)) {
size = ARRAY_SIZE(bxt_stepping_info);
si = bxt_stepping_info;
}
- if (IS_ICELAKE(dev_priv) || IS_SKYLAKE(dev_priv) ||
IS_BROXTON(dev_priv))
+ if (IS_ICELAKE(dev_priv) || IS_BROXTON(dev_priv))
return INTEL_REVID(dev_priv) < size ? si +
INTEL_REVID(dev_priv) : &no_stepping_info;
else {
@@ -331,6 +321,18 @@ intel_get_stepping_info(struct drm_i915_private *dev_priv)
display_step->stepping = 'G';
display_step->substepping = '0';
break;
+ case STEP_H0:
+ display_step->stepping = 'H';
+ display_step->substepping = '0';
+ break;
+ case STEP_I0:
+ display_step->stepping = 'I';
+ display_step->substepping = '0';
+ break;
+ case STEP_J0:
+ display_step->stepping = 'J';
+ display_step->substepping = '0';
+ break;
default:
display_step->stepping = '*';
display_step->substepping = '*';
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d9a5a445ceec..6dfd564e078f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -883,7 +883,7 @@ skl_gt_workarounds_init(struct drm_i915_private *i915,
struct i915_wa_list *wal)
GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
/* WaInPlaceDecompressionHang:skl */
- if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER))
+ if (IS_SKL_GT_STEP(i915, STEP_H0, STEP_FOREVER))
wa_write_or(wal,
GEN9_GAMT_ECO_REG_RW_IA,
GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 30d8cd8c69b1..9a4a623ad6d4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -271,7 +271,7 @@ static void intel_detect_preproduction_hw(struct
drm_i915_private *dev_priv)
bool pre = false;
pre |= IS_HSW_EARLY_SDV(dev_priv);
- pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
+ pre |= IS_SKL_GT_STEP(dev_priv, 0, STEP_F0);
pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6dff4ca01241..b4a7652d0c50 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/driver
[Intel-gfx] [PATCH 0/8] Abstract steppings for all platforms
Instead of having a separate lookup table in intel_dmc.c per platform, centralize stepping info in intel_step.c. We already have stepping info table for some platforms in intel_step.c, add stepping information for remaining platforms and use this info to laod specific blob for a given stepping/substepping combination. While at it, change the names of stepping info table to simpler names: s/_revid_step_tbl/_revids Anusha Srivatsa (8): drm/i915/step: s/_revid_tbl/_revids drm/i915/dmc: Use RUNTIME_INFO->step for DMC drm/i915/skl: s/IS_SKL_REVID/IS_SKL_GT_STEP drm/i915/bxt: s/IS_BXT_REVID/IS_BXT_GT_STEP drm/i915/icl: s/IS_ICL_REVID/IS_ICL_GT_STEP drm/i915/glk: s/IS_GLK_REVID/IS_GLK_GT_STEP drm/i915/rkl: s/IS_RKL_REVID/IS_RKL_GT_STEP drm/i915/dg1: s/IS_DG1_REVID/IS_DG1_GT_STEP .../drm/i915/display/intel_display_power.c| 2 +- drivers/gpu/drm/i915/display/intel_dmc.c | 112 -- drivers/gpu/drm/i915/display/intel_psr.c | 4 +- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 ++-- drivers/gpu/drm/i915/i915_drv.c | 6 +- drivers/gpu/drm/i915/i915_drv.h | 63 -- drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_step.c | 93 +-- drivers/gpu/drm/i915/intel_step.h | 6 + 10 files changed, 200 insertions(+), 114 deletions(-) -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/8] drm/i915/step: s/_revid_tbl/_revids
Simplify the stepping info array name.
Cc: Jani Nikula
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_step.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index ba9479a67521..93ccd42f2514 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -26,7 +26,7 @@ static const struct intel_step_info kbl_revids[] = {
[7] = { .gt_step = STEP_G0, .display_step = STEP_C0 },
};
-static const struct intel_step_info tgl_uy_revid_step_tbl[] = {
+static const struct intel_step_info tgl_uy_revids[] = {
[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
[2] = { .gt_step = STEP_B1, .display_step = STEP_C0 },
@@ -34,12 +34,12 @@ static const struct intel_step_info tgl_uy_revid_step_tbl[]
= {
};
/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same
HW */
-static const struct intel_step_info tgl_revid_step_tbl[] = {
+static const struct intel_step_info tgl_revids[] = {
[0] = { .gt_step = STEP_A0, .display_step = STEP_B0 },
[1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },
};
-static const struct intel_step_info adls_revid_step_tbl[] = {
+static const struct intel_step_info adls_revids[] = {
[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
[0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
@@ -47,7 +47,7 @@ static const struct intel_step_info adls_revid_step_tbl[] = {
[0xC] = { .gt_step = STEP_D0, .display_step = STEP_C0 },
};
-static const struct intel_step_info adlp_revid_step_tbl[] = {
+static const struct intel_step_info adlp_revids[] = {
[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
[0x8] = { .gt_step = STEP_C0, .display_step = STEP_C0 },
@@ -62,17 +62,17 @@ void intel_step_init(struct drm_i915_private *i915)
struct intel_step_info step = {};
if (IS_ALDERLAKE_P(i915)) {
- revids = adlp_revid_step_tbl;
- size = ARRAY_SIZE(adlp_revid_step_tbl);
+ revids = adlp_revids;
+ size = ARRAY_SIZE(adlp_revids);
} else if (IS_ALDERLAKE_S(i915)) {
- revids = adls_revid_step_tbl;
- size = ARRAY_SIZE(adls_revid_step_tbl);
+ revids = adls_revids;
+ size = ARRAY_SIZE(adls_revids);
} else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) {
- revids = tgl_uy_revid_step_tbl;
- size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
+ revids = tgl_uy_revids;
+ size = ARRAY_SIZE(tgl_uy_revids);
} else if (IS_TIGERLAKE(i915)) {
- revids = tgl_revid_step_tbl;
- size = ARRAY_SIZE(tgl_revid_step_tbl);
+ revids = tgl_revids;
+ size = ARRAY_SIZE(tgl_revids);
} else if (IS_KABYLAKE(i915)) {
revids = kbl_revids;
size = ARRAY_SIZE(kbl_revids);
--
2.32.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/dmc: Use RUNTIME_INFO->step for DMC
> -Original Message-
> From: Jani Nikula
> Sent: Monday, July 5, 2021 3:01 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Cc: De Marchi, Lucas
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/dmc: Use RUNTIME_INFO-
> >step for DMC
>
> On Thu, 01 Jul 2021, Anusha Srivatsa wrote:
> > On the dmc side,we maintain a lookup table with different display
> > stepping-substepping combinations.
> >
> > Instead of adding new table for every new platform, lets ues the
> > stepping info from RUNTIME_INFO(dev_priv)->step
> >
> > v2: Add stepping table for older platforms in intel_step.c (Lucas)
> >
> > Cc: Lucas De Marchi
> > Signed-off-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/i915/display/intel_dmc.c | 117
> > +++
>
> The changes here...
>
> > drivers/gpu/drm/i915/intel_step.c| 41
> > drivers/gpu/drm/i915/intel_step.h| 7 ++
>
> ...should be separate from, and depend on, the changes here. Please don't
> try to do too much in one patch. Smaller is better.
>
> > 3 files changed, 126 insertions(+), 39 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> > b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index f8789d4543bf..df888a3d086e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -247,50 +247,89 @@ bool intel_dmc_has_payload(struct
> drm_i915_private *i915)
> > return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
> > }
> >
> > -static const struct stepping_info skl_stepping_info[] = {
> > - {'A', '0'}, {'B', '0'}, {'C', '0'},
> > - {'D', '0'}, {'E', '0'}, {'F', '0'},
> > - {'G', '0'}, {'H', '0'}, {'I', '0'},
> > - {'J', '0'}, {'K', '0'}
> > -};
> > -
> > -static const struct stepping_info bxt_stepping_info[] = {
> > - {'A', '0'}, {'A', '1'}, {'A', '2'},
> > - {'B', '0'}, {'B', '1'}, {'B', '2'}
> > -};
> > -
> > -static const struct stepping_info icl_stepping_info[] = {
> > - {'A', '0'}, {'A', '1'}, {'A', '2'},
> > - {'B', '0'}, {'B', '2'},
> > - {'C', '0'}
> > -};
> > -
> > static const struct stepping_info no_stepping_info = { '*', '*' };
> > +struct stepping_info *display_step;
> >
> > -static const struct stepping_info *
> > +static struct stepping_info *
> > intel_get_stepping_info(struct drm_i915_private *dev_priv) {
> > - const struct stepping_info *si;
> > - unsigned int size;
> > -
> > - if (IS_ICELAKE(dev_priv)) {
> > - size = ARRAY_SIZE(icl_stepping_info);
> > - si = icl_stepping_info;
> > - } else if (IS_SKYLAKE(dev_priv)) {
> > - size = ARRAY_SIZE(skl_stepping_info);
> > - si = skl_stepping_info;
> > - } else if (IS_BROXTON(dev_priv)) {
> > - size = ARRAY_SIZE(bxt_stepping_info);
> > - si = bxt_stepping_info;
> > - } else {
> > - size = 0;
> > - si = NULL;
> > + struct intel_step_info step = RUNTIME_INFO(dev_priv)->step;
> > +
> > + switch (step.display_step) {
> > + case STEP_A0:
> > + display_step->stepping = 'A';
> > + display_step->substepping = '0';
> > + break;
> > + case STEP_A1:
> > + display_step->stepping = 'A';
> > + display_step->substepping = '1';
> > + break;
> > + case STEP_A2:
> > + display_step->stepping = 'A';
> > + display_step->substepping = '2';
> > + break;
> > + case STEP_B0:
> > + display_step->stepping = 'B';
> > + display_step->substepping = '0';
> > + break;
> > + case STEP_B1:
> > + display_step->stepping = 'B';
> > + display_step->substepping = '1';
> > + break;
> > + case STEP_B2:
> > + display_step->step
[Intel-gfx] [PATCH 1/2] drm/i915/dmc: Use RUNTIME_INFO->step for DMC
On the dmc side,we maintain a lookup table with different display
stepping-substepping combinations.
Instead of adding new table for every new platform, lets ues
the stepping info from RUNTIME_INFO(dev_priv)->step
v2: Add stepping table for older platforms in intel_step.c (Lucas)
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 117 +++
drivers/gpu/drm/i915/intel_step.c| 41
drivers/gpu/drm/i915/intel_step.h| 7 ++
3 files changed, 126 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index f8789d4543bf..df888a3d086e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -247,50 +247,89 @@ bool intel_dmc_has_payload(struct drm_i915_private *i915)
return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
-static const struct stepping_info skl_stepping_info[] = {
- {'A', '0'}, {'B', '0'}, {'C', '0'},
- {'D', '0'}, {'E', '0'}, {'F', '0'},
- {'G', '0'}, {'H', '0'}, {'I', '0'},
- {'J', '0'}, {'K', '0'}
-};
-
-static const struct stepping_info bxt_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '1'}, {'B', '2'}
-};
-
-static const struct stepping_info icl_stepping_info[] = {
- {'A', '0'}, {'A', '1'}, {'A', '2'},
- {'B', '0'}, {'B', '2'},
- {'C', '0'}
-};
-
static const struct stepping_info no_stepping_info = { '*', '*' };
+struct stepping_info *display_step;
-static const struct stepping_info *
+static struct stepping_info *
intel_get_stepping_info(struct drm_i915_private *dev_priv)
{
- const struct stepping_info *si;
- unsigned int size;
-
- if (IS_ICELAKE(dev_priv)) {
- size = ARRAY_SIZE(icl_stepping_info);
- si = icl_stepping_info;
- } else if (IS_SKYLAKE(dev_priv)) {
- size = ARRAY_SIZE(skl_stepping_info);
- si = skl_stepping_info;
- } else if (IS_BROXTON(dev_priv)) {
- size = ARRAY_SIZE(bxt_stepping_info);
- si = bxt_stepping_info;
- } else {
- size = 0;
- si = NULL;
+ struct intel_step_info step = RUNTIME_INFO(dev_priv)->step;
+
+ switch (step.display_step) {
+ case STEP_A0:
+ display_step->stepping = 'A';
+ display_step->substepping = '0';
+ break;
+ case STEP_A1:
+ display_step->stepping = 'A';
+ display_step->substepping = '1';
+ break;
+ case STEP_A2:
+ display_step->stepping = 'A';
+ display_step->substepping = '2';
+ break;
+ case STEP_B0:
+ display_step->stepping = 'B';
+ display_step->substepping = '0';
+ break;
+ case STEP_B1:
+ display_step->stepping = 'B';
+ display_step->substepping = '1';
+ break;
+ case STEP_B2:
+ display_step->stepping = 'B';
+ display_step->substepping = '2';
+ break;
+ case STEP_C0:
+ display_step->stepping = 'C';
+ display_step->substepping = '0';
+ break;
+ case STEP_C1:
+ display_step->stepping = 'C';
+ display_step->substepping = '1';
+ break;
+ case STEP_D0:
+ display_step->stepping = 'D';
+ display_step->substepping = '0';
+ break;
+ case STEP_D1:
+ display_step->stepping = 'D';
+ display_step->substepping = '1';
+ break;
+ case STEP_E0:
+ display_step->stepping = 'E';
+ display_step->substepping = '0';
+ break;
+ case STEP_F0:
+ display_step->stepping = 'F';
+ display_step->substepping = '0';
+ break;
+ case STEP_G0:
+ display_step->stepping = 'G';
+ display_step->substepping = '0&
[Intel-gfx] [PATCH 0/2] Stepping/substepping reorg for DMC
This series addresses the following: 1. Add missing stepping/substepping info for all platforms. 2. Use RUNTIME_INFO->step to grab the actual stepping info for a platform instead of having separate lookup tables for each platform on DMC side. Anusha Srivatsa (2): drm/i915/dmc: Use RUNTIME_INFO->step for DMC drm/i915/dmc: Add steping info table for remaining platforms drivers/gpu/drm/i915/display/intel_dmc.c | 117 +++ drivers/gpu/drm/i915/intel_step.c| 69 + drivers/gpu/drm/i915/intel_step.h| 7 ++ 3 files changed, 154 insertions(+), 39 deletions(-) -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/dmc: Add steping info table for remaining platforms
intel_step.c has stepping_info for most platforms. With DMC using
display_step from here, lets add the info for all older platforms
as well
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_step.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index c8542161c5d0..d8f5ef9ac158 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -38,6 +38,13 @@ static const struct intel_step_info skl_revid_step_tbl[] = {
[9] = { .gt_step = STEP_J0, .display_step = STEP_J0 },
};
+static const struct intel_step_info glk_revid_step_tbl[] = {
+ [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+ [1] = { .gt_step = STEP_A1, .display_step = STEP_A1 },
+ [2] = { .gt_step = STEP_A2, .display_step = STEP_A2 },
+ [3] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+};
+
static const struct intel_step_info icl_revid_step_tbl[] = {
[0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[3] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
@@ -71,6 +78,18 @@ static const struct intel_step_info tgl_revid_step_tbl[] = {
[1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },
};
+static const struct intel_step_info dg1_revid_step_tbl[] = {
+ [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+ [0x1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+};
+
+static const struct intel_step_info rkl_revid_step_tbl[] = {
+ [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
+ [0x1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
+ [0x4] = { .gt_step = STEP_C0, .display_step = STEP_C0 },
+
+};
+
static const struct intel_step_info adls_revid_step_tbl[] = {
[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
[0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
@@ -99,6 +118,12 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ALDERLAKE_S(i915)) {
revids = adls_revid_step_tbl;
size = ARRAY_SIZE(adls_revid_step_tbl);
+ } else if (IS_ROCKETLAKE(i915)) {
+ revids = rkl_revid_step_tbl;
+ size = ARRAY_SIZE(rkl_revid_step_tbl);
+ } else if (IS_DG1(i915)) {
+ revids = dg1_revid_step_tbl;
+ size = ARRAY_SIZE(dg1_revid_step_tbl);
} else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) {
revids = tgl_uy_revid_step_tbl;
size = ARRAY_SIZE(tgl_uy_revid_step_tbl);
@@ -111,6 +136,9 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ICELAKE(i915)) {
revids = icl_revid_step_tbl;
size = ARRAY_SIZE(icl_revid_step_tbl);
+ } else if (IS_GEMINILAKE(i915)) {
+ revids = glk_revid_step_tbl;
+ size = ARRAY_SIZE(glk_revid_step_tbl);
} else if (IS_SKYLAKE(i915)) {
revids = skl_revid_step_tbl;
size = ARRAY_SIZE(skl_revid_step_tbl);
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/dmc: Use RUNTIME_INFO->stp for DMC
On the dmc side,we maintain a lookup table with different display
stepping-substepping combinations.
Instead of adding new table for every new platform, lets ues
the stepping info from RUNTIME_INFO(dev_priv)->step
Adding the helper intel_get_display_step().
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 49 ++--
1 file changed, 45 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index f8789d4543bf..c7ff7ff3f412 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -266,14 +266,55 @@ static const struct stepping_info icl_stepping_info[] = {
};
static const struct stepping_info no_stepping_info = { '*', '*' };
+struct stepping_info *display_step;
+
+static struct stepping_info *
+intel_get_display_stepping(struct intel_step_info step)
+{
+
+ switch (step.display_step) {
+ case STEP_A0:
+ display_step->stepping = 'A';
+ display_step->substepping = '0';
+ break;
+ case STEP_A2:
+ display_step->stepping = 'A';
+ display_step->substepping = '2';
+ break;
+ case STEP_B0:
+ display_step->stepping = 'B';
+ display_step->substepping = '0';
+ break;
+ case STEP_B1:
+ display_step->stepping = 'B';
+ display_step->substepping = '1';
+ break;
+ case STEP_C0:
+ display_step->stepping = 'C';
+ display_step->substepping = '0';
+ break;
+ case STEP_D0:
+ display_step->stepping = 'D';
+ display_step->substepping = '0';
+ break;
+ default:
+ display_step->stepping = '*';
+ display_step->substepping = '*';
+ break;
+ }
+ return display_step;
+}
static const struct stepping_info *
intel_get_stepping_info(struct drm_i915_private *dev_priv)
{
const struct stepping_info *si;
+ struct intel_step_info step = RUNTIME_INFO(dev_priv)->step;
unsigned int size;
- if (IS_ICELAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 12) {
+ si = intel_get_display_stepping(step);
+ } else if (IS_ICELAKE(dev_priv)) {
size = ARRAY_SIZE(icl_stepping_info);
si = icl_stepping_info;
} else if (IS_SKYLAKE(dev_priv)) {
@@ -287,10 +328,10 @@ intel_get_stepping_info(struct drm_i915_private *dev_priv)
si = NULL;
}
- if (INTEL_REVID(dev_priv) < size)
- return si + INTEL_REVID(dev_priv);
+ if (DISPLAY_VER(dev_priv) < 12)
+ return INTEL_REVID(dev_priv) < size ? si +
INTEL_REVID(dev_priv) : &no_stepping_info;
- return &no_stepping_info;
+ return si;
}
static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
--
2.32.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 2/2] drm/i915/dmc: Modify stepping/substepping table
Grab the stepping info from RUNTIME_INFO(dev_priv)->step
on the dmc side to grab the right blob.
Adding the helper intel_get_soc_info() that has SOC stepping
lookup table.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 113 ++-
1 file changed, 109 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index f8789d4543bf..1b2e01adac48 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -266,14 +266,119 @@ static const struct stepping_info icl_stepping_info[] = {
};
static const struct stepping_info no_stepping_info = { '*', '*' };
+struct stepping_info *soc;
+
+static struct stepping_info *
+intel_get_soc_stepping(struct intel_step_info step)
+{
+
+ switch (step.soc_step) {
+ case STEP_A0:
+ soc->stepping = 'A';
+ soc->substepping = '0';
+ break;
+ case STEP_A2:
+ soc->stepping = 'A';
+ soc->substepping = '2';
+ break;
+ case STEP_B0:
+ soc->stepping = 'B';
+ soc->substepping = '0';
+ break;
+ case STEP_B1:
+ soc->stepping = 'B';
+ soc->substepping = '1';
+ break;
+ case STEP_B2:
+ soc->stepping = 'B';
+ soc->substepping = '2';
+ break;
+ case STEP_B10:
+ soc->stepping = 'B';
+ soc->substepping = 'A';
+ break;
+ case STEP_C0:
+ soc->stepping = 'C';
+ soc->substepping = '0';
+ break;
+ case STEP_D0:
+ soc->stepping = 'D';
+ soc->substepping = '0';
+ break;
+ case STEP_D1:
+ soc->stepping = 'D';
+ soc->substepping = '1';
+ break;
+ case STEP_E0:
+ soc->stepping = 'E';
+ soc->substepping = '0';
+ break;
+ case STEP_F0:
+ soc->stepping = 'F';
+ soc->substepping = '0';
+ break;
+ case STEP_G0:
+ soc->stepping = 'G';
+ soc->substepping = '0';
+ break;
+ case STEP_H0:
+ soc->stepping = 'H';
+ soc->substepping = '0';
+ break;
+ case STEP_H5:
+ soc->stepping = 'H';
+ soc->substepping = '5';
+ break;
+ case STEP_J0:
+ soc->stepping = 'J';
+ soc->substepping = '0';
+ break;
+ case STEP_J1:
+ soc->stepping = 'J';
+ soc->substepping = '1';
+ break;
+ case STEP_K0:
+ soc->stepping = 'K';
+ soc->substepping = '0';
+ break;
+ case STEP_P0:
+ soc->stepping = 'L';
+ soc->substepping = '0';
+ break;
+ case STEP_L0:
+ soc->stepping = 'P';
+ soc->substepping = '0';
+ break;
+ case STEP_Q0:
+ soc->stepping = 'Q';
+ soc->substepping = '0';
+ break;
+ case STEP_R0:
+ soc->stepping = 'R';
+ soc->substepping = '0';
+ break;
+ case STEP_Y0:
+ soc->stepping = 'Y';
+ soc->substepping = '0';
+ break;
+ default:
+ soc->stepping = '*';
+ soc
[Intel-gfx] [RFC 1/2] drm/i915/dmc: Add soc stepping to intel_step
DMC firmware looks for SOC stepping to load specific firmware.
While we maintained a separate lookup table, lets consolidate
SOC steppings with gt and display steppings.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_step.c | 46 +++
drivers/gpu/drm/i915/intel_step.h | 13 +
2 files changed, 36 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_step.c
b/drivers/gpu/drm/i915/intel_step.c
index ba9479a67521..bc139c7e3e37 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -16,42 +16,42 @@
/* FIXME: what about REVID_E0 */
static const struct intel_step_info kbl_revids[] = {
- [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
- [1] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
- [2] = { .gt_step = STEP_C0, .display_step = STEP_B0 },
- [3] = { .gt_step = STEP_D0, .display_step = STEP_B0 },
- [4] = { .gt_step = STEP_F0, .display_step = STEP_C0 },
- [5] = { .gt_step = STEP_C0, .display_step = STEP_B1 },
- [6] = { .gt_step = STEP_D1, .display_step = STEP_B1 },
- [7] = { .gt_step = STEP_G0, .display_step = STEP_C0 },
+ [0] = { .gt_step = STEP_A0, .display_step = STEP_A0, .soc_step =
STEP_G0 },
+ [1] = { .gt_step = STEP_B0, .display_step = STEP_B0, .soc_step =
STEP_A0 },
+ [2] = { .gt_step = STEP_C0, .display_step = STEP_B0, .soc_step =
STEP_H0 },
+ [3] = { .gt_step = STEP_D0, .display_step = STEP_B0, .soc_step =
STEP_J0 },
+ [4] = { .gt_step = STEP_F0, .display_step = STEP_C0, .soc_step =
STEP_B0 },
+ [5] = { .gt_step = STEP_C0, .display_step = STEP_B1, .soc_step =
STEP_H5 },
+ [6] = { .gt_step = STEP_D1, .display_step = STEP_B1, .soc_step =
STEP_J1 },
+ [7] = { .gt_step = STEP_G0, .display_step = STEP_C0, .soc_step =
STEP_Y0 },
};
static const struct intel_step_info tgl_uy_revid_step_tbl[] = {
- [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
- [1] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
- [2] = { .gt_step = STEP_B1, .display_step = STEP_C0 },
- [3] = { .gt_step = STEP_C0, .display_step = STEP_D0 },
+ [0] = { .gt_step = STEP_A0, .display_step = STEP_A0, .soc_step =
STEP_A0 },
+ [1] = { .gt_step = STEP_B0, .display_step = STEP_C0, .soc_step =
STEP_B2 },
+ [2] = { .gt_step = STEP_B1, .display_step = STEP_C0, .soc_step =
STEP_B10 },
+ [3] = { .gt_step = STEP_C0, .display_step = STEP_D0, .soc_step =
STEP_C0 },
};
/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same
HW */
static const struct intel_step_info tgl_revid_step_tbl[] = {
- [0] = { .gt_step = STEP_A0, .display_step = STEP_B0 },
- [1] = { .gt_step = STEP_B0, .display_step = STEP_D0 },
+ [0] = { .gt_step = STEP_A0, .display_step = STEP_B0, .soc_step =
STEP_P0 },
+ [1] = { .gt_step = STEP_B0, .display_step = STEP_D0, .soc_step =
STEP_R0 },
};
static const struct intel_step_info adls_revid_step_tbl[] = {
- [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
- [0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 },
- [0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
- [0x8] = { .gt_step = STEP_C0, .display_step = STEP_B0 },
- [0xC] = { .gt_step = STEP_D0, .display_step = STEP_C0 },
+ [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0, .soc_step =
STEP_A0 },
+ [0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2, .soc_step =
STEP_A2 },
+ [0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0, .soc_step =
STEP_B0 },
+ [0x8] = { .gt_step = STEP_C0, .display_step = STEP_B0, .soc_step =
STEP_G0 },
+ [0xC] = { .gt_step = STEP_D0, .display_step = STEP_C0, .soc_step =
STEP_H0 },
};
static const struct intel_step_info adlp_revid_step_tbl[] = {
- [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
- [0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
- [0x8] = { .gt_step = STEP_C0, .display_step = STEP_C0 },
- [0xC] = { .gt_step = STEP_C0, .display_step = STEP_D0 },
+ [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0, .soc_step =
STEP_J0 },
+ [0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0, .soc_step =
STEP_Q0 },
+ [0x8] = { .gt_step = STEP_C0, .display_step = STEP_C0, .soc_step =
STEP_K0 },
+ [0xC] = { .gt_step = STEP_C0, .display_step = STEP_D0, .soc_step =
STEP_L0 },
};
void intel_step_init(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/intel_step.h
b/drivers/gpu/drm/i915/intel_step.h
index 958a8bb5d677..2b0b0aaffe27 100644
--- a/drivers/gpu/drm/i915/intel_step.h
+++ b/drivers/gpu/drm/i915/intel_step.h
@@ -13,6 +13,7 @@ struct drm_i915_private;
struct intel_step_info {
u8 gt_step;
u8 display_step;
+ u8 soc_step;
};
/*
@@ -25,12 +26,24 @@ enum intel_step {
STEP_A2,
ST
[Intel-gfx] [PATCH 2/2] drm/i915/firmware: Update to DMC v2.03 on RKL
Add support to load latest DMC version. The Release Notes mentions that this version fixes timeout issues. Cc: Madhumitha Pradeep Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 1d47f43ada51..45b7515e6a91 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -53,8 +53,8 @@ MODULE_FIRMWARE(ADLS_DMC_PATH); #define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) MODULE_FIRMWARE(DG1_DMC_PATH); -#define RKL_DMC_PATH DMC_PATH(rkl, 2, 02) -#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) +#define RKL_DMC_PATH DMC_PATH(rkl, 2, 03) +#define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 3) MODULE_FIRMWARE(RKL_DMC_PATH); #define TGL_DMC_PATH DMC_PATH(tgl, 2, 12) -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/firmware: Update to DMC v2.12 on TGL
Add support to the latest DMC firmware. Cc: Madhunitha Pradeep Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 97308da28059..1d47f43ada51 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -57,8 +57,8 @@ MODULE_FIRMWARE(DG1_DMC_PATH); #define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) MODULE_FIRMWARE(RKL_DMC_PATH); -#define TGL_DMC_PATH DMC_PATH(tgl, 2, 08) -#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8) +#define TGL_DMC_PATH DMC_PATH(tgl, 2, 12) +#define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 12) MODULE_FIRMWARE(TGL_DMC_PATH); #define ICL_DMC_PATH DMC_PATH(icl, 1, 09) -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] DMC Updates for RKL, TGL
Adding PR to the the cover letter for CI to pull the updates. The following changes since commit 0f66b74b6267fce66395316308d88b0535aa3df2: cypress: update firmware for cyw54591 pcie (2021-06-09 07:12:02 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware rkl_tgl_dmc_updates for you to fetch changes up to 885ee4dde3c760e7b8b8a43a5ba4056a7e66c788: drm/i915/firmware: Add DMC v2.02 for RKL (2021-06-21 16:06:07 -0700) Anusha Srivatsa (2): drm/i915/firmware: Add V2.12 DC fo TGL drm/i915/firmware: Add DMC v2.02 for RKL WHENCE | 6 ++ i915/rkl_dmc_ver2_03.bin | Bin 0 -> 18476 bytes i915/tgl_dmc_ver2_12.bin | Bin 0 -> 19760 bytes 3 files changed, 6 insertions(+) create mode 100644 i915/rkl_dmc_ver2_03.bin create mode 100644 i915/tgl_dmc_ver2_12.bin Anusha Srivatsa (2): drm/i915/firmware: Update to DMC v2.12 on TGL drm/i915/firmware: Update to DMC v2.03 on RKL drivers/gpu/drm/i915/display/intel_dmc.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Pipe DMC bits
From: Patchwork Sent: Monday, June 21, 2021 2:30 PM To: Srivatsa, Anusha Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.IGT: failure for Pipe DMC bits Patch Details Series: Pipe DMC bits URL: https://patchwork.freedesktop.org/series/91746/ State: failure Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20421/index.html CI Bug Log - changes from CI_DRM_10256_full -> Patchwork_20421_full Summary FAILURE Serious unknown changes coming with Patchwork_20421_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20421_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues Here are the unknown changes that may have been introduced in Patchwork_20421_full: IGT changes Possible regressions * igt@kms_big_fb@y-tiled-16bpp-rotate-180: * shard-iclb: NOTRUN -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20421/shard-iclb4/igt@kms_big...@y-tiled-16bpp-rotate-180.html> * shard-tglb: NOTRUN -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20421/shard-tglb8/igt@kms_big...@y-tiled-16bpp-rotate-180.html> Not related to the changes introduced by this series. Anusha Known issues Here are the changes found in Patchwork_20421_full that come from known issues: IGT changes Issues hit * igt@kms_big_fb@y-tiled-16bpp-rotate-180: * shard-glk: NOTRUN -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20421/shard-glk7/igt@kms_big...@y-tiled-16bpp-rotate-180.html> (i915#1610<https://gitlab.freedesktop.org/drm/intel/issues/1610>) * shard-kbl: NOTRUN -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20421/shard-kbl3/igt@kms_big...@y-tiled-16bpp-rotate-180.html> (i915#1610<https://gitlab.freedesktop.org/drm/intel/issues/1610>) * shard-skl: NOTRUN -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20421/shard-skl9/igt@kms_big...@y-tiled-16bpp-rotate-180.html> (i915#1610<https://gitlab.freedesktop.org/drm/intel/issues/1610>) * igt@kms_color_chamelium@pipe-a-ctm-0-75: * shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20421/shard-apl1/igt@kms_color_chamel...@pipe-a-ctm-0-75.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / fdo#111827<https://bugs.freedesktop.org/show_bug.cgi?id=111827>) * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt: * shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20421/shard-apl3/igt@kms_frontbuffer_track...@psr-2p-primscrn-pri-indfb-draw-blt.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +1 similar issue * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: * shard-apl: NOTRUN -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20421/shard-apl1/igt@kms_pipe_crc_ba...@hang-read-crc-pipe-c.html> (i915#1610<https://gitlab.freedesktop.org/drm/intel/issues/1610>) * igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm: * shard-snb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20421/shard-snb6/igt@kms_vbl...@pipe-a-ts-continuation-modeset-rpm.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +4 similar issues Warnings * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: * shard-apl: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10256/shard-apl6/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html> (i915#1610<https://gitlab.freedesktop.org/drm/intel/issues/1610>) -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20421/shard-apl8/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html> (i915#1610<https://gitlab.freedesktop.org/drm/intel/issues/1610> / i915#180<https://gitlab.freedesktop.org/drm/intel/issues/180>) * shard-kbl: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10256/shard-kbl6/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html> (i915#1610<https://gitlab.freedesktop.org/drm/intel/issues/1610>) -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20421/shard-kbl6/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html> (i915#1610<https://gitlab.freedesktop.org/drm/intel/issues/1610> / i915#180<https://gitlab.freedesktop.org/drm/intel/issues/180>) * igt@runner@aborted: * shard-apl: (FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10256/shard-apl6/igt@run...@aborted.html>, FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10256/shard-apl6/igt@run...@aborted.html>, FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10256/shard-apl6/igt@ru
[Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging
This patch adds Pipe A plumbing to the already
existing parsing and loading functions which is
taken care of in the prep patches. Adding MAX_DMC_FW
to keep track for both Main and Pipe A DMC while loading
the respective blobs.
Also adding present field in dmc_info.
s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
fw_info_matches_stepping() helper. CSR_PROGRAM() should now
take the starting address of the particular blob (Main or Pipe)
and not hardcode it.
v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct.
v3: Add a missing corner cases of stepping-substepping combination in
fw_info_matches_stepping() helper.
v4: Add macro for start_mmioaddr for V1 package. Simplify code
in dmc_set_fw_offset (Lucas)
Cc: Souza, Jose
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_power.c| 5 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 131 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 4 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
5 files changed, 85 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 88bb05d5c483..2a1c39a0e56e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "fw loaded: %s\n",
yesno(intel_dmc_has_payload(dev_priv)));
seq_printf(m, "path: %s\n", dmc->fw_path);
+ seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
+ seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
out:
seq_printf(m, "program base: 0x%08x\n",
- intel_de_read(dev_priv, DMC_PROGRAM(0)));
+ intel_de_read(dev_priv,
DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
seq_printf(m, "ssp base: 0x%08x\n",
intel_de_read(dev_priv, DMC_SSP_BASE));
seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4298ae684d7d..285380079aab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private
*dev_priv)
static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
{
drm_WARN_ONCE(&dev_priv->drm,
- !intel_de_read(dev_priv, DMC_PROGRAM(0)),
- "DMC program storage start is NULL\n");
+ !intel_de_read(dev_priv,
+
DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+"DMC program storage start is NULL\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 269a57d936ab..18e0d225a478 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -96,6 +96,7 @@ MODULE_FIRMWARE(BXT_DMC_PATH);
#define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
#define DMC_V1_MAX_MMIO_COUNT 8
#define DMC_V3_MAX_MMIO_COUNT 20
+#define DMC_V1_MMIO_START_RANGE0x8
struct intel_css_header {
/* 0x09 for DMC */
@@ -317,8 +318,7 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
struct intel_dmc *dmc = &dev_priv->dmc;
- struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
- u32 i, fw_size;
+ u32 id, i;
if (!HAS_DMC(dev_priv)) {
drm_err(&dev_priv->drm,
@@ -332,20 +332,25 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
- for (i = 0; i < fw_size; i++)
- intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- dmc_info->payload[i]);
[Intel-gfx] [CI 1/4] drm/i915/dmc: Introduce DMC_FW_MAIN
This is a prep patch for Pipe DMC plugging.
Add dmc_info struct in intel_dmc to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
v2: Remove dmc_offset and start_mmioaddr from dmc_info struct (Jose)
Cc: Souza, Jose
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 38 +---
drivers/gpu/drm/i915/display/intel_dmc.h | 18 +++
2 files changed, 33 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 97308da28059..269a57d936ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
bool intel_dmc_has_payload(struct drm_i915_private *i915)
{
- return i915->dmc.dmc_payload;
+ return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
static const struct stepping_info skl_stepping_info[] = {
@@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
*/
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
- u32 *payload = dev_priv->dmc.dmc_payload;
+ struct intel_dmc *dmc = &dev_priv->dmc;
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
u32 i, fw_size;
if (!HAS_DMC(dev_priv)) {
@@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- if (!intel_dmc_has_payload(dev_priv)) {
+ if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
}
- fw_size = dev_priv->dmc.dmc_fw_size;
+ fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
for (i = 0; i < fw_size; i++)
intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- payload[i]);
+ dmc_info->payload[i]);
preempt_enable();
- for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
- intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
- dev_priv->dmc.mmiodata[i]);
+ for (i = 0; i < dmc_info->mmio_count; i++) {
+ intel_de_write(dev_priv, dmc_info->mmioaddr[i],
+ dmc_info->mmiodata[i]);
}
dev_priv->dmc.dc_state = 0;
@@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
size_t rem_size)
{
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
u8 *payload;
- BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
-ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
/*
* Check if we can access common fields, we will checkc again below
@@ -469,10 +471,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
mmioaddr[i]);
return 0;
}
- dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
- dmc->mmiodata[i] = mmiodata[i];
+ dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
+ dmc_info->mmiodata[i] = mmiodata[i];
}
- dmc->mmio_count = mmio_count;
+ dmc_info->mmio_count = mmio_count;
rem_size -= header_len_bytes;
@@ -485,14 +487,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
drm_err(&i915->drm, "DMC FW too big (%u bytes)\n",
payload_size);
return 0;
}
- dmc->dmc_fw_size = dmc_header->fw_size;
+ dmc_info->dmc_fw_size = dmc_header->fw_size;
- dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!dmc->dmc_payload)
+ dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
+ if (!dmc_info->payload)
return 0;
payload = (u8 *)(dmc_header) + header_len_bytes;
- memcpy(dmc->dmc_payload, payload, payload_size);
+ memcpy(dmc_info->payload, payload, payload_size);
return header_len_bytes + payload_size;
@@ -827,5 +829,5 @@ void intel_dmc_ucode_fini(struct drm_i915_priva
[Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC
Load DMC v2.10 on ADLP. The release notes mention that
this version enables few power savings features.
v2: Add DMC_PATH() for ADLP (Lucas)
Cc: Lucas De Marchi
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 18e0d225a478..f8789d4543bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -45,6 +45,10 @@
#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 10)
+#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 10)
+MODULE_FIRMWARE(ADLP_DMC_PATH);
+
#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
MODULE_FIRMWARE(ADLS_DMC_PATH);
@@ -724,7 +728,11 @@ void intel_dmc_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_dmc_runtime_pm_get(dev_priv);
- if (IS_ALDERLAKE_S(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ dmc->fw_path = ADLP_DMC_PATH;
+ dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
dmc->fw_path = ADLS_DMC_PATH;
dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
--
2.32.0
___
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[Intel-gfx] [CI 3/4] drm/i915/adl_p: Pipe B DMC Support
ADLP requires us to load both Pipe A and Pipe B.
Plug Pipe B loading support.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2a1c39a0e56e..db38891a9ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -546,6 +546,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "path: %s\n", dmc->fw_path);
seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
+ seq_printf(m, "Pipe B fw support: %s\n",
yesno(IS_ALDERLAKE_P(dev_priv)));
+ seq_printf(m, "Pipe B fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEB].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 007a284b0ef0..c3c00ff03869 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -19,6 +19,7 @@ struct drm_i915_private;
enum {
DMC_FW_MAIN = 0,
DMC_FW_PIPEA,
+ DMC_FW_PIPEB,
DMC_FW_MAX
};
--
2.32.0
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[Intel-gfx] [CI 0/4] Pipe DMC bits
One change from previous verison is a fix of SKL regression. Corner cases for stepping-substepping combination was missing from fw_info_matches_stepping() helper. Luckily SKL was the only platform in CI that came under this category and DMC refused to load. v2: SKL fix tested on SKL. v3: Minor changes in Pipe DMC plugging patch as suggested by Lucas v4: Remove the sanity check for MMIO that no longer apply to newer platforms.(Anusha) Anusha Srivatsa (4): drm/i915/dmc: Introduce DMC_FW_MAIN drm/i915/xelpd: Pipe A DMC plugging drm/i915/adl_p: Pipe B DMC Support drm/i915/adl_p: Load DMC .../drm/i915/display/intel_display_debugfs.c | 6 +- .../drm/i915/display/intel_display_power.c| 5 +- drivers/gpu/drm/i915/display/intel_dmc.c | 165 ++ drivers/gpu/drm/i915/display/intel_dmc.h | 23 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 5 files changed, 123 insertions(+), 78 deletions(-) -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Limit disabling PSR around cdclk changes to ADL-P
> -Original Message-
> From: Souza, Jose
> Sent: Thursday, June 17, 2021 2:18 PM
> To: Mun, Gwan-gyeong ; Srivatsa, Anusha
> ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Limit disabling PSR
> around cdclk changes to ADL-P
>
> On Thu, 2021-06-17 at 14:12 -0700, Anusha Srivatsa wrote:
> > From: Gwan-gyeong Mun
> >
> > Only ADL-P platform requires a temporal disabling of PSR for changing
> > the CDCLK PLL frequency with crawling. Changing the CDCLK PLL
> > frequency on prior platforms of ADL-P or changing the CDCLK PLL
> > frequency without crawling on ADL-P don't need to disable of PSR.
>
> This is only hiding a possible bug found in ICL under the IS_ALDERLAKE_P()
> check.
> There is no reason to not pause PSR in older platforms during cdclck changes.
According to 15729, pausing PSR during cdclk changes is not valid.
Anusha
> >
> > Bspec: 49207
> >
> > Cc: Ville Syrjälä
> > Cc: Mika Kahola
> > Cc: Stanislav Lisovskiy
> > Cc: Anusha Srivatsa
> > Fixes: 17c1a4b7ac6f ("drm/i915: Disable PSR around cdclk change")
> > Signed-off-by: Gwan-gyeong Mun
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 22
> > --
> > 1 file changed, 16 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 613ffcc68eba..6da426d26aac 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1962,10 +1962,18 @@ static void intel_set_cdclk(struct
> > drm_i915_private *dev_priv,
> >
> > intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
> >
> > - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > + /*
> > +* Only ADL-P platform requires a temporal disabling of PSR for
> changing
> > +* the CDCLK PLL frequency with crawling.
> > +* Changing the CDCLK PLL frequency on prior platforms of ADL-P or
> changing
> > +* the CDCLK PLL frequency without crawling on ADL-P don't need to
> disable of PSR.
> > +*/
> > + if (IS_ALDERLAKE_P(dev_priv)) {
> > + for_each_intel_encoder_with_psr(&dev_priv->drm,
> encoder) {
> > + struct intel_dp *intel_dp =
> enc_to_intel_dp(encoder);
> >
> > - intel_psr_pause(intel_dp);
> > + intel_psr_pause(intel_dp);
> > + }
> > }
> >
> > /*
> > @@ -1990,10 +1998,12 @@ static void intel_set_cdclk(struct
> drm_i915_private *dev_priv,
> > }
> > mutex_unlock(&dev_priv->gmbus_mutex);
> >
> > - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > + if (IS_ALDERLAKE_P(dev_priv)) {
> > + for_each_intel_encoder_with_psr(&dev_priv->drm,
> encoder) {
> > + struct intel_dp *intel_dp =
> enc_to_intel_dp(encoder);
> >
> > - intel_psr_resume(intel_dp);
> > + intel_psr_resume(intel_dp);
> > + }
> > }
> >
> > if (drm_WARN(&dev_priv->drm,
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[Intel-gfx] [PATCH 1/5] drm/i915/display: Limit disabling PSR around cdclk changes to ADL-P
From: Gwan-gyeong Mun
Only ADL-P platform requires a temporal disabling of PSR for changing the
CDCLK PLL frequency with crawling. Changing the CDCLK PLL frequency on
prior platforms of ADL-P or changing the CDCLK PLL frequency without
crawling on ADL-P don't need to disable of PSR.
Bspec: 49207
Cc: Ville Syrjälä
Cc: Mika Kahola
Cc: Stanislav Lisovskiy
Cc: Anusha Srivatsa
Fixes: 17c1a4b7ac6f ("drm/i915: Disable PSR around cdclk change")
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 613ffcc68eba..6da426d26aac 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1962,10 +1962,18 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ /*
+* Only ADL-P platform requires a temporal disabling of PSR for changing
+* the CDCLK PLL frequency with crawling.
+* Changing the CDCLK PLL frequency on prior platforms of ADL-P or
changing
+* the CDCLK PLL frequency without crawling on ADL-P don't need to
disable of PSR.
+*/
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- intel_psr_pause(intel_dp);
+ intel_psr_pause(intel_dp);
+ }
}
/*
@@ -1990,10 +1998,12 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
}
mutex_unlock(&dev_priv->gmbus_mutex);
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- intel_psr_resume(intel_dp);
+ intel_psr_resume(intel_dp);
+ }
}
if (drm_WARN(&dev_priv->drm,
--
2.32.0
___
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[Intel-gfx] [PATCH 5/5] drm/i915/adl_p: Load DMC
Load DMC v2.10 on ADLP. The release notes mention that
this version enables few power savings features.
v2: Add DMC_PATH() for ADLP (Lucas)
Cc: Lucas De Marchi
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 18e0d225a478..f8789d4543bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -45,6 +45,10 @@
#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 10)
+#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 10)
+MODULE_FIRMWARE(ADLP_DMC_PATH);
+
#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
MODULE_FIRMWARE(ADLS_DMC_PATH);
@@ -724,7 +728,11 @@ void intel_dmc_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_dmc_runtime_pm_get(dev_priv);
- if (IS_ALDERLAKE_S(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ dmc->fw_path = ADLP_DMC_PATH;
+ dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
dmc->fw_path = ADLS_DMC_PATH;
dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
--
2.32.0
___
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[Intel-gfx] [PATCH 4/5] drm/i915/adl_p: Pipe B DMC Support
ADLP requires us to load both Pipe A and Pipe B.
Plug Pipe B loading support.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2a1c39a0e56e..db38891a9ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -546,6 +546,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "path: %s\n", dmc->fw_path);
seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
+ seq_printf(m, "Pipe B fw support: %s\n",
yesno(IS_ALDERLAKE_P(dev_priv)));
+ seq_printf(m, "Pipe B fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEB].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 007a284b0ef0..c3c00ff03869 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -19,6 +19,7 @@ struct drm_i915_private;
enum {
DMC_FW_MAIN = 0,
DMC_FW_PIPEA,
+ DMC_FW_PIPEB,
DMC_FW_MAX
};
--
2.32.0
___
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[Intel-gfx] [PATCH 2/5] drm/i915/dmc: Introduce DMC_FW_MAIN
This is a prep patch for Pipe DMC plugging.
Add dmc_info struct in intel_dmc to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
v2: Remove dmc_offset and start_mmioaddr from dmc_info struct (Jose)
Cc: Souza, Jose
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 38 +---
drivers/gpu/drm/i915/display/intel_dmc.h | 18 +++
2 files changed, 33 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 97308da28059..269a57d936ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
bool intel_dmc_has_payload(struct drm_i915_private *i915)
{
- return i915->dmc.dmc_payload;
+ return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
static const struct stepping_info skl_stepping_info[] = {
@@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
*/
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
- u32 *payload = dev_priv->dmc.dmc_payload;
+ struct intel_dmc *dmc = &dev_priv->dmc;
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
u32 i, fw_size;
if (!HAS_DMC(dev_priv)) {
@@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- if (!intel_dmc_has_payload(dev_priv)) {
+ if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
}
- fw_size = dev_priv->dmc.dmc_fw_size;
+ fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
for (i = 0; i < fw_size; i++)
intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- payload[i]);
+ dmc_info->payload[i]);
preempt_enable();
- for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
- intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
- dev_priv->dmc.mmiodata[i]);
+ for (i = 0; i < dmc_info->mmio_count; i++) {
+ intel_de_write(dev_priv, dmc_info->mmioaddr[i],
+ dmc_info->mmiodata[i]);
}
dev_priv->dmc.dc_state = 0;
@@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
size_t rem_size)
{
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
u8 *payload;
- BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
-ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
/*
* Check if we can access common fields, we will checkc again below
@@ -469,10 +471,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
mmioaddr[i]);
return 0;
}
- dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
- dmc->mmiodata[i] = mmiodata[i];
+ dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
+ dmc_info->mmiodata[i] = mmiodata[i];
}
- dmc->mmio_count = mmio_count;
+ dmc_info->mmio_count = mmio_count;
rem_size -= header_len_bytes;
@@ -485,14 +487,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
drm_err(&i915->drm, "DMC FW too big (%u bytes)\n",
payload_size);
return 0;
}
- dmc->dmc_fw_size = dmc_header->fw_size;
+ dmc_info->dmc_fw_size = dmc_header->fw_size;
- dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!dmc->dmc_payload)
+ dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
+ if (!dmc_info->payload)
return 0;
payload = (u8 *)(dmc_header) + header_len_bytes;
- memcpy(dmc->dmc_payload, payload, payload_size);
+ memcpy(dmc_info->payload, payload, payload_size);
return header_len_bytes + payload_size;
@@ -827,5 +829,5 @@ void intel_dmc_ucode_fini(struct drm_i915_priva
[Intel-gfx] [PATCH 3/5] drm/i915/xelpd: Pipe A DMC plugging
This patch adds Pipe A plumbing to the already
existing parsing and loading functions which is
taken care of in the prep patches. Adding MAX_DMC_FW
to keep track for both Main and Pipe A DMC while loading
the respective blobs.
Also adding present field in dmc_info.
s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
fw_info_matches_stepping() helper. CSR_PROGRAM() should now
take the starting address of the particular blob (Main or Pipe)
and not hardcode it.
v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct.
v3: Add a missing corner cases of stepping-substepping combination in
fw_info_matches_stepping() helper.
v4: Add macro for start_mmioaddr for V1 package. Simplify code
in dmc_set_fw_offset (Lucas)
Cc: Souza, Jose
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_power.c| 5 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 131 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 4 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
5 files changed, 85 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 88bb05d5c483..2a1c39a0e56e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "fw loaded: %s\n",
yesno(intel_dmc_has_payload(dev_priv)));
seq_printf(m, "path: %s\n", dmc->fw_path);
+ seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
+ seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
out:
seq_printf(m, "program base: 0x%08x\n",
- intel_de_read(dev_priv, DMC_PROGRAM(0)));
+ intel_de_read(dev_priv,
DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
seq_printf(m, "ssp base: 0x%08x\n",
intel_de_read(dev_priv, DMC_SSP_BASE));
seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4298ae684d7d..285380079aab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private
*dev_priv)
static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
{
drm_WARN_ONCE(&dev_priv->drm,
- !intel_de_read(dev_priv, DMC_PROGRAM(0)),
- "DMC program storage start is NULL\n");
+ !intel_de_read(dev_priv,
+
DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+"DMC program storage start is NULL\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 269a57d936ab..18e0d225a478 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -96,6 +96,7 @@ MODULE_FIRMWARE(BXT_DMC_PATH);
#define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
#define DMC_V1_MAX_MMIO_COUNT 8
#define DMC_V3_MAX_MMIO_COUNT 20
+#define DMC_V1_MMIO_START_RANGE0x8
struct intel_css_header {
/* 0x09 for DMC */
@@ -317,8 +318,7 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
struct intel_dmc *dmc = &dev_priv->dmc;
- struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
- u32 i, fw_size;
+ u32 id, i;
if (!HAS_DMC(dev_priv)) {
drm_err(&dev_priv->drm,
@@ -332,20 +332,25 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
- for (i = 0; i < fw_size; i++)
- intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- dmc_info->payload[i]);
[Intel-gfx] [PATCH 0/5] Pipe DMC bits + PSR fix
Pipe DMC series exposed a corner case in PSR patches that were merged recently. Sending the fix along with the Pipe DMC bits to get ensure that CI has no regressions. Anusha Srivatsa (4): drm/i915/dmc: Introduce DMC_FW_MAIN drm/i915/xelpd: Pipe A DMC plugging drm/i915/adl_p: Pipe B DMC Support drm/i915/adl_p: Load DMC Gwan-gyeong Mun (1): drm/i915/display: Limit disabling PSR around cdclk changes to ADL-P drivers/gpu/drm/i915/display/intel_cdclk.c| 22 ++- .../drm/i915/display/intel_display_debugfs.c | 6 +- .../drm/i915/display/intel_display_power.c| 5 +- drivers/gpu/drm/i915/display/intel_dmc.c | 165 ++ drivers/gpu/drm/i915/display/intel_dmc.h | 23 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 6 files changed, 139 insertions(+), 84 deletions(-) -- 2.32.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/4] drm/i915/adl_p: Pipe B DMC Support
ADLP requires us to load both Pipe A and Pipe B.
Plug Pipe B loading support.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2a1c39a0e56e..db38891a9ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -546,6 +546,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "path: %s\n", dmc->fw_path);
seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
+ seq_printf(m, "Pipe B fw support: %s\n",
yesno(IS_ALDERLAKE_P(dev_priv)));
+ seq_printf(m, "Pipe B fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEB].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 007a284b0ef0..c3c00ff03869 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -19,6 +19,7 @@ struct drm_i915_private;
enum {
DMC_FW_MAIN = 0,
DMC_FW_PIPEA,
+ DMC_FW_PIPEB,
DMC_FW_MAX
};
--
2.32.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC
Load DMC v2.10 on ADLP. The release notes mention that
this version enables few power savings features.
v2: Add DMC_PATH() for ADLP (Lucas)
Cc: Lucas De Marchi
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 18e0d225a478..f8789d4543bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -45,6 +45,10 @@
#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 10)
+#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 10)
+MODULE_FIRMWARE(ADLP_DMC_PATH);
+
#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
MODULE_FIRMWARE(ADLS_DMC_PATH);
@@ -724,7 +728,11 @@ void intel_dmc_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_dmc_runtime_pm_get(dev_priv);
- if (IS_ALDERLAKE_S(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ dmc->fw_path = ADLP_DMC_PATH;
+ dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
dmc->fw_path = ADLS_DMC_PATH;
dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
--
2.32.0
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging
This patch adds Pipe A plumbing to the already
existing parsing and loading functions which is
taken care of in the prep patches. Adding MAX_DMC_FW
to keep track for both Main and Pipe A DMC while loading
the respective blobs.
Also adding present field in dmc_info.
s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
fw_info_matches_stepping() helper. CSR_PROGRAM() should now
take the starting address of the particular blob (Main or Pipe)
and not hardcode it.
v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct.
v3: Add a missing corner cases of stepping-substepping combination in
fw_info_matches_stepping() helper.
v4: Add macro for start_mmioaddr for V1 package. Simplify code
in dmc_set_fw_offset (Lucas)
Cc: Souza, Jose
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_power.c| 5 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 131 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 4 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
5 files changed, 85 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 88bb05d5c483..2a1c39a0e56e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "fw loaded: %s\n",
yesno(intel_dmc_has_payload(dev_priv)));
seq_printf(m, "path: %s\n", dmc->fw_path);
+ seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
+ seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
out:
seq_printf(m, "program base: 0x%08x\n",
- intel_de_read(dev_priv, DMC_PROGRAM(0)));
+ intel_de_read(dev_priv,
DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
seq_printf(m, "ssp base: 0x%08x\n",
intel_de_read(dev_priv, DMC_SSP_BASE));
seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4298ae684d7d..285380079aab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private
*dev_priv)
static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
{
drm_WARN_ONCE(&dev_priv->drm,
- !intel_de_read(dev_priv, DMC_PROGRAM(0)),
- "DMC program storage start is NULL\n");
+ !intel_de_read(dev_priv,
+
DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+"DMC program storage start is NULL\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 269a57d936ab..18e0d225a478 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -96,6 +96,7 @@ MODULE_FIRMWARE(BXT_DMC_PATH);
#define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
#define DMC_V1_MAX_MMIO_COUNT 8
#define DMC_V3_MAX_MMIO_COUNT 20
+#define DMC_V1_MMIO_START_RANGE0x8
struct intel_css_header {
/* 0x09 for DMC */
@@ -317,8 +318,7 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
struct intel_dmc *dmc = &dev_priv->dmc;
- struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
- u32 i, fw_size;
+ u32 id, i;
if (!HAS_DMC(dev_priv)) {
drm_err(&dev_priv->drm,
@@ -332,20 +332,25 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
- for (i = 0; i < fw_size; i++)
- intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- dmc_info->payload[i]);
[Intel-gfx] [CI 0/4] Pipe DMC Support
One change from previous verison is a fix of SKL regression. Corner cases for stepping-substepping combination was missing from fw_info_matches_stepping() helper. Luckily SKL was the only platform in CI that came under this category and DMC refused to load. v2: SKL fix tested on SKL. v3: Minor changes in Pipe DMC plugging patch as suggested by Lucas v4: Remove the sanity check for MMIO that no longer apply to newer platforms.(Anusha) Anusha Srivatsa (4): drm/i915/dmc: Introduce DMC_FW_MAIN drm/i915/xelpd: Pipe A DMC plugging drm/i915/adl_p: Pipe B DMC Support drm/i915/adl_p: Load DMC .../drm/i915/display/intel_display_debugfs.c | 6 +- .../drm/i915/display/intel_display_power.c| 5 +- drivers/gpu/drm/i915/display/intel_dmc.c | 165 ++ drivers/gpu/drm/i915/display/intel_dmc.h | 23 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 5 files changed, 123 insertions(+), 78 deletions(-) -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/4] drm/i915/dmc: Introduce DMC_FW_MAIN
This is a prep patch for Pipe DMC plugging.
Add dmc_info struct in intel_dmc to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
v2: Remove dmc_offset and start_mmioaddr from dmc_info struct (Jose)
Cc: Souza, Jose
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 38 +---
drivers/gpu/drm/i915/display/intel_dmc.h | 18 +++
2 files changed, 33 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 97308da28059..269a57d936ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
bool intel_dmc_has_payload(struct drm_i915_private *i915)
{
- return i915->dmc.dmc_payload;
+ return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
static const struct stepping_info skl_stepping_info[] = {
@@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
*/
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
- u32 *payload = dev_priv->dmc.dmc_payload;
+ struct intel_dmc *dmc = &dev_priv->dmc;
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
u32 i, fw_size;
if (!HAS_DMC(dev_priv)) {
@@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- if (!intel_dmc_has_payload(dev_priv)) {
+ if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
}
- fw_size = dev_priv->dmc.dmc_fw_size;
+ fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
for (i = 0; i < fw_size; i++)
intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- payload[i]);
+ dmc_info->payload[i]);
preempt_enable();
- for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
- intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
- dev_priv->dmc.mmiodata[i]);
+ for (i = 0; i < dmc_info->mmio_count; i++) {
+ intel_de_write(dev_priv, dmc_info->mmioaddr[i],
+ dmc_info->mmiodata[i]);
}
dev_priv->dmc.dc_state = 0;
@@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
size_t rem_size)
{
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
u8 *payload;
- BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
-ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
/*
* Check if we can access common fields, we will checkc again below
@@ -469,10 +471,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
mmioaddr[i]);
return 0;
}
- dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
- dmc->mmiodata[i] = mmiodata[i];
+ dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
+ dmc_info->mmiodata[i] = mmiodata[i];
}
- dmc->mmio_count = mmio_count;
+ dmc_info->mmio_count = mmio_count;
rem_size -= header_len_bytes;
@@ -485,14 +487,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
drm_err(&i915->drm, "DMC FW too big (%u bytes)\n",
payload_size);
return 0;
}
- dmc->dmc_fw_size = dmc_header->fw_size;
+ dmc_info->dmc_fw_size = dmc_header->fw_size;
- dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!dmc->dmc_payload)
+ dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
+ if (!dmc_info->payload)
return 0;
payload = (u8 *)(dmc_header) + header_len_bytes;
- memcpy(dmc->dmc_payload, payload, payload_size);
+ memcpy(dmc_info->payload, payload, payload_size);
return header_len_bytes + payload_size;
@@ -827,5 +829,5 @@ void intel_dmc_ucode_fini(struct drm_i915_priva
[Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging
This patch adds Pipe A plumbing to the already
existing parsing and loading functions which is
taken care of in the prep patches. Adding MAX_DMC_FW
to keep track for both Main and Pipe A DMC while loading
the respective blobs.
Also adding present field in dmc_info.
s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
fw_info_matches_stepping() helper. CSR_PROGRAM() should now
take the starting address of the particular blob (Main or Pipe)
and not hardcode it.
v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct.
v3: Add a missing corner cases of stepping-substepping combination in
fw_info_matches_stepping() helper.
v4: Add macro for start_mmioaddr for V1 package. Simplify code
in dmc_set_fw_offset (Lucas)
Cc: Souza, Jose
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_power.c| 5 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 131 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 4 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
5 files changed, 85 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 88bb05d5c483..2a1c39a0e56e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "fw loaded: %s\n",
yesno(intel_dmc_has_payload(dev_priv)));
seq_printf(m, "path: %s\n", dmc->fw_path);
+ seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
+ seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
out:
seq_printf(m, "program base: 0x%08x\n",
- intel_de_read(dev_priv, DMC_PROGRAM(0)));
+ intel_de_read(dev_priv,
DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
seq_printf(m, "ssp base: 0x%08x\n",
intel_de_read(dev_priv, DMC_SSP_BASE));
seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4298ae684d7d..285380079aab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private
*dev_priv)
static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
{
drm_WARN_ONCE(&dev_priv->drm,
- !intel_de_read(dev_priv, DMC_PROGRAM(0)),
- "DMC program storage start is NULL\n");
+ !intel_de_read(dev_priv,
+
DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+"DMC program storage start is NULL\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 269a57d936ab..18e0d225a478 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -96,6 +96,7 @@ MODULE_FIRMWARE(BXT_DMC_PATH);
#define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
#define DMC_V1_MAX_MMIO_COUNT 8
#define DMC_V3_MAX_MMIO_COUNT 20
+#define DMC_V1_MMIO_START_RANGE0x8
struct intel_css_header {
/* 0x09 for DMC */
@@ -317,8 +318,7 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
struct intel_dmc *dmc = &dev_priv->dmc;
- struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
- u32 i, fw_size;
+ u32 id, i;
if (!HAS_DMC(dev_priv)) {
drm_err(&dev_priv->drm,
@@ -332,20 +332,25 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
- for (i = 0; i < fw_size; i++)
- intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- dmc_info->payload[i]);
+ for (id = 0; id < DMC_FW_MAX; id++) {
+
[Intel-gfx] [CI 1/4] drm/i915/dmc: Introduce DMC_FW_MAIN
This is a prep patch for Pipe DMC plugging.
Add dmc_info struct in intel_dmc to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
v2: Remove dmc_offset and start_mmioaddr from dmc_info struct (Jose)
Cc: Souza, Jose
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 38 +---
drivers/gpu/drm/i915/display/intel_dmc.h | 18 +++
2 files changed, 33 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 97308da28059..269a57d936ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
bool intel_dmc_has_payload(struct drm_i915_private *i915)
{
- return i915->dmc.dmc_payload;
+ return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
static const struct stepping_info skl_stepping_info[] = {
@@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
*/
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
- u32 *payload = dev_priv->dmc.dmc_payload;
+ struct intel_dmc *dmc = &dev_priv->dmc;
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
u32 i, fw_size;
if (!HAS_DMC(dev_priv)) {
@@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- if (!intel_dmc_has_payload(dev_priv)) {
+ if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
}
- fw_size = dev_priv->dmc.dmc_fw_size;
+ fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
for (i = 0; i < fw_size; i++)
intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- payload[i]);
+ dmc_info->payload[i]);
preempt_enable();
- for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
- intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
- dev_priv->dmc.mmiodata[i]);
+ for (i = 0; i < dmc_info->mmio_count; i++) {
+ intel_de_write(dev_priv, dmc_info->mmioaddr[i],
+ dmc_info->mmiodata[i]);
}
dev_priv->dmc.dc_state = 0;
@@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
size_t rem_size)
{
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
u8 *payload;
- BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
-ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
/*
* Check if we can access common fields, we will checkc again below
@@ -469,10 +471,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
mmioaddr[i]);
return 0;
}
- dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
- dmc->mmiodata[i] = mmiodata[i];
+ dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
+ dmc_info->mmiodata[i] = mmiodata[i];
}
- dmc->mmio_count = mmio_count;
+ dmc_info->mmio_count = mmio_count;
rem_size -= header_len_bytes;
@@ -485,14 +487,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
drm_err(&i915->drm, "DMC FW too big (%u bytes)\n",
payload_size);
return 0;
}
- dmc->dmc_fw_size = dmc_header->fw_size;
+ dmc_info->dmc_fw_size = dmc_header->fw_size;
- dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!dmc->dmc_payload)
+ dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
+ if (!dmc_info->payload)
return 0;
payload = (u8 *)(dmc_header) + header_len_bytes;
- memcpy(dmc->dmc_payload, payload, payload_size);
+ memcpy(dmc_info->payload, payload, payload_size);
return header_len_bytes + payload_size;
@@ -827,5 +829,5 @@ void intel_dmc_ucode_fini(struct drm_i915_priva
[Intel-gfx] [CI 3/4] drm/i915/adl_p: Pipe B DMC Support
ADLP requires us to load both Pipe A and Pipe B.
Plug Pipe B loading support.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2a1c39a0e56e..db38891a9ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -546,6 +546,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "path: %s\n", dmc->fw_path);
seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
+ seq_printf(m, "Pipe B fw support: %s\n",
yesno(IS_ALDERLAKE_P(dev_priv)));
+ seq_printf(m, "Pipe B fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEB].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 007a284b0ef0..c3c00ff03869 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -19,6 +19,7 @@ struct drm_i915_private;
enum {
DMC_FW_MAIN = 0,
DMC_FW_PIPEA,
+ DMC_FW_PIPEB,
DMC_FW_MAX
};
--
2.25.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC
Load DMC v2.10 on ADLP. The release notes mention that
this version enables few power savings features.
v2: Add DMC_PATH() for ADLP (Lucas)
Cc: Lucas De Marchi
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 18e0d225a478..f8789d4543bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -45,6 +45,10 @@
#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 10)
+#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 10)
+MODULE_FIRMWARE(ADLP_DMC_PATH);
+
#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
MODULE_FIRMWARE(ADLS_DMC_PATH);
@@ -724,7 +728,11 @@ void intel_dmc_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_dmc_runtime_pm_get(dev_priv);
- if (IS_ALDERLAKE_S(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ dmc->fw_path = ADLP_DMC_PATH;
+ dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
dmc->fw_path = ADLS_DMC_PATH;
dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
--
2.25.0
___
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[Intel-gfx] [CI 0/4] Pipe DMC Support
One change from previous verison is a fix of SKL regression. Corner cases for stepping-substepping combination was missing from fw_info_matches_stepping() helper. Luckily SKL was the only platform in CI that came under this category and DMC refused to load. v2: SKL fix tested on SKL. v3: Minor changes in Pipe DMC plugging patch as suggested by Lucas v4: Remove the sanity check for MMIO that no longer apply to newer platforms.(Anusha) Anusha Srivatsa (4): drm/i915/dmc: Introduce DMC_FW_MAIN drm/i915/xelpd: Pipe A DMC plugging drm/i915/adl_p: Pipe B DMC Support drm/i915/adl_p: Load DMC .../drm/i915/display/intel_display_debugfs.c | 6 +- .../drm/i915/display/intel_display_power.c| 5 +- drivers/gpu/drm/i915/display/intel_dmc.c | 165 ++ drivers/gpu/drm/i915/display/intel_dmc.h | 23 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 5 files changed, 123 insertions(+), 78 deletions(-) -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging
> -Original Message-
> From: De Marchi, Lucas
> Sent: Wednesday, June 9, 2021 11:22 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging
>
> On Fri, Jun 04, 2021 at 12:01:26PM -0700, Anusha Srivatsa wrote:
> >This patch adds Pipe A plumbing to the already existing parsing and
> >loading functions which is taken care of in the prep patches. Adding
> >MAX_DMC_FW to keep track for both Main and Pipe A DMC while loading
> the
> >respective blobs.
> >
> >Also adding present field in dmc_info.
> >s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
> >fw_info_matches_stepping() helper. CSR_PROGRAM() should now take
> the
> >starting address of the particular blob (Main or Pipe) and not hardcode
> >it.
> >
> >v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct.
> >
> >v3: Add a missing corner cases of stepping-substepping combination in
> >fw_info_matches_stepping() helper.
> >
> >Cc: Souza, Jose
> >Cc: Lucas De Marchi
> >Signed-off-by: Anusha Srivatsa
> >---
> > .../drm/i915/display/intel_display_debugfs.c | 4 +-
> > .../drm/i915/display/intel_display_power.c| 5 +-
> > drivers/gpu/drm/i915/display/intel_dmc.c | 130 +++---
> > drivers/gpu/drm/i915/display/intel_dmc.h | 4 +
> > drivers/gpu/drm/i915/i915_reg.h | 2 +-
> > 5 files changed, 89 insertions(+), 56 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >index 88bb05d5c483..2a1c39a0e56e 100644
> >--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void
> >*unused)
> >
> > seq_printf(m, "fw loaded: %s\n",
> yesno(intel_dmc_has_payload(dev_priv)));
> > seq_printf(m, "path: %s\n", dmc->fw_path);
> >+seq_printf(m, "Pipe A fw support: %s\n",
> yesno(INTEL_GEN(dev_priv) >= 12));
> >+seq_printf(m, "Pipe A fw loaded: %s\n",
> >+yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
> >
> > if (!intel_dmc_has_payload(dev_priv))
> > goto out;
> >@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void
> >*unused)
> >
> > out:
> > seq_printf(m, "program base: 0x%08x\n",
> >- intel_de_read(dev_priv, DMC_PROGRAM(0)));
> >+ intel_de_read(dev_priv,
> >+DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> > seq_printf(m, "ssp base: 0x%08x\n",
> >intel_de_read(dev_priv, DMC_SSP_BASE));
> > seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv,
> DMC_HTP_SKL));
> >diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> >b/drivers/gpu/drm/i915/display/intel_display_power.c
> >index 3e1f6ec61514..b7d4993feca6 100644
> >--- a/drivers/gpu/drm/i915/display/intel_display_power.c
> >+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> >@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private
> >*dev_priv) static void assert_dmc_loaded(struct drm_i915_private
> >*dev_priv) {
> > drm_WARN_ONCE(&dev_priv->drm,
> >- !intel_de_read(dev_priv, DMC_PROGRAM(0)),
> >- "DMC program storage start is NULL\n");
> >+ !intel_de_read(dev_priv,
> >+ DMC_PROGRAM(dev_priv-
> >dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
> >+ "DMC program storage start is NULL\n");
> > drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv,
> DMC_SSP_BASE),
> > "DMC SSP Base Not fine\n");
> > drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv,
> DMC_HTP_SKL),
> >diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> >b/drivers/gpu/drm/i915/display/intel_dmc.c
> >index b78cb44731fe..09f65ad71f7e 100644
> >--- a/drivers/gpu/drm/i915/display/intel_dmc.c
> >+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> >@@ -317,8 +317,7 @@ static void gen9_set_dc_state_debugmask(struct
> >drm_i915_private *dev_priv) void intel_dmc_load_program(struct
> >drm_i915_private *dev_priv) {
> > struct intel_dmc *dmc = &dev_priv->dmc;
> >-struct dmc_fw_info *dmc_info = &dmc-
> >dm
[Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC
Load DMC v2.10 on ADLP. The release notes mention that
this version enables few power savings features.
v2: Add DMC_PATH() for ADLP (Lucas)
Cc: Lucas De Marchi
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 449fce65e139..48d0a5a69627 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -45,6 +45,10 @@
#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 10)
+#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 10)
+MODULE_FIRMWARE(ADLP_DMC_PATH);
+
#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
MODULE_FIRMWARE(ADLS_DMC_PATH);
@@ -729,7 +733,11 @@ void intel_dmc_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_dmc_runtime_pm_get(dev_priv);
- if (IS_ALDERLAKE_S(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ dmc->fw_path = ADLP_DMC_PATH;
+ dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
dmc->fw_path = ADLS_DMC_PATH;
dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
--
2.25.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/4] drm/i915/adl_p: Pipe B DMC Support
ADLP requires us to load both Pipe A and Pipe B.
Plug Pipe B loading support.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2a1c39a0e56e..db38891a9ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -546,6 +546,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "path: %s\n", dmc->fw_path);
seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
+ seq_printf(m, "Pipe B fw support: %s\n",
yesno(IS_ALDERLAKE_P(dev_priv)));
+ seq_printf(m, "Pipe B fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEB].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 007a284b0ef0..c3c00ff03869 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -19,6 +19,7 @@ struct drm_i915_private;
enum {
DMC_FW_MAIN = 0,
DMC_FW_PIPEA,
+ DMC_FW_PIPEB,
DMC_FW_MAX
};
--
2.25.0
___
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[Intel-gfx] [CI 1/4] drm/i915/dmc: Introduce DMC_FW_MAIN
This is a prep patch for Pipe DMC plugging.
Add dmc_info struct in intel_dmc to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
v2: Remove dmc_offset and start_mmioaddr from dmc_info struct (Jose)
Cc: Souza, Jose
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 38 +---
drivers/gpu/drm/i915/display/intel_dmc.h | 18 +++
2 files changed, 33 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 97308da28059..269a57d936ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
bool intel_dmc_has_payload(struct drm_i915_private *i915)
{
- return i915->dmc.dmc_payload;
+ return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
static const struct stepping_info skl_stepping_info[] = {
@@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
*/
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
- u32 *payload = dev_priv->dmc.dmc_payload;
+ struct intel_dmc *dmc = &dev_priv->dmc;
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
u32 i, fw_size;
if (!HAS_DMC(dev_priv)) {
@@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- if (!intel_dmc_has_payload(dev_priv)) {
+ if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
}
- fw_size = dev_priv->dmc.dmc_fw_size;
+ fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
for (i = 0; i < fw_size; i++)
intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- payload[i]);
+ dmc_info->payload[i]);
preempt_enable();
- for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
- intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
- dev_priv->dmc.mmiodata[i]);
+ for (i = 0; i < dmc_info->mmio_count; i++) {
+ intel_de_write(dev_priv, dmc_info->mmioaddr[i],
+ dmc_info->mmiodata[i]);
}
dev_priv->dmc.dc_state = 0;
@@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
size_t rem_size)
{
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
u8 *payload;
- BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
-ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
/*
* Check if we can access common fields, we will checkc again below
@@ -469,10 +471,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
mmioaddr[i]);
return 0;
}
- dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
- dmc->mmiodata[i] = mmiodata[i];
+ dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
+ dmc_info->mmiodata[i] = mmiodata[i];
}
- dmc->mmio_count = mmio_count;
+ dmc_info->mmio_count = mmio_count;
rem_size -= header_len_bytes;
@@ -485,14 +487,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
drm_err(&i915->drm, "DMC FW too big (%u bytes)\n",
payload_size);
return 0;
}
- dmc->dmc_fw_size = dmc_header->fw_size;
+ dmc_info->dmc_fw_size = dmc_header->fw_size;
- dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!dmc->dmc_payload)
+ dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
+ if (!dmc_info->payload)
return 0;
payload = (u8 *)(dmc_header) + header_len_bytes;
- memcpy(dmc->dmc_payload, payload, payload_size);
+ memcpy(dmc_info->payload, payload, payload_size);
return header_len_bytes + payload_size;
@@ -827,5 +829,5 @@ void intel_dmc_ucode_fini(struct drm_i915_priva
[Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging
This patch adds Pipe A plumbing to the already
existing parsing and loading functions which is
taken care of in the prep patches. Adding MAX_DMC_FW
to keep track for both Main and Pipe A DMC while loading
the respective blobs.
Also adding present field in dmc_info.
s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
fw_info_matches_stepping() helper. CSR_PROGRAM() should now
take the starting address of the particular blob (Main or Pipe)
and not hardcode it.
v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct.
v3: Add a missing corner cases of stepping-substepping combination in
fw_info_matches_stepping() helper.
v4: Add macro for start_mmioaddr for V1 package. Simplify code
in dmc_set_fw_offset (Lucas)
Cc: Souza, Jose
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_power.c| 5 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 128 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 4 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
5 files changed, 86 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 88bb05d5c483..2a1c39a0e56e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "fw loaded: %s\n",
yesno(intel_dmc_has_payload(dev_priv)));
seq_printf(m, "path: %s\n", dmc->fw_path);
+ seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
+ seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
out:
seq_printf(m, "program base: 0x%08x\n",
- intel_de_read(dev_priv, DMC_PROGRAM(0)));
+ intel_de_read(dev_priv,
DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
seq_printf(m, "ssp base: 0x%08x\n",
intel_de_read(dev_priv, DMC_SSP_BASE));
seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4298ae684d7d..285380079aab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private
*dev_priv)
static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
{
drm_WARN_ONCE(&dev_priv->drm,
- !intel_de_read(dev_priv, DMC_PROGRAM(0)),
- "DMC program storage start is NULL\n");
+ !intel_de_read(dev_priv,
+
DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+"DMC program storage start is NULL\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 269a57d936ab..449fce65e139 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -96,6 +96,7 @@ MODULE_FIRMWARE(BXT_DMC_PATH);
#define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
#define DMC_V1_MAX_MMIO_COUNT 8
#define DMC_V3_MAX_MMIO_COUNT 20
+#define DMC_V1_MMIO_START_RANGE0x8
struct intel_css_header {
/* 0x09 for DMC */
@@ -317,8 +318,7 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
struct intel_dmc *dmc = &dev_priv->dmc;
- struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
- u32 i, fw_size;
+ u32 id, i;
if (!HAS_DMC(dev_priv)) {
drm_err(&dev_priv->drm,
@@ -332,20 +332,25 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
- for (i = 0; i < fw_size; i++)
- intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- dmc_info->payload[i]);
+ for (id = 0; id < DMC_FW_MAX; id++) {
+
[Intel-gfx] [CI 0/4] Pipe DMC Support
With all DMC cleanup patches merged, sending the rebased version of actual Pipe DMC bits. One change from previous verison is a fix of SKL regression. Corner cases for stepping-substepping combination was missing from fw_info_matches_stepping() helper. Luckily SKL was the only platform in CI that came under this category and DMC refused to load. v2: SKL fix tested on SKL. v3: Minor changes in Pipe DMC plugging patch as suggested by Lucas Anusha Srivatsa (4): drm/i915/dmc: Introduce DMC_FW_MAIN drm/i915/xelpd: Pipe A DMC plugging drm/i915/adl_p: Pipe B DMC Support drm/i915/adl_p: Load DMC .../drm/i915/display/intel_display_debugfs.c | 6 +- .../drm/i915/display/intel_display_power.c| 5 +- drivers/gpu/drm/i915/display/intel_dmc.c | 162 +++--- drivers/gpu/drm/i915/display/intel_dmc.h | 23 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 5 files changed, 124 insertions(+), 74 deletions(-) -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC
Load DMC v2.10 on ADLP. The release notes mention that
this version enables few power savings features.
Cc: Lucas De Marchi
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 09f65ad71f7e..52cedd5ea48e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -45,6 +45,10 @@
#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define ADLP_DMC_PATH "i915/adlp_dmc_ver2_10.bin"
+#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 10)
+MODULE_FIRMWARE(ADLP_DMC_PATH);
+
#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
MODULE_FIRMWARE(ADLS_DMC_PATH);
@@ -727,7 +731,11 @@ void intel_dmc_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_dmc_runtime_pm_get(dev_priv);
- if (IS_ALDERLAKE_S(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ dmc->fw_path = ADLP_DMC_PATH;
+ dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
dmc->fw_path = ADLS_DMC_PATH;
dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 0/4] Pipe DMC Support
With all DMC cleanup patches merged, sending the rebased version of actual Pipe DMC bits. One change from previous verison is a fix of SKL regression. Corner cases for stepping-substepping combination was missing from fw_info_matches_stepping() helper. Luckily SKL was the only platform in CI that came under this category and DMC refused to load. This fix is tested on SKL. Anusha Srivatsa (4): drm/i915/dmc: Introduce DMC_FW_MAIN xdrm/i915/xelpd: Pipe A DMC plugging drm/i915/adl_p: Pipe B DMC Support drm/i915/adl_p: Load DMC .../drm/i915/display/intel_display_debugfs.c | 6 +- .../drm/i915/display/intel_display_power.c| 5 +- drivers/gpu/drm/i915/display/intel_dmc.c | 170 ++ drivers/gpu/drm/i915/display/intel_dmc.h | 23 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 5 files changed, 127 insertions(+), 79 deletions(-) -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging
This patch adds Pipe A plumbing to the already
existing parsing and loading functions which is
taken care of in the prep patches. Adding MAX_DMC_FW
to keep track for both Main and Pipe A DMC while loading
the respective blobs.
Also adding present field in dmc_info.
s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
fw_info_matches_stepping() helper. CSR_PROGRAM() should now
take the starting address of the particular blob (Main or Pipe)
and not hardcode it.
v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct.
v3: Add a missing corner cases of stepping-substepping combination in
fw_info_matches_stepping() helper.
Cc: Souza, Jose
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_power.c| 5 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 130 +++---
drivers/gpu/drm/i915/display/intel_dmc.h | 4 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
5 files changed, 89 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 88bb05d5c483..2a1c39a0e56e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "fw loaded: %s\n",
yesno(intel_dmc_has_payload(dev_priv)));
seq_printf(m, "path: %s\n", dmc->fw_path);
+ seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
+ seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
out:
seq_printf(m, "program base: 0x%08x\n",
- intel_de_read(dev_priv, DMC_PROGRAM(0)));
+ intel_de_read(dev_priv,
DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
seq_printf(m, "ssp base: 0x%08x\n",
intel_de_read(dev_priv, DMC_SSP_BASE));
seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3e1f6ec61514..b7d4993feca6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private
*dev_priv)
static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
{
drm_WARN_ONCE(&dev_priv->drm,
- !intel_de_read(dev_priv, DMC_PROGRAM(0)),
- "DMC program storage start is NULL\n");
+ !intel_de_read(dev_priv,
+
DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+"DMC program storage start is NULL\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index b78cb44731fe..09f65ad71f7e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -317,8 +317,7 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
struct intel_dmc *dmc = &dev_priv->dmc;
- struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
- u32 i, fw_size;
+ u32 id, i;
if (!HAS_DMC(dev_priv)) {
drm_err(&dev_priv->drm,
@@ -332,20 +331,25 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
- for (i = 0; i < fw_size; i++)
- intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- dmc_info->payload[i]);
+ for (id = 0; id < DMC_FW_MAX; id++) {
+ for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) {
+ intel_uncore_write_fw(&dev_priv->uncore,
+
DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i),
+ dmc->dmc_info[id].payload[i]);
+ }
+ }
preempt_enable();
-
[Intel-gfx] [CI 3/4] drm/i915/adl_p: Pipe B DMC Support
ADLP requires us to load both Pipe A and Pipe B.
Plug Pipe B loading support.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2a1c39a0e56e..db38891a9ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -546,6 +546,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "path: %s\n", dmc->fw_path);
seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
+ seq_printf(m, "Pipe B fw support: %s\n",
yesno(IS_ALDERLAKE_P(dev_priv)));
+ seq_printf(m, "Pipe B fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEB].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 007a284b0ef0..c3c00ff03869 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -19,6 +19,7 @@ struct drm_i915_private;
enum {
DMC_FW_MAIN = 0,
DMC_FW_PIPEA,
+ DMC_FW_PIPEB,
DMC_FW_MAX
};
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/4] drm/i915/dmc: Introduce DMC_FW_MAIN
This is a prep patch for Pipe DMC plugging.
Add dmc_info struct in intel_dmc to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
v2: Remove dmc_offset and start_mmioaddr from dmc_info struct (Jose)
Cc: Souza, Jose
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 44 +++-
drivers/gpu/drm/i915/display/intel_dmc.h | 18 +++---
2 files changed, 33 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 97308da28059..b78cb44731fe 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
bool intel_dmc_has_payload(struct drm_i915_private *i915)
{
- return i915->dmc.dmc_payload;
+ return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
static const struct stepping_info skl_stepping_info[] = {
@@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
*/
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
- u32 *payload = dev_priv->dmc.dmc_payload;
+ struct intel_dmc *dmc = &dev_priv->dmc;
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
u32 i, fw_size;
if (!HAS_DMC(dev_priv)) {
@@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- if (!intel_dmc_has_payload(dev_priv)) {
+ if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
}
- fw_size = dev_priv->dmc.dmc_fw_size;
+ fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
for (i = 0; i < fw_size; i++)
intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- payload[i]);
+ dmc_info->payload[i]);
preempt_enable();
- for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
- intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
- dev_priv->dmc.mmiodata[i]);
+ for (i = 0; i < dmc_info->mmio_count; i++) {
+ intel_de_write(dev_priv, dmc_info->mmioaddr[i],
+ dmc_info->mmiodata[i]);
}
dev_priv->dmc.dc_state = 0;
@@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
size_t rem_size)
{
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
u8 *payload;
- BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
-ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
/*
* Check if we can access common fields, we will checkc again below
@@ -463,16 +465,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
}
for (i = 0; i < mmio_count; i++) {
- if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
- mmioaddr[i] > DMC_MMIO_END_RANGE) {
- drm_err(&i915->drm, "DMC firmware has wrong mmio
address 0x%x\n",
- mmioaddr[i]);
- return 0;
- }
- dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
- dmc->mmiodata[i] = mmiodata[i];
+ dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
+ dmc_info->mmiodata[i] = mmiodata[i];
}
- dmc->mmio_count = mmio_count;
+ dmc_info->mmio_count = mmio_count;
rem_size -= header_len_bytes;
@@ -485,14 +481,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
drm_err(&i915->drm, "DMC FW too big (%u bytes)\n",
payload_size);
return 0;
}
- dmc->dmc_fw_size = dmc_header->fw_size;
+ dmc_info->dmc_fw_size = dmc_header->fw_size;
- dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!dmc->dmc_payload)
+ dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
+ if (!dmc_info->payload)
return 0;
payload = (u8 *)(dmc_he
[Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC
Load DMC v2.06 on ADLP. The release notes mention that
this version enables few power savings features.
Cc: Lucas De Marchi
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 09f65ad71f7e..52cedd5ea48e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -45,6 +45,10 @@
#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define ADLP_DMC_PATH "i915/adlp_dmc_ver2_10.bin"
+#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 10)
+MODULE_FIRMWARE(ADLP_DMC_PATH);
+
#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
MODULE_FIRMWARE(ADLS_DMC_PATH);
@@ -727,7 +731,11 @@ void intel_dmc_ucode_init(struct drm_i915_private
*dev_priv)
*/
intel_dmc_runtime_pm_get(dev_priv);
- if (IS_ALDERLAKE_S(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ dmc->fw_path = ADLP_DMC_PATH;
+ dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
dmc->fw_path = ADLS_DMC_PATH;
dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 0/4] Pipe DMC Support
With all DMC cleanup patches merged, sending the rebased version of actual Pipe DMC bits. One change from previous verison is a fix of SKL regression. Corner cases for stepping-substepping combination was missing from fw_info_matches_stepping() helper. Luckily SKL was the only platform in CI that came under this category and DMC refused to load. This fix is tested on SKL. Anusha Srivatsa (4): drm/i915/dmc: Introduce DMC_FW_MAIN xdrm/i915/xelpd: Pipe A DMC plugging drm/i915/adl_p: Pipe B DMC Support drm/i915/adl_p: Load DMC .../drm/i915/display/intel_display_debugfs.c | 6 +- .../drm/i915/display/intel_display_power.c| 5 +- drivers/gpu/drm/i915/display/intel_dmc.c | 170 ++ drivers/gpu/drm/i915/display/intel_dmc.h | 23 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 5 files changed, 127 insertions(+), 79 deletions(-) -- 2.25.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/4] drm/i915/adl_p: Pipe B DMC Support
ADLP requires us to load both Pipe A and Pipe B.
Plug Pipe B loading support.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2a1c39a0e56e..db38891a9ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -546,6 +546,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "path: %s\n", dmc->fw_path);
seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
+ seq_printf(m, "Pipe B fw support: %s\n",
yesno(IS_ALDERLAKE_P(dev_priv)));
+ seq_printf(m, "Pipe B fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEB].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 007a284b0ef0..c3c00ff03869 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -19,6 +19,7 @@ struct drm_i915_private;
enum {
DMC_FW_MAIN = 0,
DMC_FW_PIPEA,
+ DMC_FW_PIPEB,
DMC_FW_MAX
};
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging
This patch adds Pipe A plumbing to the already
existing parsing and loading functions which is
taken care of in the prep patches. Adding MAX_DMC_FW
to keep track for both Main and Pipe A DMC while loading
the respective blobs.
Also adding present field in dmc_info.
s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
fw_info_matches_stepping() helper. CSR_PROGRAM() should now
take the starting address of the particular blob (Main or Pipe)
and not hardcode it.
v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct.
v3: Add a missing corner cases of stepping-substepping combination in
fw_info_matches_stepping() helper.
Cc: Souza, Jose
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_power.c| 5 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 130 +++---
drivers/gpu/drm/i915/display/intel_dmc.h | 4 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
5 files changed, 89 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 88bb05d5c483..2a1c39a0e56e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "fw loaded: %s\n",
yesno(intel_dmc_has_payload(dev_priv)));
seq_printf(m, "path: %s\n", dmc->fw_path);
+ seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >=
12));
+ seq_printf(m, "Pipe A fw loaded: %s\n",
yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
out:
seq_printf(m, "program base: 0x%08x\n",
- intel_de_read(dev_priv, DMC_PROGRAM(0)));
+ intel_de_read(dev_priv,
DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
seq_printf(m, "ssp base: 0x%08x\n",
intel_de_read(dev_priv, DMC_SSP_BASE));
seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3e1f6ec61514..b7d4993feca6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private
*dev_priv)
static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
{
drm_WARN_ONCE(&dev_priv->drm,
- !intel_de_read(dev_priv, DMC_PROGRAM(0)),
- "DMC program storage start is NULL\n");
+ !intel_de_read(dev_priv,
+
DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+"DMC program storage start is NULL\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index b78cb44731fe..09f65ad71f7e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -317,8 +317,7 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
struct intel_dmc *dmc = &dev_priv->dmc;
- struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
- u32 i, fw_size;
+ u32 id, i;
if (!HAS_DMC(dev_priv)) {
drm_err(&dev_priv->drm,
@@ -332,20 +331,25 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
- for (i = 0; i < fw_size; i++)
- intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- dmc_info->payload[i]);
+ for (id = 0; id < DMC_FW_MAX; id++) {
+ for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) {
+ intel_uncore_write_fw(&dev_priv->uncore,
+
DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i),
+ dmc->dmc_info[id].payload[i]);
+ }
+ }
preempt_enable();
-
[Intel-gfx] [CI 1/4] drm/i915/dmc: Introduce DMC_FW_MAIN
This is a prep patch for Pipe DMC plugging.
Add dmc_info struct in intel_dmc to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
v2: Remove dmc_offset and start_mmioaddr from dmc_info struct (Jose)
Cc: Souza, Jose
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 44 +++-
drivers/gpu/drm/i915/display/intel_dmc.h | 18 +++---
2 files changed, 33 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 97308da28059..b78cb44731fe 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
bool intel_dmc_has_payload(struct drm_i915_private *i915)
{
- return i915->dmc.dmc_payload;
+ return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
static const struct stepping_info skl_stepping_info[] = {
@@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
*/
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
- u32 *payload = dev_priv->dmc.dmc_payload;
+ struct intel_dmc *dmc = &dev_priv->dmc;
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
u32 i, fw_size;
if (!HAS_DMC(dev_priv)) {
@@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- if (!intel_dmc_has_payload(dev_priv)) {
+ if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
}
- fw_size = dev_priv->dmc.dmc_fw_size;
+ fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
for (i = 0; i < fw_size; i++)
intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- payload[i]);
+ dmc_info->payload[i]);
preempt_enable();
- for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
- intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
- dev_priv->dmc.mmiodata[i]);
+ for (i = 0; i < dmc_info->mmio_count; i++) {
+ intel_de_write(dev_priv, dmc_info->mmioaddr[i],
+ dmc_info->mmiodata[i]);
}
dev_priv->dmc.dc_state = 0;
@@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
size_t rem_size)
{
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
u8 *payload;
- BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
-ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
/*
* Check if we can access common fields, we will checkc again below
@@ -463,16 +465,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
}
for (i = 0; i < mmio_count; i++) {
- if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
- mmioaddr[i] > DMC_MMIO_END_RANGE) {
- drm_err(&i915->drm, "DMC firmware has wrong mmio
address 0x%x\n",
- mmioaddr[i]);
- return 0;
- }
- dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
- dmc->mmiodata[i] = mmiodata[i];
+ dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
+ dmc_info->mmiodata[i] = mmiodata[i];
}
- dmc->mmio_count = mmio_count;
+ dmc_info->mmio_count = mmio_count;
rem_size -= header_len_bytes;
@@ -485,14 +481,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
drm_err(&i915->drm, "DMC FW too big (%u bytes)\n",
payload_size);
return 0;
}
- dmc->dmc_fw_size = dmc_header->fw_size;
+ dmc_info->dmc_fw_size = dmc_header->fw_size;
- dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!dmc->dmc_payload)
+ dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
+ if (!dmc_info->payload)
return 0;
payload = (u8 *)(dmc_he
[Intel-gfx] [PATCH 1/7] drm/i915/dmc: s/DRM_ERROR/drm_err
Use new format of debug messages across intel_csr.
While at it, change some function definitions which now
need dev_priv for drm_err and drm_info etc.
v2: use container_of() (Jani)
v3: Indentation fixes. (Jani)
Cc: Jani Nikula
Suggested-by: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 50
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 560574dd929a..5e9c0b509034 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -395,6 +395,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size)
{
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
@@ -439,28 +440,28 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
header_len_bytes = dmc_header->header_len;
dmc_header_size = sizeof(*v1);
} else {
- DRM_ERROR("Unknown DMC fw header version: %u\n",
- dmc_header->header_ver);
+ drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",
+ dmc_header->header_ver);
return 0;
}
if (header_len_bytes != dmc_header_size) {
- DRM_ERROR("DMC firmware has wrong dmc header length "
- "(%u bytes)\n", header_len_bytes);
+ drm_err(&i915->drm, "DMC firmware has wrong dmc header length "
+ "(%u bytes)\n", header_len_bytes);
return 0;
}
/* Cache the dmc header info. */
if (mmio_count > mmio_count_max) {
- DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
+ drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n",
mmio_count);
return 0;
}
for (i = 0; i < mmio_count; i++) {
if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
mmioaddr[i] > DMC_MMIO_END_RANGE) {
- DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
- mmioaddr[i]);
+ drm_err(&i915->drm, "DMC firmware has wrong mmio
address 0x%x\n",
+ mmioaddr[i]);
return 0;
}
dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
@@ -476,16 +477,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
goto error_truncated;
if (payload_size > dmc->max_fw_size) {
- DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
+ drm_err(&i915->drm, "DMC FW too big (%u bytes)\n",
payload_size);
return 0;
}
dmc->dmc_fw_size = dmc_header->fw_size;
dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!dmc->dmc_payload) {
- DRM_ERROR("Memory allocation failed for dmc payload\n");
+ if (!dmc->dmc_payload)
return 0;
- }
payload = (u8 *)(dmc_header) + header_len_bytes;
memcpy(dmc->dmc_payload, payload, payload_size);
@@ -493,7 +492,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
return header_len_bytes + payload_size;
error_truncated:
- DRM_ERROR("Truncated DMC firmware, refusing.\n");
+ drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
return 0;
}
@@ -503,6 +502,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
const struct stepping_info *si,
size_t rem_size)
{
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
u32 package_size = sizeof(struct intel_package_header);
u32 num_entries, max_entries, dmc_offset;
const struct intel_fw_info *fw_info;
@@ -515,8 +515,8 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
} else if (package_header->header_ver == 2) {
max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
} else {
- DRM_ERROR("DMC firmware has unknown header version %u\n",
- package_header->header_ver);
+ drm_err(&i915->drm, "DMC firmware has unknown header version
%u\n",
+ package_header->header_ver);
return 0;
[Intel-gfx] [PATCH 4/7] drm/i915/dmc: Introduce DMC_FW_MAIN
This is a prep patch for Pipe DMC plugging.
Add dmc_info struct in intel_dmc to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
v2: Remove dmc_offset and start_mmioaddr from dmc_info struct (Jose)
Cc: Souza, Jose
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 44 +++-
drivers/gpu/drm/i915/display/intel_dmc.h | 18 +++---
2 files changed, 33 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 97308da28059..b78cb44731fe 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
bool intel_dmc_has_payload(struct drm_i915_private *i915)
{
- return i915->dmc.dmc_payload;
+ return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
static const struct stepping_info skl_stepping_info[] = {
@@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct
drm_i915_private *dev_priv)
*/
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
- u32 *payload = dev_priv->dmc.dmc_payload;
+ struct intel_dmc *dmc = &dev_priv->dmc;
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
u32 i, fw_size;
if (!HAS_DMC(dev_priv)) {
@@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
return;
}
- if (!intel_dmc_has_payload(dev_priv)) {
+ if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
}
- fw_size = dev_priv->dmc.dmc_fw_size;
+ fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
for (i = 0; i < fw_size; i++)
intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- payload[i]);
+ dmc_info->payload[i]);
preempt_enable();
- for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
- intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
- dev_priv->dmc.mmiodata[i]);
+ for (i = 0; i < dmc_info->mmio_count; i++) {
+ intel_de_write(dev_priv, dmc_info->mmioaddr[i],
+ dmc_info->mmiodata[i]);
}
dev_priv->dmc.dc_state = 0;
@@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
size_t rem_size)
{
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
u8 *payload;
- BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
-ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
/*
* Check if we can access common fields, we will checkc again below
@@ -463,16 +465,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
}
for (i = 0; i < mmio_count; i++) {
- if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
- mmioaddr[i] > DMC_MMIO_END_RANGE) {
- drm_err(&i915->drm, "DMC firmware has wrong mmio
address 0x%x\n",
- mmioaddr[i]);
- return 0;
- }
- dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
- dmc->mmiodata[i] = mmiodata[i];
+ dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
+ dmc_info->mmiodata[i] = mmiodata[i];
}
- dmc->mmio_count = mmio_count;
+ dmc_info->mmio_count = mmio_count;
rem_size -= header_len_bytes;
@@ -485,14 +481,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
drm_err(&i915->drm, "DMC FW too big (%u bytes)\n",
payload_size);
return 0;
}
- dmc->dmc_fw_size = dmc_header->fw_size;
+ dmc_info->dmc_fw_size = dmc_header->fw_size;
- dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!dmc->dmc_payload)
+ dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
+ if (!dmc_info->payload)
return 0;
payload = (u8 *)(dmc_he
[Intel-gfx] [PATCH 3/7] drm/i915/dmc: Move struct intel_dmc to intel_dmc.h
Move struct intel_dmc from i915_drv.h to intel_dmc.h.
v2: Add includes along with moving the struct.
Reviewed-by: José Roberto de Souza
Reviewed-by: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dmc.h | 21 +
drivers/gpu/drm/i915/i915_drv.h | 18 +-
2 files changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 64816f4a71b6..4c22f567b61b 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -6,12 +6,33 @@
#ifndef __INTEL_DMC_H__
#define __INTEL_DMC_H__
+#include "i915_reg.h"
+#include "intel_wakeref.h"
+#include
+
struct drm_i915_private;
#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
#define DMC_VERSION_MAJOR(version) ((version) >> 16)
#define DMC_VERSION_MINOR(version) ((version) & 0x)
+struct intel_dmc {
+ struct work_struct work;
+ const char *fw_path;
+ u32 required_version;
+ u32 max_fw_size; /* bytes */
+ u32 *dmc_payload;
+ u32 dmc_fw_size; /* dwords */
+ u32 version;
+ u32 mmio_count;
+ i915_reg_t mmioaddr[20];
+ u32 mmiodata[20];
+ u32 dc_state;
+ u32 target_dc_state;
+ u32 allowed_dc_mask;
+ intel_wakeref_t wakeref;
+};
+
void intel_dmc_ucode_init(struct drm_i915_private *i915);
void intel_dmc_load_program(struct drm_i915_private *i915);
void intel_dmc_ucode_fini(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0f6d27da69ac..0c6301b28c37 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -67,6 +67,7 @@
#include "display/intel_bios.h"
#include "display/intel_display.h"
#include "display/intel_display_power.h"
+#include "display/intel_dmc.h"
#include "display/intel_dpll_mgr.h"
#include "display/intel_dsb.h"
#include "display/intel_frontbuffer.h"
@@ -328,23 +329,6 @@ struct drm_i915_display_funcs {
void (*read_luts)(struct intel_crtc_state *crtc_state);
};
-struct intel_dmc {
- struct work_struct work;
- const char *fw_path;
- u32 required_version;
- u32 max_fw_size; /* bytes */
- u32 *dmc_payload;
- u32 dmc_fw_size; /* dwords */
- u32 version;
- u32 mmio_count;
- i915_reg_t mmioaddr[20];
- u32 mmiodata[20];
- u32 dc_state;
- u32 target_dc_state;
- u32 allowed_dc_mask;
- intel_wakeref_t wakeref;
-};
-
enum i915_cache_level {
I915_CACHE_NONE = 0,
I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
--
2.25.0
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