Re: [Intel-gfx] [PATCH 28/56] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 28/56] drm/i915/adl_p: Extend PLANE_WM bits
> for blocks & lines
> 
> ADL-P further extends the bits in PLANE_WM that represent blocks and lines;
> we need to extend our masks accordingly.  Since these bits are reserved and
> MBZ on earlier platforms, it's safe to use the larger bitmask on all 
> platforms.
> 
> Bspec: 50419
> Cc: Matt Atwood 
> Signed-off-by: Matt Roper 
> Signed-off-by: Clinton Taylor 

Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index cdb2f7b136a9..1d0cb423720e
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6439,8 +6439,8 @@ enum {
>  #define _PLANE_WM_TRANS_2_B  0x71368
>  #define   PLANE_WM_EN(1 << 31)
>  #define   PLANE_WM_IGNORE_LINES  (1 << 30)
> -#define   PLANE_WM_LINES_MASKREG_GENMASK(21, 14)
> -#define   PLANE_WM_BLOCKS_MASK   0x7ff /* skl+: 10 bits, icl+ 11 bits */
> +#define   PLANE_WM_LINES_MASKREG_GENMASK(26, 14)
> +#define   PLANE_WM_BLOCKS_MASK   REG_GENMASK(11, 0)
> 
>  #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
> #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
> --
> 2.25.4
> 
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Re: [Intel-gfx] [PATCH 26/56] drm/i915/adl_p: Add PCH support

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 26/56] drm/i915/adl_p: Add PCH support
> 
> From: Clinton Taylor 
> 
> Add ADP-P PCH device ID and assign as ADL PCH if found. Previously we
> would assign the DDC pin map based on the PCH, but it can also change
> based on the CPU. From Bspec 20124: "The physical port to pin pair mapping
> are defined in the Bspec per PCH. Mapping can further change based on CPU
> Si used as CPU and PCH can be mixed and matched".
> 
> Bspec: 20124
> Cc: Matt Atwood 
> Cc: Matt Roper 
> Signed-off-by: Clinton Taylor 
> Signed-off-by: Matt Roper 
Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
>  drivers/gpu/drm/i915/intel_pch.c  | 6 --
>  drivers/gpu/drm/i915/intel_pch.h  | 1 +
>  4 files changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index e4cef54726b4..5f8d14be1265 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1649,7 +1649,7 @@ static u8 map_ddc_pin(struct drm_i915_private
> *dev_priv, u8 vbt_pin)
>   const u8 *ddc_pin_map;
>   int n_entries;
> 
> - if (HAS_PCH_ADP(dev_priv)) {
> + if (IS_ALDERLAKE_S(dev_priv)) {
>   ddc_pin_map = adls_ddc_pin_map;
>   n_entries = ARRAY_SIZE(adls_ddc_pin_map);
>   } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) { diff --git
> a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 4f285c7d54c4..2a2b01026564 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3213,7 +3213,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
> *encoder)
>   return ddc_pin;
>   }
> 
> - if (HAS_PCH_ADP(dev_priv))
> + if (IS_ALDERLAKE_S(dev_priv))
>   ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
>   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
>   ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); diff --git
> a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
> index 7476f0e063c6..98a17dd1bda4 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -130,8 +130,10 @@ intel_pch_type(const struct drm_i915_private
> *dev_priv, unsigned short id)
>   drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
>   return PCH_JSP;
>   case INTEL_PCH_ADP_DEVICE_ID_TYPE:
> + case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
>   drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
> - drm_WARN_ON(&dev_priv->drm,
> !IS_ALDERLAKE_S(dev_priv));
> + drm_WARN_ON(&dev_priv->drm,
> !IS_ALDERLAKE_S(dev_priv) &&
> + !IS_ALDERLAKE_P(dev_priv));
>   return PCH_ADP;
>   default:
>   return PCH_NONE;
> @@ -161,7 +163,7 @@ intel_virt_detect_pch(const struct drm_i915_private
> *dev_priv,
>* make an educated guess as to which PCH is really there.
>*/
> 
> - if (IS_ALDERLAKE_S(dev_priv))
> + if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
>   id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
>   else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
>   id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
> diff --git a/drivers/gpu/drm/i915/intel_pch.h
> b/drivers/gpu/drm/i915/intel_pch.h
> index 7318377503b0..e2f3f30c6445 100644
> --- a/drivers/gpu/drm/i915/intel_pch.h
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -55,6 +55,7 @@ enum intel_pch {
>  #define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
>  #define INTEL_PCH_JSP2_DEVICE_ID_TYPE0x3880
>  #define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
> +#define INTEL_PCH_ADP2_DEVICE_ID_TYPE0x5180
>  #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
>  #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
>  #define INTEL_PCH_QEMU_DEVICE_ID_TYPE0x2900 /* qemu q35
> has 2918 */
> --
> 2.25.4
> 
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Re: [Intel-gfx] [PATCH 24/56] drm/i915/adl_p: Add PCI Devices IDs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 24/56] drm/i915/adl_p: Add PCI Devices IDs
> 
> From: Clinton Taylor 
> 
> Add 12 known PCI device IDs
> 
> Bspec: 55376
> Cc: Caz Yokoyama 
> Cc: Matt Atwood 
> Cc: Matt Roper 
> Signed-off-by: Clinton Taylor 
> Signed-off-by: Matt Roper 

Reviewed-by: Anusha Srivatsa 

> ---
>  include/drm/i915_pciids.h | 20 
>  1 file changed, 20 insertions(+)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> ebd0dd1c35b3..6607b65e7ae2 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -645,4 +645,24 @@
>   INTEL_VGA_DEVICE(0x4692, info), \
>   INTEL_VGA_DEVICE(0x4693, info)
> 
> +/* ADL-P */
> +#define INTEL_ADLP_IDS(info) \
> + INTEL_VGA_DEVICE(0x46A0, info), \
> + INTEL_VGA_DEVICE(0x46A1, info), \
> + INTEL_VGA_DEVICE(0x46A2, info), \
> + INTEL_VGA_DEVICE(0x46A3, info), \
> + INTEL_VGA_DEVICE(0x46A6, info), \
> + INTEL_VGA_DEVICE(0x46A8, info), \
> + INTEL_VGA_DEVICE(0x46AA, info), \
> + INTEL_VGA_DEVICE(0x462A, info), \
> + INTEL_VGA_DEVICE(0x4626, info), \
> + INTEL_VGA_DEVICE(0x4628, info), \
> + INTEL_VGA_DEVICE(0x46B0, info), \
> + INTEL_VGA_DEVICE(0x46B1, info), \
> + INTEL_VGA_DEVICE(0x46B2, info), \
> + INTEL_VGA_DEVICE(0x46B3, info), \
> + INTEL_VGA_DEVICE(0x46C0, info), \
> + INTEL_VGA_DEVICE(0x46C1, info), \
> + INTEL_VGA_DEVICE(0x46C2, info), \
> + INTEL_VGA_DEVICE(0x46C3, info)
>  #endif /* _I915_PCIIDS_H */
> --
> 2.25.4
> 
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Re: [Intel-gfx] [PATCH 16/56] drm/i915/xelpd: Required bandwidth increases when VT-d is active

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 16/56] drm/i915/xelpd: Required bandwidth
> increases when VT-d is active
> 
> If VT-d is active, the memory bandwidth usage of the display is 5% higher.
> Take this into account when determining whether we can support a display
> configuration.
> 
> Bspec: 64631
> Cc: Matt Atwood 
> Signed-off-by: Matt Roper 

Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 20dbc3759d27..23cf9bf31e41 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -344,6 +344,9 @@ static unsigned int intel_bw_data_rate(struct
> drm_i915_private *dev_priv,
>   for_each_pipe(dev_priv, pipe)
>   data_rate += bw_state->data_rate[pipe];
> 
> + if (DISPLAY_VER(dev_priv) >= 13 && intel_vtd_active())
> + data_rate = data_rate * 105 / 100;
> +
>   return data_rate;
>  }
> 
> --
> 2.25.4
> 
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Re: [Intel-gfx] [PATCH 08/56] drm/i915/xelpd: Handle proper AUX interrupt bits

[Srivatsa, Anusha]

> -Original Message-
> From: Roper, Matthew D 
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; Srivatsa, Anusha
> ; De Marchi, Lucas
> 
> Subject: [PATCH 08/56] drm/i915/xelpd: Handle proper AUX interrupt bits
> 
> XE_LPD has new AUX interrupt bits for DDI-D and DDI-E that take the spots
> that were used by TC5/TC6 on Display12 platforms.
> 
> While we're at it, let's convert the bit definitions for all TGL+ aux bits 
> over to
> the modern REG_BIT() notation.
> 
> v2:
>  - Maintain bit order rather than logical order.  (Lucas)
>  - Convert surrounding code to REG_BIT() notation.  (Lucas)
> 
Reviewed-by: Anusha Srivatsa 

> Bspec: 50064
> Cc: Anusha Srivatsa 
> Cc: Lucas De Marchi 
> Signed-off-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 12 +++-
> drivers/gpu/drm/i915/i915_reg.h | 20 +++-
>  2 files changed, 22 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c index 23be88d59055..c9e03973502c
> 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2269,7 +2269,17 @@ static u32 gen8_de_port_aux_mask(struct
> drm_i915_private *dev_priv)  {
>   u32 mask;
> 
> - if (DISPLAY_VER(dev_priv) >= 12)
> + if (DISPLAY_VER(dev_priv) >= 13)
> + return TGL_DE_PORT_AUX_DDIA |
> + TGL_DE_PORT_AUX_DDIB |
> + TGL_DE_PORT_AUX_DDIC |
> + XELPD_DE_PORT_AUX_DDID |
> + XELPD_DE_PORT_AUX_DDIE |
> + TGL_DE_PORT_AUX_USBC1 |
> + TGL_DE_PORT_AUX_USBC2 |
> + TGL_DE_PORT_AUX_USBC3 |
> + TGL_DE_PORT_AUX_USBC4;
> + else if (DISPLAY_VER(dev_priv) >= 12)
>   return TGL_DE_PORT_AUX_DDIA |
>   TGL_DE_PORT_AUX_DDIB |
>   TGL_DE_PORT_AUX_DDIC |
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index e5dd0203991b..475d14db2844
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7855,15 +7855,17 @@ enum {
>  #define  BDW_DE_PORT_HOTPLUG_MASK
>   GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
>  #define  BXT_DE_PORT_GMBUS   (1 << 1)
>  #define  GEN8_AUX_CHANNEL_A  (1 << 0)
> -#define  TGL_DE_PORT_AUX_USBC6   (1 << 13)
> -#define  TGL_DE_PORT_AUX_USBC5   (1 << 12)
> -#define  TGL_DE_PORT_AUX_USBC4   (1 << 11)
> -#define  TGL_DE_PORT_AUX_USBC3   (1 << 10)
> -#define  TGL_DE_PORT_AUX_USBC2   (1 << 9)
> -#define  TGL_DE_PORT_AUX_USBC1   (1 << 8)
> -#define  TGL_DE_PORT_AUX_DDIC(1 << 2)
> -#define  TGL_DE_PORT_AUX_DDIB(1 << 1)
> -#define  TGL_DE_PORT_AUX_DDIA(1 << 0)
> +#define  TGL_DE_PORT_AUX_USBC6   REG_BIT(13)
> +#define  XELPD_DE_PORT_AUX_DDIE  REG_BIT(13)
> +#define  TGL_DE_PORT_AUX_USBC5   REG_BIT(12)
> +#define  XELPD_DE_PORT_AUX_DDID  REG_BIT(12)
> +#define  TGL_DE_PORT_AUX_USBC4   REG_BIT(11)
> +#define  TGL_DE_PORT_AUX_USBC3   REG_BIT(10)
> +#define  TGL_DE_PORT_AUX_USBC2   REG_BIT(9)
> +#define  TGL_DE_PORT_AUX_USBC1   REG_BIT(8)
> +#define  TGL_DE_PORT_AUX_DDICREG_BIT(2)
> +#define  TGL_DE_PORT_AUX_DDIBREG_BIT(1)
> +#define  TGL_DE_PORT_AUX_DDIAREG_BIT(0)
> 
>  #define GEN8_DE_MISC_ISR _MMIO(0x44460)  #define GEN8_DE_MISC_IMR
> _MMIO(0x44464)
> --
> 2.25.4

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Re: [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in intel_pm.c

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Matt
> Roper
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 04/56] drm/i915: Convert INTEL_GEN() to
> DISPLAY_VER() as appropriate in intel_pm.c
> 
> Although most of the code in this file is display-related (watermarks), 
> there's
> some functions that are not (e.g., clock gating).  Thus we need to do the
> conversions to DISPLAY_VER() manually here rather than using Coccinelle.
> 
> In the near-future we'll probably want to think about moving watermark
> logic out of intel_pm.c and into watermark-specific files under the display/
> directory.
> 
> Signed-off-by: Matt Roper 

Any reason Patch 4 and Patch 5 are not one single patch? It looks like both 
replace INTEL_GEN() with DISPLAY_VER() where necessary... 

Anusha 
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 132 
>  1 file changed, 66 insertions(+), 66 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c index 854ffecd98d9..2616b1845719
> 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2339,7 +2339,7 @@ static void i9xx_update_wm(struct intel_crtc
> *unused_crtc)
> 
>   if (IS_I945GM(dev_priv))
>   wm_info = &i945_wm_info;
> - else if (!IS_GEN(dev_priv, 2))
> + else if (DISPLAY_VER(dev_priv) != 2)
>   wm_info = &i915_wm_info;
>   else
>   wm_info = &i830_a_wm_info;
> @@ -2353,7 +2353,7 @@ static void i9xx_update_wm(struct intel_crtc
> *unused_crtc)
>   crtc->base.primary->state->fb;
>   int cpp;
> 
> - if (IS_GEN(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
>   cpp = 4;
>   else
>   cpp = fb->format->cpp[0];
> @@ -2368,7 +2368,7 @@ static void i9xx_update_wm(struct intel_crtc
> *unused_crtc)
>   planea_wm = wm_info->max_wm;
>   }
> 
> - if (IS_GEN(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
>   wm_info = &i830_bc_wm_info;
> 
>   fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B); @@ -
> 2380,7 +2380,7 @@ static void i9xx_update_wm(struct intel_crtc
> *unused_crtc)
>   crtc->base.primary->state->fb;
>   int cpp;
> 
> - if (IS_GEN(dev_priv, 2))
> + if (DISPLAY_VER(dev_priv) == 2)
>   cpp = 4;
>   else
>   cpp = fb->format->cpp[0];
> @@ -2652,9 +2652,9 @@ static u32 ilk_compute_fbc_wm(const struct
> intel_crtc_state *crtc_state,  static unsigned int  
> ilk_display_fifo_size(const
> struct drm_i915_private *dev_priv)  {
> - if (INTEL_GEN(dev_priv) >= 8)
> + if (DISPLAY_VER(dev_priv) >= 8)
>   return 3072;
> - else if (INTEL_GEN(dev_priv) >= 7)
> + else if (DISPLAY_VER(dev_priv) >= 7)
>   return 768;
>   else
>   return 512;
> @@ -2664,10 +2664,10 @@ static unsigned int
> ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
>int level, bool is_sprite)
>  {
> - if (INTEL_GEN(dev_priv) >= 8)
> + if (DISPLAY_VER(dev_priv) >= 8)
>   /* BDW primary/sprite plane watermarks */
>   return level == 0 ? 255 : 2047;
> - else if (INTEL_GEN(dev_priv) >= 7)
> + else if (DISPLAY_VER(dev_priv) >= 7)
>   /* IVB/HSW primary/sprite plane watermarks */
>   return level == 0 ? 127 : 1023;
>   else if (!is_sprite)
> @@ -2681,7 +2681,7 @@ ilk_plane_wm_reg_max(const struct
> drm_i915_private *dev_priv,  static unsigned int
> ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)  {
> - if (INTEL_GEN(dev_priv) >= 7)
> + if (DISPLAY_VER(dev_priv) >= 7)
>   return level == 0 ? 63 : 255;
>   else
>   return level == 0 ? 31 : 63;
> @@ -2689,7 +2689,7 @@ ilk_cursor_wm_reg_max(const struct
> drm_i915_private *dev_priv, int level)
> 
>  static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private
> *dev_priv)  {
> - if (INTEL_GEN(dev_priv) >= 8)
> + if (DISPLAY_VER(dev_priv) >= 8)
>   return 31;
>   else
>   return 15;
> @@ -2717,7 +2717,7 @@ static unsigned int ilk_plane_wm_max(const struct
> drm_i915_private *dev_priv,
>* FIFO size is only half of the self
>* refresh FIFO size on

Re: [Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support

[Srivatsa, Anusha]

> -Original Message-
> From: Chris Wilson 
> Sent: Monday, February 1, 2021 3:22 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support
> 
> Quoting Srivatsa, Anusha (2021-02-01 23:19:40)
> >
> >
> > > -Original Message-
> > > From: Chris Wilson 
> > > Sent: Monday, February 1, 2021 3:05 PM
> > > To: Srivatsa, Anusha ; intel-
> > > g...@lists.freedesktop.org
> > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC
> > > support
> > >
> > > Quoting Anusha Srivatsa (2021-02-01 23:01:33)
> > > > Add support to load GuC and HuC firmware for Dg1.
> > >
> > > Do you have the corresponding link for the linux-firmware.git? That
> > > is useful for cross referencing that the target version does exist
> > > in the public repository.
> >
> > I am waiting for CI runs before I can propagate it to linux-firmware.git.
> 
> From upstream CI? We don't have guc loading enabled for dg1, or much of
> dg1 for that matter. Best we can do is compile check :( -Chris

Totally missed that bit. I will go ahead with propagating PR to linux-firmware 
first. It might be sometime till we have DG1 working on CI.

Anusha
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Re: [Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support

[Srivatsa, Anusha]

> -Original Message-
> From: Chris Wilson 
> Sent: Monday, February 1, 2021 3:05 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support
> 
> Quoting Anusha Srivatsa (2021-02-01 23:01:33)
> > Add support to load GuC and HuC firmware for Dg1.
> 
> Do you have the corresponding link for the linux-firmware.git? That is
> useful for cross referencing that the target version does exist in the public
> repository.

I am waiting for CI runs before I can propagate it to linux-firmware.git. 

Anusha
> -Chris
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[Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support

[Anusha Srivatsa]

Add support to load GuC and HuC firmware for Dg1.

Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 984fa79e0fa7..0e63881674a4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -48,6 +48,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * firmware as TGL.
  */
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+   fw_def(DG1, 0, guc_def(dg1, 49, 0, 1), huc_def(dg1,  7, 7, 1)) \
fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
fw_def(ROCKETLAKE,  0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
fw_def(TIGERLAKE,   0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
-- 
2.25.0

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[Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support

[Anusha Srivatsa]

Add support to load GuC and HuC firmware for Dg1.

Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 67b06fde1225..31e24c3a947e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -47,6 +47,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * Note that RKL uses the same firmware as TGL.
  */
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+   fw_def(DG1, 0, guc_def(dg1, 49, 0, 1), huc_def(dg1,  7, 7, 1)) \
fw_def(ROCKETLAKE,  0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
fw_def(TIGERLAKE,   0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
fw_def(JASPERLAKE,  0, guc_def(ehl, 49, 0, 1), huc_def(ehl,  9, 0, 0)) \
-- 
2.25.0

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[Intel-gfx] DG1 Guc HuC and ADL-S DMC

[Srivatsa, Anusha]

Adding Pull Request for CI to grab these new updates:

The following changes since commit 05789708b79b38eb0f1a20d8449b4eb56d39b39f:

  brcm: Link RPi4's WiFi firmware with DMI machine name. (2021-01-19 07:42:43 
-0500)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-firmware DG1-guc-huc-ADLS-dmc

for you to fetch changes up to 348d8a9740930e7b8bd83a36baba40c5cfc3f8be:

  i915: Add DMC v2.01 for ADL-S (2021-01-29 11:43:12 -0800)


Anusha Srivatsa (3):
  i915: Add GuC v49.0.1 for DG1
  i915: Add HuC v7.7.1 for DG1
  i915: Add DMC v2.01 for ADL-S

WHENCE|   9 +
i915/adls_dmc_ver2_01.bin | Bin 0 -> 18704 bytes
i915/dg1_guc_49.0.1.bin   | Bin 0 -> 311872 bytes
i915/dg1_huc_7.7.1.bin| Bin 0 -> 582400 bytes
4 files changed, 9 insertions(+)
create mode 100644 i915/adls_dmc_ver2_01.bin
create mode 100644 i915/dg1_guc_49.0.1.bin
create mode 100644 i915/dg1_huc_7.7.1.bin


Thanks,
Anusha
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Re: [Intel-gfx] [PATCH 15/21] drm/i915/adl_s: Add display, gt, ctx and ADL-S

[Srivatsa, Anusha]

s/Add display, gt, ctx and ADL-S/ Add display, gt, ctx WA for ADL-S

Anusha


> -Original Message-
> From: Intel-gfx  On Behalf Of
> Aditya Swarup
> Sent: Tuesday, November 17, 2020 10:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
> 
> Subject: [Intel-gfx] [PATCH 15/21] drm/i915/adl_s: Add display, gt, ctx and
> ADL-S
> 
> - Inherit the gen12 workarounds.
> - Add placeholders to setup GT WA.
> - Extend permanent driver WA Wa_1409767108 to adl-s and
>   Wa_14010685332 to adl-s.
> - Extend permanent driver WA Wa_1606054188 to adl-s
> - Add Wa_14011765242 for adl-s A0 stepping.
> 
> v2:
> - Extend Wa_14010919138 and Wa_14010229206 to ADL-S (Madhumitha)
> - Extend Wa_22010271021 to ADLS (cyokoyam)
> 
> Cc: Jani Nikula 
> Cc: Ville Syrjälä 
> Cc: Imre Deak 
> Cc: Matt Roper 
> Cc: Lucas De Marchi 
> Signed-off-by: Madhumitha Tolakanahalli Pradeep
> 
> Signed-off-by: Aditya Swarup 
> ---
>  .../drm/i915/display/intel_display_power.c|  7 +-
>  drivers/gpu/drm/i915/display/intel_sprite.c   |  4 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 91 +--
>  drivers/gpu/drm/i915/intel_device_info.c  |  6 +-
>  4 files changed, 72 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 06c036e2092c..8b163d804a41 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5282,9 +5282,10 @@ static void tgl_bw_buddy_init(struct
> drm_i915_private *dev_priv)
>   unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
>   int config, i;
> 
> - if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> + if (IS_ALDERLAKE_S(dev_priv) ||
> + IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>   IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
> - /* Wa_1409767108:tgl,dg1 */
> + /* Wa_1409767108:tgl,dg1,adl-s */
>   table = wa_1409767108_buddy_page_masks;
>   else
>   table = tgl_buddy_page_masks;
> @@ -5322,7 +5323,7 @@ static void icl_display_core_init(struct
> drm_i915_private *dev_priv,
> 
>   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> 
> - /* Wa_14011294188:ehl,jsl,tgl,rkl */
> + /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
>   if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
>   INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
>   intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, diff --git
> a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index f7da4a56054e..1e954e2928fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2359,8 +2359,8 @@ static int skl_plane_check_fb(const struct
> intel_crtc_state *crtc_state,
>   return -EINVAL;
>   }
> 
> - /* Wa_1606054188:tgl */
> - if (IS_TIGERLAKE(dev_priv) &&
> + /* Wa_1606054188:tgl,adl-s */
> + if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>   plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
>   intel_format_is_p01x(fb->format->format)) {
>   drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d88d3d60fb1c..e6f149bd537f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -664,22 +664,6 @@ static void tgl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>struct i915_wa_list *wal)
>  {
>   gen12_ctx_workarounds_init(engine, wal);
> -
> - /*
> -  * Wa_1604555607:tgl,rkl
> -  *
> -  * Note that the implementation of this workaround is further
> modified
> -  * according to the FF_MODE2 guidance given by
> Wa_1608008084:gen12.
> -  * FF_MODE2 register will return the wrong value when read. The
> default
> -  * value for this register is zero for all fields and there are no bit
> -  * masks. So instead of doing a RMW we should just write the GS
> Timer
> -  * and TDS timer values for Wa_1604555607 and Wa_16011163337.
> -  */
> - wa_add(wal,
> -FF_MODE2,
> -FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK,
> -FF_MODE2_GS_TIMER_224  | FF_MODE2_TDS_TIMER_128,
> -0);
>  }
> 
>  static void dg1_ctx_workarounds_init(struct intel_engine_cs *engin

Re: [Intel-gfx] [PATCH 19/21] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of
> Aditya Swarup
> Sent: Tuesday, November 17, 2020 10:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
> 
> Subject: [Intel-gfx] [PATCH 19/21] drm/i915/display: Add
> HAS_D12_PLANE_MINIMIZATION
> 
> From: José Roberto de Souza 
> 
> - As RKL and ADL-S only have 5 planes, primary and 4 sprites and
>   the cursor plane, let's group the handling together under
>   HAS_D12_PLANE_MINIMIZATION.
> - Also use macro to select pipe irq fault error mask.
> 
> BSpec: 49251
> Cc: Lucas De Marchi 
> Cc: Jani Nikula 
> Cc: Ville Syrjälä 
> Cc: Imre Deak 
> Cc: Matt Roper 
> Signed-off-by: José Roberto de Souza 
> Signed-off-by: Aditya Swarup 

Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
>  drivers/gpu/drm/i915/i915_drv.h | 3 +++
>  drivers/gpu/drm/i915/i915_irq.c | 2 +-
>  drivers/gpu/drm/i915/intel_device_info.c| 2 +-
>  4 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 1e954e2928fe..f65fd937bc55 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -351,7 +351,7 @@ int intel_plane_check_src_coordinates(struct
> intel_plane_state *plane_state)
> 
>  static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)  {
> - if (IS_ROCKETLAKE(i915))
> + if (HAS_D12_PLANE_MINIMIZATION(i915))
>   return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
>   else
>   return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5); diff --git
> a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 817a5102b94f..f8d61785600d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1770,6 +1770,9 @@ extern const struct i915_rev_steppings
> adls_revids[];  #define INTEL_DISPLAY_ENABLED(dev_priv) \
>   (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),
> !(dev_priv)->params.disable_display)
> 
> +#define HAS_D12_PLANE_MINIMIZATION(dev_priv)
> (IS_ROCKETLAKE(dev_priv) || \
> +   IS_ALDERLAKE_S(dev_priv))
> +
>  static inline bool intel_vtd_active(void)  {  #ifdef CONFIG_INTEL_IOMMU
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c index 758ed4f6c9f3..e39db39cd796
> 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2246,7 +2246,7 @@ static u32 gen8_de_port_aux_mask(struct
> drm_i915_private *dev_priv)
> 
>  static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)  {
> - if (IS_ROCKETLAKE(dev_priv))
> + if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
>   return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
>   else if (INTEL_GEN(dev_priv) >= 11)
>   return GEN11_DE_PIPE_IRQ_FAULT_ERRORS; diff --git
> a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 64a09954fd54..49d5dac34d51 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -409,7 +409,7 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
> 
>   BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) <
> I915_NUM_ENGINES);
> 
> - if (IS_ROCKETLAKE(dev_priv))
> + if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
>   for_each_pipe(dev_priv, pipe)
>   runtime->num_sprites[pipe] = 4;
>   else if (INTEL_GEN(dev_priv) >= 11)
> --
> 2.27.0
> 
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Re: [Intel-gfx] [PATCH 13/21] drm/i915/adl_s: Update combo PHY master/slave relationships

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of
> Aditya Swarup
> Sent: Tuesday, November 17, 2020 10:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
> 
> Subject: [Intel-gfx] [PATCH 13/21] drm/i915/adl_s: Update combo PHY
> master/slave relationships
> 
> From: Matt Roper 
> 
> ADL-S switches up which PHYs are considered a master to other PHYs; PHY-C
> is no longer a master, but PHY-D is now.
> 
> Bspec: 49291
> Cc: Jani Nikula 
> Cc: Ville Syrjälä 
> Cc: Imre Deak 
> Cc: Lucas De Marchi 
> Signed-off-by: Matt Roper 
> Signed-off-by: Aditya Swarup 

Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/display/intel_combo_phy.c | 11 +--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index d5ad61e4083e..55d2d2d9efbb 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -246,14 +246,21 @@ static bool phy_is_master(struct
> drm_i915_private *dev_priv, enum phy phy)
>* RKL,DG1:
>*   A(master) -> B(slave)
>*   C(master) -> D(slave)
> +  * ADL-S:
> +  *   A(master) -> B(slave), C(slave)
> +  *   D(master) -> E(slave)
>*
>* We must set the IREFGEN bit for any PHY acting as a master
>* to another PHY.
>*/
> - if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy ==
> PHY_C)
> + if (phy == PHY_A)
>   return true;
> + else if (IS_ALDERLAKE_S(dev_priv))
> + return phy == PHY_D;
> + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
> + return phy == PHY_C;
> 
> - return phy == PHY_A;
> + return false;
>  }
> 
>  static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
> --
> 2.27.0
> 
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Re: [Intel-gfx] [PATCH 18/21] drm/i915/adl_s: Re-use TGL GuC/HuC firmware

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of
> Aditya Swarup
> Sent: Tuesday, November 17, 2020 10:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas 
> Subject: [Intel-gfx] [PATCH 18/21] drm/i915/adl_s: Re-use TGL GuC/HuC
> firmware
> 
> From: Matt Roper 
> 
> ADL-S, like RKL, uses the same internal device ID for the GuC and HuC as
> TGL did, making them all firmware-compatible.  Let's re-use TGL's firmware
> for ADL-S.
> 
> Bspec: 50668
> Cc: John Harrison 
> Cc: Lucas De Marchi 
> Signed-off-by: Matt Roper 
> Signed-off-by: Aditya Swarup 

Reviewed-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index 180c23e2e25e..2d123158df0d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -44,9 +44,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw
> *uc_fw,
>   * List of required GuC and HuC binaries per-platform.
>   * Must be ordered based on platform + revid, from newer to older.
>   *
> - * Note that RKL uses the same firmware as TGL.
> + * Note that RKL and ADL-S have the same GuC/HuC device ID's and use
> + the same
> + * firmware as TGL.
>   */
>  #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
> + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0))
> +\
>   fw_def(ROCKETLAKE,  0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
>   fw_def(TIGERLAKE,   0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
>   fw_def(JASPERLAKE,  0, guc_def(ehl, 49, 0, 1), huc_def(ehl,  9, 0, 0)) \
> --
> 2.27.0
> 
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Re: [Intel-gfx] [PATCH 21/21] drm/i915/adl_s: Update memory bandwidth parameters

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of
> Aditya Swarup
> Sent: Tuesday, November 17, 2020 10:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
> 
> Subject: [Intel-gfx] [PATCH 21/21] drm/i915/adl_s: Update memory
> bandwidth parameters
> 
> From: Tejas Upadhyay 
> 
> Just like RKL, the ADL_S platform also has different memory characteristics
> from past platforms.  Update the values used by our memory bandwidth
> calculations accordingly.
> 
> Bspec: 64631
> Cc: Matt Roper 
> Cc: Lucas De Marchi 
> Cc: Jani Nikula 
> Cc: Ville Syrjälä 
> Cc: Imre Deak 
> Signed-off-by: Tejas Upadhyay
> 
> Signed-off-by: Aditya Swarup 

Reviewed-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index bd060404d249..32522ec1ffb9 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -205,6 +205,12 @@ static const struct intel_sa_info rkl_sa_info = {
>   .displayrtids = 128,
>  };
> 
> +static const struct intel_sa_info adls_sa_info = {
> + .deburst = 16,
> + .deprogbwlimit = 38, /* GB/s */
> + .displayrtids = 256,
> +};
> +
>  static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
> intel_sa_info *sa)  {
>   struct intel_qgv_info qi = {};
> @@ -317,6 +323,8 @@ void intel_bw_init_hw(struct drm_i915_private
> *dev_priv)
> 
>   if (IS_ROCKETLAKE(dev_priv))
>   icl_get_bw_info(dev_priv, &rkl_sa_info);
> + else if (IS_ALDERLAKE_S(dev_priv))
> + icl_get_bw_info(dev_priv, &adls_sa_info);
>   else if (IS_GEN(dev_priv, 12))
>   icl_get_bw_info(dev_priv, &tgl_sa_info);
>   else if (IS_GEN(dev_priv, 11))
> --
> 2.27.0
> 
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Re: [Intel-gfx] [PATCH] drm/i915/ehl: Remove invalid PCI ID

[Srivatsa, Anusha]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Monday, November 2, 2020 9:29 AM
> To: Srivatsa, Anusha 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/ehl: Remove invalid PCI ID
> 
> On Fri, Oct 30, 2020 at 02:26:14PM -0700, Anusha Srivatsa wrote:
> > Update the EHL PCI IDs from BSpec.
> > Remove the invalid ones.
> >
> > Cc: Ville Syrjälä 
> > Signed-off-by: Anusha Srivatsa 
> 
> Reviewed-by: Ville Syrjälä 
> 
> Pls sort out the ci fail so we can merge this.

Merged.

Anusha 

> > ---
> >  include/drm/i915_pciids.h | 1 -
> >  1 file changed, 1 deletion(-)
> >
> > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > index 3b5ed1e4f3ec..28428e08a8d3 100644
> > --- a/include/drm/i915_pciids.h
> > +++ b/include/drm/i915_pciids.h
> > @@ -584,7 +584,6 @@
> >
> >  /* EHL */
> >  #define INTEL_EHL_IDS(info) \
> > -   INTEL_VGA_DEVICE(0x4500, info), \
> > INTEL_VGA_DEVICE(0x4571, info), \
> > INTEL_VGA_DEVICE(0x4551, info), \
> > INTEL_VGA_DEVICE(0x4541, info), \
> > --
> > 2.25.0
> 
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] [PATCH] drm/i915/ehl: Remove invalid PCI ID

[Anusha Srivatsa]

Update the EHL PCI IDs from BSpec.
Remove the invalid ones.

Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Ville Syrjälä 
---
 include/drm/i915_pciids.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 7eeecb07c9a1..ac884aabae07 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -581,7 +581,6 @@
 
 /* EHL/JSL */
 #define INTEL_EHL_IDS(info) \
-   INTEL_VGA_DEVICE(0x4500, info), \
INTEL_VGA_DEVICE(0x4571, info), \
INTEL_VGA_DEVICE(0x4551, info), \
INTEL_VGA_DEVICE(0x4541, info), \
-- 
2.25.0

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Re: [Intel-gfx] [PATCH] drm/i915/ehl: Remove invalid PCI ID

[Srivatsa, Anusha]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Monday, November 2, 2020 9:29 AM
> To: Srivatsa, Anusha 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/ehl: Remove invalid PCI ID
> 
> On Fri, Oct 30, 2020 at 02:26:14PM -0700, Anusha Srivatsa wrote:
> > Update the EHL PCI IDs from BSpec.
> > Remove the invalid ones.
> >
> > Cc: Ville Syrjälä 
> > Signed-off-by: Anusha Srivatsa 
> 
> Reviewed-by: Ville Syrjälä 
> 
> Pls sort out the ci fail so we can merge this.

Sure. Thanks!

Anusha
> > ---
> >  include/drm/i915_pciids.h | 1 -
> >  1 file changed, 1 deletion(-)
> >
> > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > index 3b5ed1e4f3ec..28428e08a8d3 100644
> > --- a/include/drm/i915_pciids.h
> > +++ b/include/drm/i915_pciids.h
> > @@ -584,7 +584,6 @@
> >
> >  /* EHL */
> >  #define INTEL_EHL_IDS(info) \
> > -   INTEL_VGA_DEVICE(0x4500, info), \
> > INTEL_VGA_DEVICE(0x4571, info), \
> > INTEL_VGA_DEVICE(0x4551, info), \
> > INTEL_VGA_DEVICE(0x4541, info), \
> > --
> > 2.25.0
> 
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] [PATCH] drm/i915/ehl: Remove invalid PCI ID

[Anusha Srivatsa]

Update the EHL PCI IDs from BSpec.
Remove the invalid ones.

Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
---
 include/drm/i915_pciids.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 3b5ed1e4f3ec..28428e08a8d3 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -584,7 +584,6 @@
 
 /* EHL */
 #define INTEL_EHL_IDS(info) \
-   INTEL_VGA_DEVICE(0x4500, info), \
INTEL_VGA_DEVICE(0x4571, info), \
INTEL_VGA_DEVICE(0x4551, info), \
INTEL_VGA_DEVICE(0x4541, info), \
-- 
2.25.0

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Re: [Intel-gfx] [PATCH v2] drm/i915: Sort EHL/JSL PCI IDs

[Srivatsa, Anusha]

> -Original Message-
> From: Ville Syrjala 
> Sent: Friday, October 30, 2020 9:41 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha 
> Subject: [PATCH v2] drm/i915: Sort EHL/JSL PCI IDs
> 
> From: Ville Syrjälä 
> 
> Sort the EHL/JSL PCI IDs numerically. Some order seems better than
> randomness.
> 
> v2: Deal with the JSL vs. EHL split
> 
> Reviewed-by: Anusha Srivatsa  #v1
> Signed-off-by: Ville Syrjälä 
> ---
>  include/drm/i915_pciids.h | 14 +++---
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 3b5ed1e4f3ec..4a0a06f4a81e 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -585,19 +585,19 @@
>  /* EHL */
>  #define INTEL_EHL_IDS(info) \
>   INTEL_VGA_DEVICE(0x4500, info), \
0x4500 is actually no longer  a valid PCI ID for the platform.

Anusha
> - INTEL_VGA_DEVICE(0x4571, info), \
> - INTEL_VGA_DEVICE(0x4551, info), \
>   INTEL_VGA_DEVICE(0x4541, info), \
> + INTEL_VGA_DEVICE(0x4551, info), \
> + INTEL_VGA_DEVICE(0x4555, info), \
>   INTEL_VGA_DEVICE(0x4557, info), \
> - INTEL_VGA_DEVICE(0x4555, info)
> + INTEL_VGA_DEVICE(0x4571, info)
> 
>  /* JSL */
>  #define INTEL_JSL_IDS(info) \
> - INTEL_VGA_DEVICE(0x4E71, info), \
> - INTEL_VGA_DEVICE(0x4E61, info), \
> - INTEL_VGA_DEVICE(0x4E57, info), \
> + INTEL_VGA_DEVICE(0x4E51, info), \
>   INTEL_VGA_DEVICE(0x4E55, info), \
> - INTEL_VGA_DEVICE(0x4E51, info)
> + INTEL_VGA_DEVICE(0x4E57, info), \
> + INTEL_VGA_DEVICE(0x4E61, info), \
> + INTEL_VGA_DEVICE(0x4E71, info)
> 
>  /* TGL */
>  #define INTEL_TGL_12_GT1_IDS(info) \
> --
> 2.26.2

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Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of
> Lucas De Marchi
> Sent: Monday, October 26, 2020 9:46 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers
> from MCHBAR
> 
> GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
> commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for
> Sandy Bridge").  Other than printing their values in debugfs we don't do
> anything with them.  There's not much useful information in them. These
> registers may change location in future platforms, but instead of adding
> new locations, it's simpler to just remove them.
> 
> Cc: Matt Roper 
> Signed-off-by: Lucas De Marchi 

Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 17 ++---
>  drivers/gpu/drm/i915/i915_debugfs.c | 17 ++---
>  drivers/gpu/drm/i915/i915_reg.h |  3 ---
>  3 files changed, 4 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> index 174a24553322..8a68088c12ea 100644
> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> @@ -296,8 +296,6 @@ static int frequency_show(struct seq_file *m, void
> *unused)
>   seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
>  intel_gpu_freq(rps, rps->efficient_freq));
>   } else if (INTEL_GEN(i915) >= 6) {
> - u32 rp_state_limits;
> - u32 gt_perf_status;
>   u32 rp_state_cap;
>   u32 rpmodectl, rpinclimit, rpdeclimit;
>   u32 rpstat, cagf, reqf;
> @@ -307,14 +305,10 @@ static int frequency_show(struct seq_file *m, void
> *unused)
>   u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
>   int max_freq;
> 
> - rp_state_limits = intel_uncore_read(uncore,
> GEN6_RP_STATE_LIMITS);
> - if (IS_GEN9_LP(i915)) {
> + if (IS_GEN9_LP(i915))
>   rp_state_cap = intel_uncore_read(uncore,
> BXT_RP_STATE_CAP);
> - gt_perf_status = intel_uncore_read(uncore,
> BXT_GT_PERF_STATUS);
> - } else {
> + else
>   rp_state_cap = intel_uncore_read(uncore,
> GEN6_RP_STATE_CAP);
> - gt_perf_status = intel_uncore_read(uncore,
> GEN6_GT_PERF_STATUS);
> - }
> 
>   /* RPSTAT1 is in the GT power well */
>   intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); @@
> -390,13 +384,6 @@ static int frequency_show(struct seq_file *m, void
> *unused)
>  pm_isr, pm_iir);
>   seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
>  rps->pm_intrmsk_mbz);
> - seq_printf(m, "GT_PERF_STATUS: 0x%08x\n",
> gt_perf_status);
> - seq_printf(m, "Render p-state ratio: %d\n",
> -(gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 :
> 0xff00)) >> 8);
> - seq_printf(m, "Render p-state VID: %d\n",
> -gt_perf_status & 0xff);
> - seq_printf(m, "Render p-state limit: %d\n",
> -rp_state_limits & 0xff);
>   seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
>   seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
>   seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); diff --git
> a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index ea469168cd44..c01f27eebf9c 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -838,8 +838,6 @@ static int i915_frequency_info(struct seq_file *m,
> void *unused)
>  "efficient (RPe) frequency: %d MHz\n",
>  intel_gpu_freq(rps, rps->efficient_freq));
>   } else if (INTEL_GEN(dev_priv) >= 6) {
> - u32 rp_state_limits;
> - u32 gt_perf_status;
>   u32 rp_state_cap;
>   u32 rpmodectl, rpinclimit, rpdeclimit;
>   u32 rpstat, cagf, reqf;
> @@ -848,14 +846,10 @@ static int i915_frequency_info(struct seq_file *m,
> void *unused)
>   u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
>   int max_freq;
> 
> - rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> - if (IS_GEN9_LP(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv))
>  

Re: [Intel-gfx] i915 Update : DG1 DMC

[Srivatsa, Anusha]

> -Original Message-
> From: Josh Boyer 
> Sent: Friday, October 23, 2020 4:58 AM
> To: Srivatsa, Anusha 
> Cc: linux-firmw...@kernel.org; Kyle McMartin ;
> b...@decadent.org.uk; intel-gfx@lists.freedesktop.org
> Subject: Re: i915 Update : DG1 DMC
> 
> Pulled and pushed out.
> 
> josh
>
Thanks Josh.

> On Fri, Oct 9, 2020 at 2:41 PM Srivatsa, Anusha
>  wrote:
> >
> > Hi Kyle, Ben,
> >
> >
> >
> > Please add the i915 updates to linux-firmware from branch
> > dg1_dmc_v2_02
> >
> >
> >
> > The following changes since commit
> 58d41d0facca2478d3e45f6321224361519aee96:
> >
> >
> >
> >   ice: Add comms package file for Intel E800 series driver (2020-10-05
> > 08:09:03 -0400)
> >
> >
> >
> > are available in the Git repository at: dg1_dmc_v2_02
> >
> >
> >
> >   git://anongit.freedesktop.org/drm/drm-firmware dg1_dmc_v2_02
> >
> >
> >
> > for you to fetch changes up to
> a140ef3eb3746aba2c897db16e02ffb5ffa9e7a2:
> >
> >
> >
> >   i915: Add DG1 DMC v2.02 (2020-10-08 12:13:33 -0700)
> >
> >
> >
> > 
> >
> > Anusha Srivatsa (1):
> >
> >   i915: Add DG1 DMC v2.02
> >
> >
> >
> > WHENCE   |   2 ++
> >
> > i915/dg1_dmc_ver2_02.bin | Bin 0 -> 16624 bytes
> >
> > 2 files changed, 2 insertions(+)
> >
> > create mode 100644 i915/dg1_dmc_ver2_02.bin
> >
> >
> >
> > Thanks,
> >
> > Anusha
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Re: [Intel-gfx] [PATCH] drm/i915/rkl: Add new cdclk table

[Srivatsa, Anusha]

> -Original Message-
> From: Matt Roper 
> Sent: Thursday, October 15, 2020 3:01 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; Srivatsa, Anusha
> 
> Subject: [PATCH] drm/i915/rkl: Add new cdclk table
> 
> A recent bspec update has provided a new cdclk table for RKL.  All of the
> cdclk values are the same as those we've been using on ICL, TGL, etc., but
> we obtain them by doubling both the PLL ratio and CD2X divider numbers.
> 
> Bspec: 49202
> Cc: Anusha Srivatsa 
> Signed-off-by: Matt Roper 
Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 32 +-
>  1 file changed, 31 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 7b46330fa69c..c449d28d0560 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1233,6 +1233,30 @@ static const struct intel_cdclk_vals
> icl_cdclk_table[] = {
>   {}
>  };
> 
> +static const struct intel_cdclk_vals rkl_cdclk_table[] = {
> + { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio =  36 },
> + { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio =  40 },
> + { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio =  64 },
> + { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
> + { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
> + { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
> +
> + { .refclk = 24000, .cdclk = 18, .divider = 4, .ratio =  30 },
> + { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio =  32 },
> + { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio =  52 },
> + { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
> + { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio =  92 },
> + { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
> +
> + { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
> + { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
> + { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
> + { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
> + { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
> + { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
> + {}
> +};
> +
>  static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
> {
>   const struct intel_cdclk_vals *table = dev_priv->cdclk.table; @@ -
> 2823,7 +2847,13 @@ u32 intel_read_rawclk(struct drm_i915_private
> *dev_priv)
>   */
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)  {
> - if (INTEL_GEN(dev_priv) >= 12) {
> + if (IS_ROCKETLAKE(dev_priv)) {
> + dev_priv->display.set_cdclk = bxt_set_cdclk;
> + dev_priv->display.bw_calc_min_cdclk =
> skl_bw_calc_min_cdclk;
> + dev_priv->display.modeset_calc_cdclk =
> bxt_modeset_calc_cdclk;
> + dev_priv->display.calc_voltage_level =
> tgl_calc_voltage_level;
> + dev_priv->cdclk.table = rkl_cdclk_table;
> + } else if (INTEL_GEN(dev_priv) >= 12) {
>   dev_priv->display.set_cdclk = bxt_set_cdclk;
>   dev_priv->display.bw_calc_min_cdclk =
> skl_bw_calc_min_cdclk;
>   dev_priv->display.modeset_calc_cdclk =
> bxt_modeset_calc_cdclk;
> --
> 2.24.1

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[Intel-gfx] i915 Update : DG1 DMC

[Srivatsa, Anusha]

Hi Kyle, Ben,

Please add the i915 updates to linux-firmware from branch dg1_dmc_v2_02

The following changes since commit 58d41d0facca2478d3e45f6321224361519aee96:

  ice: Add comms package file for Intel E800 series driver (2020-10-05 08:09:03 
-0400)

are available in the Git repository at: dg1_dmc_v2_02

  git://anongit.freedesktop.org/drm/drm-firmware dg1_dmc_v2_02

for you to fetch changes up to a140ef3eb3746aba2c897db16e02ffb5ffa9e7a2:

  i915: Add DG1 DMC v2.02 (2020-10-08 12:13:33 -0700)


Anusha Srivatsa (1):
  i915: Add DG1 DMC v2.02

WHENCE   |   2 ++
i915/dg1_dmc_ver2_02.bin | Bin 0 -> 16624 bytes
2 files changed, 2 insertions(+)
create mode 100644 i915/dg1_dmc_ver2_02.bin

Thanks,
Anusha
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[Intel-gfx] PR - DG1 DMC v2.02

[Srivatsa, Anusha]

Sending PR for DG1 DMC for our CI to install DG1 DMC.

The following changes since commit 58d41d0facca2478d3e45f6321224361519aee96:

  ice: Add comms package file for Intel E800 series driver (2020-10-05 08:09:03 
-0400)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-firmware dg1_dmc_v2_02

for you to fetch changes up to a140ef3eb3746aba2c897db16e02ffb5ffa9e7a2:

  i915: Add DG1 DMC v2.02 (2020-10-08 12:13:33 -0700)


Anusha Srivatsa (1):
  i915: Add DG1 DMC v2.02

WHENCE   |   2 ++
i915/dg1_dmc_ver2_02.bin | Bin 0 -> 16624 bytes
2 files changed, 2 insertions(+)
create mode 100644 i915/dg1_dmc_ver2_02.bin


Thanks,
Anusha
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Re: [Intel-gfx] [PATCH 04/14] drm/i915: Add SKL GT1.5 PCI IDs

[Srivatsa, Anusha]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Thursday, September 24, 2020 3:46 AM
> To: Srivatsa, Anusha 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 04/14] drm/i915: Add SKL GT1.5 PCI IDs
> 
> On Thu, Sep 24, 2020 at 12:37:47AM +, Srivatsa, Anusha wrote:
> >
> >
> > > -Original Message-
> > > From: Intel-gfx  On Behalf
> > > Of Ville Syrjala
> > > Sent: Thursday, July 16, 2020 10:21 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Subject: [Intel-gfx] [PATCH 04/14] drm/i915: Add SKL GT1.5 PCI IDs
> > >
> > > From: Alexei Podtelezhnikov 
> > >
> > > Add three new devices 0x1913, 0x1915, and 0x1917 also known as
> > > iSKLULTGT15, iSKLULXGT15, and iSKLDTGT15.
> > >
> > > Signed-off-by: Alexei Podtelezhnikov 
> > > [vsyrjala: Split separate changes into separate patchs,
> > >Sort the IDs]
> > The above comment appears in every patch. If this is v2 of the patches
> then it goes right after the commit message as:
> >
> >  V2: Split separate changes into separate patches, sort the IDs
> > (Ville)
> 
> No. I use the [vsyrjala: blah] notation to indicate I modified the original
> patch which was authored by someone else.
> 
> >
> > > Signed-off-by: Ville Syrjälä 
> > The code changes itself look good.

Ah. Ok.
Makes sense

Anusha 
> > Reviewed-by: Anusha Srivatsa 
> >
> > > ---
> > >  include/drm/i915_pciids.h | 9 ++---
> > >  1 file changed, 6 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > > index 9df3697f074d..c906088ccffe 100644
> > > --- a/include/drm/i915_pciids.h
> > > +++ b/include/drm/i915_pciids.h
> > > @@ -329,17 +329,20 @@
> > >   INTEL_VGA_DEVICE(0x22b3, info)
> > >
> > >  #define INTEL_SKL_ULT_GT1_IDS(info) \
> > > - INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
> > > + INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
> > > + INTEL_VGA_DEVICE(0x1913, info)  /* ULT GT1.5 */
> > >
> > >  #define INTEL_SKL_ULX_GT1_IDS(info) \
> > > - INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
> > > + INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
> > > + INTEL_VGA_DEVICE(0x1915, info)  /* ULX GT1.5 */
> > >
> > >  #define INTEL_SKL_GT1_IDS(info)  \
> > >   INTEL_SKL_ULT_GT1_IDS(info), \
> > >   INTEL_SKL_ULX_GT1_IDS(info), \
> > >   INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
> > >   INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
> > > - INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
> > > + INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \
> > > + INTEL_VGA_DEVICE(0x1917, info)  /* DT  GT1.5 */
> > >
> > >  #define INTEL_SKL_ULT_GT2_IDS(info) \
> > >   INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
> > > --
> > > 2.26.2
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH 14/14] drm/i915: Sort EHL/JSL PCI IDs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 14/14] drm/i915: Sort EHL/JSL PCI IDs
> 
> From: Ville Syrjälä 
> 
> Sort the EHL/JSL PCI IDs numerically. Some order seems better than
> randomness.
> 
> Cc: Alexei Podtelezhnikov 
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Anusha Srivatsa 

> ---
>  include/drm/i915_pciids.h | 14 +++---
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 45da1b45c01e..880ffe8571e8 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -585,16 +585,16 @@
>  /* EHL/JSL */
>  #define INTEL_EHL_IDS(info) \
>   INTEL_VGA_DEVICE(0x4500, info), \
> - INTEL_VGA_DEVICE(0x4571, info), \
> - INTEL_VGA_DEVICE(0x4551, info), \
>   INTEL_VGA_DEVICE(0x4541, info), \
> - INTEL_VGA_DEVICE(0x4E71, info), \
> - INTEL_VGA_DEVICE(0x4557, info), \
> + INTEL_VGA_DEVICE(0x4551, info), \
>   INTEL_VGA_DEVICE(0x4555, info), \
> - INTEL_VGA_DEVICE(0x4E61, info), \
> - INTEL_VGA_DEVICE(0x4E57, info), \
> + INTEL_VGA_DEVICE(0x4557, info), \
> + INTEL_VGA_DEVICE(0x4571, info), \
> + INTEL_VGA_DEVICE(0x4E51, info), \
>   INTEL_VGA_DEVICE(0x4E55, info), \
> - INTEL_VGA_DEVICE(0x4E51, info)
> + INTEL_VGA_DEVICE(0x4E57, info), \
> + INTEL_VGA_DEVICE(0x4E61, info), \
> + INTEL_VGA_DEVICE(0x4E71, info)
> 
>  /* TGL */
>  #define INTEL_TGL_12_IDS(info) \
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 13/14] drm/i915: Sort ICL PCI IDs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 13/14] drm/i915: Sort ICL PCI IDs
> 
> From: Ville Syrjälä 
> 
> Sort the ICL PCI IDs numerically. Some order seems better than randomness.
> 
> Cc: Alexei Podtelezhnikov 
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Anusha Srivatsa 

> ---
>  include/drm/i915_pciids.h | 16 
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 33a72e6eadd8..45da1b45c01e 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -564,18 +564,18 @@
>  /* ICL */
>  #define INTEL_ICL_PORT_F_IDS(info) \
>   INTEL_VGA_DEVICE(0x8A50, info), \
> - INTEL_VGA_DEVICE(0x8A5C, info), \
> - INTEL_VGA_DEVICE(0x8A59, info), \
> - INTEL_VGA_DEVICE(0x8A58, info), \
>   INTEL_VGA_DEVICE(0x8A52, info), \
> + INTEL_VGA_DEVICE(0x8A53, info), \
> + INTEL_VGA_DEVICE(0x8A54, info), \
> + INTEL_VGA_DEVICE(0x8A56, info), \
> + INTEL_VGA_DEVICE(0x8A57, info), \
> + INTEL_VGA_DEVICE(0x8A58, info), \
> + INTEL_VGA_DEVICE(0x8A59, info), \
>   INTEL_VGA_DEVICE(0x8A5A, info), \
>   INTEL_VGA_DEVICE(0x8A5B, info), \
> - INTEL_VGA_DEVICE(0x8A57, info), \
> - INTEL_VGA_DEVICE(0x8A56, info), \
> - INTEL_VGA_DEVICE(0x8A71, info), \
> + INTEL_VGA_DEVICE(0x8A5C, info), \
>   INTEL_VGA_DEVICE(0x8A70, info), \
> - INTEL_VGA_DEVICE(0x8A53, info), \
> - INTEL_VGA_DEVICE(0x8A54, info)
> + INTEL_VGA_DEVICE(0x8A71, info)
> 
>  #define INTEL_ICL_11_IDS(info) \
>   INTEL_ICL_PORT_F_IDS(info), \
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 12/14] drm/i915: Sort CNL PCI IDs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 12/14] drm/i915: Sort CNL PCI IDs
> 
> From: Ville Syrjälä 
> 
> Sort the CNL PCI IDs numerically. Some order seems better than
> randomness.
> 
> Cc: Alexei Podtelezhnikov 
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Anusha Srivatsa 

> ---
>  include/drm/i915_pciids.h | 18 +-
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> c48c2b76aa7d..33a72e6eadd8 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -543,23 +543,23 @@
> 
>  /* CNL */
>  #define INTEL_CNL_PORT_F_IDS(info) \
> - INTEL_VGA_DEVICE(0x5A54, info), \
> - INTEL_VGA_DEVICE(0x5A5C, info), \
>   INTEL_VGA_DEVICE(0x5A44, info), \
> - INTEL_VGA_DEVICE(0x5A4C, info)
> + INTEL_VGA_DEVICE(0x5A4C, info), \
> + INTEL_VGA_DEVICE(0x5A54, info), \
> + INTEL_VGA_DEVICE(0x5A5C, info)
> 
>  #define INTEL_CNL_IDS(info) \
>   INTEL_CNL_PORT_F_IDS(info), \
> - INTEL_VGA_DEVICE(0x5A51, info), \
> - INTEL_VGA_DEVICE(0x5A59, info), \
> + INTEL_VGA_DEVICE(0x5A40, info), \
>   INTEL_VGA_DEVICE(0x5A41, info), \
> - INTEL_VGA_DEVICE(0x5A49, info), \
> - INTEL_VGA_DEVICE(0x5A52, info), \
> - INTEL_VGA_DEVICE(0x5A5A, info), \
>   INTEL_VGA_DEVICE(0x5A42, info), \
> + INTEL_VGA_DEVICE(0x5A49, info), \
>   INTEL_VGA_DEVICE(0x5A4A, info), \
>   INTEL_VGA_DEVICE(0x5A50, info), \
> - INTEL_VGA_DEVICE(0x5A40, info)
> + INTEL_VGA_DEVICE(0x5A51, info), \
> + INTEL_VGA_DEVICE(0x5A52, info), \
> + INTEL_VGA_DEVICE(0x5A59, info), \
> + INTEL_VGA_DEVICE(0x5A5A, info)
> 
>  /* ICL */
>  #define INTEL_ICL_PORT_F_IDS(info) \
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 11/14] drm/i915: Sort CFL PCI IDs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 11/14] drm/i915: Sort CFL PCI IDs
> 
> From: Ville Syrjälä 
> 
> Sort the CFL PCI IDs numerically. Some order seems better than
> randomness.
> 
> Cc: Alexei Podtelezhnikov 
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Anusha Srivatsa 

> ---
>  include/drm/i915_pciids.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 2d36cbce0ac0..c48c2b76aa7d 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -497,8 +497,8 @@
>   INTEL_VGA_DEVICE(0x3E9C, info)
> 
>  #define INTEL_CFL_H_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
> - INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */
> + INTEL_VGA_DEVICE(0x3E94, info),  /* Halo GT2 */ \
> + INTEL_VGA_DEVICE(0x3E9B, info) /* Halo GT2 */
> 
>  /* CFL U GT2 */
>  #define INTEL_CFL_U_GT2_IDS(info) \
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 10/14] drm/i915: Sort CML PCI IDs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 10/14] drm/i915: Sort CML PCI IDs
> 
> From: Ville Syrjälä 
> 
> Sort the CML PCI IDs numerically. Some order seems better than
> randomness.
> 
> Cc: Alexei Podtelezhnikov 
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Anusha Srivatsa 

> ---
>  include/drm/i915_pciids.h | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> db409171d9c3..2d36cbce0ac0 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -447,10 +447,10 @@
> 
>  /* CML GT1 */
>  #define INTEL_CML_GT1_IDS(info)  \
> - INTEL_VGA_DEVICE(0x9BA5, info), \
> - INTEL_VGA_DEVICE(0x9BA8, info), \
> + INTEL_VGA_DEVICE(0x9BA2, info), \
>   INTEL_VGA_DEVICE(0x9BA4, info), \
> - INTEL_VGA_DEVICE(0x9BA2, info)
> + INTEL_VGA_DEVICE(0x9BA5, info), \
> + INTEL_VGA_DEVICE(0x9BA8, info)
> 
>  #define INTEL_CML_U_GT1_IDS(info) \
>   INTEL_VGA_DEVICE(0x9B21, info), \
> @@ -459,11 +459,11 @@
> 
>  /* CML GT2 */
>  #define INTEL_CML_GT2_IDS(info)  \
> - INTEL_VGA_DEVICE(0x9BC5, info), \
> - INTEL_VGA_DEVICE(0x9BC8, info), \
> - INTEL_VGA_DEVICE(0x9BC4, info), \
>   INTEL_VGA_DEVICE(0x9BC2, info), \
> + INTEL_VGA_DEVICE(0x9BC4, info), \
> + INTEL_VGA_DEVICE(0x9BC5, info), \
>   INTEL_VGA_DEVICE(0x9BC6, info), \
> + INTEL_VGA_DEVICE(0x9BC8, info), \
>   INTEL_VGA_DEVICE(0x9BE6, info), \
>   INTEL_VGA_DEVICE(0x9BF6, info)
> 
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 09/14] drm/i915: Sort KBL PCI IDs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 09/14] drm/i915: Sort KBL PCI IDs
> 
> From: Ville Syrjälä 
> 
> Sort the KBL PCI IDs numerically. Some order seems better than
> randomness.
> 
> Cc: Alexei Podtelezhnikov 
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Anusha Srivatsa 

> ---
>  include/drm/i915_pciids.h | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 5185ac789038..db409171d9c3 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -406,8 +406,8 @@
>   INTEL_KBL_ULX_GT1_IDS(info), \
>   INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
>   INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
> + INTEL_VGA_DEVICE(0x590A, info), /* SRV GT1 */ \
> + INTEL_VGA_DEVICE(0x590B, info) /* Halo GT1 */
> 
>  #define INTEL_KBL_ULT_GT2_IDS(info) \
>   INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ @@ -419,10
> +419,10 @@
>  #define INTEL_KBL_GT2_IDS(info)  \
>   INTEL_KBL_ULT_GT2_IDS(info), \
>   INTEL_KBL_ULX_GT2_IDS(info), \
> - INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
>   INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
> - INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
> + INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
>   INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
> + INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
>   INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
> 
>  #define INTEL_KBL_ULT_GT3_IDS(info) \
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 08/14] drm/i915: Sort SKL PCI IDs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 08/14] drm/i915: Sort SKL PCI IDs
> 
> From: Ville Syrjälä 
> 
> Sort the SKL PCI IDs numerically. Some order seems better than
> randomness.

There are 2 patches - patch 2 and 3 in the series that are reclassifying some 
PCI IDs  and there is patch 4 that adds a missing ID. All of those with this 
patch can be combined to a single patch OR patch 2, 3 and 4 can be squashed as 
one solitary patch.

Anusha 
> Cc: Alexei Podtelezhnikov 
> Signed-off-by: Ville Syrjälä 
> ---
>  include/drm/i915_pciids.h | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 4870c3c9f9b2..5185ac789038 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -340,8 +340,8 @@
>   INTEL_SKL_ULT_GT1_IDS(info), \
>   INTEL_SKL_ULX_GT1_IDS(info), \
>   INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
> - INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
>   INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \
> + INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
>   INTEL_VGA_DEVICE(0x1917, info)  /* DT  GT1.5 */
> 
>  #define INTEL_SKL_ULT_GT2_IDS(info) \
> @@ -355,8 +355,8 @@
>   INTEL_SKL_ULT_GT2_IDS(info), \
>   INTEL_SKL_ULX_GT2_IDS(info), \
>   INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
> - INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
>   INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
> + INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
>   INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */
> 
>  #define INTEL_SKL_ULT_GT3_IDS(info) \
> @@ -372,9 +372,9 @@
> 
>  #define INTEL_SKL_GT4_IDS(info) \
>   INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
> + INTEL_VGA_DEVICE(0x193A, info), /* SRV GT4e */ \
>   INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4e */ \
> - INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4e */ \
> - INTEL_VGA_DEVICE(0x193A, info)  /* SRV GT4e */
> + INTEL_VGA_DEVICE(0x193D, info) /* WKS GT4e */
> 
>  #define INTEL_SKL_IDS(info)   \
>   INTEL_SKL_GT1_IDS(info), \
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 07/14] drm/i915: Sort HSW PCI IDs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 07/14] drm/i915: Sort HSW PCI IDs
> 
> From: Ville Syrjälä 
> 
> Sort the HSW PCI IDs numerically. Some order seems better than
> randomness.

I think the sorting, OCD-ness with hex and reclassifying can be combined in one 
patch.

Anusha 
> Cc: Alexei Podtelezhnikov 
> Signed-off-by: Ville Syrjälä 
> ---
>  include/drm/i915_pciids.h | 34 +-
>  1 file changed, 17 insertions(+), 17 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 026db4d496e9..4870c3c9f9b2 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -170,9 +170,9 @@
> 
>  #define INTEL_HSW_ULT_GT1_IDS(info) \
>   INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
>   INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
> - INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0A06, info)  /* ULT GT1 mobile */
> + INTEL_VGA_DEVICE(0x0A0B, info)  /* ULT GT1 reserved */
> 
>  #define INTEL_HSW_ULX_GT1_IDS(info) \
>   INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */ @@ -181,26
> +181,26 @@
>   INTEL_HSW_ULT_GT1_IDS(info), \
>   INTEL_HSW_ULX_GT1_IDS(info), \
>   INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
>   INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \
>   INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
>   INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
>   INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
>   INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
>   INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
>   INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
>   INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */\
>   INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
>   INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0D06, info)  /* CRW GT1 mobile */
> + INTEL_VGA_DEVICE(0x0D0E, info)  /* CRW GT1 reserved */
> 
>  #define INTEL_HSW_ULT_GT2_IDS(info) \
>   INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */\
>   INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
> - INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0A16, info)  /* ULT GT2 mobile */
> + INTEL_VGA_DEVICE(0x0A1B, info)  /* ULT GT2 reserved */ \
> 
>  #define INTEL_HSW_ULX_GT2_IDS(info) \
>   INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \ @@ -
> 209,45 +209,45 @@
>   INTEL_HSW_ULT_GT2_IDS(info), \
>   INTEL_HSW_ULX_GT2_IDS(info), \
>   INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
>   INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \
>   INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
>   INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
>   INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
>   INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
>   INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
>   INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
>   INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
>   INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
>   INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0D16, info)  /* CRW GT2 mobile */
> + INTEL_VGA_DEVICE(0x0D1E, info)  /* CRW GT2 reserved */
> 
>  #define INTEL_HSW_ULT_GT3_IDS(info) \
>   INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
> + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
>   INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
>   INTEL_VGA_D

Re: [Intel-gfx] [PATCH 06/14] drm/i915: Ocd the HSW PCI ID hex numbers

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 06/14] drm/i915: Ocd the HSW PCI ID hex
> numbers
> 
> From: Ville Syrjälä 
> 
> Most of the HSW PCI IDs are upper case hex numbers, but a few are lower
> case. Make it consistent so these don't stick out like a sore thumb.
> 
> Cc: Alexei Podtelezhnikov 
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Anusha Srivatsa 

> ---
>  include/drm/i915_pciids.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 3792ab5f20ff..026db4d496e9 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -181,7 +181,7 @@
>   INTEL_HSW_ULT_GT1_IDS(info), \
>   INTEL_HSW_ULX_GT1_IDS(info), \
>   INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
> + INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \
>   INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
>   INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
>   INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ @@ -
> 209,7 +209,7 @@
>   INTEL_HSW_ULT_GT2_IDS(info), \
>   INTEL_HSW_ULX_GT2_IDS(info), \
>   INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
> + INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \
>   INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
>   INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
>   INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ @@ -
> 234,7 +234,7 @@  #define INTEL_HSW_GT3_IDS(info) \
>   INTEL_HSW_ULT_GT3_IDS(info), \
>   INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
> + INTEL_VGA_DEVICE(0x042A, info), /* GT3 server */ \
>   INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
>   INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
>   INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 05/14] drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 05/14] drm/i915: Try to fix the SKL GT3/4 vs.
> GT3e/4e comments
> 
> From: Ville Syrjälä 
> 
> Bunch of the SKL SKUs currently documented as GT3/4 seem to actually be
> GT3e/4e. Fix up the comments.
> 
> Cc: Alexei Podtelezhnikov 
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Anusha Srivatsa 

> ---
>  include/drm/i915_pciids.h | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> c906088ccffe..3792ab5f20ff 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -361,19 +361,19 @@
> 
>  #define INTEL_SKL_ULT_GT3_IDS(info) \
>   INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x1927, info)  /* ULT GT3 */
> + INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3e */ \
> + INTEL_VGA_DEVICE(0x1927, info)  /* ULT GT3e */
> 
>  #define INTEL_SKL_GT3_IDS(info) \
>   INTEL_SKL_ULT_GT3_IDS(info), \
>   INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \
> - INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
> - INTEL_VGA_DEVICE(0x192D, info)  /* SRV GT3 */
> + INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3e */ \
> + INTEL_VGA_DEVICE(0x192D, info)  /* SRV GT3e */
> 
>  #define INTEL_SKL_GT4_IDS(info) \
>   INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
> - INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
> - INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
> + INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4e */ \
> + INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4e */ \
>   INTEL_VGA_DEVICE(0x193A, info)  /* SRV GT4e */
> 
>  #define INTEL_SKL_IDS(info)   \
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 04/14] drm/i915: Add SKL GT1.5 PCI IDs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 04/14] drm/i915: Add SKL GT1.5 PCI IDs
> 
> From: Alexei Podtelezhnikov 
> 
> Add three new devices 0x1913, 0x1915, and 0x1917 also known as
> iSKLULTGT15, iSKLULXGT15, and iSKLDTGT15.
> 
> Signed-off-by: Alexei Podtelezhnikov 
> [vsyrjala: Split separate changes into separate patchs,
>Sort the IDs]
The above comment appears in every patch. If this is v2 of the patches then it 
goes right after the commit message as:

 V2: Split separate changes into separate patches, sort the IDs (Ville)
 
> Signed-off-by: Ville Syrjälä 
The code changes itself look good.

Reviewed-by: Anusha Srivatsa 

> ---
>  include/drm/i915_pciids.h | 9 ++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 9df3697f074d..c906088ccffe 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -329,17 +329,20 @@
>   INTEL_VGA_DEVICE(0x22b3, info)
> 
>  #define INTEL_SKL_ULT_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
> + INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
> + INTEL_VGA_DEVICE(0x1913, info)  /* ULT GT1.5 */
> 
>  #define INTEL_SKL_ULX_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
> + INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
> + INTEL_VGA_DEVICE(0x1915, info)  /* ULX GT1.5 */
> 
>  #define INTEL_SKL_GT1_IDS(info)  \
>   INTEL_SKL_ULT_GT1_IDS(info), \
>   INTEL_SKL_ULX_GT1_IDS(info), \
>   INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
>   INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
> + INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \
> + INTEL_VGA_DEVICE(0x1917, info)  /* DT  GT1.5 */
> 
>  #define INTEL_SKL_ULT_GT2_IDS(info) \
>   INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 03/14] drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 03/14] drm/i915: Reclassify SKL 0x1923 and
> 0x1927 as ULT
> 
> From: Alexei Podtelezhnikov 
> 
> Reclassify 0x1923, 0x1927 according to specifications. Of note, the second to
> last digit seems to correspond to GT#.

IMO we don’t need to specify the above.

> Signed-off-by: Alexei Podtelezhnikov 
> [vsyrjala: Split separate changes into separate patches,
>Sort the IDs]
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Anusha Srivatsa 
> ---
>  include/drm/i915_pciids.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> d4c054e3b95f..9df3697f074d 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -357,12 +357,12 @@
>   INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */
> 
>  #define INTEL_SKL_ULT_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */
> + INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x1927, info)  /* ULT GT3 */
> 
>  #define INTEL_SKL_GT3_IDS(info) \
>   INTEL_SKL_ULT_GT3_IDS(info), \
> - INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
>   INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \
>   INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
>   INTEL_VGA_DEVICE(0x192D, info)  /* SRV GT3 */
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 01/14] drm/i915: Update Haswell PCI IDs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 01/14] drm/i915: Update Haswell PCI IDs
> 
> From: Alexei Podtelezhnikov 
> 
> Reclassify 0x0426 as GT3 (GT2+) according to specifications and the second
> least significant digit.
> 
> Signed-off-by: Alexei Podtelezhnikov 
> [vsyrjala: s/GT2/GT3/ in the comment]
> Signed-off-by: Ville Syrjälä 
Reviewed-by: Anusha Srivatsa 

> ---
>  include/drm/i915_pciids.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 8e7ae30ebcbb..51831c6f603c 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -221,7 +221,6 @@
>   INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
>   INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
>   INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
>   INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
>   INTEL_VGA_DEVICE(0x0D16, info)  /* CRW GT2 mobile */
> 
> @@ -246,6 +245,7 @@
>   INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
>   INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
>   INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
> + INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \
>   INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
>   INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
> 
> --
> 2.26.2
> 
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Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pll: Centralize PLL_ENABLE register lookup (rev4)

[Srivatsa, Anusha]

> -Original Message-
> From: Jani Nikula 
> Sent: Wednesday, September 16, 2020 6:51 AM
> To: Srivatsa, Anusha 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pll:
> Centralize PLL_ENABLE register lookup (rev4)
> 
> On Fri, 11 Sep 2020, Patchwork  wrote:
> > == Series Details ==
> >
> > Series: drm/i915/pll: Centralize PLL_ENABLE register lookup (rev4)
> > URL   : https://patchwork.freedesktop.org/series/81150/
> > State : warning
> >
> > == Summary ==
> >
> > $ dim checkpatch origin/drm-tip
> > dac234339c17 drm/i915/pll: Centralize PLL_ENABLE register lookup
> > -:38: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
> > #38: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:154:
> > +{
> > +
> >
> > -:39: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses
> around 'pll->info->id == DPLL_ID_EHL_DPLL4'
> > #39: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:155:
> > +   if (IS_ELKHARTLAKE(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
> >
> > -:44: CHECK:LINE_SPACING: Please don't use multiple blank lines
> > #44: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:160:
> > +
> > +
> >
> > -:45: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
> > #45: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:161:
> > +
> > +}
> 
> We have this in CI so people don't have to bother with mentioning this
> stuff. But I do expect people to look at them and fix them.

Yes jani. Will definitely keep this in mind.

Anusha
> BR,
> Jani.
> 
> 
> >
> > total: 0 errors, 0 warnings, 4 checks, 66 lines checked
> >
> >
> > ___
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
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[Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup

[Anusha Srivatsa]

We currenty check for platform at multiple parts in the driver
to grab the correct PLL. Let us begin to centralize it through a
helper function.

v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg() (Ville)

v3: Clean up combo_pll_disable() (Rodrigo)

v4: s/dev_priv/i915 (Jani)
Move static and return type to the same line( Ville, Jani)

Suggested-by: Matt Roper 
Cc: Ville Syrjälä 
Cc: Matt Roper 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 35 ++-
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c9013f8f766f..e08684e34078 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -147,6 +147,18 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
pll->info->name, onoff(state), onoff(cur_state));
 }
 
+static i915_reg_t
+intel_combo_pll_enable_reg(struct drm_i915_private *i915,
+  struct intel_shared_dpll *pll)
+{
+
+   if (IS_ELKHARTLAKE(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
+   return MG_PLL_ENABLE(0);
+
+   return CNL_DPLL_ENABLE(pll->info->id);
+
+
+}
 /**
  * intel_prepare_shared_dpll - call a dpll's prepare hook
  * @crtc_state: CRTC, and its state, which has a shared dpll
@@ -3842,12 +3854,7 @@ static bool combo_pll_get_hw_state(struct 
drm_i915_private *dev_priv,
   struct intel_shared_dpll *pll,
   struct intel_dpll_hw_state *hw_state)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
-
-   if (IS_ELKHARTLAKE(dev_priv) &&
-   pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
-   }
+   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
 }
@@ -4045,11 +4052,10 @@ static void icl_pll_enable(struct drm_i915_private 
*dev_priv,
 static void combo_pll_enable(struct drm_i915_private *dev_priv,
 struct intel_shared_dpll *pll)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
if (IS_ELKHARTLAKE(dev_priv) &&
pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
 
/*
 * We need to disable DC states when this DPLL is enabled.
@@ -4157,19 +4163,14 @@ static void icl_pll_disable(struct drm_i915_private 
*dev_priv,
 static void combo_pll_disable(struct drm_i915_private *dev_priv,
  struct intel_shared_dpll *pll)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
-   if (IS_ELKHARTLAKE(dev_priv) &&
-   pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
-   icl_pll_disable(dev_priv, pll, enable_reg);
+   icl_pll_disable(dev_priv, pll, enable_reg);
 
+   if (IS_ELKHARTLAKE(dev_priv) &&
+   pll->info->id == DPLL_ID_EHL_DPLL4)
intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
pll->wakeref);
-   return;
-   }
-
-   icl_pll_disable(dev_priv, pll, enable_reg);
 }
 
 static void tbt_pll_disable(struct drm_i915_private *dev_priv,
-- 
2.25.0

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[Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup

[Anusha Srivatsa]

We currenty check for platform at multiple parts in the driver
to grab the correct PLL. Let us begin to centralize it through a
helper function.

v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg() (Ville)

v3: Clean up combo_pll_disable() (Rodrigo)

v4: s/dev_priv/i915 (Jani)
Move static and return type to the same line( Ville, Jxani)

Suggested-by: Matt Roper 
Cc: Ville Syrjälä 
Cc: Matt Roper 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 35 ++-
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c9013f8f766f..e08684e34078 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -147,6 +147,18 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
pll->info->name, onoff(state), onoff(cur_state));
 }
 
+static i915_reg_t
+intel_combo_pll_enable_reg(struct drm_i915_private *i915,
+  struct intel_shared_dpll *pll)
+{
+
+   if (IS_ELKHARTLAKE(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
+   return MG_PLL_ENABLE(0);
+
+   return CNL_DPLL_ENABLE(pll->info->id);
+
+
+}
 /**
  * intel_prepare_shared_dpll - call a dpll's prepare hook
  * @crtc_state: CRTC, and its state, which has a shared dpll
@@ -3842,12 +3854,7 @@ static bool combo_pll_get_hw_state(struct 
drm_i915_private *dev_priv,
   struct intel_shared_dpll *pll,
   struct intel_dpll_hw_state *hw_state)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
-
-   if (IS_ELKHARTLAKE(dev_priv) &&
-   pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
-   }
+   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
 }
@@ -4045,11 +4052,10 @@ static void icl_pll_enable(struct drm_i915_private 
*dev_priv,
 static void combo_pll_enable(struct drm_i915_private *dev_priv,
 struct intel_shared_dpll *pll)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
if (IS_ELKHARTLAKE(dev_priv) &&
pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
 
/*
 * We need to disable DC states when this DPLL is enabled.
@@ -4157,19 +4163,14 @@ static void icl_pll_disable(struct drm_i915_private 
*dev_priv,
 static void combo_pll_disable(struct drm_i915_private *dev_priv,
  struct intel_shared_dpll *pll)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
-   if (IS_ELKHARTLAKE(dev_priv) &&
-   pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
-   icl_pll_disable(dev_priv, pll, enable_reg);
+   icl_pll_disable(dev_priv, pll, enable_reg);
 
+   if (IS_ELKHARTLAKE(dev_priv) &&
+   pll->info->id == DPLL_ID_EHL_DPLL4)
intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
pll->wakeref);
-   return;
-   }
-
-   icl_pll_disable(dev_priv, pll, enable_reg);
 }
 
 static void tbt_pll_disable(struct drm_i915_private *dev_priv,
-- 
2.25.0

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Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup

[Srivatsa, Anusha]

> -Original Message-
> From: Jani Nikula 
> Sent: Thursday, September 10, 2020 6:31 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register
> lookup
> 
> On Tue, 08 Sep 2020, Anusha Srivatsa  wrote:
> > We currenty check for platform at multiple parts in the driver to grab
> > the correct PLL. Let us begin to centralize it through a helper
> > function.
> >
> > v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg() (Ville)
> >
> > v3: Clean up combo_pll_disable() (Rodrigo)
> >
> > Suggested-by: Matt Roper 
> > Cc: Ville Syrjälä 
> > Cc: Matt Roper 
> > Signed-off-by: Anusha Srivatsa 
> > Reviewed-by: Rodrigo Vivi 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29
> > +++
> >  1 file changed, 17 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index c9013f8f766f..441b6f52e808 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -147,6 +147,18 @@ void assert_shared_dpll(struct drm_i915_private
> *dev_priv,
> > pll->info->name, onoff(state), onoff(cur_state));  }
> >
> > +static
> > +i915_reg_t intel_combo_pll_enable_reg(struct drm_i915_private
> > +*dev_priv,
> 
> Please keep the static keyword and the return type on the same line with
> each other.
> 
> And since you're touching this, please rename dev_priv to i915 in all new
> code adding it.

Sure. Thanks for the feedback Jani.

Anusha
> BR,
> Jani.
> 
> 
> > +   struct intel_shared_dpll *pll) {
> > +
> > +   if (IS_ELKHARTLAKE(dev_priv) && (pll->info->id ==
> DPLL_ID_EHL_DPLL4))
> > +   return MG_PLL_ENABLE(0);
> > +
> > +   return CNL_DPLL_ENABLE(pll->info->id);
> > +
> > +
> > +}
> >  /**
> >   * intel_prepare_shared_dpll - call a dpll's prepare hook
> >   * @crtc_state: CRTC, and its state, which has a shared dpll @@
> > -3842,12 +3854,7 @@ static bool combo_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
> >struct intel_shared_dpll *pll,
> >struct intel_dpll_hw_state *hw_state)  {
> > -   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > -
> > -   if (IS_ELKHARTLAKE(dev_priv) &&
> > -   pll->info->id == DPLL_ID_EHL_DPLL4) {
> > -   enable_reg = MG_PLL_ENABLE(0);
> > -   }
> > +   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
> >
> > return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);  }
> > @@ -4045,11 +4052,10 @@ static void icl_pll_enable(struct
> > drm_i915_private *dev_priv,  static void combo_pll_enable(struct
> drm_i915_private *dev_priv,
> >  struct intel_shared_dpll *pll)  {
> > -   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > +   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
> >
> > if (IS_ELKHARTLAKE(dev_priv) &&
> > pll->info->id == DPLL_ID_EHL_DPLL4) {
> > -   enable_reg = MG_PLL_ENABLE(0);
> >
> > /*
> >  * We need to disable DC states when this DPLL is enabled.
> > @@ -4157,19 +4163,18 @@ static void icl_pll_disable(struct
> > drm_i915_private *dev_priv,  static void combo_pll_disable(struct
> drm_i915_private *dev_priv,
> >   struct intel_shared_dpll *pll)  {
> > -   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > +   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
> > +
> > +   icl_pll_disable(dev_priv, pll, enable_reg);
> >
> > if (IS_ELKHARTLAKE(dev_priv) &&
> > pll->info->id == DPLL_ID_EHL_DPLL4) {
> > -   enable_reg = MG_PLL_ENABLE(0);
> > -   icl_pll_disable(dev_priv, pll, enable_reg);
> >
> > intel_display_power_put(dev_priv,
> POWER_DOMAIN_DPLL_DC_OFF,
> > pll->wakeref);
> > return;
> > }
> >
> > -   icl_pll_disable(dev_priv, pll, enable_reg);
> >  }
> >
> >  static void tbt_pll_disable(struct drm_i915_private *dev_priv,
> 
> --
> Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup

[Anusha Srivatsa]

We currenty check for platform at multiple parts in the driver
to grab the correct PLL. Let us begin to centralize it through a
helper function.

v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg() (Ville)

v3: Clean up combo_pll_disable() (Rodrigo)

Suggested-by: Matt Roper 
Cc: Ville Syrjälä 
Cc: Matt Roper 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c9013f8f766f..441b6f52e808 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -147,6 +147,18 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
pll->info->name, onoff(state), onoff(cur_state));
 }
 
+static
+i915_reg_t intel_combo_pll_enable_reg(struct drm_i915_private *dev_priv,
+   struct intel_shared_dpll *pll)
+{
+
+   if (IS_ELKHARTLAKE(dev_priv) && (pll->info->id == DPLL_ID_EHL_DPLL4))
+   return MG_PLL_ENABLE(0);
+
+   return CNL_DPLL_ENABLE(pll->info->id);
+
+
+}
 /**
  * intel_prepare_shared_dpll - call a dpll's prepare hook
  * @crtc_state: CRTC, and its state, which has a shared dpll
@@ -3842,12 +3854,7 @@ static bool combo_pll_get_hw_state(struct 
drm_i915_private *dev_priv,
   struct intel_shared_dpll *pll,
   struct intel_dpll_hw_state *hw_state)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
-
-   if (IS_ELKHARTLAKE(dev_priv) &&
-   pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
-   }
+   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
 }
@@ -4045,11 +4052,10 @@ static void icl_pll_enable(struct drm_i915_private 
*dev_priv,
 static void combo_pll_enable(struct drm_i915_private *dev_priv,
 struct intel_shared_dpll *pll)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
if (IS_ELKHARTLAKE(dev_priv) &&
pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
 
/*
 * We need to disable DC states when this DPLL is enabled.
@@ -4157,19 +4163,18 @@ static void icl_pll_disable(struct drm_i915_private 
*dev_priv,
 static void combo_pll_disable(struct drm_i915_private *dev_priv,
  struct intel_shared_dpll *pll)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
+
+   icl_pll_disable(dev_priv, pll, enable_reg);
 
if (IS_ELKHARTLAKE(dev_priv) &&
pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
-   icl_pll_disable(dev_priv, pll, enable_reg);
 
intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
pll->wakeref);
return;
}
 
-   icl_pll_disable(dev_priv, pll, enable_reg);
 }
 
 static void tbt_pll_disable(struct drm_i915_private *dev_priv,
-- 
2.25.0

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Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup

[Srivatsa, Anusha]

> -Original Message-
> From: Vivi, Rodrigo 
> Sent: Wednesday, September 2, 2020 2:32 PM
> To: Srivatsa, Anusha 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register
> lookup
> 
> 
> 
> > On Sep 2, 2020, at 12:30 PM, Srivatsa, Anusha
>  wrote:
> >
> >
> >
> >> -Original Message-
> >> From: Rodrigo Vivi 
> >> Sent: Tuesday, September 1, 2020 12:30 PM
> >> To: Srivatsa, Anusha 
> >> Cc: intel-gfx@lists.freedesktop.org
> >> Subject: Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE
> >> register lookup
> >>
> >> On Tue, Sep 01, 2020 at 11:27:58AM -0700, Anusha Srivatsa wrote:
> >>> We currenty check for platform at multiple parts in the driver to
> >>> grab the correct PLL. Let us begin to centralize it through a helper
> >>> function.
> >>>
> >>> v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg()
> >>> (Ville)
> >>>
> >>> Suggested-by: Matt Roper 
> >>> Cc: Ville Syrjälä 
> >>> Cc: Matt Roper 
> >>> Signed-off-by: Anusha Srivatsa 
> >>> ---
> >>> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 25
> >>> +++
> >>> 1 file changed, 15 insertions(+), 10 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >>> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >>> index c9013f8f766f..7440836c5e44 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >>> @@ -147,6 +147,18 @@ void assert_shared_dpll(struct
> drm_i915_private
> >> *dev_priv,
> >>>   pll->info->name, onoff(state), onoff(cur_state));  }
> >>>
> >>> +static
> >>> +i915_reg_t intel_combo_pll_enable_reg(struct drm_i915_private
> >> *dev_priv,
> >>> + struct intel_shared_dpll *pll) {
> >>> +
> >>> + if (IS_ELKHARTLAKE(dev_priv) && (pll->info->id ==
> >> DPLL_ID_EHL_DPLL4))
> >>> + return MG_PLL_ENABLE(0);
> >>> +
> >>> + return CNL_DPLL_ENABLE(pll->info->id);
> >>> +
> >>> +
> >>> +}
> >>> /**
> >>>  * intel_prepare_shared_dpll - call a dpll's prepare hook
> >>>  * @crtc_state: CRTC, and its state, which has a shared dpll @@
> >>> -3842,12 +3854,7 @@ static bool combo_pll_get_hw_state(struct
> >> drm_i915_private *dev_priv,
> >>>  struct intel_shared_dpll *pll,
> >>>  struct intel_dpll_hw_state *hw_state)  {
> >>> - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> >>> -
> >>> - if (IS_ELKHARTLAKE(dev_priv) &&
> >>> - pll->info->id == DPLL_ID_EHL_DPLL4) {
> >>> - enable_reg = MG_PLL_ENABLE(0);
> >>> - }
> >>> + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
> >>>
> >>>   return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
> >>> } @@ -4045,11 +4052,10 @@ static void icl_pll_enable(struct
> >>> drm_i915_private *dev_priv,  static void combo_pll_enable(struct
> >> drm_i915_private *dev_priv,
> >>>struct intel_shared_dpll *pll)  {
> >>> - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> >>> + i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
> >>>
> >>>   if (IS_ELKHARTLAKE(dev_priv) &&
> >>>   pll->info->id == DPLL_ID_EHL_DPLL4) {
> >>
> >> there's probably something else that we can do now with the
> >> power_{put,get} to get rid of the, now, doubled if checks...
> >
> > Don't follow you here Rodrigo.
> 
> me neither ;)
> I'm just brainstorming... thinking out lout.
> 
> > Are you suggesting using power_{put/get} to somehow get rid of doubled
> if?
> 
> after this patch, on this path we will do this if check twice.
> not a big deal, but we can probably do something better.
> 
> However I don't understand why we had this get/put here at first place.
> Only for this platform and only for this pll4. So, what I am wondering is that
> we have something better to do with the power_well infr

Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup

[Srivatsa, Anusha]

> -Original Message-
> From: Rodrigo Vivi 
> Sent: Tuesday, September 1, 2020 12:30 PM
> To: Srivatsa, Anusha 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register
> lookup
> 
> On Tue, Sep 01, 2020 at 11:27:58AM -0700, Anusha Srivatsa wrote:
> > We currenty check for platform at multiple parts in the driver to grab
> > the correct PLL. Let us begin to centralize it through a helper
> > function.
> >
> > v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg() (Ville)
> >
> > Suggested-by: Matt Roper 
> > Cc: Ville Syrjälä 
> > Cc: Matt Roper 
> > Signed-off-by: Anusha Srivatsa 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 25
> > +++
> >  1 file changed, 15 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index c9013f8f766f..7440836c5e44 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -147,6 +147,18 @@ void assert_shared_dpll(struct drm_i915_private
> *dev_priv,
> > pll->info->name, onoff(state), onoff(cur_state));  }
> >
> > +static
> > +i915_reg_t intel_combo_pll_enable_reg(struct drm_i915_private
> *dev_priv,
> > +   struct intel_shared_dpll *pll) {
> > +
> > +   if (IS_ELKHARTLAKE(dev_priv) && (pll->info->id ==
> DPLL_ID_EHL_DPLL4))
> > +   return MG_PLL_ENABLE(0);
> > +
> > +   return CNL_DPLL_ENABLE(pll->info->id);
> > +
> > +
> > +}
> >  /**
> >   * intel_prepare_shared_dpll - call a dpll's prepare hook
> >   * @crtc_state: CRTC, and its state, which has a shared dpll @@
> > -3842,12 +3854,7 @@ static bool combo_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
> >struct intel_shared_dpll *pll,
> >struct intel_dpll_hw_state *hw_state)  {
> > -   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > -
> > -   if (IS_ELKHARTLAKE(dev_priv) &&
> > -   pll->info->id == DPLL_ID_EHL_DPLL4) {
> > -   enable_reg = MG_PLL_ENABLE(0);
> > -   }
> > +   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
> >
> > return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);  }
> > @@ -4045,11 +4052,10 @@ static void icl_pll_enable(struct
> > drm_i915_private *dev_priv,  static void combo_pll_enable(struct
> drm_i915_private *dev_priv,
> >  struct intel_shared_dpll *pll)  {
> > -   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > +   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
> >
> > if (IS_ELKHARTLAKE(dev_priv) &&
> > pll->info->id == DPLL_ID_EHL_DPLL4) {
> 
> there's probably something else that we can do now with the
> power_{put,get} to get rid of the, now, doubled if checks...

Don't follow you here Rodrigo. Are you suggesting using power_{put/get} to 
somehow get rid of doubled if?

> > -   enable_reg = MG_PLL_ENABLE(0);
> >
> > /*
> >  * We need to disable DC states when this DPLL is enabled.
> > @@ -4157,11 +4163,10 @@ static void icl_pll_disable(struct
> > drm_i915_private *dev_priv,  static void combo_pll_disable(struct
> drm_i915_private *dev_priv,
> >   struct intel_shared_dpll *pll)  {
> > -   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > +   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
> >
> > if (IS_ELKHARTLAKE(dev_priv) &&
> > pll->info->id == DPLL_ID_EHL_DPLL4) {
> > -   enable_reg = MG_PLL_ENABLE(0);
> > icl_pll_disable(dev_priv, pll, enable_reg);
> 
> but here, at least, let's clean this function now...
> move this call above and out of the if and delete the one below and keep
> just the power_put inside the if...

Good change. Thanks!
Will change that.

Anusha
 
> >
> > intel_display_power_put(dev_priv,
> POWER_DOMAIN_DPLL_DC_OFF,
> > --
> > 2.25.0
> >
> > ___
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> > Intel-gfx@lists.freedesktop.org
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[Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup

[Anusha Srivatsa]

We currenty check for platform at multiple parts in the driver
to grab the correct PLL. Let us begin to centralize it through a
helper function.

v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg() (Ville)

Suggested-by: Matt Roper 
Cc: Ville Syrjälä 
Cc: Matt Roper 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 25 +++
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c9013f8f766f..7440836c5e44 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -147,6 +147,18 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
pll->info->name, onoff(state), onoff(cur_state));
 }
 
+static
+i915_reg_t intel_combo_pll_enable_reg(struct drm_i915_private *dev_priv,
+   struct intel_shared_dpll *pll)
+{
+
+   if (IS_ELKHARTLAKE(dev_priv) && (pll->info->id == DPLL_ID_EHL_DPLL4))
+   return MG_PLL_ENABLE(0);
+
+   return CNL_DPLL_ENABLE(pll->info->id);
+
+
+}
 /**
  * intel_prepare_shared_dpll - call a dpll's prepare hook
  * @crtc_state: CRTC, and its state, which has a shared dpll
@@ -3842,12 +3854,7 @@ static bool combo_pll_get_hw_state(struct 
drm_i915_private *dev_priv,
   struct intel_shared_dpll *pll,
   struct intel_dpll_hw_state *hw_state)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
-
-   if (IS_ELKHARTLAKE(dev_priv) &&
-   pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
-   }
+   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
 }
@@ -4045,11 +4052,10 @@ static void icl_pll_enable(struct drm_i915_private 
*dev_priv,
 static void combo_pll_enable(struct drm_i915_private *dev_priv,
 struct intel_shared_dpll *pll)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
if (IS_ELKHARTLAKE(dev_priv) &&
pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
 
/*
 * We need to disable DC states when this DPLL is enabled.
@@ -4157,11 +4163,10 @@ static void icl_pll_disable(struct drm_i915_private 
*dev_priv,
 static void combo_pll_disable(struct drm_i915_private *dev_priv,
  struct intel_shared_dpll *pll)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+   i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
if (IS_ELKHARTLAKE(dev_priv) &&
pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
icl_pll_disable(dev_priv, pll, enable_reg);
 
intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
-- 
2.25.0

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Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup

[Srivatsa, Anusha]

> -Original Message-
> From: Ville Syrjälä 
> Sent: Monday, August 31, 2020 6:42 AM
> To: Srivatsa, Anusha 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register
> lookup
> 
> On Fri, Aug 28, 2020 at 02:58:32PM -0700, Anusha Srivatsa wrote:
> > We currenty check for platform at multiple parts in the driver to grab
> > the correct PLL. Let us begin to centralize it through a helper
> > function.
> >
> > Suggested-by: Matt Roper 
> > Cc: Matt Roper 
> > Signed-off-by: Anusha Srivatsa 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 27
> > ---
> >  1 file changed, 17 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 81ab975fe4f0..388136618bb7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -147,6 +147,20 @@ void assert_shared_dpll(struct drm_i915_private
> *dev_priv,
> > pll->info->name, onoff(state), onoff(cur_state));  }
> >
> > +static
> > +i915_reg_t intel_get_pll_enable_reg(struct drm_i915_private *dev_priv,
> > +   struct intel_shared_dpll *pll)
> 
> combo_pll_enable_reg() ?
Actually want to avoid mentioning combo in the name. We might have platforms 
that do not have combo phys. We still want this function to be one place where 
platforms gets the PLL_ENABLE register.
 
> 
> > +{
> > +
> > +   if (IS_ELKHARTLAKE(dev_priv)) {
> > +   if (pll->info->id == DPLL_ID_EHL_DPLL4)
> > +   return MG_PLL_ENABLE(0);
> > +   }
> 
> Ugly nested if.
 Will change it.

Anusha 
> > +
> > +   return CNL_DPLL_ENABLE(pll->info->id);
> > +
> > +
> > +}
> >  /**
> >   * intel_prepare_shared_dpll - call a dpll's prepare hook
> >   * @crtc_state: CRTC, and its state, which has a shared dpll @@
> > -3842,12 +3856,7 @@ static bool combo_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
> >struct intel_shared_dpll *pll,
> >struct intel_dpll_hw_state *hw_state)  {
> > -   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > -
> > -   if (IS_ELKHARTLAKE(dev_priv) &&
> > -   pll->info->id == DPLL_ID_EHL_DPLL4) {
> > -   enable_reg = MG_PLL_ENABLE(0);
> > -   }
> > +   i915_reg_t enable_reg = intel_get_pll_enable_reg(dev_priv, pll);
> >
> > return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);  }
> > @@ -4045,11 +4054,10 @@ static void icl_pll_enable(struct
> > drm_i915_private *dev_priv,  static void combo_pll_enable(struct
> drm_i915_private *dev_priv,
> >  struct intel_shared_dpll *pll)  {
> > -   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > +   i915_reg_t enable_reg = intel_get_pll_enable_reg(dev_priv, pll);
> >
> > if (IS_ELKHARTLAKE(dev_priv) &&
> > pll->info->id == DPLL_ID_EHL_DPLL4) {
> > -   enable_reg = MG_PLL_ENABLE(0);
> >
> > /*
> >  * We need to disable DC states when this DPLL is enabled.
> > @@ -4157,11 +4165,10 @@ static void icl_pll_disable(struct
> > drm_i915_private *dev_priv,  static void combo_pll_disable(struct
> drm_i915_private *dev_priv,
> >   struct intel_shared_dpll *pll)  {
> > -   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> > +   i915_reg_t enable_reg = intel_get_pll_enable_reg(dev_priv, pll);
> >
> > if (IS_ELKHARTLAKE(dev_priv) &&
> > pll->info->id == DPLL_ID_EHL_DPLL4) {
> > -   enable_reg = MG_PLL_ENABLE(0);
> > icl_pll_disable(dev_priv, pll, enable_reg);
> >
> > intel_display_power_put(dev_priv,
> POWER_DOMAIN_DPLL_DC_OFF,
> > --
> > 2.25.0
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup

[Anusha Srivatsa]

We currenty check for platform at multiple parts in the driver
to grab the correct PLL. Let us begin to centralize it through a
helper function.

Suggested-by: Matt Roper 
Cc: Matt Roper 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 27 ---
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 81ab975fe4f0..388136618bb7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -147,6 +147,20 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
pll->info->name, onoff(state), onoff(cur_state));
 }
 
+static
+i915_reg_t intel_get_pll_enable_reg(struct drm_i915_private *dev_priv,
+   struct intel_shared_dpll *pll)
+{
+
+   if (IS_ELKHARTLAKE(dev_priv)) {
+   if (pll->info->id == DPLL_ID_EHL_DPLL4)
+   return MG_PLL_ENABLE(0);
+   }
+
+   return CNL_DPLL_ENABLE(pll->info->id);
+
+
+}
 /**
  * intel_prepare_shared_dpll - call a dpll's prepare hook
  * @crtc_state: CRTC, and its state, which has a shared dpll
@@ -3842,12 +3856,7 @@ static bool combo_pll_get_hw_state(struct 
drm_i915_private *dev_priv,
   struct intel_shared_dpll *pll,
   struct intel_dpll_hw_state *hw_state)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
-
-   if (IS_ELKHARTLAKE(dev_priv) &&
-   pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
-   }
+   i915_reg_t enable_reg = intel_get_pll_enable_reg(dev_priv, pll);
 
return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
 }
@@ -4045,11 +4054,10 @@ static void icl_pll_enable(struct drm_i915_private 
*dev_priv,
 static void combo_pll_enable(struct drm_i915_private *dev_priv,
 struct intel_shared_dpll *pll)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+   i915_reg_t enable_reg = intel_get_pll_enable_reg(dev_priv, pll);
 
if (IS_ELKHARTLAKE(dev_priv) &&
pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
 
/*
 * We need to disable DC states when this DPLL is enabled.
@@ -4157,11 +4165,10 @@ static void icl_pll_disable(struct drm_i915_private 
*dev_priv,
 static void combo_pll_disable(struct drm_i915_private *dev_priv,
  struct intel_shared_dpll *pll)
 {
-   i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+   i915_reg_t enable_reg = intel_get_pll_enable_reg(dev_priv, pll);
 
if (IS_ELKHARTLAKE(dev_priv) &&
pll->info->id == DPLL_ID_EHL_DPLL4) {
-   enable_reg = MG_PLL_ENABLE(0);
icl_pll_disable(dev_priv, pll, enable_reg);
 
intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
-- 
2.25.0

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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Fix stepping WA matching

[Srivatsa, Anusha]

With the stepping fix mentioned below,

Reviewed-by: Anusha Srivatsa 

> -Original Message-
> From: Souza, Jose 
> Sent: Thursday, August 27, 2020 3:57 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Cc: Bai, Guangyao ; Lee, Penne Y
> 
> Subject: Re: [PATCH] drm/i915/tgl: Fix stepping WA matching
> 
> On Thu, 2020-08-27 at 13:48 -0700, Srivatsa, Anusha wrote:
> > > -Original Message-
> > > From: Intel-gfx <
> > > intel-gfx-boun...@lists.freedesktop.org
> > > > On Behalf Of Souza,
> > > Jose
> > > Sent: Tuesday, August 25, 2020 12:49 PM
> > > To:
> > > intel-gfx@lists.freedesktop.org
> > >
> > > Cc: Bai, Guangyao <
> > > guangyao@intel.com
> > > >; Lee, Penne Y
> > > <
> > > penne.y@intel.com
> > > >
> > > Subject: Re: [Intel-gfx] [PATCH] drm/i915/tgl: Fix stepping WA
> > > matching
> > >
> > > On Wed, 2020-08-19 at 13:33 -0700, José Roberto de Souza wrote:
> > > > TGL made stepping a litte mess, workarounds refer to the stepping
> > > > of the IP(GT or Display) not of the GPU stepping so it would
> > > > already require the same solution as used in commit 96c5a15f9f39
> > > > ("drm/i915/kbl: Fix revision ID checks").
> > > > But to make things even more messy it have a different IP stepping
> > > > mapping between SKUs and the same stepping revision of GT do not
> > > > match the same HW between TGL U/Y and regular TGL.
> > > >
> > > > So it was required to have 2 different macros to check GT WAs
> > > > while for Display we are able to use just one macro that uses the
> > > > right revids table.
> > > >
> > > > All TGL workarounds checked and updated accordingly.
> > > >
> > > > BSpec: 52890
> > > > BSpec: 55378
> > > > BSpec: 44455
> > > > Cc: Penne Lee <
> > > > penne.y@intel.com
> > > >
> > > >
> > > > Cc: Guangyao Bai <
> > > > guangyao@intel.com
> > > >
> > > >
> > > > Cc: Matt Roper <
> > > > matthew.d.ro...@intel.com
> > > >
> > > >
> > > > Signed-off-by: José Roberto de Souza < jose.so...@intel.com
> > > >
> > > >
> > > > ---
> > > >  .../drm/i915/display/intel_display_power.c|  2 +-
> > > >  drivers/gpu/drm/i915/display/intel_psr.c  |  4 +-
> > > >  drivers/gpu/drm/i915/display/intel_sprite.c   |  2 +-
> > > >  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 24 ++--
> > > >  drivers/gpu/drm/i915/i915_drv.h   | 39 ---
> > > >  drivers/gpu/drm/i915/intel_pm.c   |  2 +-
> > > >  6 files changed, 59 insertions(+), 14 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > index 7946c6af4b1e..7277e58b01f1 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > @@ -5263,7 +5263,7 @@ static void tgl_bw_buddy_init(struct
> > >
> > > drm_i915_private *dev_priv)
> > > > unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
> > > > int config, i;
> > > >
> > > > -   if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> > > > +   if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> > > > /* Wa_1409767108: tgl */
> > > > table = wa_1409767108_buddy_page_masks;
> > > > else
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 2b004ee9619c..8a9d0bdde1bf 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -555,7 +555,7 @@ static void hsw_activate_psr2(struct intel_dp
> > > > *intel_dp)
> > > >
> > > > if (dev_priv->psr.psr2_sel_fetch_enabled) {
> > > > /* WA 1408330847 */
> > > > -   if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) 
> > > > ||
> > > > +   if (IS_TGL_DI

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Fix stepping WA matching

[Srivatsa, Anusha]

t; >
> > return plane_id < PLANE_SPRITE4;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index be5a4685c991..860d6ae1d866 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -70,6 +70,19 @@ const struct i915_rev_steppings kbl_revids[] = {
> > [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0
> > },  };
> >
> > +const struct i915_rev_steppings tgl_uy_revids[] = {
> > +   [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0
> },
> > +   [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0
> },
> > +   [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0
> },
> > +   [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0
> > +}, };
> > +
> > +/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean
> > +the same HW */ const struct i915_rev_steppings tgl_revids[] = {
> > +   [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0
Shouldn’t this have display stepping as B0? Or am I missing something?

Anusha

> },
> > +   [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0
> > +}, };
> > +
> >  static void wa_init_start(struct i915_wa_list *wal, const char *name,
> > const char *engine_name)  {
> > wal->name = name;
> > @@ -1219,13 +1232,13 @@ tgl_gt_workarounds_init(struct
> drm_i915_private *i915, struct i915_wa_list *wal)
> > gen12_gt_workarounds_init(i915, wal);
> >
> > /* Wa_1409420604:tgl */
> > -   if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> > +   if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> > wa_write_or(wal,
> > SUBSLICE_UNIT_LEVEL_CLKGATE2,
> > CPSSUNIT_CLKGATE_DIS);
> >
> > /* Wa_1607087056:tgl also know as BUG:1409180338 */
> > -   if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> > +   if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> > wa_write_or(wal,
> > SLICE_UNIT_LEVEL_CLKGATE,
> > L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); @@ -
> 1660,7 +1673,7 @@
> > rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list
> > *wal)  {
> > struct drm_i915_private *i915 = engine->i915;
> >
> > -   if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> > +   if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> > /*
> >  * Wa_1607138336:tgl
> >  * Wa_1607063988:tgl
> > @@ -1697,6 +1710,9 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> > wa_masked_en(wal, GEN9_ROW_CHICKEN4,
> GEN12_DISABLE_TDL_PUSH);
> >
> > /*
> > +* TODO: still pending the decision if this WA is permanent for
> > +* plain TGL SKU(not TGL-U/Y).
> 
> Wa_14010919138(mentioned one line bellow 'Wa_22010931296:tgl B0+') is
> now permanent so this TODO can be removed.
> 
> > +*
> >  * Wa_1407928979:tgl A*
> >  * Wa_18011464164:tgl B0+
> >  * Wa_22010931296:tgl B0+
> > @@ -1718,7 +1734,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> >  GEN8_RC_SEMA_IDLE_MSG_DISABLE);
> > }
> >
> > -   if (IS_TIGERLAKE(i915)) {
> > +   if (IS_TGL_U(i915) || IS_TGL_Y(i915)) {
> > /* Wa_1606700617:tgl */
> > wa_masked_en(wal,
> >  GEN9_CS_DEBUG_MODE1,
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 8e25dd15a2ec..499eb0a4ad3a
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1572,12 +1572,41 @@ extern const struct i915_rev_steppings
> > kbl_revids[];  #define IS_EHL_REVID(p, since, until) \
> > (IS_ELKHARTLAKE(p) && IS_REVID(p, since, until))
> >
> > -#define TGL_REVID_A0   0x0
> > -#define TGL_REVID_B0   0x1
> > -#define TGL_REVID_C0   0x2
> > +enum {
> > +   TGL_REVID_A0,
> > +   TGL_REVID_B0,
> > +   TGL_REVID_B1,
> > +   TGL_REVID_C0,
> > +   TGL_REVID_D0,
> > +};
> > +
> > +extern const struct i915_rev_steppings tgl_uy_revids[]; extern const
> > +struct i915_rev_steppings tgl_revids[];
> > +

[Intel-gfx] [PATCH 1/2] drm/i915/dmc: Load DMC firmware v2.07 for Tiger Lake

[Anusha Srivatsa]

Bump TGL DMC version to 2.07. This new version has power
saving enhancements.

Cc: José Roberto de Souza 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/display/intel_csr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_csr.c 
b/drivers/gpu/drm/i915/display/intel_csr.c
index f22a7645c249..eb74eb123148 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -44,8 +44,8 @@
 #define RKL_CSR_VERSION_REQUIRED   CSR_VERSION(2, 1)
 MODULE_FIRMWARE(RKL_CSR_PATH);
 
-#define TGL_CSR_PATH   "i915/tgl_dmc_ver2_06.bin"
-#define TGL_CSR_VERSION_REQUIRED   CSR_VERSION(2, 6)
+#define TGL_CSR_PATH   "i915/tgl_dmc_ver2_07.bin"
+#define TGL_CSR_VERSION_REQUIRED   CSR_VERSION(2, 7)
 #define TGL_CSR_MAX_FW_SIZE0x6000
 MODULE_FIRMWARE(TGL_CSR_PATH);
 
-- 
2.25.0

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[Intel-gfx] [PATCH 2/2] drm/i915/dmc: Load DMC firmware v2.02 for Rocket Lake

[Anusha Srivatsa]

The latest firmware contains fix for PSR2 power saving.

Cc: Matt Roper 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_csr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_csr.c 
b/drivers/gpu/drm/i915/display/intel_csr.c
index eb74eb123148..b6d0ce627d07 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,8 +40,8 @@
 
 #define GEN12_CSR_MAX_FW_SIZE  ICL_CSR_MAX_FW_SIZE
 
-#define RKL_CSR_PATH   "i915/rkl_dmc_ver2_01.bin"
-#define RKL_CSR_VERSION_REQUIRED   CSR_VERSION(2, 1)
+#define RKL_CSR_PATH   "i915/rkl_dmc_ver2_02.bin"
+#define RKL_CSR_VERSION_REQUIRED   CSR_VERSION(2, 2)
 MODULE_FIRMWARE(RKL_CSR_PATH);
 
 #define TGL_CSR_PATH   "i915/tgl_dmc_ver2_07.bin"
-- 
2.25.0

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[Intel-gfx] [PATCH 1/1] drm/i915/tgl: Load DMC firmware v2.07 for Tigerlake

[Anusha Srivatsa]

Bump TGL DMC version to 2.07. this new version has power
saving enhancements.

Cc: José Roberto de Souza 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_csr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_csr.c 
b/drivers/gpu/drm/i915/display/intel_csr.c
index f22a7645c249..eb74eb123148 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -44,8 +44,8 @@
 #define RKL_CSR_VERSION_REQUIRED   CSR_VERSION(2, 1)
 MODULE_FIRMWARE(RKL_CSR_PATH);
 
-#define TGL_CSR_PATH   "i915/tgl_dmc_ver2_06.bin"
-#define TGL_CSR_VERSION_REQUIRED   CSR_VERSION(2, 6)
+#define TGL_CSR_PATH   "i915/tgl_dmc_ver2_07.bin"
+#define TGL_CSR_VERSION_REQUIRED   CSR_VERSION(2, 7)
 #define TGL_CSR_MAX_FW_SIZE0x6000
 MODULE_FIRMWARE(TGL_CSR_PATH);
 
-- 
2.25.0

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[Intel-gfx] [PATCH 0/1] PR for new DMC updates

[Anusha Srivatsa]

Adding PR generated from drm-firmware repo for CI
to pull.

This has TGL DMC and also adding the RKL DMC
that got missed while adding the patch.

The following changes since commit 1d1c80b696539caa1d8a51d5f573012fbfa7eb5d:

  Update to 20200629111339 version to aligh SDK. Mainly fix DFS false alarm. 
(2020-07-16 10:43:12 -0400)

are available in the Git repository at:

  https://cgit.freedesktop.org/drm/drm-firmware/ TGL_RKL_DMC

for you to fetch changes up to f69ff907d2716a48dc84248772b2deccb033df7b:

  i915: Add RKL dmc v2.02 (2020-07-21 04:15:06 -0700)


Anusha Srivatsa (2):
  i915: Upgrade Tigerlake DMC to v2.07
  i915: Add RKL dmc v2.02

 WHENCE   |   6 ++
 i915/rkl_dmc_ver2_02.bin | Bin 0 -> 18204 bytes
 i915/tgl_dmc_ver2_07.bin | Bin 0 -> 18732 bytes
 3 files changed, 6 insertions(+)
 create mode 100644 i915/rkl_dmc_ver2_02.bin
 create mode 100644 i915/tgl_dmc_ver2_07.bin

Anusha Srivatsa (1):
  drm/i915/tgl: Load DMC firmware v2.07 for Tigerlake

 drivers/gpu/drm/i915/display/intel_csr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

-- 
2.25.0

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Re: [Intel-gfx] [PATCH v3 21/28] drm/i915/dg1: Update voltage swing tables for DP

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of
> Lucas De Marchi
> Sent: Thursday, July 2, 2020 5:24 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 21/28] drm/i915/dg1: Update voltage swing
> tables for DP
> 
> From: Matt Roper 
> 
> DG1's vswing tables are the same for eDP and HDMI but have slight
> differences from ICL/TGL for DP.
> 
> Bspec: 49291
> Cc: Clinton Taylor 
> Cc: José Roberto de Souza 
> Cc: Radhakrishna Sripada 
> Signed-off-by: Matt Roper 
> Signed-off-by: Lucas De Marchi 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 34 
>  1 file changed, 34 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 025d4052f6f8..9c230f532bbe 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans
> ehl_combo_phy_ddi_translations_dp[] = {
>   { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900   900  0.0   */
>  };
> 
> +static const struct cnl_ddi_buf_trans
> dg1_combo_phy_ddi_translations_dp_hbr[] = {
> + /* NT mV Trans mV db*/
> + { 0xA, 0x32, 0x3F, 0x00, 0x00 },/* 350   350  0.0   */
> + { 0xA, 0x48, 0x35, 0x00, 0x0A },/* 350   500  3.1   */
> + { 0xC, 0x63, 0x2F, 0x00, 0x10 },/* 350   700  6.0   */
> + { 0x6, 0x7F, 0x2C, 0x00, 0x13 },/* 350   900  8.2   */
> + { 0xA, 0x43, 0x3F, 0x00, 0x00 },/* 500   500  0.0   */
> + { 0xC, 0x60, 0x36, 0x00, 0x09 },/* 500   700  2.9   */
> + { 0x6, 0x7F, 0x30, 0x00, 0x0F },/* 500   900  5.1   */
> + { 0xC, 0x60, 0x3F, 0x00, 0x00 },/* 650   700  0.6   */
> + { 0x6, 0x7F, 0x37, 0x00, 0x08 },/* 600   900  3.5   */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900   900  0.0   */
> +};
> +
> +static const struct cnl_ddi_buf_trans
> dg1_combo_phy_ddi_translations_dp_hbr2[] = {
> + /* NT mV Trans mV db*/
> + { 0xA, 0x32, 0x3F, 0x00, 0x00 },/* 350   350  0.0   */
> + { 0xA, 0x48, 0x35, 0x00, 0x0A },/* 350   500  3.1   */
> + { 0xC, 0x63, 0x2F, 0x00, 0x10 },/* 350   700  6.0   */
> + { 0x6, 0x7F, 0x2C, 0x00, 0x13 },/* 350   900  8.2   */
> + { 0xA, 0x43, 0x3F, 0x00, 0x00 },/* 500   500  0.0   */
> + { 0xC, 0x60, 0x36, 0x00, 0x09 },/* 500   700  2.9   */
> + { 0x6, 0x7F, 0x30, 0x00, 0x0F },/* 500   900  5.1   */
> + { 0xC, 0x58, 0x3F, 0x00, 0x00 },/* 650   700  0.6   */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A },/* 600   900  3.5   */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900   900  0.0   */
> +};
From the bSpec page, the hbr2 values above are incorrect in more than one place.

Anusha

> +
>  struct icl_mg_phy_ddi_buf_trans {
>   u32 cri_txdeemph_override_11_6;
>   u32 cri_txdeemph_override_5_0;
> @@ -993,6 +1021,12 @@ icl_get_combo_buf_trans(struct drm_i915_private
> *dev_priv, int type, int rate,
>   } else if (type == INTEL_OUTPUT_EDP && dev_priv-
> >vbt.edp.low_vswing) {
>   *n_entries =
> ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
>   return icl_combo_phy_ddi_translations_edp_hbr2;
> + } else if (IS_DG1(dev_priv) && rate > 27) {
> + *n_entries =
> ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2);
> + return dg1_combo_phy_ddi_translations_dp_hbr2;
> + } else if (IS_DG1(dev_priv)) {
> + *n_entries =
> ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr);
> + return dg1_combo_phy_ddi_translations_dp_hbr;
>   }
> 
>   *n_entries =
> ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH v3 20/28] drm/i915/dg1: Update comp master/slave relationships for PHYs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of
> Lucas De Marchi
> Sent: Thursday, July 2, 2020 5:24 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 20/28] drm/i915/dg1: Update comp
> master/slave relationships for PHYs
> 
> From: Matt Roper 
> 
> As with RKL, DG1's PHY C acts as a comp master for PHY D.
> 
> Bspec: 49291
> Signed-off-by: Matt Roper 
> Signed-off-by: Lucas De Marchi 
Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 8604d4392e6a..2fad4871d4e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -243,14 +243,14 @@ static bool phy_is_master(struct
> drm_i915_private *dev_priv, enum phy phy)
>*
>* ICL,TGL:
>*   A(master) -> B(slave), C(slave)
> -  * RKL:
> +  * RKL,DG1:
>*   A(master) -> B(slave)
>*   C(master) -> D(slave)
>*
>* We must set the IREFGEN bit for any PHY acting as a master
>* to another PHY.
>*/
> - if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
> + if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy ==
> PHY_C)
>   return true;
> 
>   return phy == PHY_A;
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH v3 06/28] drm/i915/dg1: Add fake PCH

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of
> Lucas De Marchi
> Sent: Thursday, July 2, 2020 5:23 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 06/28] drm/i915/dg1: Add fake PCH
> 
> DG1 has the south engine display on the same PCI device. Ideally we could
> use HAS_PCH_SPLIT(), but that macro is misused all across the code base to
> rather signify a range of gens. So add a fake one for DG1 to be used where
> needed.
> 
> Cc: Aditya Swarup 
> Signed-off-by: Lucas De Marchi 
Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/intel_pch.c | 6 ++
> drivers/gpu/drm/i915/intel_pch.h | 4 
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pch.c
> b/drivers/gpu/drm/i915/intel_pch.c
> index c668e99eb2e4..6c97192e9ca8 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -188,6 +188,12 @@ void intel_detect_pch(struct drm_i915_private
> *dev_priv)  {
>   struct pci_dev *pch = NULL;
> 
> + /* DG1 has south engine display on the same PCI device */
> + if (IS_DG1(dev_priv)) {
> + dev_priv->pch_type = PCH_DG1;
> + return;
> + }
> +
>   /*
>* The reason to probe ISA bridge instead of Dev31:Fun0 is to
>* make graphics device passthrough work easy for VMM, that only
> diff --git a/drivers/gpu/drm/i915/intel_pch.h
> b/drivers/gpu/drm/i915/intel_pch.h
> index 3053d1ce398b..06d2cd50af0b 100644
> --- a/drivers/gpu/drm/i915/intel_pch.h
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -26,6 +26,9 @@ enum intel_pch {
>   PCH_JSP,/* Jasper Lake PCH */
>   PCH_MCC,/* Mule Creek Canyon PCH */
>   PCH_TGP,/* Tiger Lake PCH */
> +
> + /* Fake PCHs, functionality handled on the same PCI dev */
> + PCH_DG1 = 1024,
>  };
> 
>  #define INTEL_PCH_DEVICE_ID_MASK 0xff80
> @@ -56,6 +59,7 @@ enum intel_pch {
> 
>  #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
>  #define INTEL_PCH_ID(dev_priv)   ((dev_priv)->pch_id)
> +#define HAS_PCH_DG1(dev_priv)
>   (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
>  #define HAS_PCH_JSP(dev_priv)
>   (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
>  #define HAS_PCH_MCC(dev_priv)
>   (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
>  #define HAS_PCH_TGP(dev_priv)
>   (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH v3 19/28] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of
> Lucas De Marchi
> Sent: Thursday, July 2, 2020 5:24 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 19/28] drm/i915/dg1: Don't program
> PHY_MISC for PHY-C and PHY-D
> 
> From: Matt Roper 
Reviewed-by: Anusha Srivatsa 

> 
> The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the
> bspec details for that bit tell us that it need only be set for PHY-A and PHY-
> B.  It also turns out that there isn't even an instance of the PHY_MISC
> register for PHY-D on this platform.  Let's extend the EHL/RKL logic that
> conditionally skips PHY_MISC usage to DG1 as well.
> 
> Bspec: 50107
> Cc: Aditya Swarup 
> Cc: Clinton Taylor 
> Signed-off-by: Matt Roper 
> Signed-off-by: Lucas De Marchi 
> ---
>  drivers/gpu/drm/i915/display/intel_combo_phy.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 77b04bb3ec62..8604d4392e6a 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -189,7 +189,8 @@ static bool has_phy_misc(struct drm_i915_private
> *i915, enum phy phy)
>* other combo PHY's.
>*/
>   if (IS_ELKHARTLAKE(i915) ||
> - IS_ROCKETLAKE(i915))
> + IS_ROCKETLAKE(i915) ||
> + IS_DG1(i915))
>   return phy < PHY_C;
> 
>   return true;
> --
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/bios: Parse HOBL parameter

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of José
> Roberto de Souza
> Sent: Thursday, June 25, 2020 5:59 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 1/3] drm/i915/bios: Parse HOBL parameter
> 
> HOBL means hours of battery life, it is a power-saving feature were
> supported motherboards can use a special voltage swing table that uses
> less power.
> 
> So here parsing the VBT to check if this feature is supported.
> 
> BSpec: 20150
> Signed-off-by: José Roberto de Souza 

Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 3 +++
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 1 +
>  drivers/gpu/drm/i915/i915_drv.h   | 1 +
>  3 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 6593e2c38043..c53c85d38fa5 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -722,6 +722,9 @@ parse_power_conservation_features(struct
> drm_i915_private *dev_priv,
>*/
>   if (!(power->drrs & BIT(panel_type)))
>   dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> +
> + if (bdb->version >= 232)
> + dev_priv->vbt.edp.hobl = power->hobl & BIT(panel_type);
>  }
> 
>  static void
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index aef7fe932d1a..6faabd4f6d49 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -820,6 +820,7 @@ struct bdb_lfp_power {
>   u16 adb;
>   u16 lace_enabled_status;
>   struct agressiveness_profile_entry aggressivenes[16];
> + u16 hobl; /* 232+ */
>  } __packed;
> 
>  /*
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 9aad3ec979bd..16692c94351a
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -690,6 +690,7 @@ struct intel_vbt_data {
>   bool initialized;
>   int bpp;
>   struct edp_power_seq pps;
> + bool hobl;
>   } edp;
> 
>   struct {
> --
> 2.27.0
> 
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Re: [Intel-gfx] [PATCH] drm/i915/ehl: Add new PCI ids

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of José
> Roberto de Souza
> Sent: Tuesday, June 30, 2020 1:36 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH] drm/i915/ehl: Add new PCI ids
> 
> Two new PCI ids added to ehl.
> 
> BSpec: 29153
> Signed-off-by: José Roberto de Souza 
> ---
>  include/drm/i915_pciids.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> bc989de2aac2..0c7fcb1632ac 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -588,6 +588,8 @@
>   INTEL_VGA_DEVICE(0x4551, info), \
>   INTEL_VGA_DEVICE(0x4541, info), \
>   INTEL_VGA_DEVICE(0x4E71, info), \
> + INTEL_VGA_DEVICE(0x4557, info), \
> + INTEL_VGA_DEVICE(0x4555, info), \
>   INTEL_VGA_DEVICE(0x4E61, info), \
>   INTEL_VGA_DEVICE(0x4E51, info)

There are more PCIIDs missing from this patch. Like 0x4571,0x4551 etc

Anusha 
> 
> --
> 2.27.0
> 
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[Intel-gfx] [PATCH] drm/i915/dmc: Use firmware v2.02 for RKL

[Anusha Srivatsa]

The latest firmware contains fix for PSR2 power saving.

Cc: Matt Roper 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_csr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_csr.c 
b/drivers/gpu/drm/i915/display/intel_csr.c
index f22a7645c249..7e8b11aa6a8a 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,8 +40,8 @@
 
 #define GEN12_CSR_MAX_FW_SIZE  ICL_CSR_MAX_FW_SIZE
 
-#define RKL_CSR_PATH   "i915/rkl_dmc_ver2_01.bin"
-#define RKL_CSR_VERSION_REQUIRED   CSR_VERSION(2, 1)
+#define RKL_CSR_PATH   "i915/rkl_dmc_ver2_02.bin"
+#define RKL_CSR_VERSION_REQUIRED   CSR_VERSION(2, 2)
 MODULE_FIRMWARE(RKL_CSR_PATH);
 
 #define TGL_CSR_PATH   "i915/tgl_dmc_ver2_06.bin"
-- 
2.25.0

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Re: [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Matt
> Roper
> Sent: Tuesday, May 5, 2020 4:22 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas 
> Subject: [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits 
> for
> TC1 and TC2 outputs
> 
> When Rocket Lake is paired with a TGP PCH, the last two outputs utilize the
> TC1 and TC2 hpd pins, even though these are combo outputs.
> 
> Bspec: 49181
> Cc: Lucas De Marchi 
> Signed-off-by: Matt Roper 
Looks good.

Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6952b0295096..d32bbcd99b8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6172,8 +6172,12 @@ static bool bxt_digital_port_connected(struct
> intel_encoder *encoder)  static bool intel_combo_phy_connected(struct
> drm_i915_private *dev_priv,
> enum phy phy)
>  {
> - if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
> - return intel_de_read(dev_priv, SDEISR) &
> SDE_TC_HOTPLUG_ICP(PORT_TC1);
> + if (IS_ROCKETLAKE(dev_priv) && phy >= PHY_C)
> + return intel_de_read(dev_priv, SDEISR) &
> + SDE_TC_HOTPLUG_ICP(phy - PHY_C);
> + else if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
> + return intel_de_read(dev_priv, SDEISR) &
> + SDE_TC_HOTPLUG_ICP(PORT_TC1);
> 
>   return intel_de_read(dev_priv, SDEISR) &
> SDE_DDI_HOTPLUG_ICP(phy);  }
> --
> 2.24.1
> 
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Re: [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B

[Srivatsa, Anusha]

> -Original Message-
> From: Roper, Matthew D 
> Sent: Wednesday, May 6, 2020 10:20 PM
> To: Srivatsa, Anusha 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC
> for PHY's A and B
> 
> On Wed, May 06, 2020 at 06:49:06AM -0700, Srivatsa, Anusha wrote:
> >
> >
> > > -Original Message- From: Intel-gfx
> > >  On Behalf Of Matt Roper
> > > Sent: Tuesday, May 5, 2020 4:22 AM To:
> > > intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2
> > > 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
> > >
> > > Since the number of platforms with this restriction are growing,
> > > let's separate out the platform logic into a has_phy_misc()
> > > function.
> > >
> > > Bspec: 50107 Signed-off-by: Matt Roper 
> > > --- .../gpu/drm/i915/display/intel_combo_phy.c| 30
> > > +++ 1 file changed, 17 insertions(+), 13
> > > deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> > > b/drivers/gpu/drm/i915/display/intel_combo_phy.c index
> > > 9ff05ec12115..43d8784f6fa0 100644 ---
> > > a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++
> > > b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -181,11 +181,25
> > > @@ static void cnl_combo_phys_uninit(struct drm_i915_private
> > > *dev_priv) intel_de_write(dev_priv, CHICKEN_MISC_2, val);  }
> > >
> > > +static bool has_phy_misc(struct drm_i915_private *i915, enum phy
> > > phy) { +  /* + * Some platforms only expect PHY_MISC to be
> > > programmed for PHY-A and + * PHY-B and may not even have
> instances
> > > of the register for the +  * other combo PHY's.  + */ + if
> > > (IS_ELKHARTLAKE(i915) || +IS_ROCKETLAKE(i915)) + return phy <
> > > PHY_C;
> > According BSpec 50107, there is an instance of this for combo PHY C as
> > well.
> >
> Yeah, there's technically an instance of the register, but the only field in 
> it that
> our driver programs has a RKL programming note that says "This register field
> need only be programmed for port A and B."

Ok. Thanks for pointing it out.

Reviewed-by: Anusha Srivatsa 

> 
> Matt
> 
> > Anusha
> > > +
> > > + return true;
> > > +}
> > > +
> > >  static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
> > > enum phy phy)
> > >  {
> > >   /* The PHY C added by EHL has no PHY_MISC register */
> > > - if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> > > + if (!has_phy_misc(dev_priv, phy))
> > >   return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy))
> &
> > > COMP_INIT;
> > >   else
> > >   return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & @@ -
> > > 317,12 +331,7 @@ static void icl_combo_phys_init(struct
> > > drm_i915_private
> > > *dev_priv)
> > >   continue;
> > >   }
> > >
> > > - /*
> > > -  * Although EHL adds a combo PHY C, there's no PHY_MISC
> > > -  * register for it and no need to program the
> > > -  * DE_IO_COMP_PWR_DOWN setting on PHY C.
> > > -  */
> > > - if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> > > + if (!has_phy_misc(dev_priv, phy))
> > >   goto skip_phy_misc;
> > >
> > >   /*
> > > @@ -376,12 +385,7 @@ static void icl_combo_phys_uninit(struct
> > > drm_i915_private *dev_priv)
> > >"Combo PHY %c HW state changed
> unexpectedly\n",
> > >phy_name(phy));
> > >
> > > - /*
> > > -  * Although EHL adds a combo PHY C, there's no PHY_MISC
> > > -  * register for it and no need to program the
> > > -  * DE_IO_COMP_PWR_DOWN setting on PHY C.
> > > -  */
> > > - if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> > > + if (!has_phy_misc(dev_priv, phy))
> > >   goto skip_phy_misc;
> > >
> > >   val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
> > > --
> > > 2.24.1
> > >
> > > ___
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> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
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Re: [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Matt
> Roper
> Sent: Tuesday, May 5, 2020 4:22 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas 
> Subject: [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and
> PCI ids
> 
> Introduce the basic platform definition, macros, and PCI IDs.
> 
> Bspec: 44501
> Cc: Lucas De Marchi 
> Cc: Caz Yokoyama 
> Cc: Aditya Swarup 
> Signed-off-by: Matt Roper 
> Acked-by: Caz Yokoyama 

Confirmed the info with the BSpec.
Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  8 
>  drivers/gpu/drm/i915/i915_pci.c  | 10 ++
>  drivers/gpu/drm/i915/intel_device_info.c |  1 +
> drivers/gpu/drm/i915/intel_device_info.h |  1 +
>  include/drm/i915_pciids.h|  9 +
>  5 files changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 6af69555733e..1ba77283123d
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1406,6 +1406,7 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
>  #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
>  #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv,
> INTEL_ELKHARTLAKE)
>  #define IS_TIGERLAKE(dev_priv)   IS_PLATFORM(dev_priv,
> INTEL_TIGERLAKE)
> +#define IS_ROCKETLAKE(dev_priv)  IS_PLATFORM(dev_priv,
> INTEL_ROCKETLAKE)
>  #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>   (INTEL_DEVID(dev_priv) & 0xFF00) ==
> 0x0C00)  #define IS_BDW_ULT(dev_priv) \ @@ -1514,6 +1515,13 @@
> IS_SUBPLATFORM(const struct drm_i915_private *i915,  #define
> IS_TGL_REVID(p, since, until) \
>   (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
> 
> +#define RKL_REVID_A0 0x0
> +#define RKL_REVID_B0 0x1
> +#define RKL_REVID_C0 0x4
> +
> +#define IS_RKL_REVID(p, since, until) \
> + (IS_ROCKETLAKE(p) && IS_REVID(p, since, until))
> +
>  #define IS_LP(dev_priv)  (INTEL_INFO(dev_priv)->is_lp)
>  #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
>  #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 1faf9d6ec0a4..5a470bab2214 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -863,6 +863,15 @@ static const struct intel_device_info tgl_info = {
>   BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),  };
> 
> +static const struct intel_device_info rkl_info = {
> + GEN12_FEATURES,
> + PLATFORM(INTEL_ROCKETLAKE),
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> + .require_force_probe = 1,
> + .engine_mask =
> + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), };
> +
>  #define GEN12_DGFX_FEATURES \
>   GEN12_FEATURES, \
>   .is_dgfx = 1
> @@ -941,6 +950,7 @@ static const struct pci_device_id pciidlist[] = {
>   INTEL_ICL_11_IDS(&icl_info),
>   INTEL_EHL_IDS(&ehl_info),
>   INTEL_TGL_12_IDS(&tgl_info),
> + INTEL_RKL_IDS(&rkl_info),
>   {0, 0, 0}
>  };
>  MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 91bb7891c70c..9862c1185059 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -61,6 +61,7 @@ static const char * const platform_names[] = {
>   PLATFORM_NAME(ICELAKE),
>   PLATFORM_NAME(ELKHARTLAKE),
>   PLATFORM_NAME(TIGERLAKE),
> + PLATFORM_NAME(ROCKETLAKE),
>  };
>  #undef PLATFORM_NAME
> 
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 69c9257c6c6a..a126984cef7f 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -80,6 +80,7 @@ enum intel_platform {
>   INTEL_ELKHARTLAKE,
>   /* gen12 */
>   INTEL_TIGERLAKE,
> + INTEL_ROCKETLAKE,
>   INTEL_MAX_PLATFORMS
>  };
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 662d8351c87a..bc989de2aac2 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -605,4 +605,13 @@
>   INTEL_VGA_DEVICE(0x9AD9, info), \
>   INTEL_VGA_DEVICE(0x9AF8, info)
> 
> +/* RKL */
> +#define INTEL_RKL_IDS(info) \
> + INTEL_VGA_DEVICE(0x4C80, info), \
> +

Re: [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Matt
> Roper
> Sent: Tuesday, May 5, 2020 4:22 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for
> PHY's A and B
> 
> Since the number of platforms with this restriction are growing, let's 
> separate
> out the platform logic into a has_phy_misc() function.
> 
> Bspec: 50107
> Signed-off-by: Matt Roper 
> ---
>  .../gpu/drm/i915/display/intel_combo_phy.c| 30 +++
>  1 file changed, 17 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 9ff05ec12115..43d8784f6fa0 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -181,11 +181,25 @@ static void cnl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
>   intel_de_write(dev_priv, CHICKEN_MISC_2, val);  }
> 
> +static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) {
> + /*
> +  * Some platforms only expect PHY_MISC to be programmed for PHY-A
> and
> +  * PHY-B and may not even have instances of the register for the
> +  * other combo PHY's.
> +  */
> + if (IS_ELKHARTLAKE(i915) ||
> + IS_ROCKETLAKE(i915))
> + return phy < PHY_C;
According BSpec 50107, there is an instance of this for combo PHY C as well. 

Anusha
> +
> + return true;
> +}
> +
>  static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
> enum phy phy)
>  {
>   /* The PHY C added by EHL has no PHY_MISC register */
> - if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> + if (!has_phy_misc(dev_priv, phy))
>   return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy))
> & COMP_INIT;
>   else
>   return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & @@ -
> 317,12 +331,7 @@ static void icl_combo_phys_init(struct drm_i915_private
> *dev_priv)
>   continue;
>   }
> 
> - /*
> -  * Although EHL adds a combo PHY C, there's no PHY_MISC
> -  * register for it and no need to program the
> -  * DE_IO_COMP_PWR_DOWN setting on PHY C.
> -  */
> - if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> + if (!has_phy_misc(dev_priv, phy))
>   goto skip_phy_misc;
> 
>   /*
> @@ -376,12 +385,7 @@ static void icl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
>"Combo PHY %c HW state changed
> unexpectedly\n",
>phy_name(phy));
> 
> - /*
> -  * Although EHL adds a combo PHY C, there's no PHY_MISC
> -  * register for it and no need to program the
> -  * DE_IO_COMP_PWR_DOWN setting on PHY C.
> -  */
> - if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> + if (!has_phy_misc(dev_priv, phy))
>   goto skip_phy_misc;
> 
>   val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
> --
> 2.24.1
> 
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Re: [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Matt
> Roper
> Sent: Tuesday, May 5, 2020 4:22 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas 
> Subject: [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support
> 
> RKL re-uses the same stolen memory registers as TGL and ICL.
> 
> Bspec: 52055
> Bspec: 49589
> Bspec: 49636
> Cc: Lucas De Marchi 
> Signed-off-by: Matt Roper 

Confirmed with Spec.
Reviewed-by: Anusha Srivatsa 

> ---
>  arch/x86/kernel/early-quirks.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 2f9ec14be3b1..a4b5af03dcc1 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -550,6 +550,7 @@ static const struct pci_device_id intel_early_ids[]
> __initconst = {
>   INTEL_ICL_11_IDS(&gen11_early_ops),
>   INTEL_EHL_IDS(&gen11_early_ops),
>   INTEL_TGL_12_IDS(&gen11_early_ops),
> + INTEL_RKL_IDS(&gen11_early_ops),
>  };
> 
>  struct resource intel_graphics_stolen_res __ro_after_init =
> DEFINE_RES_MEM(0, 0);
> --
> 2.24.1
> 
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Re: [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave relationships for PHYs

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Matt
> Roper
> Sent: Tuesday, May 5, 2020 4:22 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas 
> Subject: [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave
> relationships for PHYs
> 
> Certain combo PHYs act as a compensation master to other PHYs and need to
> be initialized with a special irefgen bit in the PORT_COMP_DW8 register.
> Previously PHY A was the only compensation master (for PHYs B & C), but RKL
> adds a fourth PHY which is slaved to PHY C instead.
> 
> Bspec: 49291
> Cc: Lucas De Marchi 
> Cc: José Roberto de Souza 
> Cc: Aditya Swarup 
> Signed-off-by: Matt Roper 

Reviewed-by: Anusha Srivatsa 

> ---
>  .../gpu/drm/i915/display/intel_combo_phy.c| 25 +--
>  1 file changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 43d8784f6fa0..77b04bb3ec62 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -234,6 +234,27 @@ static bool ehl_vbt_ddi_d_present(struct
> drm_i915_private *i915)
>   return false;
>  }
> 
> +static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy
> +phy) {
> + /*
> +  * Certain PHYs are connected to compensation resistors and act
> +  * as masters to other PHYs.
> +  *
> +  * ICL,TGL:
> +  *   A(master) -> B(slave), C(slave)
> +  * RKL:
> +  *   A(master) -> B(slave)
> +  *   C(master) -> D(slave)
> +  *
> +  * We must set the IREFGEN bit for any PHY acting as a master
> +  * to another PHY.
> +  */
> + if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
> + return true;
> +
> + return phy == PHY_A;
> +}
> +
>  static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
>  enum phy phy)
>  {
> @@ -245,7 +266,7 @@ static bool icl_combo_phy_verify_state(struct
> drm_i915_private *dev_priv,
> 
>   ret = cnl_verify_procmon_ref_values(dev_priv, phy);
> 
> - if (phy == PHY_A) {
> + if (phy_is_master(dev_priv, phy)) {
>   ret &= check_phy_reg(dev_priv, phy,
> ICL_PORT_COMP_DW8(phy),
>IREFGEN, IREFGEN);
> 
> @@ -356,7 +377,7 @@ static void icl_combo_phys_init(struct
> drm_i915_private *dev_priv)
>  skip_phy_misc:
>   cnl_set_procmon_ref_values(dev_priv, phy);
> 
> - if (phy == PHY_A) {
> + if (phy_is_master(dev_priv, phy)) {
>   val = intel_de_read(dev_priv,
> ICL_PORT_COMP_DW8(phy));
>   val |= IREFGEN;
>   intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy),
> val);
> --
> 2.24.1
> 
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Re: [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping

[Srivatsa, Anusha]

> -Original Message-
> From: Intel-gfx  On Behalf Of Matt
> Roper
> Sent: Tuesday, May 5, 2020 4:22 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping
> 
> The pin mapping for the final two outputs varies according to which PCH is
> present on the platform:  with TGP the pins are remapped into the TC range,
> whereas with CMP they stay in the traditional combo output range.
> 
> Bspec: 49181
> Cc: Aditya Swarup 
> Signed-off-by: Matt Roper 
Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/display/intel_hdmi.c | 22 +-
>  1 file changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 010f37240710..a31a98d26882 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3082,6 +3082,24 @@ static u8 mcc_port_to_ddc_pin(struct
> drm_i915_private *dev_priv, enum port port)
>   return ddc_pin;
>  }
> 
> +static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum
> +port port) {
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> +
> + WARN_ON(port == PORT_C);
> +
> + /*
> +  * Pin mapping for RKL depends on which PCH is present.  With TGP,
> the
> +  * final two outputs use type-c pins, even though they're actually
> +  * combo outputs.  With CMP, the traditional DDI A-D pins are used for
> +  * all outputs.
> +  */
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
> + return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
> +
> + return GMBUS_PIN_1_BXT + phy;
> +}
> +
>  static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
> enum port port)
>  {
> @@ -3119,7 +3137,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder
> *encoder)
>   return ddc_pin;
>   }
> 
> - if (HAS_PCH_MCC(dev_priv))
> + if (IS_ROCKETLAKE(dev_priv))
> + ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
> + else if (HAS_PCH_MCC(dev_priv))
>   ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
>   else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>   ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
> --
> 2.24.1
> 
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Re: [Intel-gfx] [PATCH 04/23] drm/i915/rkl: Load DMC firmware for Rocket Lake

[Srivatsa, Anusha]

> -Original Message-
> From: Roper, Matthew D 
> Sent: Friday, May 1, 2020 10:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; Srivatsa, Anusha
> 
> Subject: [PATCH 04/23] drm/i915/rkl: Load DMC firmware for Rocket Lake
> 
> Cc: Anusha Srivatsa 
> Signed-off-by: Matt Roper 
Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/display/intel_csr.c | 10 +-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_csr.c
> b/drivers/gpu/drm/i915/display/intel_csr.c
> index 3112572cfb7d..319932b03e88 100644
> --- a/drivers/gpu/drm/i915/display/intel_csr.c
> +++ b/drivers/gpu/drm/i915/display/intel_csr.c
> @@ -40,6 +40,10 @@
> 
>  #define GEN12_CSR_MAX_FW_SIZEICL_CSR_MAX_FW_SIZE
> 
> +#define RKL_CSR_PATH "i915/rkl_dmc_ver2_01.bin"
> +#define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
> +MODULE_FIRMWARE(RKL_CSR_PATH);
> +
>  #define TGL_CSR_PATH "i915/tgl_dmc_ver2_06.bin"
>  #define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 6)
>  #define TGL_CSR_MAX_FW_SIZE  0x6000
> @@ -682,7 +686,11 @@ void intel_csr_ucode_init(struct drm_i915_private
> *dev_priv)
>*/
>   intel_csr_runtime_pm_get(dev_priv);
> 
> - if (INTEL_GEN(dev_priv) >= 12) {
> + if (IS_ROCKETLAKE(dev_priv)) {
> + csr->fw_path = RKL_CSR_PATH;
> + csr->required_version = RKL_CSR_VERSION_REQUIRED;
> + csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> + } else if (INTEL_GEN(dev_priv) >= 12) {
>   csr->fw_path = TGL_CSR_PATH;
>   csr->required_version = TGL_CSR_VERSION_REQUIRED;
>   /* Allow to load fw via parameter using the last known size */
> --
> 2.24.1

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Re: [Intel-gfx] [PATCH 03/23] drm/i915/rkl: Re-use TGL GuC/HuC firmware

[Srivatsa, Anusha]

> -Original Message-
> From: Roper, Matthew D 
> Sent: Friday, May 1, 2020 10:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; Srivatsa, Anusha
> 
> Subject: [PATCH 03/23] drm/i915/rkl: Re-use TGL GuC/HuC firmware
> 
> RKL uses the same GuC and HuC as TGL and should load the same firmwares.
> 
> Bspec: 50668
> Cc: Anusha Srivatsa 
> Signed-off-by: Matt Roper 
Reviewed-by: Anusha Srivatsa 

> ---
>  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index e1caae93996d..9b6218128d09 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -47,8 +47,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw
> *uc_fw,
>   * TGL 35.2 is interface-compatible with 33.0 for previous Gens. The deltas
>   * between 33.0 and 35.2 are only related to new additions to support new
> Gen12
>   * features.
> + *
> + * Note that RKL uses the same firmware as TGL.
>   */
>  #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
> + fw_def(ROCKETLAKE,  0, guc_def(tgl, 35, 2, 0), huc_def(tgl,  7, 0, 12)) 
> \
>   fw_def(TIGERLAKE,   0, guc_def(tgl, 35, 2, 0), huc_def(tgl,  7, 0, 12)) 
> \
>   fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9, 0, 0)) \
>   fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  9, 0, 0)) \
> --
> 2.24.1

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[Intel-gfx] [PATCH] drm/i915: Extend Wa_1606931601 for all steppings.

[Anusha Srivatsa]

Previously known by the WA number - Wa_1607090982, extend
the WA (Disable Early Read and Src Swap (bit 14) by
setting the chicken register.) to all steppings.

The WA is implemented in -
3873fd1a43c7 ("drm/i915: Use engine wa list for Wa_1607090982")

Bspec: 46045,52890

Cc: Mika Kuoppala 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 887e0dc701f7..7cc8a7fc53c7 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1329,6 +1329,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
 {
struct drm_i915_private *i915 = engine->i915;
 
+   if (IS_TIGERLAKE(i915)) {
+   /* Wa_1606931601:tgl */
+   wa_masked_en(wal,
+GEN7_ROW_CHICKEN2,
+GEN12_DISABLE_EARLY_READ);
+   }
+
if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/* Wa_1606700617:tgl */
wa_masked_en(wal,
@@ -1360,11 +1367,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
wa_write_or(wal,
GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
-
-   /* Wa_1606931601:tgl */
-   wa_masked_en(wal,
-GEN7_ROW_CHICKEN2,
-GEN12_DISABLE_EARLY_READ);
}
 
if (IS_GEN(i915, 11)) {
-- 
2.25.0

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[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

[Anusha Srivatsa]

Disable Early Read and Src Swap (bit 14) by setting the chicken
register.

BSpec: 46045,52890

v2: Follow the Bspec implementation for the WA.
v3: Have 2 separate defines for bit 14 and 15.
- Rename register definitions with TGL_ prefix
v4: Bspec changed. Again. Add WA to rcs_ WA list.

Cc: Daniele Ceraolo Spurio 
Cc: Matt Roper 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Matt Atwood 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 61106129287f..310f8e1beaab 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1326,6 +1326,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
 {
struct drm_i915_private *i915 = engine->i915;
 
+   if (IS_TGL_REVID(i915, TGL_REVID_A0, REVID_FOREVER)) {
+   /* Wa_1606931601:tgl */
+   wa_write_or(wal,
+   GEN7_ROW_CHICKEN2,
+   GEN12_EARLY_READ_SRC0_DISABLE);
+   }
if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/* Wa_1606700617:tgl */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bd431f6a011..c46bec8ebd17 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9151,6 +9151,7 @@ enum {
 #define   DOP_CLOCK_GATING_DISABLE (1 << 0)
 #define   PUSH_CONSTANT_DEREF_DISABLE  (1 << 8)
 #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE   (1 << 1)
+#define   GEN12_EARLY_READ_SRC0_DISABLE(1 << 14)
 
 #define HSW_ROW_CHICKEN3   _MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE(1 << 6)
-- 
2.25.0

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[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

[Anusha Srivatsa]

Disable Early Read and Src Swap (bit 14) by setting the chicken
register.

BSpec: 46045,52890

v2: Follow the Bspec implementation for the WA.
v3: Have 2 separate defines for bit 14 and 15.
- Rename register definitions with TGL_ prefix
v4: Bspec changed. Again. Add WA to rcs_ WA list.

Cc: Daniele Ceraolo Spurio 
Cc: Matt Roper 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 8d7c3191137c..b0bcf8c55da0 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -593,6 +593,7 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs 
*engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
   IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
+
 }
 
 static void
@@ -1319,6 +1320,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
 {
struct drm_i915_private *i915 = engine->i915;
 
+   if (IS_TGL_REVID(i915, TGL_REVID_A0, REVID_FOREVER)) {
+   /* Wa_1606931601:tgl */
+   wa_write_or(wal,
+   GEN7_ROW_CHICKEN2,
+   GEN12_EARLY_READ_SRC0_DISABLE);
+   }
if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
/* Wa_1606700617:tgl */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bd431f6a011..c46bec8ebd17 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9151,6 +9151,7 @@ enum {
 #define   DOP_CLOCK_GATING_DISABLE (1 << 0)
 #define   PUSH_CONSTANT_DEREF_DISABLE  (1 << 8)
 #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE   (1 << 1)
+#define   GEN12_EARLY_READ_SRC0_DISABLE(1 << 14)
 
 #define HSW_ROW_CHICKEN3   _MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE(1 << 6)
-- 
2.25.0

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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

[Srivatsa, Anusha]

> -Original Message-
> From: Roper, Matthew D 
> Sent: Thursday, January 30, 2020 12:43 PM
> To: Srivatsa, Anusha 
> Cc: intel-gfx@lists.freedesktop.org; Ceraolo Spurio, Daniele
> 
> Subject: Re: [PATCH] drm/i915/tgl: Implement Wa_1606931601
> 
> On Wed, Jan 29, 2020 at 02:42:06PM -0800, Anusha Srivatsa wrote:
> > Disable Inter and intra Read Suppression (bit 15) and Early Read and
> > Src Swap (bit 14) by setting the chicken register.
> >
> > BSpec: 46045,52890
> >
> > v2: Follow the Bspec implementation for the WA.
> > v3: Have 2 separate defines for bit 14 and 15.
> > - Rename register definitions with TGL_ prefix
> 
> The hardware guys changed their mind again and we're back to only needing
> bit 14 now.  They updated the bspec and the underlying database yet again.
> :-/
 ☹

> >
> > Cc: Matt Roper 
> > Signed-off-by: Anusha Srivatsa 
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
> >  drivers/gpu/drm/i915/i915_reg.h | 2 ++
> >  2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 5a7db279f702..1f84cd595f88 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -593,6 +593,12 @@ static void tgl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> > wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> >IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> > FF_MODE2_TDS_TIMER_MASK);
> > +
> > +   /* Wa_1606931601:tgl */
> > +   WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> > + GEN12_EARLY_READ_SRC0_DISABLE |
> > +
> GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE);
> 
> I think Daniele already mentioned this on the other discussion, but
> ROW_CHICKEN2 isn't part of the context image on gen12 (see bspec page
> 46255).  This is a change from ICL where it *was* part of the context (see
> bspec page 18907), so even though we handled this register in the
> ctx_workarounds_init for ICL, that's not the appropriate place to put it for
> TGL.
Agreed. 

> Since this isn't a context workaround, we need to determine whether it's a
> general GT workaround (which would be initialized in
> tgl_gt_workarounds_init) or an engine workaround (which would be
> initialized in {rcs,xcs}_engine_wa_init.  In this case the register we're
> modifying is 0xe49c; according to bspec page 52078 this falls in one of the
> forcewake ranges listed under the render engine column (0E000-0E8FF). 

The register we are setting is 0xe4f4. This comes under Render engine. Adding 
this change to rcs_engine_wa_init().

> So I
> believe in this case that means we want to update
> rcs_engine_wa_init() with this workaround --- that ensures that the
> workaround will be re-applied any time the engine is reset (even if it's not a
> full-GPU reset).
Yes. Adding this to rcs_engine_wa_init().


Anusha 
> 
> Matt
> 
> > +
> >  }
> >
> >  static void
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 4c72b8ac0f2e..70ead809c706
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9149,6 +9149,8 @@ enum {
> >  #define   DOP_CLOCK_GATING_DISABLE (1 << 0)
> >  #define   PUSH_CONSTANT_DEREF_DISABLE  (1 << 8)
> >  #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE   (1 << 1)
> > +#define   GEN12_EARLY_READ_SRC0_DISABLE(1 << 14)
> > +#define   GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE   (1 <<
> 15)
> >
> >  #define HSW_ROW_CHICKEN3   _MMIO(0xe49c)
> >  #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE(1 << 6)
> > --
> > 2.25.0
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
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[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

[Anusha Srivatsa]

Disable Inter and intra Read Suppression (bit 15) and
Early Read and Src Swap (bit 14) by setting the chicken
register.

BSpec: 46045,52890

v2: Follow the Bspec implementation for the WA.
v3: Have 2 separate defines for bit 14 and 15.
- Rename register definitions with TGL_ prefix

Cc: Matt Roper 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5a7db279f702..1f84cd595f88 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -593,6 +593,12 @@ static void tgl_ctx_workarounds_init(struct 
intel_engine_cs *engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
   IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
+
+   /* Wa_1606931601:tgl */
+   WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN12_EARLY_READ_SRC0_DISABLE |
+ GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE);
+
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4c72b8ac0f2e..70ead809c706 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9149,6 +9149,8 @@ enum {
 #define   DOP_CLOCK_GATING_DISABLE (1 << 0)
 #define   PUSH_CONSTANT_DEREF_DISABLE  (1 << 8)
 #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE   (1 << 1)
+#define   GEN12_EARLY_READ_SRC0_DISABLE(1 << 14)
+#define   GEN12_INTER_INTRA_READ_SUPPRESSION_DISABLE   (1 << 15)
 
 #define HSW_ROW_CHICKEN3   _MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE(1 << 6)
-- 
2.25.0

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[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

[Anusha Srivatsa]

Disable Early Read and Src Swap by setting the bit 14
and 15 in the chicken register.

BSpec: 46045,52890

v2: Follow the Bspec implementation for the WA.

Cc: Matt Roper 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5a7db279f702..c1c970b15395 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -593,6 +593,11 @@ static void tgl_ctx_workarounds_init(struct 
intel_engine_cs *engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
   IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
+
+   /* Wa_1606931601:tgl */
+   WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN11_EARLY_READ_SRC0_DISABLE);
+
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b93c4c18f05c..c8b51ccfa5e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9146,6 +9146,7 @@ enum {
 #define   DOP_CLOCK_GATING_DISABLE (1 << 0)
 #define   PUSH_CONSTANT_DEREF_DISABLE  (1 << 8)
 #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE   (1 << 1)
+#define   GEN11_EARLY_READ_SRC0_DISABLE(1 << 14)
 
 #define HSW_ROW_CHICKEN3   _MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE(1 << 6)
-- 
2.23.0

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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

[Srivatsa, Anusha]

> -Original Message-
> From: Roper, Matthew D 
> Sent: Thursday, January 23, 2020 9:50 AM
> To: Srivatsa, Anusha 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
> 
> On Wed, Jan 22, 2020 at 03:40:27PM -0800, Anusha Srivatsa wrote:
> > Disable Early Read and Src Swap by setting the bit 14 and 15 in the
> > chicken register.
> >
> > BSpec: 46045,52890
> > HSDES: 1606931601
> 
> Hmm.  The bspec WA description (which is very poorly written) only
> mentions setting bit 14, but comments in the HSD indicate that both 14 and
> 15 should be set.  Do we have offline confirmation/clarification about which
> we should trust?
> 
> If we do need to program both bits, it might still be a good idea to use two
> separate #define's for those rather than a single bitmask to make it more
> clear what we're doing and also to give us the option of just setting one or
> the other in case that winds up being necessary as a workaround for a
> different platform or future stepping.
> 
Going ahead with what the BSpec expects us to do - setting just bit 14. Sending 
v2 version shortly.

Anusha  

> Matt
> 
> >
> > Signed-off-by: Anusha Srivatsa 
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> >  drivers/gpu/drm/i915/i915_reg.h | 1 +
> >  2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 5a7db279f702..53b448b61a5f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -593,6 +593,11 @@ static void tgl_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> > wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> >IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> > FF_MODE2_TDS_TIMER_MASK);
> > +
> > +   /* Wa_1606931601:tgl */
> > +   WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> > + GEN11_EARLY_READ_SRC0_DISABLE_MASK);
> > +
> >  }
> >
> >  static void
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index b93c4c18f05c..69a1c2227b91
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9146,6 +9146,7 @@ enum {
> >  #define   DOP_CLOCK_GATING_DISABLE (1 << 0)
> >  #define   PUSH_CONSTANT_DEREF_DISABLE  (1 << 8)
> >  #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE   (1 << 1)
> > +#define   GEN11_EARLY_READ_SRC0_DISABLE_MASK
>   REG_GENMASK(15, 14)
> >
> >  #define HSW_ROW_CHICKEN3   _MMIO(0xe49c)
> >  #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE(1 << 6)
> > --
> > 2.23.0
> >
> > ___
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795
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[Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601

[Anusha Srivatsa]

Disable Early Read and Src Swap by setting the bit 14
and 15 in the chicken register.

BSpec: 46045,52890
HSDES: 1606931601

Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5a7db279f702..53b448b61a5f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -593,6 +593,11 @@ static void tgl_ctx_workarounds_init(struct 
intel_engine_cs *engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
   IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
+
+   /* Wa_1606931601:tgl */
+   WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+ GEN11_EARLY_READ_SRC0_DISABLE_MASK);
+
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b93c4c18f05c..69a1c2227b91 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9146,6 +9146,7 @@ enum {
 #define   DOP_CLOCK_GATING_DISABLE (1 << 0)
 #define   PUSH_CONSTANT_DEREF_DISABLE  (1 << 8)
 #define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE   (1 << 1)
+#define   GEN11_EARLY_READ_SRC0_DISABLE_MASK   REG_GENMASK(15, 14)
 
 #define HSW_ROW_CHICKEN3   _MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE(1 << 6)
-- 
2.23.0

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[Intel-gfx] i915 firmware updates (CMl- GuC,HuC; TGL-DMC,ICL-DMC, HuC Updates-SKL,BXT,KBL,GLK,ICL)

[Srivatsa, Anusha]

Hi,
Kyle, Josh,Ben

Ignore the previous PR and kindly consider this one. It has another new update 
and is the latest one-

The following changes since commit 6c6918ad8ae0dfb2cb591484eba525409980c16f:

  linux-firmware: Update firmware file for Intel Bluetooth AX201 (2019-09-09 
04:22:42 -0400)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-firmware cml_tgl-icl-dmc_huc_updates

for you to fetch changes up to 3ea84e52306e7b78cc6d727d9a41c8449146d765:

  drm/i915/firmware: Add v9.0.0 of HuC for Icelake (2019-09-13 14:48:47 -0700)


Anusha Srivatsa (9):
  drm/i915/firmware: Add v1.09 of DMC for ICL
  drm/i915/firmware: Add v2.04 of DMC for TGL
  drm/i915/firmware: Add v33 of GuC for CML
  drm/i915/firmware: Add v2.0.0 of HuC for Skylake
  drm/i915/firmware: Add v4.0.0 of HuC for Kabylake
  drm/i915/firmware: Add v2.0.0 of HuC for Broxton
  drm/i915/firmware: Add v4.0.0 of HuC for Geminilake
  drm/i915/firmware: Add v4.0.0 of HuC for Cometlake
  drm/i915/firmware: Add v9.0.0 of HuC for Icelake

 WHENCE   |  28 
 i915/bxt_huc_2.0.0.bin   | Bin 0 -> 149824 bytes
 i915/cml_guc_33.0.0.bin  | Bin 0 -> 182912 bytes
 i915/cml_huc_4.0.0.bin   | Bin 0 -> 226048 bytes
 i915/glk_huc_4.0.0.bin   | Bin 0 -> 226048 bytes
 i915/icl_dmc_ver1_09.bin | Bin 0 -> 25952 bytes
 i915/icl_huc_9.0.0.bin   | Bin 0 -> 498880 bytes
 i915/kbl_huc_4.0.0.bin   | Bin 0 -> 226048 bytes
 i915/skl_huc_2.0.0.bin   | Bin 0 -> 136320 bytes
 i915/tgl_dmc_ver2_04.bin | Bin 0 -> 18436 bytes
 10 files changed, 28 insertions(+)
 create mode 100644 i915/bxt_huc_2.0.0.bin
 create mode 100644 i915/cml_guc_33.0.0.bin
 create mode 100644 i915/cml_huc_4.0.0.bin
 create mode 100644 i915/glk_huc_4.0.0.bin
 create mode 100644 i915/icl_dmc_ver1_09.bin
 create mode 100644 i915/icl_huc_9.0.0.bin
 create mode 100644 i915/kbl_huc_4.0.0.bin
 create mode 100644 i915/skl_huc_2.0.0.bin
 create mode 100644 i915/tgl_dmc_ver2_04.bin


Thanks,
Anusha
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[Intel-gfx] [CI 2/2] HAX: force enable_guc=2

[Anusha Srivatsa]

Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -54,7 +54,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
+   param(int, enable_guc, 2) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.23.0

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[Intel-gfx] [CI 1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC

[Anusha Srivatsa]

Make both GuC and HuC to use "." as the separator. Hardcode
the separator in MAKE_UC_FW_PATH. Remove the usage of "ver" from HuC.

The current convention being:
_uc_..patch.bin

Update the versions of HuC being loaded of the platforms.

SKL - v2.0.0
BXT - v2.0.0
KBL - v4.0.0
GLK - v4.0.0
CFL - KBL v4.0.0
ICL - v9.0.0
CML - v4.0.0

v2: Remove the separator parameter altogether from
__MAKE_UC_FW_PATH.(Daniele)
- Squash all firmware update patches (Daniele)
v3: s/huc/HuC
- Correct the order of platforms
- Change REVID of cml to 5(Michal)
- Code space changes in huc_def (Daniele)

Suggested-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 27 
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 296a82603be0..ea9a807abd4f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -39,26 +39,27 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * Must be ordered based on platform + revid, from newer to older.
  */
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
-   fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9,  0,
0)) \
-   fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  8,  4, 
3238)) \
-   fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
-   fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 
2893)) \
-   fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
-   fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01,  8, 
2893)) \
-   fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 
1398))
-
-#define __MAKE_UC_FW_PATH(prefix_, name_, separator_, major_, minor_, patch_) \
+   fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9, 0, 0)) \
+   fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  9, 0, 0)) \
+   fw_def(COFFEELAKE,  5, guc_def(cml, 33, 0, 0), huc_def(cml,  4, 0, 0)) \
+   fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4, 0, 0)) \
+   fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk,  4, 0, 0)) \
+   fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4, 0, 0)) \
+   fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt,  2, 0, 0)) \
+   fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl,  2, 0, 0))
+
+#define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \
"i915/" \
__stringify(prefix_) name_ \
-   __stringify(major_) separator_ \
-   __stringify(minor_) separator_ \
+   __stringify(major_) "." \
+   __stringify(minor_) "." \
__stringify(patch_) ".bin"
 
 #define MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_) \
-   __MAKE_UC_FW_PATH(prefix_, "_guc_", ".", major_, minor_, patch_)
+   __MAKE_UC_FW_PATH(prefix_, "_guc_", major_, minor_, patch_)
 
 #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \
-   __MAKE_UC_FW_PATH(prefix_, "_huc_ver", "_", major_, minor_, bld_num_)
+   __MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_)
 
 /* All blobs need to be declared via MODULE_FIRMWARE() */
 #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
-- 
2.23.0

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[Intel-gfx] [PATCH 1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC

[Anusha Srivatsa]

Make both GuC and HuC to use "." as the separator. Hardcode
the separator in MAKE_UC_FW_PATH. Remove the usage of "ver" from HuC.

The current convention being:
_uc_..patch.bin

Update the versions of HuC being loaded of the platforms.

SKL - v2.0.0
BXT - v2.0.0
KBL - v4.0.0
GLK - v4.0.0
CFL - KBL v4.0.0
ICL - v9.0.0
CML - v4.0.0

v2: Remove the separator parameter altogether from
__MAKE_UC_FW_PATH.(Daniele)
- Squash all firmware update patches (Daniele)
v3: s/huc/HuC
- Correct the order of platforms
- Change REVID of cml to 5(Michal)
- Code space changes in huc_def (Daniele)

Suggested-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 27 
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 296a82603be0..ea9a807abd4f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -39,26 +39,27 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * Must be ordered based on platform + revid, from newer to older.
  */
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
-   fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9,  0,
0)) \
-   fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  8,  4, 
3238)) \
-   fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
-   fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 
2893)) \
-   fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
-   fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01,  8, 
2893)) \
-   fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 
1398))
-
-#define __MAKE_UC_FW_PATH(prefix_, name_, separator_, major_, minor_, patch_) \
+   fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9, 0, 0)) \
+   fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  9, 0, 0)) \
+   fw_def(COFFEELAKE,  5, guc_def(cml, 33, 0, 0), huc_def(cml,  4, 0, 0)) \
+   fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4, 0, 0)) \
+   fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk,  4, 0, 0)) \
+   fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4, 0, 0)) \
+   fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt,  2, 0, 0)) \
+   fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl,  2, 0, 0))
+
+#define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \
"i915/" \
__stringify(prefix_) name_ \
-   __stringify(major_) separator_ \
-   __stringify(minor_) separator_ \
+   __stringify(major_) "." \
+   __stringify(minor_) "." \
__stringify(patch_) ".bin"
 
 #define MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_) \
-   __MAKE_UC_FW_PATH(prefix_, "_guc_", ".", major_, minor_, patch_)
+   __MAKE_UC_FW_PATH(prefix_, "_guc_", major_, minor_, patch_)
 
 #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \
-   __MAKE_UC_FW_PATH(prefix_, "_huc_ver", "_", major_, minor_, bld_num_)
+   __MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_)
 
 /* All blobs need to be declared via MODULE_FIRMWARE() */
 #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
-- 
2.23.0

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[Intel-gfx] [PATCH 2/2] HAX: force enable_guc=2

[Anusha Srivatsa]

Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -54,7 +54,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
+   param(int, enable_guc, 2) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.23.0

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[Intel-gfx] i915 firmware updates - PR for CML guc,huc; TGL DMC and Gen9-Gen11 HuC Updates

[Srivatsa, Anusha]

Josh,Kyle,Ben

Can these i915 updates be merged from cml_tgldmc_huc_updates to linux-firmware

The following changes since commit 44d4fca9922a252a0bd81f6307bcc072a78da54a:

  Merge https://github.com/pmachata/linux-firmware (2018-09-13 11:45:40 -0400)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-firmware cml_tgldmc_huc_updates

for you to fetch changes up to e848f4708bcea2fa829cfbfd7e7a1b3a83b91d3e:

  drm/i915/firmware: Add v9.0.0 of HuC for Icelake (2019-09-11 15:46:03 -0700)


Anusha Srivatsa (8):
  drm/i915/firmware: Add v2.04 of DMC for TGL
  drm/i915/firmware: Add v33 of GuC for CML
  drm/i915/firmware: Add v2.0.0 of HuC for Skylake
  drm/i915/firmware: Add v4.0.0 of HuC for Kabylake
  drm/i915/firmware: Add v2.0.0 of HuC for Broxton
  drm/i915/firmware: Add v4.0.0 of HuC for Geminilake
  drm/i915/firmware: Add v4.0.0 of HuC for Cometlake
  drm/i915/firmware: Add v9.0.0 of HuC for Icelake

 WHENCE   |  26 ++
 i915/bxt_huc_2.0.0.bin   | Bin 0 -> 149824 bytes
 i915/cml_guc_33.0.0.bin  | Bin 0 -> 182912 bytes
 i915/cml_huc_4.0.0.bin   | Bin 0 -> 226048 bytes
 i915/glk_huc_4.0.0.bin   | Bin 0 -> 226048 bytes
 i915/icl_huc_9.0.0.bin   | Bin 0 -> 498880 bytes
 i915/kbl_huc_4.0.0.bin   | Bin 0 -> 226048 bytes
 i915/skl_huc_2.0.0.bin   | Bin 0 -> 136320 bytes
 i915/tgl_dmc_ver2_04.bin | Bin 0 -> 18436 bytes
 9 files changed, 26 insertions(+)
 create mode 100644 i915/bxt_huc_2.0.0.bin
 create mode 100644 i915/cml_guc_33.0.0.bin
 create mode 100644 i915/cml_huc_4.0.0.bin
 create mode 100644 i915/glk_huc_4.0.0.bin
 create mode 100644 i915/icl_huc_9.0.0.bin
 create mode 100644 i915/kbl_huc_4.0.0.bin
 create mode 100644 i915/skl_huc_2.0.0.bin
 create mode 100644 i915/tgl_dmc_ver2_04.bin

Anusha
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[Intel-gfx] [PATCH] drm/i915/dmc: Update ICL DMC version to v1.09

[Anusha Srivatsa]

We have a new version of DMC for ICL - v1.09.

This version adds the Half Refresh Rate capability
into DMC.

Cc: José Roberto de Souza 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/intel_csr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 546577e39b4e..09870a31b4f0 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -44,8 +44,8 @@
 #define TGL_CSR_MAX_FW_SIZE0x6000
 MODULE_FIRMWARE(TGL_CSR_PATH);
 
-#define ICL_CSR_PATH   "i915/icl_dmc_ver1_07.bin"
-#define ICL_CSR_VERSION_REQUIRED   CSR_VERSION(1, 7)
+#define ICL_CSR_PATH   "i915/icl_dmc_ver1_09.bin"
+#define ICL_CSR_VERSION_REQUIRED   CSR_VERSION(1, 9)
 #define ICL_CSR_MAX_FW_SIZE0x6000
 MODULE_FIRMWARE(ICL_CSR_PATH);
 
-- 
2.23.0

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[Intel-gfx] [PATCH 1/2] drm/i915/uc: Update GuC and HuC firmware naming convention

[Anusha Srivatsa]

Make both GuC and HuC to use "." as the separator. Hardcode
the separator in MAKE_UC_FW_PATH. Remove the usage of "ver" from HuC.

The current convention being:
_uc_..patch.bin

Update the versions of HuC being loaded of the platforms.

SKL - v2.0.0
BXT - v2.0.0
KBL - v4.0.0
GLK - v4.0.0
CFL - KBL v4.0.0
ICL - v9.0.0
CML - v4.0.0

v2: Remove the separator parameter altogether from
__MAKE_UC_FW_PATH.(Daniele)
- Squash all firmware update patches (Daniele)
v3: s/huc/HuC
- Correct the order of platforms
- Change REVID of cml to 5(Michal)
- Code space changes in huc_def (Daniele)

Suggested-by: Daniele Ceraolo Spurio 
Cc: Michal Wajdeczko 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 27 
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 296a82603be0..ea9a807abd4f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -39,26 +39,27 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * Must be ordered based on platform + revid, from newer to older.
  */
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
-   fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9,  0,
0)) \
-   fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  8,  4, 
3238)) \
-   fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
-   fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 
2893)) \
-   fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
-   fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01,  8, 
2893)) \
-   fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 
1398))
-
-#define __MAKE_UC_FW_PATH(prefix_, name_, separator_, major_, minor_, patch_) \
+   fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9, 0, 0)) \
+   fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  9, 0, 0)) \
+   fw_def(COFFEELAKE,  5, guc_def(cml, 33, 0, 0), huc_def(cml,  4, 0, 0)) \
+   fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4, 0, 0)) \
+   fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk,  4, 0, 0)) \
+   fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4, 0, 0)) \
+   fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt,  2, 0, 0)) \
+   fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl,  2, 0, 0))
+
+#define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \
"i915/" \
__stringify(prefix_) name_ \
-   __stringify(major_) separator_ \
-   __stringify(minor_) separator_ \
+   __stringify(major_) "." \
+   __stringify(minor_) "." \
__stringify(patch_) ".bin"
 
 #define MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_) \
-   __MAKE_UC_FW_PATH(prefix_, "_guc_", ".", major_, minor_, patch_)
+   __MAKE_UC_FW_PATH(prefix_, "_guc_", major_, minor_, patch_)
 
 #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \
-   __MAKE_UC_FW_PATH(prefix_, "_huc_ver", "_", major_, minor_, bld_num_)
+   __MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_)
 
 /* All blobs need to be declared via MODULE_FIRMWARE() */
 #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
-- 
2.23.0

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[Intel-gfx] [PATCH 2/2] HAX: force enable_guc=2

[Anusha Srivatsa]

Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -54,7 +54,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
+   param(int, enable_guc, 2) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.23.0

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[Intel-gfx] [PATCH 0/2] HuC Updates

[Anusha Srivatsa]

The following changes since commit 6c6918ad8ae0dfb2cb591484eba525409980c16f:

  linux-firmware: Update firmware file for Intel Bluetooth AX201 (2019-09-09 
04:22:42 -0400)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-firmware ehl_huc

for you to fetch changes up to 44a6d7e577ca3df16d804c560de16cb8483c4306:

  i915: Add HuC firmware v9.0.0 for EHL (2019-09-09 12:19:42 -0700)


Daniele Ceraolo Spurio (1):
  i915: Add HuC firmware v9.0.0 for EHL

 WHENCE |   3 +++
 i915/ehl_huc_9.0.0.bin | Bin 0 -> 498880 bytes
 2 files changed, 3 insertions(+)
 create mode 100644 i915/ehl_huc_9.0.0.bin


Anusha Srivatsa (2):
  drm/i915/uc: Update GuC and HuC firmware naming convention
  HAX: force enable_guc=2

 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 27 
 drivers/gpu/drm/i915/i915_params.h   |  2 +-
 2 files changed, 15 insertions(+), 14 deletions(-)

-- 
2.23.0

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Re: [Intel-gfx] [PATCH 1/2] drm/i915/uc: Update MAKE_HUC_FW_PATH macro

[Srivatsa, Anusha]

> -Original Message-
> From: Ceraolo Spurio, Daniele
> Sent: Tuesday, September 10, 2019 2:05 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH 1/2] drm/i915/uc: Update MAKE_HUC_FW_PATH macro
> 
> 
> 
> On 9/9/19 12:28 PM, Anusha Srivatsa wrote:
> > Update MAKE_HUC_FW_PATH macro to follow the same convention as the
> > MAKE_GUC_FW_PATH with the separator changing from "_" to "."
> > and removing "ver".
> >
> > The current convention being:
> > _uc_..patch.bin
> >
> > Update the versions of huc being loaded of the platforms.
> >
> > SKL - v2.0.0
> > BXT - v2.0.0
> > KBL - v4.0.0
> > GLK - v4.0.0
> > CFL - KBL v4.0.0
> > ICL - v9.0.0
> > CML - v4.0.0
> >
> > v2: Remove the separator parameter altogether from
> > __MAKE_UC_FW_PATH.(Daniele)
> > - Squash all firmware update patches (Daniele)
> >
> > Suggested-by: Daniele Ceraolo Spurio 
> > Signed-off-by: Anusha Srivatsa 
> > ---
> >   drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 25 
> >   1 file changed, 13 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> > index 296a82603be0..da4bf24368bd 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> > @@ -40,25 +40,26 @@ void intel_uc_fw_change_status(struct intel_uc_fw
> *uc_fw,
> >*/
> >   #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
> > fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9,  0,
> > 0))
> \
> > -   fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  8,  4, 
> > 3238)) \
> > -   fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00,
> 1810)) \
> > -   fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01,
> 2893)) \
> > -   fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
> > 1810))
> \
> > -   fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01,  8,
> 2893)) \
> > -   fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 
> > 1398))
> > -
> > -#define __MAKE_UC_FW_PATH(prefix_, name_, separator_, major_, minor_,
> > patch_) \
> > +   fw_def(COFFEELAKE,  0, guc_def(cml, 33, 0, 0), huc_def(cml,  4,  0,
> > 0))
> \
> > +   fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  9,  0,
> > 0)) \
> > +   fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4,  0,
> > 0)) \
> > +   fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk,  4,  0,
> > 0)) \
> > +   fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4,  0,
> > 0)) \
> > +   fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt,  2,  0,
> > 0)) \
> > +   fw_def(SKYLAKE,     0, guc_def(skl, 33, 0, 0), huc_def(skl,  2,  0,
> > 0))
> 
> In addition to what Michal pointed out, while we're at it you can also get 
> rid of
> all the extra spaces in the huc_def() column since we've now standardized the
> length of the items like we did with GuC. Maybe just leave an extra space for 
> the
> major, since we're close to hitting v10?

Regarding that, do we still want 4 spaces for HuC build number? 
And 2 spaces for minor?

Anusha 
> Daniele
> 
> > +
> > +#define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \
> > "i915/" \
> > __stringify(prefix_) name_ \
> > -   __stringify(major_) separator_ \
> > -   __stringify(minor_) separator_ \
> > +   __stringify(major_) "." \
> > +   __stringify(minor_) "." \
> > __stringify(patch_) ".bin"
> >
> >   #define MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_) \
> > -   __MAKE_UC_FW_PATH(prefix_, "_guc_", ".", major_, minor_, patch_)
> > +   __MAKE_UC_FW_PATH(prefix_, "_guc_", major_, minor_, patch_)
> >
> >   #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \
> > -   __MAKE_UC_FW_PATH(prefix_, "_huc_ver", "_", major_, minor_,
> bld_num_)
> > +   __MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_)
> >
> >   /* All blobs need to be declared via MODULE_FIRMWARE() */
> >   #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
> >
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[Intel-gfx] [PATCH 1/2] drm/i915/uc: Update MAKE_HUC_FW_PATH macro

[Anusha Srivatsa]

Update MAKE_HUC_FW_PATH macro to follow the same convention
as the MAKE_GUC_FW_PATH with the separator changing from "_" to "."
and removing "ver".

The current convention being:
_uc_..patch.bin

Update the versions of huc being loaded of the platforms.

SKL - v2.0.0
BXT - v2.0.0
KBL - v4.0.0
GLK - v4.0.0
CFL - KBL v4.0.0
ICL - v9.0.0
CML - v4.0.0

v2: Remove the separator parameter altogether from
__MAKE_UC_FW_PATH.(Daniele)
- Squash all firmware update patches (Daniele)

Suggested-by: Daniele Ceraolo Spurio 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 25 
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 296a82603be0..da4bf24368bd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -40,25 +40,26 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  */
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9,  0,
0)) \
-   fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  8,  4, 
3238)) \
-   fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
-   fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 
2893)) \
-   fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
-   fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01,  8, 
2893)) \
-   fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 
1398))
-
-#define __MAKE_UC_FW_PATH(prefix_, name_, separator_, major_, minor_, patch_) \
+   fw_def(COFFEELAKE,  0, guc_def(cml, 33, 0, 0), huc_def(cml,  4,  0,
0)) \
+   fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  9,  0,
0)) \
+   fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4,  0,
0)) \
+   fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk,  4,  0,
0)) \
+   fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4,  0,
0)) \
+   fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt,  2,  0,
0)) \
+   fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl,  2,  0,
0))
+
+#define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \
"i915/" \
__stringify(prefix_) name_ \
-   __stringify(major_) separator_ \
-   __stringify(minor_) separator_ \
+   __stringify(major_) "." \
+   __stringify(minor_) "." \
__stringify(patch_) ".bin"
 
 #define MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_) \
-   __MAKE_UC_FW_PATH(prefix_, "_guc_", ".", major_, minor_, patch_)
+   __MAKE_UC_FW_PATH(prefix_, "_guc_", major_, minor_, patch_)
 
 #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \
-   __MAKE_UC_FW_PATH(prefix_, "_huc_ver", "_", major_, minor_, bld_num_)
+   __MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_)
 
 /* All blobs need to be declared via MODULE_FIRMWARE() */
 #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
-- 
2.23.0

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[Intel-gfx] [PATCH 2/2] HAX: force enable_guc=2

[Anusha Srivatsa]

Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -54,7 +54,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
+   param(int, enable_guc, 2) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.23.0

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[Intel-gfx] [PATCH 0/2] HuC updates

[Anusha Srivatsa]

  linux-firmware: Update firmware file for Intel Bluetooth AX201 (2019-09-09 
04:22:42 -0400)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-firmware ehl_huc

for you to fetch changes up to 44a6d7e577ca3df16d804c560de16cb8483c4306:

  i915: Add HuC firmware v9.0.0 for EHL (2019-09-09 12:19:42 -0700)


Daniele Ceraolo Spurio (1):
  i915: Add HuC firmware v9.0.0 for EHL

 WHENCE |   3 +++
 i915/ehl_huc_9.0.0.bin | Bin 0 -> 498880 bytes
 2 files changed, 3 insertions(+)
 create mode 100644 i915/ehl_huc_9.0.0.bin
anusha@anusha:~/drm-firmware$ tsocks git push origin ehl_huc
Enumerating objects: 12, done.
Counting objects: 100% (12/12), done.
Delta compression using up to 4 threads
Compressing objects: 100% (8/8), done.
Writing objects: 100% (8/8), 153.31 KiB | 76.65 MiB/s, done.
Total 8 (delta 5), reused 1 (delta 0)
To ssh://git.freedesktop.org/git/drm/drm-firmware
 * [new branch]  ehl_huc -> ehl_huc

Anusha Srivatsa (2):
  drm/i915/uc: Update MAKE_HUC_FW_PATH macro
  HAX: force enable_guc=2

 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 25 
 drivers/gpu/drm/i915/i915_params.h   |  2 +-
 2 files changed, 14 insertions(+), 13 deletions(-)

-- 
2.23.0

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[Intel-gfx] [PATCH 0/9] HuC updates

[Anusha Srivatsa]

Updating HuC versions for gen9 and ICL platforms.
Also updating MAKE_HUC_FW_PATH.

From now on we can have same firmware name formats
for both guC and HuC.

Adding the new PR for the same:
The following changes since commit 6ddb9d9704e2171d91439c9c42c5965bf3863de8:

  Merge branch 'for-upstream' of git://git.chelsio.net/pub/git/linux-firmware 
(2019-09-04 07:13:26 -0400)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-firmware huc_updates

for you to fetch changes up to 02850d2cc1fe542b7f320cedc446cfefb92c083a:

  drm/i915/firmware: Add v9.0.0 of HuC for Icelake (2019-09-06 12:23:56 -0700)

--------
Anusha Srivatsa (6):
  drm/i915/firmware: Add v2.0.0 of HuC for Skylake
  drm/i915/firmware: Add v4.0.0 of HuC for Kabylake
  drm/i915/firmware: Add v2.0.0 of HuC for Broxton
  drm/i915/firmware: Add v4.0.0 of HuC for Geminilake
  drm/i915/firmware: Add v4.0.0 of HuC for Cometlake
  drm/i915/firmware: Add v9.0.0 of HuC for Icelake

 WHENCE |  19 +++
 i915/bxt_huc_2.0.0.bin | Bin 0 -> 149824 bytes
 i915/cml_huc_4.0.0.bin | Bin 0 -> 226048 bytes
 i915/glk_huc_4.0.0.bin | Bin 0 -> 226048 bytes
 i915/icl_huc_9.0.0.bin | Bin 0 -> 498880 bytes
 i915/kbl_huc_4.0.0.bin | Bin 0 -> 226048 bytes
 i915/skl_huc_2.0.0.bin | Bin 0 -> 136320 bytes
 7 files changed, 19 insertions(+)
 create mode 100644 i915/bxt_huc_2.0.0.bin
 create mode 100644 i915/cml_huc_4.0.0.bin
 create mode 100644 i915/glk_huc_4.0.0.bin
 create mode 100644 i915/icl_huc_9.0.0.bin
 create mode 100644 i915/kbl_huc_4.0.0.bin
 create mode 100644 i915/skl_huc_2.0.0.bin

Anusha Srivatsa (9):
  drm/i915/uc: Update MAKE_HUC_FW_PATH macro
  drm/i915/firmware: Load v2.0.0 HuC for SKL
  drm/i915/firmware: Load v2.0.0 HuC for BXT
  drm/i915/firmware: Load v4.0.0 HuC for KBL
  drm/i915/firmware: Load v4.0.0 HuC for GLK
  drm/i915/firmware: CFL uses KBL firmware
  drm/i915/firmware: Load v9.0.0 HuC for ICL
  drm/i915/firmware: Load v4.0.0 HuC for CML
  HAX: force enable_guc=2

 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 15 ---
 drivers/gpu/drm/i915/i915_params.h   |  2 +-
 2 files changed, 9 insertions(+), 8 deletions(-)

-- 
2.23.0

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[Intel-gfx] [PATCH 7/9] drm/i915/firmware: Load v9.0.0 HuC for ICL

[Anusha Srivatsa]

Add support to load the latest version of HuC on ICL.

Cc: Daniele Ceraolo Spurio 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 2614f36934e5..5994a41f47a8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -40,7 +40,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  */
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9,  0,
0)) \
-   fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  8,  4, 
3238)) \
+   fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  9,  0,
0)) \
fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4,  0,
0)) \
fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk,  4,  0,
0)) \
fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4,  0,
0)) \
-- 
2.23.0

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[Intel-gfx] [PATCH 1/9] drm/i915/uc: Update MAKE_HUC_FW_PATH macro

[Anusha Srivatsa]

Update MAKE_HUC_FW_PATH macro to follow the same convention
as the MAKE_GUC_FW_PATH with the separator changing from "_" to "."
and removing "ver".

The current convention being:
_uc_..patch.bin

Suggested-by: Daniele Ceraolo Spurio 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 296a82603be0..16a5aa8fe15a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -58,7 +58,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
__MAKE_UC_FW_PATH(prefix_, "_guc_", ".", major_, minor_, patch_)
 
 #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \
-   __MAKE_UC_FW_PATH(prefix_, "_huc_ver", "_", major_, minor_, bld_num_)
+   __MAKE_UC_FW_PATH(prefix_, "_huc_", ".", major_, minor_, bld_num_)
 
 /* All blobs need to be declared via MODULE_FIRMWARE() */
 #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
-- 
2.23.0

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[Intel-gfx] [PATCH 9/9] HAX: force enable_guc=2

[Anusha Srivatsa]

Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -54,7 +54,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
-   param(int, enable_guc, 0) \
+   param(int, enable_guc, 2) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
-- 
2.23.0

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[Intel-gfx] [PATCH 6/9] drm/i915/firmware: CFL uses KBL firmware

[Anusha Srivatsa]

Add support to load the latest version of HuC on CFL.

Cc: Daniele Ceraolo Spurio 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index d590358193e4..2614f36934e5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -41,7 +41,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9,  0,
0)) \
fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  8,  4, 
3238)) \
-   fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
+   fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4,  0,
0)) \
fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk,  4,  0,
0)) \
fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4,  0,
0)) \
fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt,  2,  0,
0)) \
-- 
2.23.0

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[Intel-gfx] [PATCH 4/9] drm/i915/firmware: Load v4.0.0 HuC for KBL

[Anusha Srivatsa]

Add support to load the latest version of HuC on KBL.

Cc: Daniele Ceraolo Spurio 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index ab8fcd3e46ca..c631f1f81930 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -43,7 +43,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl,  8,  4, 
3238)) \
fw_def(COFFEELAKE,  0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
fw_def(GEMINILAKE,  0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 
2893)) \
-   fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 
1810)) \
+   fw_def(KABYLAKE,0, guc_def(kbl, 33, 0, 0), huc_def(kbl,  4,  0,
0)) \
fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt,  2,  0,
0)) \
fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl,  2,  0,
0))
 
-- 
2.23.0

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