Re: [Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines

2023-06-20 Thread Srivatsa, Anusha 



> -Original Message-
> From: Intel-gfx  On Behalf Of Jani
> Nikula
> Sent: Monday, June 19, 2023 1:46 AM
> To: Bhadane, Dnyaneshwar ; intel-
> g...@lists.freedesktop.org
> Cc: Bhadane, Dnyaneshwar 
> Subject: Re: [Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for
> platform/subplatform defines
> 
> On Thu, 15 Jun 2023, Dnyaneshwar Bhadane
>  wrote:
> > Follow consistent naming convention. Replace JSL with JASPERLAKE.
> >
> > Signed-off-by: Dnyaneshwar Bhadane 
> 
> > -#define IS_JSL_EHL(i915)   (IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
> > +#define IS_JASPERLAKE_EHL(i915)(IS_PLATFORM(i915,
> INTEL_JASPERLAKE) || \
> > IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
> 
> The new name for this is just dumb. This matches two platforms, JSL and EHL,
> and there's no point in one of them being an acronym and the other one not.
> 
> And IS_JASPERLAKE_ELKHARTLAKE() would be too long.
> 
Agreed on the long name.
Given that we are not touching Elkhartlake in this series, we can probably skip 
jasperlake too?

Anusha
> BR,
> Jani.
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines

2023-06-19 Thread Jani Nikula 
On Thu, 15 Jun 2023, Dnyaneshwar Bhadane  wrote:
> Follow consistent naming convention. Replace JSL with
> JASPERLAKE.
>
> Signed-off-by: Dnyaneshwar Bhadane 

> -#define IS_JSL_EHL(i915) (IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
> +#define IS_JASPERLAKE_EHL(i915)  (IS_PLATFORM(i915, INTEL_JASPERLAKE) || 
> \
>   IS_PLATFORM(i915, INTEL_ELKHARTLAKE))

The new name for this is just dumb. This matches two platforms, JSL and
EHL, and there's no point in one of them being an acronym and the other
one not.

And IS_JASPERLAKE_ELKHARTLAKE() would be too long.


BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 04/11] drm/i915/jsl: s/JSL/JASPERLAKE for platform/subplatform defines

2023-06-16 Thread Dnyaneshwar Bhadane 
Follow consistent naming convention. Replace JSL with
JASPERLAKE.

Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/icl_dsi.c |  4 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c |  4 ++--
 drivers/gpu/drm/i915/display/intel_combo_phy.c |  6 +++---
 drivers/gpu/drm/i915/display/intel_ddi.c   |  6 +++---
 drivers/gpu/drm/i915/display/intel_display.c   |  6 +++---
 drivers/gpu/drm/i915/display/intel_dp.c|  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c  | 18 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c   |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c|  2 +-
 drivers/gpu/drm/i915/i915_drv.h| 10 +-
 drivers/gpu/drm/i915/intel_step.c  |  2 +-
 drivers/gpu/drm/i915/soc/intel_pch.c   |  6 +++---
 15 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 59a2a289d9be..70f045da3bac 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -444,7 +444,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct 
intel_encoder *encoder)
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
-   if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
+   if (IS_JASPERLAKE_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 
12)) {
intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
 
@@ -553,7 +553,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
}
}
 
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE_EHL(dev_priv)) {
for_each_dsi_phy(phy, intel_dsi->phys)
intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4207863b7b2a..2acfa0435675 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3147,7 +3147,7 @@ static int intel_compute_max_dotclk(struct 
drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE_EHL(dev_priv)) {
if (dev_priv->display.cdclk.hw.ref == 24000)
dev_priv->display.cdclk.max_cdclk_freq = 552000;
else
@@ -3575,7 +3575,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
*dev_priv)
} else if (DISPLAY_VER(dev_priv) >= 12) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = icl_cdclk_table;
-   } else if (IS_JSL_EHL(dev_priv)) {
+   } else if (IS_JASPERLAKE_EHL(dev_priv)) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c 
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 922a6d87b553..37bd6d31ced1 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, 
enum phy phy)
 
if (IS_ALDERLAKE_S(i915))
return phy == PHY_A;
-   else if (IS_JSL_EHL(i915) ||
+   else if (IS_JASPERLAKE_EHL(i915) ||
 IS_ROCKETLAKE(i915) ||
 IS_DG1(i915))
return phy < PHY_C;
@@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct 
drm_i915_private *dev_priv,
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 IREFGEN, IREFGEN);
 
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE_EHL(dev_priv)) {
if (ehl_vbt_ddi_d_present(dev_priv))
expected_val = ICL_PHY_MISC_MUX_DDID;
 
@@ -333,7 +333,7 @@ static void icl_combo_phys_init(struct drm_i915_private 
*dev_priv)
 * "internal" child devices.
 */
val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
-   if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
+   if (IS_JASPERLAKE_EHL(dev_priv) && phy == PHY_A) {
val &= ~ICL_PHY_MISC_MUX_DDID;
 
if (ehl_vbt_ddi_d_present(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c

Re: [Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines

2023-06-15 Thread Srivatsa, Anusha 
Reviewed-by: Anusha Srivatsa 


> -Original Message-
> From: Bhadane, Dnyaneshwar 
> Sent: Wednesday, June 14, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S ; Srivatsa, Anusha
> ; Bhadane, Dnyaneshwar
> 
> Subject: [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for
> platform/subplatform defines
> 
> Follow consistent naming convention. Replace JSL with JASPERLAKE.
> 
> Signed-off-by: Dnyaneshwar Bhadane 
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c |  4 ++--
>  drivers/gpu/drm/i915/display/intel_cdclk.c |  4 ++--
>  drivers/gpu/drm/i915/display/intel_combo_phy.c |  6 +++---
>  drivers/gpu/drm/i915/display/intel_ddi.c   |  6 +++---
>  drivers/gpu/drm/i915/display/intel_display.c   |  6 +++---
>  drivers/gpu/drm/i915/display/intel_dp.c|  2 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c  | 18 +-
>  drivers/gpu/drm/i915/display/intel_hdmi.c  |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c   |  2 +-
>  drivers/gpu/drm/i915/gem/i915_gem_object.c |  2 +-
>  drivers/gpu/drm/i915/gt/intel_sseu.c   |  2 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.c|  2 +-
>  drivers/gpu/drm/i915/i915_drv.h| 10 +-
>  drivers/gpu/drm/i915/intel_step.c  |  2 +-
>  drivers/gpu/drm/i915/soc/intel_pch.c   |  6 +++---
>  15 files changed, 37 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 59a2a289d9be..70f045da3bac 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -444,7 +444,7 @@ static void
> gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
>   intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
> 
>   /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
> - if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
> + if (IS_JASPERLAKE_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >=
> 12)) {
>   intel_de_rmw(dev_priv,
> ICL_PORT_PCS_DW1_AUX(phy),
>LATENCY_OPTIM_MASK,
> LATENCY_OPTIM_VAL(0));
> 
> @@ -553,7 +553,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder
> *encoder,
>   }
>   }
> 
> - if (IS_JSL_EHL(dev_priv)) {
> + if (IS_JASPERLAKE_EHL(dev_priv)) {
>   for_each_dsi_phy(phy, intel_dsi->phys)
>   intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
>0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4207863b7b2a..2acfa0435675 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3147,7 +3147,7 @@ static int intel_compute_max_dotclk(struct
> drm_i915_private *dev_priv)
>   */
>  void intel_update_max_cdclk(struct drm_i915_private *dev_priv)  {
> - if (IS_JSL_EHL(dev_priv)) {
> + if (IS_JASPERLAKE_EHL(dev_priv)) {
>   if (dev_priv->display.cdclk.hw.ref == 24000)
>   dev_priv->display.cdclk.max_cdclk_freq = 552000;
>   else
> @@ -3575,7 +3575,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv)
>   } else if (DISPLAY_VER(dev_priv) >= 12) {
>   dev_priv->display.funcs.cdclk = _cdclk_funcs;
>   dev_priv->display.cdclk.table = icl_cdclk_table;
> - } else if (IS_JSL_EHL(dev_priv)) {
> + } else if (IS_JASPERLAKE_EHL(dev_priv)) {
>   dev_priv->display.funcs.cdclk = _cdclk_funcs;
>   dev_priv->display.cdclk.table = icl_cdclk_table;
>   } else if (DISPLAY_VER(dev_priv) >= 11) { diff --git
> a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 922a6d87b553..37bd6d31ced1 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private
> *i915, enum phy phy)
> 
>   if (IS_ALDERLAKE_S(i915))
>   return phy == PHY_A;
> - else if (IS_JSL_EHL(i915) ||
> + else if (IS_JASPERLAKE_EHL(i915) ||
>IS_ROCKETLAKE(i915) ||
>IS_DG1(i915))
>   return phy < PHY_C;
> @@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct
> drm_i915_private *dev_priv,
>   ret &= check_phy_reg(dev_priv, phy,
> ICL_PORT_COMP_DW8(phy),
>IREFGEN, IREFGEN);
> 
> - if (IS_JSL_EHL(dev_priv)) {
> + if (IS_JASPERLAKE_EHL(dev_priv)) {
>   if (ehl_vbt_ddi_d_present(dev_priv))
>   expected_val = ICL_PHY_MISC_MUX_DDID;
> 
> @@ -333,7 +333,7 @@ static void icl_combo_phys_init(struct drm_i915_private
> *dev_priv)
>

[Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines

2023-06-15 Thread Dnyaneshwar Bhadane 
Follow consistent naming convention. Replace JSL with
JASPERLAKE.

Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/icl_dsi.c |  4 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c |  4 ++--
 drivers/gpu/drm/i915/display/intel_combo_phy.c |  6 +++---
 drivers/gpu/drm/i915/display/intel_ddi.c   |  6 +++---
 drivers/gpu/drm/i915/display/intel_display.c   |  6 +++---
 drivers/gpu/drm/i915/display/intel_dp.c|  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c  | 18 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c   |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c|  2 +-
 drivers/gpu/drm/i915/i915_drv.h| 10 +-
 drivers/gpu/drm/i915/intel_step.c  |  2 +-
 drivers/gpu/drm/i915/soc/intel_pch.c   |  6 +++---
 15 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 59a2a289d9be..70f045da3bac 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -444,7 +444,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct 
intel_encoder *encoder)
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
-   if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
+   if (IS_JASPERLAKE_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 
12)) {
intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
 
@@ -553,7 +553,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
}
}
 
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE_EHL(dev_priv)) {
for_each_dsi_phy(phy, intel_dsi->phys)
intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4207863b7b2a..2acfa0435675 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3147,7 +3147,7 @@ static int intel_compute_max_dotclk(struct 
drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE_EHL(dev_priv)) {
if (dev_priv->display.cdclk.hw.ref == 24000)
dev_priv->display.cdclk.max_cdclk_freq = 552000;
else
@@ -3575,7 +3575,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
*dev_priv)
} else if (DISPLAY_VER(dev_priv) >= 12) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = icl_cdclk_table;
-   } else if (IS_JSL_EHL(dev_priv)) {
+   } else if (IS_JASPERLAKE_EHL(dev_priv)) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c 
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 922a6d87b553..37bd6d31ced1 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, 
enum phy phy)
 
if (IS_ALDERLAKE_S(i915))
return phy == PHY_A;
-   else if (IS_JSL_EHL(i915) ||
+   else if (IS_JASPERLAKE_EHL(i915) ||
 IS_ROCKETLAKE(i915) ||
 IS_DG1(i915))
return phy < PHY_C;
@@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct 
drm_i915_private *dev_priv,
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 IREFGEN, IREFGEN);
 
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE_EHL(dev_priv)) {
if (ehl_vbt_ddi_d_present(dev_priv))
expected_val = ICL_PHY_MISC_MUX_DDID;
 
@@ -333,7 +333,7 @@ static void icl_combo_phys_init(struct drm_i915_private 
*dev_priv)
 * "internal" child devices.
 */
val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
-   if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
+   if (IS_JASPERLAKE_EHL(dev_priv) && phy == PHY_A) {
val &= ~ICL_PHY_MISC_MUX_DDID;
 
if (ehl_vbt_ddi_d_present(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c

[Intel-gfx] [PATCH 04/11] drm/i915/JSL: s/JSL/JASPERLAKE for platform/subplatform defines

2023-06-14 Thread Dnyaneshwar Bhadane 
Follow consistent naming convention. Replace JSL with
JASPERLAKE.

Signed-off-by: Dnyaneshwar Bhadane 
---
 drivers/gpu/drm/i915/display/icl_dsi.c |  4 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c |  4 ++--
 drivers/gpu/drm/i915/display/intel_combo_phy.c |  6 +++---
 drivers/gpu/drm/i915/display/intel_ddi.c   |  6 +++---
 drivers/gpu/drm/i915/display/intel_display.c   |  6 +++---
 drivers/gpu/drm/i915/display/intel_dp.c|  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c  | 18 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c   |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_object.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.c   |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c|  2 +-
 drivers/gpu/drm/i915/i915_drv.h| 10 +-
 drivers/gpu/drm/i915/intel_step.c  |  2 +-
 drivers/gpu/drm/i915/soc/intel_pch.c   |  6 +++---
 15 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 59a2a289d9be..70f045da3bac 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -444,7 +444,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct 
intel_encoder *encoder)
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
-   if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
+   if (IS_JASPERLAKE_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 
12)) {
intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
 
@@ -553,7 +553,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
}
}
 
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE_EHL(dev_priv)) {
for_each_dsi_phy(phy, intel_dsi->phys)
intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4207863b7b2a..2acfa0435675 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3147,7 +3147,7 @@ static int intel_compute_max_dotclk(struct 
drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE_EHL(dev_priv)) {
if (dev_priv->display.cdclk.hw.ref == 24000)
dev_priv->display.cdclk.max_cdclk_freq = 552000;
else
@@ -3575,7 +3575,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
*dev_priv)
} else if (DISPLAY_VER(dev_priv) >= 12) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = icl_cdclk_table;
-   } else if (IS_JSL_EHL(dev_priv)) {
+   } else if (IS_JASPERLAKE_EHL(dev_priv)) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c 
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 922a6d87b553..37bd6d31ced1 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, 
enum phy phy)
 
if (IS_ALDERLAKE_S(i915))
return phy == PHY_A;
-   else if (IS_JSL_EHL(i915) ||
+   else if (IS_JASPERLAKE_EHL(i915) ||
 IS_ROCKETLAKE(i915) ||
 IS_DG1(i915))
return phy < PHY_C;
@@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct 
drm_i915_private *dev_priv,
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 IREFGEN, IREFGEN);
 
-   if (IS_JSL_EHL(dev_priv)) {
+   if (IS_JASPERLAKE_EHL(dev_priv)) {
if (ehl_vbt_ddi_d_present(dev_priv))
expected_val = ICL_PHY_MISC_MUX_DDID;
 
@@ -333,7 +333,7 @@ static void icl_combo_phys_init(struct drm_i915_private 
*dev_priv)
 * "internal" child devices.
 */
val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
-   if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
+   if (IS_JASPERLAKE_EHL(dev_priv) && phy == PHY_A) {
val &= ~ICL_PHY_MISC_MUX_DDID;
 
if (ehl_vbt_ddi_d_present(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c