Re: [Intel-gfx] [PATCH 1/2] drm/i915: Use a modparam to restrict exposed engines
On Tue, 2019-10-01 at 14:54 +0100, Chris Wilson wrote:
> Allow the user to restrict the available set of engines via a module
> parameter.
>
> Signed-off-by: Chris Wilson
> Cc: Stuart Summers
> Cc: Andi Shyti
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
> Cc: Joonas Lahtinen
> Cc: Martin Peres
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 -
> --
> drivers/gpu/drm/i915/i915_gem.c | 5
> drivers/gpu/drm/i915/i915_params.c| 4 +++
> drivers/gpu/drm/i915/i915_params.h| 1 +
> 4 files changed, 35 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 80fd072ac719..690da64ec256 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -389,6 +389,29 @@ void intel_engines_cleanup(struct
> drm_i915_private *i915)
> }
> }
>
> +static bool engine_available(struct drm_i915_private *i915, int id)
> +{
> + /* uAPI -- modparam bits must be consistent between kernels */
> + static const unsigned int param_bit[] = {
> + [RCS0] = BIT(0),
> + [VCS0] = BIT(1),
> + [BCS0] = BIT(2),
> + [VECS0] = BIT(3),
> + [VCS1] = BIT(4),
> + [VCS2] = BIT(5),
> + [VCS3] = BIT(6),
> + [VECS1] = BIT(7),
> + };
To be a little controversial here... I don't see how this is better
than just matching to our currently available engines for the platform.
The user will still need to look in the code to determine what engines
are available. I understand this restricts us to a static module
parameter across kernel revisions, but at the same time, this will add
a maintenance burden for an unsafe feature, something not used
regularly. And it seems like this will be easy to get stale over time.
> +
> + if (!HAS_ENGINE(i915, id))
> + return false;
> +
> + if (!(i915_modparams.engines & param_bit[id]))
> + return false;
> +
> + return true;
> +}
> +
> /**
> * intel_engines_init_mmio() - allocate and prepare the Engine
> Command Streamers
> * @i915: the i915 device
> @@ -397,7 +420,6 @@ void intel_engines_cleanup(struct
> drm_i915_private *i915)
> */
> int intel_engines_init_mmio(struct drm_i915_private *i915)
> {
> - struct intel_device_info *device_info =
> mkwrite_device_info(i915);
> const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;
> unsigned int mask = 0;
> unsigned int i;
> @@ -411,7 +433,7 @@ int intel_engines_init_mmio(struct
> drm_i915_private *i915)
> return -ENODEV;
>
> for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
> - if (!HAS_ENGINE(i915, i))
> + if (!engine_available(i915, i))
> continue;
>
> err = intel_engine_setup(>gt, i);
> @@ -421,14 +443,7 @@ int intel_engines_init_mmio(struct
> drm_i915_private *i915)
> mask |= BIT(i);
> }
>
> - /*
> - * Catch failures to update intel_engines table when the new
> engines
> - * are added to the driver by a warning and disabling the
> forgotten
> - * engines.
> - */
> - if (WARN_ON(mask != engine_mask))
> - device_info->engine_mask = mask;
> -
> + mkwrite_device_info(i915)->engine_mask = mask;
> RUNTIME_INFO(i915)->num_engines = hweight32(mask);
>
> intel_gt_check_and_clear_faults(>gt);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c
> b/drivers/gpu/drm/i915/i915_gem.c
> index 3d3fda4cae99..bb25731466a9 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1308,6 +1308,11 @@ int i915_gem_init(struct drm_i915_private
> *dev_priv)
> {
> int ret;
>
> + if (!RUNTIME_INFO(dev_priv)->num_engines) {
> + intel_gt_set_wedged_on_init(_priv->gt);
> + return 0;
> + }
Wait, why do we want to force a wedge if no engines are present? This
seems like an intentional limitation if we get to this point, so it
doesn't seem necessary to me to force this.
> +
> /* We need to fallback to 4K pages if host doesn't support huge
> gtt. */
> if (intel_vgpu_active(dev_priv) &&
> !intel_vgpu_has_huge_gtt(dev_priv))
> mkwrite_device_info(dev_priv)->page_sizes =
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index 296452f9efe4..27813bd79aa8 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -44,6 +44,10 @@ i915_param_named(modeset, int, 0400,
> "Use kernel modesetting [KMS] (0=disable, "
> "1=on, -1=force vga console preference [default])");
>
> +i915_param_named(engines, uint, 0400,
> + "Only expose selected command streamers [GPU engines]
> (0=disable GPU, "
> + "-1/0x enable all [default]). Each bit corresponds to a
> different
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Use a modparam to restrict exposed engines
Quoting Andi Shyti (2019-10-05 11:10:45)
> Hi Chris,
>
> On Tue, Oct 01, 2019 at 02:54:02PM +0100, Chris Wilson wrote:
> > Allow the user to restrict the available set of engines via a module
> > parameter.
>
> what is the driving reason for wanting this? Could you explain it
> in the commit log?
It's to allow the user to restrict the available set of engines, for
whatever reason they may have, presumably because they want to work
around some HW stability (or if that is the case to enable some HW
despite instability, since we should err on the side of caution).
> It feels a bit confusing, though. You are actually making a
> difference between engines we don't have and engines we don't
> want, and I don't see why.
>
> Wouldn't it make sense to either
>
> - define a new architecture (which could make things more
>confusing).
No, it's an optional overlay of an existing under the whim of the user.
> or
>
> - have it specified in kernel configuration
Is how we configure the defaults in reduced configurations.
> > Signed-off-by: Chris Wilson
> > Cc: Stuart Summers
> > Cc: Andi Shyti
> > Cc: Mika Kuoppala
> > Cc: Tvrtko Ursulin
> > Cc: Joonas Lahtinen
> > Cc: Martin Peres
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 ---
> > drivers/gpu/drm/i915/i915_gem.c | 5
> > drivers/gpu/drm/i915/i915_params.c| 4 +++
> > drivers/gpu/drm/i915/i915_params.h| 1 +
> > 4 files changed, 35 insertions(+), 10 deletions(-)
>
> Because this is a module option that is set by the user, I don't
> see any documentation about it.
It's in i915_params.c
> > +static bool engine_available(struct drm_i915_private *i915, int id)
> > +{
> > + /* uAPI -- modparam bits must be consistent between kernels */
> > + static const unsigned int param_bit[] = {
> > + [RCS0] = BIT(0),
> > + [VCS0] = BIT(1),
> > + [BCS0] = BIT(2),
> > + [VECS0] = BIT(3),
> > + [VCS1] = BIT(4),
> > + [VCS2] = BIT(5),
> > + [VCS3] = BIT(6),
> > + [VECS1] = BIT(7),
> > + };
>
> Yet another way to refer to engines... this time inside a static
> function, without any visibility outside.
Sure. It's a static mapping table that has to stable for generations to
come because it is described in i915_params as part of the i915.engines
contract.
-Chris
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Use a modparam to restrict exposed engines
Hi Chris,
On Tue, Oct 01, 2019 at 02:54:02PM +0100, Chris Wilson wrote:
> Allow the user to restrict the available set of engines via a module
> parameter.
what is the driving reason for wanting this? Could you explain it
in the commit log?
It feels a bit confusing, though. You are actually making a
difference between engines we don't have and engines we don't
want, and I don't see why.
Wouldn't it make sense to either
- define a new architecture (which could make things more
confusing).
or
- have it specified in kernel configuration
> Signed-off-by: Chris Wilson
> Cc: Stuart Summers
> Cc: Andi Shyti
> Cc: Mika Kuoppala
> Cc: Tvrtko Ursulin
> Cc: Joonas Lahtinen
> Cc: Martin Peres
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 ---
> drivers/gpu/drm/i915/i915_gem.c | 5
> drivers/gpu/drm/i915/i915_params.c| 4 +++
> drivers/gpu/drm/i915/i915_params.h| 1 +
> 4 files changed, 35 insertions(+), 10 deletions(-)
Because this is a module option that is set by the user, I don't
see any documentation about it.
> +static bool engine_available(struct drm_i915_private *i915, int id)
> +{
> + /* uAPI -- modparam bits must be consistent between kernels */
> + static const unsigned int param_bit[] = {
> + [RCS0] = BIT(0),
> + [VCS0] = BIT(1),
> + [BCS0] = BIT(2),
> + [VECS0] = BIT(3),
> + [VCS1] = BIT(4),
> + [VCS2] = BIT(5),
> + [VCS3] = BIT(6),
> + [VECS1] = BIT(7),
> + };
Yet another way to refer to engines... this time inside a static
function, without any visibility outside.
Andi
> +
> + if (!HAS_ENGINE(i915, id))
> + return false;
(engines we don't have...
> + if (!(i915_modparams.engines & param_bit[id]))
> + return false;
... engines we don't want)
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Use a modparam to restrict exposed engines
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc1 next-20191001]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Use-a-modparam-to-restrict-exposed-engines/20191002-003226
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a002-201939 (attached as .config)
compiler: gcc-5 (Ubuntu 5.5.0-12ubuntu1) 5.5.0 20171010
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/i915_gem.c: In function 'i915_gem_init':
>> drivers/gpu/drm/i915/i915_gem.c:1411:3: error: implicit declaration of
>> function 'intel_gt_set_wedged_on_init'
>> [-Werror=implicit-function-declaration]
intel_gt_set_wedged_on_init(_priv->gt);
^
cc1: some warnings being treated as errors
vim +/intel_gt_set_wedged_on_init +1411 drivers/gpu/drm/i915/i915_gem.c
1405
1406 int i915_gem_init(struct drm_i915_private *dev_priv)
1407 {
1408 int ret;
1409
1410 if (!RUNTIME_INFO(dev_priv)->num_engines) {
> 1411 intel_gt_set_wedged_on_init(_priv->gt);
1412 return 0;
1413 }
1414
1415 /* We need to fallback to 4K pages if host doesn't support huge
gtt. */
1416 if (intel_vgpu_active(dev_priv) &&
!intel_vgpu_has_huge_gtt(dev_priv))
1417 mkwrite_device_info(dev_priv)->page_sizes =
1418 I915_GTT_PAGE_SIZE_4K;
1419
1420 intel_timelines_init(dev_priv);
1421
1422 ret = i915_gem_init_userptr(dev_priv);
1423 if (ret)
1424 return ret;
1425
1426 intel_uc_fetch_firmwares(_priv->gt.uc);
1427 intel_wopcm_init(_priv->wopcm);
1428
1429 /* This is just a security blanket to placate dragons.
1430 * On some systems, we very sporadically observe that the first
TLBs
1431 * used by the CS may be stale, despite us poking the TLB
reset. If
1432 * we hold the forcewake during initialisation these problems
1433 * just magically go away.
1434 */
1435 mutex_lock(_priv->drm.struct_mutex);
1436 intel_uncore_forcewake_get(_priv->uncore, FORCEWAKE_ALL);
1437
1438 ret = i915_init_ggtt(dev_priv);
1439 if (ret) {
1440 GEM_BUG_ON(ret == -EIO);
1441 goto err_unlock;
1442 }
1443
1444 ret = i915_gem_init_scratch(dev_priv,
1445 IS_GEN(dev_priv, 2) ? SZ_256K :
PAGE_SIZE);
1446 if (ret) {
1447 GEM_BUG_ON(ret == -EIO);
1448 goto err_ggtt;
1449 }
1450
1451 ret = intel_engines_setup(dev_priv);
1452 if (ret) {
1453 GEM_BUG_ON(ret == -EIO);
1454 goto err_unlock;
1455 }
1456
1457 ret = i915_gem_contexts_init(dev_priv);
1458 if (ret) {
1459 GEM_BUG_ON(ret == -EIO);
1460 goto err_scratch;
1461 }
1462
1463 ret = intel_engines_init(dev_priv);
1464 if (ret) {
1465 GEM_BUG_ON(ret == -EIO);
1466 goto err_context;
1467 }
1468
1469 intel_init_gt_powersave(dev_priv);
1470
1471 intel_uc_init(_priv->gt.uc);
1472
1473 ret = i915_gem_init_hw(dev_priv);
1474 if (ret)
1475 goto err_uc_init;
1476
1477 /* Only when the HW is re-initialised, can we replay the
requests */
1478 ret = intel_gt_resume(_priv->gt);
1479 if (ret)
1480 goto err_init_hw;
1481
1482 /*
1483 * Despite its name intel_init_clock_gating applies both display
1484 * clock gating workarounds; GT mmio workarounds and the
occasional
1485 * GT power context workaround. Worse, sometimes it includes a
context
1486 * register workaround which we need to apply before we record
the
1487 * default HW state for all contexts.
1488 *
1489 * FIXME: break up the workarounds and apply them at the right
time!
1490 */
1491 intel_init_clock_gating(dev_priv);
1492
1493 ret = intel_engines_verify_workarounds(dev_priv);
1494 if (ret)
1495 goto err_gt;
1496
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Use a modparam to restrict exposed engines
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc1 next-20191001]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Use-a-modparam-to-restrict-exposed-engines/20191002-003226
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-13) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/i915_gem.c: In function 'i915_gem_init':
>> drivers/gpu/drm/i915/i915_gem.c:1411:3: error: implicit declaration of
>> function 'intel_gt_set_wedged_on_init'; did you mean 'intel_gt_set_wedged'?
>> [-Werror=implicit-function-declaration]
intel_gt_set_wedged_on_init(_priv->gt);
^~~
intel_gt_set_wedged
cc1: some warnings being treated as errors
vim +1411 drivers/gpu/drm/i915/i915_gem.c
1405
1406 int i915_gem_init(struct drm_i915_private *dev_priv)
1407 {
1408 int ret;
1409
1410 if (!RUNTIME_INFO(dev_priv)->num_engines) {
> 1411 intel_gt_set_wedged_on_init(_priv->gt);
1412 return 0;
1413 }
1414
1415 /* We need to fallback to 4K pages if host doesn't support huge
gtt. */
1416 if (intel_vgpu_active(dev_priv) &&
!intel_vgpu_has_huge_gtt(dev_priv))
1417 mkwrite_device_info(dev_priv)->page_sizes =
1418 I915_GTT_PAGE_SIZE_4K;
1419
1420 intel_timelines_init(dev_priv);
1421
1422 ret = i915_gem_init_userptr(dev_priv);
1423 if (ret)
1424 return ret;
1425
1426 intel_uc_fetch_firmwares(_priv->gt.uc);
1427 intel_wopcm_init(_priv->wopcm);
1428
1429 /* This is just a security blanket to placate dragons.
1430 * On some systems, we very sporadically observe that the first
TLBs
1431 * used by the CS may be stale, despite us poking the TLB
reset. If
1432 * we hold the forcewake during initialisation these problems
1433 * just magically go away.
1434 */
1435 mutex_lock(_priv->drm.struct_mutex);
1436 intel_uncore_forcewake_get(_priv->uncore, FORCEWAKE_ALL);
1437
1438 ret = i915_init_ggtt(dev_priv);
1439 if (ret) {
1440 GEM_BUG_ON(ret == -EIO);
1441 goto err_unlock;
1442 }
1443
1444 ret = i915_gem_init_scratch(dev_priv,
1445 IS_GEN(dev_priv, 2) ? SZ_256K :
PAGE_SIZE);
1446 if (ret) {
1447 GEM_BUG_ON(ret == -EIO);
1448 goto err_ggtt;
1449 }
1450
1451 ret = intel_engines_setup(dev_priv);
1452 if (ret) {
1453 GEM_BUG_ON(ret == -EIO);
1454 goto err_unlock;
1455 }
1456
1457 ret = i915_gem_contexts_init(dev_priv);
1458 if (ret) {
1459 GEM_BUG_ON(ret == -EIO);
1460 goto err_scratch;
1461 }
1462
1463 ret = intel_engines_init(dev_priv);
1464 if (ret) {
1465 GEM_BUG_ON(ret == -EIO);
1466 goto err_context;
1467 }
1468
1469 intel_init_gt_powersave(dev_priv);
1470
1471 intel_uc_init(_priv->gt.uc);
1472
1473 ret = i915_gem_init_hw(dev_priv);
1474 if (ret)
1475 goto err_uc_init;
1476
1477 /* Only when the HW is re-initialised, can we replay the
requests */
1478 ret = intel_gt_resume(_priv->gt);
1479 if (ret)
1480 goto err_init_hw;
1481
1482 /*
1483 * Despite its name intel_init_clock_gating applies both display
1484 * clock gating workarounds; GT mmio workarounds and the
occasional
1485 * GT power context workaround. Worse, sometimes it includes a
context
1486 * register workaround which we need to apply before we record
the
1487 * default HW state for all contexts.
1488 *
1489 * FIXME: break up the workarounds and apply them at the right
time!
1490 */
1491 intel_init_clock_gating(dev_priv);
1492
1493 ret = intel_engines_verify_workarounds(dev_priv);
1494 if (ret)
1495
[Intel-gfx] [PATCH 1/2] drm/i915: Use a modparam to restrict exposed engines
Allow the user to restrict the available set of engines via a module
parameter.
Signed-off-by: Chris Wilson
Cc: Stuart Summers
Cc: Andi Shyti
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Martin Peres
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 ---
drivers/gpu/drm/i915/i915_gem.c | 5
drivers/gpu/drm/i915/i915_params.c| 4 +++
drivers/gpu/drm/i915/i915_params.h| 1 +
4 files changed, 35 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 80fd072ac719..690da64ec256 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -389,6 +389,29 @@ void intel_engines_cleanup(struct drm_i915_private *i915)
}
}
+static bool engine_available(struct drm_i915_private *i915, int id)
+{
+ /* uAPI -- modparam bits must be consistent between kernels */
+ static const unsigned int param_bit[] = {
+ [RCS0] = BIT(0),
+ [VCS0] = BIT(1),
+ [BCS0] = BIT(2),
+ [VECS0] = BIT(3),
+ [VCS1] = BIT(4),
+ [VCS2] = BIT(5),
+ [VCS3] = BIT(6),
+ [VECS1] = BIT(7),
+ };
+
+ if (!HAS_ENGINE(i915, id))
+ return false;
+
+ if (!(i915_modparams.engines & param_bit[id]))
+ return false;
+
+ return true;
+}
+
/**
* intel_engines_init_mmio() - allocate and prepare the Engine Command
Streamers
* @i915: the i915 device
@@ -397,7 +420,6 @@ void intel_engines_cleanup(struct drm_i915_private *i915)
*/
int intel_engines_init_mmio(struct drm_i915_private *i915)
{
- struct intel_device_info *device_info = mkwrite_device_info(i915);
const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;
unsigned int mask = 0;
unsigned int i;
@@ -411,7 +433,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
return -ENODEV;
for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
- if (!HAS_ENGINE(i915, i))
+ if (!engine_available(i915, i))
continue;
err = intel_engine_setup(>gt, i);
@@ -421,14 +443,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
mask |= BIT(i);
}
- /*
-* Catch failures to update intel_engines table when the new engines
-* are added to the driver by a warning and disabling the forgotten
-* engines.
-*/
- if (WARN_ON(mask != engine_mask))
- device_info->engine_mask = mask;
-
+ mkwrite_device_info(i915)->engine_mask = mask;
RUNTIME_INFO(i915)->num_engines = hweight32(mask);
intel_gt_check_and_clear_faults(>gt);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3d3fda4cae99..bb25731466a9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1308,6 +1308,11 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
{
int ret;
+ if (!RUNTIME_INFO(dev_priv)->num_engines) {
+ intel_gt_set_wedged_on_init(_priv->gt);
+ return 0;
+ }
+
/* We need to fallback to 4K pages if host doesn't support huge gtt. */
if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
mkwrite_device_info(dev_priv)->page_sizes =
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..27813bd79aa8 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -44,6 +44,10 @@ i915_param_named(modeset, int, 0400,
"Use kernel modesetting [KMS] (0=disable, "
"1=on, -1=force vga console preference [default])");
+i915_param_named(engines, uint, 0400,
+ "Only expose selected command streamers [GPU engines] (0=disable GPU, "
+ "-1/0x enable all [default]). Each bit corresponds to a
different phyiscal engine: 0=RCS0, 1=VCS0, 2=BCS0, 3=VECS0, 4=VCS1, 5=VCS2,
6=VCS3, 7=VECS1");
+
i915_param_named_unsafe(enable_dc, int, 0400,
"Enable power-saving display C-states. "
"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f876db78a59a 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -45,6 +45,7 @@ struct drm_printer;
#define I915_PARAMS_FOR_EACH(param) \
param(char *, vbt_firmware, NULL) \
param(int, modeset, -1) \
+ param(unsigned int, engines, -1) \
param(int, lvds_channel_mode, 0) \
param(int, panel_use_ssc, -1) \
param(int, vbt_sdvo_panel_type, -1) \
--
2.23.0
___
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