Re: [Intel-gfx] [PROBLEM FOUND] Problem No HDMI when AV/TV in standby mode
An update on this issue. The registers VSYNCSHIFT PIPEACONF and TRANSACONF are been set to interlace mode at GRUB startup. Test: Boot computer with AV/TV in standby.Force GRUB to show menu selection.Turn on AV/TV and select PC HDMI while in GRUB menu.GRUB shows up with 1080i 50hz. So is it GRUB setting the mode or the BIOS? This may happen to me since my AV is telling via EDID that the preferred mode is interlaced? -- Paulo Louro > Date: Tue, 24 Jan 2012 23:28:36 +0100 > From: dan...@ffwll.ch > To: paulo_lo...@msn.com > CC: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PROBLEM FOUND] Problem No HDMI when AV/TV in > standby mode > > On Tue, Jan 24, 2012 at 10:03:57PM +, paulo louro wrote: > > > > Very ugly hack, > > In file ---> intel_display.c function --- > > > ironlake_crtc_mode_set > > temp = I915_READ(_TRANSACONF); I915_WRITE(_TRANSACONF, temp & > > ~(7<<21)); > > I915_WRITE( 0x60028, 0x); //VSYNCSHIFT_A— Vertical Sync Shift > > Register This register needs to be 0x for progressive mode > > I915_WRITE(PIPECONF(pipe), pipeconf); POSTING_READ(PIPECONF(pipe)); > > In file ---> i915_reg.h #define > > PIPECONF_INTERLACE_W_FIELD_INDICATION(7 << 21) // ( 6 << 21) > > Not sure why the PIPECONF MASK is 110 and not 111, from intel pdf 000b > > Progressive Fetch / Progressive display / 001b PF-ID Progressive Fetch / > > Interlaced display (HDMI) Requires panel fitting to be enabled > > Wohoo, this is awesome. Can you maybe go right ahead and create a patch > for this? Should be nothing more than checking for an interlaced mode and > banging the right values into these registers ... > > Yours, Daniel > -- > Daniel Vetter > Mail: dan...@ffwll.ch > Mobile: +41 (0)79 365 57 48 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PROBLEM FOUND] Problem No HDMI when AV/TV in standby mode
On Tue, Jan 24, 2012 at 10:03:57PM +, paulo louro wrote: > > Very ugly hack, > In file ---> intel_display.c function --- > > ironlake_crtc_mode_set > temp = I915_READ(_TRANSACONF); I915_WRITE(_TRANSACONF, temp & > ~(7<<21)); > I915_WRITE( 0x60028, 0x); //VSYNCSHIFT_A— Vertical Sync Shift > Register This register needs to be 0x for progressive mode > I915_WRITE(PIPECONF(pipe), pipeconf); POSTING_READ(PIPECONF(pipe)); > In file ---> i915_reg.h #define > PIPECONF_INTERLACE_W_FIELD_INDICATION (7 << 21) // ( 6 << 21) > Not sure why the PIPECONF MASK is 110 and not 111, from intel pdf 000b > Progressive Fetch / Progressive display / 001b PF-ID Progressive Fetch / > Interlaced display (HDMI) Requires panel fitting to be enabled Wohoo, this is awesome. Can you maybe go right ahead and create a patch for this? Should be nothing more than checking for an interlaced mode and banging the right values into these registers ... Yours, Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PROBLEM FOUND] Problem No HDMI when AV/TV in standby mode
Very ugly hack, In file ---> intel_display.c function --- > ironlake_crtc_mode_set temp = I915_READ(_TRANSACONF); I915_WRITE(_TRANSACONF, temp & ~(7<<21)); I915_WRITE( 0x60028, 0x); //VSYNCSHIFT_A— Vertical Sync Shift Register This register needs to be 0x for progressive mode I915_WRITE(PIPECONF(pipe), pipeconf); POSTING_READ(PIPECONF(pipe)); In file ---> i915_reg.h #define PIPECONF_INTERLACE_W_FIELD_INDICATION(7 << 21) // ( 6 << 21) Not sure why the PIPECONF MASK is 110 and not 111, from intel pdf 000b Progressive Fetch / Progressive display / 001b PF-ID Progressive Fetch / Interlaced display (HDMI) Requires panel fitting to be enabled Next will be to solve the RGB problem i have. From: paulo_lo...@msn.com To: intel-gfx@lists.freedesktop.org Date: Tue, 24 Jan 2012 20:38:57 + Subject: Re: [Intel-gfx] [PROBLEM FOUND] Problem No HDMI when AV/TV in standby mode Hello all, I think i have found why there is a problem with my Onkyo AV when the TV/AV are in standby mode. I run the following test. Boot PC with AV/TV in standby and dump intel registers to a file TEST1Boot PC with AV/TV on and dump intel register to file TEST2Using the diff to find the difference between both files i found the following: root@SERVER:~# diff test1 test214c14< PIPEACONF: 0xc020 (enabled, active, 8bpc)---> PIPEACONF: 0xc000 (enabled, active, 8bpc)21c21< VSYNCSHIFT_A: 0x038c---> VSYNCSHIFT_A: 0x125c125< TRANSACONF: 0xc060 (enable, active)---> TRANSACONF: 0xc000 (enable, active) So register PIPEACONF, VSYNCSHIFT_A and TRANSACONF are different. By checking intel documentation i found that this registers are responsibly for setting up the progressive/interleave mode. As so im thinking that this registers are not being reinitialize or cleaned. Is this possible? Since im up for one more test i used intel_reg_read/write to modified the registers and correct the values, to my surprise after writing to all the register the AV shows my desktop correctly. My other question is if they need to be reinitialized where in the code shall this be done? I'm up for writing a small patch to fix this issue, just need some one to point me on the right direction. Thanks--Paulo Louro ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PROBLEM FOUND] Problem No HDMI when AV/TV in standby mode
Hello all, I think i have found why there is a problem with my Onkyo AV when the TV/AV are in standby mode. I run the following test. Boot PC with AV/TV in standby and dump intel registers to a file TEST1Boot PC with AV/TV on and dump intel register to file TEST2Using the diff to find the difference between both files i found the following: root@SERVER:~# diff test1 test214c14< PIPEACONF: 0xc020 (enabled, active, 8bpc)---> PIPEACONF: 0xc000 (enabled, active, 8bpc)21c21< VSYNCSHIFT_A: 0x038c---> VSYNCSHIFT_A: 0x125c125< TRANSACONF: 0xc060 (enable, active)---> TRANSACONF: 0xc000 (enable, active) So register PIPEACONF, VSYNCSHIFT_A and TRANSACONF are different. By checking intel documentation i found that this registers are responsibly for setting up the progressive/interleave mode. As so im thinking that this registers are not being reinitialize or cleaned. Is this possible? Since im up for one more test i used intel_reg_read/write to modified the registers and correct the values, to my surprise after writing to all the register the AV shows my desktop correctly. My other question is if they need to be reinitialized where in the code shall this be done? I'm up for writing a small patch to fix this issue, just need some one to point me on the right direction. Thanks--Paulo Louro ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
