Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support
On Wed, Jun 13, 2018 at 07:21:54PM -0700, Dhinakaran Pandiyan wrote:
> On Wed, 2018-06-13 at 15:23 -0700, Lucas De Marchi wrote:
> > On Tue, May 29, 2018 at 05:04:58PM -0700, Lucas De Marchi wrote:
> > >
> > > On Thu, May 24, 2018 at 05:43:24PM -0700, Lucas De Marchi wrote:
> > > >
> > > > On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan
> > > > wrote:
> > > > >
> > > > > On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > > > > >
> > > > > > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > > > > > >
> > > > > > >
> > > > > > > From: Anusha Srivatsa
> > > > > > >
> > > > > > > This patch addresses Interrupts from south display engine
> > > > > > > (SDE).
> > > > > > >
> > > > > > > ICP has two registers - SHOTPLUG_CTL_DDI and
> > > > > > > SHOTPLUG_CTL_TC.
> > > > > > > Introduce these registers and their intended values.
> > > > > > >
> > > > > > > Introduce icp_irq_handler().
> > > > > > >
> > > > > > > Cc: Paulo Zanoni
> > > > > > > Cc: Dhinakaran Pandiyan
> > > > > > > Cc: Ville Syrjala
> > > > > > > Signed-off-by: Anusha Srivatsa
> > > > > > > [Paulo: coding style bikesheds and rebases].
> > > > > > > Signed-off-by: Paulo Zanoni
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/i915_irq.c | 134
> > > > > > > +++-
> > > > > > > drivers/gpu/drm/i915/i915_reg.h | 40
> > > > > > > 2 files changed, 172 insertions(+), 2 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > > index 9bcec5fdb9d0..6b109991786f 100644
> > > > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > > @@ -122,6 +122,15 @@ static const u32
> > > > > > > hpd_tc_gen11[HPD_NUM_PINS] =
> > > > > > > {
> > > > > > > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > > > > > > };
> > > > > > >
> > > > > > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > > > > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > > > > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > > > > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > > > > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > > > > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > > > > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > > > > > +};
> > > > > > > +
> > > > > > > /* IIR can theoretically queue up two events. Be paranoid.
> > > > > > > */
> > > > > > > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > > > > > > I915_WRITE(GEN8_##type##_IMR(which), 0x);
> > > > > > > \
> > > > > > > @@ -1586,6 +1595,34 @@ static bool
> > > > > > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > > > > > }
> > > > > > > }
> > > > > > >
> > > > > > > +static bool icp_ddi_port_hotplug_long_detect(enum port
> > > > > > > port, u32
> > > > > > > val)
> > > > > > > +{
> > > > > > > + switch (port) {
> > > > > > > + case PORT_A:
> > > > > > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > > > > > + case PORT_B:
> > > > > > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > > > > > + default:
> > > > > > > + return false;
> > > > > > > + }
> > > > > > > +}
> > > > > > > +
> > > > > > > +static bool icp_tc_port_hotplug_long_detect(enum port
> > > > > > > port, u32
> > > > > > > val)
> > > > > > > +{
> > > > > > > + switch (port) {
> > > > > > > + case PORT_C:
> > > > > > > + return val &
> > > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > > > > > > + case PORT_D:
> > > > > > > + return val &
> > > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > > > > > > + case PORT_E:
> > > > > > > + return val &
> > > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > > > > > > + case PORT_F:
> > > > > > > + return val &
> > > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > > > > > > + default:
> > > > > > > + return false;
> > > > > > > + }
> > > > > > > +}
> > > > > > > +
> > > > > > > static bool spt_port_hotplug2_long_detect(enum port port,
> > > > > > > u32 val)
> > > > > > > {
> > > > > > > switch (port) {
> > > > > > > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > > > > > > drm_i915_private *dev_priv, u32 pch_iir)
> > > > > > > cpt_serr_int_handler(dev_priv);
> > > > > > > }
> > > > > > >
> > > > > > > +static void icp_irq_handler(struct drm_i915_private
> > > > > > > *dev_priv, u32
> > > > > > > pch_iir)
> > > > > > > +{
> > > > > > > + u32 ddi_hotplug_trigger = pch_iir &
> > > > > > > ICP_SDE_DDI_MASK;
> > > > > > > + u32 tc_hotplug_trigger = pch_iir &
> > > > > > > ICP_SDE_TC_MASK;
> > > > > > > + u32 pin_mask = 0, long_mask = 0;
> > > > > > > +
> > > > > > > + if (ddi_hotplug_trigger) {
> > > > > > > + u32 dig_hotplug_reg;
> > > > > > > +
> > > > > > > + dig_hotplug_reg =
> > > > > > > I915_READ(SHOTPLUG_CTL_DDI);
> > > > > > > + I915_WRITE(SHOTPLUG_CTL_DDI,
> > > > > > > dig_hotplug_reg);
> > > > > > > +
> > > > > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
>
Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support
On Wed, 2018-06-13 at 15:23 -0700, Lucas De Marchi wrote:
> On Tue, May 29, 2018 at 05:04:58PM -0700, Lucas De Marchi wrote:
> >
> > On Thu, May 24, 2018 at 05:43:24PM -0700, Lucas De Marchi wrote:
> > >
> > > On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan
> > > wrote:
> > > >
> > > > On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > > > >
> > > > > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > > > > >
> > > > > >
> > > > > > From: Anusha Srivatsa
> > > > > >
> > > > > > This patch addresses Interrupts from south display engine
> > > > > > (SDE).
> > > > > >
> > > > > > ICP has two registers - SHOTPLUG_CTL_DDI and
> > > > > > SHOTPLUG_CTL_TC.
> > > > > > Introduce these registers and their intended values.
> > > > > >
> > > > > > Introduce icp_irq_handler().
> > > > > >
> > > > > > Cc: Paulo Zanoni
> > > > > > Cc: Dhinakaran Pandiyan
> > > > > > Cc: Ville Syrjala
> > > > > > Signed-off-by: Anusha Srivatsa
> > > > > > [Paulo: coding style bikesheds and rebases].
> > > > > > Signed-off-by: Paulo Zanoni
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/i915_irq.c | 134
> > > > > > +++-
> > > > > > drivers/gpu/drm/i915/i915_reg.h | 40
> > > > > > 2 files changed, 172 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > index 9bcec5fdb9d0..6b109991786f 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > @@ -122,6 +122,15 @@ static const u32
> > > > > > hpd_tc_gen11[HPD_NUM_PINS] =
> > > > > > {
> > > > > > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > > > > > };
> > > > > >
> > > > > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > > > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > > > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > > > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > > > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > > > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > > > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > > > > +};
> > > > > > +
> > > > > > /* IIR can theoretically queue up two events. Be paranoid.
> > > > > > */
> > > > > > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > > > > > I915_WRITE(GEN8_##type##_IMR(which), 0x);
> > > > > > \
> > > > > > @@ -1586,6 +1595,34 @@ static bool
> > > > > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > > > > }
> > > > > > }
> > > > > >
> > > > > > +static bool icp_ddi_port_hotplug_long_detect(enum port
> > > > > > port, u32
> > > > > > val)
> > > > > > +{
> > > > > > + switch (port) {
> > > > > > + case PORT_A:
> > > > > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > > > > + case PORT_B:
> > > > > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > > > > + default:
> > > > > > + return false;
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > +static bool icp_tc_port_hotplug_long_detect(enum port
> > > > > > port, u32
> > > > > > val)
> > > > > > +{
> > > > > > + switch (port) {
> > > > > > + case PORT_C:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > > > > > + case PORT_D:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > > > > > + case PORT_E:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > > > > > + case PORT_F:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > > > > > + default:
> > > > > > + return false;
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > static bool spt_port_hotplug2_long_detect(enum port port,
> > > > > > u32 val)
> > > > > > {
> > > > > > switch (port) {
> > > > > > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > > > > > drm_i915_private *dev_priv, u32 pch_iir)
> > > > > > cpt_serr_int_handler(dev_priv);
> > > > > > }
> > > > > >
> > > > > > +static void icp_irq_handler(struct drm_i915_private
> > > > > > *dev_priv, u32
> > > > > > pch_iir)
> > > > > > +{
> > > > > > + u32 ddi_hotplug_trigger = pch_iir &
> > > > > > ICP_SDE_DDI_MASK;
> > > > > > + u32 tc_hotplug_trigger = pch_iir &
> > > > > > ICP_SDE_TC_MASK;
> > > > > > + u32 pin_mask = 0, long_mask = 0;
> > > > > > +
> > > > > > + if (ddi_hotplug_trigger) {
> > > > > > + u32 dig_hotplug_reg;
> > > > > > +
> > > > > > + dig_hotplug_reg =
> > > > > > I915_READ(SHOTPLUG_CTL_DDI);
> > > > > > + I915_WRITE(SHOTPLUG_CTL_DDI,
> > > > > > dig_hotplug_reg);
> > > > > > +
> > > > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > > > &long_mask,
> > > > > > + ddi_hotplug_trigger,
> > > > > > + dig_hotplug_reg,
> > > > > > hpd_icp,
> > > > > > + icp_ddi_port_hotplug_lo
> > > > > > ng_de
Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support
Em Qua, 2018-06-13 às 15:23 -0700, Lucas De Marchi escreveu:
> On Tue, May 29, 2018 at 05:04:58PM -0700, Lucas De Marchi wrote:
> > On Thu, May 24, 2018 at 05:43:24PM -0700, Lucas De Marchi wrote:
> > > On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan
> > > wrote:
> > > > On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > > > > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > > > > >
> > > > > > From: Anusha Srivatsa
> > > > > >
> > > > > > This patch addresses Interrupts from south display engine
> > > > > > (SDE).
> > > > > >
> > > > > > ICP has two registers - SHOTPLUG_CTL_DDI and
> > > > > > SHOTPLUG_CTL_TC.
> > > > > > Introduce these registers and their intended values.
> > > > > >
> > > > > > Introduce icp_irq_handler().
> > > > > >
> > > > > > Cc: Paulo Zanoni
> > > > > > Cc: Dhinakaran Pandiyan
> > > > > > Cc: Ville Syrjala
> > > > > > Signed-off-by: Anusha Srivatsa
> > > > > > [Paulo: coding style bikesheds and rebases].
> > > > > > Signed-off-by: Paulo Zanoni
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/i915_irq.c | 134
> > > > > > +++-
> > > > > > drivers/gpu/drm/i915/i915_reg.h | 40
> > > > > > 2 files changed, 172 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > index 9bcec5fdb9d0..6b109991786f 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > > @@ -122,6 +122,15 @@ static const u32
> > > > > > hpd_tc_gen11[HPD_NUM_PINS] =
> > > > > > {
> > > > > > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > > > > > };
> > > > > >
> > > > > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > > > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > > > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > > > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > > > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > > > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > > > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > > > > +};
> > > > > > +
> > > > > > /* IIR can theoretically queue up two events. Be paranoid.
> > > > > > */
> > > > > > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > > > > > I915_WRITE(GEN8_##type##_IMR(which), 0x);
> > > > > > \
> > > > > > @@ -1586,6 +1595,34 @@ static bool
> > > > > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > > > > }
> > > > > > }
> > > > > >
> > > > > > +static bool icp_ddi_port_hotplug_long_detect(enum port
> > > > > > port, u32
> > > > > > val)
> > > > > > +{
> > > > > > + switch (port) {
> > > > > > + case PORT_A:
> > > > > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > > > > + case PORT_B:
> > > > > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > > > > + default:
> > > > > > + return false;
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > +static bool icp_tc_port_hotplug_long_detect(enum port
> > > > > > port, u32
> > > > > > val)
> > > > > > +{
> > > > > > + switch (port) {
> > > > > > + case PORT_C:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > > > > > + case PORT_D:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > > > > > + case PORT_E:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > > > > > + case PORT_F:
> > > > > > + return val &
> > > > > > ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > > > > > + default:
> > > > > > + return false;
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > static bool spt_port_hotplug2_long_detect(enum port port,
> > > > > > u32 val)
> > > > > > {
> > > > > > switch (port) {
> > > > > > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > > > > > drm_i915_private *dev_priv, u32 pch_iir)
> > > > > > cpt_serr_int_handler(dev_priv);
> > > > > > }
> > > > > >
> > > > > > +static void icp_irq_handler(struct drm_i915_private
> > > > > > *dev_priv, u32
> > > > > > pch_iir)
> > > > > > +{
> > > > > > + u32 ddi_hotplug_trigger = pch_iir &
> > > > > > ICP_SDE_DDI_MASK;
> > > > > > + u32 tc_hotplug_trigger = pch_iir &
> > > > > > ICP_SDE_TC_MASK;
> > > > > > + u32 pin_mask = 0, long_mask = 0;
> > > > > > +
> > > > > > + if (ddi_hotplug_trigger) {
> > > > > > + u32 dig_hotplug_reg;
> > > > > > +
> > > > > > + dig_hotplug_reg =
> > > > > > I915_READ(SHOTPLUG_CTL_DDI);
> > > > > > + I915_WRITE(SHOTPLUG_CTL_DDI,
> > > > > > dig_hotplug_reg);
> > > > > > +
> > > > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > > > &long_mask,
> > > > > > + ddi_hotplug_trigger,
> > > > > > + dig_hotplug_reg,
> > > > > > hpd_icp,
> > > > > > + icp_ddi_port_hotplug_lo
> > > > > > ng_detec
> > > > > > t);
> > > > > > + }
> >
Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support
On Tue, May 29, 2018 at 05:04:58PM -0700, Lucas De Marchi wrote:
> On Thu, May 24, 2018 at 05:43:24PM -0700, Lucas De Marchi wrote:
> > On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan wrote:
> > > On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > > > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > > > >
> > > > > From: Anusha Srivatsa
> > > > >
> > > > > This patch addresses Interrupts from south display engine (SDE).
> > > > >
> > > > > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> > > > > Introduce these registers and their intended values.
> > > > >
> > > > > Introduce icp_irq_handler().
> > > > >
> > > > > Cc: Paulo Zanoni
> > > > > Cc: Dhinakaran Pandiyan
> > > > > Cc: Ville Syrjala
> > > > > Signed-off-by: Anusha Srivatsa
> > > > > [Paulo: coding style bikesheds and rebases].
> > > > > Signed-off-by: Paulo Zanoni
> > > > > ---
> > > > > drivers/gpu/drm/i915/i915_irq.c | 134
> > > > > +++-
> > > > > drivers/gpu/drm/i915/i915_reg.h | 40
> > > > > 2 files changed, 172 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > > index 9bcec5fdb9d0..6b109991786f 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > > @@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] =
> > > > > {
> > > > > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > > > > };
> > > > >
> > > > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > > > +};
> > > > > +
> > > > > /* IIR can theoretically queue up two events. Be paranoid. */
> > > > > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > > > > I915_WRITE(GEN8_##type##_IMR(which), 0x); \
> > > > > @@ -1586,6 +1595,34 @@ static bool
> > > > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > > > }
> > > > > }
> > > > >
> > > > > +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32
> > > > > val)
> > > > > +{
> > > > > + switch (port) {
> > > > > + case PORT_A:
> > > > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > > > + case PORT_B:
> > > > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > > > + default:
> > > > > + return false;
> > > > > + }
> > > > > +}
> > > > > +
> > > > > +static bool icp_tc_port_hotplug_long_detect(enum port port, u32
> > > > > val)
> > > > > +{
> > > > > + switch (port) {
> > > > > + case PORT_C:
> > > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > > > > + case PORT_D:
> > > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > > > > + case PORT_E:
> > > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > > > > + case PORT_F:
> > > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > > > > + default:
> > > > > + return false;
> > > > > + }
> > > > > +}
> > > > > +
> > > > > static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
> > > > > {
> > > > > switch (port) {
> > > > > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > > > > drm_i915_private *dev_priv, u32 pch_iir)
> > > > > cpt_serr_int_handler(dev_priv);
> > > > > }
> > > > >
> > > > > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> > > > > pch_iir)
> > > > > +{
> > > > > + u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
> > > > > + u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
> > > > > + u32 pin_mask = 0, long_mask = 0;
> > > > > +
> > > > > + if (ddi_hotplug_trigger) {
> > > > > + u32 dig_hotplug_reg;
> > > > > +
> > > > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> > > > > + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> > > > > +
> > > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > > &long_mask,
> > > > > + ddi_hotplug_trigger,
> > > > > + dig_hotplug_reg, hpd_icp,
> > > > > + icp_ddi_port_hotplug_long_detec
> > > > > t);
> > > > > + }
> > > > > +
> > > > > + if (tc_hotplug_trigger) {
> > > > > + u32 dig_hotplug_reg;
> > > > > +
> > > > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> > > > > + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> > > > > +
> > > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > > &long_mask,
> > > > > + tc_hotplug_trigger,
> > > > > +
Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support
On Thu, May 24, 2018 at 05:43:24PM -0700, Lucas De Marchi wrote:
> On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > > >
> > > > From: Anusha Srivatsa
> > > >
> > > > This patch addresses Interrupts from south display engine (SDE).
> > > >
> > > > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> > > > Introduce these registers and their intended values.
> > > >
> > > > Introduce icp_irq_handler().
> > > >
> > > > Cc: Paulo Zanoni
> > > > Cc: Dhinakaran Pandiyan
> > > > Cc: Ville Syrjala
> > > > Signed-off-by: Anusha Srivatsa
> > > > [Paulo: coding style bikesheds and rebases].
> > > > Signed-off-by: Paulo Zanoni
> > > > ---
> > > > drivers/gpu/drm/i915/i915_irq.c | 134
> > > > +++-
> > > > drivers/gpu/drm/i915/i915_reg.h | 40
> > > > 2 files changed, 172 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > index 9bcec5fdb9d0..6b109991786f 100644
> > > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > > @@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] =
> > > > {
> > > > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > > > };
> > > >
> > > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > > +};
> > > > +
> > > > /* IIR can theoretically queue up two events. Be paranoid. */
> > > > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > > > I915_WRITE(GEN8_##type##_IMR(which), 0x); \
> > > > @@ -1586,6 +1595,34 @@ static bool
> > > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > > }
> > > > }
> > > >
> > > > +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32
> > > > val)
> > > > +{
> > > > + switch (port) {
> > > > + case PORT_A:
> > > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > > + case PORT_B:
> > > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > > + default:
> > > > + return false;
> > > > + }
> > > > +}
> > > > +
> > > > +static bool icp_tc_port_hotplug_long_detect(enum port port, u32
> > > > val)
> > > > +{
> > > > + switch (port) {
> > > > + case PORT_C:
> > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > > > + case PORT_D:
> > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > > > + case PORT_E:
> > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > > > + case PORT_F:
> > > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > > > + default:
> > > > + return false;
> > > > + }
> > > > +}
> > > > +
> > > > static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
> > > > {
> > > > switch (port) {
> > > > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > > > drm_i915_private *dev_priv, u32 pch_iir)
> > > > cpt_serr_int_handler(dev_priv);
> > > > }
> > > >
> > > > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> > > > pch_iir)
> > > > +{
> > > > + u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
> > > > + u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
> > > > + u32 pin_mask = 0, long_mask = 0;
> > > > +
> > > > + if (ddi_hotplug_trigger) {
> > > > + u32 dig_hotplug_reg;
> > > > +
> > > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> > > > + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> > > > +
> > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > &long_mask,
> > > > + ddi_hotplug_trigger,
> > > > + dig_hotplug_reg, hpd_icp,
> > > > + icp_ddi_port_hotplug_long_detec
> > > > t);
> > > > + }
> > > > +
> > > > + if (tc_hotplug_trigger) {
> > > > + u32 dig_hotplug_reg;
> > > > +
> > > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> > > > + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> > > > +
> > > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > > &long_mask,
> > > > + tc_hotplug_trigger,
> > > > + dig_hotplug_reg, hpd_icp,
> > > > + icp_tc_port_hotplug_long_detect
> > > > );
> > > > + }
> > > > +
> > > > + if (pin_mask)
> > > > +
Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support
On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan wrote:
> On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > >
> > > From: Anusha Srivatsa
> > >
> > > This patch addresses Interrupts from south display engine (SDE).
> > >
> > > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> > > Introduce these registers and their intended values.
> > >
> > > Introduce icp_irq_handler().
> > >
> > > Cc: Paulo Zanoni
> > > Cc: Dhinakaran Pandiyan
> > > Cc: Ville Syrjala
> > > Signed-off-by: Anusha Srivatsa
> > > [Paulo: coding style bikesheds and rebases].
> > > Signed-off-by: Paulo Zanoni
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 134
> > > +++-
> > > drivers/gpu/drm/i915/i915_reg.h | 40
> > > 2 files changed, 172 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 9bcec5fdb9d0..6b109991786f 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] =
> > > {
> > > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > > };
> > >
> > > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > > +};
> > > +
> > > /* IIR can theoretically queue up two events. Be paranoid. */
> > > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > > I915_WRITE(GEN8_##type##_IMR(which), 0x); \
> > > @@ -1586,6 +1595,34 @@ static bool
> > > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > > }
> > > }
> > >
> > > +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32
> > > val)
> > > +{
> > > + switch (port) {
> > > + case PORT_A:
> > > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > > + case PORT_B:
> > > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > > + default:
> > > + return false;
> > > + }
> > > +}
> > > +
> > > +static bool icp_tc_port_hotplug_long_detect(enum port port, u32
> > > val)
> > > +{
> > > + switch (port) {
> > > + case PORT_C:
> > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > > + case PORT_D:
> > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > > + case PORT_E:
> > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > > + case PORT_F:
> > > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > > + default:
> > > + return false;
> > > + }
> > > +}
> > > +
> > > static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
> > > {
> > > switch (port) {
> > > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > > drm_i915_private *dev_priv, u32 pch_iir)
> > > cpt_serr_int_handler(dev_priv);
> > > }
> > >
> > > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> > > pch_iir)
> > > +{
> > > + u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
> > > + u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
> > > + u32 pin_mask = 0, long_mask = 0;
> > > +
> > > + if (ddi_hotplug_trigger) {
> > > + u32 dig_hotplug_reg;
> > > +
> > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> > > + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> > > +
> > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > &long_mask,
> > > + ddi_hotplug_trigger,
> > > + dig_hotplug_reg, hpd_icp,
> > > + icp_ddi_port_hotplug_long_detec
> > > t);
> > > + }
> > > +
> > > + if (tc_hotplug_trigger) {
> > > + u32 dig_hotplug_reg;
> > > +
> > > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> > > + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> > > +
> > > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > > &long_mask,
> > > + tc_hotplug_trigger,
> > > + dig_hotplug_reg, hpd_icp,
> > > + icp_tc_port_hotplug_long_detect
> > > );
> > > + }
> > > +
> > > + if (pin_mask)
> > > + intel_hpd_irq_handler(dev_priv, pin_mask,
> > > long_mask);
> > > +
> > > + if (pch_iir & ICP_GMBUS)
> > > + gmbus_irq_handler(dev_priv);
> > > +}
> > > +
> > > static void spt_irq_handler(struct drm_i915_private *dev_priv, u32
> > > pch_iir)
> > > {
> > > u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> > > @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct drm_i915_private
> > > *dev_priv, u32 master_ctl)
> > > I915_WRITE(SDEIIR, iir);
> > > ret = IRQ_HANDLED;
> > >
> > > - if (HAS_PCH_SPT(dev_priv) ||
> > > HAS_PCH_KBP(dev_priv) ||
> > > -
Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support
On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> >
> > From: Anusha Srivatsa
> >
> > This patch addresses Interrupts from south display engine (SDE).
> >
> > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> > Introduce these registers and their intended values.
> >
> > Introduce icp_irq_handler().
> >
> > Cc: Paulo Zanoni
> > Cc: Dhinakaran Pandiyan
> > Cc: Ville Syrjala
> > Signed-off-by: Anusha Srivatsa
> > [Paulo: coding style bikesheds and rebases].
> > Signed-off-by: Paulo Zanoni
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 134
> > +++-
> > drivers/gpu/drm/i915/i915_reg.h | 40
> > 2 files changed, 172 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 9bcec5fdb9d0..6b109991786f 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] =
> > {
> > [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> > };
> >
> > +static const u32 hpd_icp[HPD_NUM_PINS] = {
> > + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> > + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> > + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> > + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> > + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> > + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> > +};
> > +
> > /* IIR can theoretically queue up two events. Be paranoid. */
> > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > I915_WRITE(GEN8_##type##_IMR(which), 0x); \
> > @@ -1586,6 +1595,34 @@ static bool
> > bxt_port_hotplug_long_detect(enum port port, u32 val)
> > }
> > }
> >
> > +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32
> > val)
> > +{
> > + switch (port) {
> > + case PORT_A:
> > + return val & ICP_DDIA_HPD_LONG_DETECT;
> > + case PORT_B:
> > + return val & ICP_DDIB_HPD_LONG_DETECT;
> > + default:
> > + return false;
> > + }
> > +}
> > +
> > +static bool icp_tc_port_hotplug_long_detect(enum port port, u32
> > val)
> > +{
> > + switch (port) {
> > + case PORT_C:
> > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> > + case PORT_D:
> > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> > + case PORT_E:
> > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> > + case PORT_F:
> > + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> > + default:
> > + return false;
> > + }
> > +}
> > +
> > static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
> > {
> > switch (port) {
> > @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct
> > drm_i915_private *dev_priv, u32 pch_iir)
> > cpt_serr_int_handler(dev_priv);
> > }
> >
> > +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32
> > pch_iir)
> > +{
> > + u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
> > + u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
> > + u32 pin_mask = 0, long_mask = 0;
> > +
> > + if (ddi_hotplug_trigger) {
> > + u32 dig_hotplug_reg;
> > +
> > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> > + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> > +
> > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > &long_mask,
> > + ddi_hotplug_trigger,
> > + dig_hotplug_reg, hpd_icp,
> > + icp_ddi_port_hotplug_long_detec
> > t);
> > + }
> > +
> > + if (tc_hotplug_trigger) {
> > + u32 dig_hotplug_reg;
> > +
> > + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> > + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> > +
> > + intel_get_hpd_pins(dev_priv, &pin_mask,
> > &long_mask,
> > + tc_hotplug_trigger,
> > + dig_hotplug_reg, hpd_icp,
> > + icp_tc_port_hotplug_long_detect
> > );
> > + }
> > +
> > + if (pin_mask)
> > + intel_hpd_irq_handler(dev_priv, pin_mask,
> > long_mask);
> > +
> > + if (pch_iir & ICP_GMBUS)
> > + gmbus_irq_handler(dev_priv);
> > +}
> > +
> > static void spt_irq_handler(struct drm_i915_private *dev_priv, u32
> > pch_iir)
> > {
> > u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> > @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct drm_i915_private
> > *dev_priv, u32 master_ctl)
> > I915_WRITE(SDEIIR, iir);
> > ret = IRQ_HANDLED;
> >
> > - if (HAS_PCH_SPT(dev_priv) ||
> > HAS_PCH_KBP(dev_priv) ||
> > - HAS_PCH_CNP(dev_priv))
> > + if (HAS_PCH_ICP(dev_priv))
> > + icp_irq_handler(dev_priv, iir);
> > + else if (HAS_PCH_SPT(dev_priv) ||
> > + HAS_P
Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support
On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> From: Anusha Srivatsa
>
> This patch addresses Interrupts from south display engine (SDE).
>
> ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> Introduce these registers and their intended values.
>
> Introduce icp_irq_handler().
>
> Cc: Paulo Zanoni
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjala
> Signed-off-by: Anusha Srivatsa
> [Paulo: coding style bikesheds and rebases].
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_irq.c | 134
> +++-
> drivers/gpu/drm/i915/i915_reg.h | 40
> 2 files changed, 172 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 9bcec5fdb9d0..6b109991786f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -122,6 +122,15 @@ static const u32 hpd_tc_gen11[HPD_NUM_PINS] = {
> [HPD_PORT_F] = GEN11_TC4_HOTPLUG
> };
>
> +static const u32 hpd_icp[HPD_NUM_PINS] = {
> + [HPD_PORT_A] = ICP_DDIA_HOTPLUG,
> + [HPD_PORT_B] = ICP_DDIB_HOTPLUG,
> + [HPD_PORT_C] = ICP_TC1_HOTPLUG,
> + [HPD_PORT_D] = ICP_TC2_HOTPLUG,
> + [HPD_PORT_E] = ICP_TC3_HOTPLUG,
> + [HPD_PORT_F] = ICP_TC4_HOTPLUG
> +};
> +
> /* IIR can theoretically queue up two events. Be paranoid. */
> #define GEN8_IRQ_RESET_NDX(type, which) do { \
> I915_WRITE(GEN8_##type##_IMR(which), 0x); \
> @@ -1586,6 +1595,34 @@ static bool bxt_port_hotplug_long_detect(enum port
> port, u32 val)
> }
> }
>
> +static bool icp_ddi_port_hotplug_long_detect(enum port port, u32 val)
> +{
> + switch (port) {
> + case PORT_A:
> + return val & ICP_DDIA_HPD_LONG_DETECT;
> + case PORT_B:
> + return val & ICP_DDIB_HPD_LONG_DETECT;
> + default:
> + return false;
> + }
> +}
> +
> +static bool icp_tc_port_hotplug_long_detect(enum port port, u32 val)
> +{
> + switch (port) {
> + case PORT_C:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
> + case PORT_D:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
> + case PORT_E:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
> + case PORT_F:
> + return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
> + default:
> + return false;
> + }
> +}
> +
> static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
> {
> switch (port) {
> @@ -2377,6 +2414,43 @@ static void cpt_irq_handler(struct drm_i915_private
> *dev_priv, u32 pch_iir)
> cpt_serr_int_handler(dev_priv);
> }
>
> +static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> +{
> + u32 ddi_hotplug_trigger = pch_iir & ICP_SDE_DDI_MASK;
> + u32 tc_hotplug_trigger = pch_iir & ICP_SDE_TC_MASK;
> + u32 pin_mask = 0, long_mask = 0;
> +
> + if (ddi_hotplug_trigger) {
> + u32 dig_hotplug_reg;
> +
> + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
> + I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
> +
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> +ddi_hotplug_trigger,
> +dig_hotplug_reg, hpd_icp,
> +icp_ddi_port_hotplug_long_detect);
> + }
> +
> + if (tc_hotplug_trigger) {
> + u32 dig_hotplug_reg;
> +
> + dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
> + I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
> +
> + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> +tc_hotplug_trigger,
> +dig_hotplug_reg, hpd_icp,
> +icp_tc_port_hotplug_long_detect);
> + }
> +
> + if (pin_mask)
> + intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
> +
> + if (pch_iir & ICP_GMBUS)
> + gmbus_irq_handler(dev_priv);
> +}
> +
> static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> {
> u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> @@ -2779,8 +2853,11 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
> u32 master_ctl)
> I915_WRITE(SDEIIR, iir);
> ret = IRQ_HANDLED;
>
> - if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) ||
> - HAS_PCH_CNP(dev_priv))
> + if (HAS_PCH_ICP(dev_priv))
> + icp_irq_handler(dev_priv, iir);
> + else if (HAS_PCH_SPT(dev_priv) ||
> + HAS_PCH_KBP(dev_priv) ||
> + HAS_PCH_CNP(dev_priv))
> spt_irq_handler(dev_priv, iir);
> else
> cpt_irq_handler(dev_priv, iir);
> @@ -3548,6 +
