Re: [Intel-gfx] [PATCH 2/9] drm/i915/gen12: Fix HDC pipeline flush

2020-05-05 Thread D Scott Phillips 
Mika Kuoppala  writes:

> HDC pipeline flush is bit on the first dword of
> the PIPE_CONTROL, not the second. Make it so.
>
> Signed-off-by: Mika Kuoppala 

Fixes: 4aa0b5d457f5 ("drm/i915/tgl: Add HDC Pipeline Flush")
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Re: [Intel-gfx] [PATCH 2/9] drm/i915/gen12: Fix HDC pipeline flush

2020-05-03 Thread Chris Wilson 
Quoting Mika Kuoppala (2020-04-30 16:47:28)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h 
> b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index b3cf09657fb2..534e435f20bc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -237,7 +237,7 @@
>  #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE(1<<11) /* MBZ on ILK 
> */
>  #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE(1<<10) /* 
> GM45+ only */
>  #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE  (1<<9)
> -#define   PIPE_CONTROL_HDC_PIPELINE_FLUSH  REG_BIT(9)  /* gen12 
> */
> +#define   PIPE_CONTROL0_HDC_PIPELINE_FLUSH REG_BIT(9)  /* gen12 
> */
>  #define   PIPE_CONTROL_NOTIFY  (1<<8)
>  #define   PIPE_CONTROL_FLUSH_ENABLE(1<<7) /* gen7+ */
>  #define   PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)

Confirmed. With the naming inversion resolved,
Reviewed-by: Chris Wilson 
-Chris
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Re: [Intel-gfx] [PATCH 2/9] drm/i915/gen12: Fix HDC pipeline flush

2020-05-03 Thread Chris Wilson 
Quoting Mika Kuoppala (2020-04-30 16:47:28)
> HDC pipeline flush is bit on the first dword of
> the PIPE_CONTROL, not the second. Make it so.
> 
> Signed-off-by: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/gt/intel_engine.h   | 23 +++
>  drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  2 +-
>  drivers/gpu/drm/i915/gt/intel_lrc.c  | 30 ++--
>  3 files changed, 33 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h 
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index d10e52ff059f..f449171ae808 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -241,19 +241,24 @@ void intel_engine_fini_breadcrumbs(struct 
> intel_engine_cs *engine);
>  void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
> struct drm_printer *p);
>  
> -static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
> +static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 
> flags1, u32 offset)
>  {
> memset(batch, 0, 6 * sizeof(u32));
>  
> -   batch[0] = GFX_OP_PIPE_CONTROL(6);
> -   batch[1] = flags;
> +   batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0;
> +   batch[1] = flags1;
> batch[2] = offset;
>  
> return batch + 6;
>  }
>  
> +static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
> +{
> +   return gen12_emit_pipe_control(batch, 0, flags, offset);

We always call into older; the gen prefix indicates the earliest the
function is usable.
-Chris
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