Re: [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support
On Wed, May 06, 2020 at 04:16:36PM +0300, Ville Syrjälä wrote:
> On Wed, May 06, 2020 at 03:12:10PM +0300, Lisovskiy, Stanislav wrote:
> > On Wed, May 06, 2020 at 12:12:28PM +0300, Ville Syrjälä wrote:
> > > On Wed, May 06, 2020 at 11:31:05AM +0300, Lisovskiy, Stanislav wrote:
> > > > On Tue, May 05, 2020 at 01:59:11PM +0300, Ville Syrjälä wrote:
> > > > > On Tue, May 05, 2020 at 01:22:44PM +0300, Stanislav Lisovskiy wrote:
> > > > > > Starting from TGL we need to have a separate wm0
> > > > > > values for SAGV and non-SAGV which affects
> > > > > > how calculations are done.
> > > > > >
> > > > > > v2: Remove long lines
> > > > > > v3: Removed COLOR_PLANE enum references
> > > > > > v4, v5, v6: Fixed rebase conflict
> > > > > >
> > > > > > Signed-off-by: Stanislav Lisovskiy
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> > > > > > .../drm/i915/display/intel_display_types.h| 3 +
> > > > > > drivers/gpu/drm/i915/intel_pm.c | 128
> > > > > > +-
> > > > > > 3 files changed, 130 insertions(+), 9 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > index fd6d63b03489..be5741cb7595 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct
> > > > > > intel_crtc *crtc,
> > > > > > /* Watermarks */
> > > > > > for (level = 0; level <= max_level; level++) {
> > > > > > if (skl_wm_level_equals(_plane_wm->wm[level],
> > > > > > -
> > > > > > _plane_wm->wm[level]))
> > > > > > +
> > > > > > _plane_wm->wm[level]) ||
> > > > > > + (level == 0 &&
> > > > > > skl_wm_level_equals(_plane_wm->wm[level],
> > > > > > +
> > > > > > _plane_wm->sagv_wm0)))
> > > > > > continue;
> > > > > >
> > > > > > drm_err(_priv->drm,
> > > > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct
> > > > > > intel_crtc *crtc,
> > > > > > /* Watermarks */
> > > > > > for (level = 0; level <= max_level; level++) {
> > > > > > if (skl_wm_level_equals(_plane_wm->wm[level],
> > > > > > -
> > > > > > _plane_wm->wm[level]))
> > > > > > +
> > > > > > _plane_wm->wm[level]) ||
> > > > > > + (level == 0 &&
> > > > > > skl_wm_level_equals(_plane_wm->wm[level],
> > > > > > +
> > > > > > _plane_wm->sagv_wm0)))
> > > > > > continue;
> > > > > >
> > > > > > drm_err(_priv->drm,
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > index 9488449e4b94..32cbbf7dddc6 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > @@ -688,11 +688,14 @@ struct skl_plane_wm {
> > > > > > struct skl_wm_level wm[8];
> > > > > > struct skl_wm_level uv_wm[8];
> > > > > > struct skl_wm_level trans_wm;
> > > > > > + struct skl_wm_level sagv_wm0;
> > > > > > + struct skl_wm_level uv_sagv_wm0;
> > > > >
> > > > > As mentioned before uv_wm is not a thing on icl+, so nuke this.
> > > >
> > > > This is used in skl_plane_wm_level accessor, which is used for all
> > > > platforms, not just icl+. I remember we had agreed that for all
> > > > platforms
> > > > before tgl I simply copy sagv_wm0 values from regular wm0, so that this
> > > > behaviour is unified(remember that your comment about memcpy which I
> > > > changed
> > > > to assignment, see skl_compute_sagv_wm).
> > >
> > > I think having that duplicated is just making things more confusing.
> > > Also uv_wm is never used by the hardware even on pre-icl, so having
> > > the accessor thing use it for the hw programming just doesn't make
> > > any sense.
> >
> > Problem is that we use it in skl_allocate_pipe_ddb in a few places:
> >
> > blocks += wm_level->min_ddb_alloc;
> > blocks += wm_uv_level->min_ddb_alloc;
>
> I don't think we should need any accessor in there. If we do
> what I suggested earlier, which I think was something like
> (can't find the mail anymore unfortunately):
>
> for reverse wm levels {
> blocks = sum(wm[level] blocks for all planes) +
> sum(uv_wm[level] blocks for all planes)
> ...
> if (block <= alloc_size)
> break;
> }
>
> if (level < 0)
> fail;
>
> blocks_sagv = sum(sagv_wm
Re: [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support
On Wed, May 06, 2020 at 03:12:10PM +0300, Lisovskiy, Stanislav wrote:
> On Wed, May 06, 2020 at 12:12:28PM +0300, Ville Syrjälä wrote:
> > On Wed, May 06, 2020 at 11:31:05AM +0300, Lisovskiy, Stanislav wrote:
> > > On Tue, May 05, 2020 at 01:59:11PM +0300, Ville Syrjälä wrote:
> > > > On Tue, May 05, 2020 at 01:22:44PM +0300, Stanislav Lisovskiy wrote:
> > > > > Starting from TGL we need to have a separate wm0
> > > > > values for SAGV and non-SAGV which affects
> > > > > how calculations are done.
> > > > >
> > > > > v2: Remove long lines
> > > > > v3: Removed COLOR_PLANE enum references
> > > > > v4, v5, v6: Fixed rebase conflict
> > > > >
> > > > > Signed-off-by: Stanislav Lisovskiy
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> > > > > .../drm/i915/display/intel_display_types.h| 3 +
> > > > > drivers/gpu/drm/i915/intel_pm.c | 128
> > > > > +-
> > > > > 3 files changed, 130 insertions(+), 9 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index fd6d63b03489..be5741cb7595 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc
> > > > > *crtc,
> > > > > /* Watermarks */
> > > > > for (level = 0; level <= max_level; level++) {
> > > > > if (skl_wm_level_equals(_plane_wm->wm[level],
> > > > > -
> > > > > _plane_wm->wm[level]))
> > > > > +
> > > > > _plane_wm->wm[level]) ||
> > > > > + (level == 0 &&
> > > > > skl_wm_level_equals(_plane_wm->wm[level],
> > > > > +
> > > > > _plane_wm->sagv_wm0)))
> > > > > continue;
> > > > >
> > > > > drm_err(_priv->drm,
> > > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc
> > > > > *crtc,
> > > > > /* Watermarks */
> > > > > for (level = 0; level <= max_level; level++) {
> > > > > if (skl_wm_level_equals(_plane_wm->wm[level],
> > > > > -
> > > > > _plane_wm->wm[level]))
> > > > > +
> > > > > _plane_wm->wm[level]) ||
> > > > > + (level == 0 &&
> > > > > skl_wm_level_equals(_plane_wm->wm[level],
> > > > > +
> > > > > _plane_wm->sagv_wm0)))
> > > > > continue;
> > > > >
> > > > > drm_err(_priv->drm,
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > index 9488449e4b94..32cbbf7dddc6 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > @@ -688,11 +688,14 @@ struct skl_plane_wm {
> > > > > struct skl_wm_level wm[8];
> > > > > struct skl_wm_level uv_wm[8];
> > > > > struct skl_wm_level trans_wm;
> > > > > + struct skl_wm_level sagv_wm0;
> > > > > + struct skl_wm_level uv_sagv_wm0;
> > > >
> > > > As mentioned before uv_wm is not a thing on icl+, so nuke this.
> > >
> > > This is used in skl_plane_wm_level accessor, which is used for all
> > > platforms, not just icl+. I remember we had agreed that for all platforms
> > > before tgl I simply copy sagv_wm0 values from regular wm0, so that this
> > > behaviour is unified(remember that your comment about memcpy which I
> > > changed
> > > to assignment, see skl_compute_sagv_wm).
> >
> > I think having that duplicated is just making things more confusing.
> > Also uv_wm is never used by the hardware even on pre-icl, so having
> > the accessor thing use it for the hw programming just doesn't make
> > any sense.
>
> Problem is that we use it in skl_allocate_pipe_ddb in a few places:
>
> blocks += wm_level->min_ddb_alloc;
> blocks += wm_uv_level->min_ddb_alloc;
I don't think we should need any accessor in there. If we do
what I suggested earlier, which I think was something like
(can't find the mail anymore unfortunately):
for reverse wm levels {
blocks = sum(wm[level] blocks for all planes) +
sum(uv_wm[level] blocks for all planes)
...
if (block <= alloc_size)
break;
}
if (level < 0)
fail;
blocks_sagv = sum(sagv_wm blocks for all planes)
if (blocks_sagv > blocks && blocks_sagv <= alloc_size) {
blocks = blocks_sagv;
use_sagv_wm = true;
} else {
use_sagv_wm = false;
}
alloc_size -= blocks;
for_each_plane_id() {
Re: [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support
On Wed, May 06, 2020 at 12:12:28PM +0300, Ville Syrjälä wrote:
> On Wed, May 06, 2020 at 11:31:05AM +0300, Lisovskiy, Stanislav wrote:
> > On Tue, May 05, 2020 at 01:59:11PM +0300, Ville Syrjälä wrote:
> > > On Tue, May 05, 2020 at 01:22:44PM +0300, Stanislav Lisovskiy wrote:
> > > > Starting from TGL we need to have a separate wm0
> > > > values for SAGV and non-SAGV which affects
> > > > how calculations are done.
> > > >
> > > > v2: Remove long lines
> > > > v3: Removed COLOR_PLANE enum references
> > > > v4, v5, v6: Fixed rebase conflict
> > > >
> > > > Signed-off-by: Stanislav Lisovskiy
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> > > > .../drm/i915/display/intel_display_types.h| 3 +
> > > > drivers/gpu/drm/i915/intel_pm.c | 128 +-
> > > > 3 files changed, 130 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index fd6d63b03489..be5741cb7595 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc
> > > > *crtc,
> > > > /* Watermarks */
> > > > for (level = 0; level <= max_level; level++) {
> > > > if (skl_wm_level_equals(_plane_wm->wm[level],
> > > > -
> > > > _plane_wm->wm[level]))
> > > > +
> > > > _plane_wm->wm[level]) ||
> > > > + (level == 0 &&
> > > > skl_wm_level_equals(_plane_wm->wm[level],
> > > > +
> > > > _plane_wm->sagv_wm0)))
> > > > continue;
> > > >
> > > > drm_err(_priv->drm,
> > > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc
> > > > *crtc,
> > > > /* Watermarks */
> > > > for (level = 0; level <= max_level; level++) {
> > > > if (skl_wm_level_equals(_plane_wm->wm[level],
> > > > -
> > > > _plane_wm->wm[level]))
> > > > +
> > > > _plane_wm->wm[level]) ||
> > > > + (level == 0 &&
> > > > skl_wm_level_equals(_plane_wm->wm[level],
> > > > +
> > > > _plane_wm->sagv_wm0)))
> > > > continue;
> > > >
> > > > drm_err(_priv->drm,
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 9488449e4b94..32cbbf7dddc6 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -688,11 +688,14 @@ struct skl_plane_wm {
> > > > struct skl_wm_level wm[8];
> > > > struct skl_wm_level uv_wm[8];
> > > > struct skl_wm_level trans_wm;
> > > > + struct skl_wm_level sagv_wm0;
> > > > + struct skl_wm_level uv_sagv_wm0;
> > >
> > > As mentioned before uv_wm is not a thing on icl+, so nuke this.
> >
> > This is used in skl_plane_wm_level accessor, which is used for all
> > platforms, not just icl+. I remember we had agreed that for all platforms
> > before tgl I simply copy sagv_wm0 values from regular wm0, so that this
> > behaviour is unified(remember that your comment about memcpy which I changed
> > to assignment, see skl_compute_sagv_wm).
>
> I think having that duplicated is just making things more confusing.
> Also uv_wm is never used by the hardware even on pre-icl, so having
> the accessor thing use it for the hw programming just doesn't make
> any sense.
Problem is that we use it in skl_allocate_pipe_ddb in a few places:
blocks += wm_level->min_ddb_alloc;
blocks += wm_uv_level->min_ddb_alloc;
then those plane data rates:
rate = plane_data_rate[plane_id];
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate, total_data_rate));
total[plane_id] = wm_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
if (total_data_rate == 0)
break;
rate = uv_plane_data_rate[plane_id];
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate, total_data_rate));
uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
So if I remove this wm_uv from skl_plane_wm_level accessor,
the logic in skl_allocate_pipe_ddb will obvisouly change?
Stan
>
> For the compute side I think all we should really need is
> something like:
>
> tgl_compute_sagv_wm()
> {
> skl_compute_wm_level(sagv_wm0, latency + whatever);
> }
>
> skl_build_plane_wm_single()
> {
> ...
>
Re: [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support
On Wed, May 06, 2020 at 11:31:05AM +0300, Lisovskiy, Stanislav wrote:
> On Tue, May 05, 2020 at 01:59:11PM +0300, Ville Syrjälä wrote:
> > On Tue, May 05, 2020 at 01:22:44PM +0300, Stanislav Lisovskiy wrote:
> > > Starting from TGL we need to have a separate wm0
> > > values for SAGV and non-SAGV which affects
> > > how calculations are done.
> > >
> > > v2: Remove long lines
> > > v3: Removed COLOR_PLANE enum references
> > > v4, v5, v6: Fixed rebase conflict
> > >
> > > Signed-off-by: Stanislav Lisovskiy
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> > > .../drm/i915/display/intel_display_types.h| 3 +
> > > drivers/gpu/drm/i915/intel_pm.c | 128 +-
> > > 3 files changed, 130 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index fd6d63b03489..be5741cb7595 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc
> > > *crtc,
> > > /* Watermarks */
> > > for (level = 0; level <= max_level; level++) {
> > > if (skl_wm_level_equals(_plane_wm->wm[level],
> > > - _plane_wm->wm[level]))
> > > + _plane_wm->wm[level]) ||
> > > + (level == 0 &&
> > > skl_wm_level_equals(_plane_wm->wm[level],
> > > +
> > > _plane_wm->sagv_wm0)))
> > > continue;
> > >
> > > drm_err(_priv->drm,
> > > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc
> > > *crtc,
> > > /* Watermarks */
> > > for (level = 0; level <= max_level; level++) {
> > > if (skl_wm_level_equals(_plane_wm->wm[level],
> > > - _plane_wm->wm[level]))
> > > + _plane_wm->wm[level]) ||
> > > + (level == 0 &&
> > > skl_wm_level_equals(_plane_wm->wm[level],
> > > +
> > > _plane_wm->sagv_wm0)))
> > > continue;
> > >
> > > drm_err(_priv->drm,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 9488449e4b94..32cbbf7dddc6 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -688,11 +688,14 @@ struct skl_plane_wm {
> > > struct skl_wm_level wm[8];
> > > struct skl_wm_level uv_wm[8];
> > > struct skl_wm_level trans_wm;
> > > + struct skl_wm_level sagv_wm0;
> > > + struct skl_wm_level uv_sagv_wm0;
> >
> > As mentioned before uv_wm is not a thing on icl+, so nuke this.
>
> This is used in skl_plane_wm_level accessor, which is used for all
> platforms, not just icl+. I remember we had agreed that for all platforms
> before tgl I simply copy sagv_wm0 values from regular wm0, so that this
> behaviour is unified(remember that your comment about memcpy which I changed
> to assignment, see skl_compute_sagv_wm).
I think having that duplicated is just making things more confusing.
Also uv_wm is never used by the hardware even on pre-icl, so having
the accessor thing use it for the hw programming just doesn't make
any sense.
For the compute side I think all we should really need is
something like:
tgl_compute_sagv_wm()
{
skl_compute_wm_level(sagv_wm0, latency + whatever);
}
skl_build_plane_wm_single()
{
...
skl_compute_transition_wm();
+ if (gen >= 12)
+ tgl_compute_sagv_wm();
}
And for the progamming side we should just pick the right
wm0 based on the crtc_state->use_sagv_wm or whatever flag.
>
> So if I remove it and this is called for pre-icl platforms, guess this would
> still
> need wm_uv data?
>
>
> Stan
>
> >
> > > bool is_planar;
> > > };
> > >
> > > struct skl_pipe_wm {
> > > struct skl_plane_wm planes[I915_MAX_PLANES];
> > > + bool can_sagv;
> >
> > I would call it use_sagv_wm or somesuch to make it actually clear what
> > it does.
> >
> > > };
> > >
> > > enum vlv_wm_level {
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index c7d726a656b2..1b9925b6672c 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3871,6 +3871,9 @@ static bool icl_crtc_can_enable_sagv(const struct
> > > intel_crtc_state *crtc_state)
> > > return intel_crtc_can_enable_sagv(crtc_state);
> > > }
> > >
> > > +static bool
> > > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > > +
> > > bool
Re: [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support
On Tue, May 05, 2020 at 01:59:11PM +0300, Ville Syrjälä wrote:
> On Tue, May 05, 2020 at 01:22:44PM +0300, Stanislav Lisovskiy wrote:
> > Starting from TGL we need to have a separate wm0
> > values for SAGV and non-SAGV which affects
> > how calculations are done.
> >
> > v2: Remove long lines
> > v3: Removed COLOR_PLANE enum references
> > v4, v5, v6: Fixed rebase conflict
> >
> > Signed-off-by: Stanislav Lisovskiy
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> > .../drm/i915/display/intel_display_types.h| 3 +
> > drivers/gpu/drm/i915/intel_pm.c | 128 +-
> > 3 files changed, 130 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index fd6d63b03489..be5741cb7595 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > /* Watermarks */
> > for (level = 0; level <= max_level; level++) {
> > if (skl_wm_level_equals(_plane_wm->wm[level],
> > - _plane_wm->wm[level]))
> > + _plane_wm->wm[level]) ||
> > + (level == 0 &&
> > skl_wm_level_equals(_plane_wm->wm[level],
> > +
> > _plane_wm->sagv_wm0)))
> > continue;
> >
> > drm_err(_priv->drm,
> > @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> > /* Watermarks */
> > for (level = 0; level <= max_level; level++) {
> > if (skl_wm_level_equals(_plane_wm->wm[level],
> > - _plane_wm->wm[level]))
> > + _plane_wm->wm[level]) ||
> > + (level == 0 &&
> > skl_wm_level_equals(_plane_wm->wm[level],
> > +
> > _plane_wm->sagv_wm0)))
> > continue;
> >
> > drm_err(_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 9488449e4b94..32cbbf7dddc6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -688,11 +688,14 @@ struct skl_plane_wm {
> > struct skl_wm_level wm[8];
> > struct skl_wm_level uv_wm[8];
> > struct skl_wm_level trans_wm;
> > + struct skl_wm_level sagv_wm0;
> > + struct skl_wm_level uv_sagv_wm0;
>
> As mentioned before uv_wm is not a thing on icl+, so nuke this.
This is used in skl_plane_wm_level accessor, which is used for all
platforms, not just icl+. I remember we had agreed that for all platforms
before tgl I simply copy sagv_wm0 values from regular wm0, so that this
behaviour is unified(remember that your comment about memcpy which I changed
to assignment, see skl_compute_sagv_wm).
So if I remove it and this is called for pre-icl platforms, guess this would
still
need wm_uv data?
Stan
>
> > bool is_planar;
> > };
> >
> > struct skl_pipe_wm {
> > struct skl_plane_wm planes[I915_MAX_PLANES];
> > + bool can_sagv;
>
> I would call it use_sagv_wm or somesuch to make it actually clear what
> it does.
>
> > };
> >
> > enum vlv_wm_level {
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index c7d726a656b2..1b9925b6672c 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3871,6 +3871,9 @@ static bool icl_crtc_can_enable_sagv(const struct
> > intel_crtc_state *crtc_state)
> > return intel_crtc_can_enable_sagv(crtc_state);
> > }
> >
> > +static bool
> > +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> > +
> > bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > {
> > if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > @@ -3884,7 +3887,7 @@ static int intel_compute_sagv_mask(struct
> > intel_atomic_state *state)
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > int ret;
> > struct intel_crtc *crtc;
> > - const struct intel_crtc_state *new_crtc_state;
> > + struct intel_crtc_state *new_crtc_state;
> > struct intel_bw_state *new_bw_state = NULL;
> > const struct intel_bw_state *old_bw_state = NULL;
> > int i;
> > @@ -3899,7 +3902,9 @@ static int intel_compute_sagv_mask(struct
> > intel_atomic_state *state)
> >
> > old_bw_state = intel_atomic_get_old_bw_state(state);
> >
> > - if (INTEL_GEN(dev_priv) >= 11)
> > + if (INTEL_GEN(dev_priv) >= 12)
> > +
Re: [Intel-gfx] [PATCH v27 3/6] drm/i915: Add TGL+ SAGV support
On Tue, May 05, 2020 at 01:22:44PM +0300, Stanislav Lisovskiy wrote:
> Starting from TGL we need to have a separate wm0
> values for SAGV and non-SAGV which affects
> how calculations are done.
>
> v2: Remove long lines
> v3: Removed COLOR_PLANE enum references
> v4, v5, v6: Fixed rebase conflict
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 8 +-
> .../drm/i915/display/intel_display_types.h| 3 +
> drivers/gpu/drm/i915/intel_pm.c | 128 +-
> 3 files changed, 130 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index fd6d63b03489..be5741cb7595 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13961,7 +13961,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> /* Watermarks */
> for (level = 0; level <= max_level; level++) {
> if (skl_wm_level_equals(_plane_wm->wm[level],
> - _plane_wm->wm[level]))
> + _plane_wm->wm[level]) ||
> + (level == 0 &&
> skl_wm_level_equals(_plane_wm->wm[level],
> +
> _plane_wm->sagv_wm0)))
> continue;
>
> drm_err(_priv->drm,
> @@ -14016,7 +14018,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
> /* Watermarks */
> for (level = 0; level <= max_level; level++) {
> if (skl_wm_level_equals(_plane_wm->wm[level],
> - _plane_wm->wm[level]))
> + _plane_wm->wm[level]) ||
> + (level == 0 &&
> skl_wm_level_equals(_plane_wm->wm[level],
> +
> _plane_wm->sagv_wm0)))
> continue;
>
> drm_err(_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9488449e4b94..32cbbf7dddc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -688,11 +688,14 @@ struct skl_plane_wm {
> struct skl_wm_level wm[8];
> struct skl_wm_level uv_wm[8];
> struct skl_wm_level trans_wm;
> + struct skl_wm_level sagv_wm0;
> + struct skl_wm_level uv_sagv_wm0;
As mentioned before uv_wm is not a thing on icl+, so nuke this.
> bool is_planar;
> };
>
> struct skl_pipe_wm {
> struct skl_plane_wm planes[I915_MAX_PLANES];
> + bool can_sagv;
I would call it use_sagv_wm or somesuch to make it actually clear what
it does.
> };
>
> enum vlv_wm_level {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c7d726a656b2..1b9925b6672c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3871,6 +3871,9 @@ static bool icl_crtc_can_enable_sagv(const struct
> intel_crtc_state *crtc_state)
> return intel_crtc_can_enable_sagv(crtc_state);
> }
>
> +static bool
> +tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
> +
> bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> {
> if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> @@ -3884,7 +3887,7 @@ static int intel_compute_sagv_mask(struct
> intel_atomic_state *state)
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> int ret;
> struct intel_crtc *crtc;
> - const struct intel_crtc_state *new_crtc_state;
> + struct intel_crtc_state *new_crtc_state;
> struct intel_bw_state *new_bw_state = NULL;
> const struct intel_bw_state *old_bw_state = NULL;
> int i;
> @@ -3899,7 +3902,9 @@ static int intel_compute_sagv_mask(struct
> intel_atomic_state *state)
>
> old_bw_state = intel_atomic_get_old_bw_state(state);
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (INTEL_GEN(dev_priv) >= 12)
> + can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
> + else if (INTEL_GEN(dev_priv) >= 11)
> can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
> else
> can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> @@ -3921,6 +3926,24 @@ static int intel_compute_sagv_mask(struct
> intel_atomic_state *state)
> return ret;
> }
>
> + for_each_new_intel_crtc_in_state(state, crtc,
> + new_crtc_state, i) {
> + struct skl_pipe_wm *pipe_wm = _crtc_state->wm.skl.optimal;
> +
> + /*
> +
