RE: [PATCH 5/5 v9] iommu/fsl: Freescale PAMU driver and iommu implementation.
> -Original Message- > From: Kumar Gala [mailto:ga...@kernel.crashing.org] > Sent: Thursday, March 14, 2013 3:20 PM > To: Sethi Varun-B16395 > Cc: j...@8bytes.org; iommu@lists.linux-foundation.org; > linuxppc-...@lists.ozlabs.org; linux- > ker...@vger.kernel.org; b...@kernel.crashing.org; Wood Scott-B07421; Yoder > Stuart-B08248 > Subject: Re: [PATCH 5/5 v9] iommu/fsl: Freescale PAMU driver and iommu > implementation. > > > On Mar 13, 2013, at 1:49 PM, Varun Sethi wrote: > > > +/* > > + * Table of SVRs and the corresponding PORT_ID values. > > + * > > + * All future CoreNet-enabled SOCs will have this erratum fixed, so this > > table > > + * should never need to be updated. SVRs are guaranteed to be unique, so > > + * there is no worry that a future SOC will inadvertently have one of these > > + * values. > > + */ > > Maybe add to the comment about what port_id represents When you update the comment, I would also suggest identifying the specific errata here (A-004510) so that it's easy to reference back to the specific issue this code is fixing. Stuart ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH 5/5 v9] iommu/fsl: Freescale PAMU driver and iommu implementation.
On Mar 14, 2013, at 3:20 PM, Kumar Gala wrote:
>
> On Mar 13, 2013, at 1:49 PM, Varun Sethi wrote:
>
>> +/*
>> + * Table of SVRs and the corresponding PORT_ID values.
>> + *
>> + * All future CoreNet-enabled SOCs will have this erratum fixed, so this
>> table
>> + * should never need to be updated. SVRs are guaranteed to be unique, so
>> + * there is no worry that a future SOC will inadvertently have one of these
>> + * values.
>> + */
>
> Maybe add to the comment about what port_id represents
also, add reference to the erratum #/id/name
>
>> +static const struct {
>> +u32 svr;
>> +u32 port_id;
>> +} port_id_map[] = {
>> +{0x82100010, 0xFF00}, /* P2040 1.0 */
>> +{0x82100011, 0xFF00}, /* P2040 1.1 */
>> +{0x82100110, 0xFF00}, /* P2041 1.0 */
>> +{0x82100111, 0xFF00}, /* P2041 1.1 */
>> +{0x82110310, 0xFF00}, /* P3041 1.0 */
>> +{0x82110311, 0xFF00}, /* P3041 1.1 */
>> +{0x82010020, 0xFFF8}, /* P4040 2.0 */
>> +{0x8220, 0xFFF8}, /* P4080 2.0 */
>> +{0x82210010, 0xFC00}, /* P5010 1.0 */
>> +{0x82210020, 0xFC00}, /* P5010 2.0 */
>> +{0x82200010, 0xFC00}, /* P5020 1.0 */
>> +{0x82050010, 0xFF80}, /* P5021 1.0 */
>> +{0x82040010, 0xFF80}, /* P5040 1.0 */
>> +};
>> +
>> +#define SVR_SECURITY0x8 /* The Security (E) bit */
>> +
>> +static int __init fsl_pamu_probe(struct platform_device *pdev)
>> +{
>> +void __iomem *pamu_regs = NULL;
>> +struct ccsr_guts __iomem *guts_regs = NULL;
>> +u32 pamubypenr, pamu_counter;
>> +unsigned long pamu_reg_off;
>> +unsigned long pamu_reg_base;
>> +struct pamu_isr_data *data;
>> +struct device_node *guts_node;
>> +u64 size;
>> +struct page *p;
>> +int ret = 0;
>> +int irq;
>> +phys_addr_t ppaact_phys;
>> +phys_addr_t spaact_phys;
>> +phys_addr_t omt_phys;
>> +size_t mem_size = 0;
>> +unsigned int order = 0;
>> +u32 csd_port_id = 0;
>> +unsigned i;
>> +/*
>> + * enumerate all PAMUs and allocate and setup PAMU tables
>> + * for each of them,
>> + * NOTE : All PAMUs share the same LIODN tables.
>> + */
>> +
>> +pamu_regs = of_iomap(pdev->dev.of_node, 0);
>> +if (!pamu_regs) {
>> +dev_err(&pdev->dev, "ioremap of PAMU node failed\n");
>> +return -ENOMEM;
>> +}
>> +of_get_address(pdev->dev.of_node, 0, &size, NULL);
>> +
>> +irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
>> +if (irq == NO_IRQ) {
>> +dev_warn(&pdev->dev, "no interrupts listed in PAMU node\n");
>> +goto error;
>> +}
>> +
>> +data = kzalloc(sizeof(struct pamu_isr_data), GFP_KERNEL);
>> +if (!data) {
>> +iounmap(pamu_regs);
>> +return -ENOMEM;
>> +}
>> +data->pamu_reg_base = pamu_regs;
>> +data->count = size / PAMU_OFFSET;
>> +
>> +/* The ISR needs access to the regs, so we won't iounmap them */
>> +ret = request_irq(irq, pamu_av_isr, 0, "pamu", data);
>> +if (ret < 0) {
>> +dev_err(&pdev->dev, "error %i installing ISR for irq %i\n",
>> +ret, irq);
>> +goto error;
>> +}
>> +
>> +guts_node = of_find_compatible_node(NULL, NULL,
>> +"fsl,qoriq-device-config-1.0");
>
> This doesn't work for T4 or B4 device trees.
>
>> +if (!guts_node) {
>> +dev_err(&pdev->dev, "could not find GUTS node %s\n",
>> +pdev->dev.of_node->full_name);
>> +ret = -ENODEV;
>> +goto error;
>> +}
>> +
>> +guts_regs = of_iomap(guts_node, 0);
>> +of_node_put(guts_node);
>> +if (!guts_regs) {
>> +dev_err(&pdev->dev, "ioremap of GUTS node failed\n");
>> +ret = -ENODEV;
>> +goto error;
>> +}
>> +
>> +/* read in the PAMU capability registers */
>> +get_pamu_cap_values((unsigned long)pamu_regs);
>> +/*
>> + * To simplify the allocation of a coherency domain, we allocate the
>> + * PAACT and the OMT in the same memory buffer. Unfortunately, this
>> + * wastes more memory compared to allocating the buffers separately.
>> + */
>> +/* Determine how much memory we need */
>> +mem_size = (PAGE_SIZE << get_order(PAACT_SIZE)) +
>> +(PAGE_SIZE << get_order(SPAACT_SIZE)) +
>> +(PAGE_SIZE << get_order(OMT_SIZE));
>> +order = get_order(mem_size);
>> +
>> +p = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
>> +if (!p) {
>> +dev_err(&pdev->dev, "unable to allocate PAACT/SPAACT/OMT
>> block\n");
>> +ret = -ENOMEM;
>> +goto error;
>> +}
>> +
>> +ppaact = page_address(p);
>> +ppaact_phys = page_to_phys(p);
>> +
>> +/* Make sure the memory is naturally aligned */
>> +if (ppaact_phys & ((PAGE_SIZE << order) - 1)) {
>> +dev_e
Re: [PATCH 5/5 v9] iommu/fsl: Freescale PAMU driver and iommu implementation.
On Mar 13, 2013, at 1:49 PM, Varun Sethi wrote:
> +/*
> + * Table of SVRs and the corresponding PORT_ID values.
> + *
> + * All future CoreNet-enabled SOCs will have this erratum fixed, so this
> table
> + * should never need to be updated. SVRs are guaranteed to be unique, so
> + * there is no worry that a future SOC will inadvertently have one of these
> + * values.
> + */
Maybe add to the comment about what port_id represents
> +static const struct {
> + u32 svr;
> + u32 port_id;
> +} port_id_map[] = {
> + {0x82100010, 0xFF00}, /* P2040 1.0 */
> + {0x82100011, 0xFF00}, /* P2040 1.1 */
> + {0x82100110, 0xFF00}, /* P2041 1.0 */
> + {0x82100111, 0xFF00}, /* P2041 1.1 */
> + {0x82110310, 0xFF00}, /* P3041 1.0 */
> + {0x82110311, 0xFF00}, /* P3041 1.1 */
> + {0x82010020, 0xFFF8}, /* P4040 2.0 */
> + {0x8220, 0xFFF8}, /* P4080 2.0 */
> + {0x82210010, 0xFC00}, /* P5010 1.0 */
> + {0x82210020, 0xFC00}, /* P5010 2.0 */
> + {0x82200010, 0xFC00}, /* P5020 1.0 */
> + {0x82050010, 0xFF80}, /* P5021 1.0 */
> + {0x82040010, 0xFF80}, /* P5040 1.0 */
> +};
> +
> +#define SVR_SECURITY 0x8 /* The Security (E) bit */
> +
> +static int __init fsl_pamu_probe(struct platform_device *pdev)
> +{
> + void __iomem *pamu_regs = NULL;
> + struct ccsr_guts __iomem *guts_regs = NULL;
> + u32 pamubypenr, pamu_counter;
> + unsigned long pamu_reg_off;
> + unsigned long pamu_reg_base;
> + struct pamu_isr_data *data;
> + struct device_node *guts_node;
> + u64 size;
> + struct page *p;
> + int ret = 0;
> + int irq;
> + phys_addr_t ppaact_phys;
> + phys_addr_t spaact_phys;
> + phys_addr_t omt_phys;
> + size_t mem_size = 0;
> + unsigned int order = 0;
> + u32 csd_port_id = 0;
> + unsigned i;
> + /*
> + * enumerate all PAMUs and allocate and setup PAMU tables
> + * for each of them,
> + * NOTE : All PAMUs share the same LIODN tables.
> + */
> +
> + pamu_regs = of_iomap(pdev->dev.of_node, 0);
> + if (!pamu_regs) {
> + dev_err(&pdev->dev, "ioremap of PAMU node failed\n");
> + return -ENOMEM;
> + }
> + of_get_address(pdev->dev.of_node, 0, &size, NULL);
> +
> + irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
> + if (irq == NO_IRQ) {
> + dev_warn(&pdev->dev, "no interrupts listed in PAMU node\n");
> + goto error;
> + }
> +
> + data = kzalloc(sizeof(struct pamu_isr_data), GFP_KERNEL);
> + if (!data) {
> + iounmap(pamu_regs);
> + return -ENOMEM;
> + }
> + data->pamu_reg_base = pamu_regs;
> + data->count = size / PAMU_OFFSET;
> +
> + /* The ISR needs access to the regs, so we won't iounmap them */
> + ret = request_irq(irq, pamu_av_isr, 0, "pamu", data);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "error %i installing ISR for irq %i\n",
> + ret, irq);
> + goto error;
> + }
> +
> + guts_node = of_find_compatible_node(NULL, NULL,
> + "fsl,qoriq-device-config-1.0");
This doesn't work for T4 or B4 device trees.
> + if (!guts_node) {
> + dev_err(&pdev->dev, "could not find GUTS node %s\n",
> + pdev->dev.of_node->full_name);
> + ret = -ENODEV;
> + goto error;
> + }
> +
> + guts_regs = of_iomap(guts_node, 0);
> + of_node_put(guts_node);
> + if (!guts_regs) {
> + dev_err(&pdev->dev, "ioremap of GUTS node failed\n");
> + ret = -ENODEV;
> + goto error;
> + }
> +
> + /* read in the PAMU capability registers */
> + get_pamu_cap_values((unsigned long)pamu_regs);
> + /*
> + * To simplify the allocation of a coherency domain, we allocate the
> + * PAACT and the OMT in the same memory buffer. Unfortunately, this
> + * wastes more memory compared to allocating the buffers separately.
> + */
> + /* Determine how much memory we need */
> + mem_size = (PAGE_SIZE << get_order(PAACT_SIZE)) +
> + (PAGE_SIZE << get_order(SPAACT_SIZE)) +
> + (PAGE_SIZE << get_order(OMT_SIZE));
> + order = get_order(mem_size);
> +
> + p = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
> + if (!p) {
> + dev_err(&pdev->dev, "unable to allocate PAACT/SPAACT/OMT
> block\n");
> + ret = -ENOMEM;
> + goto error;
> + }
> +
> + ppaact = page_address(p);
> + ppaact_phys = page_to_phys(p);
> +
> + /* Make sure the memory is naturally aligned */
> + if (ppaact_phys & ((PAGE_SIZE << order) - 1)) {
> + dev_err(&pdev->dev, "PAACT/OMT block is unaligned\n");
> + ret = -ENOMEM;
> + goto error;
> + }
> +
> + spaact = (void *)p
