Re: [PATCH 17/37] iommu/arm-smmu-v3: Move context descriptor code

2018-03-14 Thread Jean-Philippe Brucker 
On 09/03/18 11:44, Jonathan Cameron wrote:
> On Mon, 12 Feb 2018 18:33:32 +
> Jean-Philippe Brucker  wrote:
> 
>> In order to add support for substream ID, move the context descriptor code
>> into a separate library. At the moment it only manages context descriptor
>> 0, which is used for non-PASID translations.
>>
>> One important behavior change is the ASID allocator, which is now global
>> instead of per-SMMU. If we end up needing per-SMMU ASIDs after all, it
>> would be relatively simple to move back to per-device allocator instead
>> of a global one. Sharing ASIDs will require an IDR, so implement the
>> ASID allocator with an IDA instead of porting the bitmap, to ease the
>> transition.
>>
>> Signed-off-by: Jean-Philippe Brucker 
> Hi Jean-Philippe,
> 
> This would have been easier to review if split into a 'move' and additional
> patches actually making the changes described.
> 
> Superficially it looks like there may be more going on in here than the
> above description suggests.  I'm unsure why we are gaining 
> the CFGI_CD_ALL and similar in this patch as there is just to much going on.

Ok I'll try to split this

Thanks,
Jean
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Re: [PATCH 17/37] iommu/arm-smmu-v3: Move context descriptor code

2018-03-09 Thread Jonathan Cameron 
On Mon, 12 Feb 2018 18:33:32 +
Jean-Philippe Brucker  wrote:

> In order to add support for substream ID, move the context descriptor code
> into a separate library. At the moment it only manages context descriptor
> 0, which is used for non-PASID translations.
> 
> One important behavior change is the ASID allocator, which is now global
> instead of per-SMMU. If we end up needing per-SMMU ASIDs after all, it
> would be relatively simple to move back to per-device allocator instead
> of a global one. Sharing ASIDs will require an IDR, so implement the
> ASID allocator with an IDA instead of porting the bitmap, to ease the
> transition.
> 
> Signed-off-by: Jean-Philippe Brucker 
Hi Jean-Philippe,

This would have been easier to review if split into a 'move' and additional
patches actually making the changes described.

Superficially it looks like there may be more going on in here than the
above description suggests.  I'm unsure why we are gaining 
the CFGI_CD_ALL and similar in this patch as there is just to much going on.

Thanks,

Jonathan
> ---
>  MAINTAINERS |   2 +-
>  drivers/iommu/Kconfig   |  11 ++
>  drivers/iommu/Makefile  |   1 +
>  drivers/iommu/arm-smmu-v3-context.c | 289 
> 
>  drivers/iommu/arm-smmu-v3.c | 265 +++--
>  drivers/iommu/iommu-pasid.c |   1 +
>  drivers/iommu/iommu-pasid.h |  27 
>  7 files changed, 451 insertions(+), 145 deletions(-)
>  create mode 100644 drivers/iommu/arm-smmu-v3-context.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9cb8ced8322a..93507bfe03a6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1104,7 +1104,7 @@ R:  Robin Murphy 
>  L:   linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
>  S:   Maintained
>  F:   drivers/iommu/arm-smmu.c
> -F:   drivers/iommu/arm-smmu-v3.c
> +F:   drivers/iommu/arm-smmu-v3*
>  F:   drivers/iommu/io-pgtable-arm.c
>  F:   drivers/iommu/io-pgtable-arm.h
>  F:   drivers/iommu/io-pgtable-arm-v7s.c
> diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
> index 8add90ba9b75..4b272925ee78 100644
> --- a/drivers/iommu/Kconfig
> +++ b/drivers/iommu/Kconfig
> @@ -66,6 +66,16 @@ menu "Generic PASID table support"
>  config IOMMU_PASID_TABLE
>   bool
>  
> +config ARM_SMMU_V3_CONTEXT
> + bool "ARM SMMU v3 Context Descriptor tables"
> + select IOMMU_PASID_TABLE
> + depends on ARM64
> + help
> + Enable support for ARM SMMU v3 Context Descriptor tables, used for DMA
> + and PASID support.
> +
> + If unsure, say N here.
> +
>  endmenu
>  
>  config IOMMU_IOVA
> @@ -344,6 +354,7 @@ config ARM_SMMU_V3
>   depends on ARM64
>   select IOMMU_API
>   select IOMMU_IO_PGTABLE_LPAE
> + select ARM_SMMU_V3_CONTEXT
>   select GENERIC_MSI_IRQ_DOMAIN
>   help
> Support for implementations of the ARM System MMU architecture
> diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
> index 338e59c93131..22758960ed02 100644
> --- a/drivers/iommu/Makefile
> +++ b/drivers/iommu/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_IOMMU_IO_PGTABLE) += io-pgtable.o
>  obj-$(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) += io-pgtable-arm-v7s.o
>  obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o
>  obj-$(CONFIG_IOMMU_PASID_TABLE) += iommu-pasid.o
> +obj-$(CONFIG_ARM_SMMU_V3_CONTEXT) += arm-smmu-v3-context.o
>  obj-$(CONFIG_IOMMU_IOVA) += iova.o
>  obj-$(CONFIG_OF_IOMMU)   += of_iommu.o
>  obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o
> diff --git a/drivers/iommu/arm-smmu-v3-context.c 
> b/drivers/iommu/arm-smmu-v3-context.c
> new file mode 100644
> index ..e910cb356f45
> --- /dev/null
> +++ b/drivers/iommu/arm-smmu-v3-context.c
> @@ -0,0 +1,289 @@
> +/*
> + * Context descriptor table driver for SMMUv3
> + *
> + * Copyright (C) 2018 ARM Ltd.
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "iommu-pasid.h"
> +
> +#define CTXDESC_CD_DWORDS8
> +#define CTXDESC_CD_0_TCR_T0SZ_SHIFT  0
> +#define ARM64_TCR_T0SZ_SHIFT 0
> +#define ARM64_TCR_T0SZ_MASK  0x1fUL
> +#define CTXDESC_CD_0_TCR_TG0_SHIFT   6
> +#define ARM64_TCR_TG0_SHIFT  14
> +#define ARM64_TCR_TG0_MASK   0x3UL
> +#define CTXDESC_CD_0_TCR_IRGN0_SHIFT 8
> +#define ARM64_TCR_IRGN0_SHIFT8
> +#define ARM64_TCR_IRGN0_MASK 0x3UL
> +#define CTXDESC_CD_0_TCR_ORGN0_SHIFT 10
> +#define ARM64_TCR_ORGN0_SHIFT10
> +#define ARM64_TCR_ORGN0_MASK 0x3UL
> +#define CTXDESC_CD_0_TCR_SH0_SHIFT   12
> +#define ARM64_TCR_SH0_SHIFT  12
> +#define ARM64_TCR_SH0_MASK   0x3UL
> +#define CTXDESC_CD_0_TCR_EPD0_SHIFT  14
> +#define ARM64_TCR_EPD0_SHIFT 7
> +#define ARM64_TCR_EPD0_MASK  0x1UL
> +#define

[PATCH 17/37] iommu/arm-smmu-v3: Move context descriptor code

2018-02-12 Thread Jean-Philippe Brucker 
In order to add support for substream ID, move the context descriptor code
into a separate library. At the moment it only manages context descriptor
0, which is used for non-PASID translations.

One important behavior change is the ASID allocator, which is now global
instead of per-SMMU. If we end up needing per-SMMU ASIDs after all, it
would be relatively simple to move back to per-device allocator instead
of a global one. Sharing ASIDs will require an IDR, so implement the
ASID allocator with an IDA instead of porting the bitmap, to ease the
transition.

Signed-off-by: Jean-Philippe Brucker 
---
 MAINTAINERS |   2 +-
 drivers/iommu/Kconfig   |  11 ++
 drivers/iommu/Makefile  |   1 +
 drivers/iommu/arm-smmu-v3-context.c | 289 
 drivers/iommu/arm-smmu-v3.c | 265 +++--
 drivers/iommu/iommu-pasid.c |   1 +
 drivers/iommu/iommu-pasid.h |  27 
 7 files changed, 451 insertions(+), 145 deletions(-)
 create mode 100644 drivers/iommu/arm-smmu-v3-context.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 9cb8ced8322a..93507bfe03a6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1104,7 +1104,7 @@ R:Robin Murphy 
 L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
 S: Maintained
 F: drivers/iommu/arm-smmu.c
-F: drivers/iommu/arm-smmu-v3.c
+F: drivers/iommu/arm-smmu-v3*
 F: drivers/iommu/io-pgtable-arm.c
 F: drivers/iommu/io-pgtable-arm.h
 F: drivers/iommu/io-pgtable-arm-v7s.c
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 8add90ba9b75..4b272925ee78 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -66,6 +66,16 @@ menu "Generic PASID table support"
 config IOMMU_PASID_TABLE
bool
 
+config ARM_SMMU_V3_CONTEXT
+   bool "ARM SMMU v3 Context Descriptor tables"
+   select IOMMU_PASID_TABLE
+   depends on ARM64
+   help
+   Enable support for ARM SMMU v3 Context Descriptor tables, used for DMA
+   and PASID support.
+
+   If unsure, say N here.
+
 endmenu
 
 config IOMMU_IOVA
@@ -344,6 +354,7 @@ config ARM_SMMU_V3
depends on ARM64
select IOMMU_API
select IOMMU_IO_PGTABLE_LPAE
+   select ARM_SMMU_V3_CONTEXT
select GENERIC_MSI_IRQ_DOMAIN
help
  Support for implementations of the ARM System MMU architecture
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index 338e59c93131..22758960ed02 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_IOMMU_IO_PGTABLE) += io-pgtable.o
 obj-$(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) += io-pgtable-arm-v7s.o
 obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o
 obj-$(CONFIG_IOMMU_PASID_TABLE) += iommu-pasid.o
+obj-$(CONFIG_ARM_SMMU_V3_CONTEXT) += arm-smmu-v3-context.o
 obj-$(CONFIG_IOMMU_IOVA) += iova.o
 obj-$(CONFIG_OF_IOMMU) += of_iommu.o
 obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o
diff --git a/drivers/iommu/arm-smmu-v3-context.c 
b/drivers/iommu/arm-smmu-v3-context.c
new file mode 100644
index ..e910cb356f45
--- /dev/null
+++ b/drivers/iommu/arm-smmu-v3-context.c
@@ -0,0 +1,289 @@
+/*
+ * Context descriptor table driver for SMMUv3
+ *
+ * Copyright (C) 2018 ARM Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "iommu-pasid.h"
+
+#define CTXDESC_CD_DWORDS  8
+#define CTXDESC_CD_0_TCR_T0SZ_SHIFT0
+#define ARM64_TCR_T0SZ_SHIFT   0
+#define ARM64_TCR_T0SZ_MASK0x1fUL
+#define CTXDESC_CD_0_TCR_TG0_SHIFT 6
+#define ARM64_TCR_TG0_SHIFT14
+#define ARM64_TCR_TG0_MASK 0x3UL
+#define CTXDESC_CD_0_TCR_IRGN0_SHIFT   8
+#define ARM64_TCR_IRGN0_SHIFT  8
+#define ARM64_TCR_IRGN0_MASK   0x3UL
+#define CTXDESC_CD_0_TCR_ORGN0_SHIFT   10
+#define ARM64_TCR_ORGN0_SHIFT  10
+#define ARM64_TCR_ORGN0_MASK   0x3UL
+#define CTXDESC_CD_0_TCR_SH0_SHIFT 12
+#define ARM64_TCR_SH0_SHIFT12
+#define ARM64_TCR_SH0_MASK 0x3UL
+#define CTXDESC_CD_0_TCR_EPD0_SHIFT14
+#define ARM64_TCR_EPD0_SHIFT   7
+#define ARM64_TCR_EPD0_MASK0x1UL
+#define CTXDESC_CD_0_TCR_EPD1_SHIFT30
+#define ARM64_TCR_EPD1_SHIFT   23
+#define ARM64_TCR_EPD1_MASK0x1UL
+
+#define CTXDESC_CD_0_ENDI  (1UL << 15)
+#define CTXDESC_CD_0_V (1UL << 31)
+
+#define CTXDESC_CD_0_TCR_IPS_SHIFT 32
+#define ARM64_TCR_IPS_SHIFT32
+#define ARM64_TCR_IPS_MASK 0x7UL
+#define CTXDESC_CD_0_TCR_TBI0_SHIFT38
+#define ARM64_TCR_TBI0_SHIFT   37
+#define ARM64_TCR_TBI0_MASK0x1UL
+
+#define CTXDESC_CD_0_AA64  (1UL << 41)
+#define CTXDESC_CD_0_S (1UL << 44)
+#define CTXDESC_CD_0_R (1UL << 45)
+#define