Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-11 Thread Jan Kiszka 
On 2018-02-12 05:53, bharat gohil wrote:
> Hello Jan,
> 
> Please find attached root cell config file.

> /*
>  * Jailhouse, a Linux-based partitioning hypervisor
>  *
>  * Test configuration for X (2-Cortex-A72, 4-Cortex-A35, 2GB RAM)
>  *
>  * Copyright (c) Siemens AG, 2014-2016
>  *
>  * Authors:
>  *  Jan Kiszka 
>  *
>  * This work is licensed under the terms of the GNU GPL, version 2.  See
>  * the COPYING file in the top-level directory.
>  */
> 
> #include 
> #include 
> 
> #define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
> 
> struct {
>   struct jailhouse_system header;
>   __u64 cpus[1];
>   struct jailhouse_memory mem_regions[8];

You are preparing for 8 regions here, but only 6 are initialized below.
First thing to fix.

>   struct jailhouse_irqchip irqchips[1];
>   struct jailhouse_pci_device pci_devices[1];
> } __attribute__((packed)) config = {
>   .header = {
>   .signature = JAILHOUSE_SYSTEM_SIGNATURE,
>   .revision = JAILHOUSE_CONFIG_REVISION,
>   .hypervisor_memory = {
>   .phys_start = 0x7C00,
>   .size = 0x400,
>   },
>   .debug_console = {
>   .address = 0x11002000,
>   .size = 0x1000,
>   .flags = JAILHOUSE_CON1_TYPE_8250 |
>JAILHOUSE_CON1_ACCESS_MMIO |
>JAILHOUSE_CON1_REGDIST_4 |
>JAILHOUSE_CON2_TYPE_ROOTPAGE,
>   },
>   .platform_info = {
>   .pci_mmconfig_base = 0x200,
>   .pci_mmconfig_end_bus = 0,
>   .pci_is_virtual = 1,
>   .arm = {
>   .gic_version = 2,
>   .gicd_base = 0x1051,
>   .gicc_base = 0x1052,
>   .gich_base = 0x1054,
>   .gicv_base = 0x1056,
>   .maintenance_irq = 25,
>   },
>   },
>   .root_cell = {
>   .name = "X",
> 
>   .cpu_set_size = sizeof(config.cpus),
>   .num_memory_regions = ARRAY_SIZE(config.mem_regions),
>   .num_irqchips = ARRAY_SIZE(config.irqchips),
>   .num_pci_devices = ARRAY_SIZE(config.pci_devices),
> 
>   .vpci_irq_base = 108,
>   },
>   },
> 
>   .cpus = {
>   0x3F,
>   },
> 
>   .mem_regions = {
>   /* CCU */ {
> .phys_start = 0x1000,
> .virt_start = 0x1000,
> .size = 0x200,
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
> JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
> },
>   /* MMIO 1 (permissive) */ {
>   .phys_start = 0x1300,
>   .virt_start = 0x1300,
>   .size =  0x400,
>   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
>   JAILHOUSE_MEM_IO,
>   },
>   /* pinctrl PA */ {
>   .phys_start = 0x1800,
>   .virt_start = 0x1800,
>   .size = 0x200,
>   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
>   JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
>   },
>   /* RAM */ {
>   .phys_start = 0x4000,
>   .virt_start = 0x4000,
>   .size =0x02FF,

This switches the region in to sub-page mode, and that may cause this
surprising behavior. Just do size + 1, as it is correct.

>   .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | 
> JAILHOUSE_MEM_EXECUTE,
>   },
>/* RAM*/  /*{
> .phys_start = 0x40EC,
> .virt_start = 0x40EC,
> .size =0x0213,
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | 
> JAILHOUSE_MEM_EXECUTE,
> },*/
>   /**THIS HOLE FOR ARM TRUSTED FIRMWARE**/
> 
>/* RAM*/  {
> .phys_start = 0x4304,
> .virt_start = 0x4304,
> .size =0x38EC,
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | 
> JAILHOUSE_MEM_EXECUTE,
> },
> 
>   /* IVSHMEM shared memory region */ {
>   .phys_start = 0x7BF0,
>

Re: Jailhouse on OrangePI PC2 and A35/A72 based board

2018-02-11 Thread bharat gohil 
Hello Jan,

Please find attached root cell config file.

Thanks,
Bharat

On Sat, Feb 10, 2018 at 2:23 PM, Jan Kiszka  wrote:

> On 2018-02-10 08:46, bharat gohil wrote:
> >
> > Yes, that is correct.
> > When starting root cell,
> > jailhouse enable .cell
>
> Could you share your config file?
>
> Also, you have local modifications on your tree. What are they changing,
> just configuration files?
>
> Jan
>
> > Thanks,
> > Bharat
> >
> >
> > On 07-Feb-2018 5:39 PM, "Jan Kiszka"  > > wrote:
> >
> > On 2018-02-07 10:27, bharat gohil wrote:
> > > Hi
> > >
> > > I was trying to Run jailhouse on two board i.e OrangePi PC2 and
> > Quad core A35/A72 based SoC.
> > >
> > > I am able run Jailhouse on OrangePI PC2 and ran simple application
> > on single core which blinks the LED which works fine on OrangePI PC2
> > board.
> > >
> > > But I have problem running Jailhouse on other board which has A35
> > and A72.
> > >
> > > I got following crash when enable Jailhouse on this board,
> > >
> > > Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 0
> > > Code location: 0xc0200060
> > > Page pool usage after early setup: mem 61/16356, remap 48/131072
> > > Initializing processors:
> > >  CPU 0... OK
> > >  CPU 1... OK
> > >  CPU 2... OK
> > > Adding virtual PCI device 00:00.0 to cell "Dione"
> > > Page pool usage after late setup: mem 66/16356, remap 53/131072
> > > FATAL: instruction abort at 0x40ebdee8
> > >
> > > FATAL: unhandled trap (exception class 0x20)
> > > Cell state before exception:
> > >  pc: ff80008f0ee8   lr: ff80008f0ee8 spsr: 61c5 EL1
> > >  sp: ffc02f003bb0  esr: 20 1 086
> > >  x0:    x1:    x2: 
> > >  x3:    x4:    x5: 
> > >  x6:    x7:    x8: 
> > >  x9:   x10:   x11: 
> > > x12:   x13:   x14: 
> > > x15:   x16:   x17: 
> > > x18:   x19: ff80008f4910  x20: ff801000
> > > x21: ff801000  x22:   x23: 0140
> > > x24: ff80008f4600  x25: ff8008d26de0  x26: ff801000
> > > x27: 02c4  x28: ffc02f00  x29: ffc02f003bb0
> > >
> > > Parking CPU 2 (Cell: "X")
> > >
> > > It generate exception at 0x40ebdee8 which is DDR address.
> > >
> > > I have mentioned DDR range including above address in to the
> > root-cell configuration like this,
> > >  /* RAM */ {
> > > .phys_start = 0x4000,
> > > .virt_start = 0x4000,
> > > .size =0x02FF,
> > > .flags = JAILHOUSE_MEM_READ |
> > JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE,
> > > },
> > >
> > > Can anyone help me to figure out what is the problem or how to
> > debug and resolve this issue?
> >
> > Only the root cell is running at this point, right? There is no
> overlap
> > of other regions or the hypervisor region itself?
> >
> > Jan
> >
> > --
> > Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> > Corporate Competence Center Embedded Linux
> >
> >
> > --
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>
>


-- 
Regards,
Bharat Gohil
Sr.Software Engineer
bharat.go...@harman.com
+919427054633

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/*
 * Jailhouse, a Linux-based partitioning hypervisor
 *
 * Test configuration for X (2-Cortex-A72, 4-Cortex-A35, 2GB RAM)
 *
 * Copyright (c) Siemens AG, 2014-2016
 *
 * Authors:
 *  Jan Kiszka 
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 */

#include 
#include 

#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])

struct {
	struct jailhouse_system header;
	__u64 cpus[1];
	struct jailhouse_memory mem_regions[8];
	struct jailhouse_irqchip irqchips[1];
	struct jailhouse_pci_device pci_devices[1];
}