Re: How to measure the RAM read/write performance
> >> >> [ 2.331207] 6174 e92d4007 e59f301c e59cc000 e1a02001 e59f1014 >> >> >> e58dc000 >> >> >> eb055aab e3a0 >> >> >> [2.339385] 6194 e8bd800e c0958220 c0791c27 c0791c1b e121f007 >> >> >> e1a4 >> >> >> e1a0e006 e1a0f005 >> >> >> [2.347534] 61b4 eb02959a e320f000 e59f300c e5932000 e2822001 >> >> >> e5832000 >> >> >> e12fff1e c0958224 >> >> >> [2.355682] 61d4 e59f300c e5932000 e2422001 e5832000 e12fff1e >> >> >> c0958224 >> >> >> e12fff1e e12fff1e >> >> >> [2.363861] 61f4 e12fff1e e12fff1e eafe e59f3014 e92d4010 >> >> >> e5933004 >> >> >> e353 08bd8010 >> >> >> [2.372009] 6214 e12fff33 e8bd8010 c0958224 e59f3014 e1a01000 >> >> >> e92d4010 >> >> >> e5d3 e1a0e00f >> >> >> [2.380187] Process swapper (pid: 1, stack limit = 0xe982a2e8) >> >> >> [2.385986] Stack: (0xe982bf98 to 0xe982c000) >> >> >> [2.390319] bf80: >> >> >> 3ffd a27e >> >> >> [2.398498] bfa0: c0037b4c c0022e94 c003f3fc e9814a80 >> >> >> 00373231 >> >> >> >> >> >> [2.406646] bfc0: 0236 c0037b4c c003818c c00461b4 >> >> >> 0013 >> >> >> >> >> >> [2.414825] bfe0: c0008374 c0008300 c00461b4 >> >> >> c00461b4 >> >> >> >> >> >> [2.423004] [] (sand_misc_init+0x4c/0xac) from >> >> >> [] >> >> >> (do_one_initcall+0xd0/0x1a4) >> >> >> [2.431915] [] (do_one_initcall+0xd0/0x1a4) from >> >> >> [] >> >> >> (kernel_init+0x74/0x118) >> >> >> [2.440673] [] (kernel_init+0x74/0x118) from >> >> >> [] >> >> >> (kernel_thread_exit+0x0/0x8) >> >> >> [2.449462] Code: e58d4000 e3033fff ea07 e59d2000 (e7952002) >> >> >> [2.455566] ---[ end trace f76f3c76dcb9b9ef ]--- >> >> >> [2.460144] Kernel panic - not syncing: Attempted to kill init! >> >> >> [2.466064] [] (unwind_backtrace+0x0/0x12c) from >> >> >> [] >> >> >> (panic+0x90/0x1bc) >> >> >> [2.474304] [] (panic+0x90/0x1bc) from [] >> >> >> (do_exit+0xb8/0x734) >> >> >> [2.481842] [] (do_exit+0xb8/0x734) from [] >> >> >> (die+0x208/0x23c) >> >> >> [2.489318] [] (die+0x208/0x23c) from [] >> >> >> (__do_kernel_fault+0x64/0x84) >> >> >> [2.497558] [] (__do_kernel_fault+0x64/0x84) from >> >> >> [] (do_page_fault+0x268/0x288) >> >> >> [2.506683] [] (do_page_fault+0x268/0x288) from >> >> >> [] >> >> >> (do_DataAbort+0x34/0x94) >> >> >> [2.515350] [] (do_DataAbort+0x34/0x94) from >> >> >> [] >> >> >> (__dabt_svc+0x4c/0x60) >> >> >> [2.523590] Exception stack(0xe982bf50 to 0xe982bf98) >> >> >> [2.528625] bf40: 0063 >> >> >> c07ea2cf >> >> >> 3ffd 3fff >> >> >> [2.536804] bf60: ea828000 c00461b4 >> >> >> >> >> >> >> >> >> [2.544952] bf80: e982bf98 c0022ed0 c0022ee0 8013 >> >> >> >> >> >> [2.551544] [] (__dabt_svc+0x4c/0x60) from [] >> >> >> (sand_misc_init+0x4c/0xac) >> >> >> [2.559967] [] (sand_misc_init+0x4c/0xac) from >> >> >> [] >> >> >> (do_one_initcall+0xd0/0x1a4) >> >> >> [2.568908] [] (do_one_initcall+0xd0/0x1a4) from >> >> >> [] >> >> >> (kernel_init+0x74/0x118) >> >> >> [2.577667] [] (kernel_init+0x74/0x118) from >> >> >> [] >> >> >> (kernel_thread_exit+0x0/0x8) >> >> >> >> >> >> >> >> >> Any idea what went wrong. >> >> >> I am sure about the ioremap() start address, thats what i reserved >> >> >> in >> >> >> ATAGS. >> >> >> >> >> >> Thanks >> >> >> Sandeep >> >> >> >> >> >> >> >> >> On Thu, Feb 28, 2013 at 10:30 AM, sandeep kumar >> >> >> wrote: >> >> >>> >> >> >>> >1. use early_param to get the physical start address and size of >> >> >>> > test_region, or you can just ignore this step and hard code to >> >> >>> > 510M >> >> >>> > and 2M >> >> >>> > for test purpose only. >> >> >>> >> >> >>> >2. use ioremap_nocache() to map this region to a virtual region. >> >> >>> > note >> >> >>> > that this funtion may fail if you are asking a very large vitual >> >> >>> > memroy >> >> >>> > region. >> >> >>> >> >> >>> Sounds good, i am gonna try this and let you know.. :) >> >> >>> >> >> >>> >> >> >>> On Wed, Feb 27, 2013 at 8:19 PM, buyitian wrote: >> >> >>>> >> >> >>>> >> >> >>>> > From: bu...@live.cn >> >> >>>> > To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org >> >> >>>> > Subject: RE: How to measure the RAM read/write performance >> >> >>>> > Date: Wed, 27 Feb 2013 22:33:15 +0800 >> >> >>>> > CC: dhyla...@gmail.com >> >> >>>> > >> >> >>>> > >> >> >>>> > > From: coolsandyfor...@gmail.com >> >> >>>> > > Date: Tue, 26 Feb 2013 17:01:54 +0530 >> >> >>>> > > Subject: How to measure the RAM read/write performance >> >> >>>> > > To: kernelnewbies@kernelnewbies.org >> >> >>>> > > CC: dhyla...@gmail.com >> >> >>>> > > >> >> >>>> > > Hi All >> >> >>>> > > In performance benchmark tools, When we profile read/write >> >> >>>> > > timings >> >> >>>> > > mostly, those read/writes are done to cache only. >> >> >>>> > > >> >> >>>> > > I want to measure my DDR(RAM chip) performance. >> >> >>>> > > So i want to make sure, every read/write should happen to DDR >> >> >>>> > > RAM >> >> >>>> > > chip only. >> >> >>>> > > >> >> >>>> > > How can i achieve this...Any ideas/suggestions...? >> >> >>>> > >> >> >>>> > try to reserve a large region from bootloader(L4 in Qualcomm >> >> >>>> > platform), let's say it is 10MB continuous physical memory. >> >> >>>> >> >> >>>> sorry, to be accurate, reserve physical memory is done by kernel >> >> >>>> cmdline, this cmdline parameter can be passed from L4 to kernel, >> >> >>>> or >> >> >>>> configed >> >> >>>> by kernel itself. >> >> >>>> the cmdline will be like below: >> >> >>>> mem=510M@0 test_region=2M@510M >> >> >>>> >> >> >>>> above example tells kernel you have totally 512MB physical memory, >> >> >>>> but >> >> >>>> kernel will only use the first 510MB, the latter 2MB memory is >> >> >>>> used >> >> >>>> by you. >> >> >>>> how to map and use this region depends on you. >> >> >>>> >> >> >>>> > in kernel, map this region to an continuous virtual region, note >> >> >>>> > that >> >> >>>> > the pgprot should be uncachable since you want to test without >> >> >>>> > cache. >> >> >>>> >> >> >>>> 1. use early_param to get the physical start address and size of >> >> >>>> test_region, or you can just ignore this step and hard code to >> >> >>>> 510M >> >> >>>> and 2M >> >> >>>> for test purpose only. >> >> >>>> >> >> >>>> 2. use ioremap_nocache() to map this region to a virtual region. >> >> >>>> note >> >> >>>> that this funtion may fail if you are asking a very large vitual >> >> >>>> memroy >> >> >>>> region. >> >> >>>> >> >> >>>> > once you configed like this, you can read/write to this vitual >> >> >>>> > region >> >> >>>> > without data cache invovled. >> >> >>>> > >> >> >>>> > > >> >> >>>> > > -- >> >> >>>> > > With regards, >> >> >>>> > > Sandeep Kumar Anantapalli, >> >> >>>> > > >> >> >>>> > > ___ Kernelnewbies >> >> >>>> > > mailing >> >> >>>> > > list Kernelnewbies@kernelnewbies.org >> >> >>>> > > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >> >> >>>> > ___ >> >> >>>> > Kernelnewbies mailing list >> >> >>>> > Kernelnewbies@kernelnewbies.org >> >> >>>> > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >> >> >>> >> >> >>> >> >> >>> >> >> >>> >> >> >>> -- >> >> >>> With regards, >> >> >>> Sandeep Kumar Anantapalli, >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> -- >> >> >> With regards, >> >> >> Sandeep Kumar Anantapalli, >> >> > >> >> > >> >> > >> >> > >> >> > -- >> >> > With regards, >> >> > Sandeep Kumar Anantapalli, >> >> > >> >> > ___ >> >> > Kernelnewbies mailing list >> >> > Kernelnewbies@kernelnewbies.org >> >> > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >> >> > >> > >> > >> > >> > >> > -- >> > With regards, >> > Sandeep Kumar Anantapalli, > > > > > -- > With regards, > Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
d >> >> [2.216613] a30c 736b3a29 635f7465 74616572 6e615f65 64615f64 >> >> 61662064 >> >> 000a6c69 703e343c >> >> [2.224792] a32c 3a6d656d 6d6f7320 69687465 6920676e 65762073 >> >> 77207972 >> >> 676e6f72 6f79202c >> >> [2.232940] a34c 72612075 6c632065 6e69736f 20612067 62206d76 >> >> 696b6361 >> >> 6120676e 6c61206e >> >> [2.241119] >> >> [2.241119] R5: 0xea827f80: >> >> [2.245361] 7f80 >> >> >> >> >> >> [2.253509] 7fa0 >> >> >> >> >> >> [2.261688] 7fc0 >> >> >> >> >> >> [2.269836] 7fe0 >> >> >> >> >> >> [2.278015] 8000 >> >> >> >> >> >> [2.286163] 8020 >> >> >> >> >> >> [2.294311] 8040 >> >> >> >> >> >> [2.302490] 8060 >> >> >> >> >> >> [2.310638] >> >> [2.310638] R6: 0xc0046134: >> >> [2.314880] 6134 eb038dff eb02a1f9 e1a03007 e1a5 e1a02006 >> >> eb025566 >> >> e59f3008 e5834000 >> >> [2.323059] 6154 e8bd41f0 ea0259b3 c09059d4 c08fbcd4 c064e808 >> >> c0791c0d >> >> c0958220 e59fc020 >> >> [2.331207] 6174 e92d4007 e59f301c e59cc000 e1a02001 e59f1014 >> >> e58dc000 >> >> eb055aab e3a0 >> >> [2.339385] 6194 e8bd800e c0958220 c0791c27 c0791c1b e121f007 >> >> e1a4 >> >> e1a0e006 e1a0f005 >> >> [2.347534] 61b4 eb02959a e320f000 e59f300c e5932000 e2822001 >> >> e5832000 >> >> e12fff1e c0958224 >> >> [2.355682] 61d4 e59f300c e5932000 e2422001 e5832000 e12fff1e >> >> c0958224 >> >> e12fff1e e12fff1e >> >> [2.363861] 61f4 e12fff1e e12fff1e eafe e59f3014 e92d4010 >> >> e5933004 >> >> e353 08bd8010 >> >> [2.372009] 6214 e12fff33 e8bd8010 c0958224 e59f3014 e1a01000 >> >> e92d4010 >> >> e5d3 e1a0e00f >> >> [2.380187] Process swapper (pid: 1, stack limit = 0xe982a2e8) >> >> [2.385986] Stack: (0xe982bf98 to 0xe982c000) >> >> [2.390319] bf80: >> >> 3ffd a27e >> >> [2.398498] bfa0: c0037b4c c0022e94 c003f3fc e9814a80 >> >> 00373231 >> >> >> >> [2.406646] bfc0: 0236 c0037b4c c003818c c00461b4 >> >> 00000013 >> >> >> >> [2.414825] bfe0: c0008374 c0008300 c00461b4 >> >> c00461b4 >> >> >> >> [2.423004] [] (sand_misc_init+0x4c/0xac) from >> >> [] >> >> (do_one_initcall+0xd0/0x1a4) >> >> [2.431915] [] (do_one_initcall+0xd0/0x1a4) from >> >> [] >> >> (kernel_init+0x74/0x118) >> >> [2.440673] [] (kernel_init+0x74/0x118) from [] >> >> (kernel_thread_exit+0x0/0x8) >> >> [2.449462] Code: e58d4000 e3033fff ea07 e59d2000 (e7952002) >> >> [2.455566] ---[ end trace f76f3c76dcb9b9ef ]--- >> >> [2.460144] Kernel panic - not syncing: Attempted to kill init! >> >> [2.466064] [] (unwind_backtrace+0x0/0x12c) from >> >> [] >> >> (panic+0x90/0x1bc) >> >> [2.474304] [] (panic+0x90/0x1bc) from [] >> >> (do_exit+0xb8/0x734) >> >> [2.481842] [] (do_exit+0xb8/0x734) from [] >> >> (die+0x208/0x23c) >> >> [2.489318] [] (die+0x208/0x23c) from [] >> >> (__do_kernel_fault+0x64/0x84) >> >> [2.497558] [] (__do_kernel_fault+0x64/0x84) from >> >> [] (do_page_fault+0x268/0x288) >> >> [2.506683] [] (do_page_fault+0x268/0x288) from >> >> [] >> >> (do_DataAbort+0x34/0x94) >> >> [2.515350] [] (do_DataAbort+0x
Re: How to measure the RAM read/write performance
e59f3008 e5834000 > >> [2.323059] 6154 e8bd41f0 ea0259b3 c09059d4 c08fbcd4 c064e808 > c0791c0d > >> c0958220 e59fc020 > >> [2.331207] 6174 e92d4007 e59f301c e59cc000 e1a02001 e59f1014 > e58dc000 > >> eb055aab e3a0 > >> [2.339385] 6194 e8bd800e c0958220 c0791c27 c0791c1b e121f007 > e1a4 > >> e1a0e006 e1a0f005 > >> [2.347534] 61b4 eb02959a e320f000 e59f300c e5932000 e2822001 > e5832000 > >> e12fff1e c0958224 > >> [2.355682] 61d4 e59f300c e5932000 e2422001 e5832000 e12fff1e > c0958224 > >> e12fff1e e12fff1e > >> [2.363861] 61f4 e12fff1e e12fff1e eafe e59f3014 e92d4010 > e5933004 > >> e353 08bd8010 > >> [2.372009] 6214 e12fff33 e8bd8010 c0958224 e59f3014 e1a01000 > e92d4010 > >> e5d3 e1a0e00f > >> [2.380187] Process swapper (pid: 1, stack limit = 0xe982a2e8) > >> [2.385986] Stack: (0xe982bf98 to 0xe982c000) > >> [2.390319] bf80: > >> 3ffd a27e > >> [2.398498] bfa0: c0037b4c c0022e94 c003f3fc e9814a80 > 00373231 > >> > >> [2.406646] bfc0: 0236 c0037b4c c003818c c00461b4 > 0013 > >> > >> [2.414825] bfe0: c0008374 c0008300 c00461b4 > c00461b4 > >> > >> [2.423004] [] (sand_misc_init+0x4c/0xac) from [] > >> (do_one_initcall+0xd0/0x1a4) > >> [2.431915] [] (do_one_initcall+0xd0/0x1a4) from > [] > >> (kernel_init+0x74/0x118) > >> [2.440673] [] (kernel_init+0x74/0x118) from [] > >> (kernel_thread_exit+0x0/0x8) > >> [2.449462] Code: e58d4000 e3033fff ea07 e59d2000 (e7952002) > >> [2.455566] ---[ end trace f76f3c76dcb9b9ef ]--- > >> [2.460144] Kernel panic - not syncing: Attempted to kill init! > >> [2.466064] [] (unwind_backtrace+0x0/0x12c) from > [] > >> (panic+0x90/0x1bc) > >> [2.474304] [] (panic+0x90/0x1bc) from [] > >> (do_exit+0xb8/0x734) > >> [2.481842] [] (do_exit+0xb8/0x734) from [] > >> (die+0x208/0x23c) > >> [ 2.489318] [] (die+0x208/0x23c) from [] > >> (__do_kernel_fault+0x64/0x84) > >> [2.497558] [] (__do_kernel_fault+0x64/0x84) from > >> [] (do_page_fault+0x268/0x288) > >> [2.506683] [] (do_page_fault+0x268/0x288) from > [] > >> (do_DataAbort+0x34/0x94) > >> [2.515350] [] (do_DataAbort+0x34/0x94) from [] > >> (__dabt_svc+0x4c/0x60) > >> [2.523590] Exception stack(0xe982bf50 to 0xe982bf98) > >> [2.528625] bf40: 0063 > c07ea2cf > >> 3ffd 3fff > >> [2.536804] bf60: ea828000 c00461b4 > > >> > >> [2.544952] bf80: e982bf98 c0022ed0 c0022ee0 8013 > > >> [2.551544] [] (__dabt_svc+0x4c/0x60) from [] > >> (sand_misc_init+0x4c/0xac) > >> [2.559967] [] (sand_misc_init+0x4c/0xac) from [] > >> (do_one_initcall+0xd0/0x1a4) > >> [2.568908] [] (do_one_initcall+0xd0/0x1a4) from > [] > >> (kernel_init+0x74/0x118) > >> [2.577667] [] (kernel_init+0x74/0x118) from [] > >> (kernel_thread_exit+0x0/0x8) > >> > >> > >> Any idea what went wrong. > >> I am sure about the ioremap() start address, thats what i reserved in > >> ATAGS. > >> > >> Thanks > >> Sandeep > >> > >> > >> On Thu, Feb 28, 2013 at 10:30 AM, sandeep kumar > >> wrote: > >>> > >>> >1. use early_param to get the physical start address and size of > >>> > test_region, or you can just ignore this step and hard code to 510M > and 2M > >>> > for test purpose only. > >>> > >>> >2. use ioremap_nocache() to map this region to a virtual region. note > >>> > that this funtion may fail if you are asking a very large vitual > memroy > >>> > region. > >>> > >>> Sounds good, i am gonna try this and let you know.. :) > >>> > >>> > >>> On Wed, Feb 27, 2013 at 8:19 PM, buyitian wrote: > >>>> > >>>> > >>>> > From: bu...@live.cn > >>>> > To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org > >>>> > Subject: RE: How to measure the RAM read/write performance > >>>> > Date
Re: How to measure the RAM read/write performance
On Tue, Feb 26, 2013 at 6:50 PM, ankur dwivedi wrote:
> I am not sure but what if you make the variable as a volatile?
Volatile in simple terms
==
Consider this eg:
1 int main(void){
2 int a, x, y;
3 x=a;
4 y=a;
5 }
Line 3 with be converted to a LDR instruction.
Line 4 is where the compiler optimization comes in. It may be loaded
from the previous loaded register.
Line 3: ldr r0[r1]; r1 is having the address of a
Line 4: mov r2 r0; because we have value of a already in r0.
But if a is volatile variable, then compiler places ldr for both
instructions(ie for x=a and y = a).
so line 4 will change as follows.
Line 3: ldr r0[r1];r1 is having the address of a
Line 4: ldr r2[r1]; r1 is having the address of a
But if cache is enabled, ldr can fetch the data from cache if present.
So volatile cannot help us here.
Thanks,
Arun
>
> On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar
> wrote:
>>
>> Hi All
>> In performance benchmark tools, When we profile read/write timings mostly,
>> those read/writes are done to cache only.
>>
>> I want to measure my DDR(RAM chip) performance.
>> So i want to make sure, every read/write should happen to DDR RAM chip
>> only.
>>
>> How can i achieve this...Any ideas/suggestions...?
>>
>> --
>> With regards,
>> Sandeep Kumar Anantapalli,
>>
>> ___
>> Kernelnewbies mailing list
>> Kernelnewbies@kernelnewbies.org
>> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
>>
>
>
>
> --
> Thanks
>
> Ankur Dwivedi
>
>
> ___
> Kernelnewbies mailing list
> Kernelnewbies@kernelnewbies.org
> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
>
___
Kernelnewbies mailing list
Kernelnewbies@kernelnewbies.org
http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
t syncing: Attempted to kill init! >> [2.466064] [] (unwind_backtrace+0x0/0x12c) from [] >> (panic+0x90/0x1bc) >> [2.474304] [] (panic+0x90/0x1bc) from [] >> (do_exit+0xb8/0x734) >> [2.481842] [] (do_exit+0xb8/0x734) from [] >> (die+0x208/0x23c) >> [2.489318] [] (die+0x208/0x23c) from [] >> (__do_kernel_fault+0x64/0x84) >> [2.497558] [] (__do_kernel_fault+0x64/0x84) from >> [] (do_page_fault+0x268/0x288) >> [2.506683] [] (do_page_fault+0x268/0x288) from [] >> (do_DataAbort+0x34/0x94) >> [2.515350] [] (do_DataAbort+0x34/0x94) from [] >> (__dabt_svc+0x4c/0x60) >> [2.523590] Exception stack(0xe982bf50 to 0xe982bf98) >> [2.528625] bf40: 0063 c07ea2cf >> 3ffd 3fff >> [2.536804] bf60: ea828000 c00461b4 >> >> [2.544952] bf80: 00000000 e982bf98 c0022ed0 c0022ee0 8013 >> [2.551544] [] (__dabt_svc+0x4c/0x60) from [] >> (sand_misc_init+0x4c/0xac) >> [2.559967] [] (sand_misc_init+0x4c/0xac) from [] >> (do_one_initcall+0xd0/0x1a4) >> [2.568908] [] (do_one_initcall+0xd0/0x1a4) from [] >> (kernel_init+0x74/0x118) >> [2.577667] [] (kernel_init+0x74/0x118) from [] >> (kernel_thread_exit+0x0/0x8) >> >> >> Any idea what went wrong. >> I am sure about the ioremap() start address, thats what i reserved in >> ATAGS. >> >> Thanks >> Sandeep >> >> >> On Thu, Feb 28, 2013 at 10:30 AM, sandeep kumar >> wrote: >>> >>> >1. use early_param to get the physical start address and size of >>> > test_region, or you can just ignore this step and hard code to 510M and 2M >>> > for test purpose only. >>> >>> >2. use ioremap_nocache() to map this region to a virtual region. note >>> > that this funtion may fail if you are asking a very large vitual memroy >>> > region. >>> >>> Sounds good, i am gonna try this and let you know.. :) >>> >>> >>> On Wed, Feb 27, 2013 at 8:19 PM, buyitian wrote: >>>> >>>> >>>> > From: bu...@live.cn >>>> > To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org >>>> > Subject: RE: How to measure the RAM read/write performance >>>> > Date: Wed, 27 Feb 2013 22:33:15 +0800 >>>> > CC: dhyla...@gmail.com >>>> > >>>> > >>>> > > From: coolsandyfor...@gmail.com >>>> > > Date: Tue, 26 Feb 2013 17:01:54 +0530 >>>> > > Subject: How to measure the RAM read/write performance >>>> > > To: kernelnewbies@kernelnewbies.org >>>> > > CC: dhyla...@gmail.com >>>> > > >>>> > > Hi All >>>> > > In performance benchmark tools, When we profile read/write timings >>>> > > mostly, those read/writes are done to cache only. >>>> > > >>>> > > I want to measure my DDR(RAM chip) performance. >>>> > > So i want to make sure, every read/write should happen to DDR RAM >>>> > > chip only. >>>> > > >>>> > > How can i achieve this...Any ideas/suggestions...? >>>> > >>>> > try to reserve a large region from bootloader(L4 in Qualcomm >>>> > platform), let's say it is 10MB continuous physical memory. >>>> >>>> sorry, to be accurate, reserve physical memory is done by kernel >>>> cmdline, this cmdline parameter can be passed from L4 to kernel, or >>>> configed >>>> by kernel itself. >>>> the cmdline will be like below: >>>> mem=510M@0 test_region=2M@510M >>>> >>>> above example tells kernel you have totally 512MB physical memory, but >>>> kernel will only use the first 510MB, the latter 2MB memory is used by you. >>>> how to map and use this region depends on you. >>>> >>>> > in kernel, map this region to an continuous virtual region, note that >>>> > the pgprot should be uncachable since you want to test without cache. >>>> >>>> 1. use early_param to get the physical start address and size of >>>> test_region, or you can just ignore this step and hard code to 510M and 2M >>>> for test purpose only. >>>> >>>> 2. use ioremap_nocache() to map this region to a virtual region. note >>>> that this funtion may fail if you are asking a very large vitual memroy >>>> region. >>>> >>>> > once you configed like this, you can read/write to this vitual region >>>> > without data cache invovled. >>>> > >>>> > > >>>> > > -- >>>> > > With regards, >>>> > > Sandeep Kumar Anantapalli, >>>> > > >>>> > > ___ Kernelnewbies >>>> > > mailing >>>> > > list Kernelnewbies@kernelnewbies.org >>>> > > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >>>> > ___ >>>> > Kernelnewbies mailing list >>>> > Kernelnewbies@kernelnewbies.org >>>> > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >>> >>> >>> >>> >>> -- >>> With regards, >>> Sandeep Kumar Anantapalli, >> >> >> >> >> -- >> With regards, >> Sandeep Kumar Anantapalli, > > > > > -- > With regards, > Sandeep Kumar Anantapalli, > > ___ > Kernelnewbies mailing list > Kernelnewbies@kernelnewbies.org > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
ll+0xd0/0x1a4) from [] > (kernel_init+0x74/0x118) > [2.577667] [] (kernel_init+0x74/0x118) from [] > (kernel_thread_exit+0x0/0x8) > > > Any idea what went wrong. > I am sure about the ioremap() start address, thats what i reserved in > ATAGS. > > Thanks > Sandeep > > > On Thu, Feb 28, 2013 at 10:30 AM, sandeep kumar > wrote: > >> >1. use early_param to get the physical start address and size of >> test_region, or you can just ignore this step and hard code to 510M and 2M >> for test purpose only. >> >> >2. use ioremap_nocache() to map this region to a virtual region. note >> that this funtion may fail if you are asking a very large vitual memroy >> region. >> >> Sounds good, i am gonna try this and let you know.. :) >> >> >> On Wed, Feb 27, 2013 at 8:19 PM, buyitian wrote: >> >>> >>> > From: bu...@live.cn >>> > To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org >>> > Subject: RE: How to measure the RAM read/write performance >>> > Date: Wed, 27 Feb 2013 22:33:15 +0800 >>> > CC: dhyla...@gmail.com >>> > >>> > >>> > > From: coolsandyfor...@gmail.com >>> > > Date: Tue, 26 Feb 2013 17:01:54 +0530 >>> > > Subject: How to measure the RAM read/write performance >>> > > To: kernelnewbies@kernelnewbies.org >>> > > CC: dhyla...@gmail.com >>> > > >>> > > Hi All >>> > > In performance benchmark tools, When we profile read/write timings >>> > > mostly, those read/writes are done to cache only. >>> > > >>> > > I want to measure my DDR(RAM chip) performance. >>> > > So i want to make sure, every read/write should happen to DDR RAM >>> chip only. >>> > > >>> > > How can i achieve this...Any ideas/suggestions...? >>> > >>> > try to reserve a large region from bootloader(L4 in Qualcomm >>> platform), let's say it is 10MB continuous physical memory. >>> >>> sorry, to be accurate, reserve physical memory is done by kernel >>> cmdline, this cmdline parameter can be passed from L4 to kernel, or >>> configed by kernel itself. >>> the cmdline will be like below: >>> mem=510M@0 test_region=2M@510M >>> >>> above example tells kernel you have totally 512MB physical memory, but >>> kernel will only use the first 510MB, the latter 2MB memory is used by you. >>> how to map and use this region depends on you. >>> >>> > in kernel, map this region to an continuous virtual region, note that >>> the pgprot should be uncachable since you want to test without cache. >>> >>> 1. use early_param to get the physical start address and size of >>> test_region, or you can just ignore this step and hard code to 510M and 2M >>> for test purpose only. >>> >>> 2. use ioremap_nocache() to map this region to a virtual region. note >>> that this funtion may fail if you are asking a very large vitual memroy >>> region. >>> >>> > once you configed like this, you can read/write to this vitual region >>> without data cache invovled. >>> > >>> > > >>> > > -- >>> > > With regards, >>> > > Sandeep Kumar Anantapalli, >>> > > >>> > > ___ Kernelnewbies mailing >>> > > list Kernelnewbies@kernelnewbies.org >>> > > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >>> > ___ >>> > Kernelnewbies mailing list >>> > Kernelnewbies@kernelnewbies.org >>> > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >>> >>> >> >> >> >> -- >> With regards, >> Sandeep Kumar Anantapalli, >> > > > > -- > With regards, > Sandeep Kumar Anantapalli, > -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
000 [2.302490] 8060 [2.310638] [2.310638] R6: 0xc0046134: [2.314880] 6134 eb038dff eb02a1f9 e1a03007 e1a5 e1a02006 eb025566 e59f3008 e5834000 [2.323059] 6154 e8bd41f0 ea0259b3 c09059d4 c08fbcd4 c064e808 c0791c0d c0958220 e59fc020 [2.331207] 6174 e92d4007 e59f301c e59cc000 e1a02001 e59f1014 e58dc000 eb055aab e3a0 [2.339385] 6194 e8bd800e c0958220 c0791c27 c0791c1b e121f007 e1a4 e1a0e006 e1a0f005 [2.347534] 61b4 eb02959a e320f000 e59f300c e5932000 e2822001 e5832000 e12fff1e c0958224 [2.355682] 61d4 e59f300c e5932000 e2422001 e5832000 e12fff1e c0958224 e12fff1e e12fff1e [2.363861] 61f4 e12fff1e e12fff1e eafe e59f3014 e92d4010 e5933004 e353 08bd8010 [2.372009] 6214 e12fff33 e8bd8010 c0958224 e59f3014 e1a01000 e92d4010 e5d3 e1a0e00f [2.380187] Process swapper (pid: 1, stack limit = 0xe982a2e8) [2.385986] Stack: (0xe982bf98 to 0xe982c000) [2.390319] bf80: 3ffd a27e [2.398498] bfa0: c0037b4c c0022e94 c003f3fc e9814a80 00373231 [2.406646] bfc0: 0236 c0037b4c c003818c c00461b4 0013 [2.414825] bfe0: c0008374 c0008300 c00461b4 c00461b4 [2.423004] [] (sand_misc_init+0x4c/0xac) from [] (do_one_initcall+0xd0/0x1a4) [2.431915] [] (do_one_initcall+0xd0/0x1a4) from [] (kernel_init+0x74/0x118) [2.440673] [] (kernel_init+0x74/0x118) from [] (kernel_thread_exit+0x0/0x8) [2.449462] Code: e58d4000 e3033fff ea07 e59d2000 (e7952002) [2.455566] ---[ end trace f76f3c76dcb9b9ef ]--- [2.460144] Kernel panic - not syncing: Attempted to kill init! [2.466064] [] (unwind_backtrace+0x0/0x12c) from [] (panic+0x90/0x1bc) [2.474304] [] (panic+0x90/0x1bc) from [] (do_exit+0xb8/0x734) [2.481842] [] (do_exit+0xb8/0x734) from [] (die+0x208/0x23c) [2.489318] [] (die+0x208/0x23c) from [] (__do_kernel_fault+0x64/0x84) [2.497558] [] (__do_kernel_fault+0x64/0x84) from [] (do_page_fault+0x268/0x288) [2.506683] [] (do_page_fault+0x268/0x288) from [] (do_DataAbort+0x34/0x94) [2.515350] [] (do_DataAbort+0x34/0x94) from [] (__dabt_svc+0x4c/0x60) [2.523590] Exception stack(0xe982bf50 to 0xe982bf98) [2.528625] bf40: 0063 c07ea2cf 3ffd 3fff [2.536804] bf60: ea828000 c00461b4 [2.544952] bf80: e982bf98 c0022ed0 c0022ee0 8013 [2.551544] [] (__dabt_svc+0x4c/0x60) from [] (sand_misc_init+0x4c/0xac) [2.559967] [] (sand_misc_init+0x4c/0xac) from [] (do_one_initcall+0xd0/0x1a4) [2.568908] [] (do_one_initcall+0xd0/0x1a4) from [] (kernel_init+0x74/0x118) [2.577667] [] (kernel_init+0x74/0x118) from [] (kernel_thread_exit+0x0/0x8) Any idea what went wrong. I am sure about the ioremap() start address, thats what i reserved in ATAGS. Thanks Sandeep On Thu, Feb 28, 2013 at 10:30 AM, sandeep kumar wrote: > >1. use early_param to get the physical start address and size of > test_region, or you can just ignore this step and hard code to 510M and 2M > for test purpose only. > > >2. use ioremap_nocache() to map this region to a virtual region. note > that this funtion may fail if you are asking a very large vitual memroy > region. > > Sounds good, i am gonna try this and let you know.. :) > > > On Wed, Feb 27, 2013 at 8:19 PM, buyitian wrote: > >> >> > From: bu...@live.cn >> > To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org >> > Subject: RE: How to measure the RAM read/write performance >> > Date: Wed, 27 Feb 2013 22:33:15 +0800 >> > CC: dhyla...@gmail.com >> > >> > >> > > From: coolsandyfor...@gmail.com >> > > Date: Tue, 26 Feb 2013 17:01:54 +0530 >> > > Subject: How to measure the RAM read/write performance >> > > To: kernelnewbies@kernelnewbies.org >> > > CC: dhyla...@gmail.com >> > > >> > > Hi All >> > > In performance benchmark tools, When we profile read/write timings >> > > mostly, those read/writes are done to cache only. >> > > >> > > I want to measure my DDR(RAM chip) performance. >> > > So i want to make sure, every read/write should happen to DDR RAM >> chip only. >> > > >> > > How can i achieve this...Any ideas/suggestions...? >> > >> > try to reserve a large region from bootloader(L4 in Qualcomm platform), >> let's say it is 10MB continuous physical memory. >> >> sorry, to be accurate, reserve physical memo
Re: How to measure the RAM read/write performance
>1. use early_param to get the physical start address and size of test_region, or you can just ignore this step and hard code to 510M and 2M for test purpose only. >2. use ioremap_nocache() to map this region to a virtual region. note that this funtion may fail if you are asking a very large vitual memroy region. Sounds good, i am gonna try this and let you know.. :) On Wed, Feb 27, 2013 at 8:19 PM, buyitian wrote: > > > From: bu...@live.cn > > To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org > > Subject: RE: How to measure the RAM read/write performance > > Date: Wed, 27 Feb 2013 22:33:15 +0800 > > CC: dhyla...@gmail.com > > > > > > > From: coolsandyfor...@gmail.com > > > Date: Tue, 26 Feb 2013 17:01:54 +0530 > > > Subject: How to measure the RAM read/write performance > > > To: kernelnewbies@kernelnewbies.org > > > CC: dhyla...@gmail.com > > > > > > Hi All > > > In performance benchmark tools, When we profile read/write timings > > > mostly, those read/writes are done to cache only. > > > > > > I want to measure my DDR(RAM chip) performance. > > > So i want to make sure, every read/write should happen to DDR RAM chip > only. > > > > > > How can i achieve this...Any ideas/suggestions...? > > > > try to reserve a large region from bootloader(L4 in Qualcomm platform), > let's say it is 10MB continuous physical memory. > > sorry, to be accurate, reserve physical memory is done by kernel cmdline, > this cmdline parameter can be passed from L4 to kernel, or configed by > kernel itself. > the cmdline will be like below: > mem=510M@0 test_region=2M@510M > > above example tells kernel you have totally 512MB physical memory, but > kernel will only use the first 510MB, the latter 2MB memory is used by you. > how to map and use this region depends on you. > > > in kernel, map this region to an continuous virtual region, note that > the pgprot should be uncachable since you want to test without cache. > > 1. use early_param to get the physical start address and size of > test_region, or you can just ignore this step and hard code to 510M and 2M > for test purpose only. > > 2. use ioremap_nocache() to map this region to a virtual region. note that > this funtion may fail if you are asking a very large vitual memroy region. > > > once you configed like this, you can read/write to this vitual region > without data cache invovled. > > > > > > > > -- > > > With regards, > > > Sandeep Kumar Anantapalli, > > > > > > ___ Kernelnewbies mailing > > > list Kernelnewbies@kernelnewbies.org > > > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > > ___ > > Kernelnewbies mailing list > > Kernelnewbies@kernelnewbies.org > > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > > -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
On Wed, 27 Feb 2013 15:38:00 +0530, sandeep kumar said: > In development phase of the board, we are trying to measure RAM performance > gain while changing type of the RAM. > The standard benchmark tools are giving us the Cache performance only. So > we want to try some method to measure RAM performance. The fact that you can't measure the effect of RAM speed because the L1/2/3 cache masks the effect should tell you something :) If you are seeing a 98% hit rate or so, RAM speed will indeed not matter much. If you're seeing a poor cache hit ratio, you're most likely to get better performance not by changing the RAM, but changing the application to improve its cache usage. And of course, if the application's design is one that is resistant to improved cache hit ratios, it is important you measure RAM performance *with that application running*, not a benchmark. This is because if your application is managing to thrash the cache, the resulting RAM access patterns will be *highly* sensitive to actual program behavior, and any corner cases in the hardware may or may not be hit by the benchmark the same way the application does. pgpZ2odHm7mss.pgp Description: PGP signature ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
RE: How to measure the RAM read/write performance
> From: bu...@live.cn > To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org > Subject: RE: How to measure the RAM read/write performance > Date: Wed, 27 Feb 2013 22:33:15 +0800 > CC: dhyla...@gmail.com > > > > From: coolsandyfor...@gmail.com > > Date: Tue, 26 Feb 2013 17:01:54 +0530 > > Subject: How to measure the RAM read/write performance > > To: kernelnewbies@kernelnewbies.org > > CC: dhyla...@gmail.com > > > > Hi All > > In performance benchmark tools, When we profile read/write timings > > mostly, those read/writes are done to cache only. > > > > I want to measure my DDR(RAM chip) performance. > > So i want to make sure, every read/write should happen to DDR RAM chip only. > > > > How can i achieve this...Any ideas/suggestions...? > > try to reserve a large region from bootloader(L4 in Qualcomm platform), let's > say it is 10MB continuous physical memory. sorry, to be accurate, reserve physical memory is done by kernel cmdline, this cmdline parameter can be passed from L4 to kernel, or configed by kernel itself. the cmdline will be like below: mem=510M@0 test_region=2M@510M above example tells kernel you have totally 512MB physical memory, but kernel will only use the first 510MB, the latter 2MB memory is used by you. how to map and use this region depends on you. > in kernel, map this region to an continuous virtual region, note that the > pgprot should be uncachable since you want to test without cache. 1. use early_param to get the physical start address and size of test_region, or you can just ignore this step and hard code to 510M and 2M for test purpose only. 2. use ioremap_nocache() to map this region to a virtual region. note that this funtion may fail if you are asking a very large vitual memroy region. > once you configed like this, you can read/write to this vitual region without > data cache invovled. > > > > > -- > > With regards, > > Sandeep Kumar Anantapalli, > > > > ___ Kernelnewbies mailing > > list Kernelnewbies@kernelnewbies.org > > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > ___ > Kernelnewbies mailing list > Kernelnewbies@kernelnewbies.org > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
RE: How to measure the RAM read/write performance
> From: coolsandyfor...@gmail.com > Date: Tue, 26 Feb 2013 17:01:54 +0530 > Subject: How to measure the RAM read/write performance > To: kernelnewbies@kernelnewbies.org > CC: dhyla...@gmail.com > > Hi All > In performance benchmark tools, When we profile read/write timings > mostly, those read/writes are done to cache only. > > I want to measure my DDR(RAM chip) performance. > So i want to make sure, every read/write should happen to DDR RAM chip only. > > How can i achieve this...Any ideas/suggestions...? try to reserve a large region from bootloader(L4 in Qualcomm platform), let's say it is 10MB continuous physical memory. in kernel, map this region to an continuous virtual region, note that the pgprot should be uncachable since you want to test without cache. once you configed like this, you can read/write to this vitual region without data cache invovled. > > -- > With regards, > Sandeep Kumar Anantapalli, > > ___ Kernelnewbies mailing > list Kernelnewbies@kernelnewbies.org > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
On Wed, Feb 27, 2013 at 6:16 PM, sandeep kumar wrote: >>Try below points: >>1. I am not sure about snapdragon(is it Qualcomm?) but try >>CONFIG_CPU_DCACHE_DISABLE. > I did that already, device is not booting. In our architecture cache is > tightly coupled with CPU. Should be discussed with Qualcomm guys here as to the reason why it doesn't boot up. > >>2. You are better off programming some DMA master to do large (and >>uncached) reads/writes to RAM and timing that. > DMA is not a standard way, i suppose, as it depends on what I/O peripheral > we are doing the DMA. You are doing I/O to RAM so it should do what you want. CPU->DMA CONTROLLER->RAM > >>You should always add arm mailing list and please mention the chip set >> details. >>cat /proc/cpuinfo is a great way > Processor : ARMv7 Processor rev 2 (v7l) > BogoMIPS: 163.38 > Features: swp half thumb fastmult vfp edsp neon vfpv3 tls > CPU implementer : 0x51 > CPU architecture: 7 > CPU variant : 0x1 > CPU part: 0x00f > CPU revision: 2 > > Thanks > Sandeep > > > > > On Wed, Feb 27, 2013 at 5:37 PM, anish singh > wrote: >> >> On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar >> wrote: >> > Hi All >> > In performance benchmark tools, When we profile read/write timings >> > mostly, >> > those read/writes are done to cache only. >> > >> > I want to measure my DDR(RAM chip) performance. >> > So i want to make sure, every read/write should happen to DDR RAM chip >> > only. >> Try below points: >> 1. I am not sure about snapdragon(is it Qualcomm?) but try >> CONFIG_CPU_DCACHE_DISABLE. >> 2. You are better off programming some DMA master to do large (and >> uncached) reads/writes to RAM and timing that. >> >> However simple uncached LDR/STR from the CPU may not be a great >> measure of RAM controller perf. >> >> You should always add arm mailing list and please mention the chip set >> details. >> cat /proc/cpuinfo is a great way >> > >> > How can i achieve this...Any ideas/suggestions...? >> > >> > -- >> > With regards, >> > Sandeep Kumar Anantapalli, >> > >> > ___ >> > Kernelnewbies mailing list >> > Kernelnewbies@kernelnewbies.org >> > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >> > > > > > > -- > With regards, > Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
>Try below points: >1. I am not sure about snapdragon(is it Qualcomm?) but try >CONFIG_CPU_DCACHE_DISABLE. I did that already, device is not booting. In our architecture cache is tightly coupled with CPU. >2. You are better off programming some DMA master to do large (and >uncached) reads/writes to RAM and timing that. DMA is not a standard way, i suppose, as it depends on what I/O peripheral we are doing the DMA. >You should always add arm mailing list and please mention the chip set details. >cat /proc/cpuinfo is a great way Processor : ARMv7 Processor rev 2 (v7l) BogoMIPS: 163.38 Features: swp half thumb fastmult vfp edsp neon vfpv3 tls CPU implementer : 0x51 CPU architecture: 7 CPU variant : 0x1 CPU part: 0x00f CPU revision: 2 Thanks Sandeep On Wed, Feb 27, 2013 at 5:37 PM, anish singh wrote: > On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar > wrote: > > Hi All > > In performance benchmark tools, When we profile read/write timings > mostly, > > those read/writes are done to cache only. > > > > I want to measure my DDR(RAM chip) performance. > > So i want to make sure, every read/write should happen to DDR RAM chip > only. > Try below points: > 1. I am not sure about snapdragon(is it Qualcomm?) but try > CONFIG_CPU_DCACHE_DISABLE. > 2. You are better off programming some DMA master to do large (and > uncached) reads/writes to RAM and timing that. > > However simple uncached LDR/STR from the CPU may not be a great > measure of RAM controller perf. > > You should always add arm mailing list and please mention the chip set > details. > cat /proc/cpuinfo is a great way > > > > How can i achieve this...Any ideas/suggestions...? > > > > -- > > With regards, > > Sandeep Kumar Anantapalli, > > > > ___ > > Kernelnewbies mailing list > > Kernelnewbies@kernelnewbies.org > > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > > > -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar wrote: > Hi All > In performance benchmark tools, When we profile read/write timings mostly, > those read/writes are done to cache only. > > I want to measure my DDR(RAM chip) performance. > So i want to make sure, every read/write should happen to DDR RAM chip only. Try below points: 1. I am not sure about snapdragon(is it Qualcomm?) but try CONFIG_CPU_DCACHE_DISABLE. 2. You are better off programming some DMA master to do large (and uncached) reads/writes to RAM and timing that. However simple uncached LDR/STR from the CPU may not be a great measure of RAM controller perf. You should always add arm mailing list and please mention the chip set details. cat /proc/cpuinfo is a great way > > How can i achieve this...Any ideas/suggestions...? > > -- > With regards, > Sandeep Kumar Anantapalli, > > ___ > Kernelnewbies mailing list > Kernelnewbies@kernelnewbies.org > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
2013/2/27 sandeep kumar > >"volatile" only say to the compiler to not put the variable in a register. > >Could i ask why does you want to mesure the speed of the RAM ? Is it to > study the NUMA behavior of the machine? > > In development phase of the board, we are trying to measure RAM > performance gain while changing type of the RAM. > The standard benchmark tools are giving us the Cache performance only. So > we want to try some method to measure RAM performance. > ok. The answear is hardware-dependent, some hardware may have a way to disable the cachability (but will probly need to be in the kernel). But to skeep the hardware dependencie, you need to read a part of memory that is not cached. The best way is to do the test at boot time when the caches are cold. I dont think that a user-space application could do this in precise way, since it cannot know the physical address it address Doing a small "boot" code and booted directly (without grub) could give some precise numbers. You will also need to space yout read request (128*8 byte for example), since most cache caches a line while you have read only one word. Hope i helped. regards. > > On Wed, Feb 27, 2013 at 2:30 PM, Karaoui mohamed lamine < > mohar...@gmail.com> wrote: > >> >> >> 2013/2/27 sandeep kumar >> >>> >>I am not sure but what if you make the variable as a volatile? >>> Hey i tried. But still is showing the same time for int & volatile int. >>> >>> >> "volatile" only say to the compiler to not put the variable in a register. >> Could i ask why does you want to mesure the speed of the RAM ? Is it to >> study the NUMA behavior of the machine? >> >> >> >> >>> Thanks >>> Sandeep >>> >>> >>> >>> On Tue, Feb 26, 2013 at 6:50 PM, ankur dwivedi >>> wrote: >>> I am not sure but what if you make the variable as a volatile? On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar < coolsandyfor...@gmail.com> wrote: > Hi All > In performance benchmark tools, When we profile read/write timings > mostly, those read/writes are done to cache only. > > I want to measure my DDR(RAM chip) performance. > So i want to make sure, every read/write should happen to DDR RAM chip > only. > > How can i achieve this...Any ideas/suggestions...? > > -- > With regards, > Sandeep Kumar Anantapalli, > > ___ > Kernelnewbies mailing list > Kernelnewbies@kernelnewbies.org > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > > -- Thanks Ankur Dwivedi >>> >>> >>> -- >>> With regards, >>> Sandeep Kumar Anantapalli, >>> >>> ___ >>> Kernelnewbies mailing list >>> Kernelnewbies@kernelnewbies.org >>> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >>> >>> >> > > > -- > With regards, > Sandeep Kumar Anantapalli, > ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
>"volatile" only say to the compiler to not put the variable in a register. >Could i ask why does you want to mesure the speed of the RAM ? Is it to study the NUMA behavior of the machine? In development phase of the board, we are trying to measure RAM performance gain while changing type of the RAM. The standard benchmark tools are giving us the Cache performance only. So we want to try some method to measure RAM performance. On Wed, Feb 27, 2013 at 2:30 PM, Karaoui mohamed lamine wrote: > > > 2013/2/27 sandeep kumar > >> >>I am not sure but what if you make the variable as a volatile? >> Hey i tried. But still is showing the same time for int & volatile int. >> >> > "volatile" only say to the compiler to not put the variable in a register. > Could i ask why does you want to mesure the speed of the RAM ? Is it to > study the NUMA behavior of the machine? > > > > >> Thanks >> Sandeep >> >> >> >> On Tue, Feb 26, 2013 at 6:50 PM, ankur dwivedi >> wrote: >> >>> I am not sure but what if you make the variable as a volatile? >>> >>> On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar < >>> coolsandyfor...@gmail.com> wrote: >>> Hi All In performance benchmark tools, When we profile read/write timings mostly, those read/writes are done to cache only. I want to measure my DDR(RAM chip) performance. So i want to make sure, every read/write should happen to DDR RAM chip only. How can i achieve this...Any ideas/suggestions...? -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >>> >>> >>> -- >>> Thanks >>> >>> Ankur Dwivedi >>> >>> >> >> >> -- >> With regards, >> Sandeep Kumar Anantapalli, >> >> ___ >> Kernelnewbies mailing list >> Kernelnewbies@kernelnewbies.org >> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >> >> > -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
2013/2/27 sandeep kumar > >>I am not sure but what if you make the variable as a volatile? > Hey i tried. But still is showing the same time for int & volatile int. > > "volatile" only say to the compiler to not put the variable in a register. Could i ask why does you want to mesure the speed of the RAM ? Is it to study the NUMA behavior of the machine? > Thanks > Sandeep > > > > On Tue, Feb 26, 2013 at 6:50 PM, ankur dwivedi wrote: > >> I am not sure but what if you make the variable as a volatile? >> >> On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar > > wrote: >> >>> Hi All >>> In performance benchmark tools, When we profile read/write timings >>> mostly, those read/writes are done to cache only. >>> >>> I want to measure my DDR(RAM chip) performance. >>> So i want to make sure, every read/write should happen to DDR RAM chip >>> only. >>> >>> How can i achieve this...Any ideas/suggestions...? >>> >>> -- >>> With regards, >>> Sandeep Kumar Anantapalli, >>> >>> ___ >>> Kernelnewbies mailing list >>> Kernelnewbies@kernelnewbies.org >>> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >>> >>> >> >> >> -- >> Thanks >> >> Ankur Dwivedi >> >> > > > -- > With regards, > Sandeep Kumar Anantapalli, > > ___ > Kernelnewbies mailing list > Kernelnewbies@kernelnewbies.org > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > > ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
>let' see >what if you do read and write pattern, in certain order so that it >will be invalidated by the L1/L2/L3 cache everytime? And how do you suggest we do that?? That is infact my question.. On Tue, Feb 26, 2013 at 9:05 PM, Mulyadi Santosa wrote: > On Tue, Feb 26, 2013 at 6:31 PM, sandeep kumar > wrote: > > Hi All > > In performance benchmark tools, When we profile read/write timings > mostly, > > those read/writes are done to cache only. > > > > I want to measure my DDR(RAM chip) performance. > > So i want to make sure, every read/write should happen to DDR RAM chip > only. > > let' see > > what if you do read and write pattern, in certain order so that it > will be invalidated by the L1/L2/L3 cache everytime? > > AFAIK, one thing for sure, reading data from sequentially and re-read > them will make end up reading cache in the 2nd operation and so on. > > I think the most certain way to do it is to read data (or write) data > bigger than total L1/L2/L3 cache. > > -- > regards, > > Mulyadi Santosa > Freelance Linux trainer and consultant > > blog: the-hydra.blogspot.com > training: mulyaditraining.blogspot.com > -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
>>I am not sure but what if you make the variable as a volatile? Hey i tried. But still is showing the same time for int & volatile int. Thanks Sandeep On Tue, Feb 26, 2013 at 6:50 PM, ankur dwivedi wrote: > I am not sure but what if you make the variable as a volatile? > > On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar > wrote: > >> Hi All >> In performance benchmark tools, When we profile read/write timings >> mostly, those read/writes are done to cache only. >> >> I want to measure my DDR(RAM chip) performance. >> So i want to make sure, every read/write should happen to DDR RAM chip >> only. >> >> How can i achieve this...Any ideas/suggestions...? >> >> -- >> With regards, >> Sandeep Kumar Anantapalli, >> >> ___ >> Kernelnewbies mailing list >> Kernelnewbies@kernelnewbies.org >> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >> >> > > > -- > Thanks > > Ankur Dwivedi > > -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
>How could I missed memtest ! :) Of course, that's the easiest way I >could think of... if the OP doesn't mind with non programming method >IMHO But i want to check it on ARM based Android board.. On Wed, Feb 27, 2013 at 6:12 AM, Mulyadi Santosa wrote: > On Tue, Feb 26, 2013 at 11:57 PM, wrote: > > Of you could just download a copy of memtest+ and run that - I think that > > provides some timing info in addition to actually testing your memory. > > How could I missed memtest ! :) Of course, that's the easiest way I > could think of... if the OP doesn't mind with non programming method > IMHO > > Great idea! > > > -- > regards, > > Mulyadi Santosa > Freelance Linux trainer and consultant > > blog: the-hydra.blogspot.com > training: mulyaditraining.blogspot.com > -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
On Tue, Feb 26, 2013 at 11:57 PM, wrote: > Of you could just download a copy of memtest+ and run that - I think that > provides some timing info in addition to actually testing your memory. How could I missed memtest ! :) Of course, that's the easiest way I could think of... if the OP doesn't mind with non programming method IMHO Great idea! -- regards, Mulyadi Santosa Freelance Linux trainer and consultant blog: the-hydra.blogspot.com training: mulyaditraining.blogspot.com ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
On Tue, 26 Feb 2013 22:35:35 +0700, Mulyadi Santosa said: > let' see > > what if you do read and write pattern, in certain order so that it > will be invalidated by the L1/L2/L3 cache everytime? > > AFAIK, one thing for sure, reading data from sequentially and re-read > them will make end up reading cache in the 2nd operation and so on. > > I think the most certain way to do it is to read data (or write) data > bigger than total L1/L2/L3 cache. Of you could just download a copy of memtest+ and run that - I think that provides some timing info in addition to actually testing your memory. pgpXhrIunMesq.pgp Description: PGP signature ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
On Tue, Feb 26, 2013 at 6:31 PM, sandeep kumar wrote: > Hi All > In performance benchmark tools, When we profile read/write timings mostly, > those read/writes are done to cache only. > > I want to measure my DDR(RAM chip) performance. > So i want to make sure, every read/write should happen to DDR RAM chip only. let' see what if you do read and write pattern, in certain order so that it will be invalidated by the L1/L2/L3 cache everytime? AFAIK, one thing for sure, reading data from sequentially and re-read them will make end up reading cache in the 2nd operation and so on. I think the most certain way to do it is to read data (or write) data bigger than total L1/L2/L3 cache. -- regards, Mulyadi Santosa Freelance Linux trainer and consultant blog: the-hydra.blogspot.com training: mulyaditraining.blogspot.com ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
I am not sure but what if you make the variable as a volatile? On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar wrote: > Hi All > In performance benchmark tools, When we profile read/write timings mostly, > those read/writes are done to cache only. > > I want to measure my DDR(RAM chip) performance. > So i want to make sure, every read/write should happen to DDR RAM chip > only. > > How can i achieve this...Any ideas/suggestions...? > > -- > With regards, > Sandeep Kumar Anantapalli, > > ___ > Kernelnewbies mailing list > Kernelnewbies@kernelnewbies.org > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > > -- Thanks Ankur Dwivedi ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
The mechanism to disable the L1/L2 memory caches of the CPU will depend on the processor architecture itself. This can be possibly be done at kernel boot-time or more preferably, in your case, through a kernel module. For Intel x86, the kernel module would look something like following: (The key is setting bit 30 of the control register cr0) mov eax,cr0 or eax, 4000H ;set bit 30 without clearing the others mov cr0,eax Reference: http://stackoverflow.com/questions/1108485/disable-l2-l1-caches http://dirac.org/linux/writing/lkmpg/2.6/lkmpg-2.6.0.html ~ Gaurav On Tue, Feb 26, 2013 at 12:31 PM, sandeep kumar wrote: > Hi All > In performance benchmark tools, When we profile read/write timings mostly, > those read/writes are done to cache only. > > I want to measure my DDR(RAM chip) performance. > So i want to make sure, every read/write should happen to DDR RAM chip > only. > > How can i achieve this...Any ideas/suggestions...? > > -- > With regards, > Sandeep Kumar Anantapalli, > > ___ > Kernelnewbies mailing list > Kernelnewbies@kernelnewbies.org > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > > -- Gaurav Jain Associate Software Engineer VxVM Escalations Team, SAMG Symantec Software India Pvt. Ltd. ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
