Re: [Kicad-developers] Feature Request: ViaStiching
On 28.03.2015 07:55, jp charras wrote: > Le 27/03/2015 22:39, John Beard a écrit : > > John, > Currently, vias not connected to a pads (by tracks) are considered as > not connected (i.e. have the net 0) as soon as the board connections are > recalculated > > This is true also for tracks connected to nothing, and I am thinking > this is the right way to handle not connected track segments (vias are > also track segments) when the board connections are recalculated. Hi Jean-Pierre, The proprietary software that I used (Eagle, Altium, PADS) does not change the nets of any item on the board without the user explicitly allowing such a change. This - in my humble opinion - gives more control over the design and reduces the chances of accidentally breaking it. I find the current connectivity calculation algorithm a bit too invasive - but this I could live with. The worse part is that net code recalculation is silently called in many places without the agreement of the user and cannot be undone. For example, when I design PCBs, I often leave some 'snippets' (e.g. some trace/via patterns) aside, for later use. I would prefer Kicad to not change or reset their nets unless I tell it to... The cases where the net of an item may be changed (except for editing it in the item's properties) IMHO are: 1) Netlist update (propagated from the pads of the changed components, just like the current algorithm does). 2) Removing net completely on the schematic causes removal of the corresponding nets on the PCB. 3) Placing a pad (or module) over a set of board items (tracks, vias) causes the latter to inherit the pads' nets only if not connected to another pad. 4) Placing a set of board items (excluding components) over pads with assigned nets causes the former to inherit the pads' nets. This one is particularly useful for copying & pasting via fanouts under big BGAs (route one row/side of a BGA, paste over other BGA pads) 5) Zone nets may be changed only if the net no longer exists in the schematic. > > Moreover, these tracks are removed by the board cleaning functions. > > Via stitching is not a thing which is easy to add. > Be sure this feature requires a lot of work (DRC, filling zone > algorithms ... ) I agree we would need to modify the DRC (but AFAIK it only means producing errors on vias that are not connected to anything instead of removing them). > and needs file format changes. What file format changes would be required to support stitching vias if the items' nets are changed only in the situations pointed above? Cheers, Tom ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Feature Request: ViaStiching
Le 27/03/2015 22:39, John Beard a écrit : > Hi, > > The array tool should make rudimentary stitching possible - just create a > grid of the via you want to duplicate and remove any that aren't in the > area you want. It's a fully manual process, but it seems to interact > sensibly with zones at least - see the attached screenshot for the > behaviour for different and same nets (i.e part of or not part of the > zone). I have no idea if this is a generally "good" workflow, but I > suppose it is something! > > The attached patch corrects an oversight in the legacy renderer where > vias can't be duplicated by the hotkey. It already works OK in the GAL. > > Cheers, > > John > John, Currently, vias not connected to a pads (by tracks) are considered as not connected (i.e. have the net 0) as soon as the board connections are recalculated This is true also for tracks connected to nothing, and I am thinking this is the right way to handle not connected track segments (vias are also track segments) when the board connections are recalculated. Moreover, these tracks are removed by the board cleaning functions. Via stitching is not a thing which is easy to add. Be sure this feature requires a lot of work (DRC, filling zone algorithms ... ) and needs file format changes. -- Jean-Pierre CHARRAS ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Feature Request: ViaStiching
Hi,
The array tool should make rudimentary stitching possible - just create a
grid of the via you want to duplicate and remove any that aren't in the
area you want. It's a fully manual process, but it seems to interact
sensibly with zones at least - see the attached screenshot for the
behaviour for different and same nets (i.e part of or not part of the
zone). I have no idea if this is a generally "good" workflow, but I
suppose it is something!
The attached patch corrects an oversight in the legacy renderer where
vias can't be duplicated by the hotkey. It already works OK in the GAL.
Cheers,
John
On Mon, 2015-03-23 at 18:48 +0100, Michael Heidinger wrote:
> Hello,
>
> I would like to propose a tool "via stitching". Simply many via next to
> each other.
> Via stitching is required for me to do thermal transfer from one side to
> the other. Manual placing requires a lot of effort, a tool could
> simplify that.
>
> Usage: I would to specify the area and the net and the tool should place
> the the vias for me. Do you think that such tool could be possible?
> Altium has a great implementation of via stiching: Do you think that's
> possible?
> http://techdocs.altium.com/display/ADOH/Via+Stitching
>
> - Michael
>
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diff --git a/pcbnew/hotkeys_board_editor.cpp b/pcbnew/hotkeys_board_editor.cpp
index 2e36463..5c19d08 100644
--- a/pcbnew/hotkeys_board_editor.cpp
+++ b/pcbnew/hotkeys_board_editor.cpp
@@ -1108,6 +1108,7 @@ bool PCB_EDIT_FRAME::OnHotkeyDuplicateOrArrayItem( int aIdCommand )
case PCB_ZONE_AREA_T:
case PCB_TARGET_T:
case PCB_DIMENSION_T:
+case PCB_VIA_T:
switch( aIdCommand )
{
case HK_CREATE_ARRAY:
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Re: [Kicad-developers] Feature Request: ViaStiching
Le 23/03/2015 20:28, Wayne Stambaugh a écrit : > On 3/23/2015 3:25 PM, Simon Richter wrote: >> Hi, >> >> Am 23.03.2015 um 18:56 schrieb Chris Pavlina: >> >>> KiCad does not currently support standalone vias, and I think that would >>> be a necessity before a *clean* implementation of this could be done. > > This would have to be done first and it would require changes to the > file format, zone definition and filling, and the DRC at a minimum. > There are probably some other things I'm forgetting. JP would have a > better idea of the effort involved. Once this part is complete, then we > could start discussing tools for using standalone vias. That being > said, I also think this is something useful to have but as Chris eluded > to it will not happen until after the next stable release. Stand alone vias and stitching vias inside a copper zone are 2 different things. For stand alone vias (and stand alone track segments), the main issue is to know the net which contains them, and to tell the true, I am not very thrilled with adding stand alone vias. During a session, this is not a major problem, but what is the right net, after a netlist is read, and net names are modified for instance. The answer is not obvious ( vias are not always connected to the GND signal) Stitching vias depending on a zone is a bit different, because they are depending on a defined entity which already manages a net name. However changes is file format are needed (at least a zone stores the solid copper areas, and have to also also store the vias it manages, and some info to rebuild them, like size, pitch...) We have also to manage zone edition, zone merging, zone refilling (including rebuilding vias). Zone refilling algorithm with stitching vias is certainly not obvious. By the way, I was not impressed by the via stitching feature in Altium. > >> >> I think these vias would be placed inside a copper pour, so there is >> something to "connect" them to. The notion of "generated" vias is new >> though (so if I change parameters for thermal relief, these vias can be >> deleted and recreated). >> >> I'd like to tack a feature request on top of that: thermal via >> generation in pads. For my last project I simply used four rectangular >> pads with copper on top and bottom and a hole in the middle. This works, >> but for library submission I'd like to be able to express this in a >> cleaner way (i.e. one large pad, with an attribute how much thermal >> power it needs to sink). >> >>Simon >> >> >> >> ___ >> Mailing list: https://launchpad.net/~kicad-developers >> Post to : kicad-developers@lists.launchpad.net >> Unsubscribe : https://launchpad.net/~kicad-developers >> More help : https://help.launchpad.net/ListHelp >> > > ___ > Mailing list: https://launchpad.net/~kicad-developers > Post to : kicad-developers@lists.launchpad.net > Unsubscribe : https://launchpad.net/~kicad-developers > More help : https://help.launchpad.net/ListHelp > -- Jean-Pierre CHARRAS ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Feature Request: ViaStiching
On 3/23/2015 3:25 PM, Simon Richter wrote: > Hi, > > Am 23.03.2015 um 18:56 schrieb Chris Pavlina: > >> KiCad does not currently support standalone vias, and I think that would >> be a necessity before a *clean* implementation of this could be done. This would have to be done first and it would require changes to the file format, zone definition and filling, and the DRC at a minimum. There are probably some other things I'm forgetting. JP would have a better idea of the effort involved. Once this part is complete, then we could start discussing tools for using standalone vias. That being said, I also think this is something useful to have but as Chris eluded to it will not happen until after the next stable release. > > I think these vias would be placed inside a copper pour, so there is > something to "connect" them to. The notion of "generated" vias is new > though (so if I change parameters for thermal relief, these vias can be > deleted and recreated). > > I'd like to tack a feature request on top of that: thermal via > generation in pads. For my last project I simply used four rectangular > pads with copper on top and bottom and a hole in the middle. This works, > but for library submission I'd like to be able to express this in a > cleaner way (i.e. one large pad, with an attribute how much thermal > power it needs to sink). > >Simon > > > > ___ > Mailing list: https://launchpad.net/~kicad-developers > Post to : kicad-developers@lists.launchpad.net > Unsubscribe : https://launchpad.net/~kicad-developers > More help : https://help.launchpad.net/ListHelp > ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Feature Request: ViaStiching
Hi, Am 23.03.2015 um 18:56 schrieb Chris Pavlina: > KiCad does not currently support standalone vias, and I think that would > be a necessity before a *clean* implementation of this could be done. I think these vias would be placed inside a copper pour, so there is something to "connect" them to. The notion of "generated" vias is new though (so if I change parameters for thermal relief, these vias can be deleted and recreated). I'd like to tack a feature request on top of that: thermal via generation in pads. For my last project I simply used four rectangular pads with copper on top and bottom and a hole in the middle. This works, but for library submission I'd like to be able to express this in a cleaner way (i.e. one large pad, with an attribute how much thermal power it needs to sink). Simon signature.asc Description: OpenPGP digital signature ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Feature Request: ViaStiching
> On Mar 23, 2015, at 10:56 AM, Chris Pavlina wrote: > > KiCad does not currently support standalone vias, and I think that would be a > necessity before a *clean* implementation of this could be done. The only > other options are to either place a /footprint/ as a via (nasty), or place a > web of traces along with the vias (terribly, horribly filthy). The latter is what I do now. I never came up with an alternative. -a > On Mon, Mar 23, 2015 at 06:48:18PM +0100, Michael Heidinger wrote: >> Hello, >> >> I would like to propose a tool "via stitching". Simply many via next to each >> other. >> Via stitching is required for me to do thermal transfer from one side to the >> other. Manual placing requires a lot of effort, a tool could simplify that. >> >> Usage: I would to specify the area and the net and the tool should place the >> the vias for me. Do you think that such tool could be possible? >> Altium has a great implementation of via stiching: Do you think that's >> possible? >> http://techdocs.altium.com/display/ADOH/Via+Stitching ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
Re: [Kicad-developers] Feature Request: ViaStiching
KiCad does not currently support standalone vias, and I think that would be a necessity before a *clean* implementation of this could be done. The only other options are to either place a /footprint/ as a via (nasty), or place a web of traces along with the vias (terribly, horribly filthy). That said, I think both are excellent ideas. They won't make it before the freeze, but they ought to be added after it anyway, in the proper order required. -- Chris On Mon, Mar 23, 2015 at 06:48:18PM +0100, Michael Heidinger wrote: Hello, I would like to propose a tool "via stitching". Simply many via next to each other. Via stitching is required for me to do thermal transfer from one side to the other. Manual placing requires a lot of effort, a tool could simplify that. Usage: I would to specify the area and the net and the tool should place the the vias for me. Do you think that such tool could be possible? Altium has a great implementation of via stiching: Do you think that's possible? http://techdocs.altium.com/display/ADOH/Via+Stitching - Michael ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp ___ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
