[Bug 65561] KVM:Entry failed on Single stepping sti instruction
https://bugzilla.kernel.org/show_bug.cgi?id=65561 --- Comment #2 from Jatin Kumar --- Hello Jidong, thanks for the info. I will try and let you know. While you are at this, can you please help me another single stepping issue and the issue is: 1. While single stepping, the instruction immediately next to `out` (EE) instruction is skipped. I am not getting debug trap after the execution of `out` instruction completes. 2. Also is there anything special about `out` instruction that causes interrupts to come at instruction immediately next to it, when not running in single stepping mode. That would be a really great help in my project. Thanks in advance. -- You are receiving this mail because: You are watching the assignee of the bug. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Bug 45931] Nested Virt: VMX can't be initialized in L1 Xen ("Xen on KVM")
https://bugzilla.kernel.org/show_bug.cgi?id=45931 Zhou, Chao changed: What|Removed |Added CC||chao.z...@intel.com --- Comment #2 from Zhou, Chao --- kvm.git + qemu.git：198c74f4_a41b2c99 host kernel :3.15.0-rc1 test on Romley_EP, crete L1(xen on kvm) guest with "-cpu host", then create L2 guest, L1 guest can boot up. some log with command "xl dmesg" in L1 guest (XEN) Platform timer is 100.000MHz HPET (XEN) Allocated console ring of 32 KiB. (XEN) VMX: Supported advanced features: (XEN) - APIC MMIO access virtualisation (XEN) - Extended Page Tables (EPT) (XEN) - Virtual NMI (XEN) - MSR direct-access bitmap (XEN) - Unrestricted Guest (XEN) HVM: ASIDs disabled. (XEN) HVM: VMX enabled (XEN) HVM: Hardware Assisted Paging (HAP) detected (XEN) HVM: HAP page sizes: 4kB, 2MB -- You are receiving this mail because: You are watching the assignee of the bug.-- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Bug 75981] [Nested kvm on kvm]L2 guest reboot continuously when create a rhel6u5(64bit) as L2 guest.
https://bugzilla.kernel.org/show_bug.cgi?id=75981 --- Comment #4 from Zhou, Chao --- kvm.git + qemu.git: d9f89b88_e5bfd640 host kernel:3.15.0_rc1 test on Romley_EP, create a 64bit rhel6u5 guest as L2 guest, the L2 guest boots up fine. -- You are receiving this mail because: You are watching the assignee of the bug. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Bug 75981] [Nested kvm on kvm]L2 guest reboot continuously when create a rhel6u5(64bit) as L2 guest.
https://bugzilla.kernel.org/show_bug.cgi?id=75981 Zhou, Chao changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |CODE_FIX -- You are receiving this mail because: You are watching the assignee of the bug. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Bug 75981] [Nested kvm on kvm]L2 guest reboot continuously when create a rhel6u5(64bit) as L2 guest.
https://bugzilla.kernel.org/show_bug.cgi?id=75981 --- Comment #5 from Zhou, Chao --- this commit fixed the bug: commit d9f89b88f5102ce235b75a5907838e3c7ed84b97 Author: Jan Kiszka Date: Sat May 10 09:24:34 2014 +0200 KVM: x86: Fix CR3 reserved bits check in long mode Regression of 346874c9: PAE is set in long mode, but that does not mean we have valid PDPTRs. Signed-off-by: Jan Kiszka Signed-off-by: Paolo Bonzini -- You are receiving this mail because: You are watching the assignee of the bug. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Bug 75981] [Nested kvm on kvm]L2 guest reboot continuously when create a rhel6u5(64bit) as L2 guest.
https://bugzilla.kernel.org/show_bug.cgi?id=75981 Zhou, Chao changed: What|Removed |Added Status|RESOLVED|VERIFIED -- You are receiving this mail because: You are watching the assignee of the bug. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 6/6] KVM: PPC: Book3S PR: Expose TM registers
On Mon, May 19, 2014 at 03:09:07PM +0200, Alexander Graf wrote:
>
> On 17.05.14 08:20, Paul Mackerras wrote:
> >On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
> >>POWER8 introduces transactional memory which brings along a number of new
> >>registers and MSR bits.
> >>
> >>Implementing all of those is a pretty big headache, so for now let's at
> >>least
> >>emulate enough to make Linux's context switching code happy.
> >[snip]
> >
> >>- if (!(vcpu->arch.fscr & (1ULL << fac))) {
> >>+ /* We get TM interrupts only when EBB is disabled? Sigh. */
> >This comment doesn't make sense to me. Not every reason code reported
> >in the high bits of FSCR corresponds directly to an enable bit in
> >FSCR. In fact, of the 7 defined reason codes in POWER8, only three
> >correspond to an enable bit...
>
> Is there any documentation on which relate to what?
Yes, Power ISA v2.07 book 3S section 6.2.10 describes the FSCR enable
bits and the interruption cause field. There are 6 cause values
defined, of which 3 correspond to enable bits in the FSCR, and the
other 3 correspond to things enabled/disabled in MMCR0 (usermode PMC
anb BHRB access) or MSR (TM stuff).
Paul.
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Re: [Qemu-devel] [PATCH v1 RFC 6/6] KVM: s390: add cpu model support
On Mon, 19 May 2014 22:14:00 +0200
Alexander Graf wrote:
>
> On 19.05.14 19:03, Michael Mueller wrote:
> > On Mon, 19 May 2014 16:49:28 +0200
> > Alexander Graf wrote:
> >
> >> On 19.05.14 16:18, Michael Mueller wrote:
> >>> On Mon, 19 May 2014 13:48:08 +0200
> >>> Alexander Graf wrote:
> >>>
> On 19.05.14 12:53, Michael Mueller wrote:
> > On Fri, 16 May 2014 22:31:12 +0200
> > Alexander Graf wrote:
> >
> >> On 16.05.14 17:39, Michael Mueller wrote:
> >>> On Fri, 16 May 2014 14:08:24 +0200
> >>> Alexander Graf wrote:
> >>>
> On 13.05.14 16:58, Michael Mueller wrote:
> > This patch enables cpu model support in kvm/s390 via the vm
> > attribute
> > interface.
> >
> > During KVM initialization, the host properties cpuid, IBC value and
> > the
> > facility list are stored in the architecture specific cpu model
> > structure.
> >
> > During vcpu setup, these properties are taken to initialize the
> > related SIE
> > state. This mechanism allows to adjust the properties from user
> > space and thus
> > to implement different selectable cpu models.
> >
> > This patch uses the IBC functionality to block instructions that
> > have not
> > been implemented at the requested CPU type and GA level compared to
> > the
> > full host capability.
> >
> > Userspace has to initialize the cpu model before vcpu creation. A
> > cpu model
> > change of running vcpus is currently not possible.
> Why is this VM global? It usually fits a lot better modeling wise
> when
> CPU types are vcpu properties.
> >>> It simplifies the code substantially because it inherently guarantees
> >>> the vcpus being
> >>> configured identical. In addition, there is no S390 hardware
> >>> implementation containing
> >>> inhomogeneous processor types. Thus I consider the properties as
> >>> machine specific.
> >>>
> > Signed-off-by: Michael Mueller
> > ---
> > arch/s390/include/asm/kvm_host.h | 4 +-
> > arch/s390/include/uapi/asm/kvm.h | 23 ++
> > arch/s390/kvm/kvm-s390.c | 146
> > ++-
> > arch/s390/kvm/kvm-s390.h | 1 +
> > 4 files changed, 172 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/s390/include/asm/kvm_host.h
> > b/arch/s390/include/asm/kvm_host.h
> > index b4751ba..6b826cb 100644
> > --- a/arch/s390/include/asm/kvm_host.h
> > +++ b/arch/s390/include/asm/kvm_host.h
> > @@ -84,7 +84,8 @@ struct kvm_s390_sie_block {
> > atomic_t cpuflags; /* 0x */
> > __u32 : 1; /* 0x0004 */
> > __u32 prefix : 18;
> > - __u32 : 13;
> > + __u32 : 1;
> > + __u32 ibc : 12;
> > __u8reserved08[4]; /* 0x0008 */
> > #define PROG_IN_SIE (1<<0)
> > __u32 prog0c; /* 0x000c */
> > @@ -418,6 +419,7 @@ struct kvm_s390_cpu_model {
> > unsigned long *sie_fac;
> > struct cpuid cpu_id;
> > unsigned long *fac_list;
> > + unsigned short ibc;
> > };
> >
> > struct kvm_arch{
> > diff --git a/arch/s390/include/uapi/asm/kvm.h
> > b/arch/s390/include/uapi/asm/kvm.h
> > index 313100a..82ef1b5 100644
> > --- a/arch/s390/include/uapi/asm/kvm.h
> > +++ b/arch/s390/include/uapi/asm/kvm.h
> > @@ -58,12 +58,35 @@ struct kvm_s390_io_adapter_req {
> >
> > /* kvm attr_group on vm fd */
> > #define KVM_S390_VM_MEM_CTRL 0
> > +#define KVM_S390_VM_CPU_MODEL 1
> >
> > /* kvm attributes for mem_ctrl */
> > #define KVM_S390_VM_MEM_ENABLE_CMMA 0
> > #define KVM_S390_VM_MEM_CLR_CMMA 1
> > #define KVM_S390_VM_MEM_CLR_PAGES 2
> >
> > +/* kvm attributes for cpu_model */
> > +
> > +/* the s390 processor related attributes are r/w */
> > +#define KVM_S390_VM_CPU_PROCESSOR 0
> > +struct kvm_s390_vm_cpu_processor {
> > + __u64 cpuid;
> > + __u16 ibc;
> > + __u8 pad[6];
> > + __u64 fac_list[256];
> > +};
> > +
> > +/* the machine related attributes are read only */
> > +#define KVM_S390_VM_CPU_MACHINE1
> > +struct kvm_s390_vm_cpu_machine {
> > + __u64 cpuid;
> > + __u32 ibc_range;
> > +
Re: [Qemu-devel] [PATCH v1 RFC 6/6] KVM: s390: add cpu model support
On 20.05.14 12:02, Michael Mueller wrote:
On Mon, 19 May 2014 22:14:00 +0200
Alexander Graf wrote:
On 19.05.14 19:03, Michael Mueller wrote:
On Mon, 19 May 2014 16:49:28 +0200
Alexander Graf wrote:
[...]
What user and thus also user space wants depends on other factors:
1. reliability
2. performance
3. availability
It's not features, that's what programmers want.
That's why I have designed the model and migration capability around the
hardware
and not around the software features and don't allow them to be enabled
currently
together.
A software feature is a nice add on that is helpful for evaluation or
development
purpose. There is few space for it on productions systems.
One option that I currently see to make software implemented facility migration
capable is to calculate some kind of hash value derived from the full set of
active software facilities. That value can be compared with pre-calculated
values also stored in the supported model table of qemu. This value could be
seen like a virtual model extension that has to match like the model name.
But I have said it elsewhere already, a soft facility should be an exception and
not the rule.
So all we need is a list of "features the guest sees available" which is
the same as "features user space wants the guest to see" which then gets
masked through "features the host can do in hardware".
For emulation we can just check on the global feature availability on
whether we should emulate them or not.
Also, if user space wants to make sure that its feature list is actually
workable on the host kernel, it needs to set and get the features again
and then compare that with the ones it set? That's different from x86's
cpuid implementation but probably workable.
User space will probe what facilities are available and match them with the
predefined
cpu model set. Only those models which use a partial or full subset of the
hard/host
facility list are selectable.
Why?
If a host does not offer the features required for a model it is not able to
run efficiently.
Please take a look at how x86 does cpuid masking :).
In fact, I'm not 100% convinced that it's a good idea to link cpuid /
feature list exposure to the guest and actual feature implementation
inside the guest together. On POWER there is a patch set pending that
implements these two things separately - admittedly mostly because
hardware sucks and we can't change the PVR.
That is maybe the big difference with s390. The cpuid in the S390 case is not
directly comparable with the processor version register of POWER.
In the S390 world we have a well defined CPU model room spanned by the machine
type and its GA count. Thus we can define a bijective mapping between
(type, ga) <-> (cpuid, ibc, facility set). From type and ga we form the model
name which BTW is meaningful also for a human user.
Same thing as POWER.
By means of this name, a management interface (libvirt) will draw decisions if
migration to a remote hypervisor is a good idea or not. For that it just needs
to compare if the current model of the guest on the source hypervisor
("query-cpu-model"), is contained in the supported model list of the target
hypervisor ("query-cpu-definitions").
I don't think this works, since QEMU should always return all the cpu
definitions it's aware of on query-cpu-definitions, not just the ones
that it thinks may be compatible with the host at a random point in time.
It does not return model names that it thinks they are compatible at some point
in time. In s390 mode, it returns all definitions (CPU models) that a given host
system is capable to run. Together with the CPU model run by the guest, some
upper
management interface knows if the hypervisor supports the required CPU model and
uses a guest definition with the same CPU model on the target hypervisor.
The information for that is taken from the model table which QEMU builds up
during
startup time. This list limits the command line selectable CPU models as well.
This makes s390 derive from the way x86 handles things. NAK.
One second, that goes a little fast here :-). x86 returns a list they support
which happens to
be the full list they define and s390 does logically the same because we know
that certain
models are not supported due to probing. BTW that happens only if you run Qemu
on back
level hardware and that is perfectly correct.
It's not what other architectures do and I'd hate to see s390 deviate
just because.
Only these four architectures implement the query and they all differ a
little...
target-arm/helper.c:CpuDefinitionInfoList *arch_query_cpu_definitions(Error
**errp)
target-i386/cpu.c:CpuDefinitionInfoList *arch_query_cpu_definitions(Error
**errp)
target-ppc/translate_init.c:CpuDefinitionInfoList
*arch_query_cpu_definitions(Error **errp)
target-s390x/cpu.c:CpuDefinitionInfoList *arch_query_cpu_definitions(Error
**errp)
arm walks through a list of all ARM CPU types
list = object_class_get_list(TYPE_ARM_CPU
[Bug 53601] nVMX meta-bug
https://bugzilla.kernel.org/show_bug.cgi?id=53601
Bug 53601 depends on bug 45931, which changed state.
Bug 45931 Summary: Nested Virt: VMX can't be initialized in L1 Xen ("Xen on
KVM")
https://bugzilla.kernel.org/show_bug.cgi?id=45931
What|Removed |Added
Status|NEW |RESOLVED
Resolution|--- |CODE_FIX
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[Bug 45931] Nested Virt: VMX can't be initialized in L1 Xen ("Xen on KVM")
https://bugzilla.kernel.org/show_bug.cgi?id=45931 Paolo Bonzini changed: What|Removed |Added Status|NEW |RESOLVED CC||bonz...@gnu.org Resolution|--- |CODE_FIX --- Comment #3 from Paolo Bonzini --- Patches were committed to kvm/next and will be included in 3.16. -- You are receiving this mail because: You are watching the assignee of the bug. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Bug 65561] KVM:Entry failed on Single stepping sti instruction
https://bugzilla.kernel.org/show_bug.cgi?id=65561 Paolo Bonzini changed: What|Removed |Added CC||bonz...@gnu.org --- Comment #3 from Paolo Bonzini --- > 2. Also is there anything special about `out` instruction that causes > interrupts to come at instruction immediately next to it, when not running in > single stepping mode. The "out" instruction exits to QEMU and has a much higher latency than an bare-metal. This, plus the usage of mutexes in QEMU, may make it more likely that interrupts occur right after an "out" instruction. -- You are receiving this mail because: You are watching the assignee of the bug. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 00/12] kvm tools: Misc patches (mips support)
On 19/05/14 17:53, Andreas Herrmann wrote: > Hi, > > These patches contain changes that I am currently using on top of > git://github.com/penberg/linux-kvm.git (as of v3.13-rc1-1427-gd9147fb) > to run lkvm on MIPS. > > The core is David's work for mips support and loading elf binaries. > > I rebased his stuff, rearranged patches somewhat and split out general > (non-mips-specific) modifications. > > I used it to test a paravirtualized guest on a host running KVM with > MIPS-VZ (on octeon3). > > Changelog: > v2: > - Removed superfluous includes in tools/kvm/Makefile (mips) > - Fixed debug output format for register dump (mips) (when using >32-bit lkvm with 64-bit guest) > - Added comment for guest type (KVM_VM_TYPE) (mips) > - Added check for upper bound of len in hypercall_write_cons (mips) > - Modified patch sequence to avoid temporary introduction of >load_bzimage (mips) > - Added patch to return number of bytes written by term_putc > v1: > - > http://marc.info/?i=1399391491-5021-1-git-send-email-andreas.herrm...@caviumnetworks.com > > Please apply -- if there are no additional comments or objections. I don't know what Pekka's policy is for kvm tools, but to avoid confusion I'd like to make clear that this patchset depends on a KVM implementation (KVM_VM_TYPE==1 for VZ) which hasn't been accepted into the mainline kernel yet. Cheers James -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 08/12] kvm tools: Provide per arch macro to specify type for KVM_CREATE_VM
On 19/05/14 17:53, Andreas Herrmann wrote:
> This is is usually 0 for most archs. On mips we have two types.
> TE (type 0) and MIPS-VZ (type 1). Default to 1 on mips.
Minor thing I didn't spot with v1 (sorry).
I think this patch should probably be moved before patch 6 with the mips
part squashed into patch 6, otherwise AFAICT the mips support in patch
6/7 is broken out of the box until this patch fixes it.
Cheers
James
>
> Signed-off-by: Andreas Herrmann
> ---
> tools/kvm/arm/include/arm-common/kvm-arch.h |2 ++
> tools/kvm/kvm.c |2 +-
> tools/kvm/mips/include/kvm/kvm-arch.h |5 +
> tools/kvm/powerpc/include/kvm/kvm-arch.h|2 ++
> tools/kvm/x86/include/kvm/kvm-arch.h|2 ++
> 5 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/tools/kvm/arm/include/arm-common/kvm-arch.h
> b/tools/kvm/arm/include/arm-common/kvm-arch.h
> index b6c4bf8..a552163 100644
> --- a/tools/kvm/arm/include/arm-common/kvm-arch.h
> +++ b/tools/kvm/arm/include/arm-common/kvm-arch.h
> @@ -32,6 +32,8 @@
>
> #define KVM_IRQ_OFFSET GIC_SPI_IRQ_BASE
>
> +#define KVM_VM_TYPE 0
> +
> #define VIRTIO_DEFAULT_TRANS(kvm)\
> ((kvm)->cfg.arch.virtio_trans_pci ? VIRTIO_PCI : VIRTIO_MMIO)
>
> diff --git a/tools/kvm/kvm.c b/tools/kvm/kvm.c
> index 6046434..e1b9f6c 100644
> --- a/tools/kvm/kvm.c
> +++ b/tools/kvm/kvm.c
> @@ -284,7 +284,7 @@ int kvm__init(struct kvm *kvm)
> goto err_sys_fd;
> }
>
> - kvm->vm_fd = ioctl(kvm->sys_fd, KVM_CREATE_VM, 0);
> + kvm->vm_fd = ioctl(kvm->sys_fd, KVM_CREATE_VM, KVM_VM_TYPE);
> if (kvm->vm_fd < 0) {
> pr_err("KVM_CREATE_VM ioctl");
> ret = kvm->vm_fd;
> diff --git a/tools/kvm/mips/include/kvm/kvm-arch.h
> b/tools/kvm/mips/include/kvm/kvm-arch.h
> index 4a8407b..7eadbf4 100644
> --- a/tools/kvm/mips/include/kvm/kvm-arch.h
> +++ b/tools/kvm/mips/include/kvm/kvm-arch.h
> @@ -17,6 +17,11 @@
>
> #define KVM_IRQ_OFFSET 1
>
> +/*
> + * MIPS-VZ (trap and emulate is 0)
> + */
> +#define KVM_VM_TYPE 1
> +
> #define VIRTIO_DEFAULT_TRANS(kvm)VIRTIO_PCI
>
> #include
> diff --git a/tools/kvm/powerpc/include/kvm/kvm-arch.h
> b/tools/kvm/powerpc/include/kvm/kvm-arch.h
> index f8627a2..fdd518f 100644
> --- a/tools/kvm/powerpc/include/kvm/kvm-arch.h
> +++ b/tools/kvm/powerpc/include/kvm/kvm-arch.h
> @@ -44,6 +44,8 @@
>
> #define KVM_IRQ_OFFSET 16
>
> +#define KVM_VM_TYPE 0
> +
> #define VIRTIO_DEFAULT_TRANS(kvm)VIRTIO_PCI
>
> struct spapr_phb;
> diff --git a/tools/kvm/x86/include/kvm/kvm-arch.h
> b/tools/kvm/x86/include/kvm/kvm-arch.h
> index a9f23b8..673bdf1 100644
> --- a/tools/kvm/x86/include/kvm/kvm-arch.h
> +++ b/tools/kvm/x86/include/kvm/kvm-arch.h
> @@ -27,6 +27,8 @@
>
> #define KVM_IRQ_OFFSET 5
>
> +#define KVM_VM_TYPE 0
> +
> #define VIRTIO_DEFAULT_TRANS(kvm)VIRTIO_PCI
>
> struct kvm_arch {
>
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Re: [PATCH 6/6] KVM: PPC: Book3S PR: Expose TM registers
On 20.05.2014, at 11:59, Paul Mackerras wrote:
> On Mon, May 19, 2014 at 03:09:07PM +0200, Alexander Graf wrote:
>>
>> On 17.05.14 08:20, Paul Mackerras wrote:
>>> On Tue, Apr 29, 2014 at 06:17:42PM +0200, Alexander Graf wrote:
POWER8 introduces transactional memory which brings along a number of new
registers and MSR bits.
Implementing all of those is a pretty big headache, so for now let's at
least
emulate enough to make Linux's context switching code happy.
>>> [snip]
>>>
- if (!(vcpu->arch.fscr & (1ULL << fac))) {
+ /* We get TM interrupts only when EBB is disabled? Sigh. */
>>> This comment doesn't make sense to me. Not every reason code reported
>>> in the high bits of FSCR corresponds directly to an enable bit in
>>> FSCR. In fact, of the 7 defined reason codes in POWER8, only three
>>> correspond to an enable bit...
>>
>> Is there any documentation on which relate to what?
>
> Yes, Power ISA v2.07 book 3S section 6.2.10 describes the FSCR enable
> bits and the interruption cause field. There are 6 cause values
> defined, of which 3 correspond to enable bits in the FSCR, and the
> other 3 correspond to things enabled/disabled in MMCR0 (usermode PMC
> anb BHRB access) or MSR (TM stuff).
I see. How's this?
Alex
commit a8e53f5f5e6c5d99363ad0d695a9ee520e1d262d
Author: Alexander Graf
Date: Tue Apr 29 17:54:40 2014 +0200
KVM: PPC: Book3S PR: Expose TM registers
POWER8 introduces transactional memory which brings along a number of new
registers and MSR bits.
Implementing all of those is a pretty big headache, so for now let's at
least
emulate enough to make Linux's context switching code happy.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- move to book3s_64 only section
- restrict to CONFIG_PPC_TRANSACTIONAL_MEM
v2 -> v3:
- check MSR.TM for TM enablement inside the guest
diff --git a/arch/powerpc/kvm/book3s_emulate.c
b/arch/powerpc/kvm/book3s_emulate.c
index e1165ba..9bdff15 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -451,6 +451,17 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu,
int sprn, ulong spr_val)
case SPRN_EBBRR:
vcpu->arch.ebbrr = spr_val;
break;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+ case SPRN_TFHAR:
+ vcpu->arch.tfhar = spr_val;
+ break;
+ case SPRN_TEXASR:
+ vcpu->arch.texasr = spr_val;
+ break;
+ case SPRN_TFIAR:
+ vcpu->arch.tfiar = spr_val;
+ break;
+#endif
#endif
case SPRN_ICTC:
case SPRN_THRM1:
@@ -572,6 +583,17 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu,
int sprn, ulong *spr_val
case SPRN_EBBRR:
*spr_val = vcpu->arch.ebbrr;
break;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+ case SPRN_TFHAR:
+ *spr_val = vcpu->arch.tfhar;
+ break;
+ case SPRN_TEXASR:
+ *spr_val = vcpu->arch.texasr;
+ break;
+ case SPRN_TFIAR:
+ *spr_val = vcpu->arch.tfiar;
+ break;
+#endif
#endif
case SPRN_THRM1:
case SPRN_THRM2:
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 7d27a95..23367a7 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -794,9 +794,27 @@ static void kvmppc_emulate_fac(struct kvm_vcpu *vcpu,
ulong fac)
/* Enable facilities (TAR, EBB, DSCR) for the guest */
static int kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac)
{
+ bool guest_fac_enabled;
BUG_ON(!cpu_has_feature(CPU_FTR_ARCH_207S));
- if (!(vcpu->arch.fscr & (1ULL << fac))) {
+ /*
+* Not every facility is enabled by FSCR bits, check whether the
+* guest has this facility enabled at all.
+*/
+ switch (fac) {
+ case FSCR_TAR_LG:
+ case FSCR_EBB_LG:
+ guest_fac_enabled = (vcpu->arch.fscr & (1ULL << fac));
+ break;
+ case FSCR_TM_LG:
+ guest_fac_enabled = kvmppc_get_msr(vcpu) & MSR_TM;
+ break;
+ default:
+ guest_fac_enabled = false;
+ break;
+ }
+
+ if (!guest_fac_enabled) {
/* Facility not enabled by the guest */
kvmppc_trigger_fac_interrupt(vcpu, fac);
return RESUME_GUEST;--
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[PATCH 00/15] MIPS: Add mips_paravirt
Hi, Following patches add support for paravirtualized guest on mips (mips_paravirt). Some of the patches add basic support to run it on octeon3. The core of mips_paravirt is David's work. I rebased his code, rearranged it somewhat (e.g. split it into the current patches) and added some minor modifications. I've run it using lkvm on a host with KVM MIPS-VZ support (on octeon3). I've tested guest kernels built for CPU_MIPS64_R2 and CPU_MIPS32_R2. When the guest kernel is built for CPU_CAVIUM_OCTEON it requires an additional patch to avoid usage of octeon_send_ipi_single in octeon_flush_icache_all_cores. Latest patch for this is not yet included as it caused a regression and needs some rework. To built a mips_paravirt guest kernel it's easiest to start with mips_paravirt_defconfig, check/modify CPU selection (defconfig has CPU_MIPS64_R2), and kick off kernel built. Patches are against v3.15-rc5. Diffstat is arch/mips/Kbuild.platforms |1 + arch/mips/Kconfig | 30 +- arch/mips/cavium-octeon/Kconfig| 30 +- arch/mips/configs/mips_paravirt_defconfig | 1521 arch/mips/include/asm/cpu-features.h |9 +- arch/mips/include/asm/cpu-type.h |1 + .../asm/mach-cavium-octeon/cpu-feature-overrides.h |1 - .../asm/mach-paravirt/cpu-feature-overrides.h | 36 + arch/mips/include/asm/mach-paravirt/irq.h | 19 + .../include/asm/mach-paravirt/kernel-entry-init.h | 49 + arch/mips/include/asm/mach-paravirt/war.h | 25 + arch/mips/include/asm/mipsregs.h | 72 + arch/mips/include/asm/r4kcache.h |2 + arch/mips/kernel/Makefile |2 +- arch/mips/kernel/branch.c |6 +- arch/mips/kernel/octeon_switch.S | 84 +- arch/mips/kernel/r4k_switch.S |3 + arch/mips/math-emu/cp1emu.c| 12 +- arch/mips/mm/c-r4k.c | 32 + arch/mips/mm/tlbex.c |8 +- arch/mips/paravirt/Kconfig |6 + arch/mips/paravirt/Makefile| 14 + arch/mips/paravirt/Platform|9 + arch/mips/paravirt/paravirt-irq.c | 388 + arch/mips/paravirt/paravirt-smp.c | 149 ++ arch/mips/paravirt/serial.c| 38 + arch/mips/paravirt/setup.c | 67 + arch/mips/pci/Makefile |2 +- arch/mips/pci/pci-virtio-guest.c | 140 ++ 29 files changed, 2709 insertions(+), 47 deletions(-) Comments are welcome. Thanks, Andreas -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 01/15] MIPS: OCTEON: Enable use of FPU.
From: David Daney
Some versions of the assembler will not assemble CFC1 for OCTEON, so
override the ISA for these.
Add r4k_fpu.o to handle low level FPU initialization.
Modify octeon_switch.S to save the FPU registers. And include
r4k_switch.S to pick up more FPU support.
Get rid of "#define cpu_has_fpu 0"
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
.../asm/mach-cavium-octeon/cpu-feature-overrides.h |1 -
arch/mips/kernel/Makefile |2 +-
arch/mips/kernel/branch.c |6 +-
arch/mips/kernel/octeon_switch.S | 84 ++--
arch/mips/kernel/r4k_switch.S |3 +
arch/mips/math-emu/cp1emu.c| 12 ++-
6 files changed, 80 insertions(+), 28 deletions(-)
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 94ed063..cf80228 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -22,7 +22,6 @@
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 0
#define cpu_has_tx39_cache 0
-#define cpu_has_fpu0
#define cpu_has_counter1
#define cpu_has_watch 1
#define cpu_has_divec 1
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 277dab3..1d07f3c 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -42,7 +42,7 @@ obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R3000)+= r2300_fpu.o r2300_switch.o
obj-$(CONFIG_CPU_R6000)+= r6000_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
-obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
+obj-$(CONFIG_CPU_CAVIUM_OCTEON)+= r4k_fpu.o octeon_switch.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SMP_UP) += smp-up.o
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 4d78bf4..418865f 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -366,7 +366,11 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
case cop1_op:
preempt_disable();
if (is_fpu_owner())
- asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+ asm volatile(
+ ".set push\n"
+ "\t.set mips1\n"
+ "\tcfc1\t%0,$31\n"
+ "\t.set pop" : "=r" (fcr31));
else
fcr31 = current->thread.fpu.fcr31;
preempt_enable();
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index 029e002..f654768 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -10,24 +10,12 @@
* Copyright (C) 2000 MIPS Technologies, Inc.
*written by Carsten Langgaard, carst...@mips.com
*/
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include
-
-/*
- * Offset to the current process status flags, the first 32 bytes of the
- * stack are not used.
- */
-#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
+#define USE_ALTERNATE_RESUME_IMPL 1
+ .set push
+ .set arch=mips64r2
+#include "r4k_switch.S"
+ .set pop
/*
* task_struct *resume(task_struct *prev, task_struct *next,
*struct thread_info *next_ti, int usedfpu)
@@ -40,6 +28,61 @@
cpu_save_nonscratch a0
LONG_S ra, THREAD_REG31(a0)
+ /*
+* check if we need to save FPU registers
+*/
+ PTR_L t3, TASK_THREAD_INFO(a0)
+ LONG_L t0, TI_FLAGS(t3)
+ li t1, _TIF_USEDFPU
+ and t2, t0, t1
+ beqzt2, 1f
+ nor t1, zero, t1
+
+ and t0, t0, t1
+ LONG_S t0, TI_FLAGS(t3)
+
+ /*
+* clear saved user stack CU1 bit
+*/
+ LONG_L t0, ST_OFF(t3)
+ li t1, ~ST0_CU1
+ and t0, t0, t1
+ LONG_S t0, ST_OFF(t3)
+
+ .set push
+ .set arch=mips64r2
+ fpu_save_double a0 t0 t1# c0_status passed in t0
+ # clobbers t1
+ .set pop
+1:
+
+ /* check if we need to save COP2 registers */
+ PTR_L t2, TASK_THREAD_INFO(a0)
+ LONG_L t0, ST_OFF(t2)
+ bbit0 t0, 30, 1f
+
+ /* Disable COP2 in the stored process state */
+ li t1, ST0_CU2
+ xor t0, t1
+ LONG_S t0, ST_OFF(t2)
+
+ /* Enable COP2 so we can save it */
+ mfc0t0, CP0_STATUS
+ or t0, t1
+ mtc0t0, CP0_STATUS
+
+ /* Save COP2 */
+ daddu a0, THREAD_CP2
+ jal octeon_cop2_save
+ dsubu a0, THR
[PATCH 05/15] MIPS: Don't build fast TLB refill handler with 32-bit kernels.
From: David Daney
The fast handler only supports 64-bit kernels.
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/mm/tlbex.c |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index ee88367..781e183 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1250,13 +1250,17 @@ static void build_r4000_tlb_refill_handler(void)
unsigned int final_len;
struct mips_huge_tlb_info htlb_info __maybe_unused;
enum vmalloc64_mode vmalloc_mode __maybe_unused;
-
+#ifdef CONFIG_64BIT
+ bool is64bit = true;
+#else
+ bool is64bit = false;
+#endif
memset(tlb_handler, 0, sizeof(tlb_handler));
memset(labels, 0, sizeof(labels));
memset(relocs, 0, sizeof(relocs));
memset(final_handler, 0, sizeof(final_handler));
- if ((scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
+ if (is64bit && (scratch_reg >= 0 || scratchpad_available()) &&
use_bbit_insns()) {
htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
scratch_reg);
vmalloc_mode = refill_scratch;
--
1.7.9.5
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[PATCH 02/15] MIPS: Move system level config items from CPU_CAVIUM_OCTEON to CAVIUM_OCTEON_SOC
From: David Daney They are a property of the SoC not the CPU itself. Signed-off-by: David Daney Signed-off-by: Andreas Herrmann --- arch/mips/Kconfig | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5cd695f..de32ab5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -721,6 +721,11 @@ config CAVIUM_OCTEON_SOC select ZONE_DMA32 select HOLES_IN_ZONE select ARCH_REQUIRE_GPIOLIB + select LIBFDT + select USE_OF + select ARCH_SPARSEMEM_ENABLE + select SYS_SUPPORTS_SMP + select NR_CPUS_DEFAULT_16 help This option supports all of the Octeon reference boards from Cavium Networks. It builds a kernel that dynamically determines the Octeon @@ -1398,16 +1403,11 @@ config CPU_SB1 config CPU_CAVIUM_OCTEON bool "Cavium Octeon processor" depends on SYS_HAS_CPU_CAVIUM_OCTEON - select ARCH_SPARSEMEM_ENABLE select CPU_HAS_PREFETCH select CPU_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_SMP - select NR_CPUS_DEFAULT_16 select WEAK_ORDERING select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES - select LIBFDT - select USE_OF select USB_EHCI_BIG_ENDIAN_MMIO select MIPS_L1_CACHE_SHIFT_7 help -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 04/15] MIPS: Don't use RI/XI with 32-bit kernels on 64-bit CPUs.
From: David Daney The TLB handlers cannot handle this case, so disable it for now. Signed-off-by: David Daney Signed-off-by: Andreas Herrmann --- arch/mips/include/asm/cpu-features.h |9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index f56cc97..01486eb 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -110,9 +110,15 @@ #ifndef cpu_has_smartmips #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif + #ifndef cpu_has_rixi -#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) +# ifdef CONFIG_64BIT +# define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) +# else /* CONFIG_32BIT */ +# define cpu_has_rixi ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits) +# endif #endif + #ifndef cpu_has_mmips # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS # define cpu_has_mmips(cpu_data[0].options & MIPS_CPU_MICROMIPS) @@ -120,6 +126,7 @@ # define cpu_has_mmips0 # endif #endif + #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache(cpu_data[0].icache.flags & MIPS_CACHE_VTAG) #endif -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 03/15] MIPS: OCTEON: Move CAVIUM_OCTEON_CVMSEG_SIZE to CPU_CAVIUM_OCTEON
From: David Daney CVMSEG is related to the CPU core not the SoC system. So needs to be configurable there. Signed-off-by: David Daney Signed-off-by: Andreas Herrmann --- arch/mips/cavium-octeon/Kconfig | 30 -- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index 227705d..c5e9975 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -10,6 +10,17 @@ config CAVIUM_CN63XXP1 non-CN63XXP1 hardware, so it is recommended to select "n" unless it is known the workarounds are needed. +config CAVIUM_OCTEON_CVMSEG_SIZE + int "Number of L1 cache lines reserved for CVMSEG memory" + range 0 54 + default 1 + help + CVMSEG LM is a segment that accesses portions of the dcache as a + local memory; the larger CVMSEG is, the smaller the cache is. + This selects the size of CVMSEG LM, which is in cache blocks. The + legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is + between zero and 6192 bytes). + endif # CPU_CAVIUM_OCTEON if CAVIUM_OCTEON_SOC @@ -23,16 +34,16 @@ config CAVIUM_OCTEON_2ND_KERNEL with this option to be run at the same time as one built without this option. -config CAVIUM_OCTEON_CVMSEG_SIZE - int "Number of L1 cache lines reserved for CVMSEG memory" - range 0 54 - default 1 +config CAVIUM_OCTEON_HW_FIX_UNALIGNED + bool "Enable hardware fixups of unaligned loads and stores" + default "y" help - CVMSEG LM is a segment that accesses portions of the dcache as a - local memory; the larger CVMSEG is, the smaller the cache is. - This selects the size of CVMSEG LM, which is in cache blocks. The - legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is - between zero and 6192 bytes). + Configure the Octeon hardware to automatically fix unaligned loads + and stores. Normally unaligned accesses are fixed using a kernel + exception handler. This option enables the hardware automatic fixups, + which requires only an extra 3 cycles. Disable this option if you + are running code that relies on address exceptions on unaligned + accesses. config CAVIUM_OCTEON_LOCK_L2 bool "Lock often used kernel code in the L2" @@ -86,7 +97,6 @@ config SWIOTLB select IOMMU_HELPER select NEED_SG_DMA_LENGTH - config OCTEON_ILM tristate "Module to measure interrupt latency using Octeon CIU Timer" help -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 06/15] MIPS: Add minimal support for OCTEON3 to c-r4k.c
From: David Daney
These are needed to boot a generic mips64r2 kernel on OCTEONIII.
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/include/asm/r4kcache.h |2 ++
arch/mips/mm/c-r4k.c | 32
2 files changed, 34 insertions(+)
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index ca64cbe..1d86791 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -524,6 +524,8 @@ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD,
Hit_Writeback_Inv_SD, 32,
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64,
)
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD,
64, )
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
128, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD,
128, )
__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D,
16, )
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 1c74a6a..789ede9 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -109,6 +109,12 @@ static inline void r4k_blast_dcache_page_dc64(unsigned
long addr)
blast_dcache64_page(addr);
}
+static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
+{
+ R4600_HIT_CACHEOP_WAR_IMPL;
+ blast_dcache128_page(addr);
+}
+
static void r4k_blast_dcache_page_setup(void)
{
unsigned long dc_lsize = cpu_dcache_line_size();
@@ -121,6 +127,8 @@ static void r4k_blast_dcache_page_setup(void)
r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
else if (dc_lsize == 64)
r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
+ else if (dc_lsize == 128)
+ r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
}
#ifndef CONFIG_EVA
@@ -159,6 +167,8 @@ static void r4k_blast_dcache_page_indexed_setup(void)
r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
else if (dc_lsize == 64)
r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
+ else if (dc_lsize == 128)
+ r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
}
void (* r4k_blast_dcache)(void);
@@ -176,6 +186,8 @@ static void r4k_blast_dcache_setup(void)
r4k_blast_dcache = blast_dcache32;
else if (dc_lsize == 64)
r4k_blast_dcache = blast_dcache64;
+ else if (dc_lsize == 128)
+ r4k_blast_dcache = blast_dcache128;
}
/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
@@ -265,6 +277,8 @@ static void r4k_blast_icache_page_setup(void)
r4k_blast_icache_page = blast_icache32_page;
else if (ic_lsize == 64)
r4k_blast_icache_page = blast_icache64_page;
+ else if (ic_lsize == 128)
+ r4k_blast_icache_page = blast_icache128_page;
}
#ifndef CONFIG_EVA
@@ -338,6 +352,8 @@ static void r4k_blast_icache_setup(void)
r4k_blast_icache = blast_icache32;
} else if (ic_lsize == 64)
r4k_blast_icache = blast_icache64;
+ else if (ic_lsize == 128)
+ r4k_blast_icache = blast_icache128;
}
static void (* r4k_blast_scache_page)(unsigned long addr);
@@ -1094,6 +1110,21 @@ static void probe_pcache(void)
c->dcache.waybit = 0;
break;
+ case CPU_CAVIUM_OCTEON3:
+ /* For now lie about the number of ways. */
+ c->icache.linesz = 128;
+ c->icache.sets = 16;
+ c->icache.ways = 8;
+ c->icache.flags |= MIPS_CACHE_VTAG;
+ icache_size = c->icache.sets * c->icache.ways *
c->icache.linesz;
+
+ c->dcache.linesz = 128;
+ c->dcache.ways = 8;
+ c->dcache.sets = 8;
+ dcache_size = c->dcache.sets * c->dcache.ways *
c->dcache.linesz;
+ c->options |= MIPS_CPU_PREFETCH;
+ break;
+
default:
if (!(config & MIPS_CONF_M))
panic("Don't know how to probe P-caches on this cpu.");
@@ -1414,6 +1445,7 @@ static void setup_scache(void)
loongson3_sc_init();
return;
+ case CPU_CAVIUM_OCTEON3:
case CPU_XLP:
/* don't need to worry about L2, fully coherent */
return;
--
1.7.9.5
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[PATCH 08/15] MIPS: OCTEON: Add OCTEON3 to __get_cpu_type
Otherwise __builtin_unreachable might be called. Signed-off-by: Andreas Herrmann --- arch/mips/include/asm/cpu-type.h |1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h index 72190613..0bd77a0 100644 --- a/arch/mips/include/asm/cpu-type.h +++ b/arch/mips/include/asm/cpu-type.h @@ -166,6 +166,7 @@ static inline int __pure __get_cpu_type(const int cpu_type) case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: case CPU_CAVIUM_OCTEON2: + case CPU_CAVIUM_OCTEON3: #endif #if defined(CONFIG_SYS_HAS_CPU_BMIPS32_3300) || \ -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 09/15] MIPS: Add functions for hypervisor call
From: David Daney
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/include/asm/mipsregs.h | 67 ++
1 file changed, 67 insertions(+)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index f110d48..e12a518 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1916,6 +1916,73 @@ __BUILD_SET_C0(brcm_cmt_ctrl)
__BUILD_SET_C0(brcm_config)
__BUILD_SET_C0(brcm_mode)
+static inline unsigned long hypcall0(unsigned long num)
+{
+ register unsigned long n asm("v0");
+ register unsigned long r asm("v0");
+
+ n = num;
+ __asm__ __volatile__(
+ ".word 0x4228" /* HYPCALL */
+ : "=r" (r) : "r" (n) : "memory"
+ );
+
+ return r;
+}
+static inline unsigned long hypcall1(unsigned long num, unsigned long arg0)
+{
+ register unsigned long n asm("v0");
+ register unsigned long r asm("v0");
+ register unsigned long a0 asm("a0");
+
+ n = num;
+ a0 = arg0;
+ __asm__ __volatile__(
+ ".word 0x4228" /* HYPCALL */
+ : "=r" (r) : "r" (n), "r" (a0) : "memory"
+ );
+
+ return r;
+}
+static inline unsigned long hypcall2(unsigned long num, unsigned long arg0,
+unsigned long arg1)
+{
+ register unsigned long n asm("v0");
+ register unsigned long r asm("v0");
+ register unsigned long a0 asm("a0");
+ register unsigned long a1 asm("a1");
+
+ n = num;
+ a0 = arg0;
+ a1 = arg1;
+ __asm__ __volatile__(
+ ".word 0x4228" /* HYPCALL */
+ : "=r" (r) : "r" (n), "r" (a0), "r" (a1) : "memory"
+ );
+
+ return r;
+}
+static inline unsigned long hypcall3(unsigned long num, unsigned long arg0,
+unsigned long arg1, unsigned long arg2)
+{
+ register unsigned long n asm("v0");
+ register unsigned long r asm("v0");
+ register unsigned long a0 asm("a0");
+ register unsigned long a1 asm("a1");
+ register unsigned long a2 asm("a2");
+
+ n = num;
+ a0 = arg0;
+ a1 = arg1;
+ a2 = arg2;
+ __asm__ __volatile__(
+ ".word 0x4228" /* HYPCALL */
+ : "=r" (r) : "r" (n), "r" (a0), "r" (a1), "r" (a2) : "memory"
+ );
+
+ return r;
+}
+
static inline unsigned int mips_cpunum(void)
{
return read_c0_ebase() & 0x3ff; /* Low 10 bits of ebase. */
--
1.7.9.5
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[PATCH 07/15] MIPS: Add mips_cpunum() function.
From: David Daney
This returns the CPUNum from the low order Ebase bits.
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/include/asm/mipsregs.h |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 3e025b5..f110d48 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1916,6 +1916,11 @@ __BUILD_SET_C0(brcm_cmt_ctrl)
__BUILD_SET_C0(brcm_config)
__BUILD_SET_C0(brcm_mode)
+static inline unsigned int mips_cpunum(void)
+{
+ return read_c0_ebase() & 0x3ff; /* Low 10 bits of ebase. */
+}
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_MIPSREGS_H */
--
1.7.9.5
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[PATCH 15/15] MIPS: paravirt: Provide _machine_halt function to exit VM on shutdown of guest
Signed-off-by: Andreas Herrmann
---
arch/mips/paravirt/setup.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/mips/paravirt/setup.c b/arch/mips/paravirt/setup.c
index f80c3bc..6d2781c 100644
--- a/arch/mips/paravirt/setup.c
+++ b/arch/mips/paravirt/setup.c
@@ -8,6 +8,7 @@
#include
+#include
#include
#include
#include
@@ -27,6 +28,11 @@ void __init plat_time_init(void)
preset_lpj = mips_hpt_frequency / (2 * HZ);
}
+static void pv_machine_halt(void)
+{
+ hypcall0(1 /* Exit VM */);
+}
+
/*
* Early entry point for arch setup
*/
@@ -47,6 +53,7 @@ void __init prom_init(void)
if (i < argc - 1)
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
}
+ _machine_halt = pv_machine_halt;
register_smp_ops(¶virt_smp_ops);
}
--
1.7.9.5
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[PATCH 10/15] MIPS: Add code for new system 'paravirt'.
From: David Daney For para-virtualized guests running under KVM or other equivalent hypervisor. Signed-off-by: David Daney Signed-off-by: Andreas Herrmann --- .../asm/mach-paravirt/cpu-feature-overrides.h | 36 ++ arch/mips/include/asm/mach-paravirt/irq.h | 19 + .../include/asm/mach-paravirt/kernel-entry-init.h | 49 +++ arch/mips/include/asm/mach-paravirt/war.h | 25 ++ arch/mips/paravirt/Makefile| 14 + arch/mips/paravirt/Platform|9 + arch/mips/paravirt/paravirt-irq.c | 388 arch/mips/paravirt/paravirt-smp.c | 149 arch/mips/paravirt/serial.c| 38 ++ arch/mips/paravirt/setup.c | 60 +++ 10 files changed, 787 insertions(+) create mode 100644 arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-paravirt/irq.h create mode 100644 arch/mips/include/asm/mach-paravirt/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-paravirt/war.h create mode 100644 arch/mips/paravirt/Makefile create mode 100644 arch/mips/paravirt/Platform create mode 100644 arch/mips/paravirt/paravirt-irq.c create mode 100644 arch/mips/paravirt/paravirt-smp.c create mode 100644 arch/mips/paravirt/serial.c create mode 100644 arch/mips/paravirt/setup.c diff --git a/arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h b/arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h new file mode 100644 index 000..725e1ed --- /dev/null +++ b/arch/mips/include/asm/mach-paravirt/cpu-feature-overrides.h @@ -0,0 +1,36 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2013 Cavium, Inc. + */ +#ifndef __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_tx39_cache 0 +#define cpu_has_counter1 +#define cpu_has_llsc 1 +/* + * We Disable LL/SC on non SMP systems as it is faster to disable + * interrupts for atomic access than a LL/SC. + */ +#ifdef CONFIG_SMP +# define kernel_uses_llsc 1 +#else +# define kernel_uses_llsc 0 +#endif + +#ifdef CONFIG_CPU_CAVIUM_OCTEON +#define cpu_dcache_line_size() 128 +#define cpu_icache_line_size() 128 +#define cpu_has_octeon_cache 1 +#define cpu_has_4k_cache 0 +#else +#define cpu_has_octeon_cache 0 +#define cpu_has_4k_cache 1 +#endif + +#endif /* __ASM_MACH_PARAVIRT_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-paravirt/irq.h b/arch/mips/include/asm/mach-paravirt/irq.h new file mode 100644 index 000..9b4d35e --- /dev/null +++ b/arch/mips/include/asm/mach-paravirt/irq.h @@ -0,0 +1,19 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2013 Cavium, Inc. + */ +#ifndef __ASM_MACH_PARAVIRT_IRQ_H__ +#define __ASM_MACH_PARAVIRT_IRQ_H__ + +#define NR_IRQS 64 +#define MIPS_CPU_IRQ_BASE 1 + +#define MIPS_IRQ_PCIA (MIPS_CPU_IRQ_BASE + 8) + +#define MIPS_IRQ_MBOX0 (MIPS_CPU_IRQ_BASE + 32) +#define MIPS_IRQ_MBOX1 (MIPS_CPU_IRQ_BASE + 33) + +#endif /* __ASM_MACH_PARAVIRT_IRQ_H__ */ diff --git a/arch/mips/include/asm/mach-paravirt/kernel-entry-init.h b/arch/mips/include/asm/mach-paravirt/kernel-entry-init.h new file mode 100644 index 000..c812efa --- /dev/null +++ b/arch/mips/include/asm/mach-paravirt/kernel-entry-init.h @@ -0,0 +1,49 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2013 Cavium, Inc + */ +#ifndef __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H +#define __ASM_MACH_PARAVIRT_KERNEL_ENTRY_H + +#define CP0_EBASE $15, 1 + + .macro kernel_entry_setup + mfc0t0, CP0_EBASE + andit0, t0, 0x3ff # CPUNum + beqzt0, 1f + # CPUs other than zero goto smp_bootstrap + j smp_bootstrap + +1: + .endm + +/* + * Do SMP slave processor setup necessary before we can safely execute + * C code. + */ + .macro smp_slave_setup + mfc0t0, CP0_EBASE + andit0, t0, 0x3ff # CPUNum + sltit1, t0, NR_CPUS + bnezt1, 1f +2: + di + wait + b 2b # Unknown CPU, loop forever. +1: + PTR_LA t1, paravirt_smp_sp + PTR_SLL t0, PTR_SCALESHIFT + PTR_ADDU t1, t1, t0 +3: + PTR_L sp, 0(t1) + beqzsp, 3b # Spin until told to proceed. + + PTR_LA t1, paravirt_smp_gp + PTR_ADDU t1, t1, t0 +
[PATCH 11/15] MIPS: paravirt: Add pci controller for virtio
From: David Daney
Signed-off-by: David Daney
Signed-off-by: Andreas Herrmann
---
arch/mips/Kconfig|1 +
arch/mips/paravirt/Kconfig |6 ++
arch/mips/pci/Makefile |2 +-
arch/mips/pci/pci-virtio-guest.c | 140 ++
4 files changed, 148 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/paravirt/Kconfig
create mode 100644 arch/mips/pci/pci-virtio-guest.c
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index de32ab5..3621b4d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -814,6 +814,7 @@ source "arch/mips/cavium-octeon/Kconfig"
source "arch/mips/loongson/Kconfig"
source "arch/mips/loongson1/Kconfig"
source "arch/mips/netlogic/Kconfig"
+source "arch/mips/paravirt/Kconfig"
endmenu
diff --git a/arch/mips/paravirt/Kconfig b/arch/mips/paravirt/Kconfig
new file mode 100644
index 000..ecae586
--- /dev/null
+++ b/arch/mips/paravirt/Kconfig
@@ -0,0 +1,6 @@
+if MIPS_PARAVIRT
+
+config MIPS_PCI_VIRTIO
+ def_bool y
+
+endif # MIPS_PARAVIRT
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index d61138a..ff8a553 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -21,7 +21,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o
fixup-bcm63xx.o \
obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
-
+obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o
#
# These are still pretty much in the old state, watch, go blind.
#
diff --git a/arch/mips/pci/pci-virtio-guest.c b/arch/mips/pci/pci-virtio-guest.c
new file mode 100644
index 000..4ce5caa
--- /dev/null
+++ b/arch/mips/pci/pci-virtio-guest.c
@@ -0,0 +1,140 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2013 Cavium, Inc.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#define PCI_CONFIG_ADDRESS 0xcf8
+#define PCI_CONFIG_DATA0xcfc
+
+union pci_config_address {
+ struct {
+#ifdef __LITTLE_ENDIAN
+ unsignedregister_number : 8;/* 7 .. 0 */
+ unsigneddevfn_number: 8;/* 15 .. 8 */
+ unsignedbus_number : 8;/* 23 .. 16 */
+ unsignedreserved: 7;/* 30 .. 24 */
+ unsignedenable_bit : 1;/* 31 */
+#else
+ unsignedenable_bit : 1;/* 31 */
+ unsignedreserved: 7;/* 30 .. 24 */
+ unsignedbus_number : 8;/* 23 .. 16 */
+ unsigneddevfn_number: 8;/* 15 .. 8 */
+ unsignedregister_number : 8;/* 7 .. 0 */
+#endif
+ };
+ u32 w;
+};
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ return 0;
+}
+
+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+ return ((pin + slot) % 4)+ MIPS_IRQ_PCIA;
+}
+
+static unsigned long pci_virtio_guest_write_config_addr(struct pci_bus *bus,
unsigned int devfn, int reg)
+{
+ union pci_config_address pca;
+
+ pca.w = 0;
+ pca.register_number = reg;
+ pca.devfn_number = devfn;
+ pca.bus_number = bus->number;
+ pca.enable_bit = 1;
+
+ outl(pca.w, PCI_CONFIG_ADDRESS);
+
+ return PCI_CONFIG_DATA + (reg & 3);
+}
+
+static int pci_virtio_guest_write_config(struct pci_bus *bus, unsigned int
devfn,
+int reg, int size, u32 val)
+{
+ unsigned long port = pci_virtio_guest_write_config_addr(bus, devfn,
reg);
+
+ switch (size) {
+ case 1:
+ outb(val, port);
+ return PCIBIOS_SUCCESSFUL;
+ case 2:
+ outw(val, port);
+ return PCIBIOS_SUCCESSFUL;
+ case 4:
+ outl(val, port);
+ return PCIBIOS_SUCCESSFUL;
+ default:
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+ }
+}
+
+static int pci_virtio_guest_read_config(struct pci_bus *bus, unsigned int
devfn,
+ int reg, int size, u32 *val)
+{
+ unsigned long port = pci_virtio_guest_write_config_addr(bus, devfn,
reg);
+
+ switch (size) {
+ case 1:
+ *val = inb(port);
+ return PCIBIOS_SUCCESSFUL;
+ case 2:
+ *val = inw(port);
+ return PCIBIOS_SUCCESSFUL;
+ case 4:
+ *val = inl(port);
+ return PCIBIOS_SUCCESSFUL;
+ default:
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+ }
+}
+
+static struct pci_ops pci_virtio_guest_ops = {
+ .read = pci_virtio_guest_read_config,
+
[PATCH 13/15] MIPS: Add defconfig for mips_paravirt
From: David Daney Signed-off-by: David Daney Signed-off-by: Andreas Herrmann --- arch/mips/configs/mips_paravirt_defconfig | 1524 + 1 file changed, 1524 insertions(+) create mode 100644 arch/mips/configs/mips_paravirt_defconfig diff --git a/arch/mips/configs/mips_paravirt_defconfig b/arch/mips/configs/mips_paravirt_defconfig new file mode 100644 index 000..f0cac9c --- /dev/null +++ b/arch/mips/configs/mips_paravirt_defconfig @@ -0,0 +1,1524 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/mips 3.15.0-rc4 Kernel Configuration +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_ATH79 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_LANTIQ is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MACH_LOONGSON1 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD3 is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_RALINK is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_CAVIUM_OCTEON_SOC is not set +# CONFIG_NLM_XLR_BOARD is not set +# CONFIG_NLM_XLP_BOARD is not set +CONFIG_MIPS_PARAVIRT=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_CAVIUM_CN63XXP1 is not set +CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=1 +CONFIG_MIPS_PCI_VIRTIO=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_COHERENT=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_NO_IOPORT_MAP is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_MIPS_HUGE_TLB_SUPPORT=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_MIPS_L1_CACHE_SHIFT_7=y +CONFIG_MIPS_L1_CACHE_SHIFT=7 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R2 is not set +CONFIG_CPU_CAVIUM_OCTEON=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R2=y +CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y +CONFIG_WEAK_ORDERING=y +CONFIG_CPU_MIPSR2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HUGEPAGES=y +CONFIG_MIPS_PGD_C0_CONTEXT=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_64BIT=y +# CONFIG_KVM_GUEST is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +# CONFIG_CMA is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +# CONFIG_SMP is not set +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_NR_CPUS_DEFAULT_4=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_SECCOMP=y +# CONFIG_MIPS_O32_FP64_SUPPORT is not se
[PATCH 12/15] MIPS: Enable build for new system 'paravirt'.
From: David Daney Signed-off-by: David Daney Signed-off-by: Andreas Herrmann --- arch/mips/Kbuild.platforms |1 + arch/mips/Kconfig | 19 +++ 2 files changed, 20 insertions(+) diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 6e23912..f5e18bf 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -18,6 +18,7 @@ platforms += loongson1 platforms += mti-malta platforms += mti-sead3 platforms += netlogic +platforms += paravirt platforms += pmcs-msp71xx platforms += pnx833x platforms += ralink diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3621b4d..f957637 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -794,6 +794,25 @@ config NLM_XLP_BOARD This board is based on Netlogic XLP Processor. Say Y here if you have a XLP based board. +config MIPS_PARAVIRT + bool "Para-Virtualized guest system" + select CEVT_R4K + select CSRC_R4K + select DMA_COHERENT + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_SMP + select NR_CPUS_DEFAULT_4 + select SYS_HAS_EARLY_PRINTK + select SYS_HAS_CPU_MIPS32_R2 + select SYS_HAS_CPU_MIPS64_R2 + select SYS_HAS_CPU_CAVIUM_OCTEON + select HW_HAS_PCI + select SWAP_IO_SPACE + help + This option supports guest running under + endchoice source "arch/mips/alchemy/Kconfig" -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 14/15] MIPS: paravirt: Update mips_paravirt_defconfig
Change CPU selection, enable SMP, enable almost all virtio options. Signed-off-by: Andreas Herrmann --- arch/mips/configs/mips_paravirt_defconfig | 69 ++--- 1 file changed, 33 insertions(+), 36 deletions(-) diff --git a/arch/mips/configs/mips_paravirt_defconfig b/arch/mips/configs/mips_paravirt_defconfig index f0cac9c..f3215b49 100644 --- a/arch/mips/configs/mips_paravirt_defconfig +++ b/arch/mips/configs/mips_paravirt_defconfig @@ -49,10 +49,6 @@ CONFIG_MIPS=y # CONFIG_NLM_XLP_BOARD is not set CONFIG_MIPS_PARAVIRT=y # CONFIG_ALCHEMY_GPIO_INDIRECT is not set -# CONFIG_MACH_TX39XX is not set -# CONFIG_MACH_TX49XX is not set -# CONFIG_CAVIUM_CN63XXP1 is not set -CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=1 CONFIG_MIPS_PCI_VIRTIO=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set @@ -72,22 +68,22 @@ CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_SYS_SUPPORTS_HUGETLBFS=y CONFIG_MIPS_HUGE_TLB_SUPPORT=y CONFIG_SWAP_IO_SPACE=y -CONFIG_MIPS_L1_CACHE_SHIFT_7=y -CONFIG_MIPS_L1_CACHE_SHIFT=7 +CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # # CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R2 is not set -CONFIG_CPU_CAVIUM_OCTEON=y +CONFIG_CPU_MIPS64_R2=y +# CONFIG_CPU_CAVIUM_OCTEON is not set CONFIG_SYS_HAS_CPU_MIPS32_R2=y CONFIG_SYS_HAS_CPU_MIPS64_R2=y CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y -CONFIG_WEAK_ORDERING=y +CONFIG_CPU_MIPS64=y CONFIG_CPU_MIPSR2=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HUGEPAGES=y CONFIG_MIPS_PGD_C0_CONTEXT=y @@ -96,20 +92,22 @@ CONFIG_HARDWARE_WATCHPOINTS=y # # Kernel type # +# CONFIG_32BIT is not set CONFIG_64BIT=y -# CONFIG_KVM_GUEST is not set CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_32KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_CPU_HAS_PREFETCH=y CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_R4K_CACHE_TLB=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_CPU_HAS_MSA=y CONFIG_CPU_HAS_SYNC=y CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y @@ -119,6 +117,7 @@ CONFIG_ARCH_DISCARD_MEMBLOCK=y # CONFIG_HAVE_BOOTMEM_INFO_NODE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_BALLOON_COMPACTION=y CONFIG_COMPACTION=y CONFIG_MIGRATION=y CONFIG_PHYS_ADDR_T_64BIT=y @@ -130,15 +129,15 @@ CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_NEED_PER_CPU_KM=y # CONFIG_CLEANCACHE is not set # CONFIG_FRONTSWAP is not set # CONFIG_CMA is not set # CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set -# CONFIG_SMP is not set +CONFIG_SMP=y CONFIG_SYS_SUPPORTS_SMP=y CONFIG_NR_CPUS_DEFAULT_4=y +CONFIG_NR_CPUS=4 # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -165,7 +164,6 @@ CONFIG_BUILDTIME_EXTABLE_SORT=y # # General setup # -CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_CROSS_COMPILE="" # CONFIG_COMPILE_TEST is not set @@ -175,8 +173,7 @@ CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y -CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set # CONFIG_FHANDLE is not set CONFIG_USELIB=y # CONFIG_AUDIT is not set @@ -196,6 +193,7 @@ CONFIG_GENERIC_CMOS_UPDATE=y # CONFIG_HZ_PERIODIC=y # CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ_FULL is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set @@ -214,6 +212,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TREE_PREEMPT_RCU=y CONFIG_PREEMPT_RCU=y CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_USER_QS is not set CONFIG_RCU_FANOUT=64 CONFIG_RCU_FANOUT_LEAF=16 # CONFIG_RCU_FANOUT_EXACT is not set @@ -317,6 +316,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set +CONFIG_STOP_MACHINE=y CONFIG_BLOCK=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSGLIB is not set @@ -342,7 +342,8 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_FREEZER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) @@ -387,18 +388,7 @@ CONFIG_BINFMT_ELF32=y # # Power management options # -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -# CONFIG_HIBERNATION is not set -CONFIG_PM_SLEEP=y -# CONFIG_PM_AUTOSLEEP is not set -# CONFIG_PM_WAKELOCKS is not set # CONFIG_PM_RUNTIME is not set -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set CONFIG_NET=y # @@
[PATCH v3] PCI: Introduce new device binding path using pci_dev.driver_override
The driver_override field allows us to specify the driver for a device
rather than relying on the driver to provide a positive match of the
device. This shortcuts the existing process of looking up the vendor
and device ID, adding them to the driver new_id, binding the device,
then removing the ID, but it also provides a couple advantages.
First, the above existing process allows the driver to bind to any
device matching the new_id for the window where it's enabled. This is
often not desired, such as the case of trying to bind a single device
to a meta driver like pci-stub or vfio-pci. Using driver_override we
can do this deterministically using:
echo pci-stub > /sys/bus/pci/devices/:03:00.0/driver_override
echo :03:00.0 > /sys/bus/pci/devices/:03:00.0/driver/unbind
echo :03:00.0 > /sys/bus/pci/drivers_probe
Previously we could not invoke drivers_probe after adding a device
to new_id for a driver as we get non-deterministic behavior whether
the driver we intend or the standard driver will claim the device.
Now it becomes a deterministic process, only the driver matching
driver_override will probe the device.
To return the device to the standard driver, we simply clear the
driver_override and reprobe the device:
echo > /sys/bus/pci/devices/:03:00.0/driver_override
echo :03:00.0 > /sys/bus/pci/devices/:03:00.0/driver/unbind
echo :03:00.0 > /sys/bus/pci/drivers_probe
Another advantage to this approach is that we can specify a driver
override to force a specific binding or prevent any binding. For
instance when an IOMMU group is exposed to userspace through VFIO
we require that all devices within that group are owned by VFIO.
However, devices can be hot-added into an IOMMU group, in which case
we want to prevent the device from binding to any driver (override
driver = "none") or perhaps have it automatically bind to vfio-pci.
With driver_override it's a simple matter for this field to be set
internally when the device is first discovered to prevent driver
matches.
Signed-off-by: Alex Williamson
Cc: Greg Kroah-Hartman
---
v3: kfree() override buffer on device release, noted by Alex Graf
v2: Use strchr() as suggested by Guenter Roeck and adopted by the
platform driver version of this same interface.
Documentation/ABI/testing/sysfs-bus-pci | 21
drivers/pci/pci-driver.c| 25 +--
drivers/pci/pci-sysfs.c | 40 +++
drivers/pci/probe.c |1 +
include/linux/pci.h |1 +
5 files changed, 85 insertions(+), 3 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-bus-pci
b/Documentation/ABI/testing/sysfs-bus-pci
index a3c5a66..898ddc4 100644
--- a/Documentation/ABI/testing/sysfs-bus-pci
+++ b/Documentation/ABI/testing/sysfs-bus-pci
@@ -250,3 +250,24 @@ Description:
valid. For example, writing a 2 to this file when sriov_numvfs
is not 0 and not 2 already will return an error. Writing a 10
when the value of sriov_totalvfs is 8 will return an error.
+
+What: /sys/bus/pci/devices/.../driver_override
+Date: April 2014
+Contact: Alex Williamson
+Description:
+ This file allows the driver for a device to be specified which
+ will override standard static and dynamic ID matching. When
+ specified, only a driver with a name matching the value written
+ to driver_override will have an opportunity to bind to the
+ device. The override is specified by writing a string to the
+ driver_override file (echo pci-stub > driver_override) and
+ may be cleared with an empty string (echo > driver_override).
+ This returns the device to standard matching rules binding.
+ Writing to driver_override does not automatically unbind the
+ device from its current driver or make any attempt to
+ automatically load the specified driver. If no driver with a
+ matching name is currently loaded in the kernel, the device
+ will not bind to any driver. This also allows devices to
+ opt-out of driver binding using a driver_override name such as
+ "none". Only a single driver may be specified in the override,
+ there is no support for parsing delimiters.
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index d911e0c..4393c12 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -216,6 +216,13 @@ const struct pci_device_id *pci_match_id(const struct
pci_device_id *ids,
return NULL;
}
+static const struct pci_device_id pci_device_id_any = {
+ .vendor = PCI_ANY_ID,
+ .device = PCI_ANY_ID,
+ .subvendor = PCI_ANY_ID,
+ .subdevice = PCI_ANY_ID,
+};
+
/**
* pci_match_device - Tell if a PCI device s
Re: [PATCH v2 08/12] kvm tools: Provide per arch macro to specify type for KVM_CREATE_VM
On Tue, May 20, 2014 at 12:24:58PM +0100, James Hogan wrote:
> On 19/05/14 17:53, Andreas Herrmann wrote:
> > This is is usually 0 for most archs. On mips we have two types.
> > TE (type 0) and MIPS-VZ (type 1). Default to 1 on mips.
>
> Minor thing I didn't spot with v1 (sorry).
> I think this patch should probably be moved before patch 6 with the mips
> part squashed into patch 6, otherwise AFAICT the mips support in patch
> 6/7 is broken out of the box until this patch fixes it.
Yes, you are correct, the patch sequence should be changed.
(Will have to send out a new version of the patch set. But first I am
waiting a little bit to see whether there are further comments.)
Thanks,
Andreas
> Cheers
> James
>
> >
> > Signed-off-by: Andreas Herrmann
> > ---
> > tools/kvm/arm/include/arm-common/kvm-arch.h |2 ++
> > tools/kvm/kvm.c |2 +-
> > tools/kvm/mips/include/kvm/kvm-arch.h |5 +
> > tools/kvm/powerpc/include/kvm/kvm-arch.h|2 ++
> > tools/kvm/x86/include/kvm/kvm-arch.h|2 ++
> > 5 files changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/tools/kvm/arm/include/arm-common/kvm-arch.h
> > b/tools/kvm/arm/include/arm-common/kvm-arch.h
> > index b6c4bf8..a552163 100644
> > --- a/tools/kvm/arm/include/arm-common/kvm-arch.h
> > +++ b/tools/kvm/arm/include/arm-common/kvm-arch.h
> > @@ -32,6 +32,8 @@
> >
> > #define KVM_IRQ_OFFSET GIC_SPI_IRQ_BASE
> >
> > +#define KVM_VM_TYPE0
> > +
> > #define VIRTIO_DEFAULT_TRANS(kvm) \
> > ((kvm)->cfg.arch.virtio_trans_pci ? VIRTIO_PCI : VIRTIO_MMIO)
> >
> > diff --git a/tools/kvm/kvm.c b/tools/kvm/kvm.c
> > index 6046434..e1b9f6c 100644
> > --- a/tools/kvm/kvm.c
> > +++ b/tools/kvm/kvm.c
> > @@ -284,7 +284,7 @@ int kvm__init(struct kvm *kvm)
> > goto err_sys_fd;
> > }
> >
> > - kvm->vm_fd = ioctl(kvm->sys_fd, KVM_CREATE_VM, 0);
> > + kvm->vm_fd = ioctl(kvm->sys_fd, KVM_CREATE_VM, KVM_VM_TYPE);
> > if (kvm->vm_fd < 0) {
> > pr_err("KVM_CREATE_VM ioctl");
> > ret = kvm->vm_fd;
> > diff --git a/tools/kvm/mips/include/kvm/kvm-arch.h
> > b/tools/kvm/mips/include/kvm/kvm-arch.h
> > index 4a8407b..7eadbf4 100644
> > --- a/tools/kvm/mips/include/kvm/kvm-arch.h
> > +++ b/tools/kvm/mips/include/kvm/kvm-arch.h
> > @@ -17,6 +17,11 @@
> >
> > #define KVM_IRQ_OFFSET 1
> >
> > +/*
> > + * MIPS-VZ (trap and emulate is 0)
> > + */
> > +#define KVM_VM_TYPE1
> > +
> > #define VIRTIO_DEFAULT_TRANS(kvm) VIRTIO_PCI
> >
> > #include
> > diff --git a/tools/kvm/powerpc/include/kvm/kvm-arch.h
> > b/tools/kvm/powerpc/include/kvm/kvm-arch.h
> > index f8627a2..fdd518f 100644
> > --- a/tools/kvm/powerpc/include/kvm/kvm-arch.h
> > +++ b/tools/kvm/powerpc/include/kvm/kvm-arch.h
> > @@ -44,6 +44,8 @@
> >
> > #define KVM_IRQ_OFFSET 16
> >
> > +#define KVM_VM_TYPE0
> > +
> > #define VIRTIO_DEFAULT_TRANS(kvm) VIRTIO_PCI
> >
> > struct spapr_phb;
> > diff --git a/tools/kvm/x86/include/kvm/kvm-arch.h
> > b/tools/kvm/x86/include/kvm/kvm-arch.h
> > index a9f23b8..673bdf1 100644
> > --- a/tools/kvm/x86/include/kvm/kvm-arch.h
> > +++ b/tools/kvm/x86/include/kvm/kvm-arch.h
> > @@ -27,6 +27,8 @@
> >
> > #define KVM_IRQ_OFFSET 5
> >
> > +#define KVM_VM_TYPE0
> > +
> > #define VIRTIO_DEFAULT_TRANS(kvm) VIRTIO_PCI
> >
> > struct kvm_arch {
> >
--
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[PATCH v2 1/9] arm64: KVM: rename pm_fake handler to trap_raz_wi
pm_fake doesn't quite describe what the handler does (ignoring writes
and returning 0 for reads).
As we're about to use it (a lot) in a different context, rename it
with a (admitedly cryptic) name that make sense for all users.
Reviewed-by: Anup Patel
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/sys_regs.c | 83 ---
1 file changed, 43 insertions(+), 40 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 0324458..c3d28f1 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -163,18 +163,9 @@ static bool access_sctlr(struct kvm_vcpu *vcpu,
return true;
}
-/*
- * We could trap ID_DFR0 and tell the guest we don't support performance
- * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
- * NAKed, so it will read the PMCR anyway.
- *
- * Therefore we tell the guest we have 0 counters. Unfortunately, we
- * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
- * all PM registers, which doesn't crash the guest kernel at least.
- */
-static bool pm_fake(struct kvm_vcpu *vcpu,
- const struct sys_reg_params *p,
- const struct sys_reg_desc *r)
+static bool trap_raz_wi(struct kvm_vcpu *vcpu,
+ const struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
{
if (p->is_write)
return ignore_write(vcpu, p);
@@ -201,6 +192,17 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const
struct sys_reg_desc *r)
/*
* Architected system registers.
* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
+ *
+ * We could trap ID_DFR0 and tell the guest we don't support performance
+ * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
+ * NAKed, so it will read the PMCR anyway.
+ *
+ * Therefore we tell the guest we have 0 counters. Unfortunately, we
+ * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
+ * all PM registers, which doesn't crash the guest kernel at least.
+ *
+ * Same goes for the whole debug infrastructure, which probably breaks
+ * some guest functionnality. This should be fixed.
*/
static const struct sys_reg_desc sys_reg_descs[] = {
/* DC ISW */
@@ -260,10 +262,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
/* PMINTENSET_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
- pm_fake },
+ trap_raz_wi },
/* PMINTENCLR_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
- pm_fake },
+ trap_raz_wi },
/* MAIR_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
@@ -292,43 +294,43 @@ static const struct sys_reg_desc sys_reg_descs[] = {
/* PMCR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
- pm_fake },
+ trap_raz_wi },
/* PMCNTENSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
- pm_fake },
+ trap_raz_wi },
/* PMCNTENCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
- pm_fake },
+ trap_raz_wi },
/* PMOVSCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
- pm_fake },
+ trap_raz_wi },
/* PMSWINC_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
- pm_fake },
+ trap_raz_wi },
/* PMSELR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
- pm_fake },
+ trap_raz_wi },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
- pm_fake },
+ trap_raz_wi },
/* PMCEID1_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
- pm_fake },
+ trap_raz_wi },
/* PMCCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
- pm_fake },
+ trap_raz_wi },
/* PMXEVTYPER_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
- pm_fake },
+ trap_raz_wi },
/* PMXEVCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
- pm_fake },
+ trap_raz_wi },
/* PMUSERENR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
- pm_fake },
+ trap_raz_wi },
/* PMOVSSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
- pm_fake },
+ trap_raz_wi },
/* TPIDR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b010),
@@ -374,19 +376,20 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
{ Op1( 0), CRn( 7), CRm(14), Op2( 2), access_d
[PATCH v2 6/9] arm64: KVM: check ordering of all system register tables
We now have multiple tables for the various system registers
we trap. Make sure we check the order of all of them, as it is
critical that we get the order right (been there, done that...).
Reviewed-by: Anup Patel
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/sys_regs.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index e4a2113..98d60d1 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1280,14 +1280,32 @@ int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu,
u64 __user *uindices)
return write_demux_regids(uindices);
}
+static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
+{
+ unsigned int i;
+
+ for (i = 1; i < n; i++) {
+ if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
+ kvm_err("sys_reg table %p out of order (%d)\n", table,
i - 1);
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
void kvm_sys_reg_table_init(void)
{
unsigned int i;
struct sys_reg_desc clidr;
/* Make sure tables are unique and in order. */
- for (i = 1; i < ARRAY_SIZE(sys_reg_descs); i++)
- BUG_ON(cmp_sys_reg(&sys_reg_descs[i-1], &sys_reg_descs[i]) >=
0);
+ BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
+ BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
+ BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
+ BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
+ BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
+ BUG_ON(check_sysreg_table(invariant_sys_regs,
ARRAY_SIZE(invariant_sys_regs)));
/* We abuse the reset function to overwrite the table itself. */
for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
--
1.8.3.4
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[PATCH v2 3/9] arm64: KVM: add trap handlers for AArch64 debug registers
Add handlers for all the AArch64 debug registers that are accessible
from EL0 or EL1. The trapping code keeps track of the state of the
debug registers, allowing for the switch code to implement a lazy
switching strategy.
Reviewed-by: Anup Patel
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_asm.h | 28 ++--
arch/arm64/include/asm/kvm_host.h | 3 +
arch/arm64/kvm/sys_regs.c | 130 +-
3 files changed, 151 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index 9fcd54b..e6b159a 100644
--- a/arch/arm64/include/asm/kvm_asm.h
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -43,14 +43,25 @@
#defineAMAIR_EL1 19 /* Aux Memory Attribute Indirection
Register */
#defineCNTKCTL_EL1 20 /* Timer Control Register (EL1) */
#definePAR_EL1 21 /* Physical Address Register */
+#define MDSCR_EL1 22 /* Monitor Debug System Control Register */
+#define DBGBCR0_EL123 /* Debug Breakpoint Control Registers (0-15) */
+#define DBGBCR15_EL1 38
+#define DBGBVR0_EL139 /* Debug Breakpoint Value Registers (0-15) */
+#define DBGBVR15_EL1 54
+#define DBGWCR0_EL155 /* Debug Watchpoint Control Registers (0-15) */
+#define DBGWCR15_EL1 70
+#define DBGWVR0_EL171 /* Debug Watchpoint Value Registers (0-15) */
+#define DBGWVR15_EL1 86
+#define MDCCINT_EL187 /* Monitor Debug Comms Channel Interrupt Enable
Reg */
+
/* 32bit specific registers. Keep them at the end of the range */
-#defineDACR32_EL2 22 /* Domain Access Control Register */
-#defineIFSR32_EL2 23 /* Instruction Fault Status Register */
-#defineFPEXC32_EL2 24 /* Floating-Point Exception Control
Register */
-#defineDBGVCR32_EL225 /* Debug Vector Catch Register */
-#defineTEECR32_EL1 26 /* ThumbEE Configuration Register */
-#defineTEEHBR32_EL127 /* ThumbEE Handler Base Register */
-#defineNR_SYS_REGS 28
+#defineDACR32_EL2 88 /* Domain Access Control Register */
+#defineIFSR32_EL2 89 /* Instruction Fault Status Register */
+#defineFPEXC32_EL2 90 /* Floating-Point Exception Control
Register */
+#defineDBGVCR32_EL291 /* Debug Vector Catch Register */
+#defineTEECR32_EL1 92 /* ThumbEE Configuration Register */
+#defineTEEHBR32_EL193 /* ThumbEE Handler Base Register */
+#defineNR_SYS_REGS 94
/* 32bit mapping */
#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
@@ -87,6 +98,9 @@
#define ARM_EXCEPTION_IRQ0
#define ARM_EXCEPTION_TRAP 1
+#define KVM_ARM64_DEBUG_DIRTY_SHIFT0
+#define KVM_ARM64_DEBUG_DIRTY (1 << KVM_ARM64_DEBUG_DIRTY_SHIFT)
+
#ifndef __ASSEMBLY__
struct kvm;
struct kvm_vcpu;
diff --git a/arch/arm64/include/asm/kvm_host.h
b/arch/arm64/include/asm/kvm_host.h
index 0a1d697..4737961 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -101,6 +101,9 @@ struct kvm_vcpu_arch {
/* Exception Information */
struct kvm_vcpu_fault_info fault;
+ /* Debug state */
+ u64 debug_flags;
+
/* Pointer to host CPU context */
kvm_cpu_context_t *host_cpu_context;
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c3d28f1..d46a965 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include
#include "sys_regs.h"
@@ -173,6 +174,58 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu,
return read_zero(vcpu, p);
}
+static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
+ const struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ if (p->is_write) {
+ return ignore_write(vcpu, p);
+ } else {
+ *vcpu_reg(vcpu, p->Rt) = (1 << 3);
+ return true;
+ }
+}
+
+static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
+ const struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ if (p->is_write) {
+ return ignore_write(vcpu, p);
+ } else {
+ *vcpu_reg(vcpu, p->Rt) = 0x; /* Implemented and disabled */
+ return true;
+ }
+}
+
+/*
+ * Trap handler for DBG[BW][CV]Rn_EL1 and MDSCR_EL1. We track the
+ * "dirtiness" of the registers.
+ */
+static bool trap_debug_regs(struct kvm_vcpu *vcpu,
+ const struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ /*
+* The best thing to do would be to trap MDSCR_EL1
+* independently, test if DBG_MDSCR_KDE or DBG_MDSCR_MD
[PATCH v2 9/9] arm64: KVM: enable trapping of all debug registers
Enable trapping of the debug registers, preventing the guests to mess with the host state (and allowing guests to use the debug infrastructure as well). Reviewed-by: Anup Patel Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp.S | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S index 73ec5c4..72ed0bf8 100644 --- a/arch/arm64/kvm/hyp.S +++ b/arch/arm64/kvm/hyp.S @@ -777,6 +777,14 @@ __kvm_hyp_code_start: mrs x2, mdcr_el2 and x2, x2, #MDCR_EL2_HPMN_MASK orr x2, x2, #(MDCR_EL2_TPM | MDCR_EL2_TPMCR) + orr x2, x2, #(MDCR_EL2_TDRA | MDCR_EL2_TDOSA) + + // Check for KVM_ARM64_DEBUG_DIRTY, and set to debug to trap + // if not dirty. + ldr x3, [x0, #VCPU_DEBUG_FLAGS] + tbnzx3, #KVM_ARM64_DEBUG_DIRTY_SHIFT, 1f + orr x2, x2, #MDCR_EL2_TDA +1: msr mdcr_el2, x2 .endm -- 1.8.3.4 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 2/9] arm64: move DBG_MDSCR_* to asm/debug-monitors.h
In order to be able to use the DBG_MDSCR_* macros from the KVM code,
move the relevant definitions to the obvious include file.
Also move the debug_el enum to a portion of the file that is guarded
by #ifndef __ASSEMBLY__ in order to use that file from assembly code.
Acked-by: Will Deacon
Reviewed-by: Anup Patel
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/debug-monitors.h | 19 ++-
arch/arm64/kernel/debug-monitors.c | 9 -
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/include/asm/debug-monitors.h
b/arch/arm64/include/asm/debug-monitors.h
index 6e9b5b3..7fb3437 100644
--- a/arch/arm64/include/asm/debug-monitors.h
+++ b/arch/arm64/include/asm/debug-monitors.h
@@ -18,6 +18,15 @@
#ifdef __KERNEL__
+/* Low-level stepping controls. */
+#define DBG_MDSCR_SS (1 << 0)
+#define DBG_SPSR_SS(1 << 21)
+
+/* MDSCR_EL1 enabling bits */
+#define DBG_MDSCR_KDE (1 << 13)
+#define DBG_MDSCR_MDE (1 << 15)
+#define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE)
+
#defineDBG_ESR_EVT(x) (((x) >> 27) & 0x7)
/* AArch64 */
@@ -73,11 +82,6 @@
#define CACHE_FLUSH_IS_SAFE1
-enum debug_el {
- DBG_ACTIVE_EL0 = 0,
- DBG_ACTIVE_EL1,
-};
-
/* AArch32 */
#define DBG_ESR_EVT_BKPT 0x4
#define DBG_ESR_EVT_VECC 0x5
@@ -115,6 +119,11 @@ void unregister_break_hook(struct break_hook *hook);
u8 debug_monitors_arch(void);
+enum debug_el {
+ DBG_ACTIVE_EL0 = 0,
+ DBG_ACTIVE_EL1,
+};
+
void enable_debug_monitors(enum debug_el el);
void disable_debug_monitors(enum debug_el el);
diff --git a/arch/arm64/kernel/debug-monitors.c
b/arch/arm64/kernel/debug-monitors.c
index a7fb874..e022f87 100644
--- a/arch/arm64/kernel/debug-monitors.c
+++ b/arch/arm64/kernel/debug-monitors.c
@@ -30,15 +30,6 @@
#include
#include
-/* Low-level stepping controls. */
-#define DBG_MDSCR_SS (1 << 0)
-#define DBG_SPSR_SS(1 << 21)
-
-/* MDSCR_EL1 enabling bits */
-#define DBG_MDSCR_KDE (1 << 13)
-#define DBG_MDSCR_MDE (1 << 15)
-#define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE)
-
/* Determine debug architecture. */
u8 debug_monitors_arch(void)
{
--
1.8.3.4
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[PATCH v2 8/9] arm64: KVM: implement lazy world switch for debug registers
Implement switching of the debug registers. While the number of registers is massive, CPUs usually don't implement them all (A57 has 6 breakpoints and 4 watchpoints, which gives us a total of 22 registers "only"). Also, we only save/restore them when MDSCR_EL1 has debug enabled, or when we've flagged the debug registers as dirty. It means that most of the time, we only save/restore MDSCR_EL1. Reviewed-by: Anup Patel Signed-off-by: Marc Zyngier --- arch/arm64/kernel/asm-offsets.c | 1 + arch/arm64/kvm/hyp.S| 462 +++- 2 files changed, 457 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c index 646f888..ae73a83 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -120,6 +120,7 @@ int main(void) DEFINE(VCPU_ESR_EL2, offsetof(struct kvm_vcpu, arch.fault.esr_el2)); DEFINE(VCPU_FAR_EL2, offsetof(struct kvm_vcpu, arch.fault.far_el2)); DEFINE(VCPU_HPFAR_EL2, offsetof(struct kvm_vcpu, arch.fault.hpfar_el2)); + DEFINE(VCPU_DEBUG_FLAGS, offsetof(struct kvm_vcpu, arch.debug_flags)); DEFINE(VCPU_HCR_EL2, offsetof(struct kvm_vcpu, arch.hcr_el2)); DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines)); DEFINE(VCPU_HOST_CONTEXT,offsetof(struct kvm_vcpu, arch.host_cpu_context)); diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S index 2c56012..73ec5c4 100644 --- a/arch/arm64/kvm/hyp.S +++ b/arch/arm64/kvm/hyp.S @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -215,6 +216,7 @@ __kvm_hyp_code_start: mrs x22,amair_el1 mrs x23,cntkctl_el1 mrs x24,par_el1 + mrs x25,mdscr_el1 stp x4, x5, [x3] stp x6, x7, [x3, #16] @@ -226,7 +228,202 @@ __kvm_hyp_code_start: stp x18, x19, [x3, #112] stp x20, x21, [x3, #128] stp x22, x23, [x3, #144] - str x24, [x3, #160] + stp x24, x25, [x3, #160] +.endm + +.macro save_debug + // x2: base address for cpu context + // x3: tmp register + + mrs x26, id_aa64dfr0_el1 + ubfxx24, x26, #12, #4 // Extract BRPs + ubfxx25, x26, #20, #4 // Extract WRPs + mov w26, #15 + sub w24, w26, w24 // How many BPs to skip + sub w25, w26, w25 // How many WPs to skip + + add x3, x2, #CPU_SYSREG_OFFSET(DBGBCR0_EL1) + + adr x26, 1f + add x26, x26, x24, lsl #2 + br x26 +1: + mrs x20, dbgbcr15_el1 + mrs x19, dbgbcr14_el1 + mrs x18, dbgbcr13_el1 + mrs x17, dbgbcr12_el1 + mrs x16, dbgbcr11_el1 + mrs x15, dbgbcr10_el1 + mrs x14, dbgbcr9_el1 + mrs x13, dbgbcr8_el1 + mrs x12, dbgbcr7_el1 + mrs x11, dbgbcr6_el1 + mrs x10, dbgbcr5_el1 + mrs x9, dbgbcr4_el1 + mrs x8, dbgbcr3_el1 + mrs x7, dbgbcr2_el1 + mrs x6, dbgbcr1_el1 + mrs x5, dbgbcr0_el1 + + adr x26, 1f + add x26, x26, x24, lsl #2 + br x26 + +1: + str x20, [x3, #(15 * 8)] + str x19, [x3, #(14 * 8)] + str x18, [x3, #(13 * 8)] + str x17, [x3, #(12 * 8)] + str x16, [x3, #(11 * 8)] + str x15, [x3, #(10 * 8)] + str x14, [x3, #(9 * 8)] + str x13, [x3, #(8 * 8)] + str x12, [x3, #(7 * 8)] + str x11, [x3, #(6 * 8)] + str x10, [x3, #(5 * 8)] + str x9, [x3, #(4 * 8)] + str x8, [x3, #(3 * 8)] + str x7, [x3, #(2 * 8)] + str x6, [x3, #(1 * 8)] + str x5, [x3, #(0 * 8)] + + add x3, x2, #CPU_SYSREG_OFFSET(DBGBVR0_EL1) + + adr x26, 1f + add x26, x26, x24, lsl #2 + br x26 +1: + mrs x20, dbgbvr15_el1 + mrs x19, dbgbvr14_el1 + mrs x18, dbgbvr13_el1 + mrs x17, dbgbvr12_el1 + mrs x16, dbgbvr11_el1 + mrs x15, dbgbvr10_el1 + mrs x14, dbgbvr9_el1 + mrs x13, dbgbvr8_el1 + mrs x12, dbgbvr7_el1 + mrs x11, dbgbvr6_el1 + mrs x10, dbgbvr5_el1 + mrs x9, dbgbvr4_el1 + mrs x8, dbgbvr3_el1 + mrs x7, dbgbvr2_el1 + mrs x6, dbgbvr1_el1 + mrs x5, dbgbvr0_el1 + + adr x26, 1f + add x26, x26, x24, lsl #2 + br x26 + +1: + str x20, [x3, #(15 * 8)] + str x19, [x3, #(14 * 8)] + str x18, [x3, #(13 * 8)] + str x17, [x3, #(12 * 8)] + str x16, [x3, #(11 * 8)] + str x15, [x3, #(10 * 8)] + str x14, [x3, #(9 * 8)] + str x13, [x3, #(8 * 8)] + str x12, [x3, #(7 * 8)] + str x11, [x3, #(6 * 8)] + str
[PATCH v2 0/9] arm64: KVM: debug infrastructure support
This patch series adds debug support, a key feature missing from the KVM/arm64 port. The main idea is to keep track of whether the debug registers are "dirty" (changed by the guest) or not. In this case, perform the usual save/restore dance, for one run only. It means we only have a penalty if a guest is actively using the debug registers. The amount of registers is properly frightening, but CPUs actually only implement a subset of them. Also, there is a number of registers we don't bother emulating (things having to do with external debug and OSlock). This has been tested on a Cortex-A53/A57 platform, running both 32 and 64bit guests, on top of 3.15-rc4. This code also lives in my tree in the kvm-arm64/debug-trap branch. >From v1 [1]: - Renamed trap_wi_raz to trap_raz_wi - Renamed skip_clean_debug_state to skip_debug_state - Simplified debug state computing, moved to its own macro - Added some comment to make the logic more obvious [1]: https://lists.cs.columbia.edu/pipermail/kvmarm/2014-May/009332.html Marc Zyngier (9): arm64: KVM: rename pm_fake handler to trap_raz_wi arm64: move DBG_MDSCR_* to asm/debug-monitors.h arm64: KVM: add trap handlers for AArch64 debug registers arm64: KVM: common infrastructure for handling AArch32 CP14/CP15 arm64: KVM: use separate tables for AArch32 32 and 64bit traps arm64: KVM: check ordering of all system register tables arm64: KVM: add trap handlers for AArch32 debug registers arm64: KVM: implement lazy world switch for debug registers arm64: KVM: enable trapping of all debug registers arch/arm64/include/asm/debug-monitors.h | 19 +- arch/arm64/include/asm/kvm_asm.h| 39 ++- arch/arm64/include/asm/kvm_coproc.h | 3 +- arch/arm64/include/asm/kvm_host.h | 12 +- arch/arm64/kernel/asm-offsets.c | 1 + arch/arm64/kernel/debug-monitors.c | 9 - arch/arm64/kvm/handle_exit.c| 4 +- arch/arm64/kvm/hyp.S| 470 +- arch/arm64/kvm/sys_regs.c | 494 +++- 9 files changed, 953 insertions(+), 98 deletions(-) -- 1.8.3.4 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 4/9] arm64: KVM: common infrastructure for handling AArch32 CP14/CP15
As we're about to trap a bunch of CP14 registers, let's rework
the CP15 handling so it can be generalized and work with multiple
tables.
Reviewed-by: Anup Patel
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_asm.h| 2 +-
arch/arm64/include/asm/kvm_coproc.h | 3 +-
arch/arm64/include/asm/kvm_host.h | 9 ++-
arch/arm64/kvm/handle_exit.c| 4 +-
arch/arm64/kvm/sys_regs.c | 121 +---
5 files changed, 111 insertions(+), 28 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index e6b159a..12f9dd7 100644
--- a/arch/arm64/include/asm/kvm_asm.h
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -93,7 +93,7 @@
#define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
#define c14_CNTKCTL(CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
-#define NR_CP15_REGS (NR_SYS_REGS * 2)
+#define NR_COPRO_REGS (NR_SYS_REGS * 2)
#define ARM_EXCEPTION_IRQ0
#define ARM_EXCEPTION_TRAP 1
diff --git a/arch/arm64/include/asm/kvm_coproc.h
b/arch/arm64/include/asm/kvm_coproc.h
index 9a59301..0b52377 100644
--- a/arch/arm64/include/asm/kvm_coproc.h
+++ b/arch/arm64/include/asm/kvm_coproc.h
@@ -39,7 +39,8 @@ void kvm_register_target_sys_reg_table(unsigned int target,
struct kvm_sys_reg_target_table *table);
int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run);
-int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run);
int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run);
diff --git a/arch/arm64/include/asm/kvm_host.h
b/arch/arm64/include/asm/kvm_host.h
index 4737961..31cff7a 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -86,7 +86,7 @@ struct kvm_cpu_context {
struct kvm_regs gp_regs;
union {
u64 sys_regs[NR_SYS_REGS];
- u32 cp15[NR_CP15_REGS];
+ u32 copro[NR_COPRO_REGS];
};
};
@@ -141,7 +141,12 @@ struct kvm_vcpu_arch {
#define vcpu_gp_regs(v)(&(v)->arch.ctxt.gp_regs)
#define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
-#define vcpu_cp15(v,r) ((v)->arch.ctxt.cp15[(r)])
+/*
+ * CP14 and CP15 live in the same array, as they are backed by the
+ * same system registers.
+ */
+#define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)])
+#define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)])
struct kvm_vm_stat {
u32 remote_tlb_flush;
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index 7bc41ea..f0ca49f 100644
--- a/arch/arm64/kvm/handle_exit.c
+++ b/arch/arm64/kvm/handle_exit.c
@@ -69,9 +69,9 @@ static exit_handle_fn arm_exit_handlers[] = {
[ESR_EL2_EC_WFI]= kvm_handle_wfx,
[ESR_EL2_EC_CP15_32]= kvm_handle_cp15_32,
[ESR_EL2_EC_CP15_64]= kvm_handle_cp15_64,
- [ESR_EL2_EC_CP14_MR]= kvm_handle_cp14_access,
+ [ESR_EL2_EC_CP14_MR]= kvm_handle_cp14_32,
[ESR_EL2_EC_CP14_LS]= kvm_handle_cp14_load_store,
- [ESR_EL2_EC_CP14_64]= kvm_handle_cp14_access,
+ [ESR_EL2_EC_CP14_64]= kvm_handle_cp14_64,
[ESR_EL2_EC_HVC32] = handle_hvc,
[ESR_EL2_EC_SMC32] = handle_smc,
[ESR_EL2_EC_HVC64] = handle_hvc,
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index d46a965..429e38c 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -474,6 +474,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
NULL, reset_val, FPEXC32_EL2, 0x70 },
};
+/* Trapped cp14 registers */
+static const struct sys_reg_desc cp14_regs[] = {
+};
+
/*
* Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
* depending on the way they are accessed (as a 32bit or a 64bit
@@ -581,26 +585,19 @@ int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu,
struct kvm_run *run)
return 1;
}
-int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- kvm_inject_undefined(vcpu);
- return 1;
-}
-
-static void emulate_cp15(struct kvm_vcpu *vcpu,
-const struct sys_reg_params *params)
+static int emulate_cp(struct kvm_vcpu *vcpu,
+ const struct sys_reg_params *params,
+ const struct sys_reg_desc *table,
+ size_t num)
{
- size_t num;
- const struct sys_reg_desc *table, *r;
+ const struct sys_reg_desc *r;
- table = get_target_table(vcpu->arch.target, false, &num);
+ if (!table)
+
[PATCH v2 7/9] arm64: KVM: add trap handlers for AArch32 debug registers
Add handlers for all the AArch32 debug registers that are accessible
from EL0 or EL1. The code follow the same strategy as the AArch64
counterpart with regards to tracking the dirty state of the debug
registers.
Reviewed-by: Anup Patel
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/kvm_asm.h | 9 +++
arch/arm64/kvm/sys_regs.c| 137 ++-
2 files changed, 145 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index 12f9dd7..993a7db 100644
--- a/arch/arm64/include/asm/kvm_asm.h
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -93,6 +93,15 @@
#define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
#define c14_CNTKCTL(CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
+
+#define cp14_DBGDSCRext(MDSCR_EL1 * 2)
+#define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
+#define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
+#define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
+#define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
+#define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
+#define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
+
#define NR_COPRO_REGS (NR_SYS_REGS * 2)
#define ARM_EXCEPTION_IRQ0
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 98d60d1..5960d5b 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -474,12 +474,148 @@ static const struct sys_reg_desc sys_reg_descs[] = {
NULL, reset_val, FPEXC32_EL2, 0x70 },
};
+static bool trap_dbgidr(struct kvm_vcpu *vcpu,
+ const struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ if (p->is_write) {
+ return ignore_write(vcpu, p);
+ } else {
+ u64 dfr = read_cpuid(ID_AA64DFR0_EL1);
+ u64 pfr = read_cpuid(ID_AA64PFR0_EL1);
+ u32 el3 = !!((pfr >> 12) & 0xf);
+
+ *vcpu_reg(vcpu, p->Rt) = dfr >> 20) & 0xf) << 28) |
+ (((dfr >> 12) & 0xf) << 24) |
+ (((dfr >> 28) & 0xf) << 20) |
+ (6 << 16) | (el3 << 14) | (el3 <<
12));
+ return true;
+ }
+}
+
+static bool trap_debug32(struct kvm_vcpu *vcpu,
+const struct sys_reg_params *p,
+const struct sys_reg_desc *r)
+{
+ if (p->is_write) {
+ vcpu_cp14(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
+ vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
+ } else {
+ *vcpu_reg(vcpu, p->Rt) = vcpu_cp14(vcpu, r->reg);
+ }
+
+ return true;
+}
+
+#define DBG_BCR_BVR_WCR_WVR(n) \
+ /* DBGBCRn */ \
+ { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_debug32,\
+ NULL, (cp14_DBGBCR0 + (n) * 2) }, \
+ /* DBGBVRn */ \
+ { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_debug32,\
+ NULL, (cp14_DBGBVR0 + (n) * 2) }, \
+ /* DBGWVRn */ \
+ { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_debug32,\
+ NULL, (cp14_DBGWVR0 + (n) * 2) }, \
+ /* DBGWCRn */ \
+ { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_debug32,\
+ NULL, (cp14_DBGWCR0 + (n) * 2) }
+
+#define DBGBXVR(n) \
+ { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_debug32,\
+ NULL, cp14_DBGBXVR0 + n * 2 }
+
/* Trapped cp14 registers */
static const struct sys_reg_desc cp14_regs[] = {
+ /* DBGIDR */
+ { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
+ /* DBGDTRRXext */
+ { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
+
+ DBG_BCR_BVR_WCR_WVR(0),
+ /* DBGDSCRint */
+ { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
+ DBG_BCR_BVR_WCR_WVR(1),
+ /* DBGDCCINT */
+ { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
+ /* DBGDSCRext */
+ { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
+ DBG_BCR_BVR_WCR_WVR(2),
+ /* DBGDTRTXext */
+ { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
+ DBG_BCR_BVR_WCR_WVR(3),
+ DBG_BCR_BVR_WCR_WVR(4),
+ DBG_BCR_BVR_WCR_WVR(5),
+ /* DBGWFAR */
+ { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
+ /* DBGOSECCR */
+ { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
+ DBG_BCR_BVR_WCR_WVR(6),
+ /* DBGVCR */
+ { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
+ DBG_BCR_BVR_WCR_WVR(7),
+ DBG_BCR_BVR_WCR_WVR(8),
+ DBG_BCR_BVR_WCR_WVR(9),
+ DBG_BCR_BVR_WCR_WVR(10),
+ DBG_BCR_BVR_WCR_W
[PATCH v2 5/9] arm64: KVM: use separate tables for AArch32 32 and 64bit traps
An interesting "feature" of the CP14 encoding is that there is
an overlap between 32 and 64bit registers, meaning they cannot
live in the same table as we did for CP15.
Create separate tables for 64bit CP14 and CP15 registers, and
let the top level handler use the right one.
Reviewed-by: Anup Patel
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/sys_regs.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 429e38c..e4a2113 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -478,13 +478,16 @@ static const struct sys_reg_desc sys_reg_descs[] = {
static const struct sys_reg_desc cp14_regs[] = {
};
+/* Trapped cp14 64bit registers */
+static const struct sys_reg_desc cp14_64_regs[] = {
+};
+
/*
* Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
* depending on the way they are accessed (as a 32bit or a 64bit
* register).
*/
static const struct sys_reg_desc cp15_regs[] = {
- { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
{ Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_sctlr, NULL, c1_SCTLR },
{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
{ Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
@@ -525,6 +528,10 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
+};
+
+static const struct sys_reg_desc cp15_64_regs[] = {
+ { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
{ Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
};
@@ -740,7 +747,7 @@ int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct
kvm_run *run)
target_specific = get_target_table(vcpu->arch.target, false, &num);
return kvm_handle_cp_64(vcpu,
- cp15_regs, ARRAY_SIZE(cp15_regs),
+ cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
target_specific, num);
}
@@ -758,7 +765,7 @@ int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct
kvm_run *run)
int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
{
return kvm_handle_cp_64(vcpu,
- cp14_regs, ARRAY_SIZE(cp14_regs),
+ cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
NULL, 0);
}
--
1.8.3.4
--
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the body of a message to majord...@vger.kernel.org
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[PATCH] arm64: KVM: Enable minimalistic support for Cortex-A53
In order to allow KVM to run on Cortex-A53 implementations, wire the
minimal support required.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/cputype.h | 1 +
arch/arm64/include/uapi/asm/kvm.h| 3 ++-
arch/arm64/kvm/guest.c | 2 ++
arch/arm64/kvm/sys_regs_generic_v8.c | 2 ++
4 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index c404fb0..27f54a7 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -41,6 +41,7 @@
#define ARM_CPU_PART_AEM_V80xD0F0
#define ARM_CPU_PART_FOUNDATION0xD000
+#define ARM_CPU_PART_CORTEX_A530xD030
#define ARM_CPU_PART_CORTEX_A570xD070
#define APM_CPU_PART_POTENZA 0x
diff --git a/arch/arm64/include/uapi/asm/kvm.h
b/arch/arm64/include/uapi/asm/kvm.h
index eaf54a3..6396eda 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -56,8 +56,9 @@ struct kvm_regs {
#define KVM_ARM_TARGET_FOUNDATION_V8 1
#define KVM_ARM_TARGET_CORTEX_A57 2
#define KVM_ARM_TARGET_XGENE_POTENZA 3
+#define KVM_ARM_TARGET_CORTEX_A53 4
-#define KVM_ARM_NUM_TARGETS4
+#define KVM_ARM_NUM_TARGETS5
/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
#define KVM_ARM_DEVICE_TYPE_SHIFT 0
diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
index 0874557..60b5c31 100644
--- a/arch/arm64/kvm/guest.c
+++ b/arch/arm64/kvm/guest.c
@@ -214,6 +214,8 @@ int __attribute_const__ kvm_target_cpu(void)
return KVM_ARM_TARGET_AEM_V8;
case ARM_CPU_PART_FOUNDATION:
return KVM_ARM_TARGET_FOUNDATION_V8;
+ case ARM_CPU_PART_CORTEX_A53:
+ return KVM_ARM_TARGET_CORTEX_A53;
case ARM_CPU_PART_CORTEX_A57:
return KVM_ARM_TARGET_CORTEX_A57;
};
diff --git a/arch/arm64/kvm/sys_regs_generic_v8.c
b/arch/arm64/kvm/sys_regs_generic_v8.c
index 8fe6f76..475fd29 100644
--- a/arch/arm64/kvm/sys_regs_generic_v8.c
+++ b/arch/arm64/kvm/sys_regs_generic_v8.c
@@ -88,6 +88,8 @@ static int __init sys_reg_genericv8_init(void)
&genericv8_target_table);
kvm_register_target_sys_reg_table(KVM_ARM_TARGET_FOUNDATION_V8,
&genericv8_target_table);
+ kvm_register_target_sys_reg_table(KVM_ARM_TARGET_CORTEX_A53,
+ &genericv8_target_table);
kvm_register_target_sys_reg_table(KVM_ARM_TARGET_CORTEX_A57,
&genericv8_target_table);
kvm_register_target_sys_reg_table(KVM_ARM_TARGET_XGENE_POTENZA,
--
1.8.3.4
--
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Re: [PATCH v2 00/12] kvm tools: Misc patches (mips support)
On 05/20/2014 02:20 PM, James Hogan wrote: I don't know what Pekka's policy is for kvm tools, but to avoid confusion I'd like to make clear that this patchset depends on a KVM implementation (KVM_VM_TYPE==1 for VZ) which hasn't been accepted into the mainline kernel yet. Is that something that is likely to end up in mainline Linux in one form or another? If yes, we can merge early like we did with arm64. - Pekka -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Bug 65561] KVM:Entry failed on Single stepping sti instruction
https://bugzilla.kernel.org/show_bug.cgi?id=65561 --- Comment #4 from Jidong Xiao --- Jatin, are you using gdb to do the single step?(In reply to Jatin Kumar from comment #2) -- You are receiving this mail because: You are watching the assignee of the bug. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Bug 30402] Debian 4 fails to boot in KVM
https://bugzilla.kernel.org/show_bug.cgi?id=30402 Jidong Xiao changed: What|Removed |Added CC||jidong.x...@gmail.com --- Comment #2 from Jidong Xiao --- Joerg, how do you know this? "Some investigation showed that this kernel uses MMX instructions to access MMIO regions. These instructions are not emulated by the instruction emulator and need to be added there." -- You are receiving this mail because: You are watching the assignee of the bug. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Bug 30402] Debian 4 fails to boot in KVM
https://bugzilla.kernel.org/show_bug.cgi?id=30402 --- Comment #3 from Joerg Roedel --- (In reply to Jidong Xiao from comment #2) > Joerg, how do you know this? > > "Some investigation showed that this kernel uses MMX instructions to access > MMIO regions. These instructions are not emulated by the instruction > emulator and need to be added there." AFAIR the stack-trace and instruction pointer of the crashing kernel pointed to an MMX instruction and the kernel was trying to access an MMIO region. -- You are receiving this mail because: You are watching the assignee of the bug. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH uq/master] kvm_stat: add option to display non tracepoint based stats
The old stats contain information not available in the tracepoints.
Signed-off-by: Marcelo Tosatti
diff --git a/scripts/kvm/kvm_stat b/scripts/kvm/kvm_stat
index 762544b..6ac3b21 100755
--- a/scripts/kvm/kvm_stat
+++ b/scripts/kvm/kvm_stat
@@ -493,12 +493,21 @@ options.add_option('-f', '--fields',
dest = 'fields',
help = 'fields to display (regex)',
)
+options.add_option('-o', '--old',
+ action = 'store_true',
+ default = False,
+ dest = 'old',
+ help = 'show kvm statistics counters (not tracepoint
based)',
+ )
(options, args) = options.parse_args(sys.argv)
-try:
-provider = TracepointProvider()
-except:
+if options.old:
provider = DebugfsProvider()
+else:
+try:
+provider = TracepointProvider()
+except:
+provider = DebugfsProvider()
stats = Stats(provider, fields = options.fields)
--
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Re: [PATCH v2 00/12] kvm tools: Misc patches (mips support)
On 20/05/14 18:52, Pekka Enberg wrote: > On 05/20/2014 02:20 PM, James Hogan wrote: >> I don't know what Pekka's policy is for kvm tools, but to avoid >> confusion I'd like to make clear that this patchset depends on a KVM >> implementation (KVM_VM_TYPE==1 for VZ) which hasn't been accepted into >> the mainline kernel yet. > > Is that something that is likely to end up in mainline Linux in one form > or another? If yes, we can merge early like we did with arm64. Very likely yes, and most of the specifics of the MIPS KVM API have already been pinned down for the trap & emulate KVM support which is in mainline. Cheers James -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/15] MIPS: OCTEON: Move CAVIUM_OCTEON_CVMSEG_SIZE to CPU_CAVIUM_OCTEON
Hi Andreas, On Tuesday 20 May 2014 16:47:04 Andreas Herrmann wrote: > From: David Daney > > CVMSEG is related to the CPU core not the SoC system. So needs to be > configurable there. > > Signed-off-by: David Daney > Signed-off-by: Andreas Herrmann > --- > arch/mips/cavium-octeon/Kconfig | 30 -- > 1 file changed, 20 insertions(+), 10 deletions(-) > > diff --git a/arch/mips/cavium-octeon/Kconfig > b/arch/mips/cavium-octeon/Kconfig index 227705d..c5e9975 100644 > --- a/arch/mips/cavium-octeon/Kconfig > +++ b/arch/mips/cavium-octeon/Kconfig > @@ -10,6 +10,17 @@ config CAVIUM_CN63XXP1 > non-CN63XXP1 hardware, so it is recommended to select "n" > unless it is known the workarounds are needed. > > +config CAVIUM_OCTEON_CVMSEG_SIZE > + int "Number of L1 cache lines reserved for CVMSEG memory" > + range 0 54 > + default 1 > + help > + CVMSEG LM is a segment that accesses portions of the dcache as a > + local memory; the larger CVMSEG is, the smaller the cache is. > + This selects the size of CVMSEG LM, which is in cache blocks. The > + legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is > + between zero and 6192 bytes). > + > endif # CPU_CAVIUM_OCTEON > > if CAVIUM_OCTEON_SOC > @@ -23,16 +34,16 @@ config CAVIUM_OCTEON_2ND_KERNEL > with this option to be run at the same time as one built without this > option. > > -config CAVIUM_OCTEON_CVMSEG_SIZE > - int "Number of L1 cache lines reserved for CVMSEG memory" > - range 0 54 > - default 1 > +config CAVIUM_OCTEON_HW_FIX_UNALIGNED > + bool "Enable hardware fixups of unaligned loads and stores" > + default "y" Is adding CAVIUM_OCTEON_HW_FIX_UNALIGNED in this patch intentional? It seems unrelated. Cheers James > help > - CVMSEG LM is a segment that accesses portions of the dcache as a > - local memory; the larger CVMSEG is, the smaller the cache is. > - This selects the size of CVMSEG LM, which is in cache blocks. The > - legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is > - between zero and 6192 bytes). > + Configure the Octeon hardware to automatically fix unaligned loads > + and stores. Normally unaligned accesses are fixed using a kernel > + exception handler. This option enables the hardware automatic fixups, > + which requires only an extra 3 cycles. Disable this option if you > + are running code that relies on address exceptions on unaligned > + accesses. > > config CAVIUM_OCTEON_LOCK_L2 > bool "Lock often used kernel code in the L2" > @@ -86,7 +97,6 @@ config SWIOTLB > select IOMMU_HELPER > select NEED_SG_DMA_LENGTH > > - > config OCTEON_ILM > tristate "Module to measure interrupt latency using Octeon CIU Timer" > help signature.asc Description: This is a digitally signed message part.
Re: [PATCH 13/15] MIPS: Add defconfig for mips_paravirt
Hi Andreas, On Tuesday 20 May 2014 16:47:14 Andreas Herrmann wrote: > From: David Daney > > Signed-off-by: David Daney > Signed-off-by: Andreas Herrmann > --- > arch/mips/configs/mips_paravirt_defconfig | 1524 > + 1 file changed, 1524 insertions(+) > create mode 100644 arch/mips/configs/mips_paravirt_defconfig > > diff --git a/arch/mips/configs/mips_paravirt_defconfig > b/arch/mips/configs/mips_paravirt_defconfig new file mode 100644 > index 000..f0cac9c > --- /dev/null > +++ b/arch/mips/configs/mips_paravirt_defconfig > @@ -0,0 +1,1524 @@ > +# > +# Automatically generated file; DO NOT EDIT. > +# Linux/mips 3.15.0-rc4 Kernel Configuration > +# This isn't a minimal defconfig. Try make savedefconfig and copy the resulting defconfig file. Cheers James signature.asc Description: This is a digitally signed message part.
Re: [PATCH 14/15] MIPS: paravirt: Update mips_paravirt_defconfig
On Tuesday 20 May 2014 16:47:15 Andreas Herrmann wrote: > Change CPU selection, enable SMP, enable almost all virtio options. Looks like this should just be squashed into the previous patch if the original defconfig was insufficient. Cheers James signature.asc Description: This is a digitally signed message part.
Re: [PATCH 03/15] MIPS: OCTEON: Move CAVIUM_OCTEON_CVMSEG_SIZE to CPU_CAVIUM_OCTEON
On 05/20/2014 03:52 PM, James Hogan wrote: Hi Andreas, On Tuesday 20 May 2014 16:47:04 Andreas Herrmann wrote: From: David Daney CVMSEG is related to the CPU core not the SoC system. So needs to be configurable there. Signed-off-by: David Daney Signed-off-by: Andreas Herrmann --- arch/mips/cavium-octeon/Kconfig | 30 -- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index 227705d..c5e9975 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig [...] -config CAVIUM_OCTEON_CVMSEG_SIZE - int "Number of L1 cache lines reserved for CVMSEG memory" - range 0 54 - default 1 +config CAVIUM_OCTEON_HW_FIX_UNALIGNED + bool "Enable hardware fixups of unaligned loads and stores" + default "y" Is adding CAVIUM_OCTEON_HW_FIX_UNALIGNED in this patch intentional? It seems unrelated. Good catch. CAVIUM_OCTEON_HW_FIX_UNALIGNED and its users were removed, we shouldn't add it back. I think this is a case of rebasing gone wrong. David Daney -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 09/15] MIPS: Add functions for hypervisor call
On Tuesday 20 May 2014 16:47:10 Andreas Herrmann wrote:
> From: David Daney
>
> Signed-off-by: David Daney
> Signed-off-by: Andreas Herrmann
These look similar to the kvm_hypercall${n} functions in
arch/{x86,s390}/include/asm/kvm_para.h. Does it make sense to define that API
in kvm_para.h for MIPS instead of this one?
Cheers
James
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Description: This is a digitally signed message part.
[RFC PATCH v5_v2 01/11] driver core: platform: add device binding path 'driver_override'
From: Kim Phillips
Needed by platform device drivers, such as the vfio-platform driver
later in series, in order to bypass the existing OF, ACPI, id_table and
name string matches, and successfully be able to be bound to any
device, like so:
echo vfio-platform > /sys/bus/platform/devices/fff51000.ethernet/driver_override
echo fff51000.ethernet >
/sys/bus/platform/devices/fff51000.ethernet/driver/unbind
echo fff51000.ethernet > /sys/bus/platform/drivers_probe
This mimics "PCI: Introduce new device binding path using
pci_dev.driver_override" [1], which is an interface enhancement
for more deterministic PCI device binding, e.g., when in the
presence of hotplug.
[1] https://lists.cs.columbia.edu/pipermail/kvmarm/2014-May/009527.html
Suggested-by: Alex Williamson
Signed-off-by: Kim Phillips
---
changes in v2 patch of v5 of this patchseries:
- rebased onto today's Linus' ToT
- added kfree to match PCI counterpart fix, as Alex Williamson
just posted a v3 of the patch (thanks Christoffer for the
notification)
- in the commit text, replaced vfio platform driver reference with
'later in series', and updated the PCI version mailing list reference
to the v3 version.
Is it safe to assume this patch will continue to as part of the VFIO
platform driver patchseries, and be submitted by Antonis? If so, can
we start collecting some {Reviewed,Acked}-bys? Thanks, Kim.
Documentation/ABI/testing/sysfs-bus-platform | 20
drivers/base/platform.c | 47
include/linux/platform_device.h | 1 +
3 files changed, 68 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-bus-platform
diff --git a/Documentation/ABI/testing/sysfs-bus-platform
b/Documentation/ABI/testing/sysfs-bus-platform
new file mode 100644
index 000..5172a61
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-platform
@@ -0,0 +1,20 @@
+What: /sys/bus/platform/devices/.../driver_override
+Date: April 2014
+Contact: Kim Phillips
+Description:
+ This file allows the driver for a device to be specified which
+ will override standard OF, ACPI, ID table, and name matching.
+ When specified, only a driver with a name matching the value
+ written to driver_override will have an opportunity to bind
+ to the device. The override is specified by writing a string
+ to the driver_override file (echo vfio-platform > \
+ driver_override) and may be cleared with an empty string
+ (echo > driver_override). This returns the device to standard
+ matching rules binding. Writing to driver_override does not
+ automatically unbind the device from its current driver or make
+ any attempt to automatically load the specified driver. If no
+ driver with a matching name is currently loaded in the kernel,
+ the device will not bind to any driver. This also allows
+ devices to opt-out of driver binding using a driver_override
+ name such as "none". Only a single driver may be specified in
+ the override, there is no support for parsing delimiters.
diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index 5b47210..4f47563 100644
--- a/drivers/base/platform.c
+++ b/drivers/base/platform.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
#include "base.h"
#include "power/power.h"
@@ -188,6 +189,7 @@ static void platform_device_release(struct device *dev)
kfree(pa->pdev.dev.platform_data);
kfree(pa->pdev.mfd_cell);
kfree(pa->pdev.resource);
+ kfree(pa->pdev.driver_override);
kfree(pa);
}
@@ -695,8 +697,49 @@ static ssize_t modalias_show(struct device *dev, struct
device_attribute *a,
}
static DEVICE_ATTR_RO(modalias);
+static ssize_t driver_override_store(struct device *dev,
+struct device_attribute *attr,
+const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ char *driver_override, *old = pdev->driver_override, *cp;
+
+ if (count > PATH_MAX)
+ return -EINVAL;
+
+ driver_override = kstrndup(buf, count, GFP_KERNEL);
+ if (!driver_override)
+ return -ENOMEM;
+
+ cp = strchr(driver_override, '\n');
+ if (cp)
+ *cp = '\0';
+
+ if (strlen(driver_override)) {
+ pdev->driver_override = driver_override;
+ } else {
+ kfree(driver_override);
+ pdev->driver_override = NULL;
+ }
+
+ kfree(old);
+
+ return count;
+}
+
+static ssize_t driver_override_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(de
[Bug 65561] KVM:Entry failed on Single stepping sti instruction
https://bugzilla.kernel.org/show_bug.cgi?id=65561 --- Comment #5 from Jatin Kumar --- @Paolo: Thanks for the info. That makes sense to me. (In reply to Jidong Xiao from comment #4) > Jatin, are you using gdb to do the single step?(In reply to Jatin Kumar from > comment #2) No. I have been doing single stepping from inside the OS. It single steps its own code using debug trap untill some condition is met. During this whenever I hit an out instruction, the very next instruction is not skipped while single stepping. It may have been executing it because overall the code seems to be working correctly. I couldn't find anything online in this regard so I am curious if this is something QEMU specific. -- You are receiving this mail because: You are watching the assignee of the bug. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Bug 65561] KVM:Entry failed on Single stepping sti instruction
https://bugzilla.kernel.org/show_bug.cgi?id=65561 --- Comment #6 from Jatin Kumar --- (In reply to Jatin Kumar from comment #5) > whenever I hit an out instruction, the very next instruction is not skipped Sorry I meant 'is skipped'. -- You are receiving this mail because: You are watching the assignee of the bug. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
qemu.git build fail with error
Hi, After download the latest qemu.git(http://git.qemu.org/?p=qemu.git;a=summary), then compile the qemu.git, it will build fail with error Some build log CCtrace/generated-events.o CCtrace/generated-tracers.o CCutil/cutils.o ARlibqemustub.a lt LINK vscclient ARlibqemuutil.a LINK qemu-ga LINK qemu-nbd LINK qemu-img LINK qemu-io qemu-img.o: In function `add_format_to_seq': /root/qemu/qemu-img.c:73: undefined reference to `g_sequence_lookup' collect2: ld returned 1 exit status make: *** [qemu-img] Error 1 make: *** Waiting for unfinished jobs Is there anything to install ? -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: qemu.git build fail with error
On Wed, 05/21 05:40, Liu, RongrongX wrote: > Hi, > > After download the latest > qemu.git(http://git.qemu.org/?p=qemu.git;a=summary), then compile the > qemu.git, it will build fail with error > > Some build log > > CCtrace/generated-events.o > CCtrace/generated-tracers.o > CCutil/cutils.o > ARlibqemustub.a > lt LINK vscclient > ARlibqemuutil.a > LINK qemu-ga > LINK qemu-nbd > LINK qemu-img > LINK qemu-io > qemu-img.o: In function `add_format_to_seq': > /root/qemu/qemu-img.c:73: undefined reference to `g_sequence_lookup' > collect2: ld returned 1 exit status > make: *** [qemu-img] Error 1 > make: *** Waiting for unfinished jobs Hi, A recent change 1a443c1b8 (qemu-img: sort block formats in help message) added a silent dependency on glib >= 2.28. Fix posted by Mike Day is already on the way into qemu.git in Kevin's PULL request. Please wait for it to be applied and try again, or compile QEMU against a more recent glib. Thanks, Fam -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/15] MIPS: OCTEON: Move CAVIUM_OCTEON_CVMSEG_SIZE to CPU_CAVIUM_OCTEON
On Tue, May 20, 2014 at 04:23:03PM -0700, David Daney wrote: > On 05/20/2014 03:52 PM, James Hogan wrote: > >Hi Andreas, > > > >On Tuesday 20 May 2014 16:47:04 Andreas Herrmann wrote: > >>From: David Daney > >> > >>CVMSEG is related to the CPU core not the SoC system. So needs to be > >>configurable there. > >> > >>Signed-off-by: David Daney > >>Signed-off-by: Andreas Herrmann > >>--- > >> arch/mips/cavium-octeon/Kconfig | 30 -- > >> 1 file changed, 20 insertions(+), 10 deletions(-) > >> > >>diff --git a/arch/mips/cavium-octeon/Kconfig > >>b/arch/mips/cavium-octeon/Kconfig index 227705d..c5e9975 100644 > >>--- a/arch/mips/cavium-octeon/Kconfig > >>+++ b/arch/mips/cavium-octeon/Kconfig > [...] > >>-config CAVIUM_OCTEON_CVMSEG_SIZE > >>- int "Number of L1 cache lines reserved for CVMSEG memory" > >>- range 0 54 > >>- default 1 > >>+config CAVIUM_OCTEON_HW_FIX_UNALIGNED > >>+ bool "Enable hardware fixups of unaligned loads and stores" > >>+ default "y" > > > >Is adding CAVIUM_OCTEON_HW_FIX_UNALIGNED in this patch intentional? It seems > >unrelated. > > > > Good catch. CAVIUM_OCTEON_HW_FIX_UNALIGNED and its users were > removed, we shouldn't add it back. I think this is a case of > rebasing gone wrong. Oops, sorry, that wasn't intentional. James, thanks for catching this. Andreas -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 13/15] MIPS: Add defconfig for mips_paravirt
On Wed, May 21, 2014 at 12:14:31AM +0100, James Hogan wrote: > Hi Andreas, > > On Tuesday 20 May 2014 16:47:14 Andreas Herrmann wrote: > > From: David Daney > > > > Signed-off-by: David Daney > > Signed-off-by: Andreas Herrmann > > --- > > arch/mips/configs/mips_paravirt_defconfig | 1524 > > + 1 file changed, 1524 insertions(+) > > create mode 100644 arch/mips/configs/mips_paravirt_defconfig > > > > diff --git a/arch/mips/configs/mips_paravirt_defconfig > > b/arch/mips/configs/mips_paravirt_defconfig new file mode 100644 > > index 000..f0cac9c > > --- /dev/null > > +++ b/arch/mips/configs/mips_paravirt_defconfig > > @@ -0,0 +1,1524 @@ > > +# > > +# Automatically generated file; DO NOT EDIT. > > +# Linux/mips 3.15.0-rc4 Kernel Configuration > > +# > > This isn't a minimal defconfig. > > Try make savedefconfig and copy the resulting defconfig file. Ok. Thanks, Andreas -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 14/15] MIPS: paravirt: Update mips_paravirt_defconfig
On Wed, May 21, 2014 at 12:17:37AM +0100, James Hogan wrote: > On Tuesday 20 May 2014 16:47:15 Andreas Herrmann wrote: > > Change CPU selection, enable SMP, enable almost all virtio options. > > Looks like this should just be squashed into the previous patch if the > original defconfig was insufficient. I'll merge it. Andreas -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
