Re: [PATCH V3 2/2] spmi: pmic_arb: add support for hw version 2
Hey Gilad-
On Mon, Feb 09, 2015 at 03:51:12PM -0700, Gilad Avidov wrote:
Qualcomm PMIC Arbiter version-2 changes from version-1 are:
- Some different register offsets.
- New channel register space, one per PMIC peripheral (ppid).
All tx traffic uses these channels.
- New observer register space. All rx trafic uses this space.
- Different command format for spmi command registers.
Acked-by: Sagar Dharia sdha...@codeaurora.org
Signed-off-by: Gilad Avidov gavi...@codeaurora.org
[..]
+++ b/drivers/spmi/spmi-pmic-arb.c
[..]
@@ -645,12 +795,65 @@ static int spmi_pmic_arb_probe(struct platform_device
*pdev)
pa-spmic = ctrl;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, core);
- pa-base = devm_ioremap_resource(ctrl-dev, res);
- if (IS_ERR(pa-base)) {
- err = PTR_ERR(pa-base);
+ pa-rd_base = devm_ioremap_resource(ctrl-dev, res);
This seems like an awkward way to do this, especially if you end up
remapping it...
+ if (IS_ERR(pa-rd_base)) {
+ err = PTR_ERR(pa-rd_base);
goto err_put_ctrl;
}
+ hw_ver = readl_relaxed(pa-rd_base + PMIC_ARB_VERSION);
+ is_v1 = (hw_ver PMIC_ARB_VERSION_V2_MIN);
+
+ dev_info(ctrl-dev, PMIC Arb Version-%d (0x%x)\n, (is_v1 ? 1 : 2),
+ hw_ver);
+
+ if (is_v1) {
+ pa-ver_ops = pmic_arb_v1;
+ pa-wr_base = pa-rd_base;
+ } else {
+ u8 chan;
+ u16 ppid;
+ u32 regval;
+
+ pa-ver_ops = pmic_arb_v2;
+
+ pa-ppid_to_chan = devm_kzalloc(ctrl-dev,
+ PPID_TO_CHAN_TABLE_SZ, GFP_KERNEL);
+ if (!pa-ppid_to_chan) {
+ err = -ENOMEM;
+ goto err_put_ctrl;
+ }
+ /*
+ * PMIC_ARB_REG_CHNL is a table in HW mapping channel to ppid.
+ * ppid_to_chan is an in-memory invert of that table.
+ */
+ for (chan = 0; chan PMIC_ARB_MAX_CHNL; ++chan) {
+ regval = readl_relaxed(pa-rd_base +
+PMIC_ARB_REG_CHNL(chan));
+ if (!regval)
+ continue;
+
+ ppid = (regval 8) 0xFFF;
+ pa-ppid_to_chan[ppid] = chan;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+obsrvr);
+ pa-rd_base = devm_ioremap_resource(ctrl-dev, res);
...here. Especially because now you have some loose mapping hanging around
for the lifetime of the device. I'd suggest splitting the v1 and v2
probe routines out into their own functions.
Josh
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Re: [PATCH V3 1/2] spmi: remove wakeup command before slave probe
On Mon, Feb 09, 2015 at 03:51:11PM -0700, Gilad Avidov wrote: According to spmi spec a slave powers up into startup state and then transitions into active state. Thus, the wakeup command is not required before calling the slave's probe. The wakeup command is only needed for slaves that are in sleep state after receiving the sleep command. This is a bug since spmi master controllers, such as spmi-pmic-arb, which have no support for wakeup command return an error on that command and thus fail before reaching a slave driver probe. If masters are required by the spec to support all commands as Stephen mentions, then I'd argue this is not a bug in the core code at all, but in the spmi-pmic-arb driver. But, unfortunately, having lost access to the spec, I'll defer. Regardless, I think this is useful as an optimization, just with dubious justification. Therefore, Acked-by: Josh Cartwright jo...@eso.teric.us Josh -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] qcom_rpm: add support for IPQ8064 resources
The IPQ8064 SoC has several Resource Power Manager (RPM) controlled resources: four regulators (two SMB208s, each controlling two regulators) and two fabric clocks for the Network Subsystem (NSS). This patchset adds the appropriate definitions for these resources, and extends the existing RPM regulator driver to support the SMB208. This patchset is based ontop of v7 of Bjorne Andersson's RPM patchset [1]. 1: http://lkml.kernel.org/r/1411428329-23172-1-git-send-email-bjorn.anders...@sonymobile.com Josh Cartwright (3): mfd: devicetree: qcom_rpm: document IPQ8064 resources mfd: qcom_rpm: add support for IPQ8064 regulator: rpm: add support for RPM-controller SMB208 Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 6 +++- drivers/mfd/qcom_rpm.c | 41 ++ drivers/regulator/qcom_rpm-regulator.c | 19 ++ include/dt-bindings/mfd/qcom-rpm.h | 6 4 files changed, 71 insertions(+), 1 deletion(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] mfd: devicetree: qcom_rpm: document IPQ8064 resources
The IPQ8064 SoC has several RPM-controlled resources, an NSS fabrick clock and four regulator resources. Provide definitions for them. Signed-off-by: Josh Cartwright jo...@codeaurora.org --- Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 6 +- include/dt-bindings/mfd/qcom-rpm.h | 6 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt index 4264021..6d4e3ec 100644 --- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt +++ b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt @@ -12,6 +12,7 @@ frequencies. qcom,rpm-apq8064 qcom,rpm-msm8660 qcom,rpm-msm8960 + qcom,rpm-ipq8064 - reg: Usage: required @@ -67,6 +68,7 @@ of valid subnodes that can operate on these resources. qcom,rpm-pm8901-ftsmps qcom,rpm-pm8921-smps qcom,rpm-pm8921-ftsmps + qcom,rpm-smb208 - reg: Usage: required @@ -76,7 +78,9 @@ of valid subnodes that can operate on these resources. QCOM_RPM_PM8058_SMPS0 - QCOM_RPM_PM8058_SMPS4, QCOM_RPM_PM8821_SMPS1 - QCOM_RPM_PM8821_SMPS2, QCOM_RPM_PM8901_SMPS0 - QCOM_RPM_PM8901_SMPS4, - QCOM_RPM_PM8921_SMPS1 - QCOM_RPM_PM8921_SMPS8 + QCOM_RPM_PM8921_SMPS1 - QCOM_RPM_PM8921_SMPS8, + QCOM_RPM_SMB208_S1a, QCOM_RPM_SMB208_S1b, + QCOM_RPM_SMB208_S2a, QCOM_RPM_SMB208_S2b - bias-pull-down: Usage: optional diff --git a/include/dt-bindings/mfd/qcom-rpm.h b/include/dt-bindings/mfd/qcom-rpm.h index 388a6f3..13a9d4b 100644 --- a/include/dt-bindings/mfd/qcom-rpm.h +++ b/include/dt-bindings/mfd/qcom-rpm.h @@ -141,6 +141,12 @@ #define QCOM_RPM_SYS_FABRIC_MODE 131 #define QCOM_RPM_USB_OTG_SWITCH132 #define QCOM_RPM_VDDMIN_GPIO 133 +#define QCOM_RPM_NSS_FABRIC_0_CLK 134 +#define QCOM_RPM_NSS_FABRIC_1_CLK 135 +#define QCOM_RPM_SMB208_S1a136 +#define QCOM_RPM_SMB208_S1b137 +#define QCOM_RPM_SMB208_S2a138 +#define QCOM_RPM_SMB208_S2b139 /* * Constants used to select force mode for regulators. -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] mfd: qcom_rpm: add support for IPQ8064
The IPQ8064 also includes an RPM following the same message structure as
other chips. In addition, it supports a few new resource types to
support the NSS fabric clocks and the SMB208/SMB209 regulators found on
the reference boards.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/mfd/qcom_rpm.c | 41 +
1 file changed, 41 insertions(+)
diff --git a/drivers/mfd/qcom_rpm.c b/drivers/mfd/qcom_rpm.c
index 0dd7a6fe..5ead23b 100644
--- a/drivers/mfd/qcom_rpm.c
+++ b/drivers/mfd/qcom_rpm.c
@@ -324,10 +324,51 @@ static const struct qcom_rpm_data msm8960_template = {
.n_resources = ARRAY_SIZE(msm8960_rpm_resource_table),
};
+static const struct qcom_rpm_resource ipq806x_rpm_resource_table[] = {
+ [QCOM_RPM_CXO_CLK] ={ 25, 9, 5, 1 },
+ [QCOM_RPM_PXO_CLK] ={ 26, 10, 6, 1 },
+ [QCOM_RPM_APPS_FABRIC_CLK] ={ 27, 11, 8, 1 },
+ [QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 },
+ [QCOM_RPM_NSS_FABRIC_0_CLK] = { 29, 13, 10, 1 },
+ [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 },
+ [QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 },
+ [QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 },
+ [QCOM_RPM_NSS_FABRIC_1_CLK] = { 33, 17, 14, 1 },
+ [QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 },
+ [QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 2 },
+ [QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 3 },
+ [QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 },
+ [QCOM_RPM_APPS_FABRIC_ARB] ={ 41, 22, 21, 12 },
+ [QCOM_RPM_SYS_FABRIC_HALT] ={ 53, 23, 22, 2 },
+ [QCOM_RPM_SYS_FABRIC_MODE] ={ 55, 24, 23, 3 },
+ [QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 },
+ [QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 30 },
+ [QCOM_RPM_MM_FABRIC_HALT] = { 89, 27, 26, 2 },
+ [QCOM_RPM_MM_FABRIC_MODE] = { 91, 28, 27, 3 },
+ [QCOM_RPM_MM_FABRIC_IOCTL] ={ 94, 29, 28, 1 },
+ [QCOM_RPM_MM_FABRIC_ARB] = { 95, 30, 29, 2 },
+ [QCOM_RPM_CXO_BUFFERS] ={ 209, 33, 31, 1 },
+ [QCOM_RPM_USB_OTG_SWITCH] = { 210, 34, 32, 1 },
+ [QCOM_RPM_HDMI_SWITCH] ={ 211, 35, 33, 1 },
+ [QCOM_RPM_DDR_DMM] ={ 212, 36, 34, 2 },
+ [QCOM_RPM_VDDMIN_GPIO] ={ 215, 40, 39, 1 },
+ [QCOM_RPM_SMB208_S1a] = { 216, 41, 90, 2 },
+ [QCOM_RPM_SMB208_S1b] = { 218, 43, 91, 2 },
+ [QCOM_RPM_SMB208_S2a] = { 220, 45, 92, 2 },
+ [QCOM_RPM_SMB208_S2b] = { 222, 47, 93, 2 },
+};
+
+static const struct qcom_rpm_data ipq806x_template = {
+ .version = 3,
+ .resource_table = ipq806x_rpm_resource_table,
+ .n_resources = ARRAY_SIZE(ipq806x_rpm_resource_table),
+};
+
static const struct of_device_id qcom_rpm_of_match[] = {
{ .compatible = qcom,rpm-apq8064, .data = apq8064_template },
{ .compatible = qcom,rpm-msm8660, .data = msm8660_template },
{ .compatible = qcom,rpm-msm8960, .data = msm8960_template },
+ { .compatible = qcom,rpm-ipq8064, .data = ipq806x_template },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_rpm_of_match);
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[PATCH 3/3] regulator: rpm: add support for RPM-controller SMB208
The IPQ8064 reference boards make use of SMB208 regulators which are
controlled by RPM. Implement support for these regulators in the RPM
regulator driver.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/regulator/qcom_rpm-regulator.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/regulator/qcom_rpm-regulator.c
b/drivers/regulator/qcom_rpm-regulator.c
index b869254..36c39e9 100644
--- a/drivers/regulator/qcom_rpm-regulator.c
+++ b/drivers/regulator/qcom_rpm-regulator.c
@@ -183,6 +183,13 @@ static const struct regulator_linear_range ftsmps_ranges[]
= {
REGULATOR_LINEAR_RANGE(150, 64, 100, 5),
};
+static const struct regulator_linear_range smb208_ranges[] = {
+ REGULATOR_LINEAR_RANGE( 375000, 0, 29, 12500),
+ REGULATOR_LINEAR_RANGE( 75, 30, 89, 12500),
+ REGULATOR_LINEAR_RANGE(150, 90, 153, 25000),
+ REGULATOR_LINEAR_RANGE(310, 154, 234, 25000),
+};
+
static const struct regulator_linear_range ncp_ranges[] = {
REGULATOR_LINEAR_RANGE(150, 0, 31, 5),
};
@@ -559,6 +566,16 @@ static const struct qcom_rpm_reg pm8921_switch = {
.parts = rpm8960_switch_parts,
};
+static const struct qcom_rpm_reg smb208_smps = {
+ .desc.linear_ranges = smb208_ranges,
+ .desc.n_linear_ranges = ARRAY_SIZE(smb208_ranges),
+ .desc.n_voltages = 235,
+ .desc.ops = uV_ops,
+ .parts = rpm8960_smps_parts,
+ .supports_force_mode_auto = false,
+ .supports_force_mode_bypass = false,
+};
+
static const struct of_device_id rpm_of_match[] = {
{ .compatible = qcom,rpm-pm8058-pldo, .data = pm8058_pldo },
{ .compatible = qcom,rpm-pm8058-nldo, .data = pm8058_nldo },
@@ -578,6 +595,8 @@ static const struct of_device_id rpm_of_match[] = {
{ .compatible = qcom,rpm-pm8921-ftsmps, .data = pm8921_ftsmps },
{ .compatible = qcom,rpm-pm8921-ncp, .data = pm8921_ncp },
{ .compatible = qcom,rpm-pm8921-switch, .data = pm8921_switch },
+
+ { .compatible = qcom,rpm-smb208, .data = smb208_smps },
{ }
};
MODULE_DEVICE_TABLE(of, rpm_of_match);
--
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Re: [PATCH v2 3/3] ARM: dts: qcom: Add SDHC nodes for APQ8084 platform
On Wed, Oct 08, 2014 at 09:18:44PM +0200, Nicolas Dechesne wrote: Georgi, On Tue, Sep 2, 2014 at 5:40 PM, Georgi Djakov gdja...@mm-sol.com wrote: Enable support for the two SD host controllers on the APQ8084 platform by adding the required nodes to the DT files. On the IFC6540 board, the first controller is connected to the onboard eMMC and the second is connected to a micro-SD card slot. testing this set of patch on IFC6540, i noticed that not all partitions from the eMMC are detected. booting [1] which is basically 3.17-rc7 with a few additional patches, i can see the following relevant mmc traces: [1.162587] mmc0: BKOPS_EN bit is not set [1.315357] mmc0: new HS200 MMC card at address 0001 [1.318098] mmcblk0: mmc0:0001 SEM16G 14.6 GiB [1.330377] mmcblk0boot0: mmc0:0001 SEM16G partition 1 4.00 MiB [1.333652] mmcblk0boot1: mmc0:0001 SEM16G partition 2 4.00 MiB [1.345424] mmcblk0rpmb: mmc0:0001 SEM16G partition 3 4.00 MiB [1.358135] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 [1.365902] mmcblk0boot1: p1 [1.367833] mmcblk0boot0: unknown partition table This has bitten me more times than I care to admit, but have you checked that you've set CONFIG_MMC_BLOCK_MINORS higher than 16? Perhaps we should be doing that in qcom_defconfig if we aren't already. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/4] Add KPSS watchdog driver to relevant device trees
Now that the Krait Processor Sub-system (KPSS) Watchdog driver has been pulled into Wim's tree destined for 3.18, add descriptions of the WDT in the relevant device trees, and include the driver in qcom_defconfig. Josh Cartwright (4): ARM: qcom: add QCOM_WDT driver to qcom_defconfig ARM: qcom: add description of KPSS WDT for IPQ8064 ARM: qcom: add description of KPSS WDT for APQ8064 ARM: qcom: add description of KPSS WDT for MSM8960 arch/arm/boot/dts/qcom-apq8064.dtsi | 15 +++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++ arch/arm/boot/dts/qcom-msm8960.dtsi | 15 +++ arch/arm/configs/qcom_defconfig | 2 ++ 4 files changed, 47 insertions(+) -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4] ARM: qcom: add description of KPSS WDT for IPQ8064
Describe the Krait Processor Sub-system (KPSS) Watchdog timer in the
IPQ8064 device tree. Also, add a fixed-clock description of SLEEP_CLK,
which will do for now.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 244f857..3372b49 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -60,6 +60,14 @@
};
};
+ clocks {
+ sleep_clk: sleep_clk {
+ compatible = fixed-clock;
+ clock-frequency = 32768;
+ #clock-cells = 0;
+ };
+ };
+
soc: soc {
#address-cells = 1;
#size-cells = 1;
@@ -96,6 +104,13 @@
cpu-offset = 0x8;
};
+ watchdog@208a038 {
+ compatible = qcom,kpss-wdt-ipq8064;
+ reg = 0x0208a038 0x40;
+ clocks = sleep_clk;
+ timeout-sec = 10;
+ };
+
acc0: clock-controller@2088000 {
compatible = qcom,kpss-acc-v1;
reg = 0x02088000 0x1000, 0x02008000 0x1000;
--
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[PATCH 4/4] ARM: qcom: add description of KPSS WDT for MSM8960
Describe the Krait Processor Sub-system (KPSS) Watchdog timer in the
MSM8960 device tree. Also, add a fixed-clock description of SLEEP_CLK,
which will do for now.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8960.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi
b/arch/arm/boot/dts/qcom-msm8960.dtsi
index e1b0d5c..072866b 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -48,6 +48,14 @@
qcom,no-pc-write;
};
+ clocks {
+ sleep_clk: sleep_clk {
+ compatible = fixed-clock;
+ clock-frequency = 32768;
+ #clock-cells = 0;
+ };
+ };
+
soc: soc {
#address-cells = 1;
#size-cells = 1;
@@ -73,6 +81,13 @@
cpu-offset = 0x8;
};
+ watchdog@208a038 {
+ compatible = qcom,kpss-wdt-msm8960;
+ reg = 0x0208a038 0x40;
+ clocks = sleep_clk;
+ timeout-sec = 10;
+ };
+
msmgpio: gpio@80 {
compatible = qcom,msm-gpio;
gpio-controller;
--
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[PATCH 3/4] ARM: qcom: add description of KPSS WDT for APQ8064
Describe the Krait Processor Sub-system (KPSS) Watchdog timer in the
APQ8064 device tree. Also, add a fixed-clock description of SLEEP_CLK,
which will do for now.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index b3154c0..8439afa 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -66,6 +66,14 @@
interrupts = 1 10 0x304;
};
+ clocks {
+ sleep_clk: sleep_clk {
+ compatible = fixed-clock;
+ clock-frequency = 32768;
+ #clock-cells = 0;
+ };
+ };
+
soc: soc {
#address-cells = 1;
#size-cells = 1;
@@ -119,6 +127,13 @@
cpu-offset = 0x8;
};
+ watchdog@208a038 {
+ compatible = qcom,kpss-wdt-apq8064;
+ reg = 0x0208a038 0x40;
+ clocks = sleep_clk;
+ timeout-sec = 10;
+ };
+
acc0: clock-controller@2088000 {
compatible = qcom,kpss-acc-v1;
reg = 0x02088000 0x1000, 0x02008000 0x1000;
--
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Re: [PATCH 2/4] ARM: qcom: add description of KPSS WDT for IPQ8064
Hey Stephen-
Thanks for taking a look.
On Wed, Oct 01, 2014 at 10:28:55AM -0700, Stephen Boyd wrote:
On 10/01, Josh Cartwright wrote:
@@ -96,6 +104,13 @@
cpu-offset = 0x8;
};
+ watchdog@208a038 {
+ compatible = qcom,kpss-wdt-ipq8064;
+ reg = 0x0208a038 0x40;
Not being aligned to 4k or 1k raises red flags.
The watchdog is part of the timer block (on this chip it's
qcom,kpss-timer). We should add qcom,kpss-wdt to the compatible
list in the timer binding and extend that binding to have clocks
and timeout-sec (watchdog-timeout-sec?).
Yeah, the description of this thing is a bit awkward.
I'm not sure how I'd feel about just just adding qcom,kpss-wdt to the
timer node compatible. I'm wondering if the WDT(s) should be a
subnode(s) of the timer node instead?
The percpu-ness of the two WDTs makes configuration even more
interesting, as it's possible you'd want to independently configure
timeouts for CPU0_WDT0 and CPU1_WDT0, supporting this with a coalesced
timer/wdt would be cumbersome.
Something like this perhaps:
timer@200a000 {
compatible = qcom,kpss-timer, qcom,msm-timer;
interrupts = 1 1 0x301,
1 2 0x301,
1 3 0x301;
reg = 0x0200a000 0x100;
clock-frequency = 2500,
32768;
cpu-offset = 0x8;
#address-cells = 1;
#size-cells = 1;
ranges;
cpu0_wdt0: watchdog@208a038 {
compatible = qcom,kpss-wdt;
reg = 0x208a038 0x40;
interrupts = 1 4 0x301,
clocks = sleep_clk;
timeout-sec = 10;
cpu = cpu0;
};
cpu0_wdt1: watchdog@208a060 {
compatible = qcom,kpss-wdt;
reg = 0x208a060 0x40;
interrupts = 1 5 0x301,
clocks = sleep_clk;
timeout-sec = 20;
cpu = cpu0;
};
cpu1_wdt0: watchdog@209a038 {
compatible = qcom,kpss-wdt;
reg = 0x209a038 0x40;
interrupts = 1 4 0x301,
clocks = sleep_clk;
timeout-sec = 8;
cpu = cpu1;
};
cpu1_wdt1: watchdog@209a060 {
compatible = qcom,kpss-wdt;
reg = 0x209a060 0x40;
interrupts = 1 5 0x301,
clocks = sleep_clk;
timeout-sec = 15;
cpu = cpu1;
};
};
This would follow DT best practices of having one node per device. We
could also add the interrupts too, even if they're not used by the
driver right now.
+ clocks = sleep_clk;
+ timeout-sec = 10;
+ };
+
--
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[PATCH v3 3/3] watchdog: qcom: register a restart notifier
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD) are preferrable for issuing a more complete
reset of the chip. As such, keep the priority of the watchdog notifier
low.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/watchdog/qcom-wdt.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
index 0f56ca3..8ce339f 100644
--- a/drivers/watchdog/qcom-wdt.c
+++ b/drivers/watchdog/qcom-wdt.c
@@ -10,12 +10,14 @@
* GNU General Public License for more details.
*
*/
+#include linux/delay.h
#include linux/clk.h
#include linux/io.h
#include linux/kernel.h
#include linux/module.h
#include linux/of.h
#include linux/platform_device.h
+#include linux/reboot.h
#include linux/watchdog.h
#define WDT_RST0x0
@@ -26,6 +28,7 @@ struct qcom_wdt {
struct watchdog_device wdd;
struct clk *clk;
unsigned long rate;
+ struct notifier_block restart_nb;
void __iomem*base;
};
@@ -84,6 +87,32 @@ static const struct watchdog_info qcom_wdt_info = {
.identity = KBUILD_MODNAME,
};
+static int qcom_wdt_restart(struct notifier_block *nb, unsigned long action,
+ void *data)
+{
+ struct qcom_wdt *wdt = container_of(nb, struct qcom_wdt, restart_nb);
+ u32 timeout;
+
+ /*
+* Trigger watchdog bite:
+*Setup BITE_TIME to be 128ms, and enable WDT.
+*/
+ timeout = 128 * wdt-rate / 1000;
+
+ writel(0, wdt-base + WDT_EN);
+ writel(1, wdt-base + WDT_RST);
+ writel(timeout, wdt-base + WDT_BITE_TIME);
+ writel(1, wdt-base + WDT_EN);
+
+ /*
+* Actually make sure the above sequence hits hardware before sleeping.
+*/
+ wmb();
+
+ msleep(150);
+ return NOTIFY_DONE;
+}
+
static int qcom_wdt_probe(struct platform_device *pdev)
{
struct qcom_wdt *wdt;
@@ -149,6 +178,14 @@ static int qcom_wdt_probe(struct platform_device *pdev)
goto err_clk_unprepare;
}
+ /*
+* WDT restart notifier has priority 0 (use as a last resort)
+*/
+ wdt-restart_nb.notifier_call = qcom_wdt_restart;
+ ret = register_restart_handler(wdt-restart_nb);
+ if (ret)
+ dev_err(pdev-dev, failed to setup restart handler\n);
+
platform_set_drvdata(pdev, wdt);
return 0;
@@ -162,6 +199,7 @@ static int qcom_wdt_remove(struct platform_device *pdev)
{
struct qcom_wdt *wdt = platform_get_drvdata(pdev);
+ unregister_restart_handler(wdt-restart_nb);
watchdog_unregister_device(wdt-wdd);
clk_disable_unprepare(wdt-clk);
return 0;
--
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[PATCH v3 0/3] watchdog: add support for QCOM WDT
This patchset provides support for the Watchdog Timer (WDT) found in the Krait Processor Sub-system (KPSS) of the MSM8960, APQ8064, and IPQ8064 chips. This driver is implemented ontop of WATCHDOG_CORE, and therefore its primary interface is through userspace. The implemantion is currently very basic (i.e. it doesn't support PRETIMEOUT, even though it could be implemented through the WDT's BARK functionality). It should also be fairly easy to extend this driver in the future to support newer chipsets as well. Patch 3 also extends the driver to also register a restart_notifier, making it possible for the WDT to act as a restart mechanism if more favorable mechanisms don't work. This is important for some boards which don't support PS_HOLD, like the IPQ8064-based AP148 board. Changes since v2: - input clock phandle - input clock in device tree documentation - Fixup error handling paths during probe() - Use a more sane timeout (128ms), and add msleep() - Add some additional sanitation for clock rates Changes since v1: - Make use of clock API instead of using a 'clock-frequency' property - Setup default timeout of 30 seconds when one is not specified - Add remove() function to allow for module unloading - Don't acquire/release watchdog lock on restart - Don't bail completely if restart_handler registration fails Josh Cartwright (3): watchdog: qcom: add support for KPSS WDT watchdog: qcom: document device tree bindings watchdog: qcom: register a restart notifier .../devicetree/bindings/watchdog/qcom-wdt.txt | 22 ++ drivers/watchdog/Kconfig | 13 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/qcom-wdt.c| 227 + 4 files changed, 263 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt create mode 100644 drivers/watchdog/qcom-wdt.c -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 1/3] watchdog: qcom: add support for KPSS WDT
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/watchdog/Kconfig| 13 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/qcom-wdt.c | 189
3 files changed, 203 insertions(+)
create mode 100644 drivers/watchdog/qcom-wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 79d2589..c389ed7 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -421,6 +421,19 @@ config SIRFSOC_WATCHDOG
Support for CSR SiRFprimaII and SiRFatlasVI watchdog. When
the watchdog triggers the system will be reset.
+config QCOM_WDT
+ tristate QCOM watchdog
+ depends on HAS_IOMEM
+ depends on ARCH_QCOM
+ select WATCHDOG_CORE
+ help
+ Say Y here to include Watchdog timer support for the watchdog found
+ on QCOM chipsets. Currently supported targets are the MSM8960,
+ APQ8064, and IPQ8064.
+
+ To compile this driver as a module, choose M here: the
+ module will be called qcom_wdt.
+
# AVR32 Architecture
config AT32AP700X_WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 985a66c..cede21e 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o
obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
obj-$(CONFIG_MOXART_WDT) += moxart_wdt.o
obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o
+obj-$(CONFIG_QCOM_WDT) += qcom-wdt.o
obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o
# AVR32 Architecture
diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
new file mode 100644
index 000..0f56ca3
--- /dev/null
+++ b/drivers/watchdog/qcom-wdt.c
@@ -0,0 +1,189 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include linux/clk.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/watchdog.h
+
+#define WDT_RST0x0
+#define WDT_EN 0x8
+#define WDT_BITE_TIME 0x24
+
+struct qcom_wdt {
+ struct watchdog_device wdd;
+ struct clk *clk;
+ unsigned long rate;
+ void __iomem*base;
+};
+
+static inline
+struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
+{
+ return container_of(wdd, struct qcom_wdt, wdd);
+}
+
+static int qcom_wdt_start(struct watchdog_device *wdd)
+{
+ struct qcom_wdt *wdt = to_qcom_wdt(wdd);
+
+ writel(0, wdt-base + WDT_EN);
+ writel(1, wdt-base + WDT_RST);
+ writel(wdd-timeout * wdt-rate, wdt-base + WDT_BITE_TIME);
+ writel(1, wdt-base + WDT_EN);
+ return 0;
+}
+
+static int qcom_wdt_stop(struct watchdog_device *wdd)
+{
+ struct qcom_wdt *wdt = to_qcom_wdt(wdd);
+
+ writel(0, wdt-base + WDT_EN);
+ return 0;
+}
+
+static int qcom_wdt_ping(struct watchdog_device *wdd)
+{
+ struct qcom_wdt *wdt = to_qcom_wdt(wdd);
+
+ writel(1, wdt-base + WDT_RST);
+ return 0;
+}
+
+static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
+ unsigned int timeout)
+{
+ wdd-timeout = timeout;
+ return qcom_wdt_start(wdd);
+}
+
+static const struct watchdog_ops qcom_wdt_ops = {
+ .start = qcom_wdt_start,
+ .stop = qcom_wdt_stop,
+ .ping = qcom_wdt_ping,
+ .set_timeout= qcom_wdt_set_timeout,
+ .owner = THIS_MODULE,
+};
+
+static const struct watchdog_info qcom_wdt_info = {
+ .options= WDIOF_KEEPALIVEPING
+ | WDIOF_MAGICCLOSE
+ | WDIOF_SETTIMEOUT,
+ .identity = KBUILD_MODNAME,
+};
+
+static int qcom_wdt_probe(struct platform_device *pdev)
+{
+ struct qcom_wdt *wdt;
+ struct resource *res;
+ int ret;
+
+ wdt = devm_kzalloc(pdev-dev, sizeof(*wdt), GFP_KERNEL);
+ if (!wdt)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ wdt-base = devm_ioremap_resource(pdev-dev, res);
+ if (IS_ERR(wdt-base)) {
+ ret = PTR_ERR(wdt-base);
+ goto err_out;
+ }
+
+ wdt-clk = devm_clk_get(pdev-dev, NULL);
+ if (IS_ERR(wdt-clk)) {
+ ret = PTR_ERR(wdt-clk);
+ goto
[PATCH v3 2/3] watchdog: qcom: document device tree bindings
The Qualcomm Krait Processor Sub-system (KPSS) contains one or more
instances of the WDT. Provide documentation on how to describe these in
the device tree.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
.../devicetree/bindings/watchdog/qcom-wdt.txt | 22 ++
1 file changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
new file mode 100644
index 000..c75566e
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
@@ -0,0 +1,22 @@
+Qualcomm Krait Processor Sub-system (KPSS) Watchdog
+---
+
+Required properties :
+- compatible : shall contain only one of the following:
+
+ qcom,kpss-wdt-msm8960
+ qcom,kpss-wdt-apq8064
+ qcom,kpss-wdt-ipq8064
+
+- reg : shall contain base register location and length
+- clocks : shall contain the input clock
+- timeout-sec : shall contain the default watchdog timeout in seconds,
+if unset, the default timeout is 30 seconds
+
+Example:
+ watchdog@208a038 {
+ compatible = qcom,kpss-wdt-ipq8064;
+ reg = 0x0208a038 0x40;
+ clocks = sleep_clk;
+ timeout-sec = 10;
+ };
--
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Re: [PATCH v3 1/3] watchdog: qcom: add support for KPSS WDT
On Thu, Sep 25, 2014 at 11:38:57AM -0700, Guenter Roeck wrote:
On Thu, Sep 25, 2014 at 12:48:51PM -0500, Josh Cartwright wrote:
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
Hi Josh,
just a couple of minor comments this time (yes, I know,
I am being difficult ;-).
Difficult, maybe, but at least someone's taking a look! Thanks, again.
[..]
+++ b/drivers/watchdog/qcom-wdt.c
[..]
+static int qcom_wdt_probe(struct platform_device *pdev)
+{
+ struct qcom_wdt *wdt;
+ struct resource *res;
+ int ret;
+
+ wdt = devm_kzalloc(pdev-dev, sizeof(*wdt), GFP_KERNEL);
+ if (!wdt)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ wdt-base = devm_ioremap_resource(pdev-dev, res);
+ if (IS_ERR(wdt-base)) {
+ ret = PTR_ERR(wdt-base);
+ goto err_out;
This is really unnecessary. Just return PTR_ERR((wdt-base) as you did before.
No need to make the code more complicated than necessary.
Basic rule is: If you can return immediately, do it. Otherwise use goto
and have a single error handler.
+ }
+
+ wdt-clk = devm_clk_get(pdev-dev, NULL);
+ if (IS_ERR(wdt-clk)) {
+ ret = PTR_ERR(wdt-clk);
+ goto err_out;
Same here.
+ }
+
+ ret = clk_prepare_enable(wdt-clk);
+ if (ret) {
+ dev_err(pdev-dev, failed to setup clock\n);
+ goto err_out;
and here.
Okay, I can fix these up.
Josh
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Re: [PATCH v3 2/3] watchdog: qcom: document device tree bindings
On Thu, Sep 25, 2014 at 11:43:14AM -0700, Guenter Roeck wrote: On Thu, Sep 25, 2014 at 12:48:52PM -0500, Josh Cartwright wrote: [..] +- timeout-sec : shall contain the default watchdog timeout in seconds, +if unset, the default timeout is 30 seconds Hi Josh, timeout-sec is optional, not mandatory. Indeed, I made this change in v2, but didn't reflect it in the document. Good catch. Will fix. Josh -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 3/3] watchdog: qcom: register a restart notifier
On Thu, Sep 25, 2014 at 11:41:49AM -0700, Guenter Roeck wrote: On Thu, Sep 25, 2014 at 12:48:53PM -0500, Josh Cartwright wrote: The WDT's BITE_TIME warm-reset behavior can be leveraged as a last resort mechanism for triggering chip reset. Usually, other restart methods (such as PS_HOLD) are preferrable for issuing a more complete reset of the chip. As such, keep the priority of the watchdog notifier low. Signed-off-by: Josh Cartwright jo...@codeaurora.org --- drivers/watchdog/qcom-wdt.c | 38 ++ 1 file changed, 38 insertions(+) diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c index 0f56ca3..8ce339f 100644 --- a/drivers/watchdog/qcom-wdt.c +++ b/drivers/watchdog/qcom-wdt.c @@ -10,12 +10,14 @@ * GNU General Public License for more details. * */ +#include linux/delay.h Nitpick: Please keep alphabetical order of include files. That makes it easier to identify include files later on. That was my intent, but apparently I fail at the alphabet :). Normally instead of thinking I pipe the #include list through 'sort'. Not sure why I didn't do so this time around. Thanks, Josh -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 0/3] watchdog: add support for QCOM WDT
This patchset provides support for the Watchdog Timer (WDT) found in the Krait Processor Sub-system (KPSS) of the MSM8960, APQ8064, and IPQ8064 chips. This driver is implemented ontop of WATCHDOG_CORE, and therefore its primary interface is through userspace. The implemantion is currently very basic (i.e. it doesn't support PRETIMEOUT, even though it could be implemented through the WDT's BARK functionality). It should also be fairly easy to extend this driver in the future to support newer chipsets as well. Patch 3 also extends the driver to also register a restart_notifier, making it possible for the WDT to act as a restart mechanism if more favorable mechanisms don't work. This is important for some boards which don't support PS_HOLD, like the IPQ8064-based AP148 board. Changes since v3: - More error code cleanup, resolved nits - Documented 'timeout-sec' property as optional Changes since v2: - input clock phandle - input clock in device tree documentation - Fixup error handling paths during probe() - Use a more sane timeout (128ms), and add msleep() - Add some additional sanitation for clock rates Changes since v1: - Make use of clock API instead of using a 'clock-frequency' property - Setup default timeout of 30 seconds when one is not specified - Add remove() function to allow for module unloading - Don't acquire/release watchdog lock on restart - Don't bail completely if restart_handler registration fails Josh Cartwright (3): watchdog: qcom: add support for KPSS WDT watchdog: qcom: document device tree bindings watchdog: qcom: register a restart notifier .../devicetree/bindings/watchdog/qcom-wdt.txt | 24 +++ drivers/watchdog/Kconfig | 13 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/qcom-wdt.c| 224 + 4 files changed, 262 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt create mode 100644 drivers/watchdog/qcom-wdt.c -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 3/3] watchdog: qcom: register a restart notifier
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD) are preferrable for issuing a more complete
reset of the chip. As such, keep the priority of the watchdog notifier
low.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/watchdog/qcom-wdt.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
index 68db322..aa85618 100644
--- a/drivers/watchdog/qcom-wdt.c
+++ b/drivers/watchdog/qcom-wdt.c
@@ -11,11 +11,13 @@
*
*/
#include linux/clk.h
+#include linux/delay.h
#include linux/io.h
#include linux/kernel.h
#include linux/module.h
#include linux/of.h
#include linux/platform_device.h
+#include linux/reboot.h
#include linux/watchdog.h
#define WDT_RST0x0
@@ -26,6 +28,7 @@ struct qcom_wdt {
struct watchdog_device wdd;
struct clk *clk;
unsigned long rate;
+ struct notifier_block restart_nb;
void __iomem*base;
};
@@ -84,6 +87,32 @@ static const struct watchdog_info qcom_wdt_info = {
.identity = KBUILD_MODNAME,
};
+static int qcom_wdt_restart(struct notifier_block *nb, unsigned long action,
+ void *data)
+{
+ struct qcom_wdt *wdt = container_of(nb, struct qcom_wdt, restart_nb);
+ u32 timeout;
+
+ /*
+* Trigger watchdog bite:
+*Setup BITE_TIME to be 128ms, and enable WDT.
+*/
+ timeout = 128 * wdt-rate / 1000;
+
+ writel(0, wdt-base + WDT_EN);
+ writel(1, wdt-base + WDT_RST);
+ writel(timeout, wdt-base + WDT_BITE_TIME);
+ writel(1, wdt-base + WDT_EN);
+
+ /*
+* Actually make sure the above sequence hits hardware before sleeping.
+*/
+ wmb();
+
+ msleep(150);
+ return NOTIFY_DONE;
+}
+
static int qcom_wdt_probe(struct platform_device *pdev)
{
struct qcom_wdt *wdt;
@@ -147,6 +176,14 @@ static int qcom_wdt_probe(struct platform_device *pdev)
goto err_clk_unprepare;
}
+ /*
+* WDT restart notifier has priority 0 (use as a last resort)
+*/
+ wdt-restart_nb.notifier_call = qcom_wdt_restart;
+ ret = register_restart_handler(wdt-restart_nb);
+ if (ret)
+ dev_err(pdev-dev, failed to setup restart handler\n);
+
platform_set_drvdata(pdev, wdt);
return 0;
@@ -159,6 +196,7 @@ static int qcom_wdt_remove(struct platform_device *pdev)
{
struct qcom_wdt *wdt = platform_get_drvdata(pdev);
+ unregister_restart_handler(wdt-restart_nb);
watchdog_unregister_device(wdt-wdd);
clk_disable_unprepare(wdt-clk);
return 0;
--
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[PATCH v4 1/3] watchdog: qcom: add support for KPSS WDT
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/watchdog/Kconfig| 13
drivers/watchdog/Makefile | 1 +
drivers/watchdog/qcom-wdt.c | 186
3 files changed, 200 insertions(+)
create mode 100644 drivers/watchdog/qcom-wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 1d1330a..0479e3f 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -443,6 +443,19 @@ config TEGRA_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called tegra_wdt.
+config QCOM_WDT
+ tristate QCOM watchdog
+ depends on HAS_IOMEM
+ depends on ARCH_QCOM
+ select WATCHDOG_CORE
+ help
+ Say Y here to include Watchdog timer support for the watchdog found
+ on QCOM chipsets. Currently supported targets are the MSM8960,
+ APQ8064, and IPQ8064.
+
+ To compile this driver as a module, choose M here: the
+ module will be called qcom_wdt.
+
# AVR32 Architecture
config AT32AP700X_WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 468c320..d645448 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o
obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
obj-$(CONFIG_MOXART_WDT) += moxart_wdt.o
obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o
+obj-$(CONFIG_QCOM_WDT) += qcom-wdt.o
obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o
obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o
diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
new file mode 100644
index 000..68db322
--- /dev/null
+++ b/drivers/watchdog/qcom-wdt.c
@@ -0,0 +1,186 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include linux/clk.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/watchdog.h
+
+#define WDT_RST0x0
+#define WDT_EN 0x8
+#define WDT_BITE_TIME 0x24
+
+struct qcom_wdt {
+ struct watchdog_device wdd;
+ struct clk *clk;
+ unsigned long rate;
+ void __iomem*base;
+};
+
+static inline
+struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
+{
+ return container_of(wdd, struct qcom_wdt, wdd);
+}
+
+static int qcom_wdt_start(struct watchdog_device *wdd)
+{
+ struct qcom_wdt *wdt = to_qcom_wdt(wdd);
+
+ writel(0, wdt-base + WDT_EN);
+ writel(1, wdt-base + WDT_RST);
+ writel(wdd-timeout * wdt-rate, wdt-base + WDT_BITE_TIME);
+ writel(1, wdt-base + WDT_EN);
+ return 0;
+}
+
+static int qcom_wdt_stop(struct watchdog_device *wdd)
+{
+ struct qcom_wdt *wdt = to_qcom_wdt(wdd);
+
+ writel(0, wdt-base + WDT_EN);
+ return 0;
+}
+
+static int qcom_wdt_ping(struct watchdog_device *wdd)
+{
+ struct qcom_wdt *wdt = to_qcom_wdt(wdd);
+
+ writel(1, wdt-base + WDT_RST);
+ return 0;
+}
+
+static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
+ unsigned int timeout)
+{
+ wdd-timeout = timeout;
+ return qcom_wdt_start(wdd);
+}
+
+static const struct watchdog_ops qcom_wdt_ops = {
+ .start = qcom_wdt_start,
+ .stop = qcom_wdt_stop,
+ .ping = qcom_wdt_ping,
+ .set_timeout= qcom_wdt_set_timeout,
+ .owner = THIS_MODULE,
+};
+
+static const struct watchdog_info qcom_wdt_info = {
+ .options= WDIOF_KEEPALIVEPING
+ | WDIOF_MAGICCLOSE
+ | WDIOF_SETTIMEOUT,
+ .identity = KBUILD_MODNAME,
+};
+
+static int qcom_wdt_probe(struct platform_device *pdev)
+{
+ struct qcom_wdt *wdt;
+ struct resource *res;
+ int ret;
+
+ wdt = devm_kzalloc(pdev-dev, sizeof(*wdt), GFP_KERNEL);
+ if (!wdt)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ wdt-base = devm_ioremap_resource(pdev-dev, res);
+ if (IS_ERR(wdt-base))
+ return PTR_ERR(wdt-base);
+
+ wdt-clk = devm_clk_get(pdev-dev, NULL);
+ if (IS_ERR(wdt-clk)) {
+ dev_err(pdev-dev, failed to get input clock\n);
+ return PTR_ERR(wdt
[PATCH v4 2/3] watchdog: qcom: document device tree bindings
The Qualcomm Krait Processor Sub-system (KPSS) contains one or more
instances of the WDT. Provide documentation on how to describe these in
the device tree.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
.../devicetree/bindings/watchdog/qcom-wdt.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
new file mode 100644
index 000..4726924
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
@@ -0,0 +1,24 @@
+Qualcomm Krait Processor Sub-system (KPSS) Watchdog
+---
+
+Required properties :
+- compatible : shall contain only one of the following:
+
+ qcom,kpss-wdt-msm8960
+ qcom,kpss-wdt-apq8064
+ qcom,kpss-wdt-ipq8064
+
+- reg : shall contain base register location and length
+- clocks : shall contain the input clock
+
+Optional properties :
+- timeout-sec : shall contain the default watchdog timeout in seconds,
+if unset, the default timeout is 30 seconds
+
+Example:
+ watchdog@208a038 {
+ compatible = qcom,kpss-wdt-ipq8064;
+ reg = 0x0208a038 0x40;
+ clocks = sleep_clk;
+ timeout-sec = 10;
+ };
--
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hosted by The Linux Foundation
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Re: [PATCH v6 1/5] qcom: spm: Add Subsystem Power Manager driver
Hey Lina-
A few comments inline:
On Tue, Sep 23, 2014 at 05:51:17PM -0600, Lina Iyer wrote:
+++ b/drivers/soc/qcom/spm.c
[..]
+
+static u32 reg_offsets_saw2_v2_1[MSM_SPM_REG_NR] = {
const?
+ [MSM_SPM_REG_SAW2_SECURE] = 0x00,
+ [MSM_SPM_REG_SAW2_ID] = 0x04,
+ [MSM_SPM_REG_SAW2_CFG] = 0x08,
+ [MSM_SPM_REG_SAW2_SPM_STS] = 0x0C,
+ [MSM_SPM_REG_SAW2_AVS_STS] = 0x10,
+ [MSM_SPM_REG_SAW2_PMIC_STS] = 0x14,
+ [MSM_SPM_REG_SAW2_RST] = 0x18,
+ [MSM_SPM_REG_SAW2_VCTL] = 0x1C,
+ [MSM_SPM_REG_SAW2_AVS_CTL] = 0x20,
+ [MSM_SPM_REG_SAW2_AVS_LIMIT]= 0x24,
+ [MSM_SPM_REG_SAW2_AVS_DLY] = 0x28,
+ [MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x2C,
+ [MSM_SPM_REG_SAW2_SPM_CTL] = 0x30,
+ [MSM_SPM_REG_SAW2_SPM_DLY] = 0x34,
+ [MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x40,
+ [MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x44,
+ [MSM_SPM_REG_SAW2_PMIC_DATA_2] = 0x48,
+ [MSM_SPM_REG_SAW2_PMIC_DATA_3] = 0x4C,
+ [MSM_SPM_REG_SAW2_PMIC_DATA_4] = 0x50,
+ [MSM_SPM_REG_SAW2_PMIC_DATA_5] = 0x54,
+ [MSM_SPM_REG_SAW2_PMIC_DATA_6] = 0x58,
+ [MSM_SPM_REG_SAW2_PMIC_DATA_7] = 0x5C,
+ [MSM_SPM_REG_SAW2_SEQ_ENTRY]= 0x80,
+ [MSM_SPM_REG_SAW2_VERSION] = 0xFD0,
+};
+
+struct spm_of {
+ char *key;
const char *key?
+ u32 id;
+};
+
+struct msm_spm_mode {
+ u32 mode;
+ u32 start_addr;
+};
+
+struct msm_spm_driver_data {
+ void __iomem *reg_base_addr;
+ u32 *reg_offsets;
+ struct msm_spm_mode *modes;
+ u32 num_modes;
Why u32?
Actually, the maximum modes is fixed, and really all you need to keep
around is the start_addr per-mode (which is only 5 bits), and an
additional bit indicating whether that mode is valid. I'd recommend
folding msm_spm_mode into msm_spm_driver_data completely. Something
like this, maybe:
struct msm_spm_driver_data {
void __iomem *reg_base_addr;
const u32 *reg_offsets;
struct {
u8 is_valid;
u8 start_addr;
} modes[MSM_SPM_MODE_NR];
};
+};
+
+struct msm_spm_device {
+ bool initialized;
+ struct msm_spm_driver_data drv;
+};
+
+static DEFINE_PER_CPU_SHARED_ALIGNED(struct msm_spm_device,
msm_cpu_spm_device);
Why have both msm_spm_device and msm_spm_driver_data?
Would it be easier if you instead used 'struct msm_spm_device *', and
used NULL to indicate it has not been initialized?
+static const struct of_device_id msm_spm_match_table[] __initconst;
Just move the table above probe.
+
+static int msm_spm_drv_set_low_power_mode(struct msm_spm_driver_data *drv,
+ u32 mode)
+{
+ int i;
+ u32 start_addr = 0;
+ u32 ctl_val;
+
+ for (i = 0; i drv-num_modes; i++) {
+ if (drv-modes[i].mode == mode) {
+ start_addr = drv-modes[i].start_addr;
+ break;
+ }
+ }
+
+ if (i == drv-num_modes)
+ return -EINVAL;
+
+ /* Update bits 10:4 in the SPM CTL register */
+ ctl_val = readl_relaxed(drv-reg_base_addr +
+ drv-reg_offsets[MSM_SPM_REG_SAW2_SPM_CTL]);
+ start_addr = 0x7F;
+ start_addr = 4;
+ ctl_val = 0xF80F;
+ ctl_val |= start_addr;
+ writel_relaxed(ctl_val, drv-reg_base_addr +
+ drv-reg_offsets[MSM_SPM_REG_SAW2_SPM_CTL]);
+ /* Ensure we have written the start address */
+ wmb();
+
+ return 0;
+}
+
+static int msm_spm_drv_set_spm_enable(struct msm_spm_driver_data *drv,
+ bool enable)
+{
+ u32 value = enable ? 0x01 : 0x00;
+ u32 ctl_val;
+
+ ctl_val = readl_relaxed(drv-reg_base_addr +
+ drv-reg_offsets[MSM_SPM_REG_SAW2_SPM_CTL]);
+
+ /* Update SPM_CTL to enable/disable the SPM */
+ if ((ctl_val SPM_CTL_ENABLE) != value) {
+ /* Clear the existing value and update */
+ ctl_val = ~0x1;
+ ctl_val |= value;
+ writel_relaxed(ctl_val, drv-reg_base_addr +
+ drv-reg_offsets[MSM_SPM_REG_SAW2_SPM_CTL]);
+
+ /* Ensure we have enabled/disabled before returning */
+ wmb();
+ }
+
+ return 0;
+}
+
+/**
+ * msm_spm_set_low_power_mode() - Configure SPM start address for low power
mode
+ * @mode: SPM LPM mode to enter
+ */
+int msm_spm_set_low_power_mode(u32 mode)
+{
+ struct msm_spm_device *dev = __get_cpu_var(msm_cpu_spm_device);
+ int ret = -EINVAL;
+
+ if (!dev-initialized)
+ return -ENXIO;
+
+ if
Re: [PATCH v2 1/3] watchdog: qcom: add support for KPSS WDT
On Wed, Sep 24, 2014 at 08:58:54AM -0700, Guenter Roeck wrote:
On Tue, Sep 23, 2014 at 06:04:36PM -0500, Josh Cartwright wrote:
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
Hi Josh,
looks much better. Couple of comments inline.
Thanks for another review!
[..]
+++ b/drivers/watchdog/Kconfig
@@ -443,6 +443,19 @@ config TEGRA_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called tegra_wdt.
+config QCOM_WDT
+ tristate QCOM watchdog
+ depends on HAS_IOMEM
+ depends on ARCH_QCOM
+ select WATCHDOG_CORE
+ help
+ Say Y here to include Watchdog timer support for the watchdog found
+ on QCOM chipsets. Currently supported targets are the MSM8960,
+ APQ8064, and IPQ8064.
+
+ To compile this driver as a module, choose M here: the
+ module will be called qcom_wdt.
+
# AVR32 Architecture
[..]
+static int qcom_wdt_probe(struct platform_device *pdev)
+{
+ struct qcom_wdt *wdt;
+ struct resource *res;
+ unsigned long freq;
+ int ret;
+
+ wdt = devm_kzalloc(pdev-dev, sizeof(*wdt), GFP_KERNEL);
+ if (!wdt)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ wdt-base = devm_ioremap_resource(pdev-dev, res);
+ if (IS_ERR(wdt-base))
+ return PTR_ERR(wdt-base);
+
+ wdt-clk = devm_clk_get(pdev-dev, NULL);
+ if (IS_ERR(wdt-clk))
+ return PTR_ERR(wdt-clk);
+
+ ret = clk_prepare_enable(wdt-clk);
+ if (ret) {
+ dev_err(pdev-dev, failed to setup clock\n);
+ return ret;
+ }
+
+ /*
+* We use the clock rate to calculate the max timeout, so ensure it's
+* not zero to avoid a divide-by-zero exception.
+*/
+ freq = clk_get_rate(wdt-clk);
+ if (freq == 0) {
+ dev_err(pdev-dev, invalid clock rate\n);
+ return -EINVAL;
+ }
This will need clk_disable_unprepare().
Yep. Nice catch. Will fix.
Since you are reading the frequency here, it might make sense to store it
in struct qcom_wdt so you don't have to call clk_get_rate() again in the
start function.
Yeah, it doesn't save much, but I'll go ahead and add it.
+ wdt-wdd.dev = pdev-dev;
+ wdt-wdd.info = qcom_wdt_info;
+ wdt-wdd.ops = qcom_wdt_ops;
+ wdt-wdd.min_timeout = 1;
+ wdt-wdd.max_timeout = 0x1000U / freq;
What if the frequency turns out to be larger than 8947848 Hz ?
Then your maximum timeout is below the default timeout.
And if the frequency is larger than 268435456 Hz, the maximum
timeout would be 0.
Yes, I should be doing more sanity checking. I'll do so.
+ /*
+* If 'timeout-sec' unspecified in devicetree, assume a 30 second
+* default.
+*/
+ if (watchdog_init_timeout(wdt-wdd, 0, pdev-dev))
+ wdt-wdd.timeout = 30;
You can just initialize timeout above with 30 seconds. Saves you the if
statement here.
Great. Thanks.
+ ret = watchdog_register_device(wdt-wdd);
+ if (ret) {
+ dev_err(pdev-dev, failed to register watchdog\n);
This will need a clk_disable_unprepare().
Given that this is needed twice, you might want to consider using
error exit code below, as suggested in CodingStyle.
Indeed. Will do.
Thanks again,
Josh
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Re: [PATCH v3] power: reset: use restart_notifier mechanism for msm-poweroff
On Tue, Sep 23, 2014 at 12:48:42PM -0500, Kumar Gala wrote: On Sep 23, 2014, at 1:28 AM, Pramod Gurav pramod.gu...@smartplayin.com wrote: +linux-arm-msm On Tuesday 23 September 2014 11:38 AM, Pramod Gurav wrote: This change replaces use of arm_pm_restart with recently introduced reset mechanism in Linux kernel called restart_notifier. Can you update the commit message to include details about the priority level we are setting it to. Probably something like Josh had: Choose priority 128, as according to documentation, this mechanism is sufficient to restart the entire system?. Hmm, what happens if we have ps_hold restart and msm-poweroff enabled. Which one should have priority? I would hope we would avoid a situation where both this driver is probed, and the pinctrl-msm driver has registered a restart handler? That is, we wouldn't ever mix the pinctrl-msm ps_hold mechanism (for MSM8660/MSM8960/APQ8064, etc) and msm-poweroff (APQ8074 and later). Is this a case you're worried about? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/3] watchdog: add support for QCOM WDT
This patchset provides support for the Watchdog Timer (WDT) found in the Krait Processor Sub-system (KPSS) of the MSM8960, APQ8064, and IPQ8064 chips. This driver is implemented ontop of WATCHDOG_CORE, and therefore its primary interface is through userspace. The implemantion is currently very basic (i.e. it doesn't support PRETIMEOUT, even though it could be implemented through the WDT's BARK functionality). It should also be fairly easy to extend this driver in the future to support newer chipsets as well. Patch 3 also extends the driver to also register a restart_notifier, making it possible for the WDT to act as a restart mechanism if more favorable mechanisms don't work. This is important for some boards which don't support PS_HOLD, like the IPQ8064-based AP148 board. Changes since v1: - Make use of clock API instead of using a 'clock-frequency' property - Setup default timeout of 30 seconds when one is not specified - Add remove() function to allow for module unloading - Don't acquire/release watchdog lock on restart - Don't bail completely if restart_handler registration fails Josh Cartwright (3): watchdog: qcom: add support for KPSS WDT watchdog: qcom: document device tree bindings watchdog: qcom: register a restart notifier .../devicetree/bindings/watchdog/qcom-wdt.txt | 22 +++ drivers/watchdog/Kconfig | 13 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/qcom-wdt.c| 204 + 4 files changed, 240 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt create mode 100644 drivers/watchdog/qcom-wdt.c -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/3] watchdog: qcom: add support for KPSS WDT
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/watchdog/Kconfig| 13
drivers/watchdog/Makefile | 1 +
drivers/watchdog/qcom-wdt.c | 176
3 files changed, 190 insertions(+)
create mode 100644 drivers/watchdog/qcom-wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 1d1330a..0479e3f 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -443,6 +443,19 @@ config TEGRA_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called tegra_wdt.
+config QCOM_WDT
+ tristate QCOM watchdog
+ depends on HAS_IOMEM
+ depends on ARCH_QCOM
+ select WATCHDOG_CORE
+ help
+ Say Y here to include Watchdog timer support for the watchdog found
+ on QCOM chipsets. Currently supported targets are the MSM8960,
+ APQ8064, and IPQ8064.
+
+ To compile this driver as a module, choose M here: the
+ module will be called qcom_wdt.
+
# AVR32 Architecture
config AT32AP700X_WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 468c320..d645448 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o
obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
obj-$(CONFIG_MOXART_WDT) += moxart_wdt.o
obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o
+obj-$(CONFIG_QCOM_WDT) += qcom-wdt.o
obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o
obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o
diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
new file mode 100644
index 000..d5e46e2
--- /dev/null
+++ b/drivers/watchdog/qcom-wdt.c
@@ -0,0 +1,176 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include linux/clk.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/watchdog.h
+
+#define WDT_RST0x0
+#define WDT_EN 0x8
+#define WDT_BITE_TIME 0x24
+
+struct qcom_wdt {
+ struct watchdog_device wdd;
+ struct clk *clk;
+ void __iomem*base;
+};
+
+static inline
+struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
+{
+ return container_of(wdd, struct qcom_wdt, wdd);
+}
+
+static int qcom_wdt_start(struct watchdog_device *wdd)
+{
+ struct qcom_wdt *wdt = to_qcom_wdt(wdd);
+ unsigned long bite_time;
+
+ bite_time = wdd-timeout * clk_get_rate(wdt-clk);
+
+ writel(0, wdt-base + WDT_EN);
+ writel(1, wdt-base + WDT_RST);
+ writel(bite_time, wdt-base + WDT_BITE_TIME);
+ writel(1, wdt-base + WDT_EN);
+ return 0;
+}
+
+static int qcom_wdt_stop(struct watchdog_device *wdd)
+{
+ struct qcom_wdt *wdt = to_qcom_wdt(wdd);
+
+ writel(0, wdt-base + WDT_EN);
+ return 0;
+}
+
+static int qcom_wdt_ping(struct watchdog_device *wdd)
+{
+ struct qcom_wdt *wdt = to_qcom_wdt(wdd);
+
+ writel(1, wdt-base + WDT_RST);
+ return 0;
+}
+
+static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
+ unsigned int timeout)
+{
+ wdd-timeout = timeout;
+ return qcom_wdt_start(wdd);
+}
+
+static const struct watchdog_ops qcom_wdt_ops = {
+ .start = qcom_wdt_start,
+ .stop = qcom_wdt_stop,
+ .ping = qcom_wdt_ping,
+ .set_timeout= qcom_wdt_set_timeout,
+ .owner = THIS_MODULE,
+};
+
+static const struct watchdog_info qcom_wdt_info = {
+ .options= WDIOF_KEEPALIVEPING
+ | WDIOF_MAGICCLOSE
+ | WDIOF_SETTIMEOUT,
+ .identity = KBUILD_MODNAME,
+};
+
+static int qcom_wdt_probe(struct platform_device *pdev)
+{
+ struct qcom_wdt *wdt;
+ struct resource *res;
+ unsigned long freq;
+ int ret;
+
+ wdt = devm_kzalloc(pdev-dev, sizeof(*wdt), GFP_KERNEL);
+ if (!wdt)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ wdt-base = devm_ioremap_resource(pdev-dev, res);
+ if (IS_ERR(wdt-base))
+ return PTR_ERR(wdt-base);
+
+ wdt-clk = devm_clk_get(pdev-dev, NULL);
+ if (IS_ERR(wdt-clk))
+ return PTR_ERR
[PATCH v2 3/3] watchdog: qcom: register a restart notifier
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD) are preferrable for issuing a more complete
reset of the chip. As such, keep the priority of the watchdog notifier
low.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/watchdog/qcom-wdt.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
index d5e46e2..eba92ef 100644
--- a/drivers/watchdog/qcom-wdt.c
+++ b/drivers/watchdog/qcom-wdt.c
@@ -16,6 +16,7 @@
#include linux/module.h
#include linux/of.h
#include linux/platform_device.h
+#include linux/reboot.h
#include linux/watchdog.h
#define WDT_RST0x0
@@ -25,6 +26,7 @@
struct qcom_wdt {
struct watchdog_device wdd;
struct clk *clk;
+ struct notifier_block restart_nb;
void __iomem*base;
};
@@ -86,6 +88,23 @@ static const struct watchdog_info qcom_wdt_info = {
.identity = KBUILD_MODNAME,
};
+static int qcom_wdt_restart(struct notifier_block *nb, unsigned long action,
+ void *data)
+{
+ struct qcom_wdt *wdt = container_of(nb, struct qcom_wdt, restart_nb);
+
+ /*
+* Trigger watchdog bite:
+*Setup BITE_TIME to be very low, and enable WDT.
+* 0x31F3 = 390ms @ 32kHz, also value at reset
+*/
+ writel(0, wdt-base + WDT_EN);
+ writel(1, wdt-base + WDT_RST);
+ writel(0x31F3, wdt-base + WDT_BITE_TIME);
+ writel(1, wdt-base + WDT_EN);
+ return NOTIFY_DONE;
+}
+
static int qcom_wdt_probe(struct platform_device *pdev)
{
struct qcom_wdt *wdt;
@@ -141,6 +160,14 @@ static int qcom_wdt_probe(struct platform_device *pdev)
return ret;
}
+ /*
+* WDT restart notifier has priority 0 (use as a last resort)
+*/
+ wdt-restart_nb.notifier_call = qcom_wdt_restart;
+ ret = register_restart_handler(wdt-restart_nb);
+ if (ret)
+ dev_err(pdev-dev, failed to setup restart handler\n);
+
platform_set_drvdata(pdev, wdt);
return 0;
}
@@ -149,6 +176,7 @@ static int qcom_wdt_remove(struct platform_device *pdev)
{
struct qcom_wdt *wdt = platform_get_drvdata(pdev);
+ unregister_restart_handler(wdt-restart_nb);
watchdog_unregister_device(wdt-wdd);
clk_disable_unprepare(wdt-clk);
return 0;
--
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[PATCH v2 2/3] watchdog: qcom: document device tree bindings
The Qualcomm Krait Processor Sub-system (KPSS) contains one or more
instances of the WDT. Provide documentation on how to describe these in
the device tree.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
.../devicetree/bindings/watchdog/qcom-wdt.txt | 22 ++
1 file changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
new file mode 100644
index 000..6a1d758
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
@@ -0,0 +1,22 @@
+Qualcomm Krait Processor Sub-system (KPSS) Watchdog
+---
+
+Required properties :
+- compatible : shall contain only one of the following:
+
+ qcom,kpss-wdt-msm8960
+ qcom,kpss-wdt-apq8064
+ qcom,kpss-wdt-ipq8064
+
+- reg : shall contain base register location and length
+- clocks : shall contain the input clock phandle
+- timeout-sec : shall contain the default watchdog timeout in seconds,
+if unset, the default timeout is 30 seconds
+
+Example:
+ watchdog@208a038 {
+ compatible = qcom,kpss-wdt-ipq8064;
+ reg = 0x0208a038 0x40;
+ clocks = sleep_clk;
+ timeout-sec = 10;
+ };
--
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Re: [PATCH] pinctrl: qcom: use restart_notifier mechanism for ps_hold
On Thu, Sep 18, 2014 at 08:34:41PM -0700, Guenter Roeck wrote:
On 09/18/2014 07:54 PM, Guenter Roeck wrote:
On 09/18/2014 03:32 PM, Josh Cartwright wrote:
By converting to the restart_notifier mechanism for restart, we allow
for other mechanisms, like the watchdog, to be used for restart in the
case where PS_HOLD has failed to reset the chip.
Choose priority 128, as according to documentation, this mechanism is
sufficient to restart the entire system.
Cc: Pramod Gurav pramod.gu...@smartplayin.com
Cc: Guenter Roeck li...@roeck-us.net
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
[..]
int msm_pinctrl_probe(struct platform_device *pdev,
const struct msm_pinctrl_soc_data *soc_data)
@@ -943,6 +948,15 @@ int msm_pinctrl_remove(struct platform_device *pdev)
pinctrl_unregister(pctrl-pctrl);
+if (pctrl-restart_nb.notifier_call) {
One more comment: The conditional is really unnecessary. Just let
unregister_restart_handler deal with it ...
+ret = unregister_restart_handler(pctrl-restart_nb);
and just ignore the error return. The function will only return an error
if the entry was not found, and then it is a don't care.
Awesome, thanks. I like simplifications :). I was hijacking
notifier_call to indicate whether or not the restart notifier was
registered at all (because it's conditional on the particular chipset
having a ps_hold function). But, nice to know
unregister_restart_handler() does the right thing if the handler wasn't
registered in the first place.
Josh
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Re: [PATCH 1/3] watchdog: qcom: add support for KPSS WDT
On Thu, Sep 18, 2014 at 08:41:43PM -0700, Guenter Roeck wrote: On 09/18/2014 08:24 PM, Josh Cartwright wrote: On Thu, Sep 18, 2014 at 07:41:17PM -0700, Guenter Roeck wrote: On 09/18/2014 03:26 PM, Josh Cartwright wrote: Add a driver for the watchdog timer block found in the Krait Processor Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064. Signed-off-by: Josh Cartwright jo...@codeaurora.org Hi Josh, comments inline. Thanks for taking a look! [..] + watchdog_init_timeout(wdt-wdd, 0, pdev-dev); That leaves you with no default timeout if timeout-sec is not set in devicetree, which if I understand the code correctly might result in an immediate reset. Is this really what you want to happen ? I think I'd like to handle timeout-sec being unspecified as an error at probe. If someone explicitly sets timeout-sec = 0, then they get what they ask for. I'll take another look to see how to make this happen. Hmm.. kind of unusual. Usual would be to initialize the timeout together with min_timeout / max_timeout above and only force the user to specify a value if the default timeout is not desirable. You don't really gain anything by making timeout-sec mandatory. Making timeout-sec mandatory makes it so I don't have to decide what a sane default is. :) It's even less clear about what a sane default is looking at the other watchdog drivers. From the drivers I looked at, it ranges any where from 30s to 2mins. Am I just to choose? Why do these even differ between all of the drivers? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] watchdog: qcom: register a restart notifier
On Thu, Sep 18, 2014 at 09:03:18PM -0700, Guenter Roeck wrote: On 09/18/2014 08:32 PM, Josh Cartwright wrote: On Thu, Sep 18, 2014 at 07:47:54PM -0700, Guenter Roeck wrote: On 09/18/2014 03:27 PM, Josh Cartwright wrote: [..] Nothing magic, it's just a reasonably low value to set the bite time counter at. It also happens to be the value at reset. Can you add a note explaining that this reflects a reset delay of n milliseconds or whatever it is ? Certainly. Will do. Thanks, Josh -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] watchdog: add support for QCOM WDT
This patchset provides support for the Watchdog Timer (WDT) found in the Krait Processor Sub-system (KPSS) of the MSM8960, APQ8064, and IPQ8064 chips. This driver is implemented ontop of WATCHDOG_CORE, and therefore its primary interface is through userspace. The implemantion is currently very basic (i.e. it doesn't support PRETIMEOUT, even though it could be implemented through the WDT's BARK functionality). It should also be fairly easy to extend this driver in the future to support newer chipsets as well. Patch 3 also extends the driver to also register a restart_notifier, making it possible for the WDT to act as a restart mechanism if more favorable mechanisms don't work. This is important for some boards which don't support PS_HOLD, like the IPQ8064-based AP148 board. Josh Cartwright (3): watchdog: qcom: add support for KPSS WDT watchdog: qcom: document device tree bindings watchdog: qcom: register a restart notifier .../devicetree/bindings/watchdog/qcom-wdt.txt | 21 +++ drivers/watchdog/Kconfig | 10 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/qcom-wdt.c| 176 + 4 files changed, 208 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt create mode 100644 drivers/watchdog/qcom-wdt.c -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] watchdog: qcom: add support for KPSS WDT
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/watchdog/Kconfig| 10 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/qcom-wdt.c | 145
3 files changed, 156 insertions(+)
create mode 100644 drivers/watchdog/qcom-wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 1d1330a..5ccb963 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -443,6 +443,16 @@ config TEGRA_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called tegra_wdt.
+config QCOM_WDT
+ bool QCOM watchdog
+ depends on HAS_IOMEM
+ depends on ARCH_QCOM
+ select WATCHDOG_CORE
+ help
+ Say Y here to include Watchdog timer support for the watchdog found
+ on QCOM chipsets. Currently supported targets are the MSM8960,
+ APQ8064, and IPQ8064.
+
# AVR32 Architecture
config AT32AP700X_WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 468c320..d645448 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o
obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
obj-$(CONFIG_MOXART_WDT) += moxart_wdt.o
obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o
+obj-$(CONFIG_QCOM_WDT) += qcom-wdt.o
obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o
obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o
diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
new file mode 100644
index 000..e9409f5
--- /dev/null
+++ b/drivers/watchdog/qcom-wdt.c
@@ -0,0 +1,145 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/watchdog.h
+
+#define WDT_RST0x0
+#define WDT_EN 0x8
+#define WDT_BITE_TIME 0x24
+
+struct qcom_wdt {
+ struct watchdog_device wdd;
+ unsigned long freq;
+ void __iomem*base;
+};
+
+static inline
+struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
+{
+ return container_of(wdd, struct qcom_wdt, wdd);
+}
+
+static int qcom_wdt_start(struct watchdog_device *wdd)
+{
+ struct qcom_wdt *wdt = to_qcom_wdt(wdd);
+
+ writel(0, wdt-base + WDT_EN);
+ writel(1, wdt-base + WDT_RST);
+ writel(wdd-timeout * wdt-freq, wdt-base + WDT_BITE_TIME);
+ writel(1, wdt-base + WDT_EN);
+ return 0;
+}
+
+static int qcom_wdt_stop(struct watchdog_device *wdd)
+{
+ struct qcom_wdt *wdt = to_qcom_wdt(wdd);
+
+ writel(0, wdt-base + WDT_EN);
+ return 0;
+}
+
+static int qcom_wdt_ping(struct watchdog_device *wdd)
+{
+ struct qcom_wdt *wdt = to_qcom_wdt(wdd);
+
+ writel(1, wdt-base + WDT_RST);
+ return 0;
+}
+
+static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
+ unsigned int timeout)
+{
+ wdd-timeout = timeout;
+ return qcom_wdt_start(wdd);
+}
+
+static const struct watchdog_ops qcom_wdt_ops = {
+ .start = qcom_wdt_start,
+ .stop = qcom_wdt_stop,
+ .ping = qcom_wdt_ping,
+ .set_timeout= qcom_wdt_set_timeout,
+ .owner = THIS_MODULE,
+};
+
+static const struct watchdog_info qcom_wdt_info = {
+ .options= WDIOF_KEEPALIVEPING
+ | WDIOF_MAGICCLOSE
+ | WDIOF_SETTIMEOUT,
+ .identity = KBUILD_MODNAME,
+};
+
+static int qcom_watchdog_probe(struct platform_device *pdev)
+{
+ struct qcom_wdt *wdt;
+ struct resource *res;
+ u32 tmp;
+ int ret;
+
+ wdt = devm_kzalloc(pdev-dev, sizeof(*wdt), GFP_KERNEL);
+ if (!wdt)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, wdt);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ wdt-base = devm_ioremap_resource(pdev-dev, res);
+ if (IS_ERR(wdt-base))
+ return PTR_ERR(wdt-base);
+
+ ret = of_property_read_u32(pdev-dev.of_node, clock-frequency, tmp);
+ if (ret) {
+ dev_err(pdev-dev, unable to get clock-frequency\n);
+ return ret;
+ }
+
+ wdt-freq = tmp;
+
+ wdt-wdd.dev = pdev-dev;
+ wdt-wdd.info
[PATCH 2/3] watchdog: qcom: document device tree bindings
The Qualcomm Krait Processor Sub-system (KPSS) contains one or more
instances of the WDT. Provide documentation on how to describe these in
the device tree.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
.../devicetree/bindings/watchdog/qcom-wdt.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
new file mode 100644
index 000..e65cb8e
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
@@ -0,0 +1,21 @@
+Qualcomm Krait Processor Sub-system (KPSS) Watchdog
+---
+
+Required properties :
+- compatible : shall contain only one of the following:
+
+ qcom,kpss-wdt-msm8960
+ qcom,kpss-wdt-apq8064
+ qcom,kpss-wdt-ipq8064
+
+- reg : shall contain base register location and length
+- clock-frequency : shall contain the frequency at which the watchdog ticks
+- timeout-sec : shall contain the default watchdog timeout in seconds
+
+Example:
+ watchdog@208a038 {
+ compatible = qcom,kpss-wdt-ipq8064;
+ reg = 0x0208a038 0x40;
+ clock-frequency = 32768;
+ timeout-sec = 10;
+ };
--
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[PATCH 3/3] watchdog: qcom: register a restart notifier
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD) are preferrable for issuing a more complete
reset of the chip. As such, keep the priority of the watchdog notifier
low.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/watchdog/qcom-wdt.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
index e9409f5..710ab43 100644
--- a/drivers/watchdog/qcom-wdt.c
+++ b/drivers/watchdog/qcom-wdt.c
@@ -15,6 +15,7 @@
#include linux/module.h
#include linux/of.h
#include linux/platform_device.h
+#include linux/reboot.h
#include linux/watchdog.h
#define WDT_RST0x0
@@ -24,6 +25,7 @@
struct qcom_wdt {
struct watchdog_device wdd;
unsigned long freq;
+ struct notifier_block restart_nb;
void __iomem*base;
};
@@ -82,6 +84,24 @@ static const struct watchdog_info qcom_wdt_info = {
.identity = KBUILD_MODNAME,
};
+static int qcom_wdt_restart(struct notifier_block *nb, unsigned long action,
+ void *data)
+{
+ struct qcom_wdt *wdt = container_of(nb, struct qcom_wdt, restart_nb);
+
+ /*
+* Trigger watchdog bite:
+*Setup BITE_TIME to be very low, and enable WDT.
+*/
+ mutex_lock(wdt-wdd.lock);
+ writel_relaxed(0, wdt-base + WDT_EN);
+ writel_relaxed(1, wdt-base + WDT_RST);
+ writel_relaxed(0x31F3, wdt-base + WDT_BITE_TIME);
+ writel_relaxed(1, wdt-base + WDT_EN);
+ mutex_unlock(wdt-wdd.lock);
+ return NOTIFY_DONE;
+}
+
static int qcom_watchdog_probe(struct platform_device *pdev)
{
struct qcom_wdt *wdt;
@@ -121,6 +141,17 @@ static int qcom_watchdog_probe(struct platform_device
*pdev)
return ret;
}
+ /*
+* WDT restart notifier has priority 0 (use as a last resort)
+*/
+ wdt-restart_nb.notifier_call = qcom_wdt_restart;
+ ret = register_restart_handler(wdt-restart_nb);
+ if (ret) {
+ dev_err(pdev-dev, failed to setup restart handler\n);
+ watchdog_unregister_device(wdt-wdd);
+ return ret;
+ }
+
return 0;
}
--
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Re: [PATCH] pinctrl: qcom: use restart_notifier mechanism for ps_hold
On Thu, Sep 18, 2014 at 03:47:20PM -0700, Kumar Gala wrote: On Sep 18, 2014, at 3:32 PM, Josh Cartwright jo...@codeaurora.org wrote: By converting to the restart_notifier mechanism for restart, we allow for other mechanisms, like the watchdog, to be used for restart in the case where PS_HOLD has failed to reset the chip. Choose priority 128, as according to documentation, this mechanism is sufficient to restart the entire system?. Will we use a higher priority for watchdog? or how would we fail over to watchdog? The registered restart handlers are called in (descending) priority order. This driver registers as 128, but conceivably there could be some super-board-specific restart mechanism that can register itself as higher priority than this and it will be attempted first. If PS_HOLD doesn't work, the lower priority restart handlers will continue to be called, including the watchdog, which is registering with the lowest priority (0). -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] watchdog: qcom: add support for KPSS WDT
On Thu, Sep 18, 2014 at 07:41:17PM -0700, Guenter Roeck wrote:
On 09/18/2014 03:26 PM, Josh Cartwright wrote:
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
Hi Josh,
comments inline.
Thanks for taking a look!
[..]
+static int qcom_watchdog_probe(struct platform_device *pdev)
+{
+struct qcom_wdt *wdt;
+struct resource *res;
+u32 tmp;
+int ret;
+
+wdt = devm_kzalloc(pdev-dev, sizeof(*wdt), GFP_KERNEL);
+if (!wdt)
+return -ENOMEM;
+
+platform_set_drvdata(pdev, wdt);
+
+res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+wdt-base = devm_ioremap_resource(pdev-dev, res);
+if (IS_ERR(wdt-base))
+return PTR_ERR(wdt-base);
+
+ret = of_property_read_u32(pdev-dev.of_node, clock-frequency, tmp);
+if (ret) {
+dev_err(pdev-dev, unable to get clock-frequency\n);
+return ret;
+}
+
You might want to use a clock property here, and the complete sequence of
devm_clk_get
clk_prepare_enable
clk_disable_unprepare
clk_get_rate
Agreed. I think this would be ideal. I'll need to take a closer look
at how this thing is clocked, and how/if the clocks are currently
being modelled.
+wdt-freq = tmp;
+
+wdt-wdd.dev = pdev-dev;
+wdt-wdd.info = qcom_wdt_info;
+wdt-wdd.ops = qcom_wdt_ops;
+wdt-wdd.min_timeout = 1;
+wdt-wdd.max_timeout = 0x1000U / wdt-freq;
As written, wdt-freq can be 0, which results in a nice division by zero here.
Indeed. I'll add a check.
+watchdog_init_timeout(wdt-wdd, 0, pdev-dev);
That leaves you with no default timeout if timeout-sec is not set in
devicetree,
which if I understand the code correctly might result in an immediate reset.
Is this really what you want to happen ?
I think I'd like to handle timeout-sec being unspecified as an error at
probe. If someone explicitly sets timeout-sec = 0, then they get what
they ask for. I'll take another look to see how to make this happen.
+
+ret = watchdog_register_device(wdt-wdd);
+if (ret) {
+dev_err(pdev-dev, failed to register watchdog\n);
+return ret;
+}
+
+return 0;
+}
+
+static const struct of_device_id qcom_wdt_of_table[] = {
+{ .compatible = qcom,kpss-wdt-msm8960, },
+{ .compatible = qcom,kpss-wdt-apq8064, },
+{ .compatible = qcom,kpss-wdt-ipq8064, },
+{ },
+};
+MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
+
+static struct platform_driver qcom_watchdog_driver = {
+.probe = qcom_watchdog_probe,
No remove function ?
Yes, you don't need it, because the driver can only be built into the kernel,
but there is a practical impact: It means the driver must always be built
into the kernel even if the image is supposed to be used on different systems,
some of which may not support this specific watchdog.
Sure, you might say that you don't care about images supporting more than one
hardware, but the tendency seems to be multi-target images nowadays.
This was motivated by the addition of the restart_handler bits in patch
3. For some reason I was thinking there were race conditions between
module unloading/the restart_handler mechanism, but looking at it again,
I'm not so sure. Is it safe to implement these handlers in modules? If
so, I'll revisit this.
Thanks again,
Josh
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Re: [PATCH 3/3] watchdog: qcom: register a restart notifier
On Thu, Sep 18, 2014 at 07:47:54PM -0700, Guenter Roeck wrote:
On 09/18/2014 03:27 PM, Josh Cartwright wrote:
The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
resort mechanism for triggering chip reset. Usually, other restart
methods (such as PS_HOLD) are preferrable for issuing a more complete
reset of the chip. As such, keep the priority of the watchdog notifier
low.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
[..]
+static int qcom_wdt_restart(struct notifier_block *nb, unsigned long action,
+void *data)
+{
+struct qcom_wdt *wdt = container_of(nb, struct qcom_wdt, restart_nb);
+
+/*
+ * Trigger watchdog bite:
+ *Setup BITE_TIME to be very low, and enable WDT.
+ */
+mutex_lock(wdt-wdd.lock);
At this time you don't need to worry about locks.
Actually, this might be dangerous if the lock happens to be taken,
as it won't be released (there is no other code running anymore
when this function is called).
Ah, great. I'll drop the locking.
+writel_relaxed(0, wdt-base + WDT_EN);
+writel_relaxed(1, wdt-base + WDT_RST);
+writel_relaxed(0x31F3, wdt-base + WDT_BITE_TIME);
What is the magic here, ie what does 0x31F3 stand for ?
Nothing magic, it's just a reasonably low value to set the bite time
counter at. It also happens to be the value at reset.
+writel_relaxed(1, wdt-base + WDT_EN);
+mutex_unlock(wdt-wdd.lock);
+return NOTIFY_DONE;
+}
+
static int qcom_watchdog_probe(struct platform_device *pdev)
{
struct qcom_wdt *wdt;
@@ -121,6 +141,17 @@ static int qcom_watchdog_probe(struct platform_device
*pdev)
return ret;
}
+/*
+ * WDT restart notifier has priority 0 (use as a last resort)
+ */
+wdt-restart_nb.notifier_call = qcom_wdt_restart;
+ret = register_restart_handler(wdt-restart_nb);
+if (ret) {
+dev_err(pdev-dev, failed to setup restart handler\n);
+watchdog_unregister_device(wdt-wdd);
+return ret;
Sure you want to return an error here ? The watchdog itself is still working,
and this is supposed to be a restart method of last resort. Causing the driver
to fail loading because it can not register its restart handler seems to be
a bit aggressive.
It is a bit aggressive. I'll at least drop it to a dev_warn(); even
though it is a last resort, on some boards it's the only available
mechanism for reliable restart.
Thanks!
Josh
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Re: [PATCH] ARM: DT: ifc6410: Add board memory range.
On Wed, Sep 17, 2014 at 12:03:37PM -0700, Kumar Gala wrote:
On Sep 16, 2014, at 11:34 PM, Pramod Gurav pramod.gu...@smartplayin.com
wrote:
On Wednesday 17 September 2014 11:06 AM, Srinivas Kandagatla wrote:
This patch adds memory details of IFC6410 as this is necessary to
fix the in-correct memory start comming from ATAGs.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 90db8af..3287f12 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -4,6 +4,11 @@
model = Qualcomm APQ8064/IFC6410;
compatible = qcom,apq8064-ifc6410, qcom,apq8064;
+ memory{
Space before {?
+ device_type = memory;
+ reg = 0x8000 0x8000;
+ };
+
soc {
gsbi@1660 {
status = ok?;
Hmm, this doesn?t seem to work for me.
I don't see how it could with qcom_defconfig, as we set
CONFIG_ARM_ATAG_DTB_COMPAT. Is this patch fixing a real issue?
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Re: [PATCH] ARM: dts: qcom: Update msm8960 device trees
On Wed, May 28, 2014 at 01:27:23PM -0500, Kumar Gala wrote:
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8960-cdp.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
binding spec
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8960-cdp.dts | 6 ++
arch/arm/boot/dts/qcom-msm8960.dtsi| 165
+
2 files changed, 93 insertions(+), 78 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index a58fb88..8e77ed7 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -3,4 +3,10 @@
/ {
model = Qualcomm MSM8960 CDP;
compatible = qcom,msm8960-cdp, qcom,msm8960;
+
+ soc {
+ serial@1644 {
+ status = ok;
+ };
+ };
};
Is now the time put these serial nodes under a GSBI parent node?
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[PATCH] spmi: of: fixup generic SPMI devicetree binding example
The generic SPMI example was missing an equal sign in the assignment
of the #size-cells property.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
Documentation/devicetree/bindings/spmi/spmi.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spmi/spmi.txt
b/Documentation/devicetree/bindings/spmi/spmi.txt
index 462a42f..4bb10d1 100644
--- a/Documentation/devicetree/bindings/spmi/spmi.txt
+++ b/Documentation/devicetree/bindings/spmi/spmi.txt
@@ -26,7 +26,7 @@ Each child node must have one and only one 'reg' entry of
type SPMI_USID.
reg = ...;
#address-cells = 2;
- #size-cells 0;
+ #size-cells = 0;
child@0 {
compatible = ...;
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Re: [PATCH 1/2] mfd: pm8x41: add support for Qualcomm 8x41 PMICs
On Wed, Apr 23, 2014 at 04:36:22PM -0700, Courtney Cavin wrote:
On Wed, Apr 23, 2014 at 11:46:26PM +0200, Josh Cartwright wrote:
On Tue, Apr 22, 2014 at 05:31:49PM -0700, Courtney Cavin wrote:
[..]
One thing that I had meant to do is rename this thing. Nothing about
this is PM8841/PM8941 specific at all. It should apply equally to all
Qualcomm's PMICs which implement QPNP.
Perhaps a better name would be qcom-pmic-qpnp.
What's a QPNP? Really. I've heard you speak about it before as being a
definition of the register layout for interrupts, but I have no
documentation on it.
QPNP is effectively (as I explained before) a partitioning scheme for
dividing the SPMI extended register space up into logical pieces, and
set of fixed register locations/definitions within these regions, with
some of these regions specifically used for interrupt handling.
I would argue here from my understanding that this driver isn't specific
to QPNP either. With that in mind we could just go with
qcom-pmic-spmi. In fact just spmi-ext would not be incorrect, as
this driver has little to do with PMICs at all.
I'm actually not opposed to either of those suggested names.
My point here is that we can easily make this into something very
generic, but that only causes problems in the future when it's not
generic enough, and we have to add quirks.
Yes, this is why I'd still like to require having the specific PMIC
listed in the slave node's compatible string in front of a generic
one. Without a perfect crystal ball, it's the best we have.
If in the future Qualcomm releases a pm8A41, and it's qpnp, but not
spmi, or spmi, but not 'ext', then we need to either change this
driver dramatically, or write a new one. I like keeping this driver
name specific to what we know it supports. We can rename it in the
future if deemed appropriate, but I'd rather not make it something
that which turns out to be wrong at some later point.
I don't necessarily disagree with the strategy, however, if you take a
look at the downstream msm-3.10 tree[1], you'll see that there are
already quite a few other PMICs that could be made to leverage this
driver with likely no changes (downstream the equivalent is a dt node
tagged spmi-slave-container):
$ git grep spmi-slave-container arch/arm/boot/dts
arch/arm/boot/dts/qcom/msm-pm8019.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8019.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8110.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8110.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8226.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8226.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8841.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8841.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8916.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8916.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8941.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pm8941.dtsi: spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pma8084.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pma8084.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmd9635.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmd9635.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmi8962.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmi8962.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmiplutonium.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmiplutonium.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmplutonium.dtsi:
spmi-slave-container;
arch/arm/boot/dts/qcom/msm-pmplutonium.dtsi:
spmi-slave-container;
[..]
+static const struct of_device_id pm8x41_id_table[] = {
+ { .compatible = qcom,pm8841, },
+ { .compatible = qcom,pm8941, },
+ {},
+};
+MODULE_DEVICE_TABLE(of, pm8x41_id_table);
I'm thinking we should probably have a generic compatible entry as well,
qcom,pmic-qpnp or similar. We should still specify in the binding
that PMIC slaves specify a version-specific string as well as the
generic string. That is, a slave should have:
compatible = qcom,pm8841, qcom,pmic-qpnp;
...in case we would ever need to differentiate in the future.
(I recall that in a previous version I had done this, but I don't
remember why I had changed it..)
I gave this some thought but came to the conclusion that there is no
benefit of adding a generic compatible to a new binding. Please clarify
a use-case where this would be ... useful
Re: [PATCH 2/4] soc: qcom: Add GSBI driver
On Mon, Apr 21, 2014 at 12:30:42AM -0500, Andy Gross wrote:
The GSBI (General Serial Bus Interface) driver controls the overarching
configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM
functionality in various combinations.
Signed-off-by: Andy Gross agr...@codeaurora.org
[..]
+++ b/drivers/soc/qcom/qcom_gsbi.c
[..]
+#include linux/clk.h
+#include linux/err.h
+#include linux/interrupt.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_platform.h
+#include linux/platform_device.h
+
+#define GSBI_CTRL_REG0x
+#define GSBI_PROTOCOL_SHIFT 4
+
+struct gsbi_dev {
+ struct device *dev;
+ void __iomem*base;
You don't really need these.
+
+ struct clk *hclk;
+};
+
+static int gsbi_probe(struct platform_device *pdev)
+{
+ struct device_node *node = pdev-dev.of_node;
+ struct gsbi_dev *gsbi;
+ struct resource *res;
+ u32 mode;
+
+ gsbi = devm_kzalloc(pdev-dev, sizeof(*gsbi), GFP_KERNEL);
+ if (!gsbi)
+ return -ENOMEM;
+
+ gsbi-dev = pdev-dev;
+ platform_set_drvdata(pdev, gsbi);
+
+ if (of_property_read_u32(node, qcom,mode, mode)) {
+ dev_err(gsbi-dev, missing mode configuration\n);
+ return -EINVAL;
+ }
I'm wondering if you should really be a (very simple) pinctrl driver
proper.
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ gsbi-base = devm_ioremap_resource(gsbi-dev, res);
+ if (IS_ERR(gsbi-base))
+ return PTR_ERR(gsbi-base);
+
+ gsbi-hclk = devm_clk_get(gsbi-dev, iface);
+ if (IS_ERR(gsbi-hclk)) {
+ dev_err(gsbi-dev, Could not get core clock\n);
+ return PTR_ERR(gsbi-hclk);
+ }
+ clk_prepare_enable(gsbi-hclk);
+
+ writel_relaxed((mode GSBI_PROTOCOL_SHIFT), gsbi + GSBI_CTRL_REG);
Did you mean: gsbi-base + GSBI_CTRL_REG ?
+
+ /* make sure the gsbi control write is not reordered */
+ wmb();
+
+ return of_platform_populate(pdev-dev.of_node, NULL, NULL, pdev-dev);
+}
+
+static int gsbi_remove(struct platform_device *pdev)
+{
+ struct gsbi_dev *gsbi = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(gsbi-hclk);
+
+ return 0;
+}
+
+static struct of_device_id gsbi_dt_match[] = {
const
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[PATCH RFC] WIP: mfd: add support for Qualcomm RPM
The Resource Power Manager (RPM) is responsible managing SoC-wide
resources (clocks, regulators, etc) on MSM and other Qualcomm SoCs.
This driver provides an implementation of the message-RAM-based
communication protocol.
Note, this is a rewrite of the driver as it exists in the downstream
tree[1], making a few simplifying assumptions to clean it up, and adding
device tree support.
[1]:
https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/mach-msm/rpm.c?h=msm-3.4
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
This patch is intended to act as a starting point for discussions on how we
should proceed going forward supporting RPM. In particular, figuring out how
to model RPM and it's controlled resources in device tree.
I've chosen a path where a subnode logically separates the RPM resources; it's
intended each set of resources will be controlled by a single driver. For
example, an RPM-controlled regulator might consume two RPM_TYPE_REQ resources
described in 'reg'.
Effectively, this pushes the generic resource ID - SoC-specific resource
ID mapping out of the large data tables that exist in msm-3.4 into the device
tree. An alternative approach would be to still maintain the SoC-specific
tables, and have each node matched to it's resources using a unique compatible
string.
Any comments appreciated!
Thanks,
Josh
Documentation/devicetree/bindings/mfd/qcom,rpm.txt | 68 +
drivers/mfd/Kconfig| 9 +
drivers/mfd/Makefile | 1 +
drivers/mfd/qcom-rpm.c | 314 +
include/linux/mfd/qcom_rpm.h | 64 +
5 files changed, 456 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/qcom,rpm.txt
create mode 100644 drivers/mfd/qcom-rpm.c
create mode 100644 include/linux/mfd/qcom_rpm.h
diff --git a/Documentation/devicetree/bindings/mfd/qcom,rpm.txt
b/Documentation/devicetree/bindings/mfd/qcom,rpm.txt
new file mode 100644
index 000..617018f
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom,rpm.txt
@@ -0,0 +1,68 @@
+Qualcomm Resource Power Manager (RPM)
+
+This driver is used to interface with Resource Power Manager (RPM). The RPM is
+responsible managing SoC-wide resources (clocks, regulators, etc) on MSM and
+other Qualcomm chipsets.
+
+Required properties:
+
+- compatible: must be one of:
+ qcom,rpm-apq8064
+ qcom,rpm-ipq8064
+
+- reg: must contain two register specifiers, in the following order:
+ specifier 0: RPM Message RAM
+ specifier 1: IPC register
+
+- reg-names: must contain the following, in order:
+ msg_ram
+ ipc
+
+- interrupts: must contain the following three interrupt specifiers, in order:
+ specifier 0: RPM Acknowledgement Interrupt
+ specifier 1: Error Interrupt
+ specifier 2: Wakeup interrupt
+
+- interrupt-names: must contain the following, in order:
+ ack
+ err
+ wakeup
+
+- ipc-bit: bit written to the IPC register to notify RPM of a pending request
+
+- #address-cells: must be 3
+ cell 0: offset in ACK and REQ register spaces corresponding to the
register
+ cell 1: type field, one of RPM_TYPE_REQ (0) or RPM_TYPE_STATUS (1)
+ cell 2: indicates the selector bit to set when writing this register,
+ this cell is ignored (and should be set to zero) when type is
+ RPM_TYPE_STATUS
+
+Example:
+
+ #include dt-bindings/mfd/qcom_rpm.h
+
+ rpm@108000 {
+ compatible = qcom,rpm-ipq8064;
+ reg = 0x00108000 0x1000,
+ 0x02011008 0x4;
+ reg-names = msg_ram,
+ ipc;
+ interrupts = GIC_SPI 19 0,
+GIC_SPI 21 0,
+GIC_SPI 22 0;
+ interrupt-names = ack,
+ err,
+ wakeup;
+ ipc-bit = 2;
+
+ #address-cells = 3;
+ #size-cells = 0;
+
+ subnode {
+ compatible = ...;
+ reg = 464 RPM_TYPE_REQ 30,
+ 468 RPM_TYPE_REQ 30,
+ 118 RPM_TYPE_STATUS 0;
+ };
+ };
+
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 49bb445..b387ba9 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -497,6 +497,15 @@ config MFD_PM8XXX_IRQ
This is required to use certain other PM 8xxx features, such as GPIO
and MPP.
+config MFD_QCOM_RPM
+ tristate Qualcomm Resource Power Manager (RPM) driver
+ depends on (ARCH_QCOM || COMPILE_TEST)
+ help
+ The Resource Power Manager (RPM) is responsible managing SoC-wide
+ resources (clocks, regulators, etc) on MSM and other Qualcomm SoCs.
+ This driver provides an implementation of the message-RAM
Re: [PATCH 1/9] crypto: qce: Add core driver implementation
Hey Stanimir-
Just a few comments/questions from a quick scan of your patchset:
On Thu, Apr 03, 2014 at 07:17:58PM +0300, Stanimir Varbanov wrote:
[..]
+++ b/drivers/crypto/qce/core.c
[..]
+
+static struct qce_algo_ops qce_ops[] = {
+ {
+ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
+ .register_alg = qce_ablkcipher_register,
+ },
+ {
+ .type = CRYPTO_ALG_TYPE_AHASH,
+ .register_alg = qce_ahash_register,
+ },
+};
+
+static void qce_unregister_algs(struct qce_device *qce)
+{
+ struct qce_alg_template *tmpl, *n;
+
+ list_for_each_entry_safe(tmpl, n, qce-alg_list, entry) {
+ if (tmpl-crypto_alg_type == CRYPTO_ALG_TYPE_AHASH)
+ crypto_unregister_ahash(tmpl-alg.ahash);
+ else
+ crypto_unregister_alg(tmpl-alg.crypto);
Why no 'unregister_alg' member in qce_algo_ops?
+
+ list_del(tmpl-entry);
+ kfree(tmpl);
+ }
+}
+
+static int qce_register_algs(struct qce_device *qce)
+{
+ struct qce_algo_ops *ops;
+ int i, rc = -ENODEV;
+
+ for (i = 0; i ARRAY_SIZE(qce_ops); i++) {
+ ops = qce_ops[i];
+ ops-async_req_queue = qce_async_request_queue;
+ ops-async_req_done = qce_async_request_done;
Why not set these statically?
+ rc = ops-register_alg(qce, ops);
+ if (rc)
+ break;
+ }
+
+ if (rc)
+ qce_unregister_algs(qce);
+
+ return rc;
+}
[..]
+static int qce_get_version(struct qce_device *qce)
+{
+ u32 major, minor, step;
+ u32 val;
+
+ val = readl(qce-base + REG_VERSION);
+ major = (val CORE_MAJOR_REV_MASK) CORE_MAJOR_REV;
+ minor = (val CORE_MINOR_REV_MASK) CORE_MINOR_REV;
+ step = (val CORE_STEP_REV_MASK) CORE_STEP_REV;
+
+ /*
+ * the driver does not support v5 with minor 0 because it has special
+ * alignment requirements.
+ */
+ if (major QCE_MAJOR_VERSION5 minor == 0)
+ return -ENODEV;
+
+ qce-burst_size = QCE_BAM_BURST_SIZE;
+ qce-pipe_pair_index = 1;
+
+ dev_info(qce-dev, Crypto device found, version %d.%d.%d\n,
+ major, minor, step);
I'd suggest dev_dbg(). Kernel boot is chatty enough.
[..]
+static int qce_clks_enable(struct qce_device *qce, int enable)
+{
+ int rc = 0;
+ int i;
+
+ for (i = 0; i QCE_CLKS_NUM; i++) {
+ if (enable)
+ rc = clk_prepare_enable(qce-clks[i]);
+ else
+ clk_disable_unprepare(qce-clks[i]);
+
+ if (rc)
+ break;
+ }
+
+ if (rc)
+ do
+ clk_disable_unprepare(qce-clks[i]);
+ while (--i = 0);
+
+ return rc;
+}
See my below comment about lumping clocks together.
[..]
+static int qce_crypto_remove(struct platform_device *pdev)
+{
+ struct qce_device *qce = platform_get_drvdata(pdev);
+
+ cancel_work_sync(qce-queue_work);
+ destroy_workqueue(qce-queue_wq);
+ tasklet_kill(qce-done_tasklet);
+ qce_unregister_algs(qce);
+ qce_dma_release(qce-dma);
+ qce_clks_enable(qce, 0);
qce_clks_enable(qce, 0) is really confusingI'd suggest creating
separate qce_clks_enable() and qce_clks_disable() functions.
[..]
+static const struct of_device_id qce_crypto_of_match[] = {
+ { .compatible = qcom,crypto-v5.1, },
+ {}
+};
MODULE_DEVICE_TABLE()?
[..]
+++ b/drivers/crypto/qce/core.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CORE_H_
+#define _CORE_H_
+
+static const char * const clk_names[] = {
+ core, /* GCC_CE_CLK */
+ iface,/* GCC_CE_AHB_CLK */
+ bus, /* GCC_CE_AXI_CLK */
+};
You probably don't want this in a header file, as now each compilation
unit will have a copy :(.
Lumping all the clocks together assumes that you will only ever have all
clocks enabled, or all clocks disabled, are you sure that's what you
want?
[..]
+struct qce_algo_ops {
+ u32 type;
+ int (*register_alg)(struct qce_device *qce, struct qce_algo_ops *ops);
+ int (*async_req_queue)(struct qce_device *qce,
+struct crypto_async_request *req);
+ void (*async_req_done)(struct qce_device *qce, int ret);
What is the relationship between
Re: [PATCH] Input: pmic8xxx-pwrkey - Set sane default for debounce time
On Mon, Mar 31, 2014 at 11:14:24AM -0700, Stephen Boyd wrote: If the debounce time is 0 our usage of ilog2() later on in this driver will cause undefined behavior. If CONFIG_OF=n this fact is evident to the compiler, and it emits a call to ilog2_NaN() which doesn't exist. Fix this by setting a sane default for debounce. Reported-by: Arnd Bergmann a...@arndb.de Signed-off-by: Stephen Boyd sb...@codeaurora.org --- drivers/input/misc/pmic8xxx-pwrkey.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/input/misc/pmic8xxx-pwrkey.c b/drivers/input/misc/pmic8xxx-pwrkey.c index 1cb8fda7a166..27add04676e1 100644 --- a/drivers/input/misc/pmic8xxx-pwrkey.c +++ b/drivers/input/misc/pmic8xxx-pwrkey.c @@ -92,7 +92,7 @@ static int pmic8xxx_pwrkey_probe(struct platform_device *pdev) bool pull_up; if (of_property_read_u32(pdev-dev.of_node, debounce, kpd_delay)) - kpd_delay = 0; + kpd_delay = 15625; Should debounce even be optional? I'm wondering if we should just make it required... At the very least this default value should be documented in the DT binding. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 2/2] i2c: New bus driver for the Qualcomm QUP I2C controller
On Thu, Mar 13, 2014 at 07:07:43PM -0700, Bjorn Andersson wrote:
This bus driver supports the QUP i2c hardware controller in the Qualcomm SOCs.
The Qualcomm Universal Peripheral Engine (QUP) is a general purpose data path
engine with input/output FIFOs and an embedded i2c mini-core. The driver
supports FIFO mode (for low bandwidth applications) and block mode (interrupt
generated for each block-size data transfer).
Cc: Andy Gross agr...@codeaurora.org
Cc: Stephen Boyd sb...@codeaurora.org
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
+++ b/drivers/i2c/busses/i2c-qup.c
[..]
+static int qup_i2c_xfer(struct i2c_adapter *adap,
+ struct i2c_msg msgs[],
+ int num)
+{
+ struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
+ int ret, idx;
+
+ ret = pm_runtime_get_sync(qup-dev);
+ if (IS_ERR_VALUE(ret))
+ goto out;
General i2c question: is there a reason why the core isn't responsible
for ensuring a device is not suspended before invoking -master_xfer
(and smbus_xfer)?
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[PATCH v3 6/6] mfd: devicetree: bindings: add pm8xxx RTC description
The PM8xxx family of PMICs contain an RTC. This RTC is described as a
subnode of the PM8xxx. Document these bindings, and replace the pwrkey
node in the example with the RTC, which is now described in this
document.
While we're here, add a short description to the device tree bindings
describing what the the PM8xxx devices are and how they are expected to
be used.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
Andrew-
Here's a new 6/6. Like mentioned earlier, this is based on the current MFD
document that's in Lee's tree pending for 3.15. It may be best to get yours
and Rob's Ack and have Lee take it through his tree.
Thanks,
Josh
.../devicetree/bindings/mfd/qcom,pm8xxx.txt| 45 +++---
1 file changed, 39 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt
b/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt
index e3fe625..03518dc 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt
+++ b/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt
@@ -1,6 +1,9 @@
Qualcomm PM8xxx PMIC multi-function devices
-PROPERTIES
+The PM8xxx family of Power Management ICs are used to provide regulated
+voltages and other various functionality to Qualcomm SoCs.
+
+= PROPERTIES
- compatible:
Usage: required
@@ -45,7 +48,37 @@ PROPERTIES
Value type: empty
Definition: identifies this node as an interrupt controller
-EXAMPLE
+= SUBCOMPONENTS
+
+The PMIC contains multiple independent functions, each described in a subnode.
+The below bindings specify the set of valid subnodes.
+
+== Real-Time Clock
+
+- compatible:
+ Usage: required
+ Value type: string
+ Definition: must be one of:
+ qcom,pm8058-rtc
+ qcom,pm8921-rtc
+
+- reg:
+ Usage: required
+ Value type: prop-encoded-array
+ Definition: single entry specifying the base address of the RTC
registers
+
+- interrupts:
+ Usage: required
+ Value type: prop-encoded-array
+ Definition: single entry specifying the RTC's alarm interrupt
+
+- allow-set-time:
+ Usage: optional
+ Value type: empty
+ Definition: indicates that the setting of RTC time is allowed by
+ the host CPU
+
+= EXAMPLE
pmicintc: pmic@0 {
compatible = qcom,pm8921;
@@ -55,9 +88,9 @@ EXAMPLE
#address-cells = 1;
#size-cells = 0;
- pwrkey {
- compatible = qcom,pm8921-pwrkey;
- interrupt-parent = pmicintc;
- interrupts = 50 1, 51 1;
+ rtc@11d {
+ compatible = qcom,pm8921-rtc;
+ reg = 0x11d;
+ interrupts = 0x27 0;
};
};
--
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Re: [PATCH 6/6] documentation: bindings: document PMIC8921/8058 RTC
Hey Rob- Thanks for the reply. On Mon, Mar 10, 2014 at 10:35:25AM -0500, Rob Herring wrote: On Wed, Mar 5, 2014 at 6:00 PM, Josh Cartwright jo...@codeaurora.org wrote: On Wed, Mar 05, 2014 at 12:58:55PM -0800, Stephen Boyd wrote: On 03/05/14 11:29, Josh Cartwright wrote: +- interrupts: interrupt list for the RTC, must contain a single interrupt + specifier for the alarm interrupt +- interrupt-names: corresponding interrupt names for the interrupts listed in + the 'interrupts' property, must contain: + alarm - summary interrupt for PMIC peripherals optional interrupt-names? It isn't clear to me why these should be made optional, I hope Rob provides some clarification in the sdhci-msm thread. Because reg and interrupt names are relatively new and reluctantly added by DT maintainers. Personally, I think it was a mistake and it is simply Linux specific information leaking into the DT, but it did make transition to DT easier. I don't necessarily buy the Linux-specific argument in general. If a devices' datasheet clearly gives names to register regions and interrupts, what about reflecting these names in the bindings is Linux-specific? Now, there are probably abuses of this, where the reg-names and interrupt-names are abused to ensure driver compatibility with devices described in board files, and only in that case will I agree is Linux-specific and should be strongly discouraged. The requirement is still the ordering of reg and interrupts fields must be defined and you cannot rely on the names to define the order. Should this requirement also exist for other foo-names properties? It is quite pointless here since you only have 1 field. Indeed in the interrupt case it is worthless, as there is only one alarm interrupt. However for registers I do plan to extend this binding in the future to document a newer RTC which does split registers across multiple named address regions. Thanks again, Josh -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/6] rtc: make the pm8xxx RTC driver usable
This patchset is based on Stephen Boyd's PM8921 modernization/cleanups[1], and allows for this RTC driver to be usable again. Changes since v1: * Further style cleanups as suggested by Stephen Boyd * Dropped the use of reg-names/interrupt-names properties entirely [1]: http://lkml.kernel.org/g/1393441166-32692-1-git-send-email-sb...@codeaurora.org Josh Cartwright (6): rtc: pm8xxx: fixup checkpatch/style issues rtc: pm8xxx: use regmap API for register accesses rtc: pm8xxx: use devm_request_any_context_irq rtc: pm8xxx: add support for devicetree rtc: pm8xxx: move device_init_wakeup() before rtc_register documentation: bindings: document PMIC8921/8058 RTC .../devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt| 21 ++ drivers/rtc/rtc-pm8xxx.c | 284 ++--- include/linux/mfd/pm8xxx/rtc.h | 25 -- 3 files changed, 150 insertions(+), 180 deletions(-) create mode 100644 Documentation/devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt delete mode 100644 include/linux/mfd/pm8xxx/rtc.h -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/6] rtc: pm8xxx: use regmap API for register accesses
On Mon, Mar 10, 2014 at 01:47:41PM -0700, Andrew Morton wrote: On Mon, 10 Mar 2014 13:44:45 -0500 Josh Cartwright jo...@codeaurora.org wrote: Now that the parent mfd driver has been made to work again, and has been reworked to create a regmap instance intended for it's children to use, rework the pm8xxx driver to use the regmap API for it's register accesses. Do we need a depends on REGMAP in Kconfig? Good question. This driver already gets the REGMAP dependency through it's parent (MFD_PM8XXX), which does 'select REGMAP'. I recall there being some history as to why individual drivers shouldn't explicitly depend on REGMAP, as it's the parent drivers/subsystem responsibility to select it when needed, however I can't recall details. Perhaps it's due to REGMAP not being a user-selectable option. (FWIW, I did force a build of this driver with !REGMAP, and it builds just fine with the regmap_write()/_read() stubs, but of course it wouldn't do anything meaningful at runtime) Thanks, Josh -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 6/6] documentation: bindings: document PMIC8921/8058 RTC
On Mon, Mar 10, 2014 at 04:22:51PM -0500, Rob Herring wrote: On Mon, Mar 10, 2014 at 1:44 PM, Josh Cartwright jo...@codeaurora.org wrote: This RTC is found on the Qualcomm 8921 and 8058 PMICs. Signed-off-by: Josh Cartwright jo...@codeaurora.org --- .../devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt | 21 + 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt diff --git a/Documentation/devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt b/Documentation/devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt new file mode 100644 index 000..3eaa582 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt @@ -0,0 +1,21 @@ +* Real-Time Clock for Qualcomm 8058/8921 PMICs + +Required properties: +- compatible: should be one of the following. +* qcom,pm8058-rtc +* qcom,pm8921-rtc +- reg: base address of the register region Wait a second. This is all part of an MFD device. I think this whole binding does not make sense on it's own. The DT should describe the PMIC, not necessarily some sub-component of it. Perhaps there are sub nodes of the PMIC node, but that would be all part of the PMIC binding. Having sub drivers for an MFD is really a Linux problem that doesn't belong in DT. Okay, this makes sense, I can move this documentation to Documentation/bindings/mfd/qcom,pm8xxx.txt where the PMIC binding currently is. Note that this does introduce a dependency on Lee Jones' mfd tree, where DT support for the parent pm8921 driver is pending for 3.15. Andrew, how would you prefer I proceed? Would you like me to respin this patch? The whole series? An incremental patch? Thanks, Josh -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 6/6] documentation: bindings: document PMIC8921/8058 RTC
On Wed, Mar 05, 2014 at 05:31:27PM -0800, Stephen Boyd wrote: On 03/05/14 16:00, Josh Cartwright wrote: On Wed, Mar 05, 2014 at 12:58:55PM -0800, Stephen Boyd wrote: On 03/05/14 11:29, Josh Cartwright wrote: diff --git a/Documentation/devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt b/Documentation/devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt new file mode 100644 index 000..699bd30 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt @@ -0,0 +1,29 @@ +* Real-Time Clock for Qualcomm 8058/8921 PMICs + +Required properties: +- compatible: should be one of the following. +* qcom,pm8058-rtc +* qcom,pm8921-rtc +- reg: base address of the register region +- reg-names: corresponding reg names for the regions listed in the 'reg' + property, must contain: + rtc_base - base of the RTC register region optional reg-names? +- interrupts: interrupt list for the RTC, must contain a single interrupt + specifier for the alarm interrupt +- interrupt-names: corresponding interrupt names for the interrupts listed in + the 'interrupts' property, must contain: + alarm - summary interrupt for PMIC peripherals optional interrupt-names? It isn't clear to me why these should be made optional, I hope Rob provides some clarification in the sdhci-msm thread. Looks like the driver isn't using either of these properties, so I'm not sure why they're needed. Maybe they should just be removed. The driver does make use of platform_get_irq_byname(pdev, alarm), and I expect to make use of platform_get_resource_byname(pdev, IORESOURCE_REG, rtc_base) in the near future. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/6] rtc: pm8xxx: use devm_request_any_context_irq
Make use of the devm_* variant of request_any_context_irq to allow for
elimination of remove().
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/rtc/rtc-pm8xxx.c | 18 --
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c
index f6d140a..ed3fe83 100644
--- a/drivers/rtc/rtc-pm8xxx.c
+++ b/drivers/rtc/rtc-pm8xxx.c
@@ -427,9 +427,10 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev)
}
/* Request the alarm IRQ */
- rc = request_any_context_irq(rtc_dd-rtc_alarm_irq,
-pm8xxx_alarm_trigger, IRQF_TRIGGER_RISING,
-pm8xxx_rtc_alarm, rtc_dd);
+ rc = devm_request_any_context_irq(pdev-dev, rtc_dd-rtc_alarm_irq,
+ pm8xxx_alarm_trigger,
+ IRQF_TRIGGER_RISING,
+ pm8xxx_rtc_alarm, rtc_dd);
if (rc 0) {
dev_err(pdev-dev, Request IRQ failed (%d)\n, rc);
return rc;
@@ -442,16 +443,6 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev)
return 0;
}
-static int pm8xxx_rtc_remove(struct platform_device *pdev)
-{
- struct pm8xxx_rtc *rtc_dd = platform_get_drvdata(pdev);
-
- device_init_wakeup(pdev-dev, 0);
- free_irq(rtc_dd-rtc_alarm_irq, rtc_dd);
-
- return 0;
-}
-
#ifdef CONFIG_PM_SLEEP
static int pm8xxx_rtc_resume(struct device *dev)
{
@@ -480,7 +471,6 @@ static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
static struct platform_driver pm8xxx_rtc_driver = {
.probe = pm8xxx_rtc_probe,
- .remove = pm8xxx_rtc_remove,
.driver = {
.name = PM8XXX_RTC_DEV_NAME,
.owner = THIS_MODULE,
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[PATCH 2/6] rtc: pm8xxx: use regmap API for register accesses
Now that the parent mfd driver has been made to work again, and has been
reworked to create a regmap instance intended for it's children to use,
rework the pm8xxx driver to use the regmap API for it's register
accesses.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/rtc/rtc-pm8xxx.c | 145 +++
1 file changed, 57 insertions(+), 88 deletions(-)
diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c
index 772b070..f6d140a 100644
--- a/drivers/rtc/rtc-pm8xxx.c
+++ b/drivers/rtc/rtc-pm8xxx.c
@@ -13,11 +13,12 @@
#include linux/module.h
#include linux/init.h
#include linux/rtc.h
+#include linux/platform_device.h
#include linux/pm.h
+#include linux/regmap.h
#include linux/slab.h
#include linux/spinlock.h
-#include linux/mfd/pm8xxx/core.h
#include linux/mfd/pm8xxx/rtc.h
@@ -37,6 +38,7 @@
/**
* struct pm8xxx_rtc - rtc driver internal structure
* @rtc: rtc device for this driver.
+ * @regmap:regmap used to access RTC registers
* @rtc_alarm_irq: rtc alarm irq number.
* @rtc_base: address of rtc control register.
* @rtc_read_base: base address of read registers.
@@ -48,6 +50,7 @@
*/
struct pm8xxx_rtc {
struct rtc_device *rtc;
+ struct regmap *regmap;
int rtc_alarm_irq;
int rtc_base;
int rtc_read_base;
@@ -59,44 +62,6 @@ struct pm8xxx_rtc {
};
/*
- * The RTC registers need to be read/written one byte at a time. This is a
- * hardware limitation.
- */
-static int pm8xxx_read_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val,
- int base, int count)
-{
- int i, rc;
- struct device *parent = rtc_dd-rtc_dev-parent;
-
- for (i = 0; i count; i++) {
- rc = pm8xxx_readb(parent, base + i, rtc_val[i]);
- if (rc 0) {
- dev_err(rtc_dd-rtc_dev, PMIC read failed\n);
- return rc;
- }
- }
-
- return 0;
-}
-
-static int pm8xxx_write_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val,
- int base, int count)
-{
- int i, rc;
- struct device *parent = rtc_dd-rtc_dev-parent;
-
- for (i = 0; i count; i++) {
- rc = pm8xxx_writeb(parent, base + i, rtc_val[i]);
- if (rc 0) {
- dev_err(rtc_dd-rtc_dev, PMIC write failed\n);
- return rc;
- }
- }
-
- return 0;
-}
-
-/*
* Steps to write the RTC registers.
* 1. Disable alarm if enabled.
* 2. Write 0x00 to LSB.
@@ -107,7 +72,7 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct
rtc_time *tm)
{
int rc, i;
unsigned long secs, irq_flags;
- u8 value[NUM_8_BIT_RTC_REGS], reg = 0, alarm_enabled = 0, ctrl_reg;
+ u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, ctrl_reg;
struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
rtc_tm_to_time(tm, secs);
@@ -125,9 +90,8 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct
rtc_time *tm)
if (ctrl_reg PM8xxx_RTC_ALARM_ENABLE) {
alarm_enabled = 1;
ctrl_reg = ~PM8xxx_RTC_ALARM_ENABLE;
- rc = pm8xxx_write_wrapper(rtc_dd, ctrl_reg, rtc_dd-rtc_base,
- 1);
- if (rc 0) {
+ rc = regmap_write(rtc_dd-regmap, rtc_dd-rtc_base, ctrl_reg);
+ if (rc) {
dev_err(dev, Write to RTC control register failed\n);
goto rtc_rw_fail;
}
@@ -137,33 +101,31 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct
rtc_time *tm)
}
/* Write 0 to Byte[0] */
- reg = 0;
- rc = pm8xxx_write_wrapper(rtc_dd, reg, rtc_dd-rtc_write_base, 1);
- if (rc 0) {
+ rc = regmap_write(rtc_dd-regmap, rtc_dd-rtc_write_base, 0);
+ if (rc) {
dev_err(dev, Write to RTC write data register failed\n);
goto rtc_rw_fail;
}
/* Write Byte[1], Byte[2], Byte[3] */
- rc = pm8xxx_write_wrapper(rtc_dd, value + 1,
- rtc_dd-rtc_write_base + 1, 3);
- if (rc 0) {
+ rc = regmap_bulk_write(rtc_dd-regmap, rtc_dd-rtc_write_base + 1,
+ value[1], sizeof(value) - 1);
+ if (rc) {
dev_err(dev, Write to RTC write data register failed\n);
goto rtc_rw_fail;
}
/* Write Byte[0] */
- rc = pm8xxx_write_wrapper(rtc_dd, value, rtc_dd-rtc_write_base, 1);
- if (rc 0) {
+ rc = regmap_write(rtc_dd-regmap, rtc_dd-rtc_write_base, value[0]);
+ if (rc) {
dev_err(dev, Write to RTC write data register failed\n);
goto rtc_rw_fail;
}
if (alarm_enabled) {
ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
- rc
[PATCH 1/6] rtc: pm8xxx: fixup checkpatch/style issues
Before performing additional cleanups to this driver, do the easy
cleanups first.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/rtc/rtc-pm8xxx.c | 88 +---
1 file changed, 45 insertions(+), 43 deletions(-)
diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c
index bd76ffe9..772b070 100644
--- a/drivers/rtc/rtc-pm8xxx.c
+++ b/drivers/rtc/rtc-pm8xxx.c
@@ -53,7 +53,7 @@ struct pm8xxx_rtc {
int rtc_read_base;
int rtc_write_base;
int alarm_rw_base;
- u8 ctrl_reg;
+ u8 ctrl_reg;
struct device *rtc_dev;
spinlock_t ctrl_reg_lock;
};
@@ -63,7 +63,7 @@ struct pm8xxx_rtc {
* hardware limitation.
*/
static int pm8xxx_read_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val,
- int base, int count)
+ int base, int count)
{
int i, rc;
struct device *parent = rtc_dd-rtc_dev-parent;
@@ -80,7 +80,7 @@ static int pm8xxx_read_wrapper(struct pm8xxx_rtc *rtc_dd, u8
*rtc_val,
}
static int pm8xxx_write_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val,
- int base, int count)
+ int base, int count)
{
int i, rc;
struct device *parent = rtc_dd-rtc_dev-parent;
@@ -126,15 +126,15 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct
rtc_time *tm)
alarm_enabled = 1;
ctrl_reg = ~PM8xxx_RTC_ALARM_ENABLE;
rc = pm8xxx_write_wrapper(rtc_dd, ctrl_reg, rtc_dd-rtc_base,
- 1);
+ 1);
if (rc 0) {
- dev_err(dev, Write to RTC control register
- failed\n);
+ dev_err(dev, Write to RTC control register failed\n);
goto rtc_rw_fail;
}
rtc_dd-ctrl_reg = ctrl_reg;
- } else
+ } else {
spin_unlock_irqrestore(rtc_dd-ctrl_reg_lock, irq_flags);
+ }
/* Write 0 to Byte[0] */
reg = 0;
@@ -146,7 +146,7 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct
rtc_time *tm)
/* Write Byte[1], Byte[2], Byte[3] */
rc = pm8xxx_write_wrapper(rtc_dd, value + 1,
- rtc_dd-rtc_write_base + 1, 3);
+ rtc_dd-rtc_write_base + 1, 3);
if (rc 0) {
dev_err(dev, Write to RTC write data register failed\n);
goto rtc_rw_fail;
@@ -162,10 +162,9 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct
rtc_time *tm)
if (alarm_enabled) {
ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
rc = pm8xxx_write_wrapper(rtc_dd, ctrl_reg, rtc_dd-rtc_base,
- 1);
+ 1);
if (rc 0) {
- dev_err(dev, Write to RTC control register
- failed\n);
+ dev_err(dev, Write to RTC control register failed\n);
goto rtc_rw_fail;
}
rtc_dd-ctrl_reg = ctrl_reg;
@@ -186,7 +185,7 @@ static int pm8xxx_rtc_read_time(struct device *dev, struct
rtc_time *tm)
struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
rc = pm8xxx_read_wrapper(rtc_dd, value, rtc_dd-rtc_read_base,
- NUM_8_BIT_RTC_REGS);
+NUM_8_BIT_RTC_REGS);
if (rc 0) {
dev_err(dev, RTC read data register failed\n);
return rc;
@@ -204,7 +203,8 @@ static int pm8xxx_rtc_read_time(struct device *dev, struct
rtc_time *tm)
if (unlikely(reg value[0])) {
rc = pm8xxx_read_wrapper(rtc_dd, value,
- rtc_dd-rtc_read_base, NUM_8_BIT_RTC_REGS);
+rtc_dd-rtc_read_base,
+NUM_8_BIT_RTC_REGS);
if (rc 0) {
dev_err(dev, RTC read data register failed\n);
return rc;
@@ -222,8 +222,8 @@ static int pm8xxx_rtc_read_time(struct device *dev, struct
rtc_time *tm)
}
dev_dbg(dev, secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n,
- secs, tm-tm_hour, tm-tm_min, tm-tm_sec,
- tm-tm_mday, tm-tm_mon, tm-tm_year);
+ secs, tm-tm_hour, tm-tm_min, tm-tm_sec,
+ tm-tm_mday, tm-tm_mon, tm-tm_year);
return 0;
}
@@ -245,7 +245,7 @@ static int pm8xxx_rtc_set_alarm(struct device *dev, struct
rtc_wkalrm *alarm)
spin_lock_irqsave(rtc_dd-ctrl_reg_lock, irq_flags);
rc = pm8xxx_write_wrapper(rtc_dd
[PATCH 5/6] rtc: pm8xxx: move device_init_wakeup() before rtc_register
Setup wakeup capability before rtc_register to ensure the rtc class core properly sets up our 'wakealarm' sysfs attribute. Signed-off-by: Josh Cartwright jo...@codeaurora.org --- drivers/rtc/rtc-pm8xxx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c index cb5576f..761be65 100644 --- a/drivers/rtc/rtc-pm8xxx.c +++ b/drivers/rtc/rtc-pm8xxx.c @@ -422,6 +422,8 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, rtc_dd); + device_init_wakeup(pdev-dev, 1); + /* Register the RTC device */ rtc_dd-rtc = devm_rtc_device_register(pdev-dev, pm8xxx_rtc, pm8xxx_rtc_ops, THIS_MODULE); @@ -441,8 +443,6 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev) return rc; } - device_init_wakeup(pdev-dev, 1); - dev_dbg(pdev-dev, Probe success !!\n); return 0; -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 6/6] documentation: bindings: document PMIC8921/8058 RTC
This RTC is found on the Qualcomm 8921 and 8058 PMICs.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
.../devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt| 29 ++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt
diff --git a/Documentation/devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt
b/Documentation/devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt
new file mode 100644
index 000..699bd30
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/qcom,pm8xxx-rtc.txt
@@ -0,0 +1,29 @@
+* Real-Time Clock for Qualcomm 8058/8921 PMICs
+
+Required properties:
+- compatible: should be one of the following.
+* qcom,pm8058-rtc
+* qcom,pm8921-rtc
+- reg: base address of the register region
+- reg-names: corresponding reg names for the regions listed in the 'reg'
+ property, must contain:
+ rtc_base - base of the RTC register region
+- interrupts: interrupt list for the RTC, must contain a single interrupt
+ specifier for the alarm interrupt
+- interrupt-names: corresponding interrupt names for the interrupts listed in
+ the 'interrupts' property, must contain:
+ alarm - summary interrupt for PMIC peripherals
+
+Option properties:
+- linux,allow-set-time: indicates that the setting of RTC time is allowed by
+the host CPU
+
+Example:
+
+ rtc {
+ compatible = qcom,pm8921-rtc;
+ reg = 0x11D;
+ reg-names = rtc_base;
+ interrupts = 0x27 0;
+ interrupt-names = alarm;
+ };
--
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[PATCH 4/6] rtc: pm8xxx: add support for devicetree
Add support for describing the PM8921/PM8058 RTC in device tree.
Additionally:
- drop support for describing the RTC using platform data,
as there are no current in tree users who do so.
- make allow_set_time a device-specific flag, instead of mucking
with the rtc_ops
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/rtc/rtc-pm8xxx.c | 54 +++---
include/linux/mfd/pm8xxx/rtc.h | 25 ---
2 files changed, 30 insertions(+), 49 deletions(-)
delete mode 100644 include/linux/mfd/pm8xxx/rtc.h
diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c
index ed3fe83..cb5576f 100644
--- a/drivers/rtc/rtc-pm8xxx.c
+++ b/drivers/rtc/rtc-pm8xxx.c
@@ -9,7 +9,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
+#include linux/of.h
#include linux/module.h
#include linux/init.h
#include linux/rtc.h
@@ -19,9 +19,6 @@
#include linux/slab.h
#include linux/spinlock.h
-#include linux/mfd/pm8xxx/rtc.h
-
-
/* RTC Register offsets from RTC CTRL REG */
#define PM8XXX_ALARM_CTRL_OFFSET 0x01
#define PM8XXX_RTC_WRITE_OFFSET0x02
@@ -39,6 +36,7 @@
* struct pm8xxx_rtc - rtc driver internal structure
* @rtc: rtc device for this driver.
* @regmap:regmap used to access RTC registers
+ * @allow_set_time:indicates whether writing to the RTC is allowed
* @rtc_alarm_irq: rtc alarm irq number.
* @rtc_base: address of rtc control register.
* @rtc_read_base: base address of read registers.
@@ -51,6 +49,7 @@
struct pm8xxx_rtc {
struct rtc_device *rtc;
struct regmap *regmap;
+ bool allow_set_time;
int rtc_alarm_irq;
int rtc_base;
int rtc_read_base;
@@ -75,6 +74,9 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct
rtc_time *tm)
u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, ctrl_reg;
struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
+ if (!rtc_dd-allow_set_time)
+ return -EACCES;
+
rtc_tm_to_time(tm, secs);
for (i = 0; i NUM_8_BIT_RTC_REGS; i++) {
@@ -291,8 +293,9 @@ rtc_rw_fail:
return rc;
}
-static struct rtc_class_ops pm8xxx_rtc_ops = {
+static const struct rtc_class_ops pm8xxx_rtc_ops = {
.read_time = pm8xxx_rtc_read_time,
+ .set_time = pm8xxx_rtc_set_time,
.set_alarm = pm8xxx_rtc_set_alarm,
.read_alarm = pm8xxx_rtc_read_alarm,
.alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
@@ -346,18 +349,26 @@ rtc_alarm_handled:
return IRQ_HANDLED;
}
+/*
+ * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
+ */
+static const struct of_device_id pm8xxx_id_table[] = {
+ { .compatible = qcom,pm8921-rtc, .data = (void *) 0x11D },
+ { .compatible = qcom,pm8058-rtc, .data = (void *) 0x1E8 },
+ { },
+};
+MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
+
static int pm8xxx_rtc_probe(struct platform_device *pdev)
{
int rc;
unsigned int ctrl_reg;
- bool rtc_write_enable = false;
struct pm8xxx_rtc *rtc_dd;
- struct resource *rtc_resource;
- const struct pm8xxx_rtc_platform_data *pdata =
- dev_get_platdata(pdev-dev);
+ const struct of_device_id *match;
- if (pdata != NULL)
- rtc_write_enable = pdata-rtc_write_enable;
+ match = of_match_node(pm8xxx_id_table, pdev-dev.of_node);
+ if (!match)
+ return -ENXIO;
rtc_dd = devm_kzalloc(pdev-dev, sizeof(*rtc_dd), GFP_KERNEL);
if (rtc_dd == NULL)
@@ -372,20 +383,16 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev)
return -ENXIO;
}
- rtc_dd-rtc_alarm_irq = platform_get_irq(pdev, 0);
+ rtc_dd-rtc_alarm_irq = platform_get_irq_byname(pdev, alarm);
if (rtc_dd-rtc_alarm_irq 0) {
dev_err(pdev-dev, Alarm IRQ resource absent!\n);
return -ENXIO;
}
- rtc_resource = platform_get_resource_byname(pdev, IORESOURCE_IO,
- pmic_rtc_base);
- if (!(rtc_resource rtc_resource-start)) {
- dev_err(pdev-dev, RTC IO resource absent!\n);
- return -ENXIO;
- }
+ rtc_dd-allow_set_time = of_property_read_bool(pdev-dev.of_node,
+ linux,allow-set-time);
- rtc_dd-rtc_base = rtc_resource-start;
+ rtc_dd-rtc_base = (long) match-data;
/* Setup RTC register addresses */
rtc_dd-rtc_write_base = rtc_dd-rtc_base + PM8XXX_RTC_WRITE_OFFSET;
@@ -412,8 +419,6 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev)
}
rtc_dd-ctrl_reg = ctrl_reg;
- if (rtc_write_enable)
- pm8xxx_rtc_ops.set_time
[PATCH] pinctrl: msm: drop wake_irqs bitmap
Currently, the wake_irqs bitmap is used to track whether there are any
gpio's which are configured as wake irqs, and uses this to determine
whether or not to call enable_irq_wake()/disable_irq_wake() on the
summary interrupt.
However, the genirq core already handles this case, by maintaining a
'wake_count' per irq_desc, and only calling into the controlling
irq_chip when wake_count transitions 0 - 1.
Drop this bitmap, and unconditionally call irq_set_irq_wake() on the
summary interrupt.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/pinctrl/pinctrl-msm.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c
index 2cfb1d4..9b6b3a7 100644
--- a/drivers/pinctrl/pinctrl-msm.c
+++ b/drivers/pinctrl/pinctrl-msm.c
@@ -50,7 +50,6 @@
* @enabled_irqs: Bitmap of currently enabled irqs.
* @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
* detection.
- * @wake_irqs: Bitmap of irqs with requested as wakeup source.
* @soc;Reference to soc_data of platform specific data.
* @regs: Base address for the TLMM register map.
*/
@@ -65,7 +64,6 @@ struct msm_pinctrl {
DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
- DECLARE_BITMAP(wake_irqs, MAX_NR_GPIO);
const struct msm_pinctrl_soc_data *soc;
void __iomem *regs;
@@ -810,22 +808,12 @@ static int msm_gpio_irq_set_wake(struct irq_data *d,
unsigned int on)
{
struct msm_pinctrl *pctrl;
unsigned long flags;
- unsigned ngpio;
pctrl = irq_data_get_irq_chip_data(d);
- ngpio = pctrl-chip.ngpio;
spin_lock_irqsave(pctrl-lock, flags);
- if (on) {
- if (bitmap_empty(pctrl-wake_irqs, ngpio))
- enable_irq_wake(pctrl-irq);
- set_bit(d-hwirq, pctrl-wake_irqs);
- } else {
- clear_bit(d-hwirq, pctrl-wake_irqs);
- if (bitmap_empty(pctrl-wake_irqs, ngpio))
- disable_irq_wake(pctrl-irq);
- }
+ irq_set_irq_wake(pctrl-irq, on);
spin_unlock_irqrestore(pctrl-lock, flags);
--
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[PATCH] mfd: pm8921: fixup probe() error path when irq invalid
platform_get_irq() returns a negative error code when an IRQ is invalid
or unspecified. Make 'irq' signed to properly handle this.
Cc: Stephen Boyd sb...@codeaurora.org
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/mfd/pm8921-core.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
index 3aab6ac..d48452d 100644
--- a/drivers/mfd/pm8921-core.c
+++ b/drivers/mfd/pm8921-core.c
@@ -403,9 +403,8 @@ static int pm8921_probe(struct platform_device *pdev)
{
struct pm8921 *pmic;
struct regmap *regmap;
- int rc;
+ int irq, rc;
unsigned int val;
- unsigned int irq;
u32 rev;
struct pm_irq_chip *chip;
unsigned int nirqs = PM8921_NR_IRQS;
--
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Re: [PATCH v10 1/3] mmc: sdhci-msm: Qualcomm SDHCI binding documentation
Hey Rob-
On Wed, Mar 05, 2014 at 12:56:22AM -0600, Rob Herring wrote:
On Tue, Mar 4, 2014 at 1:27 PM, Georgi Djakov gdja...@mm-sol.com wrote:
+- reg-names: Should contain the following:
+ hc_mem - Host controller register map
+ core_mem - SD Core register map
reg-names should not be required and the order specified by the binding.
+- interrupts: Should contain an interrupt-specifiers for the interrupts
listed in interrupt-names.
+- interrupt-names: Should contain the following:
+ hc_irq - Host controller interrupt
+ pwr_irq- PMIC interrupt
Same for interrupt-names.
Could you elaborate on this a bit? I can understand not modifying an
existing binding to make {reg,interrupt}-names required, but for
completely new bindings, why is this a problem?
Not allowing a binding to require these properties renders
platform_get_{resource,irq}_byname() useless for drivers which
exclusively use DT for enumeration. It also makes it impossible to make
a reg entry optional (although, there probably isn't a good usecase for
this).
Thanks,
Josh
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Re: [PATCH 1/6] rtc: pm8xxx: fixup checkpatch/style issues
On Wed, Mar 05, 2014 at 01:02:29PM -0800, Stephen Boyd wrote:
On 03/05/14 11:29, Josh Cartwright wrote:
Before performing additional cleanups to this driver, do the easy
cleanups first.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
Reviewed-by: Stephen Boyd sb...@codeaurora.org
Thanks for the reviews.
@@ -253,7 +253,7 @@ static int pm8xxx_rtc_set_alarm(struct device *dev,
struct rtc_wkalrm *alarm)
ctrl_reg = rtc_dd-ctrl_reg;
ctrl_reg = alarm-enabled ? (ctrl_reg | PM8xxx_RTC_ALARM_ENABLE) :
- (ctrl_reg ~PM8xxx_RTC_ALARM_ENABLE);
+ (ctrl_reg ~PM8xxx_RTC_ALARM_ENABLE);
rc = pm8xxx_write_wrapper(rtc_dd, ctrl_reg, rtc_dd-rtc_base, 1);
if (rc 0) {
This could be better style with more lines:
if (alarm-enabled)
ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
else
ctrl_reg = ~PM8xxx_RTC_ALARM_ENABLE;
Agreed, I'll clean this up in a v2.
I might go back and see just how much can be cleanup up to use the
regmap_update_bits() API as well.
Thanks,
Josh
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[PATCH 1/2] spmi: pmic_arb: make selectable on ARCH_QCOM
With the split of Qualcomm MSM support into legacy and multiplatform, the SPMI PMIC arb driver is only relevant on the multiplatform supported SoCs. Switch the Kconfig depends to ARCH_QCOM. Cc: Kumar Gala ga...@codeaurora.org Signed-off-by: Josh Cartwright jo...@codeaurora.org --- drivers/spmi/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig index 075bd79..bf1295e 100644 --- a/drivers/spmi/Kconfig +++ b/drivers/spmi/Kconfig @@ -14,8 +14,8 @@ config SPMI_MSM_PMIC_ARB tristate Qualcomm MSM SPMI Controller (PMIC Arbiter) depends on ARM depends on IRQ_DOMAIN - depends on ARCH_MSM || COMPILE_TEST - default ARCH_MSM + depends on ARCH_QCOM || COMPILE_TEST + default ARCH_QCOM help If you say yes to this option, support will be included for the built-in SPMI PMIC Arbiter interface on Qualcomm MSM family -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 7/9] devicetree: bindings: Document PM8921/8058 keypads
On Thu, Feb 27, 2014 at 05:55:18PM -0800, Stephen Boyd wrote:
Document the keypad device found on PM8921 and PM8058 PMICs.
[..]
+++ b/Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
@@ -0,0 +1,72 @@
+Qualcomm PM8xxx PMIC Keypad
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type: string
+ Definition: must be one of:
+ qcom,pm8058-keypad
+ qcom,pm8921-keypad
+- interrupts:
+ Usage: required
+ Value type: prop-encoded-array
+ Definition: the first interrupt specifies the key sense interrupt
+ and the second interrupt specifies the key stuck interrupt.
+ The format of the specifier is defined by the binding
+ document describing the node's interrupt parent.
+
+- linux,keymap:
+ Usage: required
+ Value type: prop-encoded-array
+ Definition: the linux keymap. More information can be found in
+ input/matrix-keymap.txt.
+
+- keypad,num-rows:
+ Usage: required
+ Value type: u32
+ Definition: number of rows in the keymap. More information can be found
+ in input/matrix-keymap.txt.
+
+- keypad,num-columns:
+ Usage: required
+ Value type: u32
+ Definition: number of columns in the keymap. More information can be
+ found in input/matrix-keymap.txt.
+
+- debounce:
+ Usage: optional
+ Value type: u32
+ Definition: time in microseconds that key must be pressed or release
+ for key sense interrupt to trigger.
+
+- scan-delay:
+ Usage: optional
+ Value type: u32
+ Definition: time in microseconds to pause between successive scans
+ of the matrix array.
+
+- row-hold:
+ Usage: optional
+ Value type: u32
+ Definition: time in nanoseconds to pause between scans of each row in
+ the matrix array.
- linux,wakeup?
- linux,no-auto-repeat?
+
+EXAMPLE
+
+ keypad {
+ compatible = qcom,pm8921-keypad;
+ interrupt-parent = pmicintc;
+ interrupts = 74 1, 75 1;
+ linux,keymap =
+ MATRIX_KEY(0, 0, KEY_VOLUMEUP)
+ MATRIX_KEY(0, 1, KEY_VOLUMEDOWN)
+ MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS)
+ MATRIX_KEY(0, 3, KEY_CAMERA)
+ ;
+ keypad,num-rows = 1;
+ keypad,num-columns = 5;
+ debounce = 15;
+ scan-delay = 32;
+ row-hold = 91500;
+ };
It odd to me that these newly created bindings don't have 'reg'
properties, even though the device clearly has a register region.
I suppose it makes sense from a port over from platform data to DT
perspective, as these drivers have just assumed the location of their
registers to be fixed; however I suspect things will need to be changed
if/when we hope to share these drivers with pm8841/pm8941 and beyond...
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Re: [PATCH v4 7/9] devicetree: bindings: Document PM8921/8058 keypads
On Fri, Feb 28, 2014 at 10:37:08AM -0800, Stephen Boyd wrote:
On 02/28, Josh Cartwright wrote:
On Thu, Feb 27, 2014 at 05:55:18PM -0800, Stephen Boyd wrote:
+
+EXAMPLE
+
+ keypad {
+ compatible = qcom,pm8921-keypad;
+ interrupt-parent = pmicintc;
+ interrupts = 74 1, 75 1;
+ linux,keymap =
+ MATRIX_KEY(0, 0, KEY_VOLUMEUP)
+ MATRIX_KEY(0, 1, KEY_VOLUMEDOWN)
+ MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS)
+ MATRIX_KEY(0, 3, KEY_CAMERA)
+ ;
+ keypad,num-rows = 1;
+ keypad,num-columns = 5;
+ debounce = 15;
+ scan-delay = 32;
+ row-hold = 91500;
+ };
It odd to me that these newly created bindings don't have 'reg'
properties, even though the device clearly has a register region.
I suppose it makes sense from a port over from platform data to DT
perspective, as these drivers have just assumed the location of their
registers to be fixed; however I suspect things will need to be changed
if/when we hope to share these drivers with pm8841/pm8941 and beyond...
Agreed. I would love it if the platform OF code would create
IORESOURCE_REG resources for any reg properties that aren't
translatable to CPU addresses. That way we don't have to pick out the
reg property from DT with special OF code (like you've done in
rtc-pm8xxx).
Yes, I agree this would be nice. The rtc-pm8xxx register parsing magic
is misplaced/ugly. I'll see about taking a crack at this and seeing
what it looks like.
I'll throw the reg property into the binding so that in
the future we can support the register moving around (although at the
moment the driver will ignore it).
Great, I think this sounds good.
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Re: [PATCH v9 3/3] mmc: sdhci-msm: Add platform_execute_tunning implementation
Nit below. On Fri, Feb 28, 2014 at 01:24:35PM +0200, Georgi Djakov wrote: This patch adds implementation for platform specific tuning in order to support HS200 bus speed mode on Qualcomm SDHCI controller. Signed-off-by: Asutosh Das asuto...@codeaurora.org Signed-off-by: Venkat Gopalakrishnan venk...@codeaurora.org Signed-off-by: Georgi Djakov gdja...@mm-sol.com --- drivers/mmc/host/sdhci-msm.c | 424 +- 1 file changed, 418 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index b4490a2..69f6887 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c [..] +int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) This wants to be static. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] ARM: config: Add qcom_defconfig
On Wed, Feb 26, 2014 at 06:16:32PM -0800, Stephen Boyd wrote: Add a defconfig for mach-qcom platforms. Although these platforms are part of the multi-platform kernel, it's useful to have a stripped down version of the defconfig that just selects the Qualcomm based platforms and drivers. How minimal are we aiming here? It might be nice to at least get DEVTMPFS/DEVTMPFS_MOUNT=y in here, as I think udev barfs without it. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 5/9] Input: pmic8xxx-pwrkey - Migrate to DT
On Thu, Feb 27, 2014 at 05:55:16PM -0800, Stephen Boyd wrote: The driver is only supported on DT enabled platforms. Convert the driver to DT so that it can probe properly. Signed-off-by: Stephen Boyd sb...@codeaurora.org --- --- a/drivers/input/misc/pmic8xxx-pwrkey.c +++ b/drivers/input/misc/pmic8xxx-pwrkey.c @@ -172,7 +178,7 @@ static int pmic8xxx_pwrkey_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, pwrkey); - device_init_wakeup(pdev-dev, pdata-wakeup); + device_init_wakeup(pdev-dev, 1); Is there a particular reason you aren't providing a 'linux,wakeup' property for pwrkey? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 2/2] i2c: New bus driver for the Qualcomm QUP I2C controller
On Mon, Feb 24, 2014 at 12:33:10PM +0200, Ivan T. Ivanov wrote: On Fri, 2014-02-21 at 09:35 -0600, Kumar Gala wrote: On Feb 20, 2014, at 6:38 PM, Bjorn Andersson bjorn.anders...@sonymobile.com wrote: This bus driver supports the QUP i2c hardware controller in the Qualcomm SOCs. The Qualcomm Universal Peripheral Engine (QUP) is a general purpose data path engine with input/output FIFOs and an embedded i2c mini-core. The driver supports FIFO mode (for low bandwidth applications) and block mode (interrupt generated for each block-size data transfer). Cc: Andy Gross agr...@codeaurora.org Cc: Stephen Boyd sb...@codeaurora.org Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com --- +config I2C_QUP + tristate Qualcomm QUP based I2C controller + depends on ARCH_MSM ARCH_QCOM There is no such symbol, still. For what it's worth, the rename/split is in linux-next, and will land in 3.15 (as part of arm-soc cleanups). Is the (short-term) problem of the lack of the symbol a problem? Worse case, this driver lands before the ARCH_QCOM rename lands, and the driver is just not selectable. Only when both are in place can the driver be selected. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: linux-next: Tree for Feb 17 (pinctrl-msm)
On Mon, Feb 24, 2014 at 10:14:45AM -0800, Randy Dunlap wrote: On 02/24/2014 09:46 AM, Bjorn Andersson wrote: On Mon 24 Feb 06:46 PST 2014, Linus Walleij wrote: On Mon, Feb 17, 2014 at 6:33 PM, Randy Dunlap rdun...@infradead.org wrote: On 02/16/2014 10:23 PM, Stephen Rothwell wrote: ERROR: handle_bad_irq [drivers/pinctrl/pinctrl-msm.ko] undefined! Weird, Björn do you know what may be causing this? I include linux/irq.h to get hold of handle_bad_irq() and as far as I can see there are no changes related to that in linux-next. Do we know if the build still fails? Or if something changed? Please let me know if I should pull down the -next tree and try to reproduce this. I guess that you get off free on this one since I didn't post the failing .config file and I have already deleted it. I'm trying to reproduce it now but it's slow going. I'll let you know if I get it to fail again. Without too much effort, I can get this to fail just by making CONFIG_PINCTRL_MSM=m. handle_bad_irq isn't marked EXPORT_SYMBOL*, so hence the warning. Whether or not this is intentional is not clear. Do we support modules installing chained irq handlers? For now, the patch below just makes this driver 'bool' instead of 'tristate'. Josh --8-- Subject: [PATCH] pinctrl: msm: make PINCTRL_MSM bool instead of tristate Modular builds of pinctrl-msm break due to handle_bad_irq being unexported for module use. For now, make PINCTRL_MSM 'bool'. Signed-off-by: Josh Cartwright jo...@codeaurora.org --- drivers/pinctrl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index be361b7..1e4e693 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -217,7 +217,7 @@ config PINCTRL_IMX28 select PINCTRL_MXS config PINCTRL_MSM - tristate + bool select PINMUX select PINCONF select GENERIC_PINCONF -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/3] usb: chipidea: msm: Add device tree support
Hey Ivan-
Nit below.
On Tue, Feb 18, 2014 at 03:21:20PM +0200, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Allows controller to be specified via device tree.
Pass PHY phandle specified in DT to core driver.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/chipidea/ci_hdrc_msm.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/chipidea/ci_hdrc_msm.c
b/drivers/usb/chipidea/ci_hdrc_msm.c
index 2d51d85..3f67f1f 100644
--- a/drivers/usb/chipidea/ci_hdrc_msm.c
+++ b/drivers/usb/chipidea/ci_hdrc_msm.c
@@ -57,9 +57,21 @@ static struct ci_hdrc_platform_data ci_hdrc_msm_platdata =
{
static int ci_hdrc_msm_probe(struct platform_device *pdev)
{
struct platform_device *plat_ci;
+ struct usb_phy *phy;
dev_dbg(pdev-dev, ci_hdrc_msm_probe\n);
+ /*
+ * OTG(PHY) driver takes care of PHY initialization, clock management,
+ * powering up VBUS, mapping of registers address space and power
+ * management.
+ */
+ phy = devm_usb_get_phy_by_phandle(pdev-dev, usb-phy, 0);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ ci_hdrc_msm_platdata.phy = phy;
+
plat_ci = ci_hdrc_add_device(pdev-dev,
pdev-resource, pdev-num_resources,
ci_hdrc_msm_platdata);
@@ -86,10 +98,19 @@ static int ci_hdrc_msm_remove(struct platform_device
*pdev)
return 0;
}
+static struct of_device_id msm_ci_dt_match[] = {
const?
+ { .compatible = qcom,ci-hdrc, },
+ { }
+};
+MODULE_DEVICE_TABLE(of, msm_ci_dt_match);
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Re: [PATCH v2 1/3] usb: chipidea: msm: Add device tree binding information
On Tue, Feb 18, 2014 at 03:21:19PM +0200, Ivan T. Ivanov wrote: From: Ivan T. Ivanov iiva...@mm-sol.com Document device tree binding information as required by the Qualcomm USB controller. Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com --- .../devicetree/bindings/usb/msm-hsusb.txt | 17 + Is this really the appropriate place to document this? It seems like this binding doc should be merged with the i.MX ci13xxx binding in a common ci13xxx doc. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] usb: phy: msm: fix compilation errors when !CONFIG_PM_SLEEP
On Tue, Feb 18, 2014 at 10:24:16AM -0600, Felipe Balbi wrote:
On Fri, Jan 17, 2014 at 12:26:50PM -0600, Josh Cartwright wrote:
On Fri, Jan 17, 2014 at 11:58:51AM -0600, Josh Cartwright wrote:
Both the PM_RUNTIME and PM_SLEEP callbacks call into the common
msm_otg_{suspend,resume} routines, however these routines are only being
built when CONFIG_PM_SLEEP. In addition, msm_otg_{suspend,resume} also
depends on msm_hsusb_config_vddcx(), which is only built when
CONFIG_PM_SLEEP.
Fix the CONFIG_PM_RUNTIME, !CONFIG_PM_SLEEP case by changing the
preprocessor conditional, and moving msm_hsusb_config_vddcx().
While we're here, eliminate the CONFIG_PM conditional for setting
up the dev_pm_ops.
This address the following errors Russell King has hit doing randconfig
builds:
drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_suspend':
drivers/usb/phy/phy-msm-usb.c:1691:2: error: implicit declaration of
function 'msm_otg_suspend'
drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_resume':
drivers/usb/phy/phy-msm-usb.c:1699:2: error: implicit declaration of
function 'msm_otg_resume'
Cc: Ivan T. Ivanov iiva...@mm-sol.com
Reported-by: Russell King rmk+ker...@arm.linux.org.uk
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
v1-v2: Change conditional to simply CONFIG_PM (thanks ccov and khilman!)
drivers/usb/phy/phy-msm-usb.c | 57
---
1 file changed, 26 insertions(+), 31 deletions(-)
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 8546c8d..5b169a7 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
[..]
@@ -440,7 +414,32 @@ static int msm_otg_reset(struct usb_phy *phy)
#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
#define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
-#ifdef CONFIG_PM_SLEEP
+#if CONFIG_PM
*sigh*. This, of course, should have been #ifdef CONFIG_PM. Fixed
v3 below.
sorry, please git send-email it properly.
No problem, will do. FWIW, it's applicable with git am --scissors.
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[PATCH RESEND v3] usb: phy: msm: fix compilation errors when !CONFIG_PM_SLEEP
Both the PM_RUNTIME and PM_SLEEP callbacks call into the common
msm_otg_{suspend,resume} routines, however these routines are only being
built when CONFIG_PM_SLEEP. In addition, msm_otg_{suspend,resume} also
depends on msm_hsusb_config_vddcx(), which is only built when
CONFIG_PM_SLEEP.
Fix the CONFIG_PM_RUNTIME, !CONFIG_PM_SLEEP case by changing the
preprocessor conditional, and moving msm_hsusb_config_vddcx().
While we're here, eliminate the CONFIG_PM conditional for setting
up the dev_pm_ops.
This address the following errors Russell King has hit doing randconfig
builds:
drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_suspend':
drivers/usb/phy/phy-msm-usb.c:1691:2: error: implicit declaration of function
'msm_otg_suspend'
drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_resume':
drivers/usb/phy/phy-msm-usb.c:1699:2: error: implicit declaration of function
'msm_otg_resume'
Cc: Ivan T. Ivanov iiva...@mm-sol.com
Reported-by: Russell King rmk+ker...@arm.linux.org.uk
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/usb/phy/phy-msm-usb.c | 57 ---
1 file changed, 26 insertions(+), 31 deletions(-)
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 64c9d14e..5b37b81 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -159,32 +159,6 @@ put_3p3:
return rc;
}
-#ifdef CONFIG_PM_SLEEP
-#define USB_PHY_SUSP_DIG_VOL 50
-static int msm_hsusb_config_vddcx(int high)
-{
- int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
- int min_vol;
- int ret;
-
- if (high)
- min_vol = USB_PHY_VDD_DIG_VOL_MIN;
- else
- min_vol = USB_PHY_SUSP_DIG_VOL;
-
- ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
- if (ret) {
- pr_err(%s: unable to set the voltage for regulator
- HSUSB_VDDCX\n, __func__);
- return ret;
- }
-
- pr_debug(%s: min_vol:%d max_vol:%d\n, __func__, min_vol, max_vol);
-
- return ret;
-}
-#endif
-
static int msm_hsusb_ldo_set_mode(int on)
{
int ret = 0;
@@ -440,7 +414,32 @@ static int msm_otg_reset(struct usb_phy *phy)
#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
#define PHY_RESUME_TIMEOUT_USEC(100 * 1000)
-#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_PM
+
+#define USB_PHY_SUSP_DIG_VOL 50
+static int msm_hsusb_config_vddcx(int high)
+{
+ int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
+ int min_vol;
+ int ret;
+
+ if (high)
+ min_vol = USB_PHY_VDD_DIG_VOL_MIN;
+ else
+ min_vol = USB_PHY_SUSP_DIG_VOL;
+
+ ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
+ if (ret) {
+ pr_err(%s: unable to set the voltage for regulator
+ HSUSB_VDDCX\n, __func__);
+ return ret;
+ }
+
+ pr_debug(%s: min_vol:%d max_vol:%d\n, __func__, min_vol, max_vol);
+
+ return ret;
+}
+
static int msm_otg_suspend(struct msm_otg *motg)
{
struct usb_phy *phy = motg-phy;
@@ -1734,22 +1733,18 @@ static int msm_otg_pm_resume(struct device *dev)
}
#endif
-#ifdef CONFIG_PM
static const struct dev_pm_ops msm_otg_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
msm_otg_runtime_idle)
};
-#endif
static struct platform_driver msm_otg_driver = {
.remove = msm_otg_remove,
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
-#ifdef CONFIG_PM
.pm = msm_otg_dev_pm_ops,
-#endif
},
};
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Re: [PATCH v5 1/6] spmi: Linux driver framework for SPMI
On Sat, Feb 15, 2014 at 05:47:48PM -0600, Felipe Balbi wrote:
On Mon, Feb 03, 2014 at 05:05:33PM -0600, Josh Cartwright wrote:
+#ifdef CONFIG_PM_RUNTIME
+static int spmi_runtime_suspend(struct device *dev)
+{
+ struct spmi_device *sdev = to_spmi_device(dev);
+ int err;
+
+ err = pm_generic_runtime_suspend(dev);
+ if (err)
+ return err;
+
+ return spmi_command_sleep(sdev);
shouldn't this too calls be swapped ? I mean, some pm_runtime
implementations could be gating clocks at the driver's
-runtime_suspend() callback.
Perhaps. I had added the explicit SLEEP/WAKEUP commands to
suspend()/resume(), but now I'm thinking issuing these commands should
not be the responsibility of the core, since the semantics of the
SLEEP/ACTIVE state aren't well defined in general (each
implementation/slave defines what, if anything, these states mean).
Fortunately, there are no users yet, so this is a painless change. :)
Thanks for taking a look.
Josh
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Re: [PATCH v2 1/3] usb: chipidea: msm: Add device tree binding information
On Tue, Feb 18, 2014 at 07:27:00PM +0200, Ivan T. Ivanov wrote: On Tue, 2014-02-18 at 10:13 -0600, Josh Cartwright wrote: On Tue, Feb 18, 2014 at 03:21:19PM +0200, Ivan T. Ivanov wrote: .../devicetree/bindings/usb/msm-hsusb.txt | 17 + Is this really the appropriate place to document this? It seems like this binding doc should be merged with the i.MX ci13xxx binding in a common ci13xxx doc. This driver is a glue layer driver which control Qualcomm specific logic around Chipidea IP core. It is supposed to hold non standard Chipidea properties, but I suppose that ci-hdrc-qcom.txt will be better name and will be similar to i.MX chosen name. What do you think? Sounds like an improvement to me. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 0/6] Add support for the System Power Management Interface (SPMI)
Hey Greg-
Is it possible for you to pick this up for 3.15? It'd be nice if we could get
an Ack from devicetree folks on patches 2 and 5, but there has been many months
worth of opportunity for that.
Thanks,
Josh
---
The System Power Management Interface (SPMI) is a high-speed,
low-latency, bi-directional, two-wire serial bus suitable for real-time
control of voltage and frequency scaled multi-core application
processors and its power management of auxiliary components. SPMI
obsoletes a number of legacy, custom point-to-point interfaces and
provides a low pin count, high-speed control bus for up to 4 Master and
16 Slave devices.
SPMI is specified by the MIPI (Mobile Industry Process Interface)
Alliance [1].
This patchset is intended both to provide a core implementation of SPMI and
also to provide a controller driver implementation.
- Patches 1-2 implement the SPMI core functionality and provide basic
DT binding documentation
- Patches 3-5 provide an implementation of an SPMI controller, the
Qualcomm SPMI PMIC Arbiter, currently used on the 8x74 SoCs.
- Patch 6 rounds out regmap support for SPMI
Changes from v5[2]:
- Changed PMIC Arbiter locking to use a raw_spinlock_t over the non-raw
variant due to it's use in an irqchip implementation (feedback from Thomas
Gleixner)
- Reworded descriptions of the reg and reg-names properties in the PMIC
Arbiter devicetree binding document
Changes from v4[3]:
- Fixed a few minor error-handling bugs found with further testing
- Addressed Courtney Cavin's feedback regarding device tree bindings
- Reworked Kconfig options a bit (allow for building PMIC arb when
COMPILE_TEST=y)
Changes from v3[4]:
- Dropped the pm8x41 PMIC driver and pm8xxx-rtc changes as part of this
patchset.
(will be sent out separately)
- Rebased on v3.13-rc2
- Move to simple_ida_* for controller ID allocation
- Addressed documentation fixes and nits
- Provide pm_runtime implementation, which leverages SPMI's SLEEP and WAKEUP
commands
- Address spmi_controller object lifetime issues
Changes from v2[5]:
- Dropped RFC.
- Add basic regmap support at Mark Brown's suggestion
- Drop debugfs interface. Debugging SPMI accesses can happen via the regmap
debugfs interface if necessary.
- Add second address-cell in SPMI generic device tree binding, encoding the
address type (suggestion by Stephen Warren)
- Implement interrupt handling functionality within the PMIC Arbiter driver
- Provide basic MFD driver for the PMIC8x41 PMICs, demonstrating SPMI regmap
client use
- Adapt existing pm8xxx-rtc driver to work as a child of the PM8x41 mfd device
Changes from v1[6]:
- Adopted patch (1/5) to #define for_each_available_node() shim
in the !CONFIG_OF case
- Moved device tree logic out of drivers/of and into spmi.c core (this
mirrors what SPI is doing, and what i2c will soon be doing)
- Move of_spmi_add_devices() call into spmi_device_add(), so drivers don't
have to call it explicitly
- Unconditionally build in debugfs code (rely on the underlying
CONFIG_DEBUG_FS switch to throw unused code away)
- Change pr_* print functions to their dev_* equivalents
- Fix copy_{to,from}_user error handling
- Renamed board_lock to ctrl_idr_lock to better describe it's purpose
- Rework device object lifetime management
- Rename PMIC arb binding document, add description of PMIC arb
- Add generic SPMI device tree bindings
[1]: http://www.mipi.org/specifications/system-power-management-interface
[2]:
http://lkml.kernel.org/r/1391468739-20987-1-git-send-email-jo...@codeaurora.org
[3]: http://lkml.kernel.org/r/cover.1389738151.git.jo...@codeaurora.org
[4]: http://lkml.kernel.org/r/cover.1382985169.git.jo...@codeaurora.org
[5]: http://lkml.kernel.org/r/cover.1377202730.git.jo...@codeaurora.org
[6]: http://lkml.kernel.org/r/cover.1376596224.git.jo...@codeaurora.org
Josh Cartwright (4):
spmi: add generic SPMI controller binding documentation
spmi: pmic_arb: add support for interrupt handling
spmi: document the PMIC arbiter SPMI bindings
regmap: spmi: support base and extended register spaces
Kenneth Heitke (2):
spmi: Linux driver framework for SPMI
spmi: Add MSM PMIC Arbiter SPMI controller
.../bindings/spmi/qcom,spmi-pmic-arb.txt | 61 ++
Documentation/devicetree/bindings/spmi/spmi.txt| 41 ++
drivers/Kconfig| 2 +
drivers/Makefile | 1 +
drivers/base/regmap/regmap-spmi.c | 228 +-
drivers/spmi/Kconfig | 27 +
drivers/spmi/Makefile | 6 +
drivers/spmi/spmi-pmic-arb.c | 778 +
drivers/spmi/spmi.c| 609
include/dt-bindings/spmi/spmi.h| 18 +
include/linux/mod_devicetable.h| 8 +
include/linux
[PATCH v6 4/6] spmi: pmic_arb: add support for interrupt handling
The Qualcomm PMIC Arbiter, in addition to being a basic SPMI controller,
also implements interrupt handling for slave devices. Note, this is
outside the scope of SPMI, as SPMI leaves interrupt handling completely
unspecified.
Extend the driver to provide a irq_chip implementation and chained irq
handling which allows for these interrupts to be used.
Cc: Thomas Gleixner t...@linutronix.de
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
Thomas-
You've looked at this before[1], but I conservatively didn't turn your Looks
sane otherwise comment into full Ack. The only thing that has changed is now
a raw spinlock is used for locking.
Thanks,
Josh
[1]: http://marc.info/?l=linux-kernelm=139154465617561w=2
drivers/spmi/Kconfig | 1 +
drivers/spmi/spmi-pmic-arb.c | 377 ++-
2 files changed, 376 insertions(+), 2 deletions(-)
diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
index 80b7901..075bd79 100644
--- a/drivers/spmi/Kconfig
+++ b/drivers/spmi/Kconfig
@@ -13,6 +13,7 @@ if SPMI
config SPMI_MSM_PMIC_ARB
tristate Qualcomm MSM SPMI Controller (PMIC Arbiter)
depends on ARM
+ depends on IRQ_DOMAIN
depends on ARCH_MSM || COMPILE_TEST
default ARCH_MSM
help
diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
index 2dd27e8..246e03a 100644
--- a/drivers/spmi/spmi-pmic-arb.c
+++ b/drivers/spmi/spmi-pmic-arb.c
@@ -13,6 +13,9 @@
#include linux/err.h
#include linux/interrupt.h
#include linux/io.h
+#include linux/irqchip/chained_irq.h
+#include linux/irqdomain.h
+#include linux/irq.h
#include linux/kernel.h
#include linux/module.h
#include linux/of.h
@@ -103,6 +106,14 @@ enum pmic_arb_cmd_op_code {
* @cnfg: address of the PMIC Arbiter configuration registers.
* @lock: lock to synchronize accesses.
* @channel: which channel to use for accesses.
+ * @irq: PMIC ARB interrupt.
+ * @ee:the current Execution Environment
+ * @min_apid: minimum APID (used for bounding IRQ search)
+ * @max_apid: maximum APID
+ * @mapping_table: in-memory copy of PPID - APID mapping table.
+ * @domain:irq domain object for PMIC IRQ domain
+ * @spmic: SPMI controller object
+ * @apid_to_ppid: cached mapping from APID to PPID
*/
struct spmi_pmic_arb_dev {
void __iomem*base;
@@ -110,6 +121,14 @@ struct spmi_pmic_arb_dev {
void __iomem*cnfg;
raw_spinlock_t lock;
u8 channel;
+ int irq;
+ u8 ee;
+ u8 min_apid;
+ u8 max_apid;
+ u32 mapping_table[SPMI_MAPPING_TABLE_LEN];
+ struct irq_domain *domain;
+ struct spmi_controller *spmic;
+ u16 apid_to_ppid[256];
};
static inline u32 pmic_arb_base_read(struct spmi_pmic_arb_dev *dev, u32 offset)
@@ -306,12 +325,316 @@ static int pmic_arb_write_cmd(struct spmi_controller
*ctrl, u8 opc, u8 sid,
return rc;
}
+enum qpnpint_regs {
+ QPNPINT_REG_RT_STS = 0x10,
+ QPNPINT_REG_SET_TYPE= 0x11,
+ QPNPINT_REG_POLARITY_HIGH = 0x12,
+ QPNPINT_REG_POLARITY_LOW= 0x13,
+ QPNPINT_REG_LATCHED_CLR = 0x14,
+ QPNPINT_REG_EN_SET = 0x15,
+ QPNPINT_REG_EN_CLR = 0x16,
+ QPNPINT_REG_LATCHED_STS = 0x18,
+};
+
+struct spmi_pmic_arb_qpnpint_type {
+ u8 type; /* 1 - edge */
+ u8 polarity_high;
+ u8 polarity_low;
+} __packed;
+
+/* Simplified accessor functions for irqchip callbacks */
+static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
+ size_t len)
+{
+ struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
+ u8 sid = d-hwirq 24;
+ u8 per = d-hwirq 16;
+
+ if (pmic_arb_write_cmd(pa-spmic, SPMI_CMD_EXT_WRITEL, sid,
+ (per 8) + reg, buf, len))
+ dev_err_ratelimited(pa-spmic-dev,
+ failed irqchip transaction on %x\n,
+ d-irq);
+}
+
+static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t
len)
+{
+ struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
+ u8 sid = d-hwirq 24;
+ u8 per = d-hwirq 16;
+
+ if (pmic_arb_read_cmd(pa-spmic, SPMI_CMD_EXT_READL, sid,
+ (per 8) + reg, buf, len))
+ dev_err_ratelimited(pa-spmic-dev,
+ failed irqchip transaction on %x\n,
+ d-irq);
+}
+
+static void periph_interrupt(struct spmi_pmic_arb_dev *pa, u8 apid)
+{
+ unsigned int irq;
+ u32 status;
+ int id
[PATCH v6 2/6] spmi: add generic SPMI controller binding documentation
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
Documentation/devicetree/bindings/spmi/spmi.txt | 41 +
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spmi/spmi.txt
diff --git a/Documentation/devicetree/bindings/spmi/spmi.txt
b/Documentation/devicetree/bindings/spmi/spmi.txt
new file mode 100644
index 000..462a42f
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/spmi.txt
@@ -0,0 +1,41 @@
+System Power Management Interface (SPMI) Controller
+
+This document defines a generic set of bindings for use by SPMI controllers. A
+controller is modelled in device tree as a node with zero or more child nodes,
+each representing a unique slave on the bus.
+
+Required properties:
+- #address-cells : must be set to 2
+- #size-cells : must be set to 0
+
+Child nodes:
+
+An SPMI controller node can contain zero or more child nodes representing slave
+devices on the bus. Child 'reg' properties are specified as an address, type
+pair. The address must be in the range 0-15 (4 bits). The type must be one of
+SPMI_USID (0) or SPMI_GSID (1) for Unique Slave ID or Group Slave ID
respectively.
+These are the identifiers statically assigned by the system integrator, as
+per the SPMI spec.
+
+Each child node must have one and only one 'reg' entry of type SPMI_USID.
+
+#include dt-bindings/spmi/spmi.h
+
+ spmi@.. {
+ compatible = ...;
+ reg = ...;
+
+ #address-cells = 2;
+ #size-cells 0;
+
+ child@0 {
+ compatible = ...;
+ reg = 0 SPMI_USID;
+ };
+
+ child@7 {
+ compatible = ...;
+ reg = 7 SPMI_USID
+ 3 SPMI_GSID;
+ };
+ };
--
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[PATCH v6 6/6] regmap: spmi: support base and extended register spaces
SPMI states that a slave may contain two register spaces, the Base
register space is a 5-bit byte-addressable space accessed via the
Register Read/Write and Register Zero Write command sequences, and the
Extended register space: a 16-bit byte-addressable space accessed via
the Extended Read/Write and Extended Read/Write Long command sequences.
Provide support for accessing both of these spaces, taking advantage of
the more bandwidth-efficient commands ('Register 0 Write' vs 'Register
Write', and 'Extended Register Read/Write' vs 'Extended Register
Read/Write Long') when possible.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
Acked-by: Mark Brown broo...@linaro.org
---
drivers/base/regmap/regmap-spmi.c | 228 --
include/linux/regmap.h| 12 +-
2 files changed, 205 insertions(+), 35 deletions(-)
diff --git a/drivers/base/regmap/regmap-spmi.c
b/drivers/base/regmap/regmap-spmi.c
index ac23910..d7026dc 100644
--- a/drivers/base/regmap/regmap-spmi.c
+++ b/drivers/base/regmap/regmap-spmi.c
@@ -22,69 +22,235 @@
#include linux/module.h
#include linux/init.h
-static int regmap_spmi_read(void *context,
- const void *reg, size_t reg_size,
- void *val, size_t val_size)
+static int regmap_spmi_base_read(void *context,
+const void *reg, size_t reg_size,
+void *val, size_t val_size)
{
+ u8 addr = *(u8 *)reg;
+ int err = 0;
+
+ BUG_ON(reg_size != 1);
+
+ while (val_size-- !err)
+ err = spmi_register_read(context, addr++, val++);
+
+ return err;
+}
+
+static int regmap_spmi_base_gather_write(void *context,
+const void *reg, size_t reg_size,
+const void *val, size_t val_size)
+{
+ const u8 *data = val;
+ u8 addr = *(u8 *)reg;
+ int err = 0;
+
+ BUG_ON(reg_size != 1);
+
+ /*
+* SPMI defines a more bandwidth-efficient 'Register 0 Write' sequence,
+* use it when possible.
+*/
+ if (addr == 0 val_size) {
+ err = spmi_register_zero_write(context, *data);
+ if (err)
+ goto err_out;
+
+ data++;
+ addr++;
+ val_size--;
+ }
+
+ while (val_size) {
+ err = spmi_register_write(context, addr, *data);
+ if (err)
+ goto err_out;
+
+ data++;
+ addr++;
+ val_size--;
+ }
+
+err_out:
+ return err;
+}
+
+static int regmap_spmi_base_write(void *context, const void *data,
+ size_t count)
+{
+ BUG_ON(count 1);
+ return regmap_spmi_base_gather_write(context, data, 1, data + 1,
+count - 1);
+}
+
+static struct regmap_bus regmap_spmi_base = {
+ .read = regmap_spmi_base_read,
+ .write = regmap_spmi_base_write,
+ .gather_write = regmap_spmi_base_gather_write,
+ .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
+ .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
+};
+
+/**
+ * regmap_init_spmi_base(): Create regmap for the Base register space
+ * @sdev: SPMI device that will be interacted with
+ * @config:Configuration for register map
+ *
+ * The return value will be an ERR_PTR() on error or a valid pointer to
+ * a struct regmap.
+ */
+struct regmap *regmap_init_spmi_base(struct spmi_device *sdev,
+const struct regmap_config *config)
+{
+ return regmap_init(sdev-dev, regmap_spmi_base, sdev, config);
+}
+EXPORT_SYMBOL_GPL(regmap_init_spmi_base);
+
+/**
+ * devm_regmap_init_spmi_base(): Create managed regmap for Base register space
+ * @sdev: SPMI device that will be interacted with
+ * @config:Configuration for register map
+ *
+ * The return value will be an ERR_PTR() on error or a valid pointer
+ * to a struct regmap. The regmap will be automatically freed by the
+ * device management code.
+ */
+struct regmap *devm_regmap_init_spmi_base(struct spmi_device *sdev,
+ const struct regmap_config *config)
+{
+ return devm_regmap_init(sdev-dev, regmap_spmi_base, sdev, config);
+}
+EXPORT_SYMBOL_GPL(devm_regmap_init_spmi_base);
+
+static int regmap_spmi_ext_read(void *context,
+ const void *reg, size_t reg_size,
+ void *val, size_t val_size)
+{
+ int err = 0;
+ size_t len;
+ u16 addr;
+
BUG_ON(reg_size != 2);
- return spmi_ext_register_readl(context, *(u16 *)reg,
- val, val_size);
+
+ addr = *(u16 *)reg;
+
+ /*
+* Split accesses into two to take
[PATCH v6 5/6] spmi: document the PMIC arbiter SPMI bindings
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
.../bindings/spmi/qcom,spmi-pmic-arb.txt | 61 ++
1 file changed, 61 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
new file mode 100644
index 000..715d099
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
@@ -0,0 +1,61 @@
+Qualcomm SPMI Controller (PMIC Arbiter)
+
+The SPMI PMIC Arbiter is found on the Snapdragon 800 Series. It is an SPMI
+controller with wrapping arbitration logic to allow for multiple on-chip
+devices to control a single SPMI master.
+
+The PMIC Arbiter can also act as an interrupt controller, providing interrupts
+to slave devices.
+
+See spmi.txt for the generic SPMI controller binding requirements for child
+nodes.
+
+See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
+generic interrupt controller binding documentation.
+
+Required properties:
+- compatible : should be qcom,spmi-pmic-arb.
+- reg-names : must contain:
+ core - core registers
+ intr - interrupt controller registers
+ cnfg - configuration registers
+- reg : address + size pairs describing the PMIC arb register sets; order must
+correspond with the order of entries in reg-names
+- #address-cells : must be set to 2
+- #size-cells : must be set to 0
+- qcom,ee : indicates the active Execution Environment identifier (0-5)
+- qcom,channel : which of the PMIC Arb provided channels to use for accesses
(0-5)
+- interrupts : interrupt list for the PMIC Arb controller, must contain a
+ single interrupt entry for the peripheral interrupt
+- interrupt-names : corresponding interrupt names for the interrupts
+listed in the 'interrupts' property, must contain:
+ periph_irq - summary interrupt for PMIC peripherals
+- interrupt-controller : boolean indicator that the PMIC arbiter is an
interrupt controller
+- #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple:
+cell 1: slave ID for the requested interrupt (0-15)
+cell 2: peripheral ID for requested interrupt (0-255)
+cell 3: the requested peripheral interrupt (0-7)
+cell 4: interrupt flags indicating level-sense information, as defined in
+dt-bindings/interrupt-controller/irq.h
+
+Example:
+
+ spmi {
+ compatible = qcom,spmi-pmic-arb;
+ reg-names = core, intr, cnfg;
+ reg = 0xfc4cf000 0x1000,
+ 0xfc4cb000 0x1000,
+ 0xfc4ca000 0x1000;
+
+ interrupt-names = periph_irq;
+ interrupts = 0 190 0;
+
+ qcom,ee = 0;
+ qcom,channel = 0;
+
+ #address-cells = 2;
+ #size-cells = 0;
+
+ interrupt-controller;
+ #interrupt-cells = 4;
+ };
--
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[PATCH v6 3/6] spmi: Add MSM PMIC Arbiter SPMI controller
From: Kenneth Heitke khei...@codeaurora.org
Qualcomm's PMIC Arbiter SPMI controller functions as a bus master and
is used to communication with one or more PMIC (slave) devices on the
SPMI bus. The PMIC Arbiter is actually a hardware wrapper around the
SPMI controller that provides concurrent and autonomous PMIC access
to various entities that need to communicate with the PMIC.
The SPMI controller hardware handles all of the SPMI bus activity (bus
arbitration, sequence start condition, transmission of frames, etc).
This software driver uses the PMIC Arbiter register interface to
initiate command sequences on the SPMI bus. The status register is
read to determine when the command sequence has completed and whether
or not it completed successfully.
Signed-off-by: Kenneth Heitke khei...@codeaurora.org
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/spmi/Kconfig | 17 ++
drivers/spmi/Makefile| 2 +
drivers/spmi/spmi-pmic-arb.c | 405 +++
3 files changed, 424 insertions(+)
create mode 100644 drivers/spmi/spmi-pmic-arb.c
diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
index 1dbfee0..80b7901 100644
--- a/drivers/spmi/Kconfig
+++ b/drivers/spmi/Kconfig
@@ -7,3 +7,20 @@ menuconfig SPMI
SPMI (System Power Management Interface) is a two-wire
serial interface between baseband and application processors
and Power Management Integrated Circuits (PMIC).
+
+if SPMI
+
+config SPMI_MSM_PMIC_ARB
+ tristate Qualcomm MSM SPMI Controller (PMIC Arbiter)
+ depends on ARM
+ depends on ARCH_MSM || COMPILE_TEST
+ default ARCH_MSM
+ help
+ If you say yes to this option, support will be included for the
+ built-in SPMI PMIC Arbiter interface on Qualcomm MSM family
+ processors.
+
+ This is required for communicating with Qualcomm PMICs and
+ other devices that have the SPMI interface.
+
+endif
diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile
index 1de1acd..fc75104 100644
--- a/drivers/spmi/Makefile
+++ b/drivers/spmi/Makefile
@@ -2,3 +2,5 @@
# Makefile for kernel SPMI framework.
#
obj-$(CONFIG_SPMI) += spmi.o
+
+obj-$(CONFIG_SPMI_MSM_PMIC_ARB)+= spmi-pmic-arb.o
diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
new file mode 100644
index 000..2dd27e8
--- /dev/null
+++ b/drivers/spmi/spmi-pmic-arb.c
@@ -0,0 +1,405 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include linux/delay.h
+#include linux/err.h
+#include linux/interrupt.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/slab.h
+#include linux/spmi.h
+
+/* PMIC Arbiter configuration registers */
+#define PMIC_ARB_VERSION 0x
+#define PMIC_ARB_INT_EN0x0004
+
+/* PMIC Arbiter channel registers */
+#define PMIC_ARB_CMD(N)(0x0800 + (0x80 * (N)))
+#define PMIC_ARB_CONFIG(N) (0x0804 + (0x80 * (N)))
+#define PMIC_ARB_STATUS(N) (0x0808 + (0x80 * (N)))
+#define PMIC_ARB_WDATA0(N) (0x0810 + (0x80 * (N)))
+#define PMIC_ARB_WDATA1(N) (0x0814 + (0x80 * (N)))
+#define PMIC_ARB_RDATA0(N) (0x0818 + (0x80 * (N)))
+#define PMIC_ARB_RDATA1(N) (0x081C + (0x80 * (N)))
+
+/* Interrupt Controller */
+#define SPMI_PIC_OWNER_ACC_STATUS(M, N)(0x + ((32 * (M)) + (4 *
(N
+#define SPMI_PIC_ACC_ENABLE(N) (0x0200 + (4 * (N)))
+#define SPMI_PIC_IRQ_STATUS(N) (0x0600 + (4 * (N)))
+#define SPMI_PIC_IRQ_CLEAR(N) (0x0A00 + (4 * (N)))
+
+/* Mapping Table */
+#define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N)))
+#define SPMI_MAPPING_BIT_INDEX(X) (((X) 18) 0xF)
+#define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) 17) 0x1)
+#define SPMI_MAPPING_BIT_IS_0_RESULT(X)(((X) 9) 0xFF)
+#define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) 8) 0x1)
+#define SPMI_MAPPING_BIT_IS_1_RESULT(X)(((X) 0) 0xFF)
+
+#define SPMI_MAPPING_TABLE_LEN 255
+#define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */
+
+/* Ownership Table */
+#define SPMI_OWNERSHIP_TABLE_REG(N)(0x0700 + (4 * (N)))
+#define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) 0x7)
+
+/* Channel Status fields */
+enum pmic_arb_chnl_status {
+ PMIC_ARB_STATUS_DONE= (1 0),
+ PMIC_ARB_STATUS_FAILURE = (1 1
[PATCH v6 1/6] spmi: Linux driver framework for SPMI
From: Kenneth Heitke khei...@codeaurora.org
System Power Management Interface (SPMI) is a specification
developed by the MIPI (Mobile Industry Process Interface) Alliance
optimized for the real time control of Power Management ICs (PMIC).
SPMI is a two-wire serial interface that supports up to 4 master
devices and up to 16 logical slaves.
The framework supports message APIs, multiple busses (1 controller
per bus) and multiple clients/slave devices per controller.
Signed-off-by: Kenneth Heitke khei...@codeaurora.org
Signed-off-by: Michael Bohan mbo...@codeaurora.org
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/Kconfig | 2 +
drivers/Makefile| 1 +
drivers/spmi/Kconfig| 9 +
drivers/spmi/Makefile | 4 +
drivers/spmi/spmi.c | 609
include/dt-bindings/spmi/spmi.h | 18 ++
include/linux/mod_devicetable.h | 8 +
include/linux/spmi.h| 191 +
8 files changed, 842 insertions(+)
create mode 100644 drivers/spmi/Kconfig
create mode 100644 drivers/spmi/Makefile
create mode 100644 drivers/spmi/spmi.c
create mode 100644 include/dt-bindings/spmi/spmi.h
create mode 100644 include/linux/spmi.h
diff --git a/drivers/Kconfig b/drivers/Kconfig
index b3138fb..e0a4ae6 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -52,6 +52,8 @@ source drivers/i2c/Kconfig
source drivers/spi/Kconfig
+source drivers/spmi/Kconfig
+
source drivers/hsi/Kconfig
source drivers/pps/Kconfig
diff --git a/drivers/Makefile b/drivers/Makefile
index 8e3b8b0..3d6de8b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_ATA) += ata/
obj-$(CONFIG_TARGET_CORE) += target/
obj-$(CONFIG_MTD) += mtd/
obj-$(CONFIG_SPI) += spi/
+obj-$(CONFIG_SPMI) += spmi/
obj-y += hsi/
obj-y += net/
obj-$(CONFIG_ATM) += atm/
diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
new file mode 100644
index 000..1dbfee0
--- /dev/null
+++ b/drivers/spmi/Kconfig
@@ -0,0 +1,9 @@
+#
+# SPMI driver configuration
+#
+menuconfig SPMI
+ tristate SPMI support
+ help
+ SPMI (System Power Management Interface) is a two-wire
+ serial interface between baseband and application processors
+ and Power Management Integrated Circuits (PMIC).
diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile
new file mode 100644
index 000..1de1acd
--- /dev/null
+++ b/drivers/spmi/Makefile
@@ -0,0 +1,4 @@
+#
+# Makefile for kernel SPMI framework.
+#
+obj-$(CONFIG_SPMI) += spmi.o
diff --git a/drivers/spmi/spmi.c b/drivers/spmi/spmi.c
new file mode 100644
index 000..6122c8f
--- /dev/null
+++ b/drivers/spmi/spmi.c
@@ -0,0 +1,609 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include linux/kernel.h
+#include linux/errno.h
+#include linux/idr.h
+#include linux/slab.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/platform_device.h
+#include linux/spmi.h
+#include linux/module.h
+#include linux/pm_runtime.h
+
+#include dt-bindings/spmi/spmi.h
+
+static DEFINE_IDA(ctrl_ida);
+
+static void spmi_dev_release(struct device *dev)
+{
+ struct spmi_device *sdev = to_spmi_device(dev);
+ kfree(sdev);
+}
+
+static const struct device_type spmi_dev_type = {
+ .release= spmi_dev_release,
+};
+
+static void spmi_ctrl_release(struct device *dev)
+{
+ struct spmi_controller *ctrl = to_spmi_controller(dev);
+ ida_simple_remove(ctrl_ida, ctrl-nr);
+ kfree(ctrl);
+}
+
+static const struct device_type spmi_ctrl_type = {
+ .release= spmi_ctrl_release,
+};
+
+#ifdef CONFIG_PM_RUNTIME
+static int spmi_runtime_suspend(struct device *dev)
+{
+ struct spmi_device *sdev = to_spmi_device(dev);
+ int err;
+
+ err = pm_generic_runtime_suspend(dev);
+ if (err)
+ return err;
+
+ return spmi_command_sleep(sdev);
+}
+
+static int spmi_runtime_resume(struct device *dev)
+{
+ struct spmi_device *sdev = to_spmi_device(dev);
+ int err;
+
+ err = spmi_command_wakeup(sdev);
+ if (err)
+ return err;
+
+ return pm_generic_runtime_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops spmi_pm_ops = {
+ SET_RUNTIME_PM_OPS(
+ spmi_runtime_suspend
Re: [Patch v5 1/2] dmaengine: add Qualcomm BAM dma driver
On Tue, Feb 11, 2014 at 11:00:48PM +0530, Vinod Koul wrote:
On Tue, Feb 04, 2014 at 02:42:35PM -0600, Andy Gross wrote:
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA
controller
found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip peripheral. Each
channel provides a uni-directional data transfer engine that is capable of
transferring data between the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
+++ b/drivers/dma/qcom_bam_dma.c
[..]
+static void bam_reset_channel(struct bam_chan *bchan)
+{
+ struct bam_device *bdev = bchan-bdev;
+
+ /* reset channel */
+ writel_relaxed(1, bdev-regs + BAM_P_RST(bchan-id));
+ writel_relaxed(0, bdev-regs + BAM_P_RST(bchan-id));
+
+ /* don't allow reorder of the channel reset */
+ wmb();
Documentation/memory-barriers.txt describes wmb() as a CPU barier but based on
above you want it to be a compiler barrier then you should do 1st write,
barrier(), second write.
It could also be that the intent was to prevent these writes from being
ordered before setting the initialized flag below, either way the
comment could be made clearer.
+
+ /* make sure hw is initialized when channel is used the first time */
+ bchan-initialized = 0;
+}
--
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hosted by The Linux Foundation
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Re: [Patch v5 1/2] dmaengine: add Qualcomm BAM dma driver
Ugh.
On Tue, Feb 11, 2014 at 11:49:10AM -0600, Josh Cartwright wrote:
On Tue, Feb 11, 2014 at 11:00:48PM +0530, Vinod Koul wrote:
On Tue, Feb 04, 2014 at 02:42:35PM -0600, Andy Gross wrote:
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA
controller
found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip peripheral.
Each
channel provides a uni-directional data transfer engine that is capable of
transferring data between the peripheral and system memory (System mode),
or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross agr...@codeaurora.org
+++ b/drivers/dma/qcom_bam_dma.c
[..]
+static void bam_reset_channel(struct bam_chan *bchan)
+{
+ struct bam_device *bdev = bchan-bdev;
+
+ /* reset channel */
+ writel_relaxed(1, bdev-regs + BAM_P_RST(bchan-id));
+ writel_relaxed(0, bdev-regs + BAM_P_RST(bchan-id));
+
+ /* don't allow reorder of the channel reset */
+ wmb();
Documentation/memory-barriers.txt describes wmb() as a CPU barier but based
on
above you want it to be a compiler barrier then you should do 1st write,
barrier(), second write.
It could also be that the intent was to prevent these writes from being
ordered before setting the initialized flag below, either way the
^ after
comment could be made clearer.
--
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Re: [PATCH 2/2] spi: Add Qualcomm QUP SPI controller support
On Fri, Feb 07, 2014 at 01:39:52AM -0600, Andy Gross wrote: On Thu, Feb 06, 2014 at 06:57:48PM +0200, Ivan T. Ivanov wrote: From: Ivan T. Ivanov iiva...@mm-sol.com Qualcomm Universal Peripheral (QUP) core is an AHB slave that provides a common data path (an output FIFO and an input FIFO) for serial peripheral interface (SPI) mini-core. SPI in master mode support up to 50MHz, up to four chip selects, and a programmable data path from 4 bits to 32 bits; MODE0..3 protocols Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com Cc: Alok Chauhan al...@codeaurora.org Cc: Gilad Avidov gavi...@codeaurora.org Cc: Kiran Gunda kgu...@codeaurora.org Cc: Sagar Dharia sdha...@codeaurora.org --- drivers/spi/Kconfig | 14 + drivers/spi/Makefile |1 + drivers/spi/spi-qup.c | 898 + 3 files changed, 913 insertions(+) create mode 100644 drivers/spi/spi-qup.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ba9310b..bf8ce6b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -381,6 +381,20 @@ config SPI_RSPI help SPI driver for Renesas RSPI blocks. +config SPI_QUP + tristate Qualcomm SPI Support with QUP interface + depends on ARCH_MSM I'd change to ARCH_MSM_DT. This ensures the OF component is there. I'd rather explicitly include the CONFIG_OF dependency, but I'm not too opinionated. config SPI_QUP tristate Qualcomm SPI Support with QUP interface depends on OF depends on ARM depends on ARCH_MSM_DT || COMPILE_TEST With Kumar's pending the ARCH_MSM_DT - ARCH_QCOM rename, we'll introduce a arm-soc/spi tree dependency here that we'll need to keep track of. Kumar- How would you like to handle this? Would it make sense for this to go through the SPI tree with depending on ARCH_QCOM instead of ARCH_MSM_DT? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] spi: Add Qualcomm QUP SPI controller support
On Fri, Feb 07, 2014 at 05:31:08PM +, Mark Brown wrote: On Fri, Feb 07, 2014 at 11:20:51AM -0600, Josh Cartwright wrote: On Fri, Feb 07, 2014 at 05:18:34PM +, Mark Brown wrote: On Fri, Feb 07, 2014 at 10:51:27AM -0600, Josh Cartwright wrote: config SPI_QUP tristate Qualcomm SPI Support with QUP interface depends on OF depends on ARM Does this really depend on ARM? If so why? The ARM dependency is there for the use of _relaxed io accessor variants. That's not ARM only and I thought we were getting generic versions of it anyway? ARMv8, MIPS, Microblaze, Hexagon and SH also define it. Okay, that's fair. I'm only vaguely familiar with the generic _relaxed variants, but until they land, how do we appropriately declare the dependency to prevent breaking COMPILE_TEST builds on architectures that don't have them? Or should we either bother? Do we need to introduce a HAVE_RELAXED_IO_ACCESSORS selected by those architectures with support? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 4/6] spmi: pmic_arb: add support for interrupt handling
On Tue, Feb 04, 2014 at 09:10:45PM +0100, Thomas Gleixner wrote:
On Mon, 3 Feb 2014, Josh Cartwright wrote:
+static void qpnpint_irq_ack(struct irq_data *d)
+{
+ struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
+ u8 irq = d-hwirq 8;
+ u8 apid = d-hwirq;
+ unsigned long flags;
+ u8 data;
+
+ spin_lock_irqsave(pa-lock, flags);
This wants to be a raw_spinlock - think about RT!
Indeed. I'll change this in the next revision.
Looks sane otherwise.
Great, thanks for taking a look!
Josh
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[PATCH v5 6/6] regmap: spmi: support base and extended register spaces
SPMI states that a slave may contain two register spaces, the Base
register space is a 5-bit byte-addressable space accessed via the
Register Read/Write and Register Zero Write command sequences, and the
Extended register space: a 16-bit byte-addressable space accessed via
the Extended Read/Write and Extended Read/Write Long command sequences.
Provide support for accessing both of these spaces, taking advantage of
the more bandwidth-efficient commands ('Register 0 Write' vs 'Register
Write', and 'Extended Register Read/Write' vs 'Extended Register
Read/Write Long') when possible.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
Acked-by: Mark Brown broo...@linaro.org
---
drivers/base/regmap/regmap-spmi.c | 228 --
include/linux/regmap.h| 12 +-
2 files changed, 205 insertions(+), 35 deletions(-)
diff --git a/drivers/base/regmap/regmap-spmi.c
b/drivers/base/regmap/regmap-spmi.c
index ac23910..d7026dc 100644
--- a/drivers/base/regmap/regmap-spmi.c
+++ b/drivers/base/regmap/regmap-spmi.c
@@ -22,69 +22,235 @@
#include linux/module.h
#include linux/init.h
-static int regmap_spmi_read(void *context,
- const void *reg, size_t reg_size,
- void *val, size_t val_size)
+static int regmap_spmi_base_read(void *context,
+const void *reg, size_t reg_size,
+void *val, size_t val_size)
{
+ u8 addr = *(u8 *)reg;
+ int err = 0;
+
+ BUG_ON(reg_size != 1);
+
+ while (val_size-- !err)
+ err = spmi_register_read(context, addr++, val++);
+
+ return err;
+}
+
+static int regmap_spmi_base_gather_write(void *context,
+const void *reg, size_t reg_size,
+const void *val, size_t val_size)
+{
+ const u8 *data = val;
+ u8 addr = *(u8 *)reg;
+ int err = 0;
+
+ BUG_ON(reg_size != 1);
+
+ /*
+* SPMI defines a more bandwidth-efficient 'Register 0 Write' sequence,
+* use it when possible.
+*/
+ if (addr == 0 val_size) {
+ err = spmi_register_zero_write(context, *data);
+ if (err)
+ goto err_out;
+
+ data++;
+ addr++;
+ val_size--;
+ }
+
+ while (val_size) {
+ err = spmi_register_write(context, addr, *data);
+ if (err)
+ goto err_out;
+
+ data++;
+ addr++;
+ val_size--;
+ }
+
+err_out:
+ return err;
+}
+
+static int regmap_spmi_base_write(void *context, const void *data,
+ size_t count)
+{
+ BUG_ON(count 1);
+ return regmap_spmi_base_gather_write(context, data, 1, data + 1,
+count - 1);
+}
+
+static struct regmap_bus regmap_spmi_base = {
+ .read = regmap_spmi_base_read,
+ .write = regmap_spmi_base_write,
+ .gather_write = regmap_spmi_base_gather_write,
+ .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
+ .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
+};
+
+/**
+ * regmap_init_spmi_base(): Create regmap for the Base register space
+ * @sdev: SPMI device that will be interacted with
+ * @config:Configuration for register map
+ *
+ * The return value will be an ERR_PTR() on error or a valid pointer to
+ * a struct regmap.
+ */
+struct regmap *regmap_init_spmi_base(struct spmi_device *sdev,
+const struct regmap_config *config)
+{
+ return regmap_init(sdev-dev, regmap_spmi_base, sdev, config);
+}
+EXPORT_SYMBOL_GPL(regmap_init_spmi_base);
+
+/**
+ * devm_regmap_init_spmi_base(): Create managed regmap for Base register space
+ * @sdev: SPMI device that will be interacted with
+ * @config:Configuration for register map
+ *
+ * The return value will be an ERR_PTR() on error or a valid pointer
+ * to a struct regmap. The regmap will be automatically freed by the
+ * device management code.
+ */
+struct regmap *devm_regmap_init_spmi_base(struct spmi_device *sdev,
+ const struct regmap_config *config)
+{
+ return devm_regmap_init(sdev-dev, regmap_spmi_base, sdev, config);
+}
+EXPORT_SYMBOL_GPL(devm_regmap_init_spmi_base);
+
+static int regmap_spmi_ext_read(void *context,
+ const void *reg, size_t reg_size,
+ void *val, size_t val_size)
+{
+ int err = 0;
+ size_t len;
+ u16 addr;
+
BUG_ON(reg_size != 2);
- return spmi_ext_register_readl(context, *(u16 *)reg,
- val, val_size);
+
+ addr = *(u16 *)reg;
+
+ /*
+* Split accesses into two to take
[PATCH v5 3/6] spmi: Add MSM PMIC Arbiter SPMI controller
From: Kenneth Heitke khei...@codeaurora.org
Qualcomm's PMIC Arbiter SPMI controller functions as a bus master and
is used to communication with one or more PMIC (slave) devices on the
SPMI bus. The PMIC Arbiter is actually a hardware wrapper around the
SPMI controller that provides concurrent and autonomous PMIC access
to various entities that need to communicate with the PMIC.
The SPMI controller hardware handles all of the SPMI bus activity (bus
arbitration, sequence start condition, transmission of frames, etc).
This software driver uses the PMIC Arbiter register interface to
initiate command sequences on the SPMI bus. The status register is
read to determine when the command sequence has completed and whether
or not it completed successfully.
Signed-off-by: Kenneth Heitke khei...@codeaurora.org
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/spmi/Kconfig | 17 ++
drivers/spmi/Makefile| 2 +
drivers/spmi/spmi-pmic-arb.c | 405 +++
3 files changed, 424 insertions(+)
create mode 100644 drivers/spmi/spmi-pmic-arb.c
diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
index 1dbfee0..80b7901 100644
--- a/drivers/spmi/Kconfig
+++ b/drivers/spmi/Kconfig
@@ -7,3 +7,20 @@ menuconfig SPMI
SPMI (System Power Management Interface) is a two-wire
serial interface between baseband and application processors
and Power Management Integrated Circuits (PMIC).
+
+if SPMI
+
+config SPMI_MSM_PMIC_ARB
+ tristate Qualcomm MSM SPMI Controller (PMIC Arbiter)
+ depends on ARM
+ depends on ARCH_MSM || COMPILE_TEST
+ default ARCH_MSM
+ help
+ If you say yes to this option, support will be included for the
+ built-in SPMI PMIC Arbiter interface on Qualcomm MSM family
+ processors.
+
+ This is required for communicating with Qualcomm PMICs and
+ other devices that have the SPMI interface.
+
+endif
diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile
index 1de1acd..fc75104 100644
--- a/drivers/spmi/Makefile
+++ b/drivers/spmi/Makefile
@@ -2,3 +2,5 @@
# Makefile for kernel SPMI framework.
#
obj-$(CONFIG_SPMI) += spmi.o
+
+obj-$(CONFIG_SPMI_MSM_PMIC_ARB)+= spmi-pmic-arb.o
diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
new file mode 100644
index 000..b7f753f
--- /dev/null
+++ b/drivers/spmi/spmi-pmic-arb.c
@@ -0,0 +1,405 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include linux/delay.h
+#include linux/err.h
+#include linux/interrupt.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/slab.h
+#include linux/spmi.h
+
+/* PMIC Arbiter configuration registers */
+#define PMIC_ARB_VERSION 0x
+#define PMIC_ARB_INT_EN0x0004
+
+/* PMIC Arbiter channel registers */
+#define PMIC_ARB_CMD(N)(0x0800 + (0x80 * (N)))
+#define PMIC_ARB_CONFIG(N) (0x0804 + (0x80 * (N)))
+#define PMIC_ARB_STATUS(N) (0x0808 + (0x80 * (N)))
+#define PMIC_ARB_WDATA0(N) (0x0810 + (0x80 * (N)))
+#define PMIC_ARB_WDATA1(N) (0x0814 + (0x80 * (N)))
+#define PMIC_ARB_RDATA0(N) (0x0818 + (0x80 * (N)))
+#define PMIC_ARB_RDATA1(N) (0x081C + (0x80 * (N)))
+
+/* Interrupt Controller */
+#define SPMI_PIC_OWNER_ACC_STATUS(M, N)(0x + ((32 * (M)) + (4 *
(N
+#define SPMI_PIC_ACC_ENABLE(N) (0x0200 + (4 * (N)))
+#define SPMI_PIC_IRQ_STATUS(N) (0x0600 + (4 * (N)))
+#define SPMI_PIC_IRQ_CLEAR(N) (0x0A00 + (4 * (N)))
+
+/* Mapping Table */
+#define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N)))
+#define SPMI_MAPPING_BIT_INDEX(X) (((X) 18) 0xF)
+#define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) 17) 0x1)
+#define SPMI_MAPPING_BIT_IS_0_RESULT(X)(((X) 9) 0xFF)
+#define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) 8) 0x1)
+#define SPMI_MAPPING_BIT_IS_1_RESULT(X)(((X) 0) 0xFF)
+
+#define SPMI_MAPPING_TABLE_LEN 255
+#define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */
+
+/* Ownership Table */
+#define SPMI_OWNERSHIP_TABLE_REG(N)(0x0700 + (4 * (N)))
+#define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) 0x7)
+
+/* Channel Status fields */
+enum pmic_arb_chnl_status {
+ PMIC_ARB_STATUS_DONE= (1 0),
+ PMIC_ARB_STATUS_FAILURE = (1 1
[PATCH v5 0/6] Add support for the System Power Management Interface (SPMI)
The System Power Management Interface (SPMI) is a high-speed,
low-latency, bi-directional, two-wire serial bus suitable for real-time
control of voltage and frequency scaled multi-core application
processors and its power management of auxiliary components. SPMI
obsoletes a number of legacy, custom point-to-point interfaces and
provides a low pin count, high-speed control bus for up to 4 Master and
16 Slave devices.
SPMI is specified by the MIPI (Mobile Industry Process Interface)
Alliance [1].
This patchset is intended both to provide a core implementation of SPMI and
also to provide a controller driver implementation.
- Patches 1-2 implement the SPMI core functionality and provide basic
DT binding documentation
- Patches 3-5 provide an implementation of an SPMI controller, the
Qualcomm SPMI PMIC Arbiter, currently used on the 8x74 SoCs.
- Patch 6 rounds out regmap support for SPMI
Changes from v4[2]:
- Fixed a few minor error-handling bugs found with further testing
- Addressed Courtney Cavin's feedback regarding device tree bindings
- Reworked Kconfig options a bit (allow for building PMIC arb when
COMPILE_TEST=y)
Changes from v3[3]:
- Dropped the pm8x41 PMIC driver and pm8xxx-rtc changes as part of this
patchset.
(will be sent out separately)
- Rebased on v3.13-rc2
- Move to simple_ida_* for controller ID allocation
- Addressed documentation fixes and nits
- Provide pm_runtime implementation, which leverages SPMI's SLEEP and WAKEUP
commands
- Address spmi_controller object lifetime issues
Changes from v2[4]:
- Dropped RFC.
- Add basic regmap support at Mark Brown's suggestion
- Drop debugfs interface. Debugging SPMI accesses can happen via the regmap
debugfs interface if necessary.
- Add second address-cell in SPMI generic device tree binding, encoding the
address type (suggestion by Stephen Warren)
- Implement interrupt handling functionality within the PMIC Arbiter driver
- Provide basic MFD driver for the PMIC8x41 PMICs, demonstrating SPMI regmap
client use
- Adapt existing pm8xxx-rtc driver to work as a child of the PM8x41 mfd device
Changes from v1[5]:
- Adopted patch (1/5) to #define for_each_available_node() shim
in the !CONFIG_OF case
- Moved device tree logic out of drivers/of and into spmi.c core (this
mirrors what SPI is doing, and what i2c will soon be doing)
- Move of_spmi_add_devices() call into spmi_device_add(), so drivers don't
have to call it explicitly
- Unconditionally build in debugfs code (rely on the underlying
CONFIG_DEBUG_FS switch to throw unused code away)
- Change pr_* print functions to their dev_* equivalents
- Fix copy_{to,from}_user error handling
- Renamed board_lock to ctrl_idr_lock to better describe it's purpose
- Rework device object lifetime management
- Rename PMIC arb binding document, add description of PMIC arb
- Add generic SPMI device tree bindings
[1]: http://www.mipi.org/specifications/system-power-management-interface
[2]: http://lkml.kernel.org/r/cover.1389738151.git.jo...@codeaurora.org
[3]: http://lkml.kernel.org/r/cover.1382985169.git.jo...@codeaurora.org
[4]: http://lkml.kernel.org/r/cover.1377202730.git.jo...@codeaurora.org
[5]: http://lkml.kernel.org/r/cover.1376596224.git.jo...@codeaurora.org
Josh Cartwright (4):
spmi: add generic SPMI controller binding documentation
spmi: pmic_arb: add support for interrupt handling
spmi: document the PMIC arbiter SPMI bindings
regmap: spmi: support base and extended register spaces
Kenneth Heitke (2):
spmi: Linux driver framework for SPMI
spmi: Add MSM PMIC Arbiter SPMI controller
.../bindings/spmi/qcom,spmi-pmic-arb.txt | 60 ++
Documentation/devicetree/bindings/spmi/spmi.txt| 41 ++
drivers/Kconfig| 2 +
drivers/Makefile | 1 +
drivers/base/regmap/regmap-spmi.c | 228 +-
drivers/spmi/Kconfig | 24 +
drivers/spmi/Makefile | 6 +
drivers/spmi/spmi-pmic-arb.c | 778 +
drivers/spmi/spmi.c| 609
include/dt-bindings/spmi/spmi.h| 18 +
include/linux/mod_devicetable.h| 8 +
include/linux/regmap.h | 12 +-
include/linux/spmi.h | 191 +
13 files changed, 1943 insertions(+), 35 deletions(-)
create mode 100644
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
create mode 100644 Documentation/devicetree/bindings/spmi/spmi.txt
create mode 100644 drivers/spmi/Kconfig
create mode 100644 drivers/spmi/Makefile
create mode 100644 drivers/spmi/spmi-pmic-arb.c
create mode 100644 drivers/spmi/spmi.c
create mode 100644 include/dt-bindings/spmi/spmi.h
create mode 100644 include/linux/spmi.h
--
Qualcomm Innovation Center
[PATCH v5 5/6] spmi: document the PMIC arbiter SPMI bindings
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
.../bindings/spmi/qcom,spmi-pmic-arb.txt | 60 ++
1 file changed, 60 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
new file mode 100644
index 000..a0a5759
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
@@ -0,0 +1,60 @@
+Qualcomm SPMI Controller (PMIC Arbiter)
+
+The SPMI PMIC Arbiter is found on the Snapdragon 800 Series. It is an SPMI
+controller with wrapping arbitration logic to allow for multiple on-chip
+devices to control a single SPMI master.
+
+The PMIC Arbiter can also act as an interrupt controller, providing interrupts
+to slave devices.
+
+See spmi.txt for the generic SPMI controller binding requirements for child
+nodes.
+
+See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
+generic interrupt controller binding documentation.
+
+Required properties:
+- compatible : should be qcom,spmi-pmic-arb.
+- reg-names : should be core, intr, cnfg
+- reg : register specifiers, must contain:
+ core - core registers
+ intr - interrupt controller registers
+ cnfg - configuration registers
+- #address-cells : must be set to 2
+- #size-cells : must be set to 0
+- qcom,ee : indicates the active Execution Environment identifier (0-5)
+- qcom,channel : which of the PMIC Arb provided channels to use for accesses
(0-5)
+- interrupts : interrupt list for the PMIC Arb controller, must contain a
+ single interrupt entry for the peripheral interrupt
+- interrupt-names : corresponding interrupt names for the interrupts
+listed in the 'interrupts' property, must contain:
+ periph_irq - summary interrupt for PMIC peripherals
+- interrupt-controller : boolean indicator that the PMIC arbiter is an
interrupt controller
+- #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple:
+cell 1: slave ID for the requested interrupt (0-15)
+cell 2: peripheral ID for requested interrupt (0-255)
+cell 3: the requested peripheral interrupt (0-7)
+cell 4: interrupt flags indicating level-sense information, as defined in
+dt-bindings/interrupt-controller/irq.h
+
+Example:
+
+ spmi {
+ compatible = qcom,spmi-pmic-arb;
+ reg-names = core, intr, cnfg;
+ reg = 0xfc4cf000 0x1000,
+ 0xfc4cb000 0x1000,
+ 0xfc4ca000 0x1000;
+
+ interrupt-names = periph_irq;
+ interrupts = 0 190 0;
+
+ qcom,ee = 0;
+ qcom,channel = 0;
+
+ #address-cells = 2;
+ #size-cells = 0;
+
+ interrupt-controller;
+ #interrupt-cells = 4;
+ };
--
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[PATCH v5 4/6] spmi: pmic_arb: add support for interrupt handling
The Qualcomm PMIC Arbiter, in addition to being a basic SPMI controller,
also implements interrupt handling for slave devices. Note, this is
outside the scope of SPMI, as SPMI leaves interrupt handling completely
unspecified.
Extend the driver to provide a irq_chip implementation and chained irq
handling which allows for these interrupts to be used.
Cc: Thomas Gleixner t...@linutronix.de
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/spmi/Kconfig | 1 +
drivers/spmi/spmi-pmic-arb.c | 377 ++-
2 files changed, 376 insertions(+), 2 deletions(-)
diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
index 80b7901..075bd79 100644
--- a/drivers/spmi/Kconfig
+++ b/drivers/spmi/Kconfig
@@ -13,6 +13,7 @@ if SPMI
config SPMI_MSM_PMIC_ARB
tristate Qualcomm MSM SPMI Controller (PMIC Arbiter)
depends on ARM
+ depends on IRQ_DOMAIN
depends on ARCH_MSM || COMPILE_TEST
default ARCH_MSM
help
diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
index b7f753f..e4b6854 100644
--- a/drivers/spmi/spmi-pmic-arb.c
+++ b/drivers/spmi/spmi-pmic-arb.c
@@ -13,6 +13,9 @@
#include linux/err.h
#include linux/interrupt.h
#include linux/io.h
+#include linux/irqchip/chained_irq.h
+#include linux/irqdomain.h
+#include linux/irq.h
#include linux/kernel.h
#include linux/module.h
#include linux/of.h
@@ -103,6 +106,14 @@ enum pmic_arb_cmd_op_code {
* @cnfg: address of the PMIC Arbiter configuration registers.
* @lock: lock to synchronize accesses.
* @channel: which channel to use for accesses.
+ * @irq: PMIC ARB interrupt.
+ * @ee:the current Execution Environment
+ * @min_apid: minimum APID (used for bounding IRQ search)
+ * @max_apid: maximum APID
+ * @mapping_table: in-memory copy of PPID - APID mapping table.
+ * @domain:irq domain object for PMIC IRQ domain
+ * @spmic: SPMI controller object
+ * @apid_to_ppid: cached mapping from APID to PPID
*/
struct spmi_pmic_arb_dev {
void __iomem*base;
@@ -110,6 +121,14 @@ struct spmi_pmic_arb_dev {
void __iomem*cnfg;
spinlock_t lock;
u8 channel;
+ int irq;
+ u8 ee;
+ u8 min_apid;
+ u8 max_apid;
+ u32 mapping_table[SPMI_MAPPING_TABLE_LEN];
+ struct irq_domain *domain;
+ struct spmi_controller *spmic;
+ u16 apid_to_ppid[256];
};
static inline u32 pmic_arb_base_read(struct spmi_pmic_arb_dev *dev, u32 offset)
@@ -306,12 +325,316 @@ static int pmic_arb_write_cmd(struct spmi_controller
*ctrl, u8 opc, u8 sid,
return rc;
}
+enum qpnpint_regs {
+ QPNPINT_REG_RT_STS = 0x10,
+ QPNPINT_REG_SET_TYPE= 0x11,
+ QPNPINT_REG_POLARITY_HIGH = 0x12,
+ QPNPINT_REG_POLARITY_LOW= 0x13,
+ QPNPINT_REG_LATCHED_CLR = 0x14,
+ QPNPINT_REG_EN_SET = 0x15,
+ QPNPINT_REG_EN_CLR = 0x16,
+ QPNPINT_REG_LATCHED_STS = 0x18,
+};
+
+struct spmi_pmic_arb_qpnpint_type {
+ u8 type; /* 1 - edge */
+ u8 polarity_high;
+ u8 polarity_low;
+} __packed;
+
+/* Simplified accessor functions for irqchip callbacks */
+static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
+ size_t len)
+{
+ struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
+ u8 sid = d-hwirq 24;
+ u8 per = d-hwirq 16;
+
+ if (pmic_arb_write_cmd(pa-spmic, SPMI_CMD_EXT_WRITEL, sid,
+ (per 8) + reg, buf, len))
+ dev_err_ratelimited(pa-spmic-dev,
+ failed irqchip transaction on %x\n,
+ d-irq);
+}
+
+static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t
len)
+{
+ struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
+ u8 sid = d-hwirq 24;
+ u8 per = d-hwirq 16;
+
+ if (pmic_arb_read_cmd(pa-spmic, SPMI_CMD_EXT_READL, sid,
+ (per 8) + reg, buf, len))
+ dev_err_ratelimited(pa-spmic-dev,
+ failed irqchip transaction on %x\n,
+ d-irq);
+}
+
+static void periph_interrupt(struct spmi_pmic_arb_dev *pa, u8 apid)
+{
+ unsigned int irq;
+ u32 status;
+ int id;
+
+ status = readl_relaxed(pa-intr + SPMI_PIC_IRQ_STATUS(apid));
+ while (status) {
+ id = ffs(status) - 1;
+ status = ~(1 id);
+ irq = irq_find_mapping(pa-domain,
+ pa-apid_to_ppid[apid
[PATCH v5 1/6] spmi: Linux driver framework for SPMI
From: Kenneth Heitke khei...@codeaurora.org
System Power Management Interface (SPMI) is a specification
developed by the MIPI (Mobile Industry Process Interface) Alliance
optimized for the real time control of Power Management ICs (PMIC).
SPMI is a two-wire serial interface that supports up to 4 master
devices and up to 16 logical slaves.
The framework supports message APIs, multiple busses (1 controller
per bus) and multiple clients/slave devices per controller.
Signed-off-by: Kenneth Heitke khei...@codeaurora.org
Signed-off-by: Michael Bohan mbo...@codeaurora.org
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/Kconfig | 2 +
drivers/Makefile| 1 +
drivers/spmi/Kconfig| 9 +
drivers/spmi/Makefile | 4 +
drivers/spmi/spmi.c | 609
include/dt-bindings/spmi/spmi.h | 18 ++
include/linux/mod_devicetable.h | 8 +
include/linux/spmi.h| 191 +
8 files changed, 842 insertions(+)
create mode 100644 drivers/spmi/Kconfig
create mode 100644 drivers/spmi/Makefile
create mode 100644 drivers/spmi/spmi.c
create mode 100644 include/dt-bindings/spmi/spmi.h
create mode 100644 include/linux/spmi.h
diff --git a/drivers/Kconfig b/drivers/Kconfig
index b3138fb..e0a4ae6 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -52,6 +52,8 @@ source drivers/i2c/Kconfig
source drivers/spi/Kconfig
+source drivers/spmi/Kconfig
+
source drivers/hsi/Kconfig
source drivers/pps/Kconfig
diff --git a/drivers/Makefile b/drivers/Makefile
index 8e3b8b0..3d6de8b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_ATA) += ata/
obj-$(CONFIG_TARGET_CORE) += target/
obj-$(CONFIG_MTD) += mtd/
obj-$(CONFIG_SPI) += spi/
+obj-$(CONFIG_SPMI) += spmi/
obj-y += hsi/
obj-y += net/
obj-$(CONFIG_ATM) += atm/
diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
new file mode 100644
index 000..1dbfee0
--- /dev/null
+++ b/drivers/spmi/Kconfig
@@ -0,0 +1,9 @@
+#
+# SPMI driver configuration
+#
+menuconfig SPMI
+ tristate SPMI support
+ help
+ SPMI (System Power Management Interface) is a two-wire
+ serial interface between baseband and application processors
+ and Power Management Integrated Circuits (PMIC).
diff --git a/drivers/spmi/Makefile b/drivers/spmi/Makefile
new file mode 100644
index 000..1de1acd
--- /dev/null
+++ b/drivers/spmi/Makefile
@@ -0,0 +1,4 @@
+#
+# Makefile for kernel SPMI framework.
+#
+obj-$(CONFIG_SPMI) += spmi.o
diff --git a/drivers/spmi/spmi.c b/drivers/spmi/spmi.c
new file mode 100644
index 000..6122c8f
--- /dev/null
+++ b/drivers/spmi/spmi.c
@@ -0,0 +1,609 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include linux/kernel.h
+#include linux/errno.h
+#include linux/idr.h
+#include linux/slab.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/platform_device.h
+#include linux/spmi.h
+#include linux/module.h
+#include linux/pm_runtime.h
+
+#include dt-bindings/spmi/spmi.h
+
+static DEFINE_IDA(ctrl_ida);
+
+static void spmi_dev_release(struct device *dev)
+{
+ struct spmi_device *sdev = to_spmi_device(dev);
+ kfree(sdev);
+}
+
+static const struct device_type spmi_dev_type = {
+ .release= spmi_dev_release,
+};
+
+static void spmi_ctrl_release(struct device *dev)
+{
+ struct spmi_controller *ctrl = to_spmi_controller(dev);
+ ida_simple_remove(ctrl_ida, ctrl-nr);
+ kfree(ctrl);
+}
+
+static const struct device_type spmi_ctrl_type = {
+ .release= spmi_ctrl_release,
+};
+
+#ifdef CONFIG_PM_RUNTIME
+static int spmi_runtime_suspend(struct device *dev)
+{
+ struct spmi_device *sdev = to_spmi_device(dev);
+ int err;
+
+ err = pm_generic_runtime_suspend(dev);
+ if (err)
+ return err;
+
+ return spmi_command_sleep(sdev);
+}
+
+static int spmi_runtime_resume(struct device *dev)
+{
+ struct spmi_device *sdev = to_spmi_device(dev);
+ int err;
+
+ err = spmi_command_wakeup(sdev);
+ if (err)
+ return err;
+
+ return pm_generic_runtime_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops spmi_pm_ops = {
+ SET_RUNTIME_PM_OPS(
+ spmi_runtime_suspend
[PATCH v5 2/6] spmi: add generic SPMI controller binding documentation
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
Documentation/devicetree/bindings/spmi/spmi.txt | 41 +
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spmi/spmi.txt
diff --git a/Documentation/devicetree/bindings/spmi/spmi.txt
b/Documentation/devicetree/bindings/spmi/spmi.txt
new file mode 100644
index 000..462a42f
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/spmi.txt
@@ -0,0 +1,41 @@
+System Power Management Interface (SPMI) Controller
+
+This document defines a generic set of bindings for use by SPMI controllers. A
+controller is modelled in device tree as a node with zero or more child nodes,
+each representing a unique slave on the bus.
+
+Required properties:
+- #address-cells : must be set to 2
+- #size-cells : must be set to 0
+
+Child nodes:
+
+An SPMI controller node can contain zero or more child nodes representing slave
+devices on the bus. Child 'reg' properties are specified as an address, type
+pair. The address must be in the range 0-15 (4 bits). The type must be one of
+SPMI_USID (0) or SPMI_GSID (1) for Unique Slave ID or Group Slave ID
respectively.
+These are the identifiers statically assigned by the system integrator, as
+per the SPMI spec.
+
+Each child node must have one and only one 'reg' entry of type SPMI_USID.
+
+#include dt-bindings/spmi/spmi.h
+
+ spmi@.. {
+ compatible = ...;
+ reg = ...;
+
+ #address-cells = 2;
+ #size-cells 0;
+
+ child@0 {
+ compatible = ...;
+ reg = 0 SPMI_USID;
+ };
+
+ child@7 {
+ compatible = ...;
+ reg = 7 SPMI_USID
+ 3 SPMI_GSID;
+ };
+ };
--
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[PATCH] usb: phy: msm: fix compilation errors when !CONFIG_PM_SLEEP
Both the PM_RUNTIME and PM_SLEEP callbacks call into the common
msm_otg_{suspend,resume} routines, however these routines are only being
built when CONFIG_PM_SLEEP. In addition, msm_otg_{suspend,resume} also
depends on msm_hsusb_config_vddcx(), which is only built when
CONFIG_PM_SLEEP.
Fix the CONFIG_PM_RUNTIME, !CONFIG_PM_SLEEP case by changing the
preprocessor conditional, and moving msm_hsusb_config_vddcx().
While we're here, eliminate the CONFIG_PM conditional for setting
up the dev_pm_ops.
This address the following errors Russell King has hit doing randconfig
builds:
drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_suspend':
drivers/usb/phy/phy-msm-usb.c:1691:2: error: implicit declaration of function
'msm_otg_suspend'
drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_resume':
drivers/usb/phy/phy-msm-usb.c:1699:2: error: implicit declaration of function
'msm_otg_resume'
Cc: Ivan T. Ivanov iiva...@mm-sol.com
Reported-by: Russell King rmk+ker...@arm.linux.org.uk
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/usb/phy/phy-msm-usb.c | 57 ---
1 file changed, 26 insertions(+), 31 deletions(-)
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 8546c8d..7c7384f 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -159,32 +159,6 @@ put_3p3:
return rc;
}
-#ifdef CONFIG_PM_SLEEP
-#define USB_PHY_SUSP_DIG_VOL 50
-static int msm_hsusb_config_vddcx(int high)
-{
- int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
- int min_vol;
- int ret;
-
- if (high)
- min_vol = USB_PHY_VDD_DIG_VOL_MIN;
- else
- min_vol = USB_PHY_SUSP_DIG_VOL;
-
- ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
- if (ret) {
- pr_err(%s: unable to set the voltage for regulator
- HSUSB_VDDCX\n, __func__);
- return ret;
- }
-
- pr_debug(%s: min_vol:%d max_vol:%d\n, __func__, min_vol, max_vol);
-
- return ret;
-}
-#endif
-
static int msm_hsusb_ldo_set_mode(int on)
{
int ret = 0;
@@ -440,7 +414,32 @@ static int msm_otg_reset(struct usb_phy *phy)
#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
#define PHY_RESUME_TIMEOUT_USEC(100 * 1000)
-#ifdef CONFIG_PM_SLEEP
+#if defined(CONFIG_PM_SLEEP) || defined(CONFIG_PM_RUNTIME)
+
+#define USB_PHY_SUSP_DIG_VOL 50
+static int msm_hsusb_config_vddcx(int high)
+{
+ int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
+ int min_vol;
+ int ret;
+
+ if (high)
+ min_vol = USB_PHY_VDD_DIG_VOL_MIN;
+ else
+ min_vol = USB_PHY_SUSP_DIG_VOL;
+
+ ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
+ if (ret) {
+ pr_err(%s: unable to set the voltage for regulator
+ HSUSB_VDDCX\n, __func__);
+ return ret;
+ }
+
+ pr_debug(%s: min_vol:%d max_vol:%d\n, __func__, min_vol, max_vol);
+
+ return ret;
+}
+
static int msm_otg_suspend(struct msm_otg *motg)
{
struct usb_phy *phy = motg-phy;
@@ -1733,22 +1732,18 @@ static int msm_otg_pm_resume(struct device *dev)
}
#endif
-#ifdef CONFIG_PM
static const struct dev_pm_ops msm_otg_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
msm_otg_runtime_idle)
};
-#endif
static struct platform_driver msm_otg_driver = {
.remove = msm_otg_remove,
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
-#ifdef CONFIG_PM
.pm = msm_otg_dev_pm_ops,
-#endif
},
};
--
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[PATCH v2] usb: phy: msm: fix compilation errors when !CONFIG_PM_SLEEP
Both the PM_RUNTIME and PM_SLEEP callbacks call into the common
msm_otg_{suspend,resume} routines, however these routines are only being
built when CONFIG_PM_SLEEP. In addition, msm_otg_{suspend,resume} also
depends on msm_hsusb_config_vddcx(), which is only built when
CONFIG_PM_SLEEP.
Fix the CONFIG_PM_RUNTIME, !CONFIG_PM_SLEEP case by changing the
preprocessor conditional, and moving msm_hsusb_config_vddcx().
While we're here, eliminate the CONFIG_PM conditional for setting
up the dev_pm_ops.
This address the following errors Russell King has hit doing randconfig
builds:
drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_suspend':
drivers/usb/phy/phy-msm-usb.c:1691:2: error: implicit declaration of function
'msm_otg_suspend'
drivers/usb/phy/phy-msm-usb.c: In function 'msm_otg_runtime_resume':
drivers/usb/phy/phy-msm-usb.c:1699:2: error: implicit declaration of function
'msm_otg_resume'
Cc: Ivan T. Ivanov iiva...@mm-sol.com
Reported-by: Russell King rmk+ker...@arm.linux.org.uk
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
v1-v2: Change conditional to simply CONFIG_PM (thanks ccov and khilman!)
drivers/usb/phy/phy-msm-usb.c | 57 ---
1 file changed, 26 insertions(+), 31 deletions(-)
diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c
index 8546c8d..5b169a7 100644
--- a/drivers/usb/phy/phy-msm-usb.c
+++ b/drivers/usb/phy/phy-msm-usb.c
@@ -159,32 +159,6 @@ put_3p3:
return rc;
}
-#ifdef CONFIG_PM_SLEEP
-#define USB_PHY_SUSP_DIG_VOL 50
-static int msm_hsusb_config_vddcx(int high)
-{
- int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
- int min_vol;
- int ret;
-
- if (high)
- min_vol = USB_PHY_VDD_DIG_VOL_MIN;
- else
- min_vol = USB_PHY_SUSP_DIG_VOL;
-
- ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
- if (ret) {
- pr_err(%s: unable to set the voltage for regulator
- HSUSB_VDDCX\n, __func__);
- return ret;
- }
-
- pr_debug(%s: min_vol:%d max_vol:%d\n, __func__, min_vol, max_vol);
-
- return ret;
-}
-#endif
-
static int msm_hsusb_ldo_set_mode(int on)
{
int ret = 0;
@@ -440,7 +414,32 @@ static int msm_otg_reset(struct usb_phy *phy)
#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
#define PHY_RESUME_TIMEOUT_USEC(100 * 1000)
-#ifdef CONFIG_PM_SLEEP
+#if CONFIG_PM
+
+#define USB_PHY_SUSP_DIG_VOL 50
+static int msm_hsusb_config_vddcx(int high)
+{
+ int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
+ int min_vol;
+ int ret;
+
+ if (high)
+ min_vol = USB_PHY_VDD_DIG_VOL_MIN;
+ else
+ min_vol = USB_PHY_SUSP_DIG_VOL;
+
+ ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
+ if (ret) {
+ pr_err(%s: unable to set the voltage for regulator
+ HSUSB_VDDCX\n, __func__);
+ return ret;
+ }
+
+ pr_debug(%s: min_vol:%d max_vol:%d\n, __func__, min_vol, max_vol);
+
+ return ret;
+}
+
static int msm_otg_suspend(struct msm_otg *motg)
{
struct usb_phy *phy = motg-phy;
@@ -1733,22 +1732,18 @@ static int msm_otg_pm_resume(struct device *dev)
}
#endif
-#ifdef CONFIG_PM
static const struct dev_pm_ops msm_otg_dev_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
msm_otg_runtime_idle)
};
-#endif
static struct platform_driver msm_otg_driver = {
.remove = msm_otg_remove,
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
-#ifdef CONFIG_PM
.pm = msm_otg_dev_pm_ops,
-#endif
},
};
--
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