RE: [PATCHv2 RESEND] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value

2014-03-10 Thread Chew, Chiau Ee 

> Subject: [PATCHv2 RESEND] i2c: designware-pci: set ideal HCNT, LCNT and SDA
> hold time value
> 
> From: Chew, Chiau Ee 
> 
> On Intel BayTrail, there was case whereby the resulting fast mode bus speed
> becomes slower (~20% slower compared to expected speed) if using the
> HCNT/LCNT calculated in the core layer. Thus, this patch is added to allow pci
> glue layer to pass in optimal HCNT/LCNT/SDA hold time values to core layer
> since the core layer supports cofigurable HCNT/LCNT/SDA hold time values
> now.
> 
> Signed-off-by: Chew, Chiau Ee 
> ---
> v2 changelog:
> * Add 'dw_' prefix to struct scl_sda_cfg
> * Add Baytrail HCNT/LCNT/SDA hold time values directly in the
>   struct instead of using macro definition
> * Replace tab before "=" with space in struct
> 
>  drivers/i2c/busses/i2c-designware-pcidrv.c |   28
> 
>  1 files changed, 28 insertions(+), 0 deletions(-)
> 

I have misplaced the changelog in the previous v2 patch which would cause the 
removal of signed-off-by line. I'm resending this to fix that problem. Sorry 
for any confusion and inconvenience caused.


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[PATCHv2 RESEND] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value

2014-03-10 Thread Chew Chiau Ee 
From: Chew, Chiau Ee 

On Intel BayTrail, there was case whereby the resulting fast mode
bus speed becomes slower (~20% slower compared to expected speed)
if using the HCNT/LCNT calculated in the core layer. Thus, this
patch is added to allow pci glue layer to pass in optimal
HCNT/LCNT/SDA hold time values to core layer since the core
layer supports cofigurable HCNT/LCNT/SDA hold time values now.

Signed-off-by: Chew, Chiau Ee 
---
v2 changelog:
* Add 'dw_' prefix to struct scl_sda_cfg
* Add Baytrail HCNT/LCNT/SDA hold time values directly in the
  struct instead of using macro definition
* Replace tab before "=" with space in struct

 drivers/i2c/busses/i2c-designware-pcidrv.c |   28 
 1 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c 
b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 094509bc..91d468f 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -58,6 +58,14 @@ enum dw_pci_ctl_id_t {
baytrail,
 };
 
+struct dw_scl_sda_cfg {
+   u32 ss_hcnt;
+   u32 fs_hcnt;
+   u32 ss_lcnt;
+   u32 fs_lcnt;
+   u32 sda_hold;
+};
+
 struct dw_pci_controller {
u32 bus_num;
u32 bus_cfg;
@@ -65,6 +73,7 @@ struct dw_pci_controller {
u32 rx_fifo_depth;
u32 clk_khz;
u32 functionality;
+   struct dw_scl_sda_cfg *scl_sda_cfg;
 };
 
 #define INTEL_MID_STD_CFG  (DW_IC_CON_MASTER | \
@@ -77,6 +86,15 @@ struct dw_pci_controller {
I2C_FUNC_SMBUS_WORD_DATA |  \
I2C_FUNC_SMBUS_I2C_BLOCK)
 
+/* BayTrail HCNT/LCNT/SDA hold time */
+static struct dw_scl_sda_cfg byt_config = {
+   .ss_hcnt = 0x200,
+   .fs_hcnt = 0x55,
+   .ss_lcnt = 0x200,
+   .fs_lcnt = 0x99,
+   .sda_hold = 0x6,
+};
+
 static struct  dw_pci_controller  dw_pci_controllers[] = {
[moorestown_0] = {
.bus_num = 0,
@@ -148,6 +166,7 @@ static struct  dw_pci_controller  dw_pci_controllers[] = {
.rx_fifo_depth = 32,
.clk_khz = 10,
.functionality = I2C_FUNC_10BIT_ADDR,
+   .scl_sda_cfg = &byt_config,
},
 };
 static struct i2c_algorithm i2c_dw_algo = {
@@ -187,6 +206,7 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
struct i2c_adapter *adap;
int r;
struct  dw_pci_controller *controller;
+   struct dw_scl_sda_cfg *cfg;
 
if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
@@ -224,6 +244,14 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
DW_DEFAULT_FUNCTIONALITY;
 
dev->master_cfg =  controller->bus_cfg;
+   if (controller->scl_sda_cfg) {
+   cfg = controller->scl_sda_cfg;
+   dev->ss_hcnt = cfg->ss_hcnt;
+   dev->fs_hcnt = cfg->fs_hcnt;
+   dev->ss_lcnt = cfg->ss_lcnt;
+   dev->fs_lcnt = cfg->fs_lcnt;
+   dev->sda_hold_time = cfg->sda_hold;
+   }
 
pci_set_drvdata(pdev, dev);
 
-- 
1.7.4.4

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[PATCH v2] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value

2014-03-10 Thread Chew Chiau Ee 
From: Chew, Chiau Ee 

On Intel BayTrail, there was case whereby the resulting fast mode
bus speed becomes slower (~20% slower compared to expected speed)
if using the HCNT/LCNT calculated in the core layer. Thus, this
patch is added to allow pci glue layer to pass in optimal
HCNT/LCNT/SDA hold time values to core layer since the core
layer supports cofigurable HCNT/LCNT/SDA hold time values now.

---
v2 changelog:
 * Add 'dw_' prefix to struct scl_sda_cfg
 * Add Baytrail HCNT/LCNT/SDA hold time values directly in the
   struct instead of using macro definition
 * Replace tab before "=" with space in struct

Signed-off-by: Chew, Chiau Ee 
---
 drivers/i2c/busses/i2c-designware-pcidrv.c |   28 
 1 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c 
b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 094509bc..91d468f 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -58,6 +58,14 @@ enum dw_pci_ctl_id_t {
baytrail,
 };
 
+struct dw_scl_sda_cfg {
+   u32 ss_hcnt;
+   u32 fs_hcnt;
+   u32 ss_lcnt;
+   u32 fs_lcnt;
+   u32 sda_hold;
+};
+
 struct dw_pci_controller {
u32 bus_num;
u32 bus_cfg;
@@ -65,6 +73,7 @@ struct dw_pci_controller {
u32 rx_fifo_depth;
u32 clk_khz;
u32 functionality;
+   struct dw_scl_sda_cfg *scl_sda_cfg;
 };
 
 #define INTEL_MID_STD_CFG  (DW_IC_CON_MASTER | \
@@ -77,6 +86,15 @@ struct dw_pci_controller {
I2C_FUNC_SMBUS_WORD_DATA |  \
I2C_FUNC_SMBUS_I2C_BLOCK)
 
+/* BayTrail HCNT/LCNT/SDA hold time */
+static struct dw_scl_sda_cfg byt_config = {
+   .ss_hcnt = 0x200,
+   .fs_hcnt = 0x55,
+   .ss_lcnt = 0x200,
+   .fs_lcnt = 0x99,
+   .sda_hold = 0x6,
+};
+
 static struct  dw_pci_controller  dw_pci_controllers[] = {
[moorestown_0] = {
.bus_num = 0,
@@ -148,6 +166,7 @@ static struct  dw_pci_controller  dw_pci_controllers[] = {
.rx_fifo_depth = 32,
.clk_khz = 10,
.functionality = I2C_FUNC_10BIT_ADDR,
+   .scl_sda_cfg = &byt_config,
},
 };
 static struct i2c_algorithm i2c_dw_algo = {
@@ -187,6 +206,7 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
struct i2c_adapter *adap;
int r;
struct  dw_pci_controller *controller;
+   struct dw_scl_sda_cfg *cfg;
 
if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
@@ -224,6 +244,14 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
DW_DEFAULT_FUNCTIONALITY;
 
dev->master_cfg =  controller->bus_cfg;
+   if (controller->scl_sda_cfg) {
+   cfg = controller->scl_sda_cfg;
+   dev->ss_hcnt = cfg->ss_hcnt;
+   dev->fs_hcnt = cfg->fs_hcnt;
+   dev->ss_lcnt = cfg->ss_lcnt;
+   dev->fs_lcnt = cfg->fs_lcnt;
+   dev->sda_hold_time = cfg->sda_hold;
+   }
 
pci_set_drvdata(pdev, dev);
 
-- 
1.7.4.4

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RE: [PATCH 2/2] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value

2014-03-10 Thread Chew, Chiau Ee 


> -Original Message-
> From: Wolfram Sang [mailto:w...@the-dreams.de]
> Sent: Sunday, March 09, 2014 5:04 PM
> To: Chew, Chiau Ee
> Cc: Mika Westerberg; linux-i2c@vger.kernel.org; linux-ker...@vger.kernel.org
> Subject: Re: [PATCH 2/2] i2c: designware-pci: set ideal HCNT, LCNT and SDA
> hold time value
> 
> On Fri, Mar 07, 2014 at 10:12:51PM +0800, Chew Chiau Ee wrote:
> > From: Chew, Chiau Ee 
> >
> > On Intel BayTrail, there was case whereby the resulting fast mode bus
> > speed becomes slower (~20% slower compared to expected speed) if using
> > the HCNT/LCNT calculated in the core layer. Thus, this patch is added
> > to allow pci glue layer to pass in optimal HCNT/LCNT/SDA hold time
> > values to core layer since the core layer supports cofigurable
> > HCNT/LCNT/SDA hold time values now.
> >
> > Signed-off-by: Chew, Chiau Ee 
> 
> Can you make use of those instead?
> 
> u32 sda_falling_time;
> u32 scl_falling_time;
> 
> This is more consistent with using sda_hold_time and lets them have a common
> (and more readable) unit.

Would like to clarify on your statement above. So you are suggesting to change 
the following 
variable name in the code? As in:
"u32 ss_hcnt;"   to  "u32 ss_scl_rising_time"
"u32 fs_hcnt;"   to  "u32 fs_scl_rising_time"
"u32 ss_lcnt;"to   "u32 ss_scl_falling_time"
"u32 fs_lcnt;" to " u32 fs_scl_falling_time"
"u32 sda_hold;"  to  "u32 sda_hold_time"

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RE: [PATCH 1/2] i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C

2014-03-10 Thread Chew, Chiau Ee 


> -Original Message-
> From: Wolfram Sang [mailto:w...@the-dreams.de]
> Sent: Sunday, March 09, 2014 4:54 PM
> To: Chew, Chiau Ee
> Cc: Mika Westerberg; linux-i2c@vger.kernel.org; linux-ker...@vger.kernel.org
> Subject: Re: [PATCH 1/2] i2c: designware-pci: add 10-bit addressing mode
> functionality for BYT I2C
> 
> On Fri, Mar 07, 2014 at 10:12:50PM +0800, Chew Chiau Ee wrote:
> > From: Chew, Chiau Ee 
> >
> > All the I2C controllers on Intel BayTrail LPSS subsystem able to
> > support 10-bit addressing mode functionality.
> >
> > Signed-off-by: Chew, Chiau Ee 
> > Signed-off-by: Ong, Boon Leong 
> > ---
> >  drivers/i2c/busses/i2c-designware-pcidrv.c |   17 +++--
> >  1 files changed, 11 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c
> > b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > index f1dabee..87f2fc4 100644
> > --- a/drivers/i2c/busses/i2c-designware-pcidrv.c
> > +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
> > @@ -64,12 +64,19 @@ struct dw_pci_controller {
> > u32 tx_fifo_depth;
> > u32 rx_fifo_depth;
> > u32 clk_khz;
> > +   u32 functionality;
> >  };
> >
> >  #define INTEL_MID_STD_CFG  (DW_IC_CON_MASTER |
>   \
> > DW_IC_CON_SLAVE_DISABLE |   \
> > DW_IC_CON_RESTART_EN)
> >
> > +#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C |
>   \
> > +   I2C_FUNC_SMBUS_BYTE |
>   \
> > +   I2C_FUNC_SMBUS_BYTE_DATA |
>   \
> > +   I2C_FUNC_SMBUS_WORD_DATA |
>   \
> > +   I2C_FUNC_SMBUS_I2C_BLOCK)
> 
> Can't we have I2C_FUNC_SMBUS_EMUL here? (Need checking with
> I2C_SMBUS_QUICK)

Per my understanding, this I2C host is not able to support I2C_SMBUS_QUICK.

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[PATCH 1/2] i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C

2014-03-06 Thread Chew Chiau Ee 
From: Chew, Chiau Ee 

All the I2C controllers on Intel BayTrail LPSS subsystem able
to support 10-bit addressing mode functionality.

Signed-off-by: Chew, Chiau Ee 
Signed-off-by: Ong, Boon Leong 
---
 drivers/i2c/busses/i2c-designware-pcidrv.c |   17 +++--
 1 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c 
b/drivers/i2c/busses/i2c-designware-pcidrv.c
index f1dabee..87f2fc4 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -64,12 +64,19 @@ struct dw_pci_controller {
u32 tx_fifo_depth;
u32 rx_fifo_depth;
u32 clk_khz;
+   u32 functionality;
 };
 
 #define INTEL_MID_STD_CFG  (DW_IC_CON_MASTER | \
DW_IC_CON_SLAVE_DISABLE |   \
DW_IC_CON_RESTART_EN)
 
+#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C |   \
+   I2C_FUNC_SMBUS_BYTE |   \
+   I2C_FUNC_SMBUS_BYTE_DATA |  \
+   I2C_FUNC_SMBUS_WORD_DATA |  \
+   I2C_FUNC_SMBUS_I2C_BLOCK)
+
 static struct  dw_pci_controller  dw_pci_controllers[] = {
[moorestown_0] = {
.bus_num = 0,
@@ -140,6 +147,7 @@ static struct  dw_pci_controller  dw_pci_controllers[] = {
.tx_fifo_depth = 32,
.rx_fifo_depth = 32,
.clk_khz = 10,
+   .functionality = I2C_FUNC_10BIT_ADDR,
},
 };
 static struct i2c_algorithm i2c_dw_algo = {
@@ -256,12 +264,9 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
dev->base = pcim_iomap_table(pdev)[0];
dev->dev = &pdev->dev;
-   dev->functionality =
-   I2C_FUNC_I2C |
-   I2C_FUNC_SMBUS_BYTE |
-   I2C_FUNC_SMBUS_BYTE_DATA |
-   I2C_FUNC_SMBUS_WORD_DATA |
-   I2C_FUNC_SMBUS_I2C_BLOCK;
+   dev->functionality = controller->functionality |
+   DW_DEFAULT_FUNCTIONALITY;
+
dev->master_cfg =  controller->bus_cfg;
 
pci_set_drvdata(pdev, dev);
-- 
1.7.4.4

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[PATCH 2/2] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value

2014-03-06 Thread Chew Chiau Ee 
From: Chew, Chiau Ee 

On Intel BayTrail, there was case whereby the resulting fast mode
bus speed becomes slower (~20% slower compared to expected speed)
if using the HCNT/LCNT calculated in the core layer. Thus, this
patch is added to allow pci glue layer to pass in optimal
HCNT/LCNT/SDA hold time values to core layer since the core
layer supports cofigurable HCNT/LCNT/SDA hold time values now.

Signed-off-by: Chew, Chiau Ee 
---
 drivers/i2c/busses/i2c-designware-pcidrv.c |   34 
 1 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c 
b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 87f2fc4..96417ca 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -58,6 +58,14 @@ enum dw_pci_ctl_id_t {
baytrail,
 };
 
+struct scl_sda_cfg {
+   u32 ss_hcnt;
+   u32 fs_hcnt;
+   u32 ss_lcnt;
+   u32 fs_lcnt;
+   u32 sda_hold;
+};
+
 struct dw_pci_controller {
u32 bus_num;
u32 bus_cfg;
@@ -65,6 +73,7 @@ struct dw_pci_controller {
u32 rx_fifo_depth;
u32 clk_khz;
u32 functionality;
+   struct scl_sda_cfg *scl_sda_cfg;
 };
 
 #define INTEL_MID_STD_CFG  (DW_IC_CON_MASTER | \
@@ -77,6 +86,21 @@ struct dw_pci_controller {
I2C_FUNC_SMBUS_WORD_DATA |  \
I2C_FUNC_SMBUS_I2C_BLOCK)
 
+/* BayTrail HCNT/LCNT/SDA_HOLD */
+#define BYT_STD_MODE_HCNT  0x200
+#define BYT_STD_MODE_LCNT  BYT_STD_MODE_HCNT
+#define BYT_FAST_MODE_HCNT 0x55
+#define BYT_FAST_MODE_LCNT 0x99
+#define BYT_SDA_HOLD   0x6
+
+static struct scl_sda_cfg byt_config = {
+   .ss_hcnt= BYT_STD_MODE_HCNT,
+   .fs_hcnt= BYT_FAST_MODE_HCNT,
+   .ss_lcnt= BYT_STD_MODE_LCNT,
+   .fs_lcnt= BYT_FAST_MODE_LCNT,
+   .sda_hold   = BYT_SDA_HOLD,
+};
+
 static struct  dw_pci_controller  dw_pci_controllers[] = {
[moorestown_0] = {
.bus_num = 0,
@@ -148,6 +172,7 @@ static struct  dw_pci_controller  dw_pci_controllers[] = {
.rx_fifo_depth = 32,
.clk_khz = 10,
.functionality = I2C_FUNC_10BIT_ADDR,
+   .scl_sda_cfg = &byt_config,
},
 };
 static struct i2c_algorithm i2c_dw_algo = {
@@ -231,6 +256,7 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
struct i2c_adapter *adap;
int r;
struct  dw_pci_controller *controller;
+   struct scl_sda_cfg *cfg;
 
if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
@@ -268,6 +294,14 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
DW_DEFAULT_FUNCTIONALITY;
 
dev->master_cfg =  controller->bus_cfg;
+   if (controller->scl_sda_cfg) {
+   cfg = controller->scl_sda_cfg;
+   dev->ss_hcnt = cfg->ss_hcnt;
+   dev->fs_hcnt = cfg->fs_hcnt;
+   dev->ss_lcnt = cfg->ss_lcnt;
+   dev->fs_lcnt = cfg->fs_lcnt;
+   dev->sda_hold_time = cfg->sda_hold;
+   }
 
pci_set_drvdata(pdev, dev);
 
-- 
1.7.4.4

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[PATCH 0/2] i2c: designware-pci: extra features for PCI mode LPSS I2C

2014-03-06 Thread Chew Chiau Ee 
From: Chew, Chiau Ee 

These two patches contains the additional changes required for BayTrail LPSS
I2C on top of the patch that Mika Westerberg has submitted previously which
is still in the pending queue:
"[PATCH v2] i2c: designware-pci: Add Baytrail PCI IDs"
http://www.spinics.net/lists/linux-i2c/msg14709.html

Basically, the changes inclusive of:
i.  enable the pci glue layer to pass in target HCNT, LCNT
and SDA hold time values to core layer if they are known
beforehand, eg: for BayTrail.
ii. declare the BayTrail LPSS I2C controllers are capable of
supporting 10-bit addressing mode functionality.

Chew, Chiau Ee (2):
  i2c: designware-pci: add 10-bit addressing mode functionality for BYT
I2C
  i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value

 drivers/i2c/busses/i2c-designware-pcidrv.c |   51 ---
 1 files changed, 45 insertions(+), 6 deletions(-)

-- 
1.7.4.4

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[PATCH] i2c: i801: enable Intel BayTrail SMBUS

2014-02-28 Thread Chew Chiau Ee 
From: Chew, Kean ho 

Add Device ID of Intel BayTrail SMBus Controller.

Signed-off-by: Chew, Kean ho 
Signed-off-by: Chew, Chiau Ee 
---
 Documentation/i2c/busses/i2c-i801 |1 +
 drivers/i2c/busses/Kconfig|1 +
 drivers/i2c/busses/i2c-i801.c |3 +++
 3 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/Documentation/i2c/busses/i2c-i801 
b/Documentation/i2c/busses/i2c-i801
index aaaf0693..adf5e33 100644
--- a/Documentation/i2c/busses/i2c-i801
+++ b/Documentation/i2c/busses/i2c-i801
@@ -26,6 +26,7 @@ Supported adapters:
   * Intel Wellsburg (PCH)
   * Intel Coleto Creek (PCH)
   * Intel Wildcat Point-LP (PCH)
+  * Intel BayTrail (SOC)
Datasheets: Publicly available at the Intel website
 
 On Intel Patsburg and later chipsets, both the normal host SMBus controller
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index f5ed031..f23da0e 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -110,6 +110,7 @@ config I2C_I801
Wellsburg (PCH)
Coleto Creek (PCH)
Wildcat Point-LP (PCH)
+   BayTrail (SOC)
 
  This driver can also be built as a module.  If so, the module
  will be called i2c-i801.
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 349c2d3..899f559 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -60,6 +60,7 @@
   Wellsburg (PCH) MS0x8d7f 32 hard yes yes yes
   Coleto Creek (PCH)0x23b0 32 hard yes yes yes
   Wildcat Point-LP (PCH)   0x9ca2 32 hard yes yes yes
+  BayTrail (SOC)0x0f12 32 hard yes yes yes
 
   Features supported by this driver:
   Software PEC no
@@ -161,6 +162,7 @@
 STATUS_ERROR_FLAGS)
 
 /* Older devices have their ID defined in  */
+#define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS  0x1c22
 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
@@ -822,6 +824,7 @@ static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 
PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 
PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 
PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
+   { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
{ 0, }
 };
 
-- 
1.7.4.4

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[PATCH] i2c-designware: 10-bit addressing mode enabling if I2C_DYNAMIC_TAR_UPDATE is set.

2013-09-26 Thread Chew, Chiau Ee 
According to Designware I2C spec, if I2C_DYNAMIC_TAR_UPDATE is set to 1,
the 10-bit addressing mode is controlled by IC_10BITADDR_MASTER bit of
IC_TAR register instead of IC_CON register. The IC_10BITADDR_MASTER
in IC_CON register becomes read-only copy. Since I2C_DYNAMIC_TAR_UPDATE
value can't be detected from hardware register, so we will always set the
IC_10BITADDR_MASTER bit in both IC_CON and IC_TAR register whenever 10-bit
addresing mode is requested by user application.

Signed-off-by: Chew, Chiau Ee 
Reviewed-by: Mika Westerberg 
---
 drivers/i2c/busses/i2c-designware-core.c |   26 --
 1 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-core.c 
b/drivers/i2c/busses/i2c-designware-core.c
index dbecf08..5888fee 100644
--- a/drivers/i2c/busses/i2c-designware-core.c
+++ b/drivers/i2c/busses/i2c-designware-core.c
@@ -98,6 +98,8 @@
 
 #define DW_IC_ERR_TX_ABRT  0x1
 
+#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
+
 /*
  * status codes
  */
@@ -388,22 +390,34 @@ static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev 
*dev)
 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 {
struct i2c_msg *msgs = dev->msgs;
-   u32 ic_con;
+   u32 ic_con, ic_tar = 0;
 
/* Disable the adapter */
__i2c_dw_enable(dev, false);
 
-   /* set the slave (target) address */
-   dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR);
-
/* if the slave address is ten bit address, enable 10BITADDR */
ic_con = dw_readl(dev, DW_IC_CON);
-   if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
+   if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
ic_con |= DW_IC_CON_10BITADDR_MASTER;
-   else
+   /*
+* If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
+* mode has to be enabled via bit 12 of IC_TAR register.
+* We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
+* detected from registers.
+*/
+   ic_tar = DW_IC_TAR_10BITADDR_MASTER;
+   } else {
ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
+   }
+
dw_writel(dev, ic_con, DW_IC_CON);
 
+   /*
+* Set the slave (target) address and enable 10-bit addressing mode
+* if applicable.
+*/
+   dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
+
/* Enable the adapter */
__i2c_dw_enable(dev, true);
 
-- 
1.7.4.4

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RE: [PATCH] i2c-designware: Manually set RESTART bit between messages

2013-07-15 Thread Chew, Chiau Ee 
On Wed, Jul 03, 2013 at 10:15:11PM +0200, Wolfram Sang wrote:
> 
> CCing Mika and Christian.
> 
> On Fri, Jun 21, 2013 at 03:05:28PM +0800, Chew Chiau Ee wrote:
> > From: Chew, Chiau Ee 
> > 
> > If both IC_EMPTYFIFO_HOLD_MASTER_EN and IC_RESTART_EN are set to 1, 
> > the Designware I2C controller doesn't generate RESTART unless user 
> > specifically requests it by setting RESTART bit in IC_DATA_CMD register.
> > 
> > Since IC_EMPTYFIFO_HOLD_MASTER_EN setting can't be detected from 
> > hardware register, we must always manually set the restart bit between 
> > messages.
> > 
> > Signed-off-by: Chew, Chiau Ee 
> 
> How come restart has worked before? Or did it not?

> It works fine. However IC_EMPTYFIFO_HOLD_MASTER_EN=1 makes a difference. We 
> had similar thing with the STOP that was fixed previously.

>If I understand the dw i2c databook right, RESTART is only issued if the 
>transfer direction changes. So if you have two or more consecutive transfers 
>that have the same direction (not sure how common that is) there is no RESTART 
>between them unless >DW_IC_CON_RESTART_EN is set.

>Chiau Ee, does this fix a real problem?

Yes, it fixed a problem in one of our use case. we have a use case whereby the 
control path of the audio codec is using I2C bus. During our validation based 
on that use case,  we observed there is issue with back-to-back message 
transfer if this fix is not being added.
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[PATCH] i2c-designware: Manually set RESTART bit between messages

2013-06-21 Thread Chew Chiau Ee 
From: Chew, Chiau Ee 

If both IC_EMPTYFIFO_HOLD_MASTER_EN and IC_RESTART_EN are set to 1, the
Designware I2C controller doesn't generate RESTART unless user specifically
requests it by setting RESTART bit in IC_DATA_CMD register.

Since IC_EMPTYFIFO_HOLD_MASTER_EN setting can't be detected from hardware
register, we must always manually set the restart bit between messages.

Signed-off-by: Chew, Chiau Ee 
---
 drivers/i2c/busses/i2c-designware-core.c |   14 ++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/drivers/i2c/busses/i2c-designware-core.c 
b/drivers/i2c/busses/i2c-designware-core.c
index 3de5494..9348439 100644
--- a/drivers/i2c/busses/i2c-designware-core.c
+++ b/drivers/i2c/busses/i2c-designware-core.c
@@ -403,6 +403,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
u32 addr = msgs[dev->msg_write_idx].addr;
u32 buf_len = dev->tx_buf_len;
u8 *buf = dev->tx_buf;
+   bool need_restart = false;
 
intr_mask = DW_IC_INTR_DEFAULT_MASK;
 
@@ -430,6 +431,14 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
/* new i2c_msg */
buf = msgs[dev->msg_write_idx].buf;
buf_len = msgs[dev->msg_write_idx].len;
+
+   /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
+* IC_RESTART_EN are set, we must manually
+* set restart bit between messages.
+*/
+   if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
+   (dev->msg_write_idx > 0))
+   need_restart = true;
}
 
tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
@@ -448,6 +457,11 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
buf_len == 1)
cmd |= BIT(9);
 
+   if (need_restart) {
+   cmd |= BIT(10);
+   need_restart = false;
+   }
+
if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 
/* avoid rx buffer overrun */
-- 
1.7.4.4

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