Re: [PATCH] pwm: rockchip: State of pwm clock should synchronize with pwm enabled state

[Boris Brezillon]

Hi David,

On Tue, 28 Feb 2017 14:43:36 +0800
David Wu  wrote:

> From: "david.wu" 
> 
> If the pwm was not enabled at uboot loader, pwm could not work for clock
> always disabled at pwm driver. The pwm clock is enabled at beginning of
> pwm_apply(), but disabled at end of pwm_apply().
> 
> If the pwm was enabled at uboot loader, pwm clock is always enabled unless
> closed by ATF. The pwm-backlight might turn off the power at early suspend,
> should disable pwm clock for saving power consume.
> 
> It is important to provide opportunity to enable/disable clock at pwm driver,
> the pwm consumer should ensure correct order to call pwm enable/disable, and
> pwm driver ensure state of pwm clock synchronized with pwm enabled state.

Oops. It seems I'm the one who introduced this regression when moving
to the atomic PWM API.

You should add

Fixes: 2bf1c98aa5a4 ("pwm: rockchip: Add support for atomic update")
Cc: sta...@vger.kernel.org

> 
> Signed-off-by: David Wu 
> ---
>  drivers/pwm/pwm-rockchip.c | 38 +++---
>  1 file changed, 31 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c
> index ef89df1..14a0445 100644
> --- a/drivers/pwm/pwm-rockchip.c
> +++ b/drivers/pwm/pwm-rockchip.c
> @@ -191,6 +191,26 @@ static int rockchip_pwm_config(struct pwm_chip *chip, 
> struct pwm_device *pwm,
>   return 0;
>  }
>  
> +static int rk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
> +  bool enable, enum pwm_polarity polarity)

Please stay consistent with the existing naming scheme:

static int rockchip_pwm_enable(struct pwm_chip *chip,
   struct pwm_device *pwm,
   bool enable,
   enum pwm_polarity polarity)

Once fixed, you can add

Reviewed-by: Boris Brezillon 

> +{
> + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
> + int ret;
> +
> + if (enable) {
> + ret = clk_enable(pc->clk);
> + if (ret)
> + return ret;
> + }
> +
> + pc->data->set_enable(chip, pwm, enable, polarity);
> +
> + if (!enable)
> + clk_disable(pc->clk);
> +
> + return 0;
> +}
> +
>  static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> struct pwm_state *state)
>  {
> @@ -207,22 +227,26 @@ static int rockchip_pwm_apply(struct pwm_chip *chip, 
> struct pwm_device *pwm,
>   return ret;
>  
>   if (state->polarity != curstate.polarity && enabled) {
> - pc->data->set_enable(chip, pwm, false, state->polarity);
> + ret = rk_pwm_enable(chip, pwm, false, state->polarity);
> + if (ret)
> + goto out;
>   enabled = false;
>   }
>  
>   ret = rockchip_pwm_config(chip, pwm, state->duty_cycle, state->period);
>   if (ret) {
>   if (enabled != curstate.enabled)
> - pc->data->set_enable(chip, pwm, !enabled,
> -  state->polarity);
> -
> + rk_pwm_enable(chip, pwm, !enabled,
> +   state->polarity);
>   goto out;
>   }
>  
> - if (state->enabled != enabled)
> - pc->data->set_enable(chip, pwm, state->enabled,
> -  state->polarity);
> + if (state->enabled != enabled) {
> + ret = rk_pwm_enable(chip, pwm, state->enabled,
> + state->polarity);
> + if (ret)
> + goto out;
> + }
>  
>   /*
>* Update the state with the real hardware, which can differ a bit

Re: [PATCH] pwm: rockchip: State of pwm clock should synchronize with pwm enabled state

[Boris Brezillon]

Hi David,

On Tue, 28 Feb 2017 14:43:36 +0800
David Wu  wrote:

> From: "david.wu" 
> 
> If the pwm was not enabled at uboot loader, pwm could not work for clock
> always disabled at pwm driver. The pwm clock is enabled at beginning of
> pwm_apply(), but disabled at end of pwm_apply().
> 
> If the pwm was enabled at uboot loader, pwm clock is always enabled unless
> closed by ATF. The pwm-backlight might turn off the power at early suspend,
> should disable pwm clock for saving power consume.
> 
> It is important to provide opportunity to enable/disable clock at pwm driver,
> the pwm consumer should ensure correct order to call pwm enable/disable, and
> pwm driver ensure state of pwm clock synchronized with pwm enabled state.

Oops. It seems I'm the one who introduced this regression when moving
to the atomic PWM API.

You should add

Fixes: 2bf1c98aa5a4 ("pwm: rockchip: Add support for atomic update")
Cc: sta...@vger.kernel.org

> 
> Signed-off-by: David Wu 
> ---
>  drivers/pwm/pwm-rockchip.c | 38 +++---
>  1 file changed, 31 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c
> index ef89df1..14a0445 100644
> --- a/drivers/pwm/pwm-rockchip.c
> +++ b/drivers/pwm/pwm-rockchip.c
> @@ -191,6 +191,26 @@ static int rockchip_pwm_config(struct pwm_chip *chip, 
> struct pwm_device *pwm,
>   return 0;
>  }
>  
> +static int rk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
> +  bool enable, enum pwm_polarity polarity)

Please stay consistent with the existing naming scheme:

static int rockchip_pwm_enable(struct pwm_chip *chip,
   struct pwm_device *pwm,
   bool enable,
   enum pwm_polarity polarity)

Once fixed, you can add

Reviewed-by: Boris Brezillon 

> +{
> + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
> + int ret;
> +
> + if (enable) {
> + ret = clk_enable(pc->clk);
> + if (ret)
> + return ret;
> + }
> +
> + pc->data->set_enable(chip, pwm, enable, polarity);
> +
> + if (!enable)
> + clk_disable(pc->clk);
> +
> + return 0;
> +}
> +
>  static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> struct pwm_state *state)
>  {
> @@ -207,22 +227,26 @@ static int rockchip_pwm_apply(struct pwm_chip *chip, 
> struct pwm_device *pwm,
>   return ret;
>  
>   if (state->polarity != curstate.polarity && enabled) {
> - pc->data->set_enable(chip, pwm, false, state->polarity);
> + ret = rk_pwm_enable(chip, pwm, false, state->polarity);
> + if (ret)
> + goto out;
>   enabled = false;
>   }
>  
>   ret = rockchip_pwm_config(chip, pwm, state->duty_cycle, state->period);
>   if (ret) {
>   if (enabled != curstate.enabled)
> - pc->data->set_enable(chip, pwm, !enabled,
> -  state->polarity);
> -
> + rk_pwm_enable(chip, pwm, !enabled,
> +   state->polarity);
>   goto out;
>   }
>  
> - if (state->enabled != enabled)
> - pc->data->set_enable(chip, pwm, state->enabled,
> -  state->polarity);
> + if (state->enabled != enabled) {
> + ret = rk_pwm_enable(chip, pwm, state->enabled,
> + state->polarity);
> + if (ret)
> + goto out;
> + }
>  
>   /*
>* Update the state with the real hardware, which can differ a bit

Re: [PATCH 0/4] ARM: sun7i: Convert sun7i SoC to sunxi-ng

[Maxime Ripard]

Hi Priit,

On Mon, Feb 27, 2017 at 11:09:10PM +0200, Priit Laes wrote:
> Hi,
> 
> This is serie brings another SoC into the sunxi-ng world.
> 
> As mentioned in sun5i conversion, this is pretty much standard
> stuff as all the required clocks were already implemented in
> the sunxi-ng framework.

Thanks a lot for that work. I think the A10 should be converted at the
same time, and both would share the same driver.

Fortunately, if I recall properly, both are not too far off.

Thanks again,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


signature.asc
Description: PGP signature

Re: [PATCH 0/4] ARM: sun7i: Convert sun7i SoC to sunxi-ng

[Maxime Ripard]

Hi Priit,

On Mon, Feb 27, 2017 at 11:09:10PM +0200, Priit Laes wrote:
> Hi,
> 
> This is serie brings another SoC into the sunxi-ng world.
> 
> As mentioned in sun5i conversion, this is pretty much standard
> stuff as all the required clocks were already implemented in
> the sunxi-ng framework.

Thanks a lot for that work. I think the A10 should be converted at the
same time, and both would share the same driver.

Fortunately, if I recall properly, both are not too far off.

Thanks again,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


signature.asc
Description: PGP signature

[PATCH 1/1] Drivers: hv: util: on deinit, don't wait the release event, if we shouldn't

[kys]

From: Dexuan Cui 

If the daemon is NOT running at all, when we disable the util device from
Hyper-V Manager (or sometimes the host can rescind a util device and then
re-offer it), we'll hang in util_remove -> hv_kvp_deinit ->
wait_for_completion(_event), because this code path doesn't run:
hvt_op_release -> ... -> kvp_on_reset -> complete(_event).

Due to this, we even can't reboot the VM properly.

The patch tracks if the dev file is opened or not, and we only need to
wait if it's opened.

Fixes: 5a66fecbf6aa ("Drivers: hv: util: kvp: Fix a rescind processing issue")

Signed-off-by: Dexuan Cui 
Cc: Vitaly Kuznetsov 
Cc: "K. Y. Srinivasan" 
Cc: Haiyang Zhang 
Cc: Stephen Hemminger 
Signed-off-by: K. Y. Srinivasan 
---
 drivers/hv/hv_fcopy.c   |5 -
 drivers/hv/hv_kvp.c |6 +-
 drivers/hv/hv_snapshot.c|5 -
 drivers/hv/hv_utils_transport.c |2 ++
 drivers/hv/hv_utils_transport.h |1 +
 5 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/hv/hv_fcopy.c b/drivers/hv/hv_fcopy.c
index 9aee601..545cf43 100644
--- a/drivers/hv/hv_fcopy.c
+++ b/drivers/hv/hv_fcopy.c
@@ -358,8 +358,11 @@ int hv_fcopy_init(struct hv_util_service *srv)
 
 void hv_fcopy_deinit(void)
 {
+   bool wait = hvt->dev_opened;
+
fcopy_transaction.state = HVUTIL_DEVICE_DYING;
cancel_delayed_work_sync(_timeout_work);
hvutil_transport_destroy(hvt);
-   wait_for_completion(_event);
+   if (wait)
+   wait_for_completion(_event);
 }
diff --git a/drivers/hv/hv_kvp.c b/drivers/hv/hv_kvp.c
index de26371..15c7873 100644
--- a/drivers/hv/hv_kvp.c
+++ b/drivers/hv/hv_kvp.c
@@ -742,10 +742,14 @@ static void kvp_on_reset(void)
 
 void hv_kvp_deinit(void)
 {
+   bool wait = hvt->dev_opened;
+
kvp_transaction.state = HVUTIL_DEVICE_DYING;
cancel_delayed_work_sync(_host_handshake_work);
cancel_delayed_work_sync(_timeout_work);
cancel_work_sync(_sendkey_work);
hvutil_transport_destroy(hvt);
-   wait_for_completion(_event);
+
+   if (wait)
+   wait_for_completion(_event);
 }
diff --git a/drivers/hv/hv_snapshot.c b/drivers/hv/hv_snapshot.c
index bcc03f0..3847f19 100644
--- a/drivers/hv/hv_snapshot.c
+++ b/drivers/hv/hv_snapshot.c
@@ -396,9 +396,12 @@ static void vss_on_reset(void)
 
 void hv_vss_deinit(void)
 {
+   bool wait = hvt->dev_opened;
+
vss_transaction.state = HVUTIL_DEVICE_DYING;
cancel_delayed_work_sync(_timeout_work);
cancel_work_sync(_handle_request_work);
hvutil_transport_destroy(hvt);
-   wait_for_completion(_event);
+   if (wait)
+   wait_for_completion(_event);
 }
diff --git a/drivers/hv/hv_utils_transport.c b/drivers/hv/hv_utils_transport.c
index c235a95..05e0648 100644
--- a/drivers/hv/hv_utils_transport.c
+++ b/drivers/hv/hv_utils_transport.c
@@ -153,6 +153,7 @@ static int hvt_op_open(struct inode *inode, struct file 
*file)
 
if (issue_reset)
hvt_reset(hvt);
+   hvt->dev_opened = (hvt->mode == HVUTIL_TRANSPORT_CHARDEV) && !ret;
 
mutex_unlock(>lock);
 
@@ -182,6 +183,7 @@ static int hvt_op_release(struct inode *inode, struct file 
*file)
 * connects back.
 */
hvt_reset(hvt);
+   hvt->dev_opened = false;
mutex_unlock(>lock);
 
if (mode_old == HVUTIL_TRANSPORT_DESTROY)
diff --git a/drivers/hv/hv_utils_transport.h b/drivers/hv/hv_utils_transport.h
index d98f522..9871283 100644
--- a/drivers/hv/hv_utils_transport.h
+++ b/drivers/hv/hv_utils_transport.h
@@ -32,6 +32,7 @@ struct hvutil_transport {
int mode;   /* hvutil_transport_mode */
struct file_operations fops;/* file operations */
struct miscdevice mdev; /* misc device */
+   bool   dev_opened;  /* Is the device opened? */
struct cb_id cn_id; /* CN_*_IDX/CN_*_VAL */
struct list_head list;  /* hvt_list */
int (*on_msg)(void *, int); /* callback on new user message */
-- 
1.7.1

[PATCH 1/1] Drivers: hv: util: on deinit, don't wait the release event, if we shouldn't

[kys]

From: Dexuan Cui 

If the daemon is NOT running at all, when we disable the util device from
Hyper-V Manager (or sometimes the host can rescind a util device and then
re-offer it), we'll hang in util_remove -> hv_kvp_deinit ->
wait_for_completion(_event), because this code path doesn't run:
hvt_op_release -> ... -> kvp_on_reset -> complete(_event).

Due to this, we even can't reboot the VM properly.

The patch tracks if the dev file is opened or not, and we only need to
wait if it's opened.

Fixes: 5a66fecbf6aa ("Drivers: hv: util: kvp: Fix a rescind processing issue")

Signed-off-by: Dexuan Cui 
Cc: Vitaly Kuznetsov 
Cc: "K. Y. Srinivasan" 
Cc: Haiyang Zhang 
Cc: Stephen Hemminger 
Signed-off-by: K. Y. Srinivasan 
---
 drivers/hv/hv_fcopy.c   |5 -
 drivers/hv/hv_kvp.c |6 +-
 drivers/hv/hv_snapshot.c|5 -
 drivers/hv/hv_utils_transport.c |2 ++
 drivers/hv/hv_utils_transport.h |1 +
 5 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/hv/hv_fcopy.c b/drivers/hv/hv_fcopy.c
index 9aee601..545cf43 100644
--- a/drivers/hv/hv_fcopy.c
+++ b/drivers/hv/hv_fcopy.c
@@ -358,8 +358,11 @@ int hv_fcopy_init(struct hv_util_service *srv)
 
 void hv_fcopy_deinit(void)
 {
+   bool wait = hvt->dev_opened;
+
fcopy_transaction.state = HVUTIL_DEVICE_DYING;
cancel_delayed_work_sync(_timeout_work);
hvutil_transport_destroy(hvt);
-   wait_for_completion(_event);
+   if (wait)
+   wait_for_completion(_event);
 }
diff --git a/drivers/hv/hv_kvp.c b/drivers/hv/hv_kvp.c
index de26371..15c7873 100644
--- a/drivers/hv/hv_kvp.c
+++ b/drivers/hv/hv_kvp.c
@@ -742,10 +742,14 @@ static void kvp_on_reset(void)
 
 void hv_kvp_deinit(void)
 {
+   bool wait = hvt->dev_opened;
+
kvp_transaction.state = HVUTIL_DEVICE_DYING;
cancel_delayed_work_sync(_host_handshake_work);
cancel_delayed_work_sync(_timeout_work);
cancel_work_sync(_sendkey_work);
hvutil_transport_destroy(hvt);
-   wait_for_completion(_event);
+
+   if (wait)
+   wait_for_completion(_event);
 }
diff --git a/drivers/hv/hv_snapshot.c b/drivers/hv/hv_snapshot.c
index bcc03f0..3847f19 100644
--- a/drivers/hv/hv_snapshot.c
+++ b/drivers/hv/hv_snapshot.c
@@ -396,9 +396,12 @@ static void vss_on_reset(void)
 
 void hv_vss_deinit(void)
 {
+   bool wait = hvt->dev_opened;
+
vss_transaction.state = HVUTIL_DEVICE_DYING;
cancel_delayed_work_sync(_timeout_work);
cancel_work_sync(_handle_request_work);
hvutil_transport_destroy(hvt);
-   wait_for_completion(_event);
+   if (wait)
+   wait_for_completion(_event);
 }
diff --git a/drivers/hv/hv_utils_transport.c b/drivers/hv/hv_utils_transport.c
index c235a95..05e0648 100644
--- a/drivers/hv/hv_utils_transport.c
+++ b/drivers/hv/hv_utils_transport.c
@@ -153,6 +153,7 @@ static int hvt_op_open(struct inode *inode, struct file 
*file)
 
if (issue_reset)
hvt_reset(hvt);
+   hvt->dev_opened = (hvt->mode == HVUTIL_TRANSPORT_CHARDEV) && !ret;
 
mutex_unlock(>lock);
 
@@ -182,6 +183,7 @@ static int hvt_op_release(struct inode *inode, struct file 
*file)
 * connects back.
 */
hvt_reset(hvt);
+   hvt->dev_opened = false;
mutex_unlock(>lock);
 
if (mode_old == HVUTIL_TRANSPORT_DESTROY)
diff --git a/drivers/hv/hv_utils_transport.h b/drivers/hv/hv_utils_transport.h
index d98f522..9871283 100644
--- a/drivers/hv/hv_utils_transport.h
+++ b/drivers/hv/hv_utils_transport.h
@@ -32,6 +32,7 @@ struct hvutil_transport {
int mode;   /* hvutil_transport_mode */
struct file_operations fops;/* file operations */
struct miscdevice mdev; /* misc device */
+   bool   dev_opened;  /* Is the device opened? */
struct cb_id cn_id; /* CN_*_IDX/CN_*_VAL */
struct list_head list;  /* hvt_list */
int (*on_msg)(void *, int); /* callback on new user message */
-- 
1.7.1

[GIT PULL] objtool fixes

[Ingo Molnar]

Linus,

Please pull the latest core-urgent-for-linus git tree from:

   git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 
core-urgent-for-linus

   # HEAD: 4e4636cf981b5b629fbfb78aa9f232e015f7d521 objtool: Enclose contents 
of unreachable() macro in a block

A handful of objtool fixes related to unreachable code, plus a build fix for 
out 
of tree modules.

 Thanks,

Ingo

-->
Josh Poimboeuf (4):
  objtool: Fix CONFIG_STACK_VALIDATION=y warning for out-of-tree modules
  objtool: Improve detection of BUG() and other dead ends
  objtool: Prevent GCC from merging annotate_unreachable()
  objtool: Enclose contents of unreachable() macro in a block


 Makefile| 24 -
 arch/x86/kernel/vmlinux.lds.S   |  1 +
 include/linux/compiler-gcc.h| 14 +-
 tools/objtool/arch.h|  5 ++--
 tools/objtool/arch/x86/decode.c |  3 ---
 tools/objtool/builtin-check.c   | 60 ++---
 6 files changed, 84 insertions(+), 23 deletions(-)

diff --git a/Makefile b/Makefile
index f1e6a02a0c19..32c84577aa93 100644
--- a/Makefile
+++ b/Makefile
@@ -908,6 +908,18 @@ mod_sign_cmd = true
 endif
 export mod_sign_cmd
 
+ifdef CONFIG_STACK_VALIDATION
+  has_libelf := $(call try-run,\
+   echo "int main() {}" | $(HOSTCC) -xc -o /dev/null -lelf -,1,0)
+  ifeq ($(has_libelf),1)
+objtool_target := tools/objtool FORCE
+  else
+$(warning "Cannot use CONFIG_STACK_VALIDATION, please install libelf-dev, 
libelf-devel or elfutils-libelf-devel")
+SKIP_STACK_VALIDATION := 1
+export SKIP_STACK_VALIDATION
+  endif
+endif
+
 
 ifeq ($(KBUILD_EXTMOD),)
 core-y += kernel/ certs/ mm/ fs/ ipc/ security/ crypto/ block/
@@ -1035,18 +1047,6 @@ prepare0: archprepare gcc-plugins
 # All the preparing..
 prepare: prepare0 prepare-objtool
 
-ifdef CONFIG_STACK_VALIDATION
-  has_libelf := $(call try-run,\
-   echo "int main() {}" | $(HOSTCC) -xc -o /dev/null -lelf -,1,0)
-  ifeq ($(has_libelf),1)
-objtool_target := tools/objtool FORCE
-  else
-$(warning "Cannot use CONFIG_STACK_VALIDATION, please install libelf-dev, 
libelf-devel or elfutils-libelf-devel")
-SKIP_STACK_VALIDATION := 1
-export SKIP_STACK_VALIDATION
-  endif
-endif
-
 PHONY += prepare-objtool
 prepare-objtool: $(objtool_target)
 
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index e79f15f108a8..ad0118fbce90 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -346,6 +346,7 @@ SECTIONS
/DISCARD/ : {
*(.eh_frame)
*(__func_stack_frame_non_standard)
+   *(__unreachable)
}
 }
 
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
index 0444b1336268..f457b520ead6 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -195,6 +195,17 @@
 #endif
 #endif
 
+#ifdef CONFIG_STACK_VALIDATION
+#define annotate_unreachable() ({  \
+   asm("%c0:\t\n"  \
+   ".pushsection __unreachable, \"a\"\t\n" \
+   ".long %c0b\t\n"\
+   ".popsection\t\n" : : "i" (__LINE__));  \
+})
+#else
+#define annotate_unreachable()
+#endif
+
 /*
  * Mark a position in code as unreachable.  This can be used to
  * suppress control flow warnings after asm blocks that transfer
@@ -204,7 +215,8 @@
  * this in the preprocessor, but we can live with this because they're
  * unreleased.  Really, we need to have autoconf for the kernel.
  */
-#define unreachable() __builtin_unreachable()
+#define unreachable() \
+   do { annotate_unreachable(); __builtin_unreachable(); } while (0)
 
 /* Mark a function definition as prohibited from being cloned. */
 #define __noclone  __attribute__((__noclone__, __optimize__("no-tracer")))
diff --git a/tools/objtool/arch.h b/tools/objtool/arch.h
index f7350fcedc70..a59e061c0b4a 100644
--- a/tools/objtool/arch.h
+++ b/tools/objtool/arch.h
@@ -31,9 +31,8 @@
 #define INSN_CALL_DYNAMIC  8
 #define INSN_RETURN9
 #define INSN_CONTEXT_SWITCH10
-#define INSN_BUG   11
-#define INSN_NOP   12
-#define INSN_OTHER 13
+#define INSN_NOP   11
+#define INSN_OTHER 12
 #define INSN_LAST  INSN_OTHER
 
 int arch_decode_instruction(struct elf *elf, struct section *sec,
diff --git a/tools/objtool/arch/x86/decode.c b/tools/objtool/arch/x86/decode.c
index 039636ffb6c8..6ac99e3266eb 100644
--- a/tools/objtool/arch/x86/decode.c
+++ b/tools/objtool/arch/x86/decode.c
@@ -118,9 +118,6 @@ int arch_decode_instruction(struct elf *elf, struct section 
*sec,
 op2 == 0x35)
/* sysenter, sysret */
*type = INSN_CONTEXT_SWITCH;
-

[GIT PULL] objtool fixes

[Ingo Molnar]

Linus,

Please pull the latest core-urgent-for-linus git tree from:

   git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 
core-urgent-for-linus

   # HEAD: 4e4636cf981b5b629fbfb78aa9f232e015f7d521 objtool: Enclose contents 
of unreachable() macro in a block

A handful of objtool fixes related to unreachable code, plus a build fix for 
out 
of tree modules.

 Thanks,

Ingo

-->
Josh Poimboeuf (4):
  objtool: Fix CONFIG_STACK_VALIDATION=y warning for out-of-tree modules
  objtool: Improve detection of BUG() and other dead ends
  objtool: Prevent GCC from merging annotate_unreachable()
  objtool: Enclose contents of unreachable() macro in a block


 Makefile| 24 -
 arch/x86/kernel/vmlinux.lds.S   |  1 +
 include/linux/compiler-gcc.h| 14 +-
 tools/objtool/arch.h|  5 ++--
 tools/objtool/arch/x86/decode.c |  3 ---
 tools/objtool/builtin-check.c   | 60 ++---
 6 files changed, 84 insertions(+), 23 deletions(-)

diff --git a/Makefile b/Makefile
index f1e6a02a0c19..32c84577aa93 100644
--- a/Makefile
+++ b/Makefile
@@ -908,6 +908,18 @@ mod_sign_cmd = true
 endif
 export mod_sign_cmd
 
+ifdef CONFIG_STACK_VALIDATION
+  has_libelf := $(call try-run,\
+   echo "int main() {}" | $(HOSTCC) -xc -o /dev/null -lelf -,1,0)
+  ifeq ($(has_libelf),1)
+objtool_target := tools/objtool FORCE
+  else
+$(warning "Cannot use CONFIG_STACK_VALIDATION, please install libelf-dev, 
libelf-devel or elfutils-libelf-devel")
+SKIP_STACK_VALIDATION := 1
+export SKIP_STACK_VALIDATION
+  endif
+endif
+
 
 ifeq ($(KBUILD_EXTMOD),)
 core-y += kernel/ certs/ mm/ fs/ ipc/ security/ crypto/ block/
@@ -1035,18 +1047,6 @@ prepare0: archprepare gcc-plugins
 # All the preparing..
 prepare: prepare0 prepare-objtool
 
-ifdef CONFIG_STACK_VALIDATION
-  has_libelf := $(call try-run,\
-   echo "int main() {}" | $(HOSTCC) -xc -o /dev/null -lelf -,1,0)
-  ifeq ($(has_libelf),1)
-objtool_target := tools/objtool FORCE
-  else
-$(warning "Cannot use CONFIG_STACK_VALIDATION, please install libelf-dev, 
libelf-devel or elfutils-libelf-devel")
-SKIP_STACK_VALIDATION := 1
-export SKIP_STACK_VALIDATION
-  endif
-endif
-
 PHONY += prepare-objtool
 prepare-objtool: $(objtool_target)
 
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index e79f15f108a8..ad0118fbce90 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -346,6 +346,7 @@ SECTIONS
/DISCARD/ : {
*(.eh_frame)
*(__func_stack_frame_non_standard)
+   *(__unreachable)
}
 }
 
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
index 0444b1336268..f457b520ead6 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -195,6 +195,17 @@
 #endif
 #endif
 
+#ifdef CONFIG_STACK_VALIDATION
+#define annotate_unreachable() ({  \
+   asm("%c0:\t\n"  \
+   ".pushsection __unreachable, \"a\"\t\n" \
+   ".long %c0b\t\n"\
+   ".popsection\t\n" : : "i" (__LINE__));  \
+})
+#else
+#define annotate_unreachable()
+#endif
+
 /*
  * Mark a position in code as unreachable.  This can be used to
  * suppress control flow warnings after asm blocks that transfer
@@ -204,7 +215,8 @@
  * this in the preprocessor, but we can live with this because they're
  * unreleased.  Really, we need to have autoconf for the kernel.
  */
-#define unreachable() __builtin_unreachable()
+#define unreachable() \
+   do { annotate_unreachable(); __builtin_unreachable(); } while (0)
 
 /* Mark a function definition as prohibited from being cloned. */
 #define __noclone  __attribute__((__noclone__, __optimize__("no-tracer")))
diff --git a/tools/objtool/arch.h b/tools/objtool/arch.h
index f7350fcedc70..a59e061c0b4a 100644
--- a/tools/objtool/arch.h
+++ b/tools/objtool/arch.h
@@ -31,9 +31,8 @@
 #define INSN_CALL_DYNAMIC  8
 #define INSN_RETURN9
 #define INSN_CONTEXT_SWITCH10
-#define INSN_BUG   11
-#define INSN_NOP   12
-#define INSN_OTHER 13
+#define INSN_NOP   11
+#define INSN_OTHER 12
 #define INSN_LAST  INSN_OTHER
 
 int arch_decode_instruction(struct elf *elf, struct section *sec,
diff --git a/tools/objtool/arch/x86/decode.c b/tools/objtool/arch/x86/decode.c
index 039636ffb6c8..6ac99e3266eb 100644
--- a/tools/objtool/arch/x86/decode.c
+++ b/tools/objtool/arch/x86/decode.c
@@ -118,9 +118,6 @@ int arch_decode_instruction(struct elf *elf, struct section 
*sec,
 op2 == 0x35)
/* sysenter, sysret */
*type = INSN_CONTEXT_SWITCH;
-

Re: next: runtime warning after 'locking/refcounts: Out-of-line everything'

[Peter Zijlstra]

On Mon, Feb 27, 2017 at 01:47:47PM -0800, Guenter Roeck wrote:
> Hi Peter,
> 
> I see the following runtime warning when running a 44x/virtex5_defconfig
> image in qemu (virtex-ml507).
> 
> refcount_t: underflow; use-after-free.
> [ cut here ]
> WARNING: CPU: 0 PID: 1 at lib/refcount.c:128 refcount_sub_and_test+0x90/0xd0
> Modules linked in:
> CPU: 0 PID: 1 Comm: swapper Not tainted 4.10.0-next-20170227 #1
> task: cf81d5a0 task.stack: cf81e000
> NIP: c02100e0 LR: c02100e0 CTR: c0279970
> REGS: cf81fc90 TRAP: 0700   Not tainted  (4.10.0-next-20170227)
> MSR: 00029000 <CE,EE,ME>
> CR: 2422  XER: 
> 
> GPR00: c02100e0 cf81fd40 cf81d5a0 0026   c027a3d0 
>  
> GPR08: c05403bc 0800   2424  c0001ad0 
>  
> GPR16:       c054b3c0 
> c055 
> GPR24:   cf948010 0015   cf948000 
> cfb1c0e8 
> NIP [c02100e0] refcount_sub_and_test+0x90/0xd0
> LR [c02100e0] refcount_sub_and_test+0x90/0xd0
> Call Trace:
> [cf81fd40] [c02100e0] refcount_sub_and_test+0x90/0xd0 (unreliable)
> [cf81fd50] [c01f6564] kobject_put+0x34/0x90
> [cf81fd60] [c02ac240] ace_probe+0x410/0x450
> [cf81fda0] [c0293684] platform_drv_probe+0x44/0xc0
> [cf81fdc0] [c0291494] driver_probe_device+0x234/0x340
> [cf81fdf0] [c029166c] __driver_attach+0xcc/0xd0
> [cf81fe10] [c028eff8] bus_for_each_dev+0x68/0xc0
> [cf81fe40] [c0290838] bus_add_driver+0x208/0x280
> [cf81fe60] [c0292198] driver_register+0x88/0x140
> [cf81fe70] [c050be10] ace_init+0x48/0xa4
> [cf81fe90] [c0001350] do_one_initcall+0x40/0x180
> [cf81fef0] [c04f2ae0] kernel_init_freeable+0x134/0x1cc
> [cf81ff30] [c0001ae4] kernel_init+0x14/0x110
> [cf81ff40] [c000c3d0] ret_from_kernel_thread+0x5c/0x64
> Instruction dump:
> 40a2fff0 7f884840 7d094378 419e0044 2f89 7d434850 7f0a4840 419e0018 
> 4099ffd0 3c60c04b 386393f0 4820e99d <0fe0> 80010014 3860 38210010 
> ---[ end trace 17bd7014e44a5b26 ]---
> xsysace 8360.sysace: xsysace: error initializing device at 0x8360
> xsysace 8360.sysace: could not initialize device, err=-12
> xsysace: probe of 8360.sysace failed with error -12
> Xilinx SystemACE device driver, major=254
> 
> The complete log is available at
> http://kerneltests.org/builders/qemu-ppc-next/builds/590/steps/qemubuildcommand/logs/stdio
> 
> Bisect points to commit 29dee3c03abc ("locking/refcounts: Out-of-line
> everything'); bisect log is attached. Reverting this commit fixes the problem.
> 
> Please let me know if there is anything I can do to help tracking down the
> problem.
> 
> [ Maybe there is a bug in the ace driver's error handler, but why is it only
>   seen with your patch applied ? ]

Because it unconditionally enables the WARNs, if you revert but enable
CONFIG_DEBUG_REFCOUNT it should show up as well.

Re: next: runtime warning after 'locking/refcounts: Out-of-line everything'

[Peter Zijlstra]

On Mon, Feb 27, 2017 at 01:47:47PM -0800, Guenter Roeck wrote:
> Hi Peter,
> 
> I see the following runtime warning when running a 44x/virtex5_defconfig
> image in qemu (virtex-ml507).
> 
> refcount_t: underflow; use-after-free.
> [ cut here ]
> WARNING: CPU: 0 PID: 1 at lib/refcount.c:128 refcount_sub_and_test+0x90/0xd0
> Modules linked in:
> CPU: 0 PID: 1 Comm: swapper Not tainted 4.10.0-next-20170227 #1
> task: cf81d5a0 task.stack: cf81e000
> NIP: c02100e0 LR: c02100e0 CTR: c0279970
> REGS: cf81fc90 TRAP: 0700   Not tainted  (4.10.0-next-20170227)
> MSR: 00029000 
> CR: 2422  XER: 
> 
> GPR00: c02100e0 cf81fd40 cf81d5a0 0026   c027a3d0 
>  
> GPR08: c05403bc 0800   2424  c0001ad0 
>  
> GPR16:       c054b3c0 
> c055 
> GPR24:   cf948010 0015   cf948000 
> cfb1c0e8 
> NIP [c02100e0] refcount_sub_and_test+0x90/0xd0
> LR [c02100e0] refcount_sub_and_test+0x90/0xd0
> Call Trace:
> [cf81fd40] [c02100e0] refcount_sub_and_test+0x90/0xd0 (unreliable)
> [cf81fd50] [c01f6564] kobject_put+0x34/0x90
> [cf81fd60] [c02ac240] ace_probe+0x410/0x450
> [cf81fda0] [c0293684] platform_drv_probe+0x44/0xc0
> [cf81fdc0] [c0291494] driver_probe_device+0x234/0x340
> [cf81fdf0] [c029166c] __driver_attach+0xcc/0xd0
> [cf81fe10] [c028eff8] bus_for_each_dev+0x68/0xc0
> [cf81fe40] [c0290838] bus_add_driver+0x208/0x280
> [cf81fe60] [c0292198] driver_register+0x88/0x140
> [cf81fe70] [c050be10] ace_init+0x48/0xa4
> [cf81fe90] [c0001350] do_one_initcall+0x40/0x180
> [cf81fef0] [c04f2ae0] kernel_init_freeable+0x134/0x1cc
> [cf81ff30] [c0001ae4] kernel_init+0x14/0x110
> [cf81ff40] [c000c3d0] ret_from_kernel_thread+0x5c/0x64
> Instruction dump:
> 40a2fff0 7f884840 7d094378 419e0044 2f89 7d434850 7f0a4840 419e0018 
> 4099ffd0 3c60c04b 386393f0 4820e99d <0fe0> 80010014 3860 38210010 
> ---[ end trace 17bd7014e44a5b26 ]---
> xsysace 8360.sysace: xsysace: error initializing device at 0x8360
> xsysace 8360.sysace: could not initialize device, err=-12
> xsysace: probe of 8360.sysace failed with error -12
> Xilinx SystemACE device driver, major=254
> 
> The complete log is available at
> http://kerneltests.org/builders/qemu-ppc-next/builds/590/steps/qemubuildcommand/logs/stdio
> 
> Bisect points to commit 29dee3c03abc ("locking/refcounts: Out-of-line
> everything'); bisect log is attached. Reverting this commit fixes the problem.
> 
> Please let me know if there is anything I can do to help tracking down the
> problem.
> 
> [ Maybe there is a bug in the ace driver's error handler, but why is it only
>   seen with your patch applied ? ]

Because it unconditionally enables the WARNs, if you revert but enable
CONFIG_DEBUG_REFCOUNT it should show up as well.

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[Amit Pragash]

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Email: amitprag...@outlook.com
Fax: (94) 11-2470740/1
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Product Inquiry

[Amit Pragash]

Hi

I would like to find out about your company and your business activities.
Please send me a brochure, product catalogue and price information. kindly send 
the following to our e-mail: amitprag...@outlook.com

Yours sincerely,
Amit Pragash
CODEGEN INTERNATIONAL PVT LTD
29, Braybrooke Street,, Colombo 02,
Email: amitprag...@outlook.com
Fax: (94) 11-2470740/1
PH: (94) 11-598

Re: [PATCH v2 2/5] KVM: add KVM request variants without barrier

[Peter Xu]

On Tue, Feb 28, 2017 at 03:34:24PM +0800, Peter Xu wrote:

[...]

> > diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c
> > index ee4af898bcf6..552ae2b5e911 100644
> > --- a/arch/mips/kvm/emulate.c
> > +++ b/arch/mips/kvm/emulate.c
> > @@ -865,7 +865,7 @@ enum emulation_result kvm_mips_emul_wait(struct 
> > kvm_vcpu *vcpu)
> >  * check if any I/O interrupts are pending.
> >  */
> > if (kvm_request_test_and_clear(KVM_REQ_UNHALT, vcpu)) {
> > -   clear_bit(KVM_REQ_UNHALT, >requests);
> > +   __kvm_request_clear(KVM_REQ_UNHALT, vcpu);
> 
> Shall we just remove above line since we cleared it already?

Please ignore this since I see patch 4. :-)

It'll be nice if patch 4 will be before this one, but it's trivial.

Thanks,

-- peterx

Re: [PATCH v2 2/5] KVM: add KVM request variants without barrier

[Peter Xu]

On Tue, Feb 28, 2017 at 03:34:24PM +0800, Peter Xu wrote:

[...]

> > diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c
> > index ee4af898bcf6..552ae2b5e911 100644
> > --- a/arch/mips/kvm/emulate.c
> > +++ b/arch/mips/kvm/emulate.c
> > @@ -865,7 +865,7 @@ enum emulation_result kvm_mips_emul_wait(struct 
> > kvm_vcpu *vcpu)
> >  * check if any I/O interrupts are pending.
> >  */
> > if (kvm_request_test_and_clear(KVM_REQ_UNHALT, vcpu)) {
> > -   clear_bit(KVM_REQ_UNHALT, >requests);
> > +   __kvm_request_clear(KVM_REQ_UNHALT, vcpu);
> 
> Shall we just remove above line since we cleared it already?

Please ignore this since I see patch 4. :-)

It'll be nice if patch 4 will be before this one, but it's trivial.

Thanks,

-- peterx

Re: [PATCH v5 2/3] nvmem: sunxi-sid: add support for H3's SID controller

[Maxime Ripard]

On Tue, Feb 28, 2017 at 03:27:14AM +0800, Icenowy Zheng wrote:
> The H3 SoC have a bigger SID controller, which has its direct read
> address at 0x200 position in the SID block, not 0x0.
> 
> Also, H3 SID controller has some silicon bug that makes the direct read
> value wrong at cold boot, add code to workaround the bug. (This bug has
> already been fixed on A64 and later SoCs)
> 
> Signed-off-by: Icenowy Zheng 

Acked-by: Maxime Ripard 

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [PATCH v5 2/3] nvmem: sunxi-sid: add support for H3's SID controller

[Maxime Ripard]

On Tue, Feb 28, 2017 at 03:27:14AM +0800, Icenowy Zheng wrote:
> The H3 SoC have a bigger SID controller, which has its direct read
> address at 0x200 position in the SID block, not 0x0.
> 
> Also, H3 SID controller has some silicon bug that makes the direct read
> value wrong at cold boot, add code to workaround the bug. (This bug has
> already been fixed on A64 and later SoCs)
> 
> Signed-off-by: Icenowy Zheng 

Acked-by: Maxime Ripard 

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [PATCH v2 2/5] KVM: add KVM request variants without barrier

[Peter Xu]

On Fri, Feb 24, 2017 at 08:49:59PM +0100, Radim Krčmář wrote:
> The leading underscores denote that the call is just a bitop wrapper.
> 
> Switch all users of open-coded set/check/test to kvm_request ones.
> 
> Automated by coccinelle script:
>   @@
>   expression VCPU, REQ;
>   @@
>   -set_bit(REQ, >requests)
>   +__kvm_request_set(REQ, VCPU)
> 
>   @@
>   expression VCPU, REQ;
>   @@
>   -clear_bit(REQ, >requests)
>   +__kvm_request_clear(REQ, VCPU)
> 
>   @@
>   expression VCPU, REQ;
>   @@
>   -test_bit(REQ, >requests)
>   +__kvm_request_test(REQ, VCPU)
> 
> Signed-off-by: Radim Krčmář 
> ---
>  v2: clear_bit in __kvm_request_clear [Paolo]
> ---
>  arch/mips/kvm/emulate.c   |  2 +-
>  arch/powerpc/kvm/book3s_pr.c  |  2 +-
>  arch/powerpc/kvm/book3s_pr_papr.c |  2 +-
>  arch/powerpc/kvm/booke.c  |  4 ++--
>  arch/powerpc/kvm/powerpc.c|  2 +-
>  arch/s390/kvm/kvm-s390.c  |  2 +-
>  arch/x86/kvm/vmx.c|  2 +-
>  arch/x86/kvm/x86.c| 14 +++---
>  include/linux/kvm_host.h  | 23 ---
>  9 files changed, 35 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c
> index ee4af898bcf6..552ae2b5e911 100644
> --- a/arch/mips/kvm/emulate.c
> +++ b/arch/mips/kvm/emulate.c
> @@ -865,7 +865,7 @@ enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu 
> *vcpu)
>* check if any I/O interrupts are pending.
>*/
>   if (kvm_request_test_and_clear(KVM_REQ_UNHALT, vcpu)) {
> - clear_bit(KVM_REQ_UNHALT, >requests);
> + __kvm_request_clear(KVM_REQ_UNHALT, vcpu);

Shall we just remove above line since we cleared it already?

-- peterx

Re: [PATCH v2 2/5] KVM: add KVM request variants without barrier

[Peter Xu]

On Fri, Feb 24, 2017 at 08:49:59PM +0100, Radim Krčmář wrote:
> The leading underscores denote that the call is just a bitop wrapper.
> 
> Switch all users of open-coded set/check/test to kvm_request ones.
> 
> Automated by coccinelle script:
>   @@
>   expression VCPU, REQ;
>   @@
>   -set_bit(REQ, >requests)
>   +__kvm_request_set(REQ, VCPU)
> 
>   @@
>   expression VCPU, REQ;
>   @@
>   -clear_bit(REQ, >requests)
>   +__kvm_request_clear(REQ, VCPU)
> 
>   @@
>   expression VCPU, REQ;
>   @@
>   -test_bit(REQ, >requests)
>   +__kvm_request_test(REQ, VCPU)
> 
> Signed-off-by: Radim Krčmář 
> ---
>  v2: clear_bit in __kvm_request_clear [Paolo]
> ---
>  arch/mips/kvm/emulate.c   |  2 +-
>  arch/powerpc/kvm/book3s_pr.c  |  2 +-
>  arch/powerpc/kvm/book3s_pr_papr.c |  2 +-
>  arch/powerpc/kvm/booke.c  |  4 ++--
>  arch/powerpc/kvm/powerpc.c|  2 +-
>  arch/s390/kvm/kvm-s390.c  |  2 +-
>  arch/x86/kvm/vmx.c|  2 +-
>  arch/x86/kvm/x86.c| 14 +++---
>  include/linux/kvm_host.h  | 23 ---
>  9 files changed, 35 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c
> index ee4af898bcf6..552ae2b5e911 100644
> --- a/arch/mips/kvm/emulate.c
> +++ b/arch/mips/kvm/emulate.c
> @@ -865,7 +865,7 @@ enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu 
> *vcpu)
>* check if any I/O interrupts are pending.
>*/
>   if (kvm_request_test_and_clear(KVM_REQ_UNHALT, vcpu)) {
> - clear_bit(KVM_REQ_UNHALT, >requests);
> + __kvm_request_clear(KVM_REQ_UNHALT, vcpu);

Shall we just remove above line since we cleared it already?

-- peterx

Re: [PATCH 1/2] x86/mm/numa: trivial fix on typo and error message

[Wei Yang]

Hope someone like these two patches.

On Mon, Feb 06, 2017 at 11:35:28PM +0800, Wei Yang wrote:
>When allocating pg_data in alloc_node_data(), it will try to allocate from
>local node first and then from any node. If it fails at the second trial,
>it means there is not available memory on any node.
>
>This patch fixes the error message and correct one typo.
>
>Signed-off-by: Wei Yang 
>---
> arch/x86/mm/numa.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
>diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
>index 4366242356c5..3e9110b34147 100644
>--- a/arch/x86/mm/numa.c
>+++ b/arch/x86/mm/numa.c
>@@ -201,8 +201,8 @@ static void __init alloc_node_data(int nid)
>   nd_pa = __memblock_alloc_base(nd_size, SMP_CACHE_BYTES,
> MEMBLOCK_ALLOC_ACCESSIBLE);
>   if (!nd_pa) {
>-  pr_err("Cannot find %zu bytes in node %d\n",
>- nd_size, nid);
>+  pr_err("Cannot find %zu bytes in any node\n",
>+ nd_size);
>   return;
>   }
>   }
>@@ -225,7 +225,7 @@ static void __init alloc_node_data(int nid)
>  * numa_cleanup_meminfo - Cleanup a numa_meminfo
>  * @mi: numa_meminfo to clean up
>  *
>- * Sanitize @mi by merging and removing unncessary memblks.  Also check for
>+ * Sanitize @mi by merging and removing unnecessary memblks.  Also check for
>  * conflicts and clear unused memblks.
>  *
>  * RETURNS:
>-- 
>2.11.0

-- 
Wei Yang
Help you, Help me


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Re: [PATCH 1/2] x86/mm/numa: trivial fix on typo and error message

[Wei Yang]

Hope someone like these two patches.

On Mon, Feb 06, 2017 at 11:35:28PM +0800, Wei Yang wrote:
>When allocating pg_data in alloc_node_data(), it will try to allocate from
>local node first and then from any node. If it fails at the second trial,
>it means there is not available memory on any node.
>
>This patch fixes the error message and correct one typo.
>
>Signed-off-by: Wei Yang 
>---
> arch/x86/mm/numa.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
>diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
>index 4366242356c5..3e9110b34147 100644
>--- a/arch/x86/mm/numa.c
>+++ b/arch/x86/mm/numa.c
>@@ -201,8 +201,8 @@ static void __init alloc_node_data(int nid)
>   nd_pa = __memblock_alloc_base(nd_size, SMP_CACHE_BYTES,
> MEMBLOCK_ALLOC_ACCESSIBLE);
>   if (!nd_pa) {
>-  pr_err("Cannot find %zu bytes in node %d\n",
>- nd_size, nid);
>+  pr_err("Cannot find %zu bytes in any node\n",
>+ nd_size);
>   return;
>   }
>   }
>@@ -225,7 +225,7 @@ static void __init alloc_node_data(int nid)
>  * numa_cleanup_meminfo - Cleanup a numa_meminfo
>  * @mi: numa_meminfo to clean up
>  *
>- * Sanitize @mi by merging and removing unncessary memblks.  Also check for
>+ * Sanitize @mi by merging and removing unnecessary memblks.  Also check for
>  * conflicts and clear unused memblks.
>  *
>  * RETURNS:
>-- 
>2.11.0

-- 
Wei Yang
Help you, Help me


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Re: [PATCH v1] mmc: mediatek: Fixed bug where clock frequency could be set wrong

[Daniel Kurtz]

On Fri, Feb 24, 2017 at 5:38 PM, Yong Mao  wrote:
> From:   Yong Mao 
> To: Daniel Kurtz 
> Subject:Re: [PATCH v1] mmc: mediatek: Fixed bug where clock frequency
> could be set wrong
> Date:   Fri, 24 Feb 2017 17:33:37 +0800
>
>
> On Fri, 2017-02-24 at 17:52 +0900, Daniel Kurtz wrote:
>> On Fri, Feb 24, 2017 at 5:22 PM, Yong Mao 
> wrote:
>> >
>> > From: yong mao 
>> >
>> > This patch can fix two issues:
>> >
>> > Issue 1:
>> > The maximum value of clock divider is 0xff.
>> > Because the type of div is u32, div may be larger than max_div.
>> > In this case, we should use max_div to set the clock frequency.
>> >
>> > Issue 2:
>> > In previous code, we can not set the correct clock frequency when
>> > div equals 0xff.
>> >
>> > Signed-off-by: Yong Mao 
>> > Signed-off-by: Chaotian Jing 
>> > ---
>> >  drivers/mmc/host/mtk-sd.c |   13 -
>> >  1 file changed, 12 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
>> > index 07f3236..3174445 100644
>> > --- a/drivers/mmc/host/mtk-sd.c
>> > +++ b/drivers/mmc/host/mtk-sd.c
>> > @@ -540,6 +540,7 @@ static void msdc_set_mclk(struct msdc_host
> *host, unsigned char timing, u32 hz)
>> > u32 mode;
>> > u32 flags;
>> > u32 div;
>> > +   u32 max_div;
>>
>> There's really no need for this variable.  Just use 0xff below.
> For all of our IC, max_div is not a constant.
> We will upstream another patch which max_div will get the different
> value depending on the IC.
> Therefore, we keep the max_div as a variable here.

Please add the variable in the patch that uses it as a variable.

>
>>
>> > u32 sclk;
>> >
>> > if (!hz) {
>> > @@ -590,8 +591,18 @@ static void msdc_set_mclk(struct msdc_host
> *host, unsigned char timing, u32 hz)
>> > sclk = (host->src_clk_freq >> 2) / div;
>> > }
>> > }
>> > +
>> > +   /**
>> > +* The maximum value of div is 0xff.
>> > +* Check if the div is larger than max_div.
>> > +*/
>> > +   max_div = 0xff;
>> > +   if (div > max_div) {
>> > +   div = max_div;
>> > +   sclk = (host->src_clk_freq >> 2) / div;
>> > +   }
>> > sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD |
> MSDC_CFG_CKDIV,
>> > -   (mode << 8) | (div % 0xff));
>> > + (mode << 8) | div);
>>
>> Hmm, I don't know much about this sub-system, but should we even be
>> allowing requests to set a frequency that we can't actually achieve
>> with the divider?
>>
>
> No. We can not get a frequency that we can't actually achieve with the
> divider. This patch is to solve this kind of issue.

Sorry, I am trying to understand why we need this patch.

AFAICT, it looks like sometimes msdc_set_mclk() is being called with
hz that cannot be generated by your hardware.  In particular,
sometimes the original code computes "div > 255".
To work around this problem, this patch just caps the divider value to
255, which is the maximum divider provided by the hardware.  However,
presumably this means that in this case we won't actually be
generating the requested hz value.

So, can you please explain in what exact scenario this patch is
required, and justify why it is ok to generate a clock other than the
requested in this case?

-Dan

>
>
>> > sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
>> > while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
>> > cpu_relax();
>> > --
>> > 1.7.9.5
>> >
>> >
>> > ___
>> > Linux-mediatek mailing list
>> > linux-media...@lists.infradead.org
>> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
>
>

Re: [PATCH v1] mmc: mediatek: Fixed bug where clock frequency could be set wrong

[Daniel Kurtz]

On Fri, Feb 24, 2017 at 5:38 PM, Yong Mao  wrote:
> From:   Yong Mao 
> To: Daniel Kurtz 
> Subject:Re: [PATCH v1] mmc: mediatek: Fixed bug where clock frequency
> could be set wrong
> Date:   Fri, 24 Feb 2017 17:33:37 +0800
>
>
> On Fri, 2017-02-24 at 17:52 +0900, Daniel Kurtz wrote:
>> On Fri, Feb 24, 2017 at 5:22 PM, Yong Mao 
> wrote:
>> >
>> > From: yong mao 
>> >
>> > This patch can fix two issues:
>> >
>> > Issue 1:
>> > The maximum value of clock divider is 0xff.
>> > Because the type of div is u32, div may be larger than max_div.
>> > In this case, we should use max_div to set the clock frequency.
>> >
>> > Issue 2:
>> > In previous code, we can not set the correct clock frequency when
>> > div equals 0xff.
>> >
>> > Signed-off-by: Yong Mao 
>> > Signed-off-by: Chaotian Jing 
>> > ---
>> >  drivers/mmc/host/mtk-sd.c |   13 -
>> >  1 file changed, 12 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
>> > index 07f3236..3174445 100644
>> > --- a/drivers/mmc/host/mtk-sd.c
>> > +++ b/drivers/mmc/host/mtk-sd.c
>> > @@ -540,6 +540,7 @@ static void msdc_set_mclk(struct msdc_host
> *host, unsigned char timing, u32 hz)
>> > u32 mode;
>> > u32 flags;
>> > u32 div;
>> > +   u32 max_div;
>>
>> There's really no need for this variable.  Just use 0xff below.
> For all of our IC, max_div is not a constant.
> We will upstream another patch which max_div will get the different
> value depending on the IC.
> Therefore, we keep the max_div as a variable here.

Please add the variable in the patch that uses it as a variable.

>
>>
>> > u32 sclk;
>> >
>> > if (!hz) {
>> > @@ -590,8 +591,18 @@ static void msdc_set_mclk(struct msdc_host
> *host, unsigned char timing, u32 hz)
>> > sclk = (host->src_clk_freq >> 2) / div;
>> > }
>> > }
>> > +
>> > +   /**
>> > +* The maximum value of div is 0xff.
>> > +* Check if the div is larger than max_div.
>> > +*/
>> > +   max_div = 0xff;
>> > +   if (div > max_div) {
>> > +   div = max_div;
>> > +   sclk = (host->src_clk_freq >> 2) / div;
>> > +   }
>> > sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD |
> MSDC_CFG_CKDIV,
>> > -   (mode << 8) | (div % 0xff));
>> > + (mode << 8) | div);
>>
>> Hmm, I don't know much about this sub-system, but should we even be
>> allowing requests to set a frequency that we can't actually achieve
>> with the divider?
>>
>
> No. We can not get a frequency that we can't actually achieve with the
> divider. This patch is to solve this kind of issue.

Sorry, I am trying to understand why we need this patch.

AFAICT, it looks like sometimes msdc_set_mclk() is being called with
hz that cannot be generated by your hardware.  In particular,
sometimes the original code computes "div > 255".
To work around this problem, this patch just caps the divider value to
255, which is the maximum divider provided by the hardware.  However,
presumably this means that in this case we won't actually be
generating the requested hz value.

So, can you please explain in what exact scenario this patch is
required, and justify why it is ok to generate a clock other than the
requested in this case?

-Dan

>
>
>> > sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
>> > while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
>> > cpu_relax();
>> > --
>> > 1.7.9.5
>> >
>> >
>> > ___
>> > Linux-mediatek mailing list
>> > linux-media...@lists.infradead.org
>> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
>
>

Re: [PATCH 1/2] mm/memblock: use NUMA_NO_NODE instead of MAX_NUMNODES as default node_id

[Wei Yang]

Hi, everyone

Looking for some comment on these two patches :-)

On Fri, Jan 27, 2017 at 09:59:21AM +0800, Wei Yang wrote:
>According to commit  ('mm/memblock: switch to use
>NUMA_NO_NODE instead of MAX_NUMNODES'), MAX_NUMNODES is not preferred as an
>node_id indicator.
>
>This patch use NUMA_NO_NODE as the default node_id for memblock.
>
>Signed-off-by: Wei Yang 
>---
> arch/x86/mm/numa.c | 6 +++---
> mm/memblock.c  | 8 
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
>diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
>index 3f35b48d1d9d..4366242356c5 100644
>--- a/arch/x86/mm/numa.c
>+++ b/arch/x86/mm/numa.c
>@@ -506,7 +506,7 @@ static void __init numa_clear_kernel_node_hotplug(void)
>*   reserve specific pages for Sandy Bridge graphics. ]
>*/
>   for_each_memblock(reserved, mb_region) {
>-  if (mb_region->nid != MAX_NUMNODES)
>+  if (mb_region->nid != NUMA_NO_NODE)
>   node_set(mb_region->nid, reserved_nodemask);
>   }
> 
>@@ -633,9 +633,9 @@ static int __init numa_init(int (*init_func)(void))
>   nodes_clear(node_online_map);
>   memset(_meminfo, 0, sizeof(numa_meminfo));
>   WARN_ON(memblock_set_node(0, ULLONG_MAX, ,
>-MAX_NUMNODES));
>+NUMA_NO_NODE));
>   WARN_ON(memblock_set_node(0, ULLONG_MAX, ,
>-MAX_NUMNODES));
>+NUMA_NO_NODE));
>   /* In case that parsing SRAT failed. */
>   WARN_ON(memblock_clear_hotplug(0, ULLONG_MAX));
>   numa_reset_distance();
>diff --git a/mm/memblock.c b/mm/memblock.c
>index d0f2c9632187..7d27566cee11 100644
>--- a/mm/memblock.c
>+++ b/mm/memblock.c
>@@ -292,7 +292,7 @@ static void __init_memblock memblock_remove_region(struct 
>memblock_type *type, u
>   type->regions[0].base = 0;
>   type->regions[0].size = 0;
>   type->regions[0].flags = 0;
>-  memblock_set_region_node(>regions[0], MAX_NUMNODES);
>+  memblock_set_region_node(>regions[0], NUMA_NO_NODE);
>   }
> }
> 
>@@ -616,7 +616,7 @@ int __init_memblock memblock_add(phys_addr_t base, 
>phys_addr_t size)
>(unsigned long long)base + size - 1,
>0UL, (void *)_RET_IP_);
> 
>-  return memblock_add_range(, base, size, MAX_NUMNODES, 
>0);
>+  return memblock_add_range(, base, size, NUMA_NO_NODE, 
>0);
> }
> 
> /**
>@@ -734,7 +734,7 @@ int __init_memblock memblock_reserve(phys_addr_t base, 
>phys_addr_t size)
>(unsigned long long)base + size - 1,
>0UL, (void *)_RET_IP_);
> 
>-  return memblock_add_range(, base, size, MAX_NUMNODES, 
>0);
>+  return memblock_add_range(, base, size, NUMA_NO_NODE, 
>0);
> }
> 
> /**
>@@ -1684,7 +1684,7 @@ static void __init_memblock memblock_dump(struct 
>memblock_type *type, char *name
>   size = rgn->size;
>   flags = rgn->flags;
> #ifdef CONFIG_HAVE_MEMBLOCK_NODE_MAP
>-  if (memblock_get_region_node(rgn) != MAX_NUMNODES)
>+  if (memblock_get_region_node(rgn) != NUMA_NO_NODE)
>   snprintf(nid_buf, sizeof(nid_buf), " on node %d",
>memblock_get_region_node(rgn));
> #endif
>-- 
>2.11.0

-- 
Wei Yang
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Re: [PATCH 1/2] mm/memblock: use NUMA_NO_NODE instead of MAX_NUMNODES as default node_id

[Wei Yang]

Hi, everyone

Looking for some comment on these two patches :-)

On Fri, Jan 27, 2017 at 09:59:21AM +0800, Wei Yang wrote:
>According to commit  ('mm/memblock: switch to use
>NUMA_NO_NODE instead of MAX_NUMNODES'), MAX_NUMNODES is not preferred as an
>node_id indicator.
>
>This patch use NUMA_NO_NODE as the default node_id for memblock.
>
>Signed-off-by: Wei Yang 
>---
> arch/x86/mm/numa.c | 6 +++---
> mm/memblock.c  | 8 
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
>diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
>index 3f35b48d1d9d..4366242356c5 100644
>--- a/arch/x86/mm/numa.c
>+++ b/arch/x86/mm/numa.c
>@@ -506,7 +506,7 @@ static void __init numa_clear_kernel_node_hotplug(void)
>*   reserve specific pages for Sandy Bridge graphics. ]
>*/
>   for_each_memblock(reserved, mb_region) {
>-  if (mb_region->nid != MAX_NUMNODES)
>+  if (mb_region->nid != NUMA_NO_NODE)
>   node_set(mb_region->nid, reserved_nodemask);
>   }
> 
>@@ -633,9 +633,9 @@ static int __init numa_init(int (*init_func)(void))
>   nodes_clear(node_online_map);
>   memset(_meminfo, 0, sizeof(numa_meminfo));
>   WARN_ON(memblock_set_node(0, ULLONG_MAX, ,
>-MAX_NUMNODES));
>+NUMA_NO_NODE));
>   WARN_ON(memblock_set_node(0, ULLONG_MAX, ,
>-MAX_NUMNODES));
>+NUMA_NO_NODE));
>   /* In case that parsing SRAT failed. */
>   WARN_ON(memblock_clear_hotplug(0, ULLONG_MAX));
>   numa_reset_distance();
>diff --git a/mm/memblock.c b/mm/memblock.c
>index d0f2c9632187..7d27566cee11 100644
>--- a/mm/memblock.c
>+++ b/mm/memblock.c
>@@ -292,7 +292,7 @@ static void __init_memblock memblock_remove_region(struct 
>memblock_type *type, u
>   type->regions[0].base = 0;
>   type->regions[0].size = 0;
>   type->regions[0].flags = 0;
>-  memblock_set_region_node(>regions[0], MAX_NUMNODES);
>+  memblock_set_region_node(>regions[0], NUMA_NO_NODE);
>   }
> }
> 
>@@ -616,7 +616,7 @@ int __init_memblock memblock_add(phys_addr_t base, 
>phys_addr_t size)
>(unsigned long long)base + size - 1,
>0UL, (void *)_RET_IP_);
> 
>-  return memblock_add_range(, base, size, MAX_NUMNODES, 
>0);
>+  return memblock_add_range(, base, size, NUMA_NO_NODE, 
>0);
> }
> 
> /**
>@@ -734,7 +734,7 @@ int __init_memblock memblock_reserve(phys_addr_t base, 
>phys_addr_t size)
>(unsigned long long)base + size - 1,
>0UL, (void *)_RET_IP_);
> 
>-  return memblock_add_range(, base, size, MAX_NUMNODES, 
>0);
>+  return memblock_add_range(, base, size, NUMA_NO_NODE, 
>0);
> }
> 
> /**
>@@ -1684,7 +1684,7 @@ static void __init_memblock memblock_dump(struct 
>memblock_type *type, char *name
>   size = rgn->size;
>   flags = rgn->flags;
> #ifdef CONFIG_HAVE_MEMBLOCK_NODE_MAP
>-  if (memblock_get_region_node(rgn) != MAX_NUMNODES)
>+  if (memblock_get_region_node(rgn) != NUMA_NO_NODE)
>   snprintf(nid_buf, sizeof(nid_buf), " on node %d",
>memblock_get_region_node(rgn));
> #endif
>-- 
>2.11.0

-- 
Wei Yang
Help you, Help me


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[NAND Question] When oob_required is used?

[Masahiro Yamada]

Hi.


I am seeing the reference implementations for the callback
in drivers/mtd/nand/nand_base.c


I see only some of them use the argument "oob_required".


- oob_required is used
nand_read_page_raw()
nand_write_page_raw()
nand_write_subpage_hwecc()


- oob_required is ignored
nand_read_page_raw_syndrome()
nand_read_page_swecc()
nand_read_page_hwecc()
nand_read_page_hwecc_oob_first()
nand_read_page_syndrome()
nand_write_page_raw_syndrome()
nand_write_page_swecc()
nand_write_page_hwecc()
nand_write_page_syndrome()



I could not get the logic
when "oob_required" is used.



When implementing drivers, the "oob_required"
should be respected (i.e. oob_poi should be transferred as well),
or is it OK to ignore it?




-- 
Best Regards
Masahiro Yamada

[NAND Question] When oob_required is used?

[Masahiro Yamada]

Hi.


I am seeing the reference implementations for the callback
in drivers/mtd/nand/nand_base.c


I see only some of them use the argument "oob_required".


- oob_required is used
nand_read_page_raw()
nand_write_page_raw()
nand_write_subpage_hwecc()


- oob_required is ignored
nand_read_page_raw_syndrome()
nand_read_page_swecc()
nand_read_page_hwecc()
nand_read_page_hwecc_oob_first()
nand_read_page_syndrome()
nand_write_page_raw_syndrome()
nand_write_page_swecc()
nand_write_page_hwecc()
nand_write_page_syndrome()



I could not get the logic
when "oob_required" is used.



When implementing drivers, the "oob_required"
should be respected (i.e. oob_poi should be transferred as well),
or is it OK to ignore it?




-- 
Best Regards
Masahiro Yamada

Re: [PATCH v2 2/3] remoteproc: qcom: Add scm call to protect modem mem in mss rproc drv.

[Stephen Boyd]

On 01/30, Avaneesh Kumar Dwivedi wrote:
> This patch add hypervisor call support for second stage translation from
> mss remoteproc driver, this is required so that modem on msm8996 which is
> based on armv8 architecture can access DDR region where modem firmware
> are loaded.
> 
> Signed-off-by: Avaneesh Kumar Dwivedi 
> ---

Most of this should be combined with patch 1 from this series.

>  drivers/remoteproc/qcom_q6v5_pil.c | 202 
> -
>  1 file changed, 198 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c 
> b/drivers/remoteproc/qcom_q6v5_pil.c
> index e5edefa..35eee68 100644
> --- a/drivers/remoteproc/qcom_q6v5_pil.c
> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
> @@ -93,6 +93,23 @@
>  #define QDSS_BHS_ON  BIT(21)
>  #define QDSS_LDO_BYP BIT(22)
>  
> +struct dest_vm_and_perm_info {
> + __le32 vm;
> + __le32 perm;
> + __le32 *ctx;
> + __le32 ctx_size;
> +};
> +
> +struct mem_prot_info {
> + __le64 addr;
> + __le64 size;
> +};
> +
> +struct scm_desc {
> + __le32 arginfo;
> + __le64 args[10];
> +};

These are all firmware specific things that should live in scm
code, not PIL code.

> +
>  struct reg_info {
>   struct regulator *reg;
>   int uV;
> @@ -111,6 +128,7 @@ struct rproc_hexagon_res {
>   struct qcom_mss_reg_res active_supply[2];
>   char **proxy_clk_names;
>   char **active_clk_names;
> + int version;
>  };
>  
>  struct q6v5 {
> @@ -152,8 +170,29 @@ struct q6v5 {
>   phys_addr_t mpss_reloc;
>   void *mpss_region;
>   size_t mpss_size;
> + int version;
> + int protection_cmd;
> +};
> +
> +enum {
> + MSS_MSM8916,
> + MSS_MSM8974,
> + MSS_MSM8996,
>  };
>  
> +enum {
> + ASSIG_ACCESS_MSA,
> + REMOV_ACCESS_MSA,
> + SHARE_ACCESS_MSA,
> + REMOV_SHARE_MSA,
> +};
> +
> +#define VMID_HLOS0x3
> +#define VMID_MSS_MSA 0xF
> +#define PERM_READ0x4
> +#define PERM_WRITE   0x2
> +#define PERM_EXEC0x1
> +#define PERM_RW  (0x4 | 0x2)

Please USE PERM_READ | PERM_WRITE here instead.

>  static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
>   const struct qcom_mss_reg_res *reg_res)
>  {
> @@ -273,12 +312,123 @@ static void q6v5_clk_disable(struct device *dev,
>   clk_disable_unprepare(clks[i]);
>  }
>  
> +int hyp_mem_access(struct q6v5 *qproc, phys_addr_t addr, size_t size)

This could be the scm API for now. But instead of taking qproc,
it would take the protection_cmd variable (which looks sort of
like a state machine BTW). To be more generic, perhaps it should
take the src vmids + num src vmids, dst vmids + num dst vmids,
and protection flags (which looks to be same size as dst vmid
array). If we can get the right SCM API here everything else
should fall into place.

> +{
> + unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
> + struct dest_vm_and_perm_info *dest_info;
> + struct mem_prot_info *mem_prot_info;
> + struct scm_desc desc = {0};
> + __le32 *source_vm_copy;
> + __le64 mem_prot_phy;
> + int dest_count = 1;
> + int src_count = 1;
> + __le32 *perm = {0};
> + __le32 *dest = {0};
> + __le32 *src = {0};

src/dst seem like pretty confusing names. It makes it sound like
a memcpy operation. Perhaps from/to is better? Or current/next.

> + __le64 phys_src;
> + __le64 phy_dest;
> + int ret;
> + int i;
> +
> + if (qproc->version != MSS_MSM8996)
> + return 0;
> +
> + switch (qproc->protection_cmd) {
> + case ASSIG_ACCESS_MSA: {
> + src = (int[2]) {VMID_HLOS, 0};
> + dest = (int[2]) {VMID_MSS_MSA, 0};
> + perm = (int[2]) {PERM_READ | PERM_WRITE, 0};

Why have two element arrays when we're only using the first
element? Relying on default src_count of 1 is very confusing.

> + break;
> + }
> + case REMOV_ACCESS_MSA: {
> + src = (int[2]) {VMID_MSS_MSA, 0};
> + dest = (int[2]) {VMID_HLOS, 0};
> + perm = (int[2]) {PERM_READ | PERM_WRITE | PERM_EXEC, 0};

Same here.

> + break;
> + }
> + case SHARE_ACCESS_MSA: {
> + src = (int[2]) {VMID_HLOS, 0};
> + dest = (int[2]) {VMID_HLOS, VMID_MSS_MSA};
> + perm = (int[2]) {PERM_RW, PERM_RW};

Please add spaces around curly braces like { this }

> + dest_count = 2;
> + break;
> + }
> + case REMOV_SHARE_MSA: {

And write REMOVE_SHARE_MSA, ASSIGN_ACCESS_MSA, etc. instead of
dropping letters.

> + src = (int[2]) {VMID_HLOS, VMID_MSS_MSA};
> + dest = (int[2]) {VMID_HLOS, 0};
> + perm = (int[2]) {PERM_READ 

Re: [PATCH v2 2/3] remoteproc: qcom: Add scm call to protect modem mem in mss rproc drv.

[Stephen Boyd]

On 01/30, Avaneesh Kumar Dwivedi wrote:
> This patch add hypervisor call support for second stage translation from
> mss remoteproc driver, this is required so that modem on msm8996 which is
> based on armv8 architecture can access DDR region where modem firmware
> are loaded.
> 
> Signed-off-by: Avaneesh Kumar Dwivedi 
> ---

Most of this should be combined with patch 1 from this series.

>  drivers/remoteproc/qcom_q6v5_pil.c | 202 
> -
>  1 file changed, 198 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c 
> b/drivers/remoteproc/qcom_q6v5_pil.c
> index e5edefa..35eee68 100644
> --- a/drivers/remoteproc/qcom_q6v5_pil.c
> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
> @@ -93,6 +93,23 @@
>  #define QDSS_BHS_ON  BIT(21)
>  #define QDSS_LDO_BYP BIT(22)
>  
> +struct dest_vm_and_perm_info {
> + __le32 vm;
> + __le32 perm;
> + __le32 *ctx;
> + __le32 ctx_size;
> +};
> +
> +struct mem_prot_info {
> + __le64 addr;
> + __le64 size;
> +};
> +
> +struct scm_desc {
> + __le32 arginfo;
> + __le64 args[10];
> +};

These are all firmware specific things that should live in scm
code, not PIL code.

> +
>  struct reg_info {
>   struct regulator *reg;
>   int uV;
> @@ -111,6 +128,7 @@ struct rproc_hexagon_res {
>   struct qcom_mss_reg_res active_supply[2];
>   char **proxy_clk_names;
>   char **active_clk_names;
> + int version;
>  };
>  
>  struct q6v5 {
> @@ -152,8 +170,29 @@ struct q6v5 {
>   phys_addr_t mpss_reloc;
>   void *mpss_region;
>   size_t mpss_size;
> + int version;
> + int protection_cmd;
> +};
> +
> +enum {
> + MSS_MSM8916,
> + MSS_MSM8974,
> + MSS_MSM8996,
>  };
>  
> +enum {
> + ASSIG_ACCESS_MSA,
> + REMOV_ACCESS_MSA,
> + SHARE_ACCESS_MSA,
> + REMOV_SHARE_MSA,
> +};
> +
> +#define VMID_HLOS0x3
> +#define VMID_MSS_MSA 0xF
> +#define PERM_READ0x4
> +#define PERM_WRITE   0x2
> +#define PERM_EXEC0x1
> +#define PERM_RW  (0x4 | 0x2)

Please USE PERM_READ | PERM_WRITE here instead.

>  static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
>   const struct qcom_mss_reg_res *reg_res)
>  {
> @@ -273,12 +312,123 @@ static void q6v5_clk_disable(struct device *dev,
>   clk_disable_unprepare(clks[i]);
>  }
>  
> +int hyp_mem_access(struct q6v5 *qproc, phys_addr_t addr, size_t size)

This could be the scm API for now. But instead of taking qproc,
it would take the protection_cmd variable (which looks sort of
like a state machine BTW). To be more generic, perhaps it should
take the src vmids + num src vmids, dst vmids + num dst vmids,
and protection flags (which looks to be same size as dst vmid
array). If we can get the right SCM API here everything else
should fall into place.

> +{
> + unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
> + struct dest_vm_and_perm_info *dest_info;
> + struct mem_prot_info *mem_prot_info;
> + struct scm_desc desc = {0};
> + __le32 *source_vm_copy;
> + __le64 mem_prot_phy;
> + int dest_count = 1;
> + int src_count = 1;
> + __le32 *perm = {0};
> + __le32 *dest = {0};
> + __le32 *src = {0};

src/dst seem like pretty confusing names. It makes it sound like
a memcpy operation. Perhaps from/to is better? Or current/next.

> + __le64 phys_src;
> + __le64 phy_dest;
> + int ret;
> + int i;
> +
> + if (qproc->version != MSS_MSM8996)
> + return 0;
> +
> + switch (qproc->protection_cmd) {
> + case ASSIG_ACCESS_MSA: {
> + src = (int[2]) {VMID_HLOS, 0};
> + dest = (int[2]) {VMID_MSS_MSA, 0};
> + perm = (int[2]) {PERM_READ | PERM_WRITE, 0};

Why have two element arrays when we're only using the first
element? Relying on default src_count of 1 is very confusing.

> + break;
> + }
> + case REMOV_ACCESS_MSA: {
> + src = (int[2]) {VMID_MSS_MSA, 0};
> + dest = (int[2]) {VMID_HLOS, 0};
> + perm = (int[2]) {PERM_READ | PERM_WRITE | PERM_EXEC, 0};

Same here.

> + break;
> + }
> + case SHARE_ACCESS_MSA: {
> + src = (int[2]) {VMID_HLOS, 0};
> + dest = (int[2]) {VMID_HLOS, VMID_MSS_MSA};
> + perm = (int[2]) {PERM_RW, PERM_RW};

Please add spaces around curly braces like { this }

> + dest_count = 2;
> + break;
> + }
> + case REMOV_SHARE_MSA: {

And write REMOVE_SHARE_MSA, ASSIGN_ACCESS_MSA, etc. instead of
dropping letters.

> + src = (int[2]) {VMID_HLOS, VMID_MSS_MSA};
> + dest = (int[2]) {VMID_HLOS, 0};
> + perm = (int[2]) {PERM_READ | PERM_WRITE | 

[PATCH] arm64: dump: hide kernel pointers

[Miles Chen]

Mask kernel pointers of /sys/kernel/debug/kernel_page_tables entry like
/proc/vmallocinfo does.

With sysctl kernel.kptr_restrict=0 or 1:
cat /sys/kernel/debug/kernel_page_tables
---[ Modules start ]---
---[ Modules end ]---
---[ vmalloc() Area ]---
ff800800-ff800801  64K PTE   RW NX SHD AF...
ff8008015000-ff8008016000   4K PTE   RW NX SHD AF...
ff800802-ff800803  64K PTE   RW NX SHD AF...
ff8008031000-ff8008071000 256K PTE   RW NX SHD AF...
ff800808-ff8008201536K PTE   ro x  SHD AF...
ff800820-ff800840   2M PMD   ro x  SHD AF...
ff800840-ff8008541280K PTE   ro x  SHD AF...
ff800854-ff8008691344K PTE   ro NX SHD AF...
ff800894-ff8008a1 832K PTE   RW NX SHD AF...
ff8008aca000-ff8008acd000  12K PTE   RW NX SHD AF...
ffbebffd8000-ffbebffdb000  12K PTE   RW NX SHD AF...
---[ vmalloc() End ]---
---[ Fixmap start ]---
ffbefe80-ffbefea0   2M PMD   ro NX SHD AF...
---[ Fixmap end ]---
---[ PCI I/O start ]---
---[ PCI I/O end ]---
---[ Linear Mapping ]---
ffc0-ffc8 512K PTE   RW NX SHD AF...
ffc8-ffc000201536K PTE   ro NX SHD AF...
ffc00020-ffc00060   4M PMD   ro NX SHD AF...
ffc00060-ffc00069 576K PTE   ro NX SHD AF...
ffc00069-ffc000801472K PTE   RW NX SHD AF...
ffc00080-ffc00200  24M PMD   RW NX SHD AF...
ffc00200-ffc04000 992M PMD   RW NX SHD AF...
ffc04000-ffc08000   1G PGD   RW NX SHD AF...

With sysctl kernel.kptr_restrict=2:
cat /sys/kernel/debug/kernel_page_tables
---[ Modules start ]---
---[ Modules end ]---
---[ vmalloc() Area ]---
-  64K PTE   RW NX SHD AF...
-   4K PTE   RW NX SHD AF...
-  64K PTE   RW NX SHD AF...
- 256K PTE   RW NX SHD AF...
-1536K PTE   ro x  SHD AF...
-   2M PMD   ro x  SHD AF...
-1280K PTE   ro x  SHD AF...
-1344K PTE   ro NX SHD AF...
- 832K PTE   RW NX SHD AF...
-  12K PTE   RW NX SHD AF...
-  12K PTE   RW NX SHD AF...
---[ vmalloc() End ]---
---[ Fixmap start ]---
-   2M PMD   ro NX SHD AF...
---[ Fixmap end ]---
---[ PCI I/O start ]---
---[ PCI I/O end ]---
---[ Linear Mapping ]---
- 512K PTE   RW NX SHD AF...
-1536K PTE   ro NX SHD AF...
-   4M PMD   ro NX SHD AF...
- 576K PTE   ro NX SHD AF...
-1472K PTE   RW NX SHD AF...
-  24M PMD   RW NX SHD AF...
- 992M PMD   RW NX SHD AF...
-   1G PGD   RW NX SHD AF...

Signed-off-by: Miles Chen 
---
 arch/arm64/mm/dump.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/mm/dump.c b/arch/arm64/mm/dump.c
index ca74a2a..e055ecf 100644
--- a/arch/arm64/mm/dump.c
+++ b/arch/arm64/mm/dump.c
@@ -253,8 +253,8 @@ static void note_page(struct pg_state *st, unsigned long 
addr, unsigned level,
if (st->current_prot) {
note_prot_uxn(st, addr);
note_prot_wx(st, addr);
-   pt_dump_seq_printf(st->seq, "0x%016lx-0x%016lx   ",
-  st->start_address, addr);
+   pt_dump_seq_printf(st->seq, "%pK-%pK   ",
+  (void *)st->start_address, (void *)addr);
 
delta = (addr - st->start_address) >> 10;
while (!(delta & 1023) && unit[1]) {
-- 
1.9.1

Re: [PATCH V2 1/3] arm64: dts: Add basic DT to support Spreadtrum's SP9860G

[Chunyan Zhang]

On 24 February 2017 at 23:07, Rob Herring  wrote:
> On Fri, Feb 24, 2017 at 1:57 AM, Chunyan Zhang
>  wrote:
>> On 四,  2月 23, 2017 at 06:00:20下午 -0600, Rob Herring wrote:
>>> On Tue, Feb 21, 2017 at 12:55 AM, Chunyan Zhang
>>>  wrote:
>>> > From: Orson Zhai 
>>> >
>>> > SC9860G is a 8 cores of A53 SoC with 4G LTE support SoC from Spreadtrum.
>>> >
>>> > According to regular hierarchy of sprd dts, whale2.dtsi contains SoC
>>> > peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff
>>> > and sp9860g dts is for the board level.
>>> >
>>> > Signed-off-by: Orson Zhai 
>>> > Signed-off-by: Chunyan Zhang 
>>> > ---
>>> >  arch/arm64/boot/dts/sprd/Makefile |   3 +-
>>> >  arch/arm64/boot/dts/sprd/sc9860.dtsi  | 531 
>>> > ++
>>> >  arch/arm64/boot/dts/sprd/sp9860g-1h10.dts |  56 
>>> >  arch/arm64/boot/dts/sprd/whale2.dtsi  |  70 
>>> >  4 files changed, 659 insertions(+), 1 deletion(-)
>>> >  create mode 100644 arch/arm64/boot/dts/sprd/sc9860.dtsi
>>> >  create mode 100644 arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
>>> >  create mode 100644 arch/arm64/boot/dts/sprd/whale2.dtsi
>>> >
>>> > diff --git a/arch/arm64/boot/dts/sprd/Makefile 
>>> > b/arch/arm64/boot/dts/sprd/Makefile
>>> > index b658c5e..f0535e6 100644
>>> > --- a/arch/arm64/boot/dts/sprd/Makefile
>>> > +++ b/arch/arm64/boot/dts/sprd/Makefile
>>> > @@ -1,4 +1,5 @@
>>> > -dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb
>>> > +dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \
>>> > +   sp9860g-1h10.dtb
>>> >
>>> >  always := $(dtb-y)
>>> >  subdir-y   := $(dts-dirs)
>>> > diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi 
>>> > b/arch/arm64/boot/dts/sprd/sc9860.dtsi
>>> > new file mode 100644
>>> > index 000..73deb4e
>>> > --- /dev/null
>>> > +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi
>>> > @@ -0,0 +1,531 @@
>>> > +/*
>>> > + * Spreadtrum SP9860 SoC DTS file
>>> > + *
>>> > + * Copyright (C) 2016, Spreadtrum Communications Inc.
>>> > + *
>>> > + * This file is licensed under a dual GPLv2 or X11 license.
>>>
>>> Please use SPDX-License-Identifier tag instead.
>>>
>>
>> Just to double check, if I use it like:
>>
>> SPDX-License-Identifier: (GPL-2.0 or X11)
>>
>> Is this what you mean?
>
> Yes. However, X11 is not actually correct (pretty much all dts files
> have it wrong). This is the X11 license[1] which is explicitly for the
> X Consortium and has a couple of extra clauses. While the MIT
> license[2] is the text that most dts files actually use (while also
> stating X11 license). It's obvious that everyone just copies and
> pastes the license and has not consulted their lawyers.

OK, got it.

>
>> Will this file still be licensed under the same terms it was, right?
>
> Consult your lawyer. :)
>
> [...]
>
>>> > +   ext_26m: ext-26m {
>>>
>>> This should be at the top-level. It is not part of the bus.
>>
>> This clock node is in 'soc' node, not under 'ap-apb'.  Since there're other
>> clocks on SC9860 which would have 'reg' property, we thought this fixed
>> clock would be better under 'soc' with other clocks.
>
> But the clock is part of the board, not the soc. Or to put it another
> way, it's not related to anything else, so it shouldn't be a child of
> anything.

Ok, I will move it to the top-level.

Thanks,
Chunyan

>
> Rob
>
> [1] https://spdx.org/licenses/X11.html
> [2] https://spdx.org/licenses/MIT.html

Re: [v2] Input: pwm-beeper: support customized freq for SND_BELL

[Heiko Schocher]

Hello David,

Am 28.02.2017 um 06:30 schrieb David Lechner:

On 02/27/2017 11:19 PM, Heiko Schocher wrote:

Hello David,

Am 27.02.2017 um 19:11 schrieb David Lechner:

On 02/20/2017 02:37 AM, Heiko Schocher wrote:

From: Guan Ben 

extend the pwm-beeper driver to support customized frequency
for SND_BELL from device tree.

Signed-off-by: Guan Ben 
Signed-off-by: Mark Jonas 
[h...@denx.de: adapted to 4.10-rc7]
Signed-off-by: Heiko Schocher 
---

Changes in v2:
- add comment from Rob Herring:
  rename property name "bell-frequency" to "beeper-hz"


Is there a separate patch for the devicetree bindings documentation?


No, it is in this patch ... In the meantime I got an
Acked-by from Rob Herring ...



What I should have said is that, in general, I think it is preferred to have 
the device tree
bindings as a separate patch from the code changes.


I can split this into 2 patches ...

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[PATCH] arm64: dump: hide kernel pointers

[Miles Chen]

Mask kernel pointers of /sys/kernel/debug/kernel_page_tables entry like
/proc/vmallocinfo does.

With sysctl kernel.kptr_restrict=0 or 1:
cat /sys/kernel/debug/kernel_page_tables
---[ Modules start ]---
---[ Modules end ]---
---[ vmalloc() Area ]---
ff800800-ff800801  64K PTE   RW NX SHD AF...
ff8008015000-ff8008016000   4K PTE   RW NX SHD AF...
ff800802-ff800803  64K PTE   RW NX SHD AF...
ff8008031000-ff8008071000 256K PTE   RW NX SHD AF...
ff800808-ff8008201536K PTE   ro x  SHD AF...
ff800820-ff800840   2M PMD   ro x  SHD AF...
ff800840-ff8008541280K PTE   ro x  SHD AF...
ff800854-ff8008691344K PTE   ro NX SHD AF...
ff800894-ff8008a1 832K PTE   RW NX SHD AF...
ff8008aca000-ff8008acd000  12K PTE   RW NX SHD AF...
ffbebffd8000-ffbebffdb000  12K PTE   RW NX SHD AF...
---[ vmalloc() End ]---
---[ Fixmap start ]---
ffbefe80-ffbefea0   2M PMD   ro NX SHD AF...
---[ Fixmap end ]---
---[ PCI I/O start ]---
---[ PCI I/O end ]---
---[ Linear Mapping ]---
ffc0-ffc8 512K PTE   RW NX SHD AF...
ffc8-ffc000201536K PTE   ro NX SHD AF...
ffc00020-ffc00060   4M PMD   ro NX SHD AF...
ffc00060-ffc00069 576K PTE   ro NX SHD AF...
ffc00069-ffc000801472K PTE   RW NX SHD AF...
ffc00080-ffc00200  24M PMD   RW NX SHD AF...
ffc00200-ffc04000 992M PMD   RW NX SHD AF...
ffc04000-ffc08000   1G PGD   RW NX SHD AF...

With sysctl kernel.kptr_restrict=2:
cat /sys/kernel/debug/kernel_page_tables
---[ Modules start ]---
---[ Modules end ]---
---[ vmalloc() Area ]---
-  64K PTE   RW NX SHD AF...
-   4K PTE   RW NX SHD AF...
-  64K PTE   RW NX SHD AF...
- 256K PTE   RW NX SHD AF...
-1536K PTE   ro x  SHD AF...
-   2M PMD   ro x  SHD AF...
-1280K PTE   ro x  SHD AF...
-1344K PTE   ro NX SHD AF...
- 832K PTE   RW NX SHD AF...
-  12K PTE   RW NX SHD AF...
-  12K PTE   RW NX SHD AF...
---[ vmalloc() End ]---
---[ Fixmap start ]---
-   2M PMD   ro NX SHD AF...
---[ Fixmap end ]---
---[ PCI I/O start ]---
---[ PCI I/O end ]---
---[ Linear Mapping ]---
- 512K PTE   RW NX SHD AF...
-1536K PTE   ro NX SHD AF...
-   4M PMD   ro NX SHD AF...
- 576K PTE   ro NX SHD AF...
-1472K PTE   RW NX SHD AF...
-  24M PMD   RW NX SHD AF...
- 992M PMD   RW NX SHD AF...
-   1G PGD   RW NX SHD AF...

Signed-off-by: Miles Chen 
---
 arch/arm64/mm/dump.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/mm/dump.c b/arch/arm64/mm/dump.c
index ca74a2a..e055ecf 100644
--- a/arch/arm64/mm/dump.c
+++ b/arch/arm64/mm/dump.c
@@ -253,8 +253,8 @@ static void note_page(struct pg_state *st, unsigned long 
addr, unsigned level,
if (st->current_prot) {
note_prot_uxn(st, addr);
note_prot_wx(st, addr);
-   pt_dump_seq_printf(st->seq, "0x%016lx-0x%016lx   ",
-  st->start_address, addr);
+   pt_dump_seq_printf(st->seq, "%pK-%pK   ",
+  (void *)st->start_address, (void *)addr);
 
delta = (addr - st->start_address) >> 10;
while (!(delta & 1023) && unit[1]) {
-- 
1.9.1

Re: [PATCH V2 1/3] arm64: dts: Add basic DT to support Spreadtrum's SP9860G

[Chunyan Zhang]

On 24 February 2017 at 23:07, Rob Herring  wrote:
> On Fri, Feb 24, 2017 at 1:57 AM, Chunyan Zhang
>  wrote:
>> On 四,  2月 23, 2017 at 06:00:20下午 -0600, Rob Herring wrote:
>>> On Tue, Feb 21, 2017 at 12:55 AM, Chunyan Zhang
>>>  wrote:
>>> > From: Orson Zhai 
>>> >
>>> > SC9860G is a 8 cores of A53 SoC with 4G LTE support SoC from Spreadtrum.
>>> >
>>> > According to regular hierarchy of sprd dts, whale2.dtsi contains SoC
>>> > peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff
>>> > and sp9860g dts is for the board level.
>>> >
>>> > Signed-off-by: Orson Zhai 
>>> > Signed-off-by: Chunyan Zhang 
>>> > ---
>>> >  arch/arm64/boot/dts/sprd/Makefile |   3 +-
>>> >  arch/arm64/boot/dts/sprd/sc9860.dtsi  | 531 
>>> > ++
>>> >  arch/arm64/boot/dts/sprd/sp9860g-1h10.dts |  56 
>>> >  arch/arm64/boot/dts/sprd/whale2.dtsi  |  70 
>>> >  4 files changed, 659 insertions(+), 1 deletion(-)
>>> >  create mode 100644 arch/arm64/boot/dts/sprd/sc9860.dtsi
>>> >  create mode 100644 arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
>>> >  create mode 100644 arch/arm64/boot/dts/sprd/whale2.dtsi
>>> >
>>> > diff --git a/arch/arm64/boot/dts/sprd/Makefile 
>>> > b/arch/arm64/boot/dts/sprd/Makefile
>>> > index b658c5e..f0535e6 100644
>>> > --- a/arch/arm64/boot/dts/sprd/Makefile
>>> > +++ b/arch/arm64/boot/dts/sprd/Makefile
>>> > @@ -1,4 +1,5 @@
>>> > -dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb
>>> > +dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \
>>> > +   sp9860g-1h10.dtb
>>> >
>>> >  always := $(dtb-y)
>>> >  subdir-y   := $(dts-dirs)
>>> > diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi 
>>> > b/arch/arm64/boot/dts/sprd/sc9860.dtsi
>>> > new file mode 100644
>>> > index 000..73deb4e
>>> > --- /dev/null
>>> > +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi
>>> > @@ -0,0 +1,531 @@
>>> > +/*
>>> > + * Spreadtrum SP9860 SoC DTS file
>>> > + *
>>> > + * Copyright (C) 2016, Spreadtrum Communications Inc.
>>> > + *
>>> > + * This file is licensed under a dual GPLv2 or X11 license.
>>>
>>> Please use SPDX-License-Identifier tag instead.
>>>
>>
>> Just to double check, if I use it like:
>>
>> SPDX-License-Identifier: (GPL-2.0 or X11)
>>
>> Is this what you mean?
>
> Yes. However, X11 is not actually correct (pretty much all dts files
> have it wrong). This is the X11 license[1] which is explicitly for the
> X Consortium and has a couple of extra clauses. While the MIT
> license[2] is the text that most dts files actually use (while also
> stating X11 license). It's obvious that everyone just copies and
> pastes the license and has not consulted their lawyers.

OK, got it.

>
>> Will this file still be licensed under the same terms it was, right?
>
> Consult your lawyer. :)
>
> [...]
>
>>> > +   ext_26m: ext-26m {
>>>
>>> This should be at the top-level. It is not part of the bus.
>>
>> This clock node is in 'soc' node, not under 'ap-apb'.  Since there're other
>> clocks on SC9860 which would have 'reg' property, we thought this fixed
>> clock would be better under 'soc' with other clocks.
>
> But the clock is part of the board, not the soc. Or to put it another
> way, it's not related to anything else, so it shouldn't be a child of
> anything.

Ok, I will move it to the top-level.

Thanks,
Chunyan

>
> Rob
>
> [1] https://spdx.org/licenses/X11.html
> [2] https://spdx.org/licenses/MIT.html

Re: [v2] Input: pwm-beeper: support customized freq for SND_BELL

[Heiko Schocher]

Hello David,

Am 28.02.2017 um 06:30 schrieb David Lechner:

On 02/27/2017 11:19 PM, Heiko Schocher wrote:

Hello David,

Am 27.02.2017 um 19:11 schrieb David Lechner:

On 02/20/2017 02:37 AM, Heiko Schocher wrote:

From: Guan Ben 

extend the pwm-beeper driver to support customized frequency
for SND_BELL from device tree.

Signed-off-by: Guan Ben 
Signed-off-by: Mark Jonas 
[h...@denx.de: adapted to 4.10-rc7]
Signed-off-by: Heiko Schocher 
---

Changes in v2:
- add comment from Rob Herring:
  rename property name "bell-frequency" to "beeper-hz"


Is there a separate patch for the devicetree bindings documentation?


No, it is in this patch ... In the meantime I got an
Acked-by from Rob Herring ...



What I should have said is that, in general, I think it is preferred to have 
the device tree
bindings as a separate patch from the code changes.


I can split this into 2 patches ...

bye,
Heiko
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

[PATCH V3] ARM: dts: exynos5440: support the phy-pcie node for pcie

[Jaehoon Chung]

Add pcie-phy node for using phy-exynos-pcie.

There are some modifications.
1. Remove the configuration space values in "ranges" property.
- The getting configuration space from ranges is old way.
- Instead, It can be got from "config"

2. Use the reg-names as "elbi", "config".
- Can know the purpose of use with reg-names.

Signed-off-by: Jaehoon Chung 
Reviewed-by: Pankaj Dubey 
---
Changelog on V3:
- Split from the patches relevant to pcie
- Modify the commit-message
- Keep the original comment in dt-file
- Send this patch after applying the other patches

Changelog on V2:
- Removes the child-node
- Fixes the typo
- Removes the unnecessary comments

 arch/arm/boot/dts/exynos5440.dtsi | 30 --
 1 file changed, 20 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5440.dtsi 
b/arch/arm/boot/dts/exynos5440.dtsi
index 2a2e570..a7165b5 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -290,11 +290,22 @@
clock-names = "usbhost";
};
 
+   pcie_phy0: pcie-phy@27 {
+   #phy-cells = <0>;
+   compatible = "samsung,exynos5440-pcie-phy";
+   reg = <0x27 0x1000>, <0x271000 0x40>;
+   };
+
+   pcie_phy1: pcie-phy@272000 {
+   #phy-cells = <0>;
+   compatible = "samsung,exynos5440-pcie-phy";
+   reg = <0x272000 0x1000>, <0x271040 0x40>;
+   };
+
pcie_0: pcie@29 {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-   reg = <0x29 0x1000
-   0x27 0x1000
-   0x271000 0x40>;
+   reg = <0x29 0x1000>, <0x4000 0x1000>;
+   reg-names = "elbi", "config";
interrupts = ,
 ,
 ;
@@ -303,8 +314,8 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
-   ranges = <0x0800 0 0x4000 0x4000 0 0x1000   /* 
configuration space */
- 0x8100 0 0  0x40001000 0 0x0001   /* 
downstream I/O */
+   phys = <_phy0>;
+   ranges = <0x8100 0 0  0x40001000 0 0x0001   /* 
downstream I/O */
  0x8200 0 0x40011000 0x40011000 0 0x1ffef000>; /* 
non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
@@ -315,9 +326,8 @@
 
pcie_1: pcie@2a {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-   reg = <0x2a 0x1000
-   0x272000 0x1000
-   0x271040 0x40>;
+   reg = <0x2a 0x1000>, <0x6000 0x1000>;
+   reg-names = "elbi", "config";
interrupts = ,
 ,
 ;
@@ -326,8 +336,8 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
-   ranges = <0x0800 0 0x6000 0x6000 0 0x1000   /* 
configuration space */
- 0x8100 0 0  0x60001000 0 0x0001   /* 
downstream I/O */
+   phys = <_phy1>;
+   ranges = <0x8100 0 0  0x60001000 0 0x0001   /* 
downstream I/O */
  0x8200 0 0x60011000 0x60011000 0 0x1ffef000>; /* 
non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
-- 
2.10.2

Re: [PATCH v6] staging: xgifb: correct the multiple line dereference

[Joe Perches]

On Tue, 2017-02-28 at 06:51 +0100, Greg Kroah-Hartman wrote:
> On Tue, Feb 28, 2017 at 10:35:30AM +0530, Arushi Singhal wrote:
> > Error reported by checkpatch.pl as "avoid multiple line dereference".
> > Addition of new variables to make the code more readable and also to
> > correct about mentioned error as by itroducing new variables line is
> > not exceeding 80 characters.
[]
> Remember, coding style cleanups are to be done to make the code easier
> to understand and follow.  Not to blindly follow a perl script that
> can not think.  Sometimes it is not right...

Yeah, what Greg said.

Also very long identifier names like RefreshRateTableIndex
and simple dereferences like
XGI330_RefIndex[RefreshRateTableIndex + (*i)].Ext_InfoFlag
make using 80 columns silly.

Just ignore 80 column limits when there are 20+ character
identifiers.  Ideally shorten the identifiers to something
less verbose and/or use temporaries where appropriate like
I showed in my reply to your suggested V5 patch.

[PATCH V3] ARM: dts: exynos5440: support the phy-pcie node for pcie

[Jaehoon Chung]

Add pcie-phy node for using phy-exynos-pcie.

There are some modifications.
1. Remove the configuration space values in "ranges" property.
- The getting configuration space from ranges is old way.
- Instead, It can be got from "config"

2. Use the reg-names as "elbi", "config".
- Can know the purpose of use with reg-names.

Signed-off-by: Jaehoon Chung 
Reviewed-by: Pankaj Dubey 
---
Changelog on V3:
- Split from the patches relevant to pcie
- Modify the commit-message
- Keep the original comment in dt-file
- Send this patch after applying the other patches

Changelog on V2:
- Removes the child-node
- Fixes the typo
- Removes the unnecessary comments

 arch/arm/boot/dts/exynos5440.dtsi | 30 --
 1 file changed, 20 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5440.dtsi 
b/arch/arm/boot/dts/exynos5440.dtsi
index 2a2e570..a7165b5 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -290,11 +290,22 @@
clock-names = "usbhost";
};
 
+   pcie_phy0: pcie-phy@27 {
+   #phy-cells = <0>;
+   compatible = "samsung,exynos5440-pcie-phy";
+   reg = <0x27 0x1000>, <0x271000 0x40>;
+   };
+
+   pcie_phy1: pcie-phy@272000 {
+   #phy-cells = <0>;
+   compatible = "samsung,exynos5440-pcie-phy";
+   reg = <0x272000 0x1000>, <0x271040 0x40>;
+   };
+
pcie_0: pcie@29 {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-   reg = <0x29 0x1000
-   0x27 0x1000
-   0x271000 0x40>;
+   reg = <0x29 0x1000>, <0x4000 0x1000>;
+   reg-names = "elbi", "config";
interrupts = ,
 ,
 ;
@@ -303,8 +314,8 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
-   ranges = <0x0800 0 0x4000 0x4000 0 0x1000   /* 
configuration space */
- 0x8100 0 0  0x40001000 0 0x0001   /* 
downstream I/O */
+   phys = <_phy0>;
+   ranges = <0x8100 0 0  0x40001000 0 0x0001   /* 
downstream I/O */
  0x8200 0 0x40011000 0x40011000 0 0x1ffef000>; /* 
non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
@@ -315,9 +326,8 @@
 
pcie_1: pcie@2a {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-   reg = <0x2a 0x1000
-   0x272000 0x1000
-   0x271040 0x40>;
+   reg = <0x2a 0x1000>, <0x6000 0x1000>;
+   reg-names = "elbi", "config";
interrupts = ,
 ,
 ;
@@ -326,8 +336,8 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
-   ranges = <0x0800 0 0x6000 0x6000 0 0x1000   /* 
configuration space */
- 0x8100 0 0  0x60001000 0 0x0001   /* 
downstream I/O */
+   phys = <_phy1>;
+   ranges = <0x8100 0 0  0x60001000 0 0x0001   /* 
downstream I/O */
  0x8200 0 0x60011000 0x60011000 0 0x1ffef000>; /* 
non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
-- 
2.10.2

Re: [PATCH v6] staging: xgifb: correct the multiple line dereference

[Joe Perches]

On Tue, 2017-02-28 at 06:51 +0100, Greg Kroah-Hartman wrote:
> On Tue, Feb 28, 2017 at 10:35:30AM +0530, Arushi Singhal wrote:
> > Error reported by checkpatch.pl as "avoid multiple line dereference".
> > Addition of new variables to make the code more readable and also to
> > correct about mentioned error as by itroducing new variables line is
> > not exceeding 80 characters.
[]
> Remember, coding style cleanups are to be done to make the code easier
> to understand and follow.  Not to blindly follow a perl script that
> can not think.  Sometimes it is not right...

Yeah, what Greg said.

Also very long identifier names like RefreshRateTableIndex
and simple dereferences like
XGI330_RefIndex[RefreshRateTableIndex + (*i)].Ext_InfoFlag
make using 80 columns silly.

Just ignore 80 column limits when there are 20+ character
identifiers.  Ideally shorten the identifiers to something
less verbose and/or use temporaries where appropriate like
I showed in my reply to your suggested V5 patch.

Re: [RFC 2/3] kcmp: Add KCMP_EPOLL_TFD mode to compare epoll target files

[Cyrill Gorcunov]

On Mon, Feb 27, 2017 at 02:43:47PM -0800, Andrei Vagin wrote:
...
> > +
> > +   if (filp1 && filp_epoll) {
> > +   filp_tgt = get_epoll_tfile_raw_ptr(filp_epoll, 
> > slot.tfd, slot.toff);
> > +   if (IS_ERR(filp_tgt))
> > +   ret = PTR_ERR(filp_tgt);
> > +   else
> > +   ret = kcmp_ptr(filp1, filp_tgt, KCMP_EPOLL_TFD);
> 
> I think KCMP_FILE has to be used here , because we compare files. We
> have to use the same function for all files to be able to sort them, don't we?

Yes. I already have v2 in my queue. Strictly speaking we can use separate
salt here but it will be waste of memory from userspace POV. I didn't send
v2 yet since I'm modifying criu still to test overall picture. Hopefully
will send today.

Re: [RFC 2/3] kcmp: Add KCMP_EPOLL_TFD mode to compare epoll target files

[Cyrill Gorcunov]

On Mon, Feb 27, 2017 at 02:43:47PM -0800, Andrei Vagin wrote:
...
> > +
> > +   if (filp1 && filp_epoll) {
> > +   filp_tgt = get_epoll_tfile_raw_ptr(filp_epoll, 
> > slot.tfd, slot.toff);
> > +   if (IS_ERR(filp_tgt))
> > +   ret = PTR_ERR(filp_tgt);
> > +   else
> > +   ret = kcmp_ptr(filp1, filp_tgt, KCMP_EPOLL_TFD);
> 
> I think KCMP_FILE has to be used here , because we compare files. We
> have to use the same function for all files to be able to sort them, don't we?

Yes. I already have v2 in my queue. Strictly speaking we can use separate
salt here but it will be waste of memory from userspace POV. I didn't send
v2 yet since I'm modifying criu still to test overall picture. Hopefully
will send today.

[PATCH v3 25/25] ARM: owl: smp: Reimplement SPS power-gating for CPU2 and CPU3

[Andreas Färber]

Bring up the two remaining CPUs.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber 
---
 v3: new
 
 arch/arm/mach-actions/platsmp.c | 67 +++--
 1 file changed, 65 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-actions/platsmp.c b/arch/arm/mach-actions/platsmp.c
index 9d3601e..45b4bc5 100644
--- a/arch/arm/mach-actions/platsmp.c
+++ b/arch/arm/mach-actions/platsmp.c
@@ -28,7 +28,15 @@
 
 #define OWL_CPUx_FLAG_BOOT 0x55aa
 
+#define OWL_SPS_PG_CTL 0x0
+
+#define OWL_SPS_PG_CTL_PWR_CPU2BIT(5)
+#define OWL_SPS_PG_CTL_PWR_CPU3BIT(6)
+#define OWL_SPS_PG_CTL_ACK_CPU2BIT(21)
+#define OWL_SPS_PG_CTL_ACK_CPU3BIT(22)
+
 static void __iomem *scu_base_addr;
+static void __iomem *sps_base_addr;
 static void __iomem *timer_base_addr;
 static int ncores;
 
@@ -42,6 +50,39 @@ static void write_pen_release(int val)
outer_clean_range(__pa(_release), __pa(_release + 1));
 }
 
+/* The generic PM domain driver is not available this early. */
+static int owl_sps_set_pg(u32 pwr_mask, u32 ack_mask, bool enable)
+{
+   u32 val;
+   bool ack;
+   int timeout;
+
+   val = readl(sps_base_addr + OWL_SPS_PG_CTL);
+   ack = val & ack_mask;
+   if (ack == enable)
+   return 0;
+
+   if (enable)
+   val |= pwr_mask;
+   else
+   val &= ~pwr_mask;
+
+   writel(val, sps_base_addr + OWL_SPS_PG_CTL);
+
+   for (timeout = 5000; timeout > 0; timeout -= 50) {
+   val = readl(sps_base_addr + OWL_SPS_PG_CTL);
+   if ((val & ack_mask) == (enable ? ack_mask : 0))
+   break;
+   udelay(50);
+   }
+   if (timeout <= 0)
+   return -ETIMEDOUT;
+
+   udelay(10);
+
+   return 0;
+}
+
 static void s500_smp_secondary_init(unsigned int cpu)
 {
/*
@@ -58,14 +99,24 @@ void owl_secondary_startup(void);
 
 static int s500_wakeup_secondary(unsigned int cpu)
 {
+   int ret;
+
if (cpu > 3)
return -EINVAL;
 
switch (cpu) {
case 2:
+   ret = owl_sps_set_pg(OWL_SPS_PG_CTL_PWR_CPU2,
+OWL_SPS_PG_CTL_ACK_CPU2, true);
+   if (ret)
+   return ret;
+   break;
case 3:
-   /* CPU2/3 are power-gated */
-   return -EINVAL;
+   ret = owl_sps_set_pg(OWL_SPS_PG_CTL_PWR_CPU3,
+OWL_SPS_PG_CTL_ACK_CPU3, true);
+   if (ret)
+   return ret;
+   break;
}
 
/* wait for CPUx to run to WFE instruction */
@@ -133,6 +184,18 @@ static void __init s500_smp_prepare_cpus(unsigned int 
max_cpus)
return;
}
 
+   node = of_find_compatible_node(NULL, NULL, "actions,s500-sps");
+   if (!node) {
+   pr_err("%s: missing sps\n", __func__);
+   return;
+   }
+
+   sps_base_addr = of_iomap(node, 0);
+   if (!sps_base_addr) {
+   pr_err("%s: could not map sps registers\n", __func__);
+   return;
+   }
+
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
if (!node) {
-- 
2.10.2

[PATCH v3 25/25] ARM: owl: smp: Reimplement SPS power-gating for CPU2 and CPU3

[Andreas Färber]

Bring up the two remaining CPUs.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber 
---
 v3: new
 
 arch/arm/mach-actions/platsmp.c | 67 +++--
 1 file changed, 65 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-actions/platsmp.c b/arch/arm/mach-actions/platsmp.c
index 9d3601e..45b4bc5 100644
--- a/arch/arm/mach-actions/platsmp.c
+++ b/arch/arm/mach-actions/platsmp.c
@@ -28,7 +28,15 @@
 
 #define OWL_CPUx_FLAG_BOOT 0x55aa
 
+#define OWL_SPS_PG_CTL 0x0
+
+#define OWL_SPS_PG_CTL_PWR_CPU2BIT(5)
+#define OWL_SPS_PG_CTL_PWR_CPU3BIT(6)
+#define OWL_SPS_PG_CTL_ACK_CPU2BIT(21)
+#define OWL_SPS_PG_CTL_ACK_CPU3BIT(22)
+
 static void __iomem *scu_base_addr;
+static void __iomem *sps_base_addr;
 static void __iomem *timer_base_addr;
 static int ncores;
 
@@ -42,6 +50,39 @@ static void write_pen_release(int val)
outer_clean_range(__pa(_release), __pa(_release + 1));
 }
 
+/* The generic PM domain driver is not available this early. */
+static int owl_sps_set_pg(u32 pwr_mask, u32 ack_mask, bool enable)
+{
+   u32 val;
+   bool ack;
+   int timeout;
+
+   val = readl(sps_base_addr + OWL_SPS_PG_CTL);
+   ack = val & ack_mask;
+   if (ack == enable)
+   return 0;
+
+   if (enable)
+   val |= pwr_mask;
+   else
+   val &= ~pwr_mask;
+
+   writel(val, sps_base_addr + OWL_SPS_PG_CTL);
+
+   for (timeout = 5000; timeout > 0; timeout -= 50) {
+   val = readl(sps_base_addr + OWL_SPS_PG_CTL);
+   if ((val & ack_mask) == (enable ? ack_mask : 0))
+   break;
+   udelay(50);
+   }
+   if (timeout <= 0)
+   return -ETIMEDOUT;
+
+   udelay(10);
+
+   return 0;
+}
+
 static void s500_smp_secondary_init(unsigned int cpu)
 {
/*
@@ -58,14 +99,24 @@ void owl_secondary_startup(void);
 
 static int s500_wakeup_secondary(unsigned int cpu)
 {
+   int ret;
+
if (cpu > 3)
return -EINVAL;
 
switch (cpu) {
case 2:
+   ret = owl_sps_set_pg(OWL_SPS_PG_CTL_PWR_CPU2,
+OWL_SPS_PG_CTL_ACK_CPU2, true);
+   if (ret)
+   return ret;
+   break;
case 3:
-   /* CPU2/3 are power-gated */
-   return -EINVAL;
+   ret = owl_sps_set_pg(OWL_SPS_PG_CTL_PWR_CPU3,
+OWL_SPS_PG_CTL_ACK_CPU3, true);
+   if (ret)
+   return ret;
+   break;
}
 
/* wait for CPUx to run to WFE instruction */
@@ -133,6 +184,18 @@ static void __init s500_smp_prepare_cpus(unsigned int 
max_cpus)
return;
}
 
+   node = of_find_compatible_node(NULL, NULL, "actions,s500-sps");
+   if (!node) {
+   pr_err("%s: missing sps\n", __func__);
+   return;
+   }
+
+   sps_base_addr = of_iomap(node, 0);
+   if (!sps_base_addr) {
+   pr_err("%s: could not map sps registers\n", __func__);
+   return;
+   }
+
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
if (!node) {
-- 
2.10.2

[PATCH v3 08/25] dt-bindings: serial: Document Actions Semi Owl UARTs

[Andreas Färber]

This UART is found on S500 and S900 SoCs.

Acked-by: Rob Herring 
Signed-off-by: Andreas Färber 
---
 v2 -> v3: unchanged
 
 v1 -> v2:
 * Adopted "actions" vendor prefix
 
 .../devicetree/bindings/serial/actions,owl-uart.txt  | 16 
 1 file changed, 16 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/serial/actions,owl-uart.txt

diff --git a/Documentation/devicetree/bindings/serial/actions,owl-uart.txt 
b/Documentation/devicetree/bindings/serial/actions,owl-uart.txt
new file mode 100644
index 000..aa873ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/actions,owl-uart.txt
@@ -0,0 +1,16 @@
+Actions Semi Owl UART
+
+Required properties:
+- compatible :  "actions,s500-uart", "actions,owl-uart" for S500
+"actions,s900-uart", "actions,owl-uart" for S900
+- reg:  Offset and length of the register set for the device.
+- interrupts :  Should contain UART interrupt.
+
+
+Example:
+
+   uart3: serial@b0126000 {
+   compatible = "actions,s500-uart", "actions,owl-uart";
+   reg = <0xb0126000 0x1000>;
+   interrupts = ;
+   };
-- 
2.10.2

[PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

[Andreas Färber]

Allow to bring up CPU1.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber 
---
 v3: new
 
 arch/arm/mach-actions/Makefile  |   1 +
 arch/arm/mach-actions/headsmp.S |  68 
 arch/arm/mach-actions/platsmp.c | 166 
 3 files changed, 235 insertions(+)
 create mode 100644 arch/arm/mach-actions/headsmp.S
 create mode 100644 arch/arm/mach-actions/platsmp.c

diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile
index 524c381..2fb61f8 100644
--- a/arch/arm/mach-actions/Makefile
+++ b/arch/arm/mach-actions/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_ACTIONS) += owl.o
+obj-${CONFIG_ARCH_ACTIONS} += platsmp.o headsmp.o
diff --git a/arch/arm/mach-actions/headsmp.S b/arch/arm/mach-actions/headsmp.S
new file mode 100644
index 000..dc4832f
--- /dev/null
+++ b/arch/arm/mach-actions/headsmp.S
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2012 Actions Semi Inc.
+ * Author: Actions Semi, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+
+ENTRY(owl_v7_invalidate_l1)
+   mov r0, #0
+   mcr p15, 0, r0, c7, c5, 0   @ invalidate I cache
+   mcr p15, 2, r0, c0, c0, 0
+   mrc p15, 1, r0, c0, c0, 0
+
+   ldr r1, =0x7fff
+   and r2, r1, r0, lsr #13
+
+   ldr r1, =0x3ff
+
+   and r3, r1, r0, lsr #3  @ NumWays - 1
+   add r2, r2, #1  @ NumSets
+
+   and r0, r0, #0x7
+   add r0, r0, #4  @ SetShift
+
+   clz r1, r3  @ WayShift
+   add r4, r3, #1  @ NumWays
+1: sub r2, r2, #1  @ NumSets--
+   mov r3, r4  @ Temp = NumWays
+2: subsr3, r3, #1  @ Temp--
+   mov r5, r3, lsl r1
+   mov r6, r2, lsl r0
+   orr r5, r5, r6  @ Reg = (Temp< 3)
+   return -EINVAL;
+
+   switch (cpu) {
+   case 2:
+   case 3:
+   /* CPU2/3 are power-gated */
+   return -EINVAL;
+   }
+
+   /* wait for CPUx to run to WFE instruction */
+   udelay(200);
+
+   writel(virt_to_phys(owl_secondary_startup),
+  timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
+   writel(OWL_CPUx_FLAG_BOOT,
+  timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
+
+   dsb_sev();
+   mb();
+
+   return 0;
+}
+
+static int 

[PATCH v3 08/25] dt-bindings: serial: Document Actions Semi Owl UARTs

[Andreas Färber]

This UART is found on S500 and S900 SoCs.

Acked-by: Rob Herring 
Signed-off-by: Andreas Färber 
---
 v2 -> v3: unchanged
 
 v1 -> v2:
 * Adopted "actions" vendor prefix
 
 .../devicetree/bindings/serial/actions,owl-uart.txt  | 16 
 1 file changed, 16 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/serial/actions,owl-uart.txt

diff --git a/Documentation/devicetree/bindings/serial/actions,owl-uart.txt 
b/Documentation/devicetree/bindings/serial/actions,owl-uart.txt
new file mode 100644
index 000..aa873ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/actions,owl-uart.txt
@@ -0,0 +1,16 @@
+Actions Semi Owl UART
+
+Required properties:
+- compatible :  "actions,s500-uart", "actions,owl-uart" for S500
+"actions,s900-uart", "actions,owl-uart" for S900
+- reg:  Offset and length of the register set for the device.
+- interrupts :  Should contain UART interrupt.
+
+
+Example:
+
+   uart3: serial@b0126000 {
+   compatible = "actions,s500-uart", "actions,owl-uart";
+   reg = <0xb0126000 0x1000>;
+   interrupts = ;
+   };
-- 
2.10.2

[PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

[Andreas Färber]

Allow to bring up CPU1.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber 
---
 v3: new
 
 arch/arm/mach-actions/Makefile  |   1 +
 arch/arm/mach-actions/headsmp.S |  68 
 arch/arm/mach-actions/platsmp.c | 166 
 3 files changed, 235 insertions(+)
 create mode 100644 arch/arm/mach-actions/headsmp.S
 create mode 100644 arch/arm/mach-actions/platsmp.c

diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile
index 524c381..2fb61f8 100644
--- a/arch/arm/mach-actions/Makefile
+++ b/arch/arm/mach-actions/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_ACTIONS) += owl.o
+obj-${CONFIG_ARCH_ACTIONS} += platsmp.o headsmp.o
diff --git a/arch/arm/mach-actions/headsmp.S b/arch/arm/mach-actions/headsmp.S
new file mode 100644
index 000..dc4832f
--- /dev/null
+++ b/arch/arm/mach-actions/headsmp.S
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2012 Actions Semi Inc.
+ * Author: Actions Semi, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+
+ENTRY(owl_v7_invalidate_l1)
+   mov r0, #0
+   mcr p15, 0, r0, c7, c5, 0   @ invalidate I cache
+   mcr p15, 2, r0, c0, c0, 0
+   mrc p15, 1, r0, c0, c0, 0
+
+   ldr r1, =0x7fff
+   and r2, r1, r0, lsr #13
+
+   ldr r1, =0x3ff
+
+   and r3, r1, r0, lsr #3  @ NumWays - 1
+   add r2, r2, #1  @ NumSets
+
+   and r0, r0, #0x7
+   add r0, r0, #4  @ SetShift
+
+   clz r1, r3  @ WayShift
+   add r4, r3, #1  @ NumWays
+1: sub r2, r2, #1  @ NumSets--
+   mov r3, r4  @ Temp = NumWays
+2: subsr3, r3, #1  @ Temp--
+   mov r5, r3, lsl r1
+   mov r6, r2, lsl r0
+   orr r5, r5, r6  @ Reg = (Temp<
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define OWL_CPU1_ADDR  0x50
+#define OWL_CPU1_FLAG  0x5c
+
+#define OWL_CPUx_FLAG_BOOT 0x55aa
+
+static void __iomem *scu_base_addr;
+static void __iomem *timer_base_addr;
+static int ncores;
+
+static DEFINE_SPINLOCK(boot_lock);
+
+static void write_pen_release(int val)
+{
+   pen_release = val;
+   smp_wmb();
+   __cpuc_flush_dcache_area((void *)_release, sizeof(pen_release));
+   outer_clean_range(__pa(_release), __pa(_release + 1));
+}
+
+static void s500_smp_secondary_init(unsigned int cpu)
+{
+   /*
+* let the primary processor know we're out of the
+* pen, then head off into the C entry point
+*/
+   write_pen_release(-1);
+
+   spin_lock(_lock);
+   spin_unlock(_lock);
+}
+
+void owl_secondary_startup(void);
+
+static int s500_wakeup_secondary(unsigned int cpu)
+{
+   if (cpu > 3)
+   return -EINVAL;
+
+   switch (cpu) {
+   case 2:
+   case 3:
+   /* CPU2/3 are power-gated */
+   return -EINVAL;
+   }
+
+   /* wait for CPUx to run to WFE instruction */
+   udelay(200);
+
+   writel(virt_to_phys(owl_secondary_startup),
+  timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
+   writel(OWL_CPUx_FLAG_BOOT,
+  timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
+
+   dsb_sev();
+   mb();
+
+   return 0;
+}
+
+static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+   unsigned long timeout;
+   int ret;
+
+   ret = s500_wakeup_secondary(cpu);
+   if (ret)
+   return ret;
+
+   udelay(10);
+
+   spin_lock(_lock);
+
+   /*
+* The secondary processor is waiting to be released from
+* the holding pen - release it, then wait for it to flag
+* that it has been released by resetting pen_release.
+*/
+   write_pen_release(cpu_logical_map(cpu));
+   smp_send_reschedule(cpu);
+
+   timeout = jiffies + (1 * HZ);
+   while (time_before(jiffies, timeout)) {
+   if (pen_release == -1)
+   break;
+   }
+
+   writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
+   writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
+
+   spin_unlock(_lock);
+
+   return pen_release != -1 ? -ENOSYS : 0;
+}
+
+static void __init s500_smp_prepare_cpus(unsigned int max_cpus)
+{
+   struct device_node *node;
+
+   node = of_find_compatible_node(NULL, NULL, "actions,s500-timer");
+   if (!node) {
+   pr_err("%s: missing timer\n", __func__);
+   return;
+   }
+
+   timer_base_addr = of_iomap(node, 0);
+   if (!timer_base_addr) {
+   pr_err("%s: could not map timer registers\n", __func__);
+   return;
+   }
+
+   if 

[PATCH v3 05/25] clocksource: owl: Add S900 support

[Andreas Färber]

The Actions Semi S900 SoC provides four 32-bit timers, TIMER0/1/2/3,
but no 2Hz timers.

Deal with the S500 having less timers.

An S900 datasheet can be found in 96Boards documentation:
https://github.com/96boards/documentation/blob/master/ConsumerEdition/Bubblegum-96/HardwareDocs/SoC_bubblegum96.pdf

Signed-off-by: Andreas Färber 
---
 v3: new
 
 drivers/clocksource/owl-timer.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/owl-timer.c b/drivers/clocksource/owl-timer.c
index 1b1e26d..babbfd5 100644
--- a/drivers/clocksource/owl-timer.c
+++ b/drivers/clocksource/owl-timer.c
@@ -31,7 +31,7 @@
 #define OWL_Tx_CTL_INTEN   BIT(1)
 #define OWL_Tx_CTL_EN  BIT(2)
 
-#define OWL_MAX_Tx 2
+#define OWL_MAX_Tx 4
 
 struct owl_timer_info {
int timer_offset[OWL_MAX_Tx];
@@ -43,7 +43,8 @@ static void __iomem *owl_timer_base;
 
 static inline void __iomem *owl_timer_get_base(unsigned timer_nr)
 {
-   if (timer_nr >= OWL_MAX_Tx)
+   if (timer_nr >= OWL_MAX_Tx ||
+   owl_timer_info->timer_offset[timer_nr] == -1)
return NULL;
 
return owl_timer_base + owl_timer_info->timer_offset[timer_nr];
@@ -126,10 +127,20 @@ static irqreturn_t owl_timer1_interrupt(int irq, void 
*dev_id)
 static const struct owl_timer_info s500_timer_info = {
.timer_offset[0] = 0x08,
.timer_offset[1] = 0x14,
+   .timer_offset[2] = -1,
+   .timer_offset[3] = -1,
+};
+
+static const struct owl_timer_info s900_timer_info = {
+   .timer_offset[0] = 0x08,
+   .timer_offset[1] = 0x14,
+   .timer_offset[2] = 0x30,
+   .timer_offset[3] = 0x3c,
 };
 
 static const struct of_device_id owl_timer_of_matches[] = {
{ .compatible = "actions,s500-timer", .data = _timer_info },
+   { .compatible = "actions,s900-timer", .data = _timer_info },
{ }
 };
 
@@ -191,3 +202,4 @@ static int __init owl_timer_init(struct device_node *node)
return 0;
 }
 CLOCKSOURCE_OF_DECLARE(owl_s500, "actions,s500-timer", owl_timer_init);
+CLOCKSOURCE_OF_DECLARE(owl_s900, "actions,s900-timer", owl_timer_init);
-- 
2.10.2

[PATCH v3 05/25] clocksource: owl: Add S900 support

[Andreas Färber]

The Actions Semi S900 SoC provides four 32-bit timers, TIMER0/1/2/3,
but no 2Hz timers.

Deal with the S500 having less timers.

An S900 datasheet can be found in 96Boards documentation:
https://github.com/96boards/documentation/blob/master/ConsumerEdition/Bubblegum-96/HardwareDocs/SoC_bubblegum96.pdf

Signed-off-by: Andreas Färber 
---
 v3: new
 
 drivers/clocksource/owl-timer.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/owl-timer.c b/drivers/clocksource/owl-timer.c
index 1b1e26d..babbfd5 100644
--- a/drivers/clocksource/owl-timer.c
+++ b/drivers/clocksource/owl-timer.c
@@ -31,7 +31,7 @@
 #define OWL_Tx_CTL_INTEN   BIT(1)
 #define OWL_Tx_CTL_EN  BIT(2)
 
-#define OWL_MAX_Tx 2
+#define OWL_MAX_Tx 4
 
 struct owl_timer_info {
int timer_offset[OWL_MAX_Tx];
@@ -43,7 +43,8 @@ static void __iomem *owl_timer_base;
 
 static inline void __iomem *owl_timer_get_base(unsigned timer_nr)
 {
-   if (timer_nr >= OWL_MAX_Tx)
+   if (timer_nr >= OWL_MAX_Tx ||
+   owl_timer_info->timer_offset[timer_nr] == -1)
return NULL;
 
return owl_timer_base + owl_timer_info->timer_offset[timer_nr];
@@ -126,10 +127,20 @@ static irqreturn_t owl_timer1_interrupt(int irq, void 
*dev_id)
 static const struct owl_timer_info s500_timer_info = {
.timer_offset[0] = 0x08,
.timer_offset[1] = 0x14,
+   .timer_offset[2] = -1,
+   .timer_offset[3] = -1,
+};
+
+static const struct owl_timer_info s900_timer_info = {
+   .timer_offset[0] = 0x08,
+   .timer_offset[1] = 0x14,
+   .timer_offset[2] = 0x30,
+   .timer_offset[3] = 0x3c,
 };
 
 static const struct of_device_id owl_timer_of_matches[] = {
{ .compatible = "actions,s500-timer", .data = _timer_info },
+   { .compatible = "actions,s900-timer", .data = _timer_info },
{ }
 };
 
@@ -191,3 +202,4 @@ static int __init owl_timer_init(struct device_node *node)
return 0;
 }
 CLOCKSOURCE_OF_DECLARE(owl_s500, "actions,s500-timer", owl_timer_init);
+CLOCKSOURCE_OF_DECLARE(owl_s900, "actions,s900-timer", owl_timer_init);
-- 
2.10.2

[PATCH v3 15/25] MAINTAINERS: Add Actions Semi Owl section

[Andreas Färber]

Signed-off-by: Andreas Färber 
---
 v2 -> v3: unchanged
 
 v2: new
 
 MAINTAINERS | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b9af886..467121e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1026,6 +1026,16 @@ S:   Maintained
 F: drivers/amba/
 F: include/linux/amba/bus.h
 
+ARM/ACTIONS SEMI ARCHITECTURE
+M: Andreas Färber 
+L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+N: owl
+F: arch/arm/mach-actions/
+F: arch/arm/boot/dts/s500*
+F: arch/arm64/boot/dts/actions/
+F: Documentation/devicetree/bindings/arm/actions.txt
+
 ARM/ADS SPHERE MACHINE SUPPORT
 M: Lennert Buytenhek 
 L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
-- 
2.10.2

[PATCH v3 15/25] MAINTAINERS: Add Actions Semi Owl section

[Andreas Färber]

Signed-off-by: Andreas Färber 
---
 v2 -> v3: unchanged
 
 v2: new
 
 MAINTAINERS | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b9af886..467121e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1026,6 +1026,16 @@ S:   Maintained
 F: drivers/amba/
 F: include/linux/amba/bus.h
 
+ARM/ACTIONS SEMI ARCHITECTURE
+M: Andreas Färber 
+L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+N: owl
+F: arch/arm/mach-actions/
+F: arch/arm/boot/dts/s500*
+F: arch/arm64/boot/dts/actions/
+F: Documentation/devicetree/bindings/arm/actions.txt
+
 ARM/ADS SPHERE MACHINE SUPPORT
 M: Lennert Buytenhek 
 L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
-- 
2.10.2

[PATCH v3 12/25] dt-bindings: Add vendor prefix for uCRobotics

[Andreas Färber]

Cc: 96boa...@ucrobotics.com
Acked-by: Rob Herring 
Signed-off-by: Andreas Färber 
---
 v1 -> v2 -> v3: unchanged
 
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt 
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 2f294c8..44232c2 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -320,6 +320,7 @@ tronfy  Tronfy
 tronsmart  Tronsmart
 truly  Truly Semiconductors Limited
 tyan   Tyan Computer Corporation
+ucrobotics uCRobotics
 udoo   Udoo
 uniwestUnited Western Technologies Corp (UniWest)
 upisemiuPI Semiconductor Corp.
-- 
2.10.2

[PATCH v3 12/25] dt-bindings: Add vendor prefix for uCRobotics

[Andreas Färber]

Cc: 96boa...@ucrobotics.com
Acked-by: Rob Herring 
Signed-off-by: Andreas Färber 
---
 v1 -> v2 -> v3: unchanged
 
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt 
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 2f294c8..44232c2 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -320,6 +320,7 @@ tronfy  Tronfy
 tronsmart  Tronsmart
 truly  Truly Semiconductors Limited
 tyan   Tyan Computer Corporation
+ucrobotics uCRobotics
 udoo   Udoo
 uniwestUnited Western Technologies Corp (UniWest)
 upisemiuPI Semiconductor Corp.
-- 
2.10.2

[PATCH v3 06/25] ARM: Prepare Actions Semi S500

[Andreas Färber]

Add ARCH_ACTIONS and mach-actions/owl.c for "actions,s500".

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Selected AMBA, global timer, TWD drivers
 * Fixed copy in machine definition (Alberto)
 
 v1 -> v2:
 * Renamed ARCH_OWL to ARCH_ACTION (Arnd)
 * Renamed mach-owl to mach-actions, leaving owl.c
 * Adopted "actions" vendor prefix
 * Selected new clocksource driver
 
 arch/arm/Kconfig   |  2 ++
 arch/arm/Makefile  |  1 +
 arch/arm/mach-actions/Kconfig  | 15 +++
 arch/arm/mach-actions/Makefile |  1 +
 arch/arm/mach-actions/owl.c| 28 
 5 files changed, 47 insertions(+)
 create mode 100644 arch/arm/mach-actions/Kconfig
 create mode 100644 arch/arm/mach-actions/Makefile
 create mode 100644 arch/arm/mach-actions/owl.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0d4e71b..94fa3925 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -720,6 +720,8 @@ config ARCH_VIRT
 #
 source "arch/arm/mach-mvebu/Kconfig"
 
+source "arch/arm/mach-actions/Kconfig"
+
 source "arch/arm/mach-alpine/Kconfig"
 
 source "arch/arm/mach-artpec/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ab30cc6..d2ccf72 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -151,6 +151,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
+machine-$(CONFIG_ARCH_ACTIONS) += actions
 machine-$(CONFIG_ARCH_ALPINE)  += alpine
 machine-$(CONFIG_ARCH_ARTPEC)  += artpec
 machine-$(CONFIG_ARCH_AT91)+= at91
diff --git a/arch/arm/mach-actions/Kconfig b/arch/arm/mach-actions/Kconfig
new file mode 100644
index 000..717adc1
--- /dev/null
+++ b/arch/arm/mach-actions/Kconfig
@@ -0,0 +1,15 @@
+menuconfig ARCH_ACTIONS
+   bool "Actions Semi SoCs"
+   depends on ARCH_MULTI_V7
+   select ARM_AMBA
+   select ARM_GIC
+   select ARM_GLOBAL_TIMER
+   select CACHE_L2X0
+   select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
+   select COMMON_CLK
+   select GENERIC_IRQ_CHIP
+   select HAVE_ARM_SCU if SMP
+   select HAVE_ARM_TWD if SMP
+   select OWL_TIMER
+   help
+ This enables support for the Actions Semiconductor S500 SoC family.
diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile
new file mode 100644
index 000..524c381
--- /dev/null
+++ b/arch/arm/mach-actions/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_ACTIONS) += owl.o
diff --git a/arch/arm/mach-actions/owl.c b/arch/arm/mach-actions/owl.c
new file mode 100644
index 000..4ac4a86
--- /dev/null
+++ b/arch/arm/mach-actions/owl.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2017 Andreas Färber
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+
+static const char * const owl_dt_compat[] = {
+   "actions,s500",
+   NULL
+};
+
+DT_MACHINE_START(OWL, "Actions Semi Owl platform")
+   .dt_compat  = owl_dt_compat,
+   .l2c_aux_val= 0,
+   .l2c_aux_mask   = ~0,
+MACHINE_END
-- 
2.10.2

[PATCH v3 06/25] ARM: Prepare Actions Semi S500

[Andreas Färber]

Add ARCH_ACTIONS and mach-actions/owl.c for "actions,s500".

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Selected AMBA, global timer, TWD drivers
 * Fixed copy in machine definition (Alberto)
 
 v1 -> v2:
 * Renamed ARCH_OWL to ARCH_ACTION (Arnd)
 * Renamed mach-owl to mach-actions, leaving owl.c
 * Adopted "actions" vendor prefix
 * Selected new clocksource driver
 
 arch/arm/Kconfig   |  2 ++
 arch/arm/Makefile  |  1 +
 arch/arm/mach-actions/Kconfig  | 15 +++
 arch/arm/mach-actions/Makefile |  1 +
 arch/arm/mach-actions/owl.c| 28 
 5 files changed, 47 insertions(+)
 create mode 100644 arch/arm/mach-actions/Kconfig
 create mode 100644 arch/arm/mach-actions/Makefile
 create mode 100644 arch/arm/mach-actions/owl.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0d4e71b..94fa3925 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -720,6 +720,8 @@ config ARCH_VIRT
 #
 source "arch/arm/mach-mvebu/Kconfig"
 
+source "arch/arm/mach-actions/Kconfig"
+
 source "arch/arm/mach-alpine/Kconfig"
 
 source "arch/arm/mach-artpec/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ab30cc6..d2ccf72 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -151,6 +151,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
+machine-$(CONFIG_ARCH_ACTIONS) += actions
 machine-$(CONFIG_ARCH_ALPINE)  += alpine
 machine-$(CONFIG_ARCH_ARTPEC)  += artpec
 machine-$(CONFIG_ARCH_AT91)+= at91
diff --git a/arch/arm/mach-actions/Kconfig b/arch/arm/mach-actions/Kconfig
new file mode 100644
index 000..717adc1
--- /dev/null
+++ b/arch/arm/mach-actions/Kconfig
@@ -0,0 +1,15 @@
+menuconfig ARCH_ACTIONS
+   bool "Actions Semi SoCs"
+   depends on ARCH_MULTI_V7
+   select ARM_AMBA
+   select ARM_GIC
+   select ARM_GLOBAL_TIMER
+   select CACHE_L2X0
+   select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
+   select COMMON_CLK
+   select GENERIC_IRQ_CHIP
+   select HAVE_ARM_SCU if SMP
+   select HAVE_ARM_TWD if SMP
+   select OWL_TIMER
+   help
+ This enables support for the Actions Semiconductor S500 SoC family.
diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile
new file mode 100644
index 000..524c381
--- /dev/null
+++ b/arch/arm/mach-actions/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_ACTIONS) += owl.o
diff --git a/arch/arm/mach-actions/owl.c b/arch/arm/mach-actions/owl.c
new file mode 100644
index 000..4ac4a86
--- /dev/null
+++ b/arch/arm/mach-actions/owl.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2017 Andreas Färber
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include 
+#include 
+
+static const char * const owl_dt_compat[] = {
+   "actions,s500",
+   NULL
+};
+
+DT_MACHINE_START(OWL, "Actions Semi Owl platform")
+   .dt_compat  = owl_dt_compat,
+   .l2c_aux_val= 0,
+   .l2c_aux_mask   = ~0,
+MACHINE_END
-- 
2.10.2

[PATCH v3 09/25] tty: serial: Add Actions Semi Owl UART earlycon

[Andreas Färber]

This implements an earlycon for Actions Semi S500/S900 SoCs.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Adopted BIT() macro
 
 v1 -> v2:
 * Extended Kconfig help to mention earlycon (Arnd)
 * Spelled out Actions Semiconductor in Kconfig help
 * Adopted "actions" vendor prefix
 
 drivers/tty/serial/Kconfig|  19 ++
 drivers/tty/serial/Makefile   |   1 +
 drivers/tty/serial/owl-uart.c | 135 ++
 3 files changed, 155 insertions(+)
 create mode 100644 drivers/tty/serial/owl-uart.c

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 6117ac8..e145822 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1677,6 +1677,25 @@ config SERIAL_MVEBU_CONSOLE
  and warnings and which allows logins in single user mode)
  Otherwise, say 'N'.
 
+config SERIAL_OWL
+   bool "Actions Semi Owl serial port support"
+   depends on ARCH_ACTIONS || COMPILE_TEST
+   select SERIAL_CORE
+   help
+ This driver is for Actions Semiconductor S500/S900 SoC's UART.
+ Say 'Y' here if you wish to use the on-board serial port.
+ Otherwise, say 'N'.
+
+config SERIAL_OWL_CONSOLE
+   bool "Console on Actions Semi Owl serial port"
+   depends on SERIAL_OWL=y
+   select SERIAL_CORE_CONSOLE
+   select SERIAL_EARLYCON
+   default y
+   help
+ Say 'Y' here if you wish to use Actions Semiconductor S500/S900 UART
+ as the system console. Only earlycon is implemented currently.
+
 endmenu
 
 config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 2d6288b..91f3571 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_SERIAL_STM32)+= stm32-usart.o
 obj-$(CONFIG_SERIAL_MVEBU_UART)+= mvebu-uart.o
 obj-$(CONFIG_SERIAL_PIC32) += pic32_uart.o
 obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o
+obj-$(CONFIG_SERIAL_OWL)   += owl-uart.o
 
 # GPIOLIB helpers for modem control lines
 obj-$(CONFIG_SERIAL_MCTRL_GPIO)+= serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/owl-uart.c b/drivers/tty/serial/owl-uart.c
new file mode 100644
index 000..1b80087
--- /dev/null
+++ b/drivers/tty/serial/owl-uart.c
@@ -0,0 +1,135 @@
+/*
+ * Actions Semi Owl family serial console
+ *
+ * Copyright 2013 Actions Semi Inc.
+ * Author: Actions Semi, Inc.
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define OWL_UART_CTL   0x000
+#define OWL_UART_TXDAT 0x008
+#define OWL_UART_STAT  0x00c
+
+#define OWL_UART_CTL_TRFS_TX   BIT(14)
+#define OWL_UART_CTL_ENBIT(15)
+#define OWL_UART_CTL_RXIE  BIT(18)
+#define OWL_UART_CTL_TXIE  BIT(19)
+
+#define OWL_UART_STAT_RIP  BIT(0)
+#define OWL_UART_STAT_TIP  BIT(1)
+#define OWL_UART_STAT_TFFU BIT(6)
+#define OWL_UART_STAT_TRFL_MASK(0x1f << 11)
+#define OWL_UART_STAT_UTBB BIT(17)
+
+static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned 
int off)
+{
+   writel(val, port->membase + off);
+}
+
+static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
+{
+   return readl(port->membase + off);
+}
+
+#ifdef CONFIG_SERIAL_OWL_CONSOLE
+
+static void owl_console_putchar(struct uart_port *port, int ch)
+{
+   if (!port->membase)
+   return;
+
+   while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
+   cpu_relax();
+
+   owl_uart_write(port, ch, OWL_UART_TXDAT);
+}
+
+static void owl_uart_port_write(struct uart_port *port, const char *s,
+   u_int count)
+{
+   u32 old_ctl, val;
+   unsigned long flags;
+   int locked;
+
+   local_irq_save(flags);
+
+   if (port->sysrq)
+   locked = 0;
+   else if (oops_in_progress)
+   locked = spin_trylock(>lock);
+   else {
+   spin_lock(>lock);
+   locked = 1;
+   }
+
+   old_ctl = owl_uart_read(port, OWL_UART_CTL);
+   val = old_ctl | OWL_UART_CTL_TRFS_TX;
+   /* disable IRQ 

[PATCH v3 09/25] tty: serial: Add Actions Semi Owl UART earlycon

[Andreas Färber]

This implements an earlycon for Actions Semi S500/S900 SoCs.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Adopted BIT() macro
 
 v1 -> v2:
 * Extended Kconfig help to mention earlycon (Arnd)
 * Spelled out Actions Semiconductor in Kconfig help
 * Adopted "actions" vendor prefix
 
 drivers/tty/serial/Kconfig|  19 ++
 drivers/tty/serial/Makefile   |   1 +
 drivers/tty/serial/owl-uart.c | 135 ++
 3 files changed, 155 insertions(+)
 create mode 100644 drivers/tty/serial/owl-uart.c

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 6117ac8..e145822 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1677,6 +1677,25 @@ config SERIAL_MVEBU_CONSOLE
  and warnings and which allows logins in single user mode)
  Otherwise, say 'N'.
 
+config SERIAL_OWL
+   bool "Actions Semi Owl serial port support"
+   depends on ARCH_ACTIONS || COMPILE_TEST
+   select SERIAL_CORE
+   help
+ This driver is for Actions Semiconductor S500/S900 SoC's UART.
+ Say 'Y' here if you wish to use the on-board serial port.
+ Otherwise, say 'N'.
+
+config SERIAL_OWL_CONSOLE
+   bool "Console on Actions Semi Owl serial port"
+   depends on SERIAL_OWL=y
+   select SERIAL_CORE_CONSOLE
+   select SERIAL_EARLYCON
+   default y
+   help
+ Say 'Y' here if you wish to use Actions Semiconductor S500/S900 UART
+ as the system console. Only earlycon is implemented currently.
+
 endmenu
 
 config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 2d6288b..91f3571 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_SERIAL_STM32)+= stm32-usart.o
 obj-$(CONFIG_SERIAL_MVEBU_UART)+= mvebu-uart.o
 obj-$(CONFIG_SERIAL_PIC32) += pic32_uart.o
 obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o
+obj-$(CONFIG_SERIAL_OWL)   += owl-uart.o
 
 # GPIOLIB helpers for modem control lines
 obj-$(CONFIG_SERIAL_MCTRL_GPIO)+= serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/owl-uart.c b/drivers/tty/serial/owl-uart.c
new file mode 100644
index 000..1b80087
--- /dev/null
+++ b/drivers/tty/serial/owl-uart.c
@@ -0,0 +1,135 @@
+/*
+ * Actions Semi Owl family serial console
+ *
+ * Copyright 2013 Actions Semi Inc.
+ * Author: Actions Semi, Inc.
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define OWL_UART_CTL   0x000
+#define OWL_UART_TXDAT 0x008
+#define OWL_UART_STAT  0x00c
+
+#define OWL_UART_CTL_TRFS_TX   BIT(14)
+#define OWL_UART_CTL_ENBIT(15)
+#define OWL_UART_CTL_RXIE  BIT(18)
+#define OWL_UART_CTL_TXIE  BIT(19)
+
+#define OWL_UART_STAT_RIP  BIT(0)
+#define OWL_UART_STAT_TIP  BIT(1)
+#define OWL_UART_STAT_TFFU BIT(6)
+#define OWL_UART_STAT_TRFL_MASK(0x1f << 11)
+#define OWL_UART_STAT_UTBB BIT(17)
+
+static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned 
int off)
+{
+   writel(val, port->membase + off);
+}
+
+static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
+{
+   return readl(port->membase + off);
+}
+
+#ifdef CONFIG_SERIAL_OWL_CONSOLE
+
+static void owl_console_putchar(struct uart_port *port, int ch)
+{
+   if (!port->membase)
+   return;
+
+   while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
+   cpu_relax();
+
+   owl_uart_write(port, ch, OWL_UART_TXDAT);
+}
+
+static void owl_uart_port_write(struct uart_port *port, const char *s,
+   u_int count)
+{
+   u32 old_ctl, val;
+   unsigned long flags;
+   int locked;
+
+   local_irq_save(flags);
+
+   if (port->sysrq)
+   locked = 0;
+   else if (oops_in_progress)
+   locked = spin_trylock(>lock);
+   else {
+   spin_lock(>lock);
+   locked = 1;
+   }
+
+   old_ctl = owl_uart_read(port, OWL_UART_CTL);
+   val = old_ctl | OWL_UART_CTL_TRFS_TX;
+   /* disable IRQ */
+   val &= 

[PATCH v3 23/25] soc: actions: Add Owl SPS

[Andreas Färber]

Implement S500 Smart Power System power-gating.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber 
---
 v3: new
 
 drivers/soc/Kconfig   |   1 +
 drivers/soc/Makefile  |   1 +
 drivers/soc/actions/Kconfig   |  12 +++
 drivers/soc/actions/Makefile  |   1 +
 drivers/soc/actions/owl-sps.c | 245 ++
 5 files changed, 260 insertions(+)
 create mode 100644 drivers/soc/actions/Kconfig
 create mode 100644 drivers/soc/actions/Makefile
 create mode 100644 drivers/soc/actions/owl-sps.c

diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 45e5b13..afd3c43 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -1,5 +1,6 @@
 menu "SOC (System On Chip) specific Drivers"
 
+source "drivers/soc/actions/Kconfig"
 source "drivers/soc/atmel/Kconfig"
 source "drivers/soc/bcm/Kconfig"
 source "drivers/soc/fsl/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 3467de7..a934480 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,6 +2,7 @@
 # Makefile for the Linux Kernel SOC specific device drivers.
 #
 
+obj-$(CONFIG_ARCH_ACTIONS) += actions/
 obj-$(CONFIG_ARCH_AT91)+= atmel/
 obj-y  += bcm/
 obj-$(CONFIG_ARCH_DOVE)+= dove/
diff --git a/drivers/soc/actions/Kconfig b/drivers/soc/actions/Kconfig
new file mode 100644
index 000..f877f7d
--- /dev/null
+++ b/drivers/soc/actions/Kconfig
@@ -0,0 +1,12 @@
+if ARCH_ACTIONS || COMPILE_TEST
+
+config OWL_PM_DOMAINS
+   bool "Actions Semi SPS power domains"
+   depends on PM
+select PM_GENERIC_DOMAINS
+help
+ Say 'y' here to enable support for Smart Power System (SPS)
+ power-gating on Actions Semiconductor S500 SoC.
+ If unsure, say 'n'.
+
+endif
diff --git a/drivers/soc/actions/Makefile b/drivers/soc/actions/Makefile
new file mode 100644
index 000..720c34e
--- /dev/null
+++ b/drivers/soc/actions/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_OWL_PM_DOMAINS) += owl-sps.o
diff --git a/drivers/soc/actions/owl-sps.c b/drivers/soc/actions/owl-sps.c
new file mode 100644
index 000..caf777e
--- /dev/null
+++ b/drivers/soc/actions/owl-sps.c
@@ -0,0 +1,245 @@
+/*
+ * Actions Semi Owl Smart Power System (SPS)
+ *
+ * Copyright 2012 Actions Semi Inc.
+ * Author: Actions Semi, Inc.
+ *
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define OWL_SPS_PG_CTL 0x0
+
+struct owl_sps_domain_info {
+   const char *name;
+   int pwr_bit;
+   int ack_bit;
+};
+
+struct owl_sps_info {
+   unsigned num_domains;
+   const struct owl_sps_domain_info *domains;
+};
+
+struct owl_sps {
+   struct device *dev;
+   const struct owl_sps_info *info;
+   void __iomem *base;
+   struct genpd_onecell_data genpd_data;
+   struct generic_pm_domain *domains[];
+};
+
+#define to_owl_pd(gpd) container_of(gpd, struct owl_sps_domain, genpd)
+
+struct owl_sps_domain {
+   struct generic_pm_domain genpd;
+   const struct owl_sps_domain_info *info;
+   struct owl_sps *sps;
+};
+
+static int owl_sps_set_power(struct owl_sps_domain *pd, bool enable)
+{
+   u32 val, pwr_mask, ack_mask;
+   int timeout;
+   bool ack;
+
+   ack_mask = BIT(pd->info->ack_bit);
+   pwr_mask = BIT(pd->info->pwr_bit);
+   val = readl(pd->sps->base + OWL_SPS_PG_CTL);
+   ack = val & ack_mask;
+
+   if (ack == enable)
+   return 0;
+
+   if (enable)
+   val |= pwr_mask;
+   else
+   val &= ~pwr_mask;
+
+   writel(val, pd->sps->base + OWL_SPS_PG_CTL);
+
+   for (timeout = 5000; timeout > 0; timeout -= 50) {
+   val = readl(pd->sps->base + OWL_SPS_PG_CTL);
+   if ((val & ack_mask) == (enable ? ack_mask : 0))
+   break;
+   udelay(50);
+   }
+   if (timeout <= 0)
+   return -ETIMEDOUT;
+
+   udelay(10);
+
+   return 0;
+}
+
+static int owl_sps_power_on(struct generic_pm_domain *domain)
+{
+   struct owl_sps_domain *pd = to_owl_pd(domain);
+
+   return owl_sps_set_power(pd, true);
+}
+
+static int owl_sps_power_off(struct generic_pm_domain *domain)
+{
+   struct owl_sps_domain *pd = to_owl_pd(domain);
+
+   return owl_sps_set_power(pd, false);
+}
+
+static int owl_sps_init_domain(struct owl_sps *sps, int index)
+{
+   struct owl_sps_domain *pd;
+
+   pd = devm_kzalloc(sps->dev, sizeof(*pd), GFP_KERNEL);
+   if (!pd)
+   return -ENOMEM;
+
+   pd->info = >info->domains[index];
+   pd->sps = sps;
+
+   pd->genpd.name = 

[PATCH v3 23/25] soc: actions: Add Owl SPS

[Andreas Färber]

Implement S500 Smart Power System power-gating.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber 
---
 v3: new
 
 drivers/soc/Kconfig   |   1 +
 drivers/soc/Makefile  |   1 +
 drivers/soc/actions/Kconfig   |  12 +++
 drivers/soc/actions/Makefile  |   1 +
 drivers/soc/actions/owl-sps.c | 245 ++
 5 files changed, 260 insertions(+)
 create mode 100644 drivers/soc/actions/Kconfig
 create mode 100644 drivers/soc/actions/Makefile
 create mode 100644 drivers/soc/actions/owl-sps.c

diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 45e5b13..afd3c43 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -1,5 +1,6 @@
 menu "SOC (System On Chip) specific Drivers"
 
+source "drivers/soc/actions/Kconfig"
 source "drivers/soc/atmel/Kconfig"
 source "drivers/soc/bcm/Kconfig"
 source "drivers/soc/fsl/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 3467de7..a934480 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,6 +2,7 @@
 # Makefile for the Linux Kernel SOC specific device drivers.
 #
 
+obj-$(CONFIG_ARCH_ACTIONS) += actions/
 obj-$(CONFIG_ARCH_AT91)+= atmel/
 obj-y  += bcm/
 obj-$(CONFIG_ARCH_DOVE)+= dove/
diff --git a/drivers/soc/actions/Kconfig b/drivers/soc/actions/Kconfig
new file mode 100644
index 000..f877f7d
--- /dev/null
+++ b/drivers/soc/actions/Kconfig
@@ -0,0 +1,12 @@
+if ARCH_ACTIONS || COMPILE_TEST
+
+config OWL_PM_DOMAINS
+   bool "Actions Semi SPS power domains"
+   depends on PM
+select PM_GENERIC_DOMAINS
+help
+ Say 'y' here to enable support for Smart Power System (SPS)
+ power-gating on Actions Semiconductor S500 SoC.
+ If unsure, say 'n'.
+
+endif
diff --git a/drivers/soc/actions/Makefile b/drivers/soc/actions/Makefile
new file mode 100644
index 000..720c34e
--- /dev/null
+++ b/drivers/soc/actions/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_OWL_PM_DOMAINS) += owl-sps.o
diff --git a/drivers/soc/actions/owl-sps.c b/drivers/soc/actions/owl-sps.c
new file mode 100644
index 000..caf777e
--- /dev/null
+++ b/drivers/soc/actions/owl-sps.c
@@ -0,0 +1,245 @@
+/*
+ * Actions Semi Owl Smart Power System (SPS)
+ *
+ * Copyright 2012 Actions Semi Inc.
+ * Author: Actions Semi, Inc.
+ *
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define OWL_SPS_PG_CTL 0x0
+
+struct owl_sps_domain_info {
+   const char *name;
+   int pwr_bit;
+   int ack_bit;
+};
+
+struct owl_sps_info {
+   unsigned num_domains;
+   const struct owl_sps_domain_info *domains;
+};
+
+struct owl_sps {
+   struct device *dev;
+   const struct owl_sps_info *info;
+   void __iomem *base;
+   struct genpd_onecell_data genpd_data;
+   struct generic_pm_domain *domains[];
+};
+
+#define to_owl_pd(gpd) container_of(gpd, struct owl_sps_domain, genpd)
+
+struct owl_sps_domain {
+   struct generic_pm_domain genpd;
+   const struct owl_sps_domain_info *info;
+   struct owl_sps *sps;
+};
+
+static int owl_sps_set_power(struct owl_sps_domain *pd, bool enable)
+{
+   u32 val, pwr_mask, ack_mask;
+   int timeout;
+   bool ack;
+
+   ack_mask = BIT(pd->info->ack_bit);
+   pwr_mask = BIT(pd->info->pwr_bit);
+   val = readl(pd->sps->base + OWL_SPS_PG_CTL);
+   ack = val & ack_mask;
+
+   if (ack == enable)
+   return 0;
+
+   if (enable)
+   val |= pwr_mask;
+   else
+   val &= ~pwr_mask;
+
+   writel(val, pd->sps->base + OWL_SPS_PG_CTL);
+
+   for (timeout = 5000; timeout > 0; timeout -= 50) {
+   val = readl(pd->sps->base + OWL_SPS_PG_CTL);
+   if ((val & ack_mask) == (enable ? ack_mask : 0))
+   break;
+   udelay(50);
+   }
+   if (timeout <= 0)
+   return -ETIMEDOUT;
+
+   udelay(10);
+
+   return 0;
+}
+
+static int owl_sps_power_on(struct generic_pm_domain *domain)
+{
+   struct owl_sps_domain *pd = to_owl_pd(domain);
+
+   return owl_sps_set_power(pd, true);
+}
+
+static int owl_sps_power_off(struct generic_pm_domain *domain)
+{
+   struct owl_sps_domain *pd = to_owl_pd(domain);
+
+   return owl_sps_set_power(pd, false);
+}
+
+static int owl_sps_init_domain(struct owl_sps *sps, int index)
+{
+   struct owl_sps_domain *pd;
+
+   pd = devm_kzalloc(sps->dev, sizeof(*pd), GFP_KERNEL);
+   if (!pd)
+   return -ENOMEM;
+
+   pd->info = >info->domains[index];
+   pd->sps = sps;
+
+   pd->genpd.name = pd->info->name;
+   

[PATCH v3 00/25] ARM: Initial Actions Semi S500 and S900 enablement

[Andreas Färber]

Hello,

This series adds initial support for Actions Semiconductor S500 (ARMv7) and
S900 (ARMv8) SoCs.

v3 has the serial driver working almost equally for both, still glitch on S900.
SMP support and power-gating for S500 are implemented, so both get 4 CPUs up.

https://github.com/afaerber/linux/commits/bg96-next

Booting from U-Boot is straightforward on both boards:

https://en.opensuse.org/HCL:Guitar
https://en.opensuse.org/HCL:Bubblegum-96

Have a lot of fun!

Cheers,
Andreas

v2 -> v3:
* Clocksource fix
* Clocksource cleanups (Daniel)
* Serial cleanups
* Add S500 CPU enable-method
* Add power domain driver
* Rework clocksource for S900 compatibility

v1 -> v2:
* S900 DT fixes (Mark)
* Kconfig name changes (Arnd)
* Bubblegum-96 .dts rename
* Vendor prefix rename
* Minor cleanups
* Add serial driver
* Add MAINTAINERS section
* Use SPDX-License-Identifier in DT (Rob)
* Add clocksource driver

Cc: Mark Rutland 
Cc: Arnd Bergmann 
Cc: Rob Herring 
Cc: Daniel Lezcano 
Cc: mp...@actions-semi.com
Cc: 96boa...@ucrobotics.com
Cc: supp...@lemaker.org
Cc: linux-ser...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: devicet...@vger.kernel.org

Andreas Färber (25):
  dt-bindings: Add vendor prefix for Actions Semi
  dt-bindings: arm: Document Actions Semi S500
  dt-bindings: timer: Document Owl timer
  clocksource: Add Owl timer
  clocksource: owl: Add S900 support
  ARM: Prepare Actions Semi S500
  ARM64: Prepare Actions Semi S900
  dt-bindings: serial: Document Actions Semi Owl UARTs
  tty: serial: Add Actions Semi Owl UART earlycon
  Documentation: kernel-parameters: Document owl earlycon
  ARM: dts: Add Actions Semi S500 and LeMaker Guitar
  dt-bindings: Add vendor prefix for uCRobotics
  dt-bindings: arm: Document Actions Semi S900
  ARM64: dts: Add Actions Semi S900 and Bubblegum-96
  MAINTAINERS: Add Actions Semi Owl section
  tty: serial: owl: Implement console driver
  ARM64: dts: actions: s900-bubblegum-96: Add fake uart5 clock
  ARM: dts: s500-guitar-bb-rev-b: Add fake uart3 clock
  dt-bindings: arm: cpus: Add S500 enable-method
  ARM: owl: Implement CPU enable-method for S500
  ARM: dts: s500: Set CPU enable-method
  dt-bindings: power: Add Owl SPS power domains
  soc: actions: Add Owl SPS
  ARM: dts: s500: Add SPS node
  ARM: owl: smp: Reimplement SPS power-gating for CPU2 and CPU3

 Documentation/admin-guide/kernel-parameters.txt|   6 +
 Documentation/devicetree/bindings/arm/actions.txt  |  39 ++
 Documentation/devicetree/bindings/arm/cpus.txt |   1 +
 .../devicetree/bindings/power/actions,owl-sps.txt  |  17 +
 .../bindings/serial/actions,owl-uart.txt   |  16 +
 .../bindings/timer/actions,owl-timer.txt   |  20 +
 .../devicetree/bindings/vendor-prefixes.txt|   2 +
 MAINTAINERS|  10 +
 arch/arm/Kconfig   |   2 +
 arch/arm/Makefile  |   1 +
 arch/arm/boot/dts/Makefile |   2 +
 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts |  33 +
 arch/arm/boot/dts/s500-guitar.dtsi |  24 +
 arch/arm/boot/dts/s500.dtsi| 183 ++
 arch/arm/mach-actions/Kconfig  |  15 +
 arch/arm/mach-actions/Makefile |   2 +
 arch/arm/mach-actions/headsmp.S|  68 ++
 arch/arm/mach-actions/owl.c|  28 +
 arch/arm/mach-actions/platsmp.c| 229 +++
 arch/arm64/Kconfig.platforms   |   6 +
 arch/arm64/boot/dts/Makefile   |   1 +
 arch/arm64/boot/dts/actions/Makefile   |   5 +
 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts  |  42 ++
 arch/arm64/boot/dts/actions/s900.dtsi  | 164 +
 drivers/clocksource/Kconfig|   7 +
 drivers/clocksource/Makefile   |   1 +
 drivers/clocksource/owl-timer.c| 205 ++
 drivers/soc/Kconfig|   1 +
 drivers/soc/Makefile   |   1 +
 drivers/soc/actions/Kconfig|  12 +
 drivers/soc/actions/Makefile   |   1 +
 drivers/soc/actions/owl-sps.c  | 245 +++
 drivers/tty/serial/Kconfig |  19 +
 drivers/tty/serial/Makefile|   1 +
 drivers/tty/serial/owl-uart.c  | 724 +
 include/dt-bindings/power/s500-powergate.h |  19 +
 include/uapi/linux/serial_core.h   |   3 +
 37 files changed, 2155 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/actions.txt
 create mode 100644 Documentation/devicetree/bindings/power/actions,owl-sps.txt
 create mode 100644 
Documentation/devicetree/bindings/serial/actions,owl-uart.txt
 create mode 100644 

[PATCH v3 00/25] ARM: Initial Actions Semi S500 and S900 enablement

[Andreas Färber]

Hello,

This series adds initial support for Actions Semiconductor S500 (ARMv7) and
S900 (ARMv8) SoCs.

v3 has the serial driver working almost equally for both, still glitch on S900.
SMP support and power-gating for S500 are implemented, so both get 4 CPUs up.

https://github.com/afaerber/linux/commits/bg96-next

Booting from U-Boot is straightforward on both boards:

https://en.opensuse.org/HCL:Guitar
https://en.opensuse.org/HCL:Bubblegum-96

Have a lot of fun!

Cheers,
Andreas

v2 -> v3:
* Clocksource fix
* Clocksource cleanups (Daniel)
* Serial cleanups
* Add S500 CPU enable-method
* Add power domain driver
* Rework clocksource for S900 compatibility

v1 -> v2:
* S900 DT fixes (Mark)
* Kconfig name changes (Arnd)
* Bubblegum-96 .dts rename
* Vendor prefix rename
* Minor cleanups
* Add serial driver
* Add MAINTAINERS section
* Use SPDX-License-Identifier in DT (Rob)
* Add clocksource driver

Cc: Mark Rutland 
Cc: Arnd Bergmann 
Cc: Rob Herring 
Cc: Daniel Lezcano 
Cc: mp...@actions-semi.com
Cc: 96boa...@ucrobotics.com
Cc: supp...@lemaker.org
Cc: linux-ser...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: devicet...@vger.kernel.org

Andreas Färber (25):
  dt-bindings: Add vendor prefix for Actions Semi
  dt-bindings: arm: Document Actions Semi S500
  dt-bindings: timer: Document Owl timer
  clocksource: Add Owl timer
  clocksource: owl: Add S900 support
  ARM: Prepare Actions Semi S500
  ARM64: Prepare Actions Semi S900
  dt-bindings: serial: Document Actions Semi Owl UARTs
  tty: serial: Add Actions Semi Owl UART earlycon
  Documentation: kernel-parameters: Document owl earlycon
  ARM: dts: Add Actions Semi S500 and LeMaker Guitar
  dt-bindings: Add vendor prefix for uCRobotics
  dt-bindings: arm: Document Actions Semi S900
  ARM64: dts: Add Actions Semi S900 and Bubblegum-96
  MAINTAINERS: Add Actions Semi Owl section
  tty: serial: owl: Implement console driver
  ARM64: dts: actions: s900-bubblegum-96: Add fake uart5 clock
  ARM: dts: s500-guitar-bb-rev-b: Add fake uart3 clock
  dt-bindings: arm: cpus: Add S500 enable-method
  ARM: owl: Implement CPU enable-method for S500
  ARM: dts: s500: Set CPU enable-method
  dt-bindings: power: Add Owl SPS power domains
  soc: actions: Add Owl SPS
  ARM: dts: s500: Add SPS node
  ARM: owl: smp: Reimplement SPS power-gating for CPU2 and CPU3

 Documentation/admin-guide/kernel-parameters.txt|   6 +
 Documentation/devicetree/bindings/arm/actions.txt  |  39 ++
 Documentation/devicetree/bindings/arm/cpus.txt |   1 +
 .../devicetree/bindings/power/actions,owl-sps.txt  |  17 +
 .../bindings/serial/actions,owl-uart.txt   |  16 +
 .../bindings/timer/actions,owl-timer.txt   |  20 +
 .../devicetree/bindings/vendor-prefixes.txt|   2 +
 MAINTAINERS|  10 +
 arch/arm/Kconfig   |   2 +
 arch/arm/Makefile  |   1 +
 arch/arm/boot/dts/Makefile |   2 +
 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts |  33 +
 arch/arm/boot/dts/s500-guitar.dtsi |  24 +
 arch/arm/boot/dts/s500.dtsi| 183 ++
 arch/arm/mach-actions/Kconfig  |  15 +
 arch/arm/mach-actions/Makefile |   2 +
 arch/arm/mach-actions/headsmp.S|  68 ++
 arch/arm/mach-actions/owl.c|  28 +
 arch/arm/mach-actions/platsmp.c| 229 +++
 arch/arm64/Kconfig.platforms   |   6 +
 arch/arm64/boot/dts/Makefile   |   1 +
 arch/arm64/boot/dts/actions/Makefile   |   5 +
 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts  |  42 ++
 arch/arm64/boot/dts/actions/s900.dtsi  | 164 +
 drivers/clocksource/Kconfig|   7 +
 drivers/clocksource/Makefile   |   1 +
 drivers/clocksource/owl-timer.c| 205 ++
 drivers/soc/Kconfig|   1 +
 drivers/soc/Makefile   |   1 +
 drivers/soc/actions/Kconfig|  12 +
 drivers/soc/actions/Makefile   |   1 +
 drivers/soc/actions/owl-sps.c  | 245 +++
 drivers/tty/serial/Kconfig |  19 +
 drivers/tty/serial/Makefile|   1 +
 drivers/tty/serial/owl-uart.c  | 724 +
 include/dt-bindings/power/s500-powergate.h |  19 +
 include/uapi/linux/serial_core.h   |   3 +
 37 files changed, 2155 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/actions.txt
 create mode 100644 Documentation/devicetree/bindings/power/actions,owl-sps.txt
 create mode 100644 
Documentation/devicetree/bindings/serial/actions,owl-uart.txt
 create mode 100644 
Documentation/devicetree/bindings/timer/actions,owl-timer.txt
 create mode 100644 

[PATCH v3 01/25] dt-bindings: Add vendor prefix for Actions Semi

[Andreas Färber]

Actions Semiconductor was listed on NASDAQ as ACTS until Dec 16, 2016.

Cc: mp...@actions-semi.com
Acked-by: Rob Herring 
Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Fixed sort order after rename
 
 v1 -> v2:
 * Reverted from "acts" to "actions" (cf. IAP140 "mrvl" vs. "marvell")
 
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt 
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index a76b981..2f294c8 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -5,6 +5,7 @@ using them to avoid name-space collisions.
 
 abcn   Abracon Corporation
 abilis Abilis Systems
+actionsActions Semiconductor Co., Ltd.
 active-semiActive-Semi International Inc
 ad Avionic Design GmbH
 adapteva   Adapteva, Inc.
-- 
2.10.2

[PATCH v3 13/25] dt-bindings: arm: Document Actions Semi S900

[Andreas Färber]

The Actions Semi S900 is a quad-core ARM Cortex-A53 SoC.
The Bubblegum-96 is a 96Boards Consumer Edition compliant board (4/96).

Cc: 96boa...@ucrobotics.com
Acked-by: Rob Herring 
Signed-off-by: Andreas Färber 
---
 v2 -> v3: unchanged
 
 v1 -> v2:
 * Adopted "actions" vendor prefix
 * Extended text
 
 Documentation/devicetree/bindings/arm/actions.txt | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/actions.txt 
b/Documentation/devicetree/bindings/arm/actions.txt
index 1d3782e..3bc7ea5 100644
--- a/Documentation/devicetree/bindings/arm/actions.txt
+++ b/Documentation/devicetree/bindings/arm/actions.txt
@@ -22,3 +22,18 @@ Boards:
 Root node property compatible must contain, depending on board:
 
  - LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", 
"lemaker,guitar"
+
+
+S900 SoC
+
+
+Required root node properties:
+
+- compatible :  must contain "actions,s900"
+
+
+Boards:
+
+Root node property compatible must contain, depending on board:
+
+ - uCRobotics Bubblegum-96: "ucrobotics,bubblegum-96"
-- 
2.10.2

[PATCH v3 02/25] dt-bindings: arm: Document Actions Semi S500

[Andreas Färber]

The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
The LeMaker Guitar is an SODIMM-format module with that SoC.

Acked-by: Rob Herring 
Signed-off-by: Andreas Färber 
---
 v2 -> v3: unchanged
 
 v1 -> v2:
 * Adopted "actions" vendor prefix
 * Extended text
 
 Documentation/devicetree/bindings/arm/actions.txt | 24 +++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/actions.txt

diff --git a/Documentation/devicetree/bindings/arm/actions.txt 
b/Documentation/devicetree/bindings/arm/actions.txt
new file mode 100644
index 000..1d3782e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/actions.txt
@@ -0,0 +1,24 @@
+Actions Semi platforms device tree bindings
+---
+
+
+S500 SoC
+
+
+Required root node properties:
+
+ - compatible :  must contain "actions,s500"
+
+
+Modules:
+
+Root node property compatible must contain, depending on module:
+
+ - LeMaker Guitar: "lemaker,guitar"
+
+
+Boards:
+
+Root node property compatible must contain, depending on board:
+
+ - LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", 
"lemaker,guitar"
-- 
2.10.2

[PATCH v3 11/25] ARM: dts: Add Actions Semi S500 and LeMaker Guitar

[Andreas Färber]

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Fixed uart2 reg offset
 * Enlarged timer reg size
 * Added 2 Hz timer interrupts, interrupt-names
 * Disabled CPUs 1-3 for now (cf. later patches)
 * Added Cortex-A9 SCU, global timer, TWD timer/wdt nodes
 * Added HOSC clock for timer
 
 v1 -> v2:
 * Reworded subject
 * Updated ARCH_OWL to ARCH_ACTIONS (Arnd)
 * Adopted "actions" vendor prefix
 * Dropped irq.h include
 * Added memory@0 node for Guitar SoM
 * Dropped bogus uart3 clock-frequency
 * Added device_type for CPU nodes
 * Fixed UART reg size
 * Adopted SPDX-License-Identifier (Rob)
 * Added remaining UART nodes
 * Added timer node
 
 arch/arm/boot/dts/Makefile |   2 +
 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts |  26 +
 arch/arm/boot/dts/s500-guitar.dtsi |  24 
 arch/arm/boot/dts/s500.dtsi| 170 +
 4 files changed, 222 insertions(+)
 create mode 100644 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
 create mode 100644 arch/arm/boot/dts/s500-guitar.dtsi
 create mode 100644 arch/arm/boot/dts/s500.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0118084..578a20b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -638,6 +638,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
orion5x-maxtor-shared-storage-2.dtb \
orion5x-netgear-wnr854t.dtb \
orion5x-rd88f5182-nas.dtb
+dtb-$(CONFIG_ARCH_ACTIONS) += \
+   s500-guitar-bb-rev-b.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
 dtb-$(CONFIG_ARCH_OXNAS) += \
diff --git a/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts 
b/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
new file mode 100644
index 000..834b71d
--- /dev/null
+++ b/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include "s500-guitar.dtsi"
+
+/ {
+   compatible = "lemaker,guitar-bb-rev-b", "lemaker,guitar", 
"actions,s500";
+   model = "LeMaker Guitar Base Board rev. B";
+
+   aliases {
+   serial3 = 
+   };
+
+   chosen {
+   stdout-path = "serial3:115200n8";
+   };
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/boot/dts/s500-guitar.dtsi 
b/arch/arm/boot/dts/s500-guitar.dtsi
new file mode 100644
index 000..31c5def
--- /dev/null
+++ b/arch/arm/boot/dts/s500-guitar.dtsi
@@ -0,0 +1,24 @@
+/*
+ * LeMaker Guitar SoM
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include "s500.dtsi"
+
+/ {
+   compatible = "lemaker,guitar", "actions,s500";
+
+   /delete-node/ memory;
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x4000>;
+   };
+};
+
+ {
+   clocks = <>;
+};
diff --git a/arch/arm/boot/dts/s500.dtsi b/arch/arm/boot/dts/s500.dtsi
new file mode 100644
index 000..1973181
--- /dev/null
+++ b/arch/arm/boot/dts/s500.dtsi
@@ -0,0 +1,170 @@
+/*
+ * Actions Semi S500 SoC
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include "skeleton.dtsi"
+
+#include 
+
+/ {
+   compatible = "actions,s500";
+   interrupt-parent = <>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x0>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x1>;
+   };
+
+   cpu2: cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x2>;
+   };
+
+   cpu3: cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x3>;
+   };
+   };
+
+   arm-pmu {
+   compatible = "arm,cortex-a9-pmu";
+   interrupts = ,
+,
+,
+;
+   interrupt-affinity = <>, <>, <>, <>;
+   };
+
+   hosc: hosc {
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   #clock-cells = <0>;
+   };
+
+   soc {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   scu: scu@b002 {
+   compatible = "arm,cortex-a9-scu";
+   reg = <0xb002 0x100>;
+   };
+
+   global_timer: timer@b0020200 {
+   compatible = 

[PATCH v3 13/25] dt-bindings: arm: Document Actions Semi S900

[Andreas Färber]

The Actions Semi S900 is a quad-core ARM Cortex-A53 SoC.
The Bubblegum-96 is a 96Boards Consumer Edition compliant board (4/96).

Cc: 96boa...@ucrobotics.com
Acked-by: Rob Herring 
Signed-off-by: Andreas Färber 
---
 v2 -> v3: unchanged
 
 v1 -> v2:
 * Adopted "actions" vendor prefix
 * Extended text
 
 Documentation/devicetree/bindings/arm/actions.txt | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/actions.txt 
b/Documentation/devicetree/bindings/arm/actions.txt
index 1d3782e..3bc7ea5 100644
--- a/Documentation/devicetree/bindings/arm/actions.txt
+++ b/Documentation/devicetree/bindings/arm/actions.txt
@@ -22,3 +22,18 @@ Boards:
 Root node property compatible must contain, depending on board:
 
  - LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", 
"lemaker,guitar"
+
+
+S900 SoC
+
+
+Required root node properties:
+
+- compatible :  must contain "actions,s900"
+
+
+Boards:
+
+Root node property compatible must contain, depending on board:
+
+ - uCRobotics Bubblegum-96: "ucrobotics,bubblegum-96"
-- 
2.10.2

[PATCH v3 02/25] dt-bindings: arm: Document Actions Semi S500

[Andreas Färber]

The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
The LeMaker Guitar is an SODIMM-format module with that SoC.

Acked-by: Rob Herring 
Signed-off-by: Andreas Färber 
---
 v2 -> v3: unchanged
 
 v1 -> v2:
 * Adopted "actions" vendor prefix
 * Extended text
 
 Documentation/devicetree/bindings/arm/actions.txt | 24 +++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/actions.txt

diff --git a/Documentation/devicetree/bindings/arm/actions.txt 
b/Documentation/devicetree/bindings/arm/actions.txt
new file mode 100644
index 000..1d3782e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/actions.txt
@@ -0,0 +1,24 @@
+Actions Semi platforms device tree bindings
+---
+
+
+S500 SoC
+
+
+Required root node properties:
+
+ - compatible :  must contain "actions,s500"
+
+
+Modules:
+
+Root node property compatible must contain, depending on module:
+
+ - LeMaker Guitar: "lemaker,guitar"
+
+
+Boards:
+
+Root node property compatible must contain, depending on board:
+
+ - LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", 
"lemaker,guitar"
-- 
2.10.2

[PATCH v3 11/25] ARM: dts: Add Actions Semi S500 and LeMaker Guitar

[Andreas Färber]

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Fixed uart2 reg offset
 * Enlarged timer reg size
 * Added 2 Hz timer interrupts, interrupt-names
 * Disabled CPUs 1-3 for now (cf. later patches)
 * Added Cortex-A9 SCU, global timer, TWD timer/wdt nodes
 * Added HOSC clock for timer
 
 v1 -> v2:
 * Reworded subject
 * Updated ARCH_OWL to ARCH_ACTIONS (Arnd)
 * Adopted "actions" vendor prefix
 * Dropped irq.h include
 * Added memory@0 node for Guitar SoM
 * Dropped bogus uart3 clock-frequency
 * Added device_type for CPU nodes
 * Fixed UART reg size
 * Adopted SPDX-License-Identifier (Rob)
 * Added remaining UART nodes
 * Added timer node
 
 arch/arm/boot/dts/Makefile |   2 +
 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts |  26 +
 arch/arm/boot/dts/s500-guitar.dtsi |  24 
 arch/arm/boot/dts/s500.dtsi| 170 +
 4 files changed, 222 insertions(+)
 create mode 100644 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
 create mode 100644 arch/arm/boot/dts/s500-guitar.dtsi
 create mode 100644 arch/arm/boot/dts/s500.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0118084..578a20b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -638,6 +638,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
orion5x-maxtor-shared-storage-2.dtb \
orion5x-netgear-wnr854t.dtb \
orion5x-rd88f5182-nas.dtb
+dtb-$(CONFIG_ARCH_ACTIONS) += \
+   s500-guitar-bb-rev-b.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
 dtb-$(CONFIG_ARCH_OXNAS) += \
diff --git a/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts 
b/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
new file mode 100644
index 000..834b71d
--- /dev/null
+++ b/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include "s500-guitar.dtsi"
+
+/ {
+   compatible = "lemaker,guitar-bb-rev-b", "lemaker,guitar", 
"actions,s500";
+   model = "LeMaker Guitar Base Board rev. B";
+
+   aliases {
+   serial3 = 
+   };
+
+   chosen {
+   stdout-path = "serial3:115200n8";
+   };
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/boot/dts/s500-guitar.dtsi 
b/arch/arm/boot/dts/s500-guitar.dtsi
new file mode 100644
index 000..31c5def
--- /dev/null
+++ b/arch/arm/boot/dts/s500-guitar.dtsi
@@ -0,0 +1,24 @@
+/*
+ * LeMaker Guitar SoM
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include "s500.dtsi"
+
+/ {
+   compatible = "lemaker,guitar", "actions,s500";
+
+   /delete-node/ memory;
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x4000>;
+   };
+};
+
+ {
+   clocks = <>;
+};
diff --git a/arch/arm/boot/dts/s500.dtsi b/arch/arm/boot/dts/s500.dtsi
new file mode 100644
index 000..1973181
--- /dev/null
+++ b/arch/arm/boot/dts/s500.dtsi
@@ -0,0 +1,170 @@
+/*
+ * Actions Semi S500 SoC
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include "skeleton.dtsi"
+
+#include 
+
+/ {
+   compatible = "actions,s500";
+   interrupt-parent = <>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x0>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x1>;
+   };
+
+   cpu2: cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x2>;
+   };
+
+   cpu3: cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a9";
+   reg = <0x3>;
+   };
+   };
+
+   arm-pmu {
+   compatible = "arm,cortex-a9-pmu";
+   interrupts = ,
+,
+,
+;
+   interrupt-affinity = <>, <>, <>, <>;
+   };
+
+   hosc: hosc {
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   #clock-cells = <0>;
+   };
+
+   soc {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   scu: scu@b002 {
+   compatible = "arm,cortex-a9-scu";
+   reg = <0xb002 0x100>;
+   };
+
+   global_timer: timer@b0020200 {
+   compatible = 

[PATCH v3 01/25] dt-bindings: Add vendor prefix for Actions Semi

[Andreas Färber]

Actions Semiconductor was listed on NASDAQ as ACTS until Dec 16, 2016.

Cc: mp...@actions-semi.com
Acked-by: Rob Herring 
Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Fixed sort order after rename
 
 v1 -> v2:
 * Reverted from "acts" to "actions" (cf. IAP140 "mrvl" vs. "marvell")
 
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt 
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index a76b981..2f294c8 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -5,6 +5,7 @@ using them to avoid name-space collisions.
 
 abcn   Abracon Corporation
 abilis Abilis Systems
+actionsActions Semiconductor Co., Ltd.
 active-semiActive-Semi International Inc
 ad Avionic Design GmbH
 adapteva   Adapteva, Inc.
-- 
2.10.2

[PATCH] pwm: rockchip: State of pwm clock should synchronize with pwm enabled state

[David Wu]

From: "david.wu" 

If the pwm was not enabled at uboot loader, pwm could not work for clock
always disabled at pwm driver. The pwm clock is enabled at beginning of
pwm_apply(), but disabled at end of pwm_apply().

If the pwm was enabled at uboot loader, pwm clock is always enabled unless
closed by ATF. The pwm-backlight might turn off the power at early suspend,
should disable pwm clock for saving power consume.

It is important to provide opportunity to enable/disable clock at pwm driver,
the pwm consumer should ensure correct order to call pwm enable/disable, and
pwm driver ensure state of pwm clock synchronized with pwm enabled state.

Signed-off-by: David Wu 
---
 drivers/pwm/pwm-rockchip.c | 38 +++---
 1 file changed, 31 insertions(+), 7 deletions(-)

diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c
index ef89df1..14a0445 100644
--- a/drivers/pwm/pwm-rockchip.c
+++ b/drivers/pwm/pwm-rockchip.c
@@ -191,6 +191,26 @@ static int rockchip_pwm_config(struct pwm_chip *chip, 
struct pwm_device *pwm,
return 0;
 }
 
+static int rk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
+bool enable, enum pwm_polarity polarity)
+{
+   struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
+   int ret;
+
+   if (enable) {
+   ret = clk_enable(pc->clk);
+   if (ret)
+   return ret;
+   }
+
+   pc->data->set_enable(chip, pwm, enable, polarity);
+
+   if (!enable)
+   clk_disable(pc->clk);
+
+   return 0;
+}
+
 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  struct pwm_state *state)
 {
@@ -207,22 +227,26 @@ static int rockchip_pwm_apply(struct pwm_chip *chip, 
struct pwm_device *pwm,
return ret;
 
if (state->polarity != curstate.polarity && enabled) {
-   pc->data->set_enable(chip, pwm, false, state->polarity);
+   ret = rk_pwm_enable(chip, pwm, false, state->polarity);
+   if (ret)
+   goto out;
enabled = false;
}
 
ret = rockchip_pwm_config(chip, pwm, state->duty_cycle, state->period);
if (ret) {
if (enabled != curstate.enabled)
-   pc->data->set_enable(chip, pwm, !enabled,
-state->polarity);
-
+   rk_pwm_enable(chip, pwm, !enabled,
+ state->polarity);
goto out;
}
 
-   if (state->enabled != enabled)
-   pc->data->set_enable(chip, pwm, state->enabled,
-state->polarity);
+   if (state->enabled != enabled) {
+   ret = rk_pwm_enable(chip, pwm, state->enabled,
+   state->polarity);
+   if (ret)
+   goto out;
+   }
 
/*
 * Update the state with the real hardware, which can differ a bit
-- 
1.9.1

[PATCH] pwm: rockchip: State of pwm clock should synchronize with pwm enabled state

[David Wu]

From: "david.wu" 

If the pwm was not enabled at uboot loader, pwm could not work for clock
always disabled at pwm driver. The pwm clock is enabled at beginning of
pwm_apply(), but disabled at end of pwm_apply().

If the pwm was enabled at uboot loader, pwm clock is always enabled unless
closed by ATF. The pwm-backlight might turn off the power at early suspend,
should disable pwm clock for saving power consume.

It is important to provide opportunity to enable/disable clock at pwm driver,
the pwm consumer should ensure correct order to call pwm enable/disable, and
pwm driver ensure state of pwm clock synchronized with pwm enabled state.

Signed-off-by: David Wu 
---
 drivers/pwm/pwm-rockchip.c | 38 +++---
 1 file changed, 31 insertions(+), 7 deletions(-)

diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c
index ef89df1..14a0445 100644
--- a/drivers/pwm/pwm-rockchip.c
+++ b/drivers/pwm/pwm-rockchip.c
@@ -191,6 +191,26 @@ static int rockchip_pwm_config(struct pwm_chip *chip, 
struct pwm_device *pwm,
return 0;
 }
 
+static int rk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
+bool enable, enum pwm_polarity polarity)
+{
+   struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
+   int ret;
+
+   if (enable) {
+   ret = clk_enable(pc->clk);
+   if (ret)
+   return ret;
+   }
+
+   pc->data->set_enable(chip, pwm, enable, polarity);
+
+   if (!enable)
+   clk_disable(pc->clk);
+
+   return 0;
+}
+
 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  struct pwm_state *state)
 {
@@ -207,22 +227,26 @@ static int rockchip_pwm_apply(struct pwm_chip *chip, 
struct pwm_device *pwm,
return ret;
 
if (state->polarity != curstate.polarity && enabled) {
-   pc->data->set_enable(chip, pwm, false, state->polarity);
+   ret = rk_pwm_enable(chip, pwm, false, state->polarity);
+   if (ret)
+   goto out;
enabled = false;
}
 
ret = rockchip_pwm_config(chip, pwm, state->duty_cycle, state->period);
if (ret) {
if (enabled != curstate.enabled)
-   pc->data->set_enable(chip, pwm, !enabled,
-state->polarity);
-
+   rk_pwm_enable(chip, pwm, !enabled,
+ state->polarity);
goto out;
}
 
-   if (state->enabled != enabled)
-   pc->data->set_enable(chip, pwm, state->enabled,
-state->polarity);
+   if (state->enabled != enabled) {
+   ret = rk_pwm_enable(chip, pwm, state->enabled,
+   state->polarity);
+   if (ret)
+   goto out;
+   }
 
/*
 * Update the state with the real hardware, which can differ a bit
-- 
1.9.1

[PATCH v3 04/25] clocksource: Add Owl timer

[Andreas Färber]

The Actions Semi S500 SoC provides four timers, 2Hz0/1 and 32-bit TIMER0/1.

Use TIMER0 as clocksource and TIMER1 as clockevents.

Based on LeMaker linux-actions tree.

An S500 datasheet can be found on the LeMaker Guitar pages:
http://www.lemaker.org/product-guitar-download-29.html

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Cleared interrupt pending flag for Timer1
 * Adopted named interrupts for Timer1
 * Extended commit message (Daniel)
 * Adopted BIT() macros (Daniel)
 * Adopted PTR_ERR() (Daniel)
 * Adopted request_irq() (Daniel)
 * Factored timer reset out (Daniel)
 * Adopted CLOCK_EVT_FEAT_DYNIRQ (Daniel)
 * Adopted clk input for rate (Daniel)
 * Prepared for S900, adopting S500 DT compatible
 
 v2: new
 
 drivers/clocksource/Kconfig |   7 ++
 drivers/clocksource/Makefile|   1 +
 drivers/clocksource/owl-timer.c | 193 
 3 files changed, 201 insertions(+)
 create mode 100644 drivers/clocksource/owl-timer.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 3356ab8..2551365 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -107,6 +107,13 @@ config ORION_TIMER
help
  Enables the support for the Orion timer driver
 
+config OWL_TIMER
+   bool "Owl timer driver" if COMPILE_TEST
+   depends on GENERIC_CLOCKEVENTS
+   select CLKSRC_MMIO
+   help
+ Enables the support for the Actions Semi Owl timer driver.
+
 config SUN4I_TIMER
bool "Sun4i timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index d227d13..801b65a 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_CLKSRC_PISTACHIO)+= time-pistachio.o
 obj-$(CONFIG_CLKSRC_TI_32K)+= timer-ti-32k.o
 obj-$(CONFIG_CLKSRC_NPS)   += timer-nps.o
 obj-$(CONFIG_OXNAS_RPS_TIMER)  += timer-oxnas-rps.o
+obj-$(CONFIG_OWL_TIMER)+= owl-timer.o
 
 obj-$(CONFIG_ARC_TIMERS)   += arc_timer.o
 obj-$(CONFIG_ARM_ARCH_TIMER)   += arm_arch_timer.o
diff --git a/drivers/clocksource/owl-timer.c b/drivers/clocksource/owl-timer.c
new file mode 100644
index 000..1b1e26d
--- /dev/null
+++ b/drivers/clocksource/owl-timer.c
@@ -0,0 +1,193 @@
+/*
+ * Actions Semi Owl timer
+ *
+ * Copyright 2012 Actions Semi Inc.
+ * Author: Actions Semi, Inc.
+ *
+ * Copyright (c) 2017 SUSE Linux GmbH
+ * Author: Andreas Färber
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define OWL_Tx_CTL 0x0
+#define OWL_Tx_CMP 0x4
+#define OWL_Tx_VAL 0x8
+
+#define OWL_Tx_CTL_PD  BIT(0)
+#define OWL_Tx_CTL_INTEN   BIT(1)
+#define OWL_Tx_CTL_EN  BIT(2)
+
+#define OWL_MAX_Tx 2
+
+struct owl_timer_info {
+   int timer_offset[OWL_MAX_Tx];
+};
+
+static const struct owl_timer_info *owl_timer_info;
+
+static void __iomem *owl_timer_base;
+
+static inline void __iomem *owl_timer_get_base(unsigned timer_nr)
+{
+   if (timer_nr >= OWL_MAX_Tx)
+   return NULL;
+
+   return owl_timer_base + owl_timer_info->timer_offset[timer_nr];
+}
+
+static inline void owl_timer_reset(unsigned index)
+{
+   void __iomem *base;
+
+   base = owl_timer_get_base(index);
+   if (!base)
+   return;
+
+   writel(0, base + OWL_Tx_CTL);
+   writel(0, base + OWL_Tx_VAL);
+   writel(0, base + OWL_Tx_CMP);
+}
+
+static u64 notrace owl_timer_sched_read(void)
+{
+   return (u64)readl(owl_timer_get_base(0) + OWL_Tx_VAL);
+}
+
+static int owl_timer_set_state_shutdown(struct clock_event_device *evt)
+{
+   writel(0, owl_timer_get_base(0) + OWL_Tx_CTL);
+
+   return 0;
+}
+
+static int owl_timer_set_state_oneshot(struct clock_event_device *evt)
+{
+   owl_timer_reset(1);
+
+   return 0;
+}
+
+static int owl_timer_tick_resume(struct clock_event_device *evt)
+{
+   return 0;
+}
+
+static int owl_timer_set_next_event(unsigned long evt,
+   struct clock_event_device *ev)
+{
+   void __iomem *base = owl_timer_get_base(1);
+
+   writel(0, base + OWL_Tx_CTL);
+
+   writel(0, base + OWL_Tx_VAL);
+   writel(evt, base + OWL_Tx_CMP);
+
+   writel(OWL_Tx_CTL_EN | OWL_Tx_CTL_INTEN, base + OWL_Tx_CTL);
+
+   return 0;
+}
+
+static struct clock_event_device owl_clockevent = {
+   .name   = "owl_tick",
+   .rating = 200,
+   .features   = CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_DYNIRQ,
+   

[PATCH v3 07/25] ARM64: Prepare Actions Semi S900

[Andreas Färber]

Add ARCH_ACTIONS.

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Selected clocksource driver
 
 v1 -> v2:
 * Renamed ARCH_OWL to ARCH_ACTION (Arnd)
 
 arch/arm64/Kconfig.platforms | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 129cc5a..761b31f 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -1,5 +1,11 @@
 menu "Platform selection"
 
+config ARCH_ACTIONS
+   bool "Actions Semi Platforms"
+   select OWL_TIMER
+   help
+ This enables support for the Actions Semiconductor S900 SoC family.
+
 config ARCH_SUNXI
bool "Allwinner sunxi 64-bit SoC Family"
select GENERIC_IRQ_CHIP
-- 
2.10.2

Re: [PATCH 3/4] drm/bridge: Drivers for megachips-stdpxxxx-ge-b850v3-fw (LVDS-DP++)

[Archit Taneja]

On 02/27/2017 07:10 PM, Peter Senna Tschudin wrote:

On Wed, Feb 01, 2017 at 04:17:21PM +0530, Archit Taneja wrote:
Hi Archit,


Hi,

Some minor comments:


Thank you for the review!



On 01/28/2017 07:51 PM, Peter Senna Tschudin wrote:

The video processing pipeline on the second output on the GE B850v3:

  Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output

Each bridge has a dedicated flash containing firmware for supporting the
custom design. The result is that in this design neither the STDP4028
nor the STDP2690 behave as the stock bridges would. The compatible
strings include the suffix "-ge-b850v3-fw" to make it clear that the
driver is for the bridges with the firmware which is specific for the GE
B850v3.

The driver is powerless to control the video processing pipeline, as the
two bridges behaves as a single one. The driver is only needed for
telling the host about EDID / HPD, and for giving the host powers to ack
interrupts.

This driver adds one i2c_device for each bridge, but only one
drm_bridge. This design allows the creation of a functional connector
that is capable of reading EDID from the STDP2690 while handling
interrupts on the STDP4028.

Cc: Laurent Pinchart 
Cc: Martyn Welch 
Cc: Martin Donnelly 
Cc: Daniel Vetter 
Cc: Enric Balletbo i Serra 
Cc: Philipp Zabel 
Cc: Rob Herring 
Cc: Fabio Estevam 
Cc: David Airlie 
Cc: Thierry Reding 
Cc: Thierry Reding 
Cc: Archit Taneja 
Cc: Enric Balletbo 
Signed-off-by: Peter Senna Tschudin 
---
 drivers/gpu/drm/bridge/Kconfig |  11 +
 drivers/gpu/drm/bridge/Makefile|   1 +
 .../drm/bridge/megachips-stdp-ge-b850v3-fw.c   | 408 +
 3 files changed, 420 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/megachips-stdp-ge-b850v3-fw.c

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index eb8688e..4a937f1 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -48,6 +48,17 @@ config DRM_DW_HDMI_I2S_AUDIO
  Support the I2S Audio interface which is part of the Synopsis
  Designware HDMI block.

+config DRM_MEGACHIPS_STDP_GE_B850V3_FW
+   tristate "MegaChips stdp4028-ge-b850v3-fw and stdp2690-ge-b850v3-fw"
+   depends on OF
+   select DRM_KMS_HELPER
+   select DRM_PANEL
+   ---help---
+  This is a driver for the display bridges of
+  GE B850v3 that convert dual channel LVDS
+  to DP++. This is used with the i.MX6 imx-ldb
+  driver. You are likely to say N here.
+
 config DRM_NXP_PTN3460
tristate "NXP PTN3460 DP/LVDS bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 2e83a785..af0b7cc 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o
 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
 obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
+obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) += 
megachips-stdp-ge-b850v3-fw.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
 obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o
diff --git a/drivers/gpu/drm/bridge/megachips-stdp-ge-b850v3-fw.c 
b/drivers/gpu/drm/bridge/megachips-stdp-ge-b850v3-fw.c
new file mode 100644
index 000..13de03cf
--- /dev/null
+++ b/drivers/gpu/drm/bridge/megachips-stdp-ge-b850v3-fw.c
@@ -0,0 +1,408 @@
+/*
+ * Driver for MegaChips STDP4028 with GE B850v3 firmware (LVDS-DP)
+ * Driver for MegaChips STDP2690 with GE B850v3 firmware (DP-DP++)
+
+ * Copyright (c) 2016, Collabora Ltd.
+ * Copyright (c) 2016, General Electric Company


2017?


Fixed.




+
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+
+ * This driver creates a drm_bridge and a drm_connector for the LVDS to DP++
+ * display bridge of the GE B850v3. There are two physical bridges on the video
+ * signal pipeline: a STDP4028(LVDS to 

[PATCH v3 04/25] clocksource: Add Owl timer

[Andreas Färber]

The Actions Semi S500 SoC provides four timers, 2Hz0/1 and 32-bit TIMER0/1.

Use TIMER0 as clocksource and TIMER1 as clockevents.

Based on LeMaker linux-actions tree.

An S500 datasheet can be found on the LeMaker Guitar pages:
http://www.lemaker.org/product-guitar-download-29.html

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Cleared interrupt pending flag for Timer1
 * Adopted named interrupts for Timer1
 * Extended commit message (Daniel)
 * Adopted BIT() macros (Daniel)
 * Adopted PTR_ERR() (Daniel)
 * Adopted request_irq() (Daniel)
 * Factored timer reset out (Daniel)
 * Adopted CLOCK_EVT_FEAT_DYNIRQ (Daniel)
 * Adopted clk input for rate (Daniel)
 * Prepared for S900, adopting S500 DT compatible
 
 v2: new
 
 drivers/clocksource/Kconfig |   7 ++
 drivers/clocksource/Makefile|   1 +
 drivers/clocksource/owl-timer.c | 193 
 3 files changed, 201 insertions(+)
 create mode 100644 drivers/clocksource/owl-timer.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 3356ab8..2551365 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -107,6 +107,13 @@ config ORION_TIMER
help
  Enables the support for the Orion timer driver
 
+config OWL_TIMER
+   bool "Owl timer driver" if COMPILE_TEST
+   depends on GENERIC_CLOCKEVENTS
+   select CLKSRC_MMIO
+   help
+ Enables the support for the Actions Semi Owl timer driver.
+
 config SUN4I_TIMER
bool "Sun4i timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index d227d13..801b65a 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_CLKSRC_PISTACHIO)+= time-pistachio.o
 obj-$(CONFIG_CLKSRC_TI_32K)+= timer-ti-32k.o
 obj-$(CONFIG_CLKSRC_NPS)   += timer-nps.o
 obj-$(CONFIG_OXNAS_RPS_TIMER)  += timer-oxnas-rps.o
+obj-$(CONFIG_OWL_TIMER)+= owl-timer.o
 
 obj-$(CONFIG_ARC_TIMERS)   += arc_timer.o
 obj-$(CONFIG_ARM_ARCH_TIMER)   += arm_arch_timer.o
diff --git a/drivers/clocksource/owl-timer.c b/drivers/clocksource/owl-timer.c
new file mode 100644
index 000..1b1e26d
--- /dev/null
+++ b/drivers/clocksource/owl-timer.c
@@ -0,0 +1,193 @@
+/*
+ * Actions Semi Owl timer
+ *
+ * Copyright 2012 Actions Semi Inc.
+ * Author: Actions Semi, Inc.
+ *
+ * Copyright (c) 2017 SUSE Linux GmbH
+ * Author: Andreas Färber
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define OWL_Tx_CTL 0x0
+#define OWL_Tx_CMP 0x4
+#define OWL_Tx_VAL 0x8
+
+#define OWL_Tx_CTL_PD  BIT(0)
+#define OWL_Tx_CTL_INTEN   BIT(1)
+#define OWL_Tx_CTL_EN  BIT(2)
+
+#define OWL_MAX_Tx 2
+
+struct owl_timer_info {
+   int timer_offset[OWL_MAX_Tx];
+};
+
+static const struct owl_timer_info *owl_timer_info;
+
+static void __iomem *owl_timer_base;
+
+static inline void __iomem *owl_timer_get_base(unsigned timer_nr)
+{
+   if (timer_nr >= OWL_MAX_Tx)
+   return NULL;
+
+   return owl_timer_base + owl_timer_info->timer_offset[timer_nr];
+}
+
+static inline void owl_timer_reset(unsigned index)
+{
+   void __iomem *base;
+
+   base = owl_timer_get_base(index);
+   if (!base)
+   return;
+
+   writel(0, base + OWL_Tx_CTL);
+   writel(0, base + OWL_Tx_VAL);
+   writel(0, base + OWL_Tx_CMP);
+}
+
+static u64 notrace owl_timer_sched_read(void)
+{
+   return (u64)readl(owl_timer_get_base(0) + OWL_Tx_VAL);
+}
+
+static int owl_timer_set_state_shutdown(struct clock_event_device *evt)
+{
+   writel(0, owl_timer_get_base(0) + OWL_Tx_CTL);
+
+   return 0;
+}
+
+static int owl_timer_set_state_oneshot(struct clock_event_device *evt)
+{
+   owl_timer_reset(1);
+
+   return 0;
+}
+
+static int owl_timer_tick_resume(struct clock_event_device *evt)
+{
+   return 0;
+}
+
+static int owl_timer_set_next_event(unsigned long evt,
+   struct clock_event_device *ev)
+{
+   void __iomem *base = owl_timer_get_base(1);
+
+   writel(0, base + OWL_Tx_CTL);
+
+   writel(0, base + OWL_Tx_VAL);
+   writel(evt, base + OWL_Tx_CMP);
+
+   writel(OWL_Tx_CTL_EN | OWL_Tx_CTL_INTEN, base + OWL_Tx_CTL);
+
+   return 0;
+}
+
+static struct clock_event_device owl_clockevent = {
+   .name   = "owl_tick",
+   .rating = 200,
+   .features   = CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_DYNIRQ,
+   .set_state_shutdown = 

[PATCH v3 07/25] ARM64: Prepare Actions Semi S900

[Andreas Färber]

Add ARCH_ACTIONS.

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Selected clocksource driver
 
 v1 -> v2:
 * Renamed ARCH_OWL to ARCH_ACTION (Arnd)
 
 arch/arm64/Kconfig.platforms | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 129cc5a..761b31f 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -1,5 +1,11 @@
 menu "Platform selection"
 
+config ARCH_ACTIONS
+   bool "Actions Semi Platforms"
+   select OWL_TIMER
+   help
+ This enables support for the Actions Semiconductor S900 SoC family.
+
 config ARCH_SUNXI
bool "Allwinner sunxi 64-bit SoC Family"
select GENERIC_IRQ_CHIP
-- 
2.10.2

Re: [PATCH 3/4] drm/bridge: Drivers for megachips-stdpxxxx-ge-b850v3-fw (LVDS-DP++)

[Archit Taneja]

On 02/27/2017 07:10 PM, Peter Senna Tschudin wrote:

On Wed, Feb 01, 2017 at 04:17:21PM +0530, Archit Taneja wrote:
Hi Archit,


Hi,

Some minor comments:


Thank you for the review!



On 01/28/2017 07:51 PM, Peter Senna Tschudin wrote:

The video processing pipeline on the second output on the GE B850v3:

  Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output

Each bridge has a dedicated flash containing firmware for supporting the
custom design. The result is that in this design neither the STDP4028
nor the STDP2690 behave as the stock bridges would. The compatible
strings include the suffix "-ge-b850v3-fw" to make it clear that the
driver is for the bridges with the firmware which is specific for the GE
B850v3.

The driver is powerless to control the video processing pipeline, as the
two bridges behaves as a single one. The driver is only needed for
telling the host about EDID / HPD, and for giving the host powers to ack
interrupts.

This driver adds one i2c_device for each bridge, but only one
drm_bridge. This design allows the creation of a functional connector
that is capable of reading EDID from the STDP2690 while handling
interrupts on the STDP4028.

Cc: Laurent Pinchart 
Cc: Martyn Welch 
Cc: Martin Donnelly 
Cc: Daniel Vetter 
Cc: Enric Balletbo i Serra 
Cc: Philipp Zabel 
Cc: Rob Herring 
Cc: Fabio Estevam 
Cc: David Airlie 
Cc: Thierry Reding 
Cc: Thierry Reding 
Cc: Archit Taneja 
Cc: Enric Balletbo 
Signed-off-by: Peter Senna Tschudin 
---
 drivers/gpu/drm/bridge/Kconfig |  11 +
 drivers/gpu/drm/bridge/Makefile|   1 +
 .../drm/bridge/megachips-stdp-ge-b850v3-fw.c   | 408 +
 3 files changed, 420 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/megachips-stdp-ge-b850v3-fw.c

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index eb8688e..4a937f1 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -48,6 +48,17 @@ config DRM_DW_HDMI_I2S_AUDIO
  Support the I2S Audio interface which is part of the Synopsis
  Designware HDMI block.

+config DRM_MEGACHIPS_STDP_GE_B850V3_FW
+   tristate "MegaChips stdp4028-ge-b850v3-fw and stdp2690-ge-b850v3-fw"
+   depends on OF
+   select DRM_KMS_HELPER
+   select DRM_PANEL
+   ---help---
+  This is a driver for the display bridges of
+  GE B850v3 that convert dual channel LVDS
+  to DP++. This is used with the i.MX6 imx-ldb
+  driver. You are likely to say N here.
+
 config DRM_NXP_PTN3460
tristate "NXP PTN3460 DP/LVDS bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 2e83a785..af0b7cc 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o
 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
 obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
+obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) += 
megachips-stdp-ge-b850v3-fw.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
 obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o
diff --git a/drivers/gpu/drm/bridge/megachips-stdp-ge-b850v3-fw.c 
b/drivers/gpu/drm/bridge/megachips-stdp-ge-b850v3-fw.c
new file mode 100644
index 000..13de03cf
--- /dev/null
+++ b/drivers/gpu/drm/bridge/megachips-stdp-ge-b850v3-fw.c
@@ -0,0 +1,408 @@
+/*
+ * Driver for MegaChips STDP4028 with GE B850v3 firmware (LVDS-DP)
+ * Driver for MegaChips STDP2690 with GE B850v3 firmware (DP-DP++)
+
+ * Copyright (c) 2016, Collabora Ltd.
+ * Copyright (c) 2016, General Electric Company


2017?


Fixed.




+
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+
+ * This driver creates a drm_bridge and a drm_connector for the LVDS to DP++
+ * display bridge of the GE B850v3. There are two physical bridges on the video
+ * signal pipeline: a STDP4028(LVDS to DP) and a STDP2690(DP to DP++). The
+ * physical bridges are automatically configured by the input video signal, and
+ * the driver has no access to the video processing pipeline. The driver is
+ * only needed to read EDID from the STDP2690 and to handle HPD events from the
+ * STDP4028. The driver communicates with both bridges over i2c. The video
+ 

[PATCH v3 03/25] dt-bindings: timer: Document Owl timer

[Andreas Färber]

The Actions Semi S500 SoC contains a timer block with two 2 Hz and two
32-bit timers. The S900 SoC timer block has four 32-bit timers.

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Adopted interrupt-names
 * Changed compatible for S500
 * Added S900 compatible and interrupt names
 
 v2: new
 
 .../devicetree/bindings/timer/actions,owl-timer.txt  | 20 
 1 file changed, 20 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/timer/actions,owl-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/actions,owl-timer.txt 
b/Documentation/devicetree/bindings/timer/actions,owl-timer.txt
new file mode 100644
index 000..5b4834d
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/actions,owl-timer.txt
@@ -0,0 +1,20 @@
+Actions Semi Owl Timer
+
+Required properties:
+- compatible  :  "actions,s500-timer" for S500
+ "actions,s900-timer" for S900
+- reg :  Offset and length of the register set for the device.
+- interrupts  :  Should contain the interrupts.
+- interrupt-names :  Valid names are: "2Hz0", "2Hz1",
+  "Timer0", "Timer1", "Timer2", "Timer3"
+ See ../resource-names.txt
+
+Example:
+
+   timer@b0168000 {
+   compatible = "actions,s500-timer";
+   reg = <0xb0168000 0x100>;
+   interrupts = ,
+;
+   interrupt-names = "Timer0", "Timer1";
+   };
-- 
2.10.2

[PATCH v3 14/25] ARM64: dts: Add Actions Semi S900 and Bubblegum-96

[Andreas Färber]

UART0/1/4/6 interrupts are guesses.

Cc: 96boa...@ucrobotics.com
Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Added remaining UART nodes -- some interrupts are guesses
 * Added timer node -- only TIMER1 interrupt known
 
 v1 -> v2:
 * Reworded subject
 * Added memory@0 node for Bubblegum-96 (Mark)
 * Filled in reserved-memory sub-node for Bubblegum-96 (Mark)
 * Added arm-pmu interrupt-affinity property (Mark)
 * Changed second GIC reg size 0x1000 -> 0x2000 for Bubblegum-96 (Mark)
 * Updated ARCH_OWL to ARCH_ACTIONS (Arnd)
 * Renamed s900-bubblegum96.dts to s900-bubblegum-96.dts
 * Adopted "actions" vendor prefix
 * Dropped irq.h include
 * Adopted SPDX-License-Identifier (Rob)
 
 arch/arm64/boot/dts/Makefile  |   1 +
 arch/arm64/boot/dts/actions/Makefile  |   5 +
 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts |  35 +
 arch/arm64/boot/dts/actions/s900.dtsi | 164 ++
 4 files changed, 205 insertions(+)
 create mode 100644 arch/arm64/boot/dts/actions/Makefile
 create mode 100644 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
 create mode 100644 arch/arm64/boot/dts/actions/s900.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 080232b..d1a6b0a 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dts-dirs += actions
 dts-dirs += al
 dts-dirs += allwinner
 dts-dirs += altera
diff --git a/arch/arm64/boot/dts/actions/Makefile 
b/arch/arm64/boot/dts/actions/Makefile
new file mode 100644
index 000..62922d6
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb
+
+always := $(dtb-y)
+subdir-y   := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts 
b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
new file mode 100644
index 000..a0c3484
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include "s900.dtsi"
+
+/ {
+   compatible = "ucrobotics,bubblegum-96", "actions,s900";
+   model = "Bubblegum-96";
+
+   aliases {
+   serial5 = 
+   };
+
+   chosen {
+   stdout-path = "serial5:115200n8";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x8000>;
+   };
+};
+
+ {
+   clocks = <>;
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm64/boot/dts/actions/s900.dtsi 
b/arch/arm64/boot/dts/actions/s900.dtsi
new file mode 100644
index 000..6048651
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/s900.dtsi
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include 
+
+/ {
+   compatible = "actions,s900";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <2>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x0>;
+   enable-method = "psci";
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x1>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x2>;
+   enable-method = "psci";
+   };
+
+   cpu3: cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x3>;
+   enable-method = "psci";
+   };
+   };
+
+   reserved-memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   secmon@1f00 {
+   reg = <0x0 0x1f00 0x0 0x100>;
+   no-map;
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   arm-pmu {
+   compatible = "arm,cortex-a53-pmu";
+   interrupts = ,
+,
+,
+;
+   interrupt-affinity = <>, <>, <>, <>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupts = ,
+,
+,
+ 

[PATCH v3 03/25] dt-bindings: timer: Document Owl timer

[Andreas Färber]

The Actions Semi S500 SoC contains a timer block with two 2 Hz and two
32-bit timers. The S900 SoC timer block has four 32-bit timers.

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Adopted interrupt-names
 * Changed compatible for S500
 * Added S900 compatible and interrupt names
 
 v2: new
 
 .../devicetree/bindings/timer/actions,owl-timer.txt  | 20 
 1 file changed, 20 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/timer/actions,owl-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/actions,owl-timer.txt 
b/Documentation/devicetree/bindings/timer/actions,owl-timer.txt
new file mode 100644
index 000..5b4834d
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/actions,owl-timer.txt
@@ -0,0 +1,20 @@
+Actions Semi Owl Timer
+
+Required properties:
+- compatible  :  "actions,s500-timer" for S500
+ "actions,s900-timer" for S900
+- reg :  Offset and length of the register set for the device.
+- interrupts  :  Should contain the interrupts.
+- interrupt-names :  Valid names are: "2Hz0", "2Hz1",
+  "Timer0", "Timer1", "Timer2", "Timer3"
+ See ../resource-names.txt
+
+Example:
+
+   timer@b0168000 {
+   compatible = "actions,s500-timer";
+   reg = <0xb0168000 0x100>;
+   interrupts = ,
+;
+   interrupt-names = "Timer0", "Timer1";
+   };
-- 
2.10.2

[PATCH v3 14/25] ARM64: dts: Add Actions Semi S900 and Bubblegum-96

[Andreas Färber]

UART0/1/4/6 interrupts are guesses.

Cc: 96boa...@ucrobotics.com
Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Added remaining UART nodes -- some interrupts are guesses
 * Added timer node -- only TIMER1 interrupt known
 
 v1 -> v2:
 * Reworded subject
 * Added memory@0 node for Bubblegum-96 (Mark)
 * Filled in reserved-memory sub-node for Bubblegum-96 (Mark)
 * Added arm-pmu interrupt-affinity property (Mark)
 * Changed second GIC reg size 0x1000 -> 0x2000 for Bubblegum-96 (Mark)
 * Updated ARCH_OWL to ARCH_ACTIONS (Arnd)
 * Renamed s900-bubblegum96.dts to s900-bubblegum-96.dts
 * Adopted "actions" vendor prefix
 * Dropped irq.h include
 * Adopted SPDX-License-Identifier (Rob)
 
 arch/arm64/boot/dts/Makefile  |   1 +
 arch/arm64/boot/dts/actions/Makefile  |   5 +
 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts |  35 +
 arch/arm64/boot/dts/actions/s900.dtsi | 164 ++
 4 files changed, 205 insertions(+)
 create mode 100644 arch/arm64/boot/dts/actions/Makefile
 create mode 100644 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
 create mode 100644 arch/arm64/boot/dts/actions/s900.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 080232b..d1a6b0a 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dts-dirs += actions
 dts-dirs += al
 dts-dirs += allwinner
 dts-dirs += altera
diff --git a/arch/arm64/boot/dts/actions/Makefile 
b/arch/arm64/boot/dts/actions/Makefile
new file mode 100644
index 000..62922d6
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb
+
+always := $(dtb-y)
+subdir-y   := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts 
b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
new file mode 100644
index 000..a0c3484
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include "s900.dtsi"
+
+/ {
+   compatible = "ucrobotics,bubblegum-96", "actions,s900";
+   model = "Bubblegum-96";
+
+   aliases {
+   serial5 = 
+   };
+
+   chosen {
+   stdout-path = "serial5:115200n8";
+   };
+
+   memory@0 {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x8000>;
+   };
+};
+
+ {
+   clocks = <>;
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm64/boot/dts/actions/s900.dtsi 
b/arch/arm64/boot/dts/actions/s900.dtsi
new file mode 100644
index 000..6048651
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/s900.dtsi
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include 
+
+/ {
+   compatible = "actions,s900";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <2>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x0>;
+   enable-method = "psci";
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x1>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x2>;
+   enable-method = "psci";
+   };
+
+   cpu3: cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x3>;
+   enable-method = "psci";
+   };
+   };
+
+   reserved-memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   secmon@1f00 {
+   reg = <0x0 0x1f00 0x0 0x100>;
+   no-map;
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   arm-pmu {
+   compatible = "arm,cortex-a53-pmu";
+   interrupts = ,
+,
+,
+;
+   interrupt-affinity = <>, <>, <>, <>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupts = ,
+,
+,
+   

[PATCH v3 10/25] Documentation: kernel-parameters: Document owl earlycon

[Andreas Färber]

Signed-off-by: Andreas Färber 
---
 v1 -> v2 -> v3: unchanged
 
 Documentation/admin-guide/kernel-parameters.txt | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/admin-guide/kernel-parameters.txt 
b/Documentation/admin-guide/kernel-parameters.txt
index 986e443..f48a142 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -943,6 +943,12 @@
must already be setup and configured. Options are not
yet supported.
 
+   owl,
+   Start an early, polled-mode console on an Owl serial
+   port at the specified address. The serial port must
+   already be setup and configured. Options are not yet
+   supported.
+
smh Use ARM semihosting calls for early console.
 
s3c2410,
-- 
2.10.2

[PATCH v3 16/25] tty: serial: owl: Implement console driver

[Andreas Färber]

Implement serial console driver to complement earlycon.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Adopted BIT() macro
 * Implemented baudrate setting
 
 v2: new
 
 drivers/tty/serial/Kconfig   |   4 +-
 drivers/tty/serial/owl-uart.c| 591 ++-
 include/uapi/linux/serial_core.h |   3 +
 3 files changed, 595 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index e145822..ef232ac 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1678,7 +1678,7 @@ config SERIAL_MVEBU_CONSOLE
  Otherwise, say 'N'.
 
 config SERIAL_OWL
-   bool "Actions Semi Owl serial port support"
+   tristate "Actions Semi Owl serial port support"
depends on ARCH_ACTIONS || COMPILE_TEST
select SERIAL_CORE
help
@@ -1694,7 +1694,7 @@ config SERIAL_OWL_CONSOLE
default y
help
  Say 'Y' here if you wish to use Actions Semiconductor S500/S900 UART
- as the system console. Only earlycon is implemented currently.
+ as the system console.
 
 endmenu
 
diff --git a/drivers/tty/serial/owl-uart.c b/drivers/tty/serial/owl-uart.c
index 1b80087..14e0324 100644
--- a/drivers/tty/serial/owl-uart.c
+++ b/drivers/tty/serial/owl-uart.c
@@ -20,6 +20,7 @@
  * along with this program. If not, see .
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -28,22 +29,59 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+
+#define OWL_UART_PORT_NUM 7
+#define OWL_UART_DEV_NAME "ttyOWL"
 
 #define OWL_UART_CTL   0x000
+#define OWL_UART_RXDAT 0x004
 #define OWL_UART_TXDAT 0x008
 #define OWL_UART_STAT  0x00c
 
+#define OWL_UART_CTL_DWLS_MASK (0x3 << 0)
+#define OWL_UART_CTL_DWLS_5BITS(0x0 << 0)
+#define OWL_UART_CTL_DWLS_6BITS(0x1 << 0)
+#define OWL_UART_CTL_DWLS_7BITS(0x2 << 0)
+#define OWL_UART_CTL_DWLS_8BITS(0x3 << 0)
+#define OWL_UART_CTL_STPS_2BITSBIT(2)
+#define OWL_UART_CTL_PRS_MASK  (0x7 << 4)
+#define OWL_UART_CTL_PRS_NONE  (0x0 << 4)
+#define OWL_UART_CTL_PRS_ODD   (0x4 << 4)
+#define OWL_UART_CTL_PRS_MARK  (0x5 << 4)
+#define OWL_UART_CTL_PRS_EVEN  (0x6 << 4)
+#define OWL_UART_CTL_PRS_SPACE (0x7 << 4)
+#define OWL_UART_CTL_AFE   BIT(12)
 #define OWL_UART_CTL_TRFS_TX   BIT(14)
 #define OWL_UART_CTL_ENBIT(15)
+#define OWL_UART_CTL_RXDE  BIT(16)
+#define OWL_UART_CTL_TXDE  BIT(17)
 #define OWL_UART_CTL_RXIE  BIT(18)
 #define OWL_UART_CTL_TXIE  BIT(19)
 
 #define OWL_UART_STAT_RIP  BIT(0)
 #define OWL_UART_STAT_TIP  BIT(1)
+#define OWL_UART_STAT_RXER BIT(2)
+#define OWL_UART_STAT_TFER BIT(3)
+#define OWL_UART_STAT_RXST BIT(4)
+#define OWL_UART_STAT_RFEM BIT(5)
 #define OWL_UART_STAT_TFFU BIT(6)
+#define OWL_UART_STAT_TFES BIT(10)
 #define OWL_UART_STAT_TRFL_MASK(0x1f << 11)
 #define OWL_UART_STAT_UTBB BIT(17)
 
+static struct uart_driver owl_uart_driver;
+
+struct owl_uart_port {
+   struct uart_port port;
+   struct clk *clk;
+};
+
+#define to_owl_uart_port(prt) container_of(prt, struct owl_uart_port, prt)
+
+static struct owl_uart_port *owl_uart_ports[OWL_UART_PORT_NUM];
+
 static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned 
int off)
 {
writel(val, port->membase + off);
@@ -54,6 +92,380 @@ static inline u32 owl_uart_read(struct uart_port *port, 
unsigned int off)
return readl(port->membase + off);
 }
 
+static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}
+
+static unsigned int owl_uart_get_mctrl(struct uart_port *port)
+{
+   return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
+}
+
+static unsigned int owl_uart_tx_empty(struct uart_port *port)
+{
+   unsigned long flags;
+   u32 val;
+   unsigned int ret;
+
+   spin_lock_irqsave(>lock, flags);
+
+   val = owl_uart_read(port, OWL_UART_STAT);
+   ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0;
+
+   spin_unlock_irqrestore(>lock, flags);
+
+   return ret;
+}
+
+static void owl_uart_stop_rx(struct uart_port *port)
+{
+   u32 val;
+
+   val = owl_uart_read(port, OWL_UART_CTL);
+   val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE);
+   owl_uart_write(port, val, OWL_UART_CTL);
+
+   val = owl_uart_read(port, OWL_UART_STAT);
+   val |= OWL_UART_STAT_RIP;
+   owl_uart_write(port, val, OWL_UART_STAT);
+}
+
+static void owl_uart_stop_tx(struct uart_port *port)
+{
+   u32 val;
+
+   val = owl_uart_read(port, OWL_UART_CTL);
+   val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE);
+   owl_uart_write(port, val, OWL_UART_CTL);
+
+   val = 

[PATCH v3 10/25] Documentation: kernel-parameters: Document owl earlycon

[Andreas Färber]

Signed-off-by: Andreas Färber 
---
 v1 -> v2 -> v3: unchanged
 
 Documentation/admin-guide/kernel-parameters.txt | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/admin-guide/kernel-parameters.txt 
b/Documentation/admin-guide/kernel-parameters.txt
index 986e443..f48a142 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -943,6 +943,12 @@
must already be setup and configured. Options are not
yet supported.
 
+   owl,
+   Start an early, polled-mode console on an Owl serial
+   port at the specified address. The serial port must
+   already be setup and configured. Options are not yet
+   supported.
+
smh Use ARM semihosting calls for early console.
 
s3c2410,
-- 
2.10.2

[PATCH v3 16/25] tty: serial: owl: Implement console driver

[Andreas Färber]

Implement serial console driver to complement earlycon.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber 
---
 v2 -> v3:
 * Adopted BIT() macro
 * Implemented baudrate setting
 
 v2: new
 
 drivers/tty/serial/Kconfig   |   4 +-
 drivers/tty/serial/owl-uart.c| 591 ++-
 include/uapi/linux/serial_core.h |   3 +
 3 files changed, 595 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index e145822..ef232ac 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1678,7 +1678,7 @@ config SERIAL_MVEBU_CONSOLE
  Otherwise, say 'N'.
 
 config SERIAL_OWL
-   bool "Actions Semi Owl serial port support"
+   tristate "Actions Semi Owl serial port support"
depends on ARCH_ACTIONS || COMPILE_TEST
select SERIAL_CORE
help
@@ -1694,7 +1694,7 @@ config SERIAL_OWL_CONSOLE
default y
help
  Say 'Y' here if you wish to use Actions Semiconductor S500/S900 UART
- as the system console. Only earlycon is implemented currently.
+ as the system console.
 
 endmenu
 
diff --git a/drivers/tty/serial/owl-uart.c b/drivers/tty/serial/owl-uart.c
index 1b80087..14e0324 100644
--- a/drivers/tty/serial/owl-uart.c
+++ b/drivers/tty/serial/owl-uart.c
@@ -20,6 +20,7 @@
  * along with this program. If not, see .
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -28,22 +29,59 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+
+#define OWL_UART_PORT_NUM 7
+#define OWL_UART_DEV_NAME "ttyOWL"
 
 #define OWL_UART_CTL   0x000
+#define OWL_UART_RXDAT 0x004
 #define OWL_UART_TXDAT 0x008
 #define OWL_UART_STAT  0x00c
 
+#define OWL_UART_CTL_DWLS_MASK (0x3 << 0)
+#define OWL_UART_CTL_DWLS_5BITS(0x0 << 0)
+#define OWL_UART_CTL_DWLS_6BITS(0x1 << 0)
+#define OWL_UART_CTL_DWLS_7BITS(0x2 << 0)
+#define OWL_UART_CTL_DWLS_8BITS(0x3 << 0)
+#define OWL_UART_CTL_STPS_2BITSBIT(2)
+#define OWL_UART_CTL_PRS_MASK  (0x7 << 4)
+#define OWL_UART_CTL_PRS_NONE  (0x0 << 4)
+#define OWL_UART_CTL_PRS_ODD   (0x4 << 4)
+#define OWL_UART_CTL_PRS_MARK  (0x5 << 4)
+#define OWL_UART_CTL_PRS_EVEN  (0x6 << 4)
+#define OWL_UART_CTL_PRS_SPACE (0x7 << 4)
+#define OWL_UART_CTL_AFE   BIT(12)
 #define OWL_UART_CTL_TRFS_TX   BIT(14)
 #define OWL_UART_CTL_ENBIT(15)
+#define OWL_UART_CTL_RXDE  BIT(16)
+#define OWL_UART_CTL_TXDE  BIT(17)
 #define OWL_UART_CTL_RXIE  BIT(18)
 #define OWL_UART_CTL_TXIE  BIT(19)
 
 #define OWL_UART_STAT_RIP  BIT(0)
 #define OWL_UART_STAT_TIP  BIT(1)
+#define OWL_UART_STAT_RXER BIT(2)
+#define OWL_UART_STAT_TFER BIT(3)
+#define OWL_UART_STAT_RXST BIT(4)
+#define OWL_UART_STAT_RFEM BIT(5)
 #define OWL_UART_STAT_TFFU BIT(6)
+#define OWL_UART_STAT_TFES BIT(10)
 #define OWL_UART_STAT_TRFL_MASK(0x1f << 11)
 #define OWL_UART_STAT_UTBB BIT(17)
 
+static struct uart_driver owl_uart_driver;
+
+struct owl_uart_port {
+   struct uart_port port;
+   struct clk *clk;
+};
+
+#define to_owl_uart_port(prt) container_of(prt, struct owl_uart_port, prt)
+
+static struct owl_uart_port *owl_uart_ports[OWL_UART_PORT_NUM];
+
 static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned 
int off)
 {
writel(val, port->membase + off);
@@ -54,6 +92,380 @@ static inline u32 owl_uart_read(struct uart_port *port, 
unsigned int off)
return readl(port->membase + off);
 }
 
+static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}
+
+static unsigned int owl_uart_get_mctrl(struct uart_port *port)
+{
+   return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
+}
+
+static unsigned int owl_uart_tx_empty(struct uart_port *port)
+{
+   unsigned long flags;
+   u32 val;
+   unsigned int ret;
+
+   spin_lock_irqsave(>lock, flags);
+
+   val = owl_uart_read(port, OWL_UART_STAT);
+   ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0;
+
+   spin_unlock_irqrestore(>lock, flags);
+
+   return ret;
+}
+
+static void owl_uart_stop_rx(struct uart_port *port)
+{
+   u32 val;
+
+   val = owl_uart_read(port, OWL_UART_CTL);
+   val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE);
+   owl_uart_write(port, val, OWL_UART_CTL);
+
+   val = owl_uart_read(port, OWL_UART_STAT);
+   val |= OWL_UART_STAT_RIP;
+   owl_uart_write(port, val, OWL_UART_STAT);
+}
+
+static void owl_uart_stop_tx(struct uart_port *port)
+{
+   u32 val;
+
+   val = owl_uart_read(port, OWL_UART_CTL);
+   val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE);
+   owl_uart_write(port, val, OWL_UART_CTL);
+
+   val = owl_uart_read(port, 

[PATCH 2/2] mfd: add TI LMU driver

[Milo Kim]

TI LMU (Lighting Management Unit) driver supports lighting devices below.

  LM3532, LM3631, LM3632, LM3633, LM3695 and LM3697.

LMU devices have common features.
  - I2C interface for accessing device registers
  - Hardware enable pin control
  - Backlight brightness control
  - Notifier for hardware fault monitoring
  - Regulators for LCD display bias

It contains fault monitor, backlight, LED and regulator driver.

LMU fault monitor
-
  LM3633 and LM3697 provide hardware monitoring feature.
  It enables open or short circuit detection.
  After monitoring is done, each device should be re-initialized.
  Notifier is used for this case.
  Separate patch for 'ti-lmu-fault-monitor' will be sent later.

Backlight
-
  It's handled by TI LMU backlight consolidated driver and
  chip dependent data. Separate patchset will be sent later.

LED indicator
-
  LM3633 has 6 indicator LEDs. Programmable dimming pattern is also
  supported. Separate patch for 'leds-lm3633' will be sent later.

Regulator
-
  LM3631 has 5 regulators for the display bias.
  LM3632 supports 3 regulators. One consolidated driver enables it.
  The lm363x regulator driver is already upstreamed.

Acked-by: Lee Jones 
Signed-off-by: Milo Kim 
---
 drivers/mfd/Kconfig |  12 ++
 drivers/mfd/Makefile|   2 +
 drivers/mfd/ti-lmu.c| 259 +
 include/linux/mfd/ti-lmu-register.h | 280 
 include/linux/mfd/ti-lmu.h  |  87 +++
 5 files changed, 640 insertions(+)
 create mode 100644 drivers/mfd/ti-lmu.c
 create mode 100644 include/linux/mfd/ti-lmu-register.h
 create mode 100644 include/linux/mfd/ti-lmu.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 55ecdfb74d31..75e749c1ff1a 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1164,6 +1164,18 @@ config MFD_LP8788
  TI LP8788 PMU supports regulators, battery charger, RTC,
  ADC, backlight driver and current sinks.
 
+config MFD_TI_LMU
+   tristate "TI Lighting Management Unit driver"
+   depends on I2C
+   select MFD_CORE
+   select REGMAP_I2C
+   help
+ Say yes here to enable support for TI LMU chips.
+
+ TI LMU MFD supports LM3532, LM3631, LM3632, LM3633, LM3695 and LM3697.
+ It consists of backlight, LED and regulator driver.
+ It provides consistent device controls for lighting functions.
+
 config MFD_OMAP_USB_HOST
bool "TI OMAP USBHS core and TLL driver"
depends on USB_EHCI_HCD_OMAP || USB_OHCI_HCD_OMAP3
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 31ce07611a6f..dac78a0f23a7 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -125,6 +125,8 @@ obj-$(CONFIG_MFD_AXP20X_RSB)+= axp20x-rsb.o
 obj-$(CONFIG_MFD_LP3943)   += lp3943.o
 obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
 
+obj-$(CONFIG_MFD_TI_LMU)   += ti-lmu.o
+
 da9055-objs:= da9055-core.o da9055-i2c.o
 obj-$(CONFIG_MFD_DA9055)   += da9055.o
 obj-$(CONFIG_MFD_DA9062)   += da9062-core.o
diff --git a/drivers/mfd/ti-lmu.c b/drivers/mfd/ti-lmu.c
new file mode 100644
index ..cfb411cde51c
--- /dev/null
+++ b/drivers/mfd/ti-lmu.c
@@ -0,0 +1,259 @@
+/*
+ * TI LMU (Lighting Management Unit) Core Driver
+ *
+ * Copyright 2017 Texas Instruments
+ *
+ * Author: Milo Kim 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct ti_lmu_data {
+   struct mfd_cell *cells;
+   int num_cells;
+   unsigned int max_register;
+};
+
+static int ti_lmu_enable_hw(struct ti_lmu *lmu, enum ti_lmu_id id)
+{
+   int ret;
+
+   if (gpio_is_valid(lmu->en_gpio)) {
+   ret = devm_gpio_request_one(lmu->dev, lmu->en_gpio,
+   GPIOF_OUT_INIT_HIGH, "lmu_hwen");
+   if (ret) {
+   dev_err(lmu->dev, "Can not request enable GPIO: %d\n",
+   ret);
+   return ret;
+   }
+   }
+
+   /* Delay about 1ms after HW enable pin control */
+   usleep_range(1000, 1500);
+
+   /* LM3631 has additional power up sequence - enable LCD_EN bit. */
+   if (id == LM3631) {
+   return regmap_update_bits(lmu->regmap, LM3631_REG_DEVCTRL,
+ LM3631_LCD_EN_MASK,
+ LM3631_LCD_EN_MASK);
+   }
+
+   return 0;
+}
+
+static void ti_lmu_disable_hw(struct ti_lmu *lmu)
+{
+   if (gpio_is_valid(lmu->en_gpio))
+  

[PATCH 2/2] mfd: add TI LMU driver

[Milo Kim]

TI LMU (Lighting Management Unit) driver supports lighting devices below.

  LM3532, LM3631, LM3632, LM3633, LM3695 and LM3697.

LMU devices have common features.
  - I2C interface for accessing device registers
  - Hardware enable pin control
  - Backlight brightness control
  - Notifier for hardware fault monitoring
  - Regulators for LCD display bias

It contains fault monitor, backlight, LED and regulator driver.

LMU fault monitor
-
  LM3633 and LM3697 provide hardware monitoring feature.
  It enables open or short circuit detection.
  After monitoring is done, each device should be re-initialized.
  Notifier is used for this case.
  Separate patch for 'ti-lmu-fault-monitor' will be sent later.

Backlight
-
  It's handled by TI LMU backlight consolidated driver and
  chip dependent data. Separate patchset will be sent later.

LED indicator
-
  LM3633 has 6 indicator LEDs. Programmable dimming pattern is also
  supported. Separate patch for 'leds-lm3633' will be sent later.

Regulator
-
  LM3631 has 5 regulators for the display bias.
  LM3632 supports 3 regulators. One consolidated driver enables it.
  The lm363x regulator driver is already upstreamed.

Acked-by: Lee Jones 
Signed-off-by: Milo Kim 
---
 drivers/mfd/Kconfig |  12 ++
 drivers/mfd/Makefile|   2 +
 drivers/mfd/ti-lmu.c| 259 +
 include/linux/mfd/ti-lmu-register.h | 280 
 include/linux/mfd/ti-lmu.h  |  87 +++
 5 files changed, 640 insertions(+)
 create mode 100644 drivers/mfd/ti-lmu.c
 create mode 100644 include/linux/mfd/ti-lmu-register.h
 create mode 100644 include/linux/mfd/ti-lmu.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 55ecdfb74d31..75e749c1ff1a 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1164,6 +1164,18 @@ config MFD_LP8788
  TI LP8788 PMU supports regulators, battery charger, RTC,
  ADC, backlight driver and current sinks.
 
+config MFD_TI_LMU
+   tristate "TI Lighting Management Unit driver"
+   depends on I2C
+   select MFD_CORE
+   select REGMAP_I2C
+   help
+ Say yes here to enable support for TI LMU chips.
+
+ TI LMU MFD supports LM3532, LM3631, LM3632, LM3633, LM3695 and LM3697.
+ It consists of backlight, LED and regulator driver.
+ It provides consistent device controls for lighting functions.
+
 config MFD_OMAP_USB_HOST
bool "TI OMAP USBHS core and TLL driver"
depends on USB_EHCI_HCD_OMAP || USB_OHCI_HCD_OMAP3
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 31ce07611a6f..dac78a0f23a7 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -125,6 +125,8 @@ obj-$(CONFIG_MFD_AXP20X_RSB)+= axp20x-rsb.o
 obj-$(CONFIG_MFD_LP3943)   += lp3943.o
 obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
 
+obj-$(CONFIG_MFD_TI_LMU)   += ti-lmu.o
+
 da9055-objs:= da9055-core.o da9055-i2c.o
 obj-$(CONFIG_MFD_DA9055)   += da9055.o
 obj-$(CONFIG_MFD_DA9062)   += da9062-core.o
diff --git a/drivers/mfd/ti-lmu.c b/drivers/mfd/ti-lmu.c
new file mode 100644
index ..cfb411cde51c
--- /dev/null
+++ b/drivers/mfd/ti-lmu.c
@@ -0,0 +1,259 @@
+/*
+ * TI LMU (Lighting Management Unit) Core Driver
+ *
+ * Copyright 2017 Texas Instruments
+ *
+ * Author: Milo Kim 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct ti_lmu_data {
+   struct mfd_cell *cells;
+   int num_cells;
+   unsigned int max_register;
+};
+
+static int ti_lmu_enable_hw(struct ti_lmu *lmu, enum ti_lmu_id id)
+{
+   int ret;
+
+   if (gpio_is_valid(lmu->en_gpio)) {
+   ret = devm_gpio_request_one(lmu->dev, lmu->en_gpio,
+   GPIOF_OUT_INIT_HIGH, "lmu_hwen");
+   if (ret) {
+   dev_err(lmu->dev, "Can not request enable GPIO: %d\n",
+   ret);
+   return ret;
+   }
+   }
+
+   /* Delay about 1ms after HW enable pin control */
+   usleep_range(1000, 1500);
+
+   /* LM3631 has additional power up sequence - enable LCD_EN bit. */
+   if (id == LM3631) {
+   return regmap_update_bits(lmu->regmap, LM3631_REG_DEVCTRL,
+ LM3631_LCD_EN_MASK,
+ LM3631_LCD_EN_MASK);
+   }
+
+   return 0;
+}
+
+static void ti_lmu_disable_hw(struct ti_lmu *lmu)
+{
+   if (gpio_is_valid(lmu->en_gpio))
+   gpio_set_value(lmu->en_gpio, 0);
+}
+
+static 

[PATCH 1/2] Documentation: dt-bindings: mfd: add TI LMU device binding information

[Milo Kim]

This patch describes overall binding for TI LMU MFD devices.

Acked-by: Lee Jones 
Acked-by: Rob Herring 
Signed-off-by: Milo Kim 
---
 Documentation/devicetree/bindings/mfd/ti-lmu.txt | 243 +++
 1 file changed, 243 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/ti-lmu.txt

diff --git a/Documentation/devicetree/bindings/mfd/ti-lmu.txt 
b/Documentation/devicetree/bindings/mfd/ti-lmu.txt
new file mode 100644
index ..c885cf89b8ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/ti-lmu.txt
@@ -0,0 +1,243 @@
+TI LMU (Lighting Management Unit) device tree bindings
+
+TI LMU driver supports lighting devices below.
+
+   Name  Child nodes
+  --  -
+  LM3532   Backlight
+  LM3631   Backlight and regulator
+  LM3632   Backlight and regulator
+  LM3633   Backlight, LED and fault monitor
+  LM3695   Backlight
+  LM3697   Backlight and fault monitor
+
+Required properties:
+  - compatible: Should be one of:
+"ti,lm3532"
+"ti,lm3631"
+"ti,lm3632"
+"ti,lm3633"
+"ti,lm3695"
+"ti,lm3697"
+  - reg: I2C slave address.
+ 0x11 for LM3632
+ 0x29 for LM3631
+ 0x36 for LM3633, LM3697
+ 0x38 for LM3532
+ 0x63 for LM3695
+
+Optional property:
+  - enable-gpios: A GPIO specifier for hardware enable pin.
+
+Required node:
+  - backlight: All LMU devices have backlight child nodes.
+   For the properties, please refer to [1].
+
+Optional nodes:
+  - fault-monitor: Hardware fault monitoring driver for LM3633 and LM3697.
+Required properties:
+  - compatible: Should be one of:
+"ti,lm3633-fault-monitor"
+"ti,lm3697-fault-monitor"
+  - leds: LED properties for LM3633. Please refer to [2].
+  - regulators: Regulator properties for LM3631 and LM3632.
+Please refer to [3].
+
+[1] ../leds/backlight/ti-lmu-backlight.txt
+[2] ../leds/leds-lm3633.txt
+[3] ../regulator/lm363x-regulator.txt
+
+lm3532@38 {
+   compatible = "ti,lm3532";
+   reg = <0x38>;
+
+   enable-gpios = < 2 GPIO_ACTIVE_HIGH>;
+
+   backlight {
+   compatible = "ti,lm3532-backlight";
+
+   lcd {
+   led-sources = <0 1 2>;
+   ramp-up-msec = <30>;
+   ramp-down-msec = <0>;
+   };
+   };
+};
+
+lm3631@29 {
+   compatible = "ti,lm3631";
+   reg = <0x29>;
+
+   regulators {
+   compatible = "ti,lm363x-regulator";
+
+   vboost {
+   regulator-name = "lcd_boost";
+   regulator-min-microvolt = <450>;
+   regulator-max-microvolt = <635>;
+   regulator-always-on;
+   };
+
+   vcont {
+   regulator-name = "lcd_vcont";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <330>;
+   };
+
+   voref {
+   regulator-name = "lcd_voref";
+   regulator-min-microvolt = <400>;
+   regulator-max-microvolt = <600>;
+   };
+
+   vpos {
+   regulator-name = "lcd_vpos";
+   regulator-min-microvolt = <400>;
+   regulator-max-microvolt = <600>;
+   regulator-boot-on;
+   };
+
+   vneg {
+   regulator-name = "lcd_vneg";
+   regulator-min-microvolt = <400>;
+   regulator-max-microvolt = <600>;
+   regulator-boot-on;
+   };
+   };
+
+   backlight {
+   compatible = "ti,lm3631-backlight";
+
+   lcd_bl {
+   led-sources = <0 1>;
+   ramp-up-msec = <300>;
+   };
+   };
+};
+
+lm3632@11 {
+   compatible = "ti,lm3632";
+   reg = <0x11>;
+
+   enable-gpios = < 2 GPIO_ACTIVE_HIGH>; /* PC2 */
+
+   regulators {
+   compatible = "ti,lm363x-regulator";
+
+   ti,lcm-en1-gpio = < 0 GPIO_ACTIVE_HIGH>; /* PC0 */
+   ti,lcm-en2-gpio = < 1 GPIO_ACTIVE_HIGH>; /* PC1 */
+
+   vboost {
+   regulator-name = "lcd_boost";
+   regulator-min-microvolt = <450>;
+   regulator-max-microvolt = <640>;
+   regulator-always-on;
+   };
+
+   vpos {
+   regulator-name = "lcd_vpos";
+   regulator-min-microvolt = <400>;
+   regulator-max-microvolt = 

[PATCH 1/2] Documentation: dt-bindings: mfd: add TI LMU device binding information

[Milo Kim]

This patch describes overall binding for TI LMU MFD devices.

Acked-by: Lee Jones 
Acked-by: Rob Herring 
Signed-off-by: Milo Kim 
---
 Documentation/devicetree/bindings/mfd/ti-lmu.txt | 243 +++
 1 file changed, 243 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/ti-lmu.txt

diff --git a/Documentation/devicetree/bindings/mfd/ti-lmu.txt 
b/Documentation/devicetree/bindings/mfd/ti-lmu.txt
new file mode 100644
index ..c885cf89b8ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/ti-lmu.txt
@@ -0,0 +1,243 @@
+TI LMU (Lighting Management Unit) device tree bindings
+
+TI LMU driver supports lighting devices below.
+
+   Name  Child nodes
+  --  -
+  LM3532   Backlight
+  LM3631   Backlight and regulator
+  LM3632   Backlight and regulator
+  LM3633   Backlight, LED and fault monitor
+  LM3695   Backlight
+  LM3697   Backlight and fault monitor
+
+Required properties:
+  - compatible: Should be one of:
+"ti,lm3532"
+"ti,lm3631"
+"ti,lm3632"
+"ti,lm3633"
+"ti,lm3695"
+"ti,lm3697"
+  - reg: I2C slave address.
+ 0x11 for LM3632
+ 0x29 for LM3631
+ 0x36 for LM3633, LM3697
+ 0x38 for LM3532
+ 0x63 for LM3695
+
+Optional property:
+  - enable-gpios: A GPIO specifier for hardware enable pin.
+
+Required node:
+  - backlight: All LMU devices have backlight child nodes.
+   For the properties, please refer to [1].
+
+Optional nodes:
+  - fault-monitor: Hardware fault monitoring driver for LM3633 and LM3697.
+Required properties:
+  - compatible: Should be one of:
+"ti,lm3633-fault-monitor"
+"ti,lm3697-fault-monitor"
+  - leds: LED properties for LM3633. Please refer to [2].
+  - regulators: Regulator properties for LM3631 and LM3632.
+Please refer to [3].
+
+[1] ../leds/backlight/ti-lmu-backlight.txt
+[2] ../leds/leds-lm3633.txt
+[3] ../regulator/lm363x-regulator.txt
+
+lm3532@38 {
+   compatible = "ti,lm3532";
+   reg = <0x38>;
+
+   enable-gpios = < 2 GPIO_ACTIVE_HIGH>;
+
+   backlight {
+   compatible = "ti,lm3532-backlight";
+
+   lcd {
+   led-sources = <0 1 2>;
+   ramp-up-msec = <30>;
+   ramp-down-msec = <0>;
+   };
+   };
+};
+
+lm3631@29 {
+   compatible = "ti,lm3631";
+   reg = <0x29>;
+
+   regulators {
+   compatible = "ti,lm363x-regulator";
+
+   vboost {
+   regulator-name = "lcd_boost";
+   regulator-min-microvolt = <450>;
+   regulator-max-microvolt = <635>;
+   regulator-always-on;
+   };
+
+   vcont {
+   regulator-name = "lcd_vcont";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <330>;
+   };
+
+   voref {
+   regulator-name = "lcd_voref";
+   regulator-min-microvolt = <400>;
+   regulator-max-microvolt = <600>;
+   };
+
+   vpos {
+   regulator-name = "lcd_vpos";
+   regulator-min-microvolt = <400>;
+   regulator-max-microvolt = <600>;
+   regulator-boot-on;
+   };
+
+   vneg {
+   regulator-name = "lcd_vneg";
+   regulator-min-microvolt = <400>;
+   regulator-max-microvolt = <600>;
+   regulator-boot-on;
+   };
+   };
+
+   backlight {
+   compatible = "ti,lm3631-backlight";
+
+   lcd_bl {
+   led-sources = <0 1>;
+   ramp-up-msec = <300>;
+   };
+   };
+};
+
+lm3632@11 {
+   compatible = "ti,lm3632";
+   reg = <0x11>;
+
+   enable-gpios = < 2 GPIO_ACTIVE_HIGH>; /* PC2 */
+
+   regulators {
+   compatible = "ti,lm363x-regulator";
+
+   ti,lcm-en1-gpio = < 0 GPIO_ACTIVE_HIGH>; /* PC0 */
+   ti,lcm-en2-gpio = < 1 GPIO_ACTIVE_HIGH>; /* PC1 */
+
+   vboost {
+   regulator-name = "lcd_boost";
+   regulator-min-microvolt = <450>;
+   regulator-max-microvolt = <640>;
+   regulator-always-on;
+   };
+
+   vpos {
+   regulator-name = "lcd_vpos";
+   regulator-min-microvolt = <400>;
+   regulator-max-microvolt = <600>;
+   };
+
+   vneg {
+   

Re: [PATCH 2/3] thermal: add support for the thermal sensor on Allwinner new SoCs

[Maxime Ripard]

On Tue, Feb 28, 2017 at 03:40:53AM +0800, Icenowy Zheng wrote:
> From: Ondrej Jirman 
> 
> Allwinner SoCs from H3 (including H5, A64, etc) have a new version of
> thermal sensor, and needs a new driver for it.
> 
> Add such a driver.
> 
> Currently only H3 is supported, but other SoCs are easily to be
> supported by adding new formula and set the sensor number.
> 
> Signed-off-by: Ondřej Jirman 
> [Icenowy: extend to support further multiple-sensor SoCs, change commit
>  message]
> Signed-off-by: Icenowy Zheng 

There's no need to create a new driver for that. This can be handled
by the GPADC driver we already have.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


signature.asc
Description: PGP signature

Re: [PATCH 2/3] thermal: add support for the thermal sensor on Allwinner new SoCs

[Maxime Ripard]

On Tue, Feb 28, 2017 at 03:40:53AM +0800, Icenowy Zheng wrote:
> From: Ondrej Jirman 
> 
> Allwinner SoCs from H3 (including H5, A64, etc) have a new version of
> thermal sensor, and needs a new driver for it.
> 
> Add such a driver.
> 
> Currently only H3 is supported, but other SoCs are easily to be
> supported by adding new formula and set the sensor number.
> 
> Signed-off-by: Ondřej Jirman 
> [Icenowy: extend to support further multiple-sensor SoCs, change commit
>  message]
> Signed-off-by: Icenowy Zheng 

There's no need to create a new driver for that. This can be handled
by the GPADC driver we already have.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


signature.asc
Description: PGP signature

[PATCH v3 0/2] Support TI LMU devices

[Milo Kim]

Back from 2015! TI LMU core driver got acked but few more efforts
were required like backlight, LEDs and others.
Recently, Tony Lindgren has been working on porting mainline Linux on 
Droid 4 xt894. One of LMU devices - LM3532 is used for LCD backlight on 
that device. I hope this patch-set would be helpful.

TI Lighting Management Unit drivers support lighting devices below.

 Enable pin  Backlight  HW fault monitoring  LEDs   Regulators
 --  -  ---    
LM3532   o   o   xx x
LM3631   o   o   xx5 regulators
LM3632   o   o   xx3 regulators
LM3633   o   o   oo x
LM3695   o   o   xx x
LM3697   o   o   ox x

This patch-set includes only MFD part. Other subsystem drivers will be sent
separately.

  ti-lmu-backlight: Backlight subsystem
  ti-lmu-fault-monitor: Misc driver
  leds-lm3633: LED subsystem

Updates from v2:
  Submit acked patches to get merged quickly.

Milo Kim (2):
  Documentation: dt-bindings: mfd: add TI LMU device binding information
  mfd: add TI LMU driver

 Documentation/devicetree/bindings/mfd/ti-lmu.txt | 243 
 drivers/mfd/Kconfig  |  12 +
 drivers/mfd/Makefile |   2 +
 drivers/mfd/ti-lmu.c | 259 +
 include/linux/mfd/ti-lmu-register.h  | 280 +++
 include/linux/mfd/ti-lmu.h   |  87 +++
 6 files changed, 883 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/ti-lmu.txt
 create mode 100644 drivers/mfd/ti-lmu.c
 create mode 100644 include/linux/mfd/ti-lmu-register.h
 create mode 100644 include/linux/mfd/ti-lmu.h

-- 
2.11.0

[PATCH v3 0/2] Support TI LMU devices

[Milo Kim]

Back from 2015! TI LMU core driver got acked but few more efforts
were required like backlight, LEDs and others.
Recently, Tony Lindgren has been working on porting mainline Linux on 
Droid 4 xt894. One of LMU devices - LM3532 is used for LCD backlight on 
that device. I hope this patch-set would be helpful.

TI Lighting Management Unit drivers support lighting devices below.

 Enable pin  Backlight  HW fault monitoring  LEDs   Regulators
 --  -  ---    
LM3532   o   o   xx x
LM3631   o   o   xx5 regulators
LM3632   o   o   xx3 regulators
LM3633   o   o   oo x
LM3695   o   o   xx x
LM3697   o   o   ox x

This patch-set includes only MFD part. Other subsystem drivers will be sent
separately.

  ti-lmu-backlight: Backlight subsystem
  ti-lmu-fault-monitor: Misc driver
  leds-lm3633: LED subsystem

Updates from v2:
  Submit acked patches to get merged quickly.

Milo Kim (2):
  Documentation: dt-bindings: mfd: add TI LMU device binding information
  mfd: add TI LMU driver

 Documentation/devicetree/bindings/mfd/ti-lmu.txt | 243 
 drivers/mfd/Kconfig  |  12 +
 drivers/mfd/Makefile |   2 +
 drivers/mfd/ti-lmu.c | 259 +
 include/linux/mfd/ti-lmu-register.h  | 280 +++
 include/linux/mfd/ti-lmu.h   |  87 +++
 6 files changed, 883 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/ti-lmu.txt
 create mode 100644 drivers/mfd/ti-lmu.c
 create mode 100644 include/linux/mfd/ti-lmu-register.h
 create mode 100644 include/linux/mfd/ti-lmu.h

-- 
2.11.0

[PATCH v3 19/25] dt-bindings: arm: cpus: Add S500 enable-method

[Andreas Färber]

The Actions Semi S500 SoC requires a special secondary CPU boot procedure.

Signed-off-by: Andreas Färber 
---
 v3: new
 
 Documentation/devicetree/bindings/arm/cpus.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt 
b/Documentation/devicetree/bindings/arm/cpus.txt
index 698ad1f0..e3e1e2f 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -192,6 +192,7 @@ nodes to be present and contain the properties described 
below.
 "spin-table"
# On ARM 32-bit systems this property is optional and
  can be one of:
+   "actions,s500-smp"
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"arm,realview-smp"
-- 
2.10.2

[PATCH v3 19/25] dt-bindings: arm: cpus: Add S500 enable-method

[Andreas Färber]

The Actions Semi S500 SoC requires a special secondary CPU boot procedure.

Signed-off-by: Andreas Färber 
---
 v3: new
 
 Documentation/devicetree/bindings/arm/cpus.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt 
b/Documentation/devicetree/bindings/arm/cpus.txt
index 698ad1f0..e3e1e2f 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -192,6 +192,7 @@ nodes to be present and contain the properties described 
below.
 "spin-table"
# On ARM 32-bit systems this property is optional and
  can be one of:
+   "actions,s500-smp"
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"arm,realview-smp"
-- 
2.10.2

[PATCH v3 24/25] ARM: dts: s500: Add SPS node

[Andreas Färber]

Signed-off-by: Andreas Färber 
---
 v3: new
 
 arch/arm/boot/dts/s500.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/s500.dtsi b/arch/arm/boot/dts/s500.dtsi
index b4ebd27..e802896 100644
--- a/arch/arm/boot/dts/s500.dtsi
+++ b/arch/arm/boot/dts/s500.dtsi
@@ -9,6 +9,7 @@
 #include "skeleton.dtsi"
 
 #include 
+#include 
 
 / {
compatible = "actions,s500";
@@ -37,6 +38,7 @@
compatible = "arm,cortex-a9";
reg = <0x2>;
enable-method = "actions,s500-smp";
+   power-domains = < S500_PD_CPU2>;
};
 
cpu3: cpu@3 {
@@ -44,6 +46,7 @@
compatible = "arm,cortex-a9";
reg = <0x3>;
enable-method = "actions,s500-smp";
+   power-domains = < S500_PD_CPU3>;
};
};
 
@@ -170,5 +173,11 @@
 ;
interrupt-names = "2Hz0", "2Hz1", "Timer0", "Timer1";
};
+
+   sps: power-controller@b01b0100 {
+   compatible = "actions,s500-sps";
+   reg = <0xb01b0100 0x100>;
+   #power-domain-cells = <1>;
+   };
};
 };
-- 
2.10.2

[PATCH v3 24/25] ARM: dts: s500: Add SPS node

[Andreas Färber]

Signed-off-by: Andreas Färber 
---
 v3: new
 
 arch/arm/boot/dts/s500.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/s500.dtsi b/arch/arm/boot/dts/s500.dtsi
index b4ebd27..e802896 100644
--- a/arch/arm/boot/dts/s500.dtsi
+++ b/arch/arm/boot/dts/s500.dtsi
@@ -9,6 +9,7 @@
 #include "skeleton.dtsi"
 
 #include 
+#include 
 
 / {
compatible = "actions,s500";
@@ -37,6 +38,7 @@
compatible = "arm,cortex-a9";
reg = <0x2>;
enable-method = "actions,s500-smp";
+   power-domains = < S500_PD_CPU2>;
};
 
cpu3: cpu@3 {
@@ -44,6 +46,7 @@
compatible = "arm,cortex-a9";
reg = <0x3>;
enable-method = "actions,s500-smp";
+   power-domains = < S500_PD_CPU3>;
};
};
 
@@ -170,5 +173,11 @@
 ;
interrupt-names = "2Hz0", "2Hz1", "Timer0", "Timer1";
};
+
+   sps: power-controller@b01b0100 {
+   compatible = "actions,s500-sps";
+   reg = <0xb01b0100 0x100>;
+   #power-domain-cells = <1>;
+   };
};
 };
-- 
2.10.2

[PATCH v3 17/25] ARM64: dts: actions: s900-bubblegum-96: Add fake uart5 clock

[Andreas Färber]

Give the serial driver a fixed-clock as input for baudrate 115200.

Signed-off-by: Andreas Färber 
---
 v2 -> v3: unchanged
 
 v2: new
 
 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts 
b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
index a0c3484..21ca80f 100644
--- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
@@ -24,6 +24,12 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x8000>;
};
+
+   uart5_clk: uart5-clk {
+   compatible = "fixed-clock";
+   clock-frequency = <921600>;
+   #clock-cells = <0>;
+   };
 };
 
  {
@@ -32,4 +38,5 @@
 
  {
status = "okay";
+   clocks = <_clk>;
 };
-- 
2.10.2

[PATCH v3 22/25] dt-bindings: power: Add Owl SPS power domains

[Andreas Färber]

Define power domains for all non-reserved S500 power gates.

Signed-off-by: Andreas Färber 
---
 v3: new
 
 .../devicetree/bindings/power/actions,owl-sps.txt | 17 +
 include/dt-bindings/power/s500-powergate.h| 19 +++
 2 files changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/actions,owl-sps.txt
 create mode 100644 include/dt-bindings/power/s500-powergate.h

diff --git a/Documentation/devicetree/bindings/power/actions,owl-sps.txt 
b/Documentation/devicetree/bindings/power/actions,owl-sps.txt
new file mode 100644
index 000..c5eed06
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/actions,owl-sps.txt
@@ -0,0 +1,17 @@
+Actions Semi Owl Smart Power System (SPS)
+
+Required properties:
+- compatible  :  "actions,s500-sps" for S500
+- reg :  Offset and length of the register set for the device.
+- #power-domain-cells :  Must be 1.
+ See macros in:
+  include/dt-bindings/power/s500-powergate.h for S500
+
+
+Example:
+
+   sps: power-controller@b01b0100 {
+   compatible = "actions,s500-sps";
+   reg = <0xb01b0100 0x100>;
+   #power-domain-cells = <1>;
+   };
diff --git a/include/dt-bindings/power/s500-powergate.h 
b/include/dt-bindings/power/s500-powergate.h
new file mode 100644
index 000..ccc4ac3
--- /dev/null
+++ b/include/dt-bindings/power/s500-powergate.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+#ifndef DT_BINDINGS_POWER_S500_POWERGATE_H
+#define DT_BINDINGS_POWER_S500_POWERGATE_H
+
+#define S500_PD_VDE0
+#define S500_PD_VCE_SI 1
+#define S500_PD_USB2_1 2
+#define S500_PD_CPU2   3
+#define S500_PD_CPU3   4
+#define S500_PD_DMA5
+#define S500_PD_DS 6
+#define S500_PD_USB3   7
+#define S500_PD_USB2_0 8
+
+#endif
-- 
2.10.2

[PATCH v3 21/25] ARM: dts: s500: Set CPU enable-method

[Andreas Färber]

Use a custom S500 enable-method for all CPUs.

Signed-off-by: Andreas Färber 
---
 v3: new
 
 arch/arm/boot/dts/s500.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/s500.dtsi b/arch/arm/boot/dts/s500.dtsi
index 1973181..b4ebd27 100644
--- a/arch/arm/boot/dts/s500.dtsi
+++ b/arch/arm/boot/dts/s500.dtsi
@@ -22,24 +22,28 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x0>;
+   enable-method = "actions,s500-smp";
};
 
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x1>;
+   enable-method = "actions,s500-smp";
};
 
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x2>;
+   enable-method = "actions,s500-smp";
};
 
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x3>;
+   enable-method = "actions,s500-smp";
};
};
 
-- 
2.10.2

[PATCH v3 17/25] ARM64: dts: actions: s900-bubblegum-96: Add fake uart5 clock

[Andreas Färber]

Give the serial driver a fixed-clock as input for baudrate 115200.

Signed-off-by: Andreas Färber 
---
 v2 -> v3: unchanged
 
 v2: new
 
 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts 
b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
index a0c3484..21ca80f 100644
--- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
@@ -24,6 +24,12 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x8000>;
};
+
+   uart5_clk: uart5-clk {
+   compatible = "fixed-clock";
+   clock-frequency = <921600>;
+   #clock-cells = <0>;
+   };
 };
 
  {
@@ -32,4 +38,5 @@
 
  {
status = "okay";
+   clocks = <_clk>;
 };
-- 
2.10.2