date:20180518

PLL0 on davinci/da850-type device needs to be registered early in boot
because it is needed for clocksource/clockevent. Change the driver
to use CLK_OF_DECLARE for this special case.

Reviewed-by: Sekhar Nori 
Signed-off-by: David Lechner 
---

v11 changes:
- none

v10 changes:
- removed duplicate warning message

v9 changes:
- new patch in v9

 drivers/clk/davinci/pll-da850.c | 21 +
 drivers/clk/davinci/pll.c   |  4 +++-
 drivers/clk/davinci/pll.h   |  2 +-
 3 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/davinci/pll-da850.c b/drivers/clk/davinci/pll-da850.c
index 59cc2e3733f9..0f7198191ea2 100644
--- a/drivers/clk/davinci/pll-da850.c
+++ b/drivers/clk/davinci/pll-da850.c
@@ -13,6 +13,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 
@@ -136,11 +138,22 @@ static const struct davinci_pll_sysclk_info 
*da850_pll0_sysclk_info[] = {
NULL
 };
 
-int of_da850_pll0_init(struct device *dev, void __iomem *base, struct regmap 
*cfgchip)
+void of_da850_pll0_init(struct device_node *node)
 {
-   return of_davinci_pll_init(dev, dev->of_node, &da850_pll0_info,
-  &da850_pll0_obsclk_info,
-  da850_pll0_sysclk_info, 7, base, cfgchip);
+   void __iomem *base;
+   struct regmap *cfgchip;
+
+   base = of_iomap(node, 0);
+   if (!base) {
+   pr_err("%s: ioremap failed\n", __func__);
+   return;
+   }
+
+   cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
+
+   of_davinci_pll_init(NULL, node, &da850_pll0_info,
+   &da850_pll0_obsclk_info,
+   da850_pll0_sysclk_info, 7, base, cfgchip);
 }
 
 static const struct davinci_pll_clk_info da850_pll1_info = {
diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c
index ae5f966b503f..8dc9854d44dd 100644
--- a/drivers/clk/davinci/pll.c
+++ b/drivers/clk/davinci/pll.c
@@ -857,8 +857,10 @@ static struct davinci_pll_platform_data 
*davinci_pll_get_pdata(struct device *de
return pdata;
 }
 
+/* needed in early boot for clocksource/clockevent */
+CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init);
+
 static const struct of_device_id davinci_pll_of_match[] = {
-   { .compatible = "ti,da850-pll0", .data = of_da850_pll0_init },
{ .compatible = "ti,da850-pll1", .data = of_da850_pll1_init },
{ }
 };
diff --git a/drivers/clk/davinci/pll.h b/drivers/clk/davinci/pll.h
index 562652fc0759..b2e5c4496645 100644
--- a/drivers/clk/davinci/pll.h
+++ b/drivers/clk/davinci/pll.h
@@ -123,7 +123,7 @@ int of_davinci_pll_init(struct device *dev, struct 
device_node *node,
 /* Platform-specific callbacks */
 
 int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap 
*cfgchip);
-int of_da850_pll0_init(struct device *dev, void __iomem *base, struct regmap 
*cfgchip);
+void of_da850_pll0_init(struct device_node *node);
 int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap 
*cfgchip);
 
 int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap 
*cfgchip);
-- 
2.17.0

[PATCH v11 03/27] clk: davinci: psc: allow for dev == NULL

On some davinci SoCs, we need to register the PSC clocks during early
boot because they are needed for clocksource/clockevent. These changes
allow for dev == NULL because in this case, we won't have a platform
device for the clocks.

Some function declarations are moved to a public header files so that they can
be called from mach init code.

Signed-off-by: David Lechner 
---

v11 changes:
- proper unwinding on errors
- add #include  to avoid W=1 warnings

v10 changes:
- dropped helper functions that conditionally called devm_ versions of functions

v9 changes:
- new patch in v9


 drivers/clk/davinci/psc-dm355.c  |  3 +-
 drivers/clk/davinci/psc-dm365.c  |  3 +-
 drivers/clk/davinci/psc-dm644x.c |  3 +-
 drivers/clk/davinci/psc-dm646x.c |  3 +-
 drivers/clk/davinci/psc.c| 58 
 include/linux/clk/davinci.h  |  5 +++
 6 files changed, 57 insertions(+), 18 deletions(-)

diff --git a/drivers/clk/davinci/psc-dm355.c b/drivers/clk/davinci/psc-dm355.c
index 128e7345b20c..ddd250107c4e 100644
--- a/drivers/clk/davinci/psc-dm355.c
+++ b/drivers/clk/davinci/psc-dm355.c
@@ -6,6 +6,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -68,7 +69,7 @@ static const struct davinci_lpsc_clk_info dm355_psc_info[] = {
{ }
 };
 
-static int dm355_psc_init(struct device *dev, void __iomem *base)
+int dm355_psc_init(struct device *dev, void __iomem *base)
 {
return davinci_psc_register_clocks(dev, dm355_psc_info, 42, base);
 }
diff --git a/drivers/clk/davinci/psc-dm365.c b/drivers/clk/davinci/psc-dm365.c
index 289af3913fb0..8c73086cc676 100644
--- a/drivers/clk/davinci/psc-dm365.c
+++ b/drivers/clk/davinci/psc-dm365.c
@@ -6,6 +6,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -86,7 +87,7 @@ static const struct davinci_lpsc_clk_info dm365_psc_info[] = {
{ }
 };
 
-static int dm365_psc_init(struct device *dev, void __iomem *base)
+int dm365_psc_init(struct device *dev, void __iomem *base)
 {
return davinci_psc_register_clocks(dev, dm365_psc_info, 52, base);
 }
diff --git a/drivers/clk/davinci/psc-dm644x.c b/drivers/clk/davinci/psc-dm644x.c
index c22367baa46f..fc0230e3a3d6 100644
--- a/drivers/clk/davinci/psc-dm644x.c
+++ b/drivers/clk/davinci/psc-dm644x.c
@@ -6,6 +6,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -63,7 +64,7 @@ static const struct davinci_lpsc_clk_info dm644x_psc_info[] = 
{
{ }
 };
 
-static int dm644x_psc_init(struct device *dev, void __iomem *base)
+int dm644x_psc_init(struct device *dev, void __iomem *base)
 {
return davinci_psc_register_clocks(dev, dm644x_psc_info, 41, base);
 }
diff --git a/drivers/clk/davinci/psc-dm646x.c b/drivers/clk/davinci/psc-dm646x.c
index 468ef86ea40b..c3f82ed70a80 100644
--- a/drivers/clk/davinci/psc-dm646x.c
+++ b/drivers/clk/davinci/psc-dm646x.c
@@ -6,6 +6,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -58,7 +59,7 @@ static const struct davinci_lpsc_clk_info dm646x_psc_info[] = 
{
{ }
 };
 
-static int dm646x_psc_init(struct device *dev, void __iomem *base)
+int dm646x_psc_init(struct device *dev, void __iomem *base)
 {
return davinci_psc_register_clocks(dev, dm646x_psc_info, 46, base);
 }
diff --git a/drivers/clk/davinci/psc.c b/drivers/clk/davinci/psc.c
index ce170e600f09..6326ba1fe3cc 100644
--- a/drivers/clk/davinci/psc.c
+++ b/drivers/clk/davinci/psc.c
@@ -15,6 +15,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -63,7 +64,7 @@ struct davinci_psc_data {
 
 /**
  * struct davinci_lpsc_clk - LPSC clock structure
- * @dev: the device that provides this LPSC
+ * @dev: the device that provides this LPSC or NULL
  * @hw: clk_hw for the LPSC
  * @pm_domain: power domain for the LPSC
  * @genpd_clk: clock reference owned by @pm_domain
@@ -221,6 +222,7 @@ static void davinci_psc_genpd_detach_dev(struct 
generic_pm_domain *pm_domain,
 
 /**
  * davinci_lpsc_clk_register - register LPSC clock
+ * @dev: the clocks's device or NULL
  * @name: name of this clock
  * @parent_name: name of clock's parent
  * @regmap: PSC MMIO region
@@ -238,7 +240,7 @@ davinci_lpsc_clk_register(struct device *dev, const char 
*name,
int ret;
bool is_on;
 
-   lpsc = devm_kzalloc(dev, sizeof(*lpsc), GFP_KERNEL);
+   lpsc = kzalloc(sizeof(*lpsc), GFP_KERNEL);
if (!lpsc)
return ERR_PTR(-ENOMEM);
 
@@ -261,9 +263,15 @@ davinci_lpsc_clk_register(struct device *dev, const char 
*name,
lpsc->pd = pd;
lpsc->flags = flags;
 
-   ret = devm_clk_hw_register(dev, &lpsc->hw);
-   if (ret < 0)
+   ret = clk_hw_register(dev, &lpsc->hw);
+   if (ret < 0) {
+   kfree(lpsc);
return ERR_PTR(ret);
+   }
+
+   /* for now, genpd is only registered when using device-tree */
+   if (!dev || !dev->of_node)
+   return lpsc;
 
/* genpd attach needs a way to look up this clock */

[PATCH v11 05/27] ARM: davinci: da830: add new clock init using common clock framework

This adds the new board-specific clock init in mach-davinci/da830.c
using the new common clock framework drivers.

The #ifdefs are needed to prevent compile errors until the entire
ARCH_DAVINCI is converted.

Also clean up the #includes since we are adding some here.

Reviewed-by: Sekhar Nori 
Signed-off-by: David Lechner 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- register PLL in da830_init_time() instead of as platform device so that we
  get the correct timer0 clock for davinci_timer_init()

v8 changes:
- none

v7 changes:
- add clock platform device declarations
- register platform devices instead of registering clocks directly
- clkdev lookup is moved to drivers/clk
- add davinci prefix to commit description

v6 changes:
- add blank lines between function calls
- include da8xx_register_cfgchip()

 arch/arm/mach-davinci/board-da830-evm.c|  2 +
 arch/arm/mach-davinci/da830.c  | 70 --
 arch/arm/mach-davinci/include/mach/da8xx.h |  1 +
 3 files changed, 67 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c 
b/arch/arm/mach-davinci/board-da830-evm.c
index 14a6fc061744..74df37821abe 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -557,6 +557,8 @@ static __init void da830_evm_init(void)
struct davinci_soc_info *soc_info = &davinci_soc_info;
int ret;
 
+   da830_register_clocks();
+
ret = da830_register_gpio();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 0b17e5a22e5e..8a79e245db1f 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -8,23 +8,27 @@
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
+#include 
+#include 
 #include 
 #include 
-#include 
 #include 
 
 #include 
 
-#include "psc.h"
-#include 
-#include 
 #include 
-#include 
+#include 
 #include 
+#include 
+#include 
 
-#include "clock.h"
 #include "mux.h"
 
+#ifndef CONFIG_COMMON_CLK
+#include "clock.h"
+#include "psc.h"
+#endif
+
 /* Offsets of the 8 compare registers on the da830 */
 #define DA830_CMP12_0  0x60
 #define DA830_CMP12_1  0x64
@@ -37,6 +41,7 @@
 
 #define DA830_REF_FREQ 2400
 
+#ifndef CONFIG_COMMON_CLK
 static struct pll_data pll0_data = {
.num= 1,
.phys_base  = DA8XX_PLL0_BASE,
@@ -432,6 +437,7 @@ static struct clk_lookup da830_clks[] = {
CLK(NULL,   "rmii", &rmii_clk),
CLK(NULL,   NULL,   NULL),
 };
+#endif
 
 /*
  * Device specific mux setup
@@ -1223,6 +1229,58 @@ void __init da830_init(void)
 
 void __init da830_init_time(void)
 {
+#ifdef CONFIG_COMMON_CLK
+   void __iomem *pll;
+   struct clk *clk;
+
+   clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA830_REF_FREQ);
+
+   pll = ioremap(DA8XX_PLL0_BASE, SZ_4K);
+
+   da830_pll_init(NULL, pll, NULL);
+
+   clk = clk_get(NULL, "timer0");
+
+   davinci_timer_init(clk);
+#else
davinci_clk_init(da830_clks);
davinci_timer_init(&timerp64_0_clk);
+#endif
+}
+
+static struct resource da830_psc0_resources[] = {
+   {
+   .start  = DA8XX_PSC0_BASE,
+   .end= DA8XX_PSC0_BASE + SZ_4K - 1,
+   .flags  = IORESOURCE_MEM,
+   },
+};
+
+static struct platform_device da830_psc0_device = {
+   .name   = "da830-psc0",
+   .id = -1,
+   .resource   = da830_psc0_resources,
+   .num_resources  = ARRAY_SIZE(da830_psc0_resources),
+};
+
+static struct resource da830_psc1_resources[] = {
+   {
+   .start  = DA8XX_PSC1_BASE,
+   .end= DA8XX_PSC1_BASE + SZ_4K - 1,
+   .flags  = IORESOURCE_MEM,
+   },
+};
+
+static struct platform_device da830_psc1_device = {
+   .name   = "da830-psc1",
+   .id = -1,
+   .resource   = da830_psc1_resources,
+   .num_resources  = ARRAY_SIZE(da830_psc1_resources),
+};
+
+void __init da830_register_clocks(void)
+{
+   /* PLL is registered in da830_init_time() */
+   platform_device_register(&da830_psc0_device);
+   platform_device_register(&da830_psc1_device);
 }
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h 
b/arch/arm/mach-davinci/include/mach/da8xx.h
index 9fd6d0125762..64861ac6a9d4 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -89,6 +89,7 @@ extern unsigned int da850_max_speed;
 
 void da830_init(void);
 void da830_init_time(void);
+void da830_register_clocks(void);
 
 void da850_init(void);
 void da850_init_time(void);
-- 
2.17.0

[PATCH v11 04/27] ARM: davinci: pass clock as parameter to davinci_timer_init()

This changes davinci_timer_init() so that we pass the clock as a
parameter instead of using clk_get(). This is done in preparation
for converting to the common clock framework.

It removes the requirement that we have to have a clock with con_id
of "timer0", which will be good for DT bindings since clock-names =
"timer0" doesn't really make sense.

Also, drop use of extern in header file since we are touching the
definition.

Reviewed-by: Sekhar Nori 
Signed-off-by: David Lechner 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- drop comment about using ref_clk

v8 changes:
- none

v7 changes:
- new in v7

 arch/arm/mach-davinci/da830.c   | 2 +-
 arch/arm/mach-davinci/da850.c   | 2 +-
 arch/arm/mach-davinci/dm355.c   | 2 +-
 arch/arm/mach-davinci/dm365.c   | 2 +-
 arch/arm/mach-davinci/dm644x.c  | 2 +-
 arch/arm/mach-davinci/dm646x.c  | 2 +-
 arch/arm/mach-davinci/include/mach/common.h | 3 ++-
 arch/arm/mach-davinci/time.c| 5 +
 8 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 350d7673aa4d..0b17e5a22e5e 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1224,5 +1224,5 @@ void __init da830_init(void)
 void __init da830_init_time(void)
 {
davinci_clk_init(da830_clks);
-   davinci_timer_init();
+   davinci_timer_init(&timerp64_0_clk);
 }
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 34117e614e08..1dbf01c4124b 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1396,5 +1396,5 @@ void __init da850_init(void)
 void __init da850_init_time(void)
 {
davinci_clk_init(da850_clks);
-   davinci_timer_init();
+   davinci_timer_init(&timerp64_0_clk);
 }
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index f29480495c18..0da7516018ca 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -1047,7 +1047,7 @@ void __init dm355_init(void)
 void __init dm355_init_time(void)
 {
davinci_clk_init(dm355_clks);
-   davinci_timer_init();
+   davinci_timer_init(&timer0_clk);
 }
 
 int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 1e3df9df1e10..871372a59da8 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1172,7 +1172,7 @@ void __init dm365_init(void)
 void __init dm365_init_time(void)
 {
davinci_clk_init(dm365_clks);
-   davinci_timer_init();
+   davinci_timer_init(&timer0_clk);
 }
 
 static struct resource dm365_vpss_resources[] = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index a2e8586c8a6d..708df0ed8554 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -935,7 +935,7 @@ void __init dm644x_init(void)
 void __init dm644x_init_time(void)
 {
davinci_clk_init(dm644x_clks);
-   davinci_timer_init();
+   davinci_timer_init(&timer0_clk);
 }
 
 int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index c32ca27ab343..280b753702f3 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -957,7 +957,7 @@ void __init dm646x_init_time(unsigned long ref_clk_rate,
ref_clk.rate = ref_clk_rate;
aux_clkin.rate = aux_clkin_rate;
davinci_clk_init(dm646x_clks);
-   davinci_timer_init();
+   davinci_timer_init(&timer0_clk);
 }
 
 static int __init dm646x_init_devices(void)
diff --git a/arch/arm/mach-davinci/include/mach/common.h 
b/arch/arm/mach-davinci/include/mach/common.h
index f0d5e858f158..5f45d0ac66a8 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -12,11 +12,12 @@
 #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
 #define __ARCH_ARM_MACH_DAVINCI_COMMON_H
 
+#include 
 #include 
 #include 
 #include 
 
-extern void davinci_timer_init(void);
+void davinci_timer_init(struct clk *clk);
 
 extern void davinci_irq_init(void);
 extern void __iomem *davinci_intc_base;
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 1bb991ad9c1e..486896f309c5 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -334,10 +334,8 @@ static struct clock_event_device clockevent_davinci = {
.set_state_oneshot  = davinci_set_oneshot,
 };
 
-
-void __init davinci_timer_init(void)
+void __init davinci_timer_init(struct clk *timer_clk)
 {
-   struct clk *timer_clk;
struct davinci_soc_info *soc_info = &davinci_soc_info;
unsigned int clockevent_id;
unsigned int clocksource_id;
@@ -373,7 +371,6 @@ void __init davinci_timer_init(void)
}
}
 
-   timer_clk = clk_get(NULL, "

[PATCH v11 00/27] ARM: davinci: convert to common clock framework

This series converts mach-davinci to use the common clock framework.

The series works like this, the first 3 patches fix some issues with the clock
drivers that have already been accepted into the mainline kernel.

Then, starting with "ARM: davinci: pass clock as parameter to
davinci_timer_init()", we get the mach code ready for the switch by adding the
code needed for the new clock drivers and adding #ifndef CONFIG_COMMON_CLK
around the legacy clocks so that we can switch easily between the old and the
new.

"ARM: davinci: switch to common clock framework" actually flips the switch
to start using the new clock drivers. Then the next 8 patches remove all
of the old clock code.

The final four patches add device tree clock support to the one SoC that
supports it.

This series has been tested on TI OMAP-L138 LCDK (both device tree and legacy
board file).


Changes:

v11 changes  (also see individual patches for details):
- Proper unwinding on error in clk patches
- Dropped ref_clk fallback in device tree timer patch
- Fix W=1 and sparse warnings

v10 changes (also see individual patches for details):
- Reworked device tree bindings for DaVinci timer.
- Dropped helper functions to conditionally call devm_* versions of functions
- Fix some typos
- Fix some rebasing issues introduced in v9

v9 changes (also see individual patches for details):
- Rebased on linux-davnci/master (f5e3203bb775)
- Dropped drivers/clk patches that landed in v4.17
- New drivers/clk patches for early boot special case
- New patch for ti,davinci-timer device tree bindings
- Updated mach/davinci patches to register clocks in early boot when needed

v8 changes (also see individual patches for details):
- Rebased on linux-davinci/master
- Dropped use of __init and __initconst attributes in clk drivers
- Add clkdev lookups for PLL SYSCLKs
- Fix genpd clock reference counting issue
- Fix PSC clock driver loading order issue
- Fix typo in device tree and add more power-domains properties

v7 changes (also see individual patches for details):
- Rebased on linux-davinci/master (v4.16-rc)
- Convert clock drivers to platform devices
- New patch "ARM: davinci: pass clock as parameter to davinci_timer_init()"
- Fix issues with lcdk and aemif clock lookups and power domains
- Fixed other minor issues brought up in v6 review

v6 changes (also see individual patches for details):
- All of the device tree bindings are changed
- All of the clock drivers are changed significantly
- Fixed issues brought up during review of v5
- "ARM: davinci: move davinci_clk_init() to init_time" is removed from this
  series and submitted separately

v5 changes:
- Basically, this is an entirely new series
- Patches are broken up into bite-sized pieces
- Converted PSC clock driver to use regmap
- Restored "force" flag for certain DA850 clocks
- Added device tree bindings
- Moved more of the clock init to drivers/clk
- Fixed frequency scaling (maybe*)

* I have frequency scaling using cpufreq-dt, so I know the clocks are doing
  what they need to do to make this work, but I haven't figured out how to
  test davinci-cpufreq driver yet. (Patches to make cpufreq-dt work will be
  sent separately after this series has landed.)


Dependencies:

There are still some outstanding fixes to get everything working correctly.
For the most part, these are just runtime dependencies and only needed for
certain platforms.

Of the clk patches, only "clk: davinci: psc-da830: fix USB0 48MHz PHY clock
registration" has been picked up in clk-next so far. Theoretically, there has
been a pull request made for "drm/tilcdc: Fix setting clock divider for
omap-l138", but I haven't seen it land anywhere yet. The series "remoteproc/
davinci: common clock framework related fixes" is in rproc-next already.

- "drm/tilcdc: Fix setting clock divider for omap-l138"[1]
- "clk: davinci: pll-dm355: fix SYSCLKn parent names"[2]
- "remoteproc/davinci: common clock framework related fixes"[3]
- "clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration"[4]
- "clk: davinci: some more fixes"[5]
- "clk: davinci: psc-dm355: fix ASP0/1 clkdev lookups"[6]

[1]: https://patchwork.freedesktop.org/patch/210696/
[2]: https://lkml.org/lkml/2018/5/9/626
[3]: https://lkml.org/lkml/2018/5/2/201
[4]: 
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/commit/?h=clk-davinci-psc-da830&id=a714dceb721407c2a5d2887938f37e34ed00669c
[5]: https://www.spinics.net/lists/arm-kernel/msg652656.html
[6]: https://patchwork.kernel.org/patch/10395979/

You can find a working branch with everything included (plus a few extras, like
cpufreq-dt) in the "common-clk-v11" branch of 
https://github.com/dlech/ev3dev-kernel.git.


Testing/debugging for the uninitiated:

I only have one device to test with, which is based on da850, so I will
have to rely on others to do some testing here. Since we are dealing with
clocks, if something isn't working, you most likely won't see output on
the serial port. To figure out what is going on, you

[PATCH v11 06/27] ARM: davinci: da850: add new clock init using common clock framework

This adds the new board-specific clock init in mach-davinci/da850.c
using the new common clock framework drivers.

The #ifdefs are needed to prevent compile errors until the entire
ARCH_DAVINCI is converted.

Also clean up the #includes since we are adding some here.

Some CFGCHIP macros were removed because we are now including
linux/mfd/da8xx-cfgchip.h which defines the same values.

Reviewed-by: Sekhar Nori 
Signed-off-by: David Lechner 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- register PLL in da850_init_time() instead of as platform device so that we
  get the correct timer0 clock for davinci_timer_init()

v8 changes:
- add platform data for PLL clocks

v7 changes:
- add clock platform device declarations
- register platform devices instead of registering clocks directly
- clkdev lookup is moved to drivers/clk
- add davinci prefix to commit description

v6 changes:
- add blank lines between function calls
- include da8xx_register_cfgchip()
- add async1 and async2 clock domains


 arch/arm/mach-davinci/board-da850-evm.c |   2 +
 arch/arm/mach-davinci/board-mityomapl138.c  |   2 +
 arch/arm/mach-davinci/board-omapl138-hawk.c |   2 +
 arch/arm/mach-davinci/da850.c   | 155 ++--
 arch/arm/mach-davinci/da8xx-dt.c|   2 +
 arch/arm/mach-davinci/include/mach/da8xx.h  |   1 +
 6 files changed, 151 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da850-evm.c 
b/arch/arm/mach-davinci/board-da850-evm.c
index e22fb40e34bc..442c16773f09 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1340,6 +1340,8 @@ static __init void da850_evm_init(void)
 {
int ret;
 
+   da850_register_clocks();
+
ret = da850_register_gpio();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c 
b/arch/arm/mach-davinci/board-mityomapl138.c
index 37b3e48a21d1..2cce0d7d2f2a 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -503,6 +503,8 @@ static void __init mityomapl138_init(void)
 {
int ret;
 
+   da850_register_clocks();
+
/* for now, no special EDMA channels are reserved */
ret = da850_register_edma(NULL);
if (ret)
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c 
b/arch/arm/mach-davinci/board-omapl138-hawk.c
index be8b892a6ea7..7653e9425d44 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -285,6 +285,8 @@ static __init void omapl138_hawk_init(void)
 {
int ret;
 
+   da850_register_clocks();
+
ret = da850_register_gpio();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 1dbf01c4124b..9e00beb943c9 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -11,39 +11,45 @@
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
+
+#include 
+#include 
 #include 
+#include 
 #include 
 #include 
-#include 
+#include 
+#include 
+#include 
+#include 
 #include 
-#include 
+#include 
 #include 
-#include 
 
 #include 
 
-#include "psc.h"
-#include 
-#include 
 #include 
-#include 
-#include 
 #include 
+#include 
+#include 
+#include 
 #include 
+#include 
 
-#include "clock.h"
 #include "mux.h"
 
+#ifndef CONFIG_COMMON_CLK
+#include "clock.h"
+#include "psc.h"
+#endif
+
 #define DA850_PLL1_BASE0x01e1a000
 #define DA850_TIMER64P2_BASE   0x01f0c000
 #define DA850_TIMER64P3_BASE   0x01f0d000
 
 #define DA850_REF_FREQ 2400
 
-#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
-#define CFGCHIP3_PLL1_MASTER_LOCK  BIT(5)
-#define CFGCHIP0_PLL_MASTER_LOCK   BIT(4)
-
+#ifndef CONFIG_COMMON_CLK
 static int da850_set_armrate(struct clk *clk, unsigned long rate);
 static int da850_round_armrate(struct clk *clk, unsigned long rate);
 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
@@ -583,6 +589,7 @@ static struct clk_lookup da850_clks[] = {
CLK("ecap.2",   "fck",  &ecap2_clk),
CLK(NULL,   NULL,   NULL),
 };
+#endif
 
 /*
  * Device specific mux setup
@@ -1170,6 +1177,7 @@ int da850_register_cpufreq(char *async_clk)
return platform_device_register(&da850_cpufreq_device);
 }
 
+#ifndef CONFIG_COMMON_CLK
 static int da850_round_armrate(struct clk *clk, unsigned long rate)
 {
int ret = 0, diff;
@@ -1232,12 +1240,14 @@ static int da850_set_pll0rate(struct clk *clk, unsigned 
long rate)
 
return 0;
 }
+#endif /* CONFIG_COMMON_CLK */
 #else
 int __init da850_register_cpufreq(char *async_clk)
 {
return 0;
 }
 
+#ifndef CONFIG_COMMON_CLK
 static int da850_set_armrate(struct clk *clk, unsigned long rate)
 {
return -EINVAL;
@@ -12

[PATCH v11 08/27] ARM: davinci: dm365: add new clock init using common clock framework

This adds the new board-specific clock init in mach-davinci/dm365.c
using the new common clock framework drivers.

The #ifdefs are needed to prevent compile errors until the entire
ARCH_DAVINCI is converted.

Also clean up the #includes since we are adding some here.

Signed-off-by: David Lechner 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- register PLL1 and PSC in dm365_init_time() instead of as platform device so
  that we get the correct timer0 clock for davinci_timer_init()
- Fixed size of PLL memory block

v8 changes:
- none

v7 changes:
- add clock platform device declarations
- register platform devices instead of registering clocks directly
- add davinci prefix to commit description

v6 changes:
- add blank lines between function calls

 arch/arm/mach-davinci/board-dm365-evm.c |  2 +
 arch/arm/mach-davinci/davinci.h |  1 +
 arch/arm/mach-davinci/dm365.c   | 56 +++--
 3 files changed, 47 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm365-evm.c 
b/arch/arm/mach-davinci/board-dm365-evm.c
index 435f7ec7d9af..307e88d99dd3 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -742,6 +742,8 @@ static __init void dm365_evm_init(void)
 {
int ret;
 
+   dm365_register_clocks();
+
ret = dm365_gpio_register();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index c2c634b6578e..a799b5266d4b 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -94,6 +94,7 @@ int dm355_gpio_register(void);
 /* DM365 function declarations */
 void dm365_init(void);
 void dm365_init_time(void);
+void dm365_register_clocks(void);
 void dm365_init_asp(void);
 void dm365_init_vc(void);
 void dm365_init_ks(struct davinci_ks_platform_data *pdata);
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 871372a59da8..76de426a0e41 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -12,32 +12,38 @@
  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-#include 
-#include 
-#include 
-#include 
+
+#include 
+#include 
+#include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 
 #include 
 
+#include 
 #include 
-#include "psc.h"
-#include 
 #include 
-#include 
+#include 
 #include 
-#include 
+#include 
 
+#include "asp.h"
 #include "davinci.h"
-#include "clock.h"
 #include "mux.h"
-#include "asp.h"
+
+#ifndef CONFIG_COMMON_CLK
+#include "clock.h"
+#include "psc.h"
+#endif
 
 #define DM365_REF_FREQ 2400/* 24 MHz on the DM365 EVM */
 #define DM365_RTC_BASE 0x01c69000
@@ -54,6 +60,7 @@
 #define DM365_EMAC_CNTRL_RAM_OFFSET0x1000
 #define DM365_EMAC_CNTRL_RAM_SIZE  0x2000
 
+#ifndef CONFIG_COMMON_CLK
 static struct pll_data pll1_data = {
.num= 1,
.phys_base  = DAVINCI_PLL1_BASE,
@@ -485,7 +492,7 @@ static struct clk_lookup dm365_clks[] = {
CLK(NULL, "mjcp", &mjcp_clk),
CLK(NULL, NULL, NULL),
 };
-
+#endif
 /*--*/
 
 #define INTMUX 0x18
@@ -1171,8 +1178,33 @@ void __init dm365_init(void)
 
 void __init dm365_init_time(void)
 {
+#ifdef CONFIG_COMMON_CLK
+   void __iomem *pll1, *pll2, *psc;
+   struct clk *clk;
+
+   clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
+
+   pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
+   dm365_pll1_init(NULL, pll1, NULL);
+
+   pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
+   dm365_pll2_init(NULL, pll2, NULL);
+
+   psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
+   dm365_psc_init(NULL, psc);
+
+   clk = clk_get(NULL, "timer0");
+
+   davinci_timer_init(clk);
+#else
davinci_clk_init(dm365_clks);
davinci_timer_init(&timer0_clk);
+#endif
+}
+
+void __init dm365_register_clocks(void)
+{
+   /* all clocks are currently registered in dm365_init_time() */
 }
 
 static struct resource dm365_vpss_resources[] = {
-- 
2.17.0

[PATCH v11 07/27] ARM: davinci: dm355: add new clock init using common clock framework

This adds the new board-specific clock init in mach-davinci/dm355.c
using the new common clock framework drivers.

The #ifdefs are needed to prevent compile errors until the entire
ARCH_DAVINCI is converted.

Also clean up the #includes since we are adding some here.

Signed-off-by: David Lechner 
---

v11 changes:
- none

v10 changes:
- none (reported problems fixed in separate patch series [1])

[1]: https://lkml.org/lkml/2018/5/9/626

v9 changes:
- register PLL1 and PSC in dm355_init_time() instead of as platform device so
  that we get the correct timer0 clock for davinci_timer_init()
- Fixed size of PLL memory block

v8 changes:
- none

v7 changes:
- add clock platform device declarations
- register platform devices instead of registering clocks directly
- add davinci prefix to commit description

v6 changes:
- add blank lines between function calls


 arch/arm/mach-davinci/board-dm355-evm.c |  2 +
 arch/arm/mach-davinci/board-dm355-leopard.c |  2 +
 arch/arm/mach-davinci/davinci.h |  1 +
 arch/arm/mach-davinci/dm355.c   | 69 +
 4 files changed, 62 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm355-evm.c 
b/arch/arm/mach-davinci/board-dm355-evm.c
index a3377f959444..f53a461a606f 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -394,6 +394,8 @@ static __init void dm355_evm_init(void)
struct clk *aemif;
int ret;
 
+   dm355_register_clocks();
+
ret = dm355_gpio_register();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c 
b/arch/arm/mach-davinci/board-dm355-leopard.c
index 8249a0bf69f0..0fdf1d03eb11 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -234,6 +234,8 @@ static __init void dm355_leopard_init(void)
struct clk *aemif;
int ret;
 
+   dm355_register_clocks();
+
ret = dm355_gpio_register();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 376cdd51ce9d..c2c634b6578e 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -84,6 +84,7 @@ int davinci_init_wdt(void);
 /* DM355 function declarations */
 void dm355_init(void);
 void dm355_init_time(void);
+void dm355_register_clocks(void);
 void dm355_init_spi0(unsigned chipselect_mask,
const struct spi_board_info *info, unsigned len);
 void dm355_init_asp1(u32 evt_enable);
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 0da7516018ca..14014b942e8a 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -8,31 +8,37 @@
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
-#include 
-#include 
-#include 
-#include 
+
+#include 
+#include 
+#include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 
 #include 
 
+#include 
 #include 
-#include "psc.h"
-#include 
 #include 
-#include 
+#include 
 #include 
-#include 
+#include 
 
+#include "asp.h"
 #include "davinci.h"
-#include "clock.h"
 #include "mux.h"
-#include "asp.h"
+
+#ifndef CONFIG_COMMON_CLK
+#include "clock.h"
+#include "psc.h"
+#endif
 
 #define DM355_UART2_BASE   (IO_PHYS + 0x206000)
 #define DM355_OSD_BASE (IO_PHYS + 0x70200)
@@ -43,6 +49,7 @@
  */
 #define DM355_REF_FREQ 2400/* 24 or 36 MHz */
 
+#ifndef CONFIG_COMMON_CLK
 static struct pll_data pll1_data = {
.num   = 1,
.phys_base = DAVINCI_PLL1_BASE,
@@ -382,7 +389,7 @@ static struct clk_lookup dm355_clks[] = {
CLK(NULL, "usb", &usb_clk),
CLK(NULL, NULL, NULL),
 };
-
+#endif
 /*--*/
 
 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
@@ -1046,8 +1053,46 @@ void __init dm355_init(void)
 
 void __init dm355_init_time(void)
 {
+#ifdef CONFIG_COMMON_CLK
+   void __iomem *pll1, *psc;
+   struct clk *clk;
+
+   clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
+
+   pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
+   dm355_pll1_init(NULL, pll1, NULL);
+
+   psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
+   dm355_psc_init(NULL, psc);
+
+   clk = clk_get(NULL, "timer0");
+
+   davinci_timer_init(clk);
+#else
davinci_clk_init(dm355_clks);
davinci_timer_init(&timer0_clk);
+#endif
+}
+
+static struct resource dm355_pll2_resources[] = {
+   {
+   .start  = DAVINCI_PLL2_BASE,
+   .end= DAVINCI_PLL2_BASE + SZ_1K - 1,
+   .flags  = IORESOURCE_MEM,
+   },
+};
+
+static struct platform_device dm355_pll2_device = {
+   .name   = "dm355-pl

[PATCH v11 09/27] ARM: davinci: dm644x: add new clock init using common clock framework

This adds the new board-specific clock init in mach-davinci/dm644x.c
using the new common clock framework drivers.

The #ifdefs are needed to prevent compile errors until the entire
ARCH_DAVINCI is converted.

Also clean up the #includes since we are adding some here.

Signed-off-by: David Lechner 
---

v11 chages:
- none

v10 changes:
- fix copy/paste error s/dm355/dm644x/

v9 changes:
- register PLL1 and PSC in dm644x_init_time() instead of as platform device so
  that we get the correct timer0 clock for davinci_timer_init()
- Fixed size of PLL memory block

v8 changes:
- none

v7 changes:
- add clock platform device declarations
- register platform devices instead of registering clocks directly
- add davinci prefix to commit description

v6 changes:
- add blank lines between function calls



 arch/arm/mach-davinci/board-dm644x-evm.c  |  2 +
 arch/arm/mach-davinci/board-neuros-osd2.c |  2 +
 arch/arm/mach-davinci/board-sffsdr.c  |  2 +
 arch/arm/mach-davinci/davinci.h   |  1 +
 arch/arm/mach-davinci/dm644x.c| 64 +++
 5 files changed, 62 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c 
b/arch/arm/mach-davinci/board-dm644x-evm.c
index 48436f74fd71..738e443ab15f 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -773,6 +773,8 @@ static __init void davinci_evm_init(void)
struct clk *aemif_clk;
struct davinci_soc_info *soc_info = &davinci_soc_info;
 
+   dm644x_register_clocks();
+
dm644x_init_devices();
 
ret = dm644x_gpio_register();
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c 
b/arch/arm/mach-davinci/board-neuros-osd2.c
index 25ad9b0612be..353f9e5a1454 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -175,6 +175,8 @@ static __init void davinci_ntosd2_init(void)
struct clk *aemif_clk;
struct davinci_soc_info *soc_info = &davinci_soc_info;
 
+   dm644x_register_clocks();
+
dm644x_init_devices();
 
ret = dm644x_gpio_register();
diff --git a/arch/arm/mach-davinci/board-sffsdr.c 
b/arch/arm/mach-davinci/board-sffsdr.c
index e7c1728b0833..792bb84d5011 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -134,6 +134,8 @@ static __init void davinci_sffsdr_init(void)
 {
struct davinci_soc_info *soc_info = &davinci_soc_info;
 
+   dm644x_register_clocks();
+
dm644x_init_devices();
 
platform_add_devices(davinci_sffsdr_devices,
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index a799b5266d4b..16aca5853ab2 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -108,6 +108,7 @@ int dm365_gpio_register(void);
 void dm644x_init(void);
 void dm644x_init_devices(void);
 void dm644x_init_time(void);
+void dm644x_register_clocks(void);
 void dm644x_init_asp(void);
 int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
 int dm644x_gpio_register(void);
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 708df0ed8554..c3cd27c6cd70 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -8,28 +8,34 @@
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
-#include 
-#include 
-#include 
+
+#include 
+#include 
+#include 
 #include 
-#include 
+#include 
 #include 
 #include 
+#include 
+#include 
 
 #include 
 
+#include 
 #include 
 #include 
-#include "psc.h"
 #include 
-#include 
 #include 
-#include 
+#include 
 
+#include "asp.h"
 #include "davinci.h"
-#include "clock.h"
 #include "mux.h"
-#include "asp.h"
+
+#ifndef CONFIG_COMMON_CLK
+#include "clock.h"
+#include "psc.h"
+#endif
 
 /*
  * Device specific clocks
@@ -43,6 +49,7 @@
 #define DM644X_EMAC_CNTRL_RAM_OFFSET   0x2000
 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
 
+#ifndef CONFIG_COMMON_CLK
 static struct pll_data pll1_data = {
.num   = 1,
.phys_base = DAVINCI_PLL1_BASE,
@@ -326,6 +333,7 @@ static struct clk_lookup dm644x_clks[] = {
CLK("davinci-wdt", NULL, &timer2_clk),
CLK(NULL, NULL, NULL),
 };
+#endif
 
 static struct emac_platform_data dm644x_emac_pdata = {
.ctrl_reg_offset= DM644X_EMAC_CNTRL_OFFSET,
@@ -934,8 +942,46 @@ void __init dm644x_init(void)
 
 void __init dm644x_init_time(void)
 {
+#ifdef CONFIG_COMMON_CLK
+   void __iomem *pll1, *psc;
+   struct clk *clk;
+
+   clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
+
+   pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
+   dm644x_pll1_init(NULL, pll1, NULL);
+
+   psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
+   dm644x_psc_init(NULL, psc);
+
+   clk = clk_get(NULL, "timer0");
+
+   davinci_timer_init(clk);
+#else
davinci_clk_init(dm644x_clks);
davinci_timer_init(&timer0_

Re: [PATCH v2 01/26] rculist: introduce list_next_or_null_rr_rcu()

2018-05-18 Thread Linus Torvalds

On Fri, May 18, 2018 at 6:07 AM Roman Pen 
wrote:

> Function is going to be used in transport over RDMA module
> in subsequent patches.

Does this really merit its own helper macro in a generic header?

It honestly smells more like "just have an inline helper function that is
specific to rdma" to me. Particularly since it's probably just one specific
list where you want this oddly specific behavior.

Also, if we really want a round-robin list traversal macro, this isn't the
way it should be implemented, I suspect, and it probably shouldn't be
RCU-specific to begin with.

Side note: I notice that I should already  have been more critical of even
the much simpler "list_next_or_null_rcu()" macro. The "documentation"
comment above the macro is pure and utter cut-and-paste garbage.

Paul, mind giving this a look?

 Linus

Re: [PATCH 1/2] mfd: stm32-timers: fix pwm-stm32 linker issue with COMPILE_TEST

2018-05-18 Thread Randy Dunlap

On 05/18/2018 08:24 AM, Fabrice Gasnier wrote:
> This is seen when COMPILE_TEST=y and MFD_STM32_TIMERS=n.
> drivers/pwm/pwm-stm32.o: In function 'stm32_pwm_raw_capture':
> pwm-stm32.c:... undefined reference to 'stm32_timers_dma_burst_read'
> Fixes: 0c6609805b63 ("mfd: stm32-timers: Add support for DMAs")
> 
> Signed-off-by: Fabrice Gasnier 

Reported-by: Randy Dunlap 
Tested-by: Randy Dunlap 

Thanks.

> ---
>  include/linux/mfd/stm32-timers.h | 12 
>  1 file changed, 12 insertions(+)
> 
> diff --git a/include/linux/mfd/stm32-timers.h 
> b/include/linux/mfd/stm32-timers.h
> index 9da1d7e..067d146 100644
> --- a/include/linux/mfd/stm32-timers.h
> +++ b/include/linux/mfd/stm32-timers.h
> @@ -124,8 +124,20 @@ struct stm32_timers {
>   struct stm32_timers_dma dma; /* Only to be used by the parent */
>  };
>  
> +#if IS_REACHABLE(CONFIG_MFD_STM32_TIMERS)
>  int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
>   enum stm32_timers_dmas id, u32 reg,
>   unsigned int num_reg, unsigned int bursts,
>   unsigned long tmo_ms);
> +#else
> +static inline int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
> +   enum stm32_timers_dmas id,
> +   u32 reg,
> +   unsigned int num_reg,
> +   unsigned int bursts,
> +   unsigned long tmo_ms)
> +{
> + return -ENODEV;
> +}
> +#endif
>  #endif
> 


-- 
~Randy

[PATCH v11 16/27] ARM: davinci: da830: Remove legacy clock init

This removes the unused legacy clock init code from
arch/arm/mach-davinci/da830.c.

Signed-off-by: David Lechner 
Reviewed-by: Sekhar Nori 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- rebased

v8 changes:
- none

v7 changes:
- rebased
- add davinci prefix to commit message

v6 changes:
- rebased


 arch/arm/mach-davinci/board-da830-evm.c |  12 -
 arch/arm/mach-davinci/da830.c   | 412 
 2 files changed, 424 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c 
b/arch/arm/mach-davinci/board-da830-evm.c
index ccddbae951d6..b2470141dba3 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -110,23 +110,11 @@ static __init void da830_evm_usb_init(void)
 {
int ret;
 
-#ifdef CONFIG_COMMON_CLK
ret = da8xx_register_usb_phy_clocks();
if (ret)
pr_warn("%s: USB PHY CLK registration failed: %d\n",
__func__, ret);
-#else
-   /* USB_REFCLKIN is not used. */
-   ret = da8xx_register_usb20_phy_clk(false);
-   if (ret)
-   pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n",
-   __func__, ret);
 
-   ret = da8xx_register_usb11_phy_clk(false);
-   if (ret)
-   pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n",
-   __func__, ret);
-#endif
ret = da8xx_register_usb_phy();
if (ret)
pr_warn("%s: USB PHY registration failed: %d\n",
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 8a79e245db1f..0bc5bd2665df 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -24,11 +24,6 @@
 
 #include "mux.h"
 
-#ifndef CONFIG_COMMON_CLK
-#include "clock.h"
-#include "psc.h"
-#endif
-
 /* Offsets of the 8 compare registers on the da830 */
 #define DA830_CMP12_0  0x60
 #define DA830_CMP12_1  0x64
@@ -41,404 +36,6 @@
 
 #define DA830_REF_FREQ 2400
 
-#ifndef CONFIG_COMMON_CLK
-static struct pll_data pll0_data = {
-   .num= 1,
-   .phys_base  = DA8XX_PLL0_BASE,
-   .flags  = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
-};
-
-static struct clk ref_clk = {
-   .name   = "ref_clk",
-   .rate   = DA830_REF_FREQ,
-};
-
-static struct clk pll0_clk = {
-   .name   = "pll0",
-   .parent = &ref_clk,
-   .pll_data   = &pll0_data,
-   .flags  = CLK_PLL,
-};
-
-static struct clk pll0_aux_clk = {
-   .name   = "pll0_aux_clk",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL | PRE_PLL,
-};
-
-static struct clk pll0_sysclk2 = {
-   .name   = "pll0_sysclk2",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV2,
-};
-
-static struct clk pll0_sysclk3 = {
-   .name   = "pll0_sysclk3",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV3,
-};
-
-static struct clk pll0_sysclk4 = {
-   .name   = "pll0_sysclk4",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV4,
-};
-
-static struct clk pll0_sysclk5 = {
-   .name   = "pll0_sysclk5",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV5,
-};
-
-static struct clk pll0_sysclk6 = {
-   .name   = "pll0_sysclk6",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV6,
-};
-
-static struct clk pll0_sysclk7 = {
-   .name   = "pll0_sysclk7",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV7,
-};
-
-static struct clk i2c0_clk = {
-   .name   = "i2c0",
-   .parent = &pll0_aux_clk,
-};
-
-static struct clk timerp64_0_clk = {
-   .name   = "timer0",
-   .parent = &pll0_aux_clk,
-};
-
-static struct clk timerp64_1_clk = {
-   .name   = "timer1",
-   .parent = &pll0_aux_clk,
-};
-
-static struct clk arm_rom_clk = {
-   .name   = "arm_rom",
-   .parent = &pll0_sysclk2,
-   .lpsc   = DA8XX_LPSC0_ARM_RAM_ROM,
-   .flags  = ALWAYS_ENABLED,
-};
-
-static struct clk scr0_ss_clk = {
-   .name   = "scr0_ss",
-   .parent = &pll0_sysclk2,
-   .lpsc   = DA8XX_LPSC0_SCR0_SS,
-   .flags  = ALWAYS_ENABLED,
-};
-
-static struct clk scr1_ss_clk = {
-   .name   = "scr1_ss",
-   .parent = &pll0_sysclk2,
-   .lpsc   = DA8XX_LPSC0_SCR1_SS,
-   .flags  = ALWAYS_ENABLED,
-};
-
-static struct clk scr2_ss_clk = {
-   .name   = "scr2_ss",
-   .parent = &pll0_sysclk2,
-   .lpsc   = DA8XX_LPSC0_SCR2_SS,
-   .flags

Re: [PATCH 2/2] pwm: stm32: initialize raw local variables

2018-05-18 Thread Randy Dunlap

On 05/18/2018 08:24 AM, Fabrice Gasnier wrote:
> This removes build warning when COMPILE_TEST=y and MFD_STM32_TIMERS=n
> in drivers/pwm/pwm-stm32.c. In function 'stm32_pwm_capture' 'raw_prd' and
> 'raw_dty' may be used uninitialized in this function
> [-Wmaybe-uninitialized]
> 
> Signed-off-by: Fabrice Gasnier 

Tested-by: Randy Dunlap 

Thanks.

> ---
>  drivers/pwm/pwm-stm32.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
> index 60bfc07..09383c6 100644
> --- a/drivers/pwm/pwm-stm32.c
> +++ b/drivers/pwm/pwm-stm32.c
> @@ -170,7 +170,7 @@ static int stm32_pwm_capture(struct pwm_chip *chip, 
> struct pwm_device *pwm,
>   unsigned long long prd, div, dty;
>   unsigned long rate;
>   unsigned int psc = 0, icpsc, scale;
> - u32 raw_prd, raw_dty;
> + u32 raw_prd = 0, raw_dty = 0;
>   int ret = 0;
>  
>   mutex_lock(&priv->lock);
> 


-- 
~Randy

[PATCH] locking/rwsem: simplify the is-owner-spinnable checks

2018-05-18 Thread Oleg Nesterov

Add the trivial owner_on_cpu() helper for rwsem_can_spin_on_owner() and
rwsem_spin_on_owner(), it also allows to make rwsem_can_spin_on_owner()
a bit more clear.

Signed-off-by: Oleg Nesterov 
---
 kernel/locking/rwsem-xadd.c | 25 +
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/kernel/locking/rwsem-xadd.c b/kernel/locking/rwsem-xadd.c
index a903367..3064c50 100644
--- a/kernel/locking/rwsem-xadd.c
+++ b/kernel/locking/rwsem-xadd.c
@@ -347,6 +347,15 @@ static inline bool rwsem_try_write_lock_unqueued(struct 
rw_semaphore *sem)
}
 }
 
+static inline bool owner_on_cpu(struct task_struct *owner)
+{
+   /*
+* As lock holder preemption issue, we both skip spinning if
+* task is not on cpu or its cpu is preempted
+*/
+   return owner->on_cpu && !vcpu_is_preempted(task_cpu(owner));
+}
+
 static inline bool rwsem_can_spin_on_owner(struct rw_semaphore *sem)
 {
struct task_struct *owner;
@@ -359,17 +368,10 @@ static inline bool rwsem_can_spin_on_owner(struct 
rw_semaphore *sem)
 
rcu_read_lock();
owner = READ_ONCE(sem->owner);
-   if (!owner || !is_rwsem_owner_spinnable(owner)) {
-   ret = !owner;   /* !owner is spinnable */
-   goto done;
+   if (owner) {
+   ret = is_rwsem_owner_spinnable(owner) &&
+ owner_on_cpu(owner);
}
-
-   /*
-* As lock holder preemption issue, we both skip spinning if task is not
-* on cpu or its cpu is preempted
-*/
-   ret = owner->on_cpu && !vcpu_is_preempted(task_cpu(owner));
-done:
rcu_read_unlock();
return ret;
 }
@@ -398,8 +400,7 @@ static noinline bool rwsem_spin_on_owner(struct 
rw_semaphore *sem)
 * abort spinning when need_resched or owner is not running or
 * owner's cpu is preempted.
 */
-   if (!owner->on_cpu || need_resched() ||
-   vcpu_is_preempted(task_cpu(owner))) {
+   if (need_resched() || !owner_on_cpu(owner)) {
rcu_read_unlock();
return false;
}
-- 
2.5.0

[PATCH v11 15/27] ARM: davinci: switch to common clock framework

This switches ARCH_DAVINCI to use the common clock framework. The legacy
clock code in arch/arm/mach-davinci/ is no longer used. New drivers in
drivers/clk/davinci/ are used instead.

A few macros had to be moved to prevent compilation errors.

Signed-off-by: David Lechner 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- none

v8 changes:
- none

v7 changes:
- s/compile/compilation and space instead of tab
- add PM_GENERIC_DOMAINS dependencies

v6 changes:
- clean up indent on Common objects section


 arch/arm/Kconfig| 5 -
 arch/arm/mach-davinci/Makefile  | 4 ++--
 arch/arm/mach-davinci/clock.h   | 4 
 arch/arm/mach-davinci/davinci.h | 4 
 arch/arm/mach-davinci/psc.h | 2 --
 5 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a7f8e7f4b88f..a57ad13810c8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -609,13 +609,16 @@ config ARCH_S3C24XX
 config ARCH_DAVINCI
bool "TI DaVinci"
select ARCH_HAS_HOLES_MEMORYMODEL
-   select CLKDEV_LOOKUP
+   select COMMON_CLK
select CPU_ARM926T
select GENERIC_ALLOCATOR
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
select GPIOLIB
select HAVE_IDE
+   select PM_GENERIC_DOMAINS if PM
+   select PM_GENERIC_DOMAINS_OF if PM && OF
+   select RESET_CONTROLLER
select USE_OF
select ZONE_DMA
help
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 4e8178050027..8725d8bea567 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,8 +5,8 @@
 #
 
 # Common objects
-obj-y  := time.o clock.o serial.o psc.o \
-  usb.o common.o sram.o aemif.o
+obj-y  := time.o serial.o usb.o \
+  common.o sram.o aemif.o
 
 obj-$(CONFIG_DAVINCI_MUX)  += mux.o
 
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index d7894d5aaa25..2d058568e004 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -12,10 +12,6 @@
 #ifndef __ARCH_ARM_DAVINCI_CLOCK_H
 #define __ARCH_ARM_DAVINCI_CLOCK_H
 
-#define DAVINCI_PLL1_BASE 0x01c40800
-#define DAVINCI_PLL2_BASE 0x01c40c00
-#define MAX_PLL 2
-
 /* PLL/Reset register offsets */
 #define PLLCTL  0x100
 #define PLLCTL_PLLENBIT(0)
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index fa99197d36f9..db4c95ef4d5c 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -35,6 +35,10 @@
 #include 
 #include 
 
+#define DAVINCI_PLL1_BASE  0x01c40800
+#define DAVINCI_PLL2_BASE  0x01c40c00
+#define DAVINCI_PWR_SLEEP_CNTRL_BASE   0x01c41000
+
 #define DAVINCI_SYSTEM_MODULE_BASE 0x01c4
 #define SYSMOD_VDAC_CONFIG 0x2c
 #define SYSMOD_VIDCLKCTL   0x38
diff --git a/arch/arm/mach-davinci/psc.h b/arch/arm/mach-davinci/psc.h
index 8af9f09fc10c..b58707cf7033 100644
--- a/arch/arm/mach-davinci/psc.h
+++ b/arch/arm/mach-davinci/psc.h
@@ -27,8 +27,6 @@
 #ifndef __ASM_ARCH_PSC_H
 #define __ASM_ARCH_PSC_H
 
-#defineDAVINCI_PWR_SLEEP_CNTRL_BASE0x01C41000
-
 /* Power and Sleep Controller (PSC) Domains */
 #define DAVINCI_GPSC_ARMDOMAIN 0
 #define DAVINCI_GPSC_DSPDOMAIN 1
-- 
2.17.0

[PATCH v11 12/27] ARM: davinci: da8xx: add new sata_refclk init using common clock framework

This adds the new SATA REFCLK clock init in mach-davinci/devices-da8xx.c
using the new common clock framework drivers.

The #ifdefs are needed to prevent compile errors until the entire
ARCH_DAVINCI is converted.

Also, the #includes are sorted since we are adding some here.

Signed-off-by: David Lechner 
Reviewed-by: Sekhar Nori 
---

v10 changes:
- none

v10 changes:
- none

v9 changes:
- none

v8 changes:
- none

v7 changes:
- none

v6 changes:
- none

 arch/arm/mach-davinci/devices-da8xx.c | 36 ---
 1 file changed, 27 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-davinci/devices-da8xx.c 
b/arch/arm/mach-davinci/devices-da8xx.c
index 78390c64e6ca..73de449bbc68 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -10,25 +10,30 @@
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  */
-#include 
-#include 
-#include 
-#include 
 #include 
+#include 
 #include 
-#include 
+#include 
+#include 
 #include 
+#include 
+#include 
+#include 
+#include 
 
-#include 
 #include 
-#include 
+#include 
 #include 
-#include 
+#include 
+
+#include "asp.h"
 #include "cpuidle.h"
 #include "sram.h"
 
+#ifndef CONFIG_COMMON_CLK
+#include 
 #include "clock.h"
-#include "asp.h"
+#endif
 
 #define DA8XX_TPCC_BASE0x01c0
 #define DA8XX_TPTC0_BASE   0x01c08000
@@ -1040,6 +1045,7 @@ int __init da8xx_register_spi_bus(int instance, unsigned 
num_chipselect)
 }
 
 #ifdef CONFIG_ARCH_DAVINCI_DA850
+#ifndef CONFIG_COMMON_CLK
 static struct clk sata_refclk = {
.name   = "sata_refclk",
.set_rate   = davinci_simple_set_rate,
@@ -1061,6 +1067,18 @@ int __init da850_register_sata_refclk(int rate)
 
return 0;
 }
+#else
+int __init da850_register_sata_refclk(int rate)
+{
+   struct clk *clk;
+
+   clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);
+   if (IS_ERR(clk))
+   return PTR_ERR(clk);
+
+   return clk_register_clkdev(clk, "refclk", "ahci_da850");
+}
+#endif
 
 static struct resource da850_sata_resources[] = {
{
-- 
2.17.0

[PATCH v11 11/27] ARM: davinci: da8xx: add new USB PHY clock init using common clock framework

This adds the new USB PHY clock init in mach-davinci/usb-da8xx.c using
the new common clock framework drivers.

The #ifdefs are needed to prevent compile errors until the entire
ARCH_DAVINCI is converted.

Signed-off-by: David Lechner 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- none

v8 changes:
- rebased on "ARM: davinci: DA8XX: fix oops in USB PHY driver due to stack
  allocated platform platform_data"

v7 changes:
- register platform device instead of registering clocks directly
- USB PHY clocks now treated as single device instead of registering them
  separately

v6 changes:
- rename stuff to match changes in "clk: davinci: New driver for TI DA8XX USB
  PHY clocks"
- take advantage of syscon lookup changes in "mfd: syscon: Add syscon_register()
  function"


 arch/arm/mach-davinci/board-da830-evm.c |  8 ++-
 arch/arm/mach-davinci/board-omapl138-hawk.c |  9 +--
 arch/arm/mach-davinci/da8xx-dt.c|  8 ++-
 arch/arm/mach-davinci/include/mach/da8xx.h  |  1 +
 arch/arm/mach-davinci/usb-da8xx.c   | 26 +++--
 5 files changed, 46 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c 
b/arch/arm/mach-davinci/board-da830-evm.c
index 74df37821abe..ccddbae951d6 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -110,6 +110,12 @@ static __init void da830_evm_usb_init(void)
 {
int ret;
 
+#ifdef CONFIG_COMMON_CLK
+   ret = da8xx_register_usb_phy_clocks();
+   if (ret)
+   pr_warn("%s: USB PHY CLK registration failed: %d\n",
+   __func__, ret);
+#else
/* USB_REFCLKIN is not used. */
ret = da8xx_register_usb20_phy_clk(false);
if (ret)
@@ -120,7 +126,7 @@ static __init void da830_evm_usb_init(void)
if (ret)
pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n",
__func__, ret);
-
+#endif
ret = da8xx_register_usb_phy();
if (ret)
pr_warn("%s: USB PHY registration failed: %d\n",
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c 
b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 7653e9425d44..949ca567e965 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -235,7 +235,12 @@ static __init void omapl138_hawk_usb_init(void)
pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret);
return;
}
-
+#ifdef CONFIG_COMMON_CLK
+   ret = da8xx_register_usb_phy_clocks();
+   if (ret)
+   pr_warn("%s: USB PHY CLK registration failed: %d\n",
+   __func__, ret);
+#else
ret = da8xx_register_usb20_phy_clk(false);
if (ret)
pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n",
@@ -245,7 +250,7 @@ static __init void omapl138_hawk_usb_init(void)
if (ret)
pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n",
__func__, ret);
-
+#endif
ret = da8xx_register_usb_phy();
if (ret)
pr_warn("%s: USB PHY registration failed: %d\n",
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 91dd9cb6d113..c4edf051ef9b 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -69,6 +69,12 @@ static void __init da850_init_machine(void)
 
da850_register_clocks();
 
+#ifdef CONFIG_COMMON_CLK
+   ret = da8xx_register_usb_phy_clocks();
+   if (ret)
+   pr_warn("%s: USB PHY CLK registration failed: %d\n",
+   __func__, ret);
+#else
ret = da8xx_register_usb20_phy_clk(false);
if (ret)
pr_warn("%s: registering USB 2.0 PHY clock failed: %d",
@@ -77,7 +83,7 @@ static void __init da850_init_machine(void)
if (ret)
pr_warn("%s: registering USB 1.1 PHY clock failed: %d",
__func__, ret);
-
+#endif
ret = da850_register_sata_refclk(sata_refclkpn);
if (ret)
pr_warn("%s: registering SATA REFCLK failed: %d",
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h 
b/arch/arm/mach-davinci/include/mach/da8xx.h
index 612e45437cec..5d7b1de9aa7e 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -106,6 +106,7 @@ int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
 int da8xx_register_usb_refclkin(int rate);
 int da8xx_register_usb20_phy_clk(bool use_usb_refclkin);
 int da8xx_register_usb11_phy_clk(bool use_usb_refclkin);
+int da8xx_register_usb_phy_clocks(void);
 int da850_register_sata_refclk(int rate);
 int da8xx_register_emac(void);
 int da8xx_register_uio_pruss(void);
diff --git a/arch/arm/mach-davinci/usb-da8xx.c 
b/arch/arm/mach-davinci/usb-da8xx.c
index 50445f0e98de..c8d2f3075e69 100644
--- a/arch/arm/mach-davinci/usb-da8xx.c
+++ b/arch

[PATCH v11 13/27] ARM: davinci: remove CONFIG_DAVINCI_RESET_CLOCKS

The common clock framework will take care of disabling unused clocks when
we switch from the legacy davinci clocks and having this enabled will
cause compile errors after we switch, so remove it now.

Signed-off-by: David Lechner 
Reviewed-by: Sekhar Nori 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- none

v8 changes:
- none

v7 changes:
- none

v6 changes:
- none


 arch/arm/mach-davinci/Kconfig   | 12 
 arch/arm/mach-davinci/common.c  |  1 -
 arch/arm/mach-davinci/include/mach/common.h |  6 --
 3 files changed, 19 deletions(-)

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 05c3eecf47cb..ba9912b4dfab 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -231,18 +231,6 @@ config DAVINCI_MUX_WARNINGS
  to change the pin multiplexing setup. When there are no warnings
  printed, it's safe to deselect DAVINCI_MUX for your product.
 
-config DAVINCI_RESET_CLOCKS
-   bool "Reset unused clocks during boot"
-   depends on ARCH_DAVINCI
-   help
- Say Y if you want to reset unused clocks during boot.
- This option saves power, but assumes all drivers are
- using the clock framework. Broken drivers that do not
- yet use clock framework may not work with this option.
- If you are booting from another operating system, you
- probably do not want this option enabled until your
- device drivers work properly.
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index bcb6a7ba84e9..e03f95ccd95c 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -118,5 +118,4 @@ void __init davinci_common_init(const struct 
davinci_soc_info *soc_info)
 void __init davinci_init_late(void)
 {
davinci_cpufreq_init();
-   davinci_clk_disable_unused();
 }
diff --git a/arch/arm/mach-davinci/include/mach/common.h 
b/arch/arm/mach-davinci/include/mach/common.h
index 5f45d0ac66a8..ded8f5f42725 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -83,12 +83,6 @@ extern void davinci_common_init(const struct 
davinci_soc_info *soc_info);
 extern void davinci_init_ide(void);
 void davinci_init_late(void);
 
-#ifdef CONFIG_DAVINCI_RESET_CLOCKS
-int davinci_clk_disable_unused(void);
-#else
-static inline int davinci_clk_disable_unused(void) { return 0; }
-#endif
-
 #ifdef CONFIG_CPU_FREQ
 int davinci_cpufreq_init(void);
 #else
-- 
2.17.0

[PATCH v11 14/27] ARM: davinci_all_defconfig: remove CONFIG_DAVINCI_RESET_CLOCKS

This removes CONFIG_DAVINCI_RESET_CLOCKS. The option has been removed from
the kernel.

Signed-off-by: David Lechner 
Reviewed-by: Sekhar Nori 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- none

v8 changes:
- none

v7 changes:
- none

v6 changes:
- none


 arch/arm/configs/davinci_all_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/configs/davinci_all_defconfig 
b/arch/arm/configs/davinci_all_defconfig
index 21b2d7791df4..f83ea4131df2 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -31,7 +31,6 @@ CONFIG_MACH_MITYOMAPL138=y
 CONFIG_MACH_OMAPL138_HAWKBOARD=y
 CONFIG_DAVINCI_MUX_DEBUG=y
 CONFIG_DAVINCI_MUX_WARNINGS=y
-CONFIG_DAVINCI_RESET_CLOCKS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_CMA=y
-- 
2.17.0

[PATCH v11 19/27] ARM: davinci: dm365: Remove legacy clock init

This removes the unused legacy clock init code from
arch/arm/mach-davinci/dm365.c.

Signed-off-by: David Lechner 
Reviewed-by: Sekhar Nori 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- rebased

v8 changes:
- none

v7 changes:
- rebased
- add davinci prefix to commit message

v6 changes:
- rebased


 arch/arm/mach-davinci/dm365.c | 449 --
 1 file changed, 449 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 76de426a0e41..abcf2a5ed89b 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -40,11 +40,6 @@
 #include "davinci.h"
 #include "mux.h"
 
-#ifndef CONFIG_COMMON_CLK
-#include "clock.h"
-#include "psc.h"
-#endif
-
 #define DM365_REF_FREQ 2400/* 24 MHz on the DM365 EVM */
 #define DM365_RTC_BASE 0x01c69000
 #define DM365_KEYSCAN_BASE 0x01c69400
@@ -60,441 +55,6 @@
 #define DM365_EMAC_CNTRL_RAM_OFFSET0x1000
 #define DM365_EMAC_CNTRL_RAM_SIZE  0x2000
 
-#ifndef CONFIG_COMMON_CLK
-static struct pll_data pll1_data = {
-   .num= 1,
-   .phys_base  = DAVINCI_PLL1_BASE,
-   .flags  = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
-};
-
-static struct pll_data pll2_data = {
-   .num= 2,
-   .phys_base  = DAVINCI_PLL2_BASE,
-   .flags  = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
-};
-
-static struct clk ref_clk = {
-   .name   = "ref_clk",
-   .rate   = DM365_REF_FREQ,
-};
-
-static struct clk pll1_clk = {
-   .name   = "pll1",
-   .parent = &ref_clk,
-   .flags  = CLK_PLL,
-   .pll_data   = &pll1_data,
-};
-
-static struct clk pll1_aux_clk = {
-   .name   = "pll1_aux_clk",
-   .parent = &pll1_clk,
-   .flags  = CLK_PLL | PRE_PLL,
-};
-
-static struct clk pll1_sysclkbp = {
-   .name   = "pll1_sysclkbp",
-   .parent = &pll1_clk,
-   .flags  = CLK_PLL | PRE_PLL,
-   .div_reg= BPDIV
-};
-
-static struct clk clkout0_clk = {
-   .name   = "clkout0",
-   .parent = &pll1_clk,
-   .flags  = CLK_PLL | PRE_PLL,
-};
-
-static struct clk pll1_sysclk1 = {
-   .name   = "pll1_sysclk1",
-   .parent = &pll1_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV1,
-};
-
-static struct clk pll1_sysclk2 = {
-   .name   = "pll1_sysclk2",
-   .parent = &pll1_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV2,
-};
-
-static struct clk pll1_sysclk3 = {
-   .name   = "pll1_sysclk3",
-   .parent = &pll1_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV3,
-};
-
-static struct clk pll1_sysclk4 = {
-   .name   = "pll1_sysclk4",
-   .parent = &pll1_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV4,
-};
-
-static struct clk pll1_sysclk5 = {
-   .name   = "pll1_sysclk5",
-   .parent = &pll1_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV5,
-};
-
-static struct clk pll1_sysclk6 = {
-   .name   = "pll1_sysclk6",
-   .parent = &pll1_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV6,
-};
-
-static struct clk pll1_sysclk7 = {
-   .name   = "pll1_sysclk7",
-   .parent = &pll1_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV7,
-};
-
-static struct clk pll1_sysclk8 = {
-   .name   = "pll1_sysclk8",
-   .parent = &pll1_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV8,
-};
-
-static struct clk pll1_sysclk9 = {
-   .name   = "pll1_sysclk9",
-   .parent = &pll1_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV9,
-};
-
-static struct clk pll2_clk = {
-   .name   = "pll2",
-   .parent = &ref_clk,
-   .flags  = CLK_PLL,
-   .pll_data   = &pll2_data,
-};
-
-static struct clk pll2_aux_clk = {
-   .name   = "pll2_aux_clk",
-   .parent = &pll2_clk,
-   .flags  = CLK_PLL | PRE_PLL,
-};
-
-static struct clk clkout1_clk = {
-   .name   = "clkout1",
-   .parent = &pll2_clk,
-   .flags  = CLK_PLL | PRE_PLL,
-};
-
-static struct clk pll2_sysclk1 = {
-   .name   = "pll2_sysclk1",
-   .parent = &pll2_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV1,
-};
-
-static struct clk pll2_sysclk2 = {
-   .name   = "pll2_sysclk2",
-   .parent = &pll2_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV2,
-};
-
-static struct clk pll2_sysclk3 = {
-   .name   = "pll2_sysclk3",
-   .parent = &pll2_clk,
-   .flags  = CL

Re: [RFC PATCH 07/11] ext4: have sync_fs op report writeback errors when passed a since pointer

2018-05-18 Thread Jeff Layton

On Fri, 2018-05-18 at 08:22 -0700, Matthew Wilcox wrote:
> On Fri, May 18, 2018 at 08:34:11AM -0400, Jeff Layton wrote:
> > From: Jeff Layton 
> > 
> > When ext4_sync_fs gets a non-NULL since pointer, use it to report
> > errors vs. the errseq_t in the super_block. This allows us to
> > properly report an error to sync_fs when any inode has failed writeback
> > since we last checked for it.
> > 
> > Signed-off-by: Jeff Layton 
> > ---
> >  fs/ext4/super.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/fs/ext4/super.c b/fs/ext4/super.c
> > index 896ddf8c3421..a5f41d31611f 100644
> > --- a/fs/ext4/super.c
> > +++ b/fs/ext4/super.c
> > @@ -4898,6 +4898,8 @@ static int ext4_sync_fs(struct super_block *sb, int 
> > wait, errseq_t *since)
> > }
> >  out:
> > ret2 = __sync_blockdev(sb->s_bdev, wait);
> > +   if (since)
> > +   ret2 = errseq_check_and_advance(&sb->s_wb_err, since);
> > return ret ? ret : ret2;
> >  }
> 
> This is inconsistent with the ext2 and xfs implementations ...
> 
> I'm worried this is too much complexity to push down to the filesystems.
> When should errors get reported through the return value; when should they
> be reported through the errseq_t?
> 
> Can we hide all of this?  Maybe ext4 could do:
> 
>   errseq_set(&sb->s_wb_err, __sync_blockdev(sb->s_bdev, wait));
>   return ret;
> 

I'm not sure I understand what you intend here. If __sync_blockdev
fails, then the error should have already been marked in sb->s_wb_err
(via patch #6). We wouldn't want to record that again at syncfs time.
Note that __sync_blockdev will return errors based on the legacy
AS_EIO/AS_ENOSPC flags.

We really do need to record it in the superblock as soon as possible
after an error occurs. If we want to allow userland to eventually be
able to scrape this value out of the kernel (as we discussed at LSF/MM)
then we can't assume that it'll be doing any sort of syncfs call
beforehand.

The main reason to push this down into the filesystems is to allow them
control over whether to report errors at syncfs time via the superblock
errseq_t or not. If we don't really care about allowing this to be an
opt-in thing, then we could just take the patch that I sent on April
17th:

[PATCH] fs: track per-sb writeback errors and report them to syncfs

We'd also want patch #6 from this series, I think, but that's more or
less enough to implement this over all filesystems, assuming they use
mapping_set_error to record writeback errors. I'm fine with either
approach.

> (we'd need to make calling errseq_set(x, 0) be a no-op instead of an error)
> 
> and then the caller is the one who takes care of calling
> errseq_check_and_advance() so we don't have to pass 'since' into each
> filesystem.

Re: [PATCH v4 1/2] dt-bindings: input: Add Add Spreadtrum SC27xx vibrator documentation

On Thu, May 10, 2018 at 01:08:33PM +0800, Baolin Wang wrote:
> From: Xiaotong Lu 
> 
> This patch adds the binding documentation for Spreadtrum SC27xx series
> vibrator device.
> 
> Signed-off-by: Xiaotong Lu 
> Signed-off-by: Baolin Wang 
> ---
> Changes since v3:
>  - Change compatible string to explicit Soc name.
>  - Add parent MFD node.
> 
> Changes since v2:
>  - No updates.
> 
> Changes since v1:
>   - No updates.
> ---
>  .../bindings/input/sprd,sc27xx-vibra.txt   |   23 
> 
>  1 file changed, 23 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/input/sprd,sc27xx-vibra.txt

Reviewed-by: Rob Herring

[PATCH v11 17/27] ARM: davinci: da850: Remove legacy clock init

This removes the unused legacy clock init code from
arch/arm/mach-davinci/da850.c.

Signed-off-by: David Lechner 
Reviewed-by: Sekhar Nori 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- rebased

v8 changes:
- none

v7 changes:
- rebased
- add davinci prefix to commit message

v6 changes:
- rebased


 arch/arm/mach-davinci/board-omapl138-hawk.c |  12 +-
 arch/arm/mach-davinci/da850.c   | 653 +---
 arch/arm/mach-davinci/da8xx-dt.c|  12 +-
 3 files changed, 3 insertions(+), 674 deletions(-)

diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c 
b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 949ca567e965..466e87b24e9a 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -235,22 +235,12 @@ static __init void omapl138_hawk_usb_init(void)
pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret);
return;
}
-#ifdef CONFIG_COMMON_CLK
+
ret = da8xx_register_usb_phy_clocks();
if (ret)
pr_warn("%s: USB PHY CLK registration failed: %d\n",
__func__, ret);
-#else
-   ret = da8xx_register_usb20_phy_clk(false);
-   if (ret)
-   pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n",
-   __func__, ret);
 
-   ret = da8xx_register_usb11_phy_clk(false);
-   if (ret)
-   pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n",
-   __func__, ret);
-#endif
ret = da8xx_register_usb_phy();
if (ret)
pr_warn("%s: USB PHY registration failed: %d\n",
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 9e00beb943c9..4528bbf0c861 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -38,559 +38,12 @@
 
 #include "mux.h"
 
-#ifndef CONFIG_COMMON_CLK
-#include "clock.h"
-#include "psc.h"
-#endif
-
 #define DA850_PLL1_BASE0x01e1a000
 #define DA850_TIMER64P2_BASE   0x01f0c000
 #define DA850_TIMER64P3_BASE   0x01f0d000
 
 #define DA850_REF_FREQ 2400
 
-#ifndef CONFIG_COMMON_CLK
-static int da850_set_armrate(struct clk *clk, unsigned long rate);
-static int da850_round_armrate(struct clk *clk, unsigned long rate);
-static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
-
-static struct pll_data pll0_data = {
-   .num= 1,
-   .phys_base  = DA8XX_PLL0_BASE,
-   .flags  = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
-};
-
-static struct clk ref_clk = {
-   .name   = "ref_clk",
-   .rate   = DA850_REF_FREQ,
-   .set_rate   = davinci_simple_set_rate,
-};
-
-static struct clk pll0_clk = {
-   .name   = "pll0",
-   .parent = &ref_clk,
-   .pll_data   = &pll0_data,
-   .flags  = CLK_PLL,
-   .set_rate   = da850_set_pll0rate,
-};
-
-static struct clk pll0_aux_clk = {
-   .name   = "pll0_aux_clk",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL | PRE_PLL,
-};
-
-static struct clk pll0_sysclk1 = {
-   .name   = "pll0_sysclk1",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV1,
-};
-
-static struct clk pll0_sysclk2 = {
-   .name   = "pll0_sysclk2",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV2,
-};
-
-static struct clk pll0_sysclk3 = {
-   .name   = "pll0_sysclk3",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV3,
-   .set_rate   = davinci_set_sysclk_rate,
-   .maxrate= 1,
-};
-
-static struct clk pll0_sysclk4 = {
-   .name   = "pll0_sysclk4",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV4,
-};
-
-static struct clk pll0_sysclk5 = {
-   .name   = "pll0_sysclk5",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV5,
-};
-
-static struct clk pll0_sysclk6 = {
-   .name   = "pll0_sysclk6",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV6,
-};
-
-static struct clk pll0_sysclk7 = {
-   .name   = "pll0_sysclk7",
-   .parent = &pll0_clk,
-   .flags  = CLK_PLL,
-   .div_reg= PLLDIV7,
-};
-
-static struct pll_data pll1_data = {
-   .num= 2,
-   .phys_base  = DA850_PLL1_BASE,
-   .flags  = PLL_HAS_POSTDIV,
-};
-
-static struct clk pll1_clk = {
-   .name   = "pll1",
-   .parent = &ref_clk,
-   .pll_data   = &pll1_data,
-   .flags  = CLK_PLL,
-};
-
-static struct clk pll1_aux_clk = {
-   .name   = "pll1_aux_clk",
-   .paren

[PATCH v11 18/27] ARM: davinci: dm355: Remove legacy clock init

This removes the unused legacy clock init code from
arch/arm/mach-davinci/dm355.c.

Signed-off-by: David Lechner 
Reviewed-by: Sekhar Nori 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- rebased

v8 changes:
- none

v7 changes:
- rebased
- add davinci prefix to commit message

v6 changes:
- rebased


 arch/arm/mach-davinci/dm355.c | 357 --
 1 file changed, 357 deletions(-)

diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 14014b942e8a..9f7d38d12c88 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -35,11 +35,6 @@
 #include "davinci.h"
 #include "mux.h"
 
-#ifndef CONFIG_COMMON_CLK
-#include "clock.h"
-#include "psc.h"
-#endif
-
 #define DM355_UART2_BASE   (IO_PHYS + 0x206000)
 #define DM355_OSD_BASE (IO_PHYS + 0x70200)
 #define DM355_VENC_BASE(IO_PHYS + 0x70400)
@@ -49,349 +44,6 @@
  */
 #define DM355_REF_FREQ 2400/* 24 or 36 MHz */
 
-#ifndef CONFIG_COMMON_CLK
-static struct pll_data pll1_data = {
-   .num   = 1,
-   .phys_base = DAVINCI_PLL1_BASE,
-   .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
-};
-
-static struct pll_data pll2_data = {
-   .num   = 2,
-   .phys_base = DAVINCI_PLL2_BASE,
-   .flags = PLL_HAS_PREDIV,
-};
-
-static struct clk ref_clk = {
-   .name = "ref_clk",
-   /* FIXME -- crystal rate is board-specific */
-   .rate = DM355_REF_FREQ,
-};
-
-static struct clk pll1_clk = {
-   .name = "pll1",
-   .parent = &ref_clk,
-   .flags = CLK_PLL,
-   .pll_data = &pll1_data,
-};
-
-static struct clk pll1_aux_clk = {
-   .name = "pll1_aux_clk",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL | PRE_PLL,
-};
-
-static struct clk pll1_sysclk1 = {
-   .name = "pll1_sysclk1",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV1,
-};
-
-static struct clk pll1_sysclk2 = {
-   .name = "pll1_sysclk2",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV2,
-};
-
-static struct clk pll1_sysclk3 = {
-   .name = "pll1_sysclk3",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV3,
-};
-
-static struct clk pll1_sysclk4 = {
-   .name = "pll1_sysclk4",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV4,
-};
-
-static struct clk pll1_sysclkbp = {
-   .name = "pll1_sysclkbp",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL | PRE_PLL,
-   .div_reg = BPDIV
-};
-
-static struct clk vpss_dac_clk = {
-   .name = "vpss_dac",
-   .parent = &pll1_sysclk3,
-   .lpsc = DM355_LPSC_VPSS_DAC,
-};
-
-static struct clk vpss_master_clk = {
-   .name = "vpss_master",
-   .parent = &pll1_sysclk4,
-   .lpsc = DAVINCI_LPSC_VPSSMSTR,
-   .flags = CLK_PSC,
-};
-
-static struct clk vpss_slave_clk = {
-   .name = "vpss_slave",
-   .parent = &pll1_sysclk4,
-   .lpsc = DAVINCI_LPSC_VPSSSLV,
-};
-
-static struct clk clkout1_clk = {
-   .name = "clkout1",
-   .parent = &pll1_aux_clk,
-   /* NOTE:  clkout1 can be externally gated by muxing GPIO-18 */
-};
-
-static struct clk clkout2_clk = {
-   .name = "clkout2",
-   .parent = &pll1_sysclkbp,
-};
-
-static struct clk pll2_clk = {
-   .name = "pll2",
-   .parent = &ref_clk,
-   .flags = CLK_PLL,
-   .pll_data = &pll2_data,
-};
-
-static struct clk pll2_sysclk1 = {
-   .name = "pll2_sysclk1",
-   .parent = &pll2_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV1,
-};
-
-static struct clk pll2_sysclkbp = {
-   .name = "pll2_sysclkbp",
-   .parent = &pll2_clk,
-   .flags = CLK_PLL | PRE_PLL,
-   .div_reg = BPDIV
-};
-
-static struct clk clkout3_clk = {
-   .name = "clkout3",
-   .parent = &pll2_sysclkbp,
-   /* NOTE:  clkout3 can be externally gated by muxing GPIO-16 */
-};
-
-static struct clk arm_clk = {
-   .name = "arm_clk",
-   .parent = &pll1_sysclk1,
-   .lpsc = DAVINCI_LPSC_ARM,
-   .flags = ALWAYS_ENABLED,
-};
-
-/*
- * NOT LISTED below, and not touched by Linux
- *   - in SyncReset state by default
- * .lpsc = DAVINCI_LPSC_TPCC,
- * .lpsc = DAVINCI_LPSC_TPTC0,
- * .lpsc = DAVINCI_LPSC_TPTC1,
- * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
- * .lpsc = DAVINCI_LPSC_MEMSTICK,
- *   - in Enabled state by default
- * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
- * .lpsc = DAVINCI_LPSC_SCR2,  // "bus"
- * .lpsc = DAVINCI_LPSC_SCR3,  // "bus"
- * .lpsc = DAVINCI_LPSC_SCR4,  // "bus"
- * .lpsc = DAVINCI_LPSC_CROSSBAR,  // "emulation"
- * .lpsc = DAVINCI_LPSC_CFG27, // "test"
- * .lpsc = DAVINCI_LPSC_CFG3,  // "test"
- * .lpsc = DAVINCI_LPSC_CFG5,  // "test"
- */
-
-static struct clk mjcp_clk = {
-   .name = "mjcp",
-   .parent = &pll1_sysclk1,
-   .lpsc = DAVINCI_LPSC_IMCOP,
-};
-
-static struct clk

[PATCH v11 23/27] ARM: davinci: remove legacy clocks

This removes the unused legacy clock code from arch/arm/mach-davinci/.

Signed-off-by: David Lechner 
Reviewed-by: Sekhar Nori 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- none

v8 changes:
- none

v7 changes:
- rebased
- add davinci prefix to commit message

v6 changes:
- rebased


 arch/arm/mach-davinci/clock.c   | 745 
 arch/arm/mach-davinci/clock.h   |  72 --
 arch/arm/mach-davinci/common.c  |   2 -
 arch/arm/mach-davinci/devices.c |   1 -
 arch/arm/mach-davinci/include/mach/clock.h  |   3 -
 arch/arm/mach-davinci/include/mach/common.h |   2 -
 arch/arm/mach-davinci/psc.c | 137 
 arch/arm/mach-davinci/psc.h |  10 -
 arch/arm/mach-davinci/time.c|   2 -
 9 files changed, 974 deletions(-)
 delete mode 100644 arch/arm/mach-davinci/clock.c
 delete mode 100644 arch/arm/mach-davinci/psc.c

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
deleted file mode 100644
index f77a4f766050..
--- a/arch/arm/mach-davinci/clock.c
+++ /dev/null
@@ -1,745 +0,0 @@
-/*
- * Clock and PLL control for DaVinci devices
- *
- * Copyright (C) 2006-2007 Texas Instruments.
- * Copyright (C) 2008-2009 Deep Root Systems, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include 
-
-#include 
-#include "psc.h"
-#include 
-#include "clock.h"
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-static DEFINE_SPINLOCK(clockfw_lock);
-
-void davinci_clk_enable(struct clk *clk)
-{
-   if (clk->parent)
-   davinci_clk_enable(clk->parent);
-   if (clk->usecount++ == 0) {
-   if (clk->flags & CLK_PSC)
-   davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
-  true, clk->flags);
-   else if (clk->clk_enable)
-   clk->clk_enable(clk);
-   }
-}
-
-void davinci_clk_disable(struct clk *clk)
-{
-   if (WARN_ON(clk->usecount == 0))
-   return;
-   if (--clk->usecount == 0) {
-   if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC))
-   davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
-  false, clk->flags);
-   else if (clk->clk_disable)
-   clk->clk_disable(clk);
-   }
-   if (clk->parent)
-   davinci_clk_disable(clk->parent);
-}
-
-int davinci_clk_reset(struct clk *clk, bool reset)
-{
-   unsigned long flags;
-
-   if (clk == NULL || IS_ERR(clk))
-   return -EINVAL;
-
-   spin_lock_irqsave(&clockfw_lock, flags);
-   if (clk->flags & CLK_PSC)
-   davinci_psc_reset(clk->gpsc, clk->lpsc, reset);
-   spin_unlock_irqrestore(&clockfw_lock, flags);
-
-   return 0;
-}
-EXPORT_SYMBOL(davinci_clk_reset);
-
-int davinci_clk_reset_assert(struct clk *clk)
-{
-   if (clk == NULL || IS_ERR(clk) || !clk->reset)
-   return -EINVAL;
-
-   return clk->reset(clk, true);
-}
-EXPORT_SYMBOL(davinci_clk_reset_assert);
-
-int davinci_clk_reset_deassert(struct clk *clk)
-{
-   if (clk == NULL || IS_ERR(clk) || !clk->reset)
-   return -EINVAL;
-
-   return clk->reset(clk, false);
-}
-EXPORT_SYMBOL(davinci_clk_reset_deassert);
-
-int clk_enable(struct clk *clk)
-{
-   unsigned long flags;
-
-   if (!clk)
-   return 0;
-   else if (IS_ERR(clk))
-   return -EINVAL;
-
-   spin_lock_irqsave(&clockfw_lock, flags);
-   davinci_clk_enable(clk);
-   spin_unlock_irqrestore(&clockfw_lock, flags);
-
-   return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-   unsigned long flags;
-
-   if (clk == NULL || IS_ERR(clk))
-   return;
-
-   spin_lock_irqsave(&clockfw_lock, flags);
-   davinci_clk_disable(clk);
-   spin_unlock_irqrestore(&clockfw_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-   if (clk == NULL || IS_ERR(clk))
-   return 0;
-
-   return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-   if (clk == NULL || IS_ERR(clk))
-   return 0;
-
-   if (clk->round_rate)
-   return clk->round_rate(clk, rate);
-
-   return clk->rate;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-/* Propagate rate to children */
-static void propagate_rate(struct clk *root)
-{
-   struct clk *clk;
-
-   list_for_each_entry(clk, &root->children, childnode) {
-   i

[PATCH v11 24/27] dt-bindings: timer: new bindings for TI DaVinci timer

This adds new device tree bindings for the timer IP block of TI
DaVinci-like SoCs.

Reviewed-by: Rob Herring 
Signed-off-by: David Lechner 
---

v11 changes:
- remove trailing whitespace

v10 changes:
- changed compatible to "ti,da830-timer"
- added interrupts and interrupt-names properties
- fixed grammatical error

v9 changes:
- new patch in v9


 .../bindings/timer/ti,davinci-timer.txt   | 37 +++
 1 file changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/ti,davinci-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt 
b/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt
new file mode 100644
index ..29bf91ccf5b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ti,davinci-timer.txt
@@ -0,0 +1,37 @@
+* Device tree bindings for Texas Instruments DaVinci timer
+
+This document provides bindings for the 64-bit timer in the DaVinci
+architecture devices. The timer can be configured as a general-purpose 64-bit
+timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
+timers, each half can operate in conjunction (chain mode) or independently
+(unchained mode) of each other.
+
+The timer is a free running up-counter and can generate interrupts when the
+counter reaches preset counter values.
+
+Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
+watchdog timers.
+
+Required properties:
+
+- compatible : should be "ti,da830-timer".
+- reg : specifies base physical address and count of the registers.
+- interrupts : interrupts generated by the timer.
+- interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1",
+  "cmpint2", "cmpint3", "cmpint4", "cmpint5", "cmpint6",
+  "cmpint7" ("cmpintX" may be omitted if not present in the
+  hardware).
+- clocks : the clock feeding the timer clock.
+
+Example:
+
+   clocksource: timer@2 {
+   compatible = "ti,da830-timer";
+   reg = <0x2 0x1000>;
+   interrupts = <21>, <22>, <74>, <75>, <76>, <77>, <78>, <79>,
+<80>, <81>;
+   interrupt-names = "tint12", "tint34", "cmpint0", "cmpint1",
+ "cmpint2", "cmpint3", "cmpint4", "cmpint5",
+ "cmpint6", "cmpint7";
+   clocks = <&pll0_auxclk>;
+   };
-- 
2.17.0

[PATCH v11 25/27] ARM: davinci: add device tree support to timer

This adds device tree support to the davinci timer so that when clocks
are moved to device tree, the timer will still work.

Signed-off-by: David Lechner 
---

v11 changes:
- drop fallback to ref_clk

v10 changes:
- change compatible to "ti,da830-timer"
- remove comment clocks as platform devices

v9 changes:
- none (there were supposed to be changed, but apparently they got squashed
  into the next commit - will fix on the next round)

v8 changes:
- none

v7 changes:
- rebased
- add davinci prefix to commit message

v6 changes:
- rebased

 arch/arm/mach-davinci/Kconfig |  1 +
 arch/arm/mach-davinci/time.c  | 15 +++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index ba9912b4dfab..da8a039d65f9 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -59,6 +59,7 @@ config MACH_DA8XX_DT
default y
depends on ARCH_DAVINCI_DA850
select PINCTRL
+   select TIMER_OF
help
  Say y here to include support for TI DaVinci DA850 based using
  Flattened Device Tree. More information at Documentation/devicetree
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 7ea3db0ff062..5a6de5368ab0 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -397,3 +398,17 @@ void __init davinci_timer_init(struct clk *timer_clk)
for (i=0; i< ARRAY_SIZE(timers); i++)
timer32_config(&timers[i]);
 }
+
+static int __init of_davinci_timer_init(struct device_node *np)
+{
+   struct clk *clk;
+
+   clk = of_clk_get(np, 0);
+   if (IS_ERR(clk))
+   return PTR_ERR(clk);
+
+   davinci_timer_init(clk);
+
+   return 0;
+}
+TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_init);
-- 
2.17.0

[PATCH v11 26/27] ARM: davinci: da8xx-dt: switch to device tree clocks

This removes all of the clock init code from da8xx-dt.c. This includes
all of the OF_DEV_AUXDATA that was just used for looking up clocks.

Signed-off-by: David Lechner 
---

v11 changes:
- none

v10 changes:
- removed unused header files
- removed arch/arm/mach-davinci/time.c changes accidentally introduced in v9

v9 changes:
- changes to arch/arm/mach-davinci/time.c accidentally got squashed into this
  commit. will drop this later.

v8 changes:
- none

v7 changes:
- rebased
- drop of_platform_default_populate(NULL, NULL, NULL)
- add change in pm_domain.c

v6 changes:
- removed misleading statement from commit message


 arch/arm/mach-davinci/da8xx-dt.c  | 64 ---
 arch/arm/mach-davinci/pm_domain.c |  5 +++
 2 files changed, 5 insertions(+), 64 deletions(-)

diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 088bc5c0318b..beac80ec4037 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -7,79 +7,16 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include 
-#include 
-#include 
-#include 
-#include 
 
 #include 
 
 #include 
-#include "cp_intc.h"
 #include 
 
-static struct of_dev_auxdata da850_aemif_auxdata_lookup[] = {
-   OF_DEV_AUXDATA("ti,davinci-nand", 0x6200, "davinci-nand.0", NULL),
-   {}
-};
-
-static struct aemif_platform_data aemif_data = {
-   .dev_lookup = da850_aemif_auxdata_lookup,
-};
-
-static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
-   OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL),
-   OF_DEV_AUXDATA("ti,davinci-i2c", 0x01e28000, "i2c_davinci.2", NULL),
-   OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "davinci-wdt", NULL),
-   OF_DEV_AUXDATA("ti,da830-mmc", 0x01c4, "da830-mmc.0", NULL),
-   OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f0, "ehrpwm.0", NULL),
-   OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f02000, "ehrpwm.1", NULL),
-   OF_DEV_AUXDATA("ti,da850-ecap", 0x01f06000, "ecap.0", NULL),
-   OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap.1", NULL),
-   OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap.2", NULL),
-   OF_DEV_AUXDATA("ti,da830-spi", 0x01c41000, "spi_davinci.0", NULL),
-   OF_DEV_AUXDATA("ti,da830-spi", 0x01f0e000, "spi_davinci.1", NULL),
-   OF_DEV_AUXDATA("ns16550a", 0x01c42000, "serial8250.0", NULL),
-   OF_DEV_AUXDATA("ns16550a", 0x01d0c000, "serial8250.1", NULL),
-   OF_DEV_AUXDATA("ns16550a", 0x01d0d000, "serial8250.2", NULL),
-   OF_DEV_AUXDATA("ti,davinci_mdio", 0x01e24000, "davinci_mdio.0", NULL),
-   OF_DEV_AUXDATA("ti,davinci-dm6467-emac", 0x01e2, "davinci_emac.1",
-  NULL),
-   OF_DEV_AUXDATA("ti,da830-mcasp-audio", 0x01d0, "davinci-mcasp.0", 
NULL),
-   OF_DEV_AUXDATA("ti,da850-aemif", 0x6800, "ti-aemif", &aemif_data),
-   OF_DEV_AUXDATA("ti,da850-tilcdc", 0x01e13000, "da8xx_lcdc.0", NULL),
-   OF_DEV_AUXDATA("ti,da830-ohci", 0x01e25000, "ohci-da8xx", NULL),
-   OF_DEV_AUXDATA("ti,da830-musb", 0x01e0, "musb-da8xx", NULL),
-   OF_DEV_AUXDATA("ti,da830-usb-phy", 0x01c1417c, "da8xx-usb-phy", NULL),
-   OF_DEV_AUXDATA("ti,da850-ahci", 0x01e18000, "ahci_da850", NULL),
-   OF_DEV_AUXDATA("ti,da850-vpif", 0x01e17000, "vpif", NULL),
-   OF_DEV_AUXDATA("ti,da850-dsp", 0x1180, "davinci-rproc.0", NULL),
-   {}
-};
-
 #ifdef CONFIG_ARCH_DAVINCI_DA850
 
 static void __init da850_init_machine(void)
 {
-   /* All existing boards use 100MHz SATA refclkpn */
-   static const unsigned long sata_refclkpn = 100 * 1000 * 1000;
-
-   int ret;
-
-   da850_register_clocks();
-
-   ret = da8xx_register_usb_phy_clocks();
-   if (ret)
-   pr_warn("%s: USB PHY CLK registration failed: %d\n",
-   __func__, ret);
-
-   ret = da850_register_sata_refclk(sata_refclkpn);
-   if (ret)
-   pr_warn("%s: registering SATA REFCLK failed: %d",
-   __func__, ret);
-
-   of_platform_default_populate(NULL, da850_auxdata_lookup, NULL);
davinci_pm_init();
pdata_quirks_init();
 }
@@ -94,7 +31,6 @@ static const char *const da850_boards_compat[] __initconst = {
 
 DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x")
.map_io = da850_init,
-   .init_time  = da850_init_time,
.init_machine   = da850_init_machine,
.dt_compat  = da850_boards_compat,
.init_late  = davinci_init_late,
diff --git a/arch/arm/mach-davinci/pm_domain.c 
b/arch/arm/mach-davinci/pm_domain.c
index 78eac2c0c146..e251fd593bfd 100644
--- a/arch/arm/mach-davinci/pm_domain.c
+++ b/arch/arm/mach-davinci/pm_domain.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 
 static struct dev_pm_domain davinci_pm_domain = {
.ops = {
@@ -28,6 +29,10 @@ static struct pm_clk_notifier_bloc

[PATCH v11 27/27] ARM: dts: da850: Add clocks

This adds clock provider nodes for da850 and wires them up to all of the
devices.

Signed-off-by: David Lechner 
---

v11 changes:
- rebased

v10 changes:
- change compatible to "ti,da830-timer" and add interrupt and interrupt-names
  properties to new clocksource timer node

v9 changes:
- change mcasp and vpif nodes from clocks to power-domains

v8 changes:
- fix typo in clock-names property of psc0
- added power-domains properties to nodes that define that property in their
  device tree bindings

v7 changes:
- move ref_clk frequency to board-specific DT files
- enable sata_refclk in da850-lcdk.dts
- drop async2 fixed factor clock
- add power-domains for devices that use them
- fix USB PHY clock-names property
- move assigned-clocks to PSC device node
- drop clocks property from devices that don't use it (e.g. EDMA)
- add clock to RTC node
- add clock-ranges to usb0 and aemif nodes
- add clock-names property to aemif node
- fix typo in psc1 clock-names

v6 changes:
- updated for device tree bindings changes earlier in this series
- use single async2 clock instead of duplicate fixed factor clocks
- add clock-names property to mdio node


 arch/arm/boot/dts/da850-enbw-cmc.dts |   4 +
 arch/arm/boot/dts/da850-evm.dts  |   4 +
 arch/arm/boot/dts/da850-lcdk.dts |   9 ++
 arch/arm/boot/dts/da850-lego-ev3.dts |   4 +
 arch/arm/boot/dts/da850.dtsi | 168 +++
 5 files changed, 189 insertions(+)

diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts 
b/arch/arm/boot/dts/da850-enbw-cmc.dts
index 14dff3e188ed..0102ffc5aa53 100644
--- a/arch/arm/boot/dts/da850-enbw-cmc.dts
+++ b/arch/arm/boot/dts/da850-enbw-cmc.dts
@@ -35,6 +35,10 @@
};
 };
 
+&ref_clk {
+   clock-frequency = <2400>;
+};
+
 &edma0 {
ti,edma-reserved-slot-ranges = <32 50>;
 };
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 2e817da37fdb..6e0d84fda034 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -63,6 +63,10 @@
};
 };
 
+&ref_clk {
+   clock-frequency = <2400>;
+};
+
 &pmx_core {
status = "okay";
 
diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
index 0edf769ea95c..0177e3ed20fe 100644
--- a/arch/arm/boot/dts/da850-lcdk.dts
+++ b/arch/arm/boot/dts/da850-lcdk.dts
@@ -123,6 +123,10 @@
};
 };
 
+&ref_clk {
+   clock-frequency = <2400>;
+};
+
 &pmx_core {
status = "okay";
 
@@ -175,6 +179,11 @@
status = "okay";
 };
 
+&sata_refclk {
+   status = "okay";
+   clock-frequency = <1>;
+};
+
 &sata {
status = "okay";
 };
diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts 
b/arch/arm/boot/dts/da850-lego-ev3.dts
index ee3932475ce7..331362a6f01e 100644
--- a/arch/arm/boot/dts/da850-lego-ev3.dts
+++ b/arch/arm/boot/dts/da850-lego-ev3.dts
@@ -191,6 +191,10 @@
};
 };
 
+&ref_clk {
+   clock-frequency = <2400>;
+};
+
 &pmx_core {
status = "okay";
 
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index f6f1597b03df..de9a8bea100e 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -32,6 +32,25 @@
reg = <0xfffee000 0x2000>;
};
};
+   clocks: clocks {
+   ref_clk: ref_clk {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-output-names = "ref_clk";
+   };
+   sata_refclk: sata_refclk {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-output-names = "sata_refclk";
+   status = "disabled";
+   };
+   usb_refclkin: usb_refclkin {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-output-names = "usb_refclkin";
+   status = "disabled";
+   };
+   };
dsp: dsp@1180 {
compatible = "ti,da850-dsp";
reg = <0x1180 0x4>,
@@ -42,6 +61,7 @@
reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
interrupt-parent = <&intc>;
interrupts = <28>;
+   clocks = <&psc0 15>;
status = "disabled";
};
soc@1c0 {
@@ -52,6 +72,37 @@
ranges = <0x0 0x01c0 0x40>;
interrupt-parent = <&intc>;
 
+   psc0: clock-controller@1 {
+   compatible = "ti,da850-psc0";
+   reg = <0x1 0x1000>;
+   #clock-cells = <1>;
+   #power-domain-cells = <1>;
+   clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
+<&pll0_sysclk 4>, <&pll0_sysclk 6>,
+<&as

[PATCH v11 20/27] ARM: davinci: dm644x: Remove legacy clock init

This removes the unused legacy clock init code from
arch/arm/mach-davinci/dm644x.c.

Signed-off-by: David Lechner 
Reviewed-by: Sekhar Nori 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- rebased

v8 changes:
- none

v7 changes:
- rebased
- add davinci prefix to commit message

v6 changes:
- rebased


 arch/arm/mach-davinci/dm644x.c | 300 -
 1 file changed, 300 deletions(-)

diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index c3cd27c6cd70..0720da7809a6 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -32,11 +32,6 @@
 #include "davinci.h"
 #include "mux.h"
 
-#ifndef CONFIG_COMMON_CLK
-#include "clock.h"
-#include "psc.h"
-#endif
-
 /*
  * Device specific clocks
  */
@@ -49,292 +44,6 @@
 #define DM644X_EMAC_CNTRL_RAM_OFFSET   0x2000
 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
 
-#ifndef CONFIG_COMMON_CLK
-static struct pll_data pll1_data = {
-   .num   = 1,
-   .phys_base = DAVINCI_PLL1_BASE,
-};
-
-static struct pll_data pll2_data = {
-   .num   = 2,
-   .phys_base = DAVINCI_PLL2_BASE,
-};
-
-static struct clk ref_clk = {
-   .name = "ref_clk",
-   .rate = DM644X_REF_FREQ,
-};
-
-static struct clk pll1_clk = {
-   .name = "pll1",
-   .parent = &ref_clk,
-   .pll_data = &pll1_data,
-   .flags = CLK_PLL,
-};
-
-static struct clk pll1_sysclk1 = {
-   .name = "pll1_sysclk1",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV1,
-};
-
-static struct clk pll1_sysclk2 = {
-   .name = "pll1_sysclk2",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV2,
-};
-
-static struct clk pll1_sysclk3 = {
-   .name = "pll1_sysclk3",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV3,
-};
-
-static struct clk pll1_sysclk5 = {
-   .name = "pll1_sysclk5",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV5,
-};
-
-static struct clk pll1_aux_clk = {
-   .name = "pll1_aux_clk",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL | PRE_PLL,
-};
-
-static struct clk pll1_sysclkbp = {
-   .name = "pll1_sysclkbp",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL | PRE_PLL,
-   .div_reg = BPDIV
-};
-
-static struct clk pll2_clk = {
-   .name = "pll2",
-   .parent = &ref_clk,
-   .pll_data = &pll2_data,
-   .flags = CLK_PLL,
-};
-
-static struct clk pll2_sysclk1 = {
-   .name = "pll2_sysclk1",
-   .parent = &pll2_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV1,
-};
-
-static struct clk pll2_sysclk2 = {
-   .name = "pll2_sysclk2",
-   .parent = &pll2_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV2,
-};
-
-static struct clk pll2_sysclkbp = {
-   .name = "pll2_sysclkbp",
-   .parent = &pll2_clk,
-   .flags = CLK_PLL | PRE_PLL,
-   .div_reg = BPDIV
-};
-
-static struct clk dsp_clk = {
-   .name = "dsp",
-   .parent = &pll1_sysclk1,
-   .lpsc = DAVINCI_LPSC_GEM,
-   .domain = DAVINCI_GPSC_DSPDOMAIN,
-   .usecount = 1,  /* REVISIT how to disable? */
-};
-
-static struct clk arm_clk = {
-   .name = "arm",
-   .parent = &pll1_sysclk2,
-   .lpsc = DAVINCI_LPSC_ARM,
-   .flags = ALWAYS_ENABLED,
-};
-
-static struct clk vicp_clk = {
-   .name = "vicp",
-   .parent = &pll1_sysclk2,
-   .lpsc = DAVINCI_LPSC_IMCOP,
-   .domain = DAVINCI_GPSC_DSPDOMAIN,
-   .usecount = 1,  /* REVISIT how to disable? */
-};
-
-static struct clk vpss_master_clk = {
-   .name = "vpss_master",
-   .parent = &pll1_sysclk3,
-   .lpsc = DAVINCI_LPSC_VPSSMSTR,
-   .flags = CLK_PSC,
-};
-
-static struct clk vpss_slave_clk = {
-   .name = "vpss_slave",
-   .parent = &pll1_sysclk3,
-   .lpsc = DAVINCI_LPSC_VPSSSLV,
-};
-
-static struct clk uart0_clk = {
-   .name = "uart0",
-   .parent = &pll1_aux_clk,
-   .lpsc = DAVINCI_LPSC_UART0,
-};
-
-static struct clk uart1_clk = {
-   .name = "uart1",
-   .parent = &pll1_aux_clk,
-   .lpsc = DAVINCI_LPSC_UART1,
-};
-
-static struct clk uart2_clk = {
-   .name = "uart2",
-   .parent = &pll1_aux_clk,
-   .lpsc = DAVINCI_LPSC_UART2,
-};
-
-static struct clk emac_clk = {
-   .name = "emac",
-   .parent = &pll1_sysclk5,
-   .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
-};
-
-static struct clk i2c_clk = {
-   .name = "i2c",
-   .parent = &pll1_aux_clk,
-   .lpsc = DAVINCI_LPSC_I2C,
-};
-
-static struct clk ide_clk = {
-   .name = "ide",
-   .parent = &pll1_sysclk5,
-   .lpsc = DAVINCI_LPSC_ATA,
-};
-
-static struct clk asp_clk = {
-   .name = "asp0",
-   .parent = &pll1_sysclk5,
-   .lpsc = DAVINCI_LPSC_McBSP,
-};
-
-static struct clk mmcsd_clk = {
-   .name = "mmcsd",
-   .parent = &pll1_sysclk5,
-   .lpsc = DAVINCI_LPSC_MMC_SD,
-};
-
-static struct clk spi_clk = {

[PATCH v11 21/27] ARM: davinci: dm646x: Remove legacy clock init

This removes the unused legacy clock init code from
arch/arm/mach-davinci/dm646x.c.

Signed-off-by: David Lechner 
Reviewed-by: Sekhar Nori 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- rebased

v8 changes:
- none

v7 changes:
- rebased
- add davinci prefix to commit message

v6 changes:
- rebased


 arch/arm/mach-davinci/dm646x.c | 329 -
 1 file changed, 329 deletions(-)

diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index f05090317469..6bd2ed069d0d 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -33,11 +33,6 @@
 #include "davinci.h"
 #include "mux.h"
 
-#ifndef CONFIG_COMMON_CLK
-#include "clock.h"
-#include "psc.h"
-#endif
-
 #define DAVINCI_VPIF_BASE   (0x01C12000)
 
 #define VDD3P3V_VID_MASK   (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
@@ -52,319 +47,6 @@
 #define DM646X_EMAC_CNTRL_RAM_OFFSET   0x2000
 #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
 
-#ifndef CONFIG_COMMON_CLK
-static struct pll_data pll1_data = {
-   .num   = 1,
-   .phys_base = DAVINCI_PLL1_BASE,
-};
-
-static struct pll_data pll2_data = {
-   .num   = 2,
-   .phys_base = DAVINCI_PLL2_BASE,
-};
-
-static struct clk ref_clk = {
-   .name = "ref_clk",
-   /* rate is initialized in dm646x_init_time() */
-};
-
-static struct clk aux_clkin = {
-   .name = "aux_clkin",
-   /* rate is initialized in dm646x_init_time() */
-};
-
-static struct clk pll1_clk = {
-   .name = "pll1",
-   .parent = &ref_clk,
-   .pll_data = &pll1_data,
-   .flags = CLK_PLL,
-};
-
-static struct clk pll1_sysclk1 = {
-   .name = "pll1_sysclk1",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV1,
-};
-
-static struct clk pll1_sysclk2 = {
-   .name = "pll1_sysclk2",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV2,
-};
-
-static struct clk pll1_sysclk3 = {
-   .name = "pll1_sysclk3",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV3,
-};
-
-static struct clk pll1_sysclk4 = {
-   .name = "pll1_sysclk4",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV4,
-};
-
-static struct clk pll1_sysclk5 = {
-   .name = "pll1_sysclk5",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV5,
-};
-
-static struct clk pll1_sysclk6 = {
-   .name = "pll1_sysclk6",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV6,
-};
-
-static struct clk pll1_sysclk8 = {
-   .name = "pll1_sysclk8",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV8,
-};
-
-static struct clk pll1_sysclk9 = {
-   .name = "pll1_sysclk9",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV9,
-};
-
-static struct clk pll1_sysclkbp = {
-   .name = "pll1_sysclkbp",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL | PRE_PLL,
-   .div_reg = BPDIV,
-};
-
-static struct clk pll1_aux_clk = {
-   .name = "pll1_aux_clk",
-   .parent = &pll1_clk,
-   .flags = CLK_PLL | PRE_PLL,
-};
-
-static struct clk pll2_clk = {
-   .name = "pll2_clk",
-   .parent = &ref_clk,
-   .pll_data = &pll2_data,
-   .flags = CLK_PLL,
-};
-
-static struct clk pll2_sysclk1 = {
-   .name = "pll2_sysclk1",
-   .parent = &pll2_clk,
-   .flags = CLK_PLL,
-   .div_reg = PLLDIV1,
-};
-
-static struct clk dsp_clk = {
-   .name = "dsp",
-   .parent = &pll1_sysclk1,
-   .lpsc = DM646X_LPSC_C64X_CPU,
-   .usecount = 1,  /* REVISIT how to disable? */
-};
-
-static struct clk arm_clk = {
-   .name = "arm",
-   .parent = &pll1_sysclk2,
-   .lpsc = DM646X_LPSC_ARM,
-   .flags = ALWAYS_ENABLED,
-};
-
-static struct clk edma_cc_clk = {
-   .name = "edma_cc",
-   .parent = &pll1_sysclk2,
-   .lpsc = DM646X_LPSC_TPCC,
-   .flags = ALWAYS_ENABLED,
-};
-
-static struct clk edma_tc0_clk = {
-   .name = "edma_tc0",
-   .parent = &pll1_sysclk2,
-   .lpsc = DM646X_LPSC_TPTC0,
-   .flags = ALWAYS_ENABLED,
-};
-
-static struct clk edma_tc1_clk = {
-   .name = "edma_tc1",
-   .parent = &pll1_sysclk2,
-   .lpsc = DM646X_LPSC_TPTC1,
-   .flags = ALWAYS_ENABLED,
-};
-
-static struct clk edma_tc2_clk = {
-   .name = "edma_tc2",
-   .parent = &pll1_sysclk2,
-   .lpsc = DM646X_LPSC_TPTC2,
-   .flags = ALWAYS_ENABLED,
-};
-
-static struct clk edma_tc3_clk = {
-   .name = "edma_tc3",
-   .parent = &pll1_sysclk2,
-   .lpsc = DM646X_LPSC_TPTC3,
-   .flags = ALWAYS_ENABLED,
-};
-
-static struct clk uart0_clk = {
-   .name = "uart0",
-   .parent = &aux_clkin,
-   .lpsc = DM646X_LPSC_UART0,
-};
-
-static struct clk uart1_clk = {
-   .name = "uart1",
-   .parent = &aux_clkin,
-   .lpsc = DM646X_LPSC_UART1,
-};
-
-static struct clk uart2_clk = {

[PATCH] drm/nouveau/kms/nv50-: fix drm-get-put.cocci warnings

2018-05-18 Thread Julia Lawall

From: kbuild test robot 

 Use drm_*_get() and drm_*_put() helpers instead of drm_*_reference() and
 drm_*_unreference() helpers.

Generated by: scripts/coccinelle/api/drm-get-put.cocci

Fixes: 30ed49b55b6e ("drm/nouveau/kms/nv50-: move code underneath dispnv50/")
Signed-off-by: kbuild test robot 
Signed-off-by: Julia Lawall 
---

tree:   https://github.com/skeggsb/linux linux-4.18
head:   6c46d01f25bcf74608d09645c27c35c3f3940ebe
commit: 30ed49b55b6e44e004c3095671e74fea93ee84cb [105/165]
drm/nouveau/kms/nv50-: move code underneath dispnv50/

 disp.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -3254,7 +3254,7 @@ nv50_mstm_destroy_connector(struct drm_d
mstc->port = NULL;
drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);

-   drm_connector_unreference(&mstc->connector);
+   drm_connector_put(&mstc->connector);
 }

 static void

[PATCH v11 22/27] ARM: davinci: da8xx: Remove legacy USB and SATA clock init

This removes the unused legacy USB and SATA clock init code from
arch/arm/mach-davinci/{devices,usb}-da8xx}.c.

Signed-off-by: David Lechner 
Reviewed-by: Sekhar Nori 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- none

v8 changes:
- none

v7 changes:
- rebased
- add davinci prefix to commit message

v6 changes:
- rebased


 arch/arm/mach-davinci/devices-da8xx.c  |  29 ---
 arch/arm/mach-davinci/include/mach/da8xx.h |   3 -
 arch/arm/mach-davinci/usb-da8xx.c  | 238 -
 3 files changed, 270 deletions(-)

diff --git a/arch/arm/mach-davinci/devices-da8xx.c 
b/arch/arm/mach-davinci/devices-da8xx.c
index 73de449bbc68..1fd3619f6a09 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -30,11 +30,6 @@
 #include "cpuidle.h"
 #include "sram.h"
 
-#ifndef CONFIG_COMMON_CLK
-#include 
-#include "clock.h"
-#endif
-
 #define DA8XX_TPCC_BASE0x01c0
 #define DA8XX_TPTC0_BASE   0x01c08000
 #define DA8XX_TPTC1_BASE   0x01c08400
@@ -1045,29 +1040,6 @@ int __init da8xx_register_spi_bus(int instance, unsigned 
num_chipselect)
 }
 
 #ifdef CONFIG_ARCH_DAVINCI_DA850
-#ifndef CONFIG_COMMON_CLK
-static struct clk sata_refclk = {
-   .name   = "sata_refclk",
-   .set_rate   = davinci_simple_set_rate,
-};
-
-static struct clk_lookup sata_refclk_lookup =
-   CLK("ahci_da850", "refclk", &sata_refclk);
-
-int __init da850_register_sata_refclk(int rate)
-{
-   int ret;
-
-   sata_refclk.rate = rate;
-   ret = clk_register(&sata_refclk);
-   if (ret)
-   return ret;
-
-   clkdev_add(&sata_refclk_lookup);
-
-   return 0;
-}
-#else
 int __init da850_register_sata_refclk(int rate)
 {
struct clk *clk;
@@ -1078,7 +1050,6 @@ int __init da850_register_sata_refclk(int rate)
 
return clk_register_clkdev(clk, "refclk", "ahci_da850");
 }
-#endif
 
 static struct resource da850_sata_resources[] = {
{
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h 
b/arch/arm/mach-davinci/include/mach/da8xx.h
index 5d7b1de9aa7e..ab4a57f433f4 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -103,9 +103,6 @@ int da8xx_register_watchdog(void);
 int da8xx_register_usb_phy(void);
 int da8xx_register_usb20(unsigned mA, unsigned potpgt);
 int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
-int da8xx_register_usb_refclkin(int rate);
-int da8xx_register_usb20_phy_clk(bool use_usb_refclkin);
-int da8xx_register_usb11_phy_clk(bool use_usb_refclkin);
 int da8xx_register_usb_phy_clocks(void);
 int da850_register_sata_refclk(int rate);
 int da8xx_register_emac(void);
diff --git a/arch/arm/mach-davinci/usb-da8xx.c 
b/arch/arm/mach-davinci/usb-da8xx.c
index c8d2f3075e69..c17ce66a3d95 100644
--- a/arch/arm/mach-davinci/usb-da8xx.c
+++ b/arch/arm/mach-davinci/usb-da8xx.c
@@ -20,11 +20,6 @@
 #include 
 #include 
 
-#ifndef CONFIG_COMMON_CLK
-#include 
-#include "clock.h"
-#endif
-
 #define DA8XX_USB0_BASE0x01e0
 #define DA8XX_USB1_BASE0x01e25000
 
@@ -87,11 +82,6 @@ static struct platform_device da8xx_usb20_dev = {
.name   = "musb-da8xx",
.id = -1,
.dev = {
-   /*
-* Setting init_name so that clock lookup will work in
-* usb20_phy_clk_enable() even if this device is not registered.
-*/
-   .init_name  = "musb-da8xx",
.platform_data  = &usb_data,
.dma_mask   = &usb_dmamask,
.coherent_dma_mask  = DMA_BIT_MASK(32),
@@ -140,234 +130,6 @@ int __init da8xx_register_usb11(struct 
da8xx_ohci_root_hub *pdata)
return platform_device_register(&da8xx_usb11_device);
 }
 
-#ifndef CONFIG_COMMON_CLK
-static struct clk usb_refclkin = {
-   .name   = "usb_refclkin",
-   .set_rate   = davinci_simple_set_rate,
-};
-
-static struct clk_lookup usb_refclkin_lookup =
-   CLK(NULL, "usb_refclkin", &usb_refclkin);
-
-/**
- * da8xx_register_usb_refclkin - register USB_REFCLKIN clock
- *
- * @rate: The clock rate in Hz
- *
- * This clock is only needed if the board provides an external USB_REFCLKIN
- * signal, in which case it will be used as the parent of usb20_phy_clk and/or
- * usb11_phy_clk.
- */
-int __init da8xx_register_usb_refclkin(int rate)
-{
-   int ret;
-
-   usb_refclkin.rate = rate;
-   ret = clk_register(&usb_refclkin);
-   if (ret)
-   return ret;
-
-   clkdev_add(&usb_refclkin_lookup);
-
-   return 0;
-}
-
-static void usb20_phy_clk_enable(struct clk *clk)
-{
-   u32 val;
-   u32 timeout = 50; /* 500 msec */
-
-   val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
-
-   /* The USB 2.O PLL requires that the USB 2.O PSC is enabled as well. */
-   davinci_clk_enable(us

Re: [PATCH] audit: add containerid support for IMA-audit

2018-05-18 Thread Richard Guy Briggs

On 2018-05-18 12:34, Mimi Zohar wrote:
> On Fri, 2018-05-18 at 11:56 -0400, Richard Guy Briggs wrote:
> > On 2018-05-18 10:39, Mimi Zohar wrote:
> > > On Fri, 2018-05-18 at 09:54 -0400, Stefan Berger wrote:
> > > > On 05/18/2018 08:53 AM, Mimi Zohar wrote:
> > > 
> > > [..]
> > > 
> > > >  If so, which ones? We could probably refactor the current
> > > >  integrity_audit_message() and have ima_parse_rule() call into it 
> > > >  to get
> > > >  those fields as well. I suppose adding new fields to it wouldn't be
> > > >  considered breaking user space?
> > > > >>> Changing the order of existing fields or inserting fields could 
> > > > >>> break
> > > > >>> stuff and is strongly discouraged without a good reason, but 
> > > > >>> appending
> > > > >>> fields is usually the right way to add information.
> > > > >>>
> > > > >>> There are exceptions, and in this case, I'd pick the "more 
> > > > >>> standard" of
> > > > >>> the formats for AUDIT_INTEGRITY_RULE (ima_audit_measurement?) and 
> > > > >>> stick
> > > > >>> with that, abandoning the other format, renaming the less standard
> > > > >>> version of the record (ima_parse_rule?) and perhpas adopting that
> > > > >>> abandonned format for the new record type while using
> > > > >>> current->audit_context.
> > > > > This sounds right, other than "type=INTEGRITY_RULE" (1805) for
> > > > > ima_audit_measurement().  Could we rename type=1805 to be
> > > > 
> > > > So do we want to change both? I thought that what 
> > > > ima_audit_measurement() produces looks ok but may not have a good name 
> > > > for the 'type'. Now in this case I would not want to 'break user space'.
> > > > The only change I was going to make was to what ima_parse_rule() 
> > > > produces.
> > > 
> > > The only change for now is separating the IMA policy rules from the
> > > IMA-audit messages.
> > > 
> > > Richard, when the containerid is appended to the IMA-audit messages,
> > > would we make the audit type name change then?
> > 
> > No, go ahead and make the change now.  I'm expecting that the
> > containerid record will just be another auxiliary record and should not
> > affect you folks.
> 
> To summarize, we need to disambiguate the 1805, as both
> ima_parse_rule() and ima_audit_measurement() are using the same number
> with different formats.  The main usage of 1805 that we are aware of
> is ima_audit_measurement().  Yet the "type=" name for
> ima_audit_measurement() should be INTEGRITY_IMA_AUDIT, not
> INTEGRITY_RULE.
> 
> option 1: breaks both uses
> 1805 - INTEGRITY_IMA_AUDIT - ima_audit_measurement()
> 1806 - INTEGRITY_POLICY_RULE - ima_parse_rule()
> 
> option 2: breaks the most common usage
> 1805 - INTEGRITY_RULE - ima_parse_rule()
> 1806 - INTEGRITY_IMA_AUDIT - ima_audit_measurement()
> 
> option 3: leaves the most common usage with the wrong name, and breaks
> the other less common usage
> 1805 - INTEGRITY_RULE - ima_audit_measurement()
> 1806 - INTEGRITY_POLICY_RULE - ima_parse_rule()
> 
> So option 3 is the best option?

Yes, I think so, but option 2 I would be willing to consider.  I'd like
to get Paul and Steve's opinions on this.

> Mimi

- RGB

--
Richard Guy Briggs 
Sr. S/W Engineer, Kernel Security, Base Operating Systems
Remote, Ottawa, Red Hat Canada
IRC: rgb, SunRaycer
Voice: +1.647.777.2635, Internal: (81) 32635

[PATCH v11 10/27] ARM: davinci: dm646x: add new clock init using common clock framework

This adds the new board-specific clock init in mach-davinci/dm646x.c
using the new common clock framework drivers.

The #ifdefs are needed to prevent compile errors until the entire
ARCH_DAVINCI is converted.

Also clean up the #includes since we are adding some here.

Signed-off-by: David Lechner 
---

v11 changes:
- none

v10 changes:
- none

v9 changes:
- register PLL1 and PSC in dm646x_init_time() instead of as platform device so
  that we get the correct timer0 clock for davinci_timer_init()
- Fixed size of PLL memory block

v8 changes:
- register clkdev lookup for ref_clk and aux_clkin

v7 changes:
- add clock platform device declarations
- register platform devices instead of registering clocks directly
- add davinci prefix to commit description

v6 changes:
- add blank lines between function calls


 arch/arm/mach-davinci/board-dm646x-evm.c |  2 +
 arch/arm/mach-davinci/davinci.h  |  1 +
 arch/arm/mach-davinci/dm646x.c   | 63 +---
 3 files changed, 58 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c 
b/arch/arm/mach-davinci/board-dm646x-evm.c
index 584064fdabf5..867ab2fa6cfd 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -776,6 +776,8 @@ static __init void evm_init(void)
int ret;
struct davinci_soc_info *soc_info = &davinci_soc_info;
 
+   dm646x_register_clocks();
+
ret = dm646x_gpio_register();
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 16aca5853ab2..fa99197d36f9 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -116,6 +116,7 @@ int dm644x_gpio_register(void);
 /* DM646x function declarations */
 void dm646x_init(void);
 void dm646x_init_time(unsigned long ref_clk_rate, unsigned long 
aux_clkin_rate);
+void dm646x_register_clocks(void);
 void dm646x_init_mcasp0(struct snd_platform_data *pdata);
 void dm646x_init_mcasp1(struct snd_platform_data *pdata);
 int dm646x_init_edma(struct edma_rsv_info *rsv);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 280b753702f3..f05090317469 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -8,29 +8,35 @@
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
+
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
-#include 
-#include 
-#include 
 #include 
 #include 
+#include 
+#include 
 
 #include 
 
+#include 
 #include 
 #include 
-#include "psc.h"
 #include 
-#include 
 #include 
-#include 
+#include 
 
+#include "asp.h"
 #include "davinci.h"
-#include "clock.h"
 #include "mux.h"
-#include "asp.h"
+
+#ifndef CONFIG_COMMON_CLK
+#include "clock.h"
+#include "psc.h"
+#endif
 
 #define DAVINCI_VPIF_BASE   (0x01C12000)
 
@@ -46,6 +52,7 @@
 #define DM646X_EMAC_CNTRL_RAM_OFFSET   0x2000
 #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
 
+#ifndef CONFIG_COMMON_CLK
 static struct pll_data pll1_data = {
.num   = 1,
.phys_base = DAVINCI_PLL1_BASE,
@@ -356,6 +363,7 @@ static struct clk_lookup dm646x_clks[] = {
CLK(NULL, "vpif1", &vpif1_clk),
CLK(NULL, NULL, NULL),
 };
+#endif
 
 static struct emac_platform_data dm646x_emac_pdata = {
.ctrl_reg_offset= DM646X_EMAC_CNTRL_OFFSET,
@@ -954,10 +962,49 @@ void __init dm646x_init(void)
 void __init dm646x_init_time(unsigned long ref_clk_rate,
 unsigned long aux_clkin_rate)
 {
+#ifdef CONFIG_COMMON_CLK
+   void __iomem *pll1, *psc;
+   struct clk *clk;
+
+   clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate);
+   clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate);
+
+   pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
+   dm646x_pll1_init(NULL, pll1, NULL);
+
+   psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
+   dm646x_psc_init(NULL, psc);
+
+   clk = clk_get(NULL, "timer0");
+
+   davinci_timer_init(clk);
+#else
ref_clk.rate = ref_clk_rate;
aux_clkin.rate = aux_clkin_rate;
davinci_clk_init(dm646x_clks);
davinci_timer_init(&timer0_clk);
+#endif
+}
+
+static struct resource dm646x_pll2_resources[] = {
+   {
+   .start  = DAVINCI_PLL2_BASE,
+   .end= DAVINCI_PLL2_BASE + SZ_1K - 1,
+   .flags  = IORESOURCE_MEM,
+   },
+};
+
+static struct platform_device dm646x_pll2_device = {
+   .name   = "dm646x-pll2",
+   .id = -1,
+   .resource   = dm646x_pll2_resources,
+   .num_resources  = ARRAY_SIZE(dm646x_pll2_resources),
+};
+
+void __init dm646x_register_clocks(void)
+{
+   /* PLL1 and PSC are registered in dm646x_init_time() */
+   platform_device_register(&dm646x_pll2_device);
 }
 
 static int __init dm646x_init_devices(void)

[PATCH v11 01/27] clk: davinci: pll: allow dev == NULL

This modifies the TI Davinci PLL clock driver to allow for the case
when dev == NULL. On some (most) SoCs that use this driver, the PLL
clock needs to be registered during early boot because it is used
for clocksource/clkevent and there will be no platform device available.

Some function declarations are moved to a public header files so that they can
be called from mach init code.

Also fix some missing @dev doc comments that would have been touched in this
patch anyway.

Signed-off-by: David Lechner 
---

v11 changes:
- proper unwinding on errors
- add #include  to avoid W=1 warnings
- fix more @dev in doc comments to avoid sparse warning

v10 changes:
- dropped helper functions that called devm_* versions of functions.
- removed duplicate function declarations from pll.h

v9 changes:
- new patch in v9


 drivers/clk/davinci/pll-da830.c  |   5 +-
 drivers/clk/davinci/pll-da850.c  |  22 +--
 drivers/clk/davinci/pll-dm355.c  |   9 +-
 drivers/clk/davinci/pll-dm365.c  |   9 +-
 drivers/clk/davinci/pll-dm644x.c |   9 +-
 drivers/clk/davinci/pll-dm646x.c |   9 +-
 drivers/clk/davinci/pll.c| 275 +--
 drivers/clk/davinci/pll.h|  30 ++--
 include/linux/clk/davinci.h  |  24 +++
 9 files changed, 256 insertions(+), 136 deletions(-)
 create mode 100644 include/linux/clk/davinci.h

diff --git a/drivers/clk/davinci/pll-da830.c b/drivers/clk/davinci/pll-da830.c
index 929a3d3a9adb..0a0d06fb25fd 100644
--- a/drivers/clk/davinci/pll-da830.c
+++ b/drivers/clk/davinci/pll-da830.c
@@ -6,6 +6,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -36,11 +37,11 @@ SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
 SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
 SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
 
-int da830_pll_init(struct device *dev, void __iomem *base)
+int da830_pll_init(struct device *dev, void __iomem *base, struct regmap 
*cfgchip)
 {
struct clk *clk;
 
-   davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base);
+   davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, 
cfgchip);
 
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0");
diff --git a/drivers/clk/davinci/pll-da850.c b/drivers/clk/davinci/pll-da850.c
index 2a038b7908cc..59cc2e3733f9 100644
--- a/drivers/clk/davinci/pll-da850.c
+++ b/drivers/clk/davinci/pll-da850.c
@@ -7,7 +7,9 @@
 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -81,11 +83,11 @@ static const struct davinci_pll_obsclk_info 
da850_pll0_obsclk_info = {
.ocsrc_mask = GENMASK(4, 0),
 };
 
-int da850_pll0_init(struct device *dev, void __iomem *base)
+int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap 
*cfgchip)
 {
struct clk *clk;
 
-   davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base);
+   davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, 
cfgchip);
 
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base);
clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0");
@@ -134,11 +136,11 @@ static const struct davinci_pll_sysclk_info 
*da850_pll0_sysclk_info[] = {
NULL
 };
 
-int of_da850_pll0_init(struct device *dev, void __iomem *base)
+int of_da850_pll0_init(struct device *dev, void __iomem *base, struct regmap 
*cfgchip)
 {
-   return of_davinci_pll_init(dev, &da850_pll0_info,
+   return of_davinci_pll_init(dev, dev->of_node, &da850_pll0_info,
   &da850_pll0_obsclk_info,
-  da850_pll0_sysclk_info, 7, base);
+  da850_pll0_sysclk_info, 7, base, cfgchip);
 }
 
 static const struct davinci_pll_clk_info da850_pll1_info = {
@@ -179,11 +181,11 @@ static const struct davinci_pll_obsclk_info 
da850_pll1_obsclk_info = {
.ocsrc_mask = GENMASK(4, 0),
 };
 
-int da850_pll1_init(struct device *dev, void __iomem *base)
+int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap 
*cfgchip)
 {
struct clk *clk;
 
-   davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base);
+   davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip);
 
davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
 
@@ -204,9 +206,9 @@ static const struct davinci_pll_sysclk_info 
*da850_pll1_sysclk_info[] = {
NULL
 };
 
-int of_da850_pll1_init(struct device *dev, void __iomem *base)
+int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap 
*cfgchip)
 {
-   return of_davinci_pll_init(dev, &da850_pll1_info,
+   return of_davinci_pll_init(dev, dev->of_node, &da850_pll1_info,
   &da850_pll1_obsclk_info,
-  da850_pll1_sysclk_info, 3, base);
+  da850_pll1_sysclk_info, 3, base, cfgchip);
 }
diff --git a/drivers/clk

Re: [PATCH] audit: add containerid support for IMA-audit

2018-05-18 Thread Stefan Berger

On 05/18/2018 11:45 AM, Richard Guy Briggs wrote:

On 2018-05-18 07:49, Stefan Berger wrote:

On 05/17/2018 05:30 PM, Richard Guy Briggs wrote:

On 2018-05-17 10:18, Stefan Berger wrote:

On 03/08/2018 06:21 AM, Richard Guy Briggs wrote:

On 2018-03-05 09:24, Mimi Zohar wrote:

On Mon, 2018-03-05 at 08:50 -0500, Richard Guy Briggs wrote:

On 2018-03-05 08:43, Mimi Zohar wrote:

Hi Richard,

This patch has been compiled, but not runtime tested.

Ok, great, thank you. I assume you are offering this patch to be
included in this patchset?

Yes, thank you.

I'll have a look to see where it fits in the
IMA record. It might be better if it were an AUDIT_CONTAINER_INFO
auxiliary record, but I'll have a look at the circumstances of the
event.

I had a look at the context of this record to see if adding the contid
field to it made sense. I think the only records for which the contid
field makes sense are the two newly proposed records, AUDIT_CONTAINER
which introduces the container ID and the and AUDIT_CONTAINER_INFO which
documents the presence of the container ID in a process event (or
process-less network event). All others should use the auxiliary record
AUDIT_CONTAINER_INFO rather than include the contid field directly
itself. There are several reasons for this including record length, the
ability to filter unwanted records, the difficulty of changing the order
of or removing fields in the future.

Syscalls get this information automatically if the container ID is set
for a task via the AUDIT_CONTAINER_INFO auxiliary record. Generally a
syscall event is one that uses the task's audit_context while a
standalone event uses NULL or builds a local audit_context that is
discarded immediately after the local use.

Looking at the two cases of AUDIT_INTEGRITY_RULE record generation, it
appears that they should be split into two distinct audit record types.

The record created in ima_audit_measurement() is a syscall record that
could possibly stand on its own since the subject attributes are
present. If it remains a syscall auxiliary record it will automatically
have the AUDIT_CONTAINER_INFO record accompany it anyways. If it is
decided to detach it (which would save cpu/netlink/disk bandwidth but is
not recommended due to not wanting to throw away any other syscall
information or other involved records (PATH, CWD, etc...) then a local
audit_context would be created for the AUDIT_INTEGRITY_RULE and
AUDIT_CONTAINERID_INFO records only and immediately discarded.

What does 'detach it' mean? Does it mean we're not using
current->audit_context?

Exactly.

The record created in ima_parse_rule() is not currently a syscall record
since it is passed an audit_context of NULL and it has a very different
format that does not include any subject attributes (except subj_*=).
At first glance it appears this one should be a syscall accompanied
auxiliary record. Either way it should have an AUDIT_CONTAINER_INFO

Do you have an example (pointer) to the format for a 'syscall accompanied
auxiliary record'?

Any that uses current->audit_context (or recently proposed
audit_context() function) will be a syscall auxiliary record. Well
formed record formats are = and named as listed:

https://github.com/linux-audit/audit-documentation/wiki/SPEC-Writing-Good-Events

https://github.com/linux-audit/audit-documentation/blob/master/specs/fields/field-dictionary.csv

auxiliary record either by being converted to a syscall auxiliary record
by using current->audit_context rather than NULL when calling
audit_log_start(), or creating a local audit_context and calling

ima_parse_rule() is invoked when setting a policy by writing it into
/sys/kernel/security/ima/policy. We unfortunately don't have the
current->audit_context in this case.

Sure you do. What process writes to that file? That's the one we care
about, unless it is somehow handed off to a queue and processed later in
a different context.

I just printk'd it again. current->audit_context is NULL in this case.

Oops, that sounds like some of the netfilter empty table
initializations, whereas usually rules have a user actor.

So it's a bug elsewhere not a 'feature?'

audit_log_container_info() then releasing the local context. This
version of the record has additional concerns covered here:
https://github.com/linux-audit/audit-kernel/issues/52

Following the discussion there and the concern with breaking user space, how
can we split up the AUDIT_INTEGRITY_RULE that is used in
ima_audit_measurement() and ima_parse_rule(), without 'breaking user space'?

Arguably userspace is already broken by this wildly diverging pair of
formats for the same record.

A message produced by ima_parse_rule() looks like this here:

type=INTEGRITY_RULE msg=audit(1526566213.870:305): action="dont_measure"
fsmagic="0x9fa0" res=1

in contrast to that an INTEGRITY_PCR record type:

type=INTEGRITY_PCR msg=audit(1526566235.193:334): pid=1615 uid=0 auid=0
ses=2 subj=unconfined

Re: [PATCH] kvm: rename HINTS_DEDICATED to KVM_HINTS_REALTIME

2018-05-18 Thread Eduardo Habkost

CCing qemu-devel, as I'm now discussing userspace.

On Thu, May 17, 2018 at 10:55:33PM +0300, Michael S. Tsirkin wrote:
> On Thu, May 17, 2018 at 03:46:58PM -0300, Eduardo Habkost wrote:
> > On Thu, May 17, 2018 at 05:54:24PM +0300, Michael S. Tsirkin wrote:
> > > HINTS_DEDICATED seems to be somewhat confusing:
> > > 
> > > Guest doesn't really care whether it's the only task running on a host
> > > CPU as long as it's not preempted.
> > > 
> > > And there are more reasons for Guest to be preempted than host CPU
> > > sharing, for example, with memory overcommit it can get preempted on a
> > > memory access, post copy migration can cause preemption, etc.
> > > 
> > > Let's call it KVM_HINTS_REALTIME which seems to better
> > > match what guests expect.
> > > 
> > > Also, the flag most be set on all vCPUs - current guests assume th.
> > > Note so in the documentation.
> > > 
> > > Signed-off-by: Michael S. Tsirkin 
> > > ---
> > >  Documentation/virtual/kvm/cpuid.txt  | 6 +++---
> > >  arch/x86/include/uapi/asm/kvm_para.h | 2 +-
> > >  arch/x86/kernel/kvm.c| 8 
> > >  3 files changed, 8 insertions(+), 8 deletions(-)
> > > 
> > > diff --git a/Documentation/virtual/kvm/cpuid.txt 
> > > b/Documentation/virtual/kvm/cpuid.txt
> > > index d4f33eb8..ab022dc 100644
> > > --- a/Documentation/virtual/kvm/cpuid.txt
> > > +++ b/Documentation/virtual/kvm/cpuid.txt
> > > @@ -72,8 +72,8 @@ KVM_FEATURE_CLOCKSOURCE_STABLE_BIT ||24 || host 
> > > will warn if no guest-side
> > >  
> > >  flag   || value || meaning
> > >  
> > > ==
> > > -KVM_HINTS_DEDICATED|| 0 || guest checks this feature 
> > > bit to
> > > -   ||   || determine if there is 
> > > vCPU pinning
> > > -   ||   || and there is no vCPU 
> > > over-commitment,
> > > +KVM_HINTS_REALTIME || 0 || guest checks this feature 
> > > bit to
> > > +   ||   || determine that vCPUs are 
> > > never
> > > +   ||   || preempted for an 
> > > unlimited time,
> > > ||   || allowing optimizations
> > 
> > My understanding of the original patch is that the intention is
> > to tell the guest that it is very unlikely to be preempted,
> > so it
> > can choose a more appropriate spinlock implementation.  This
> > description implies that the guest will never be preempted, which
> > is much stronger guarantee.
> 
> Note:
> 
> ...  for an unlimited time.

Which still sounds like a stronger guarantee than the original
description.  But:

> 
> > 
> > Isn't this new description incompatible with existing usage of
> > the hint, which might include people who just use vCPU pinning
> > but no mlock?
> 
> Without mlock you should always use pv spinlocks.
> 
> Otherwise you risk blocking on a lock taken by
> a VCPU that is in turn blocked on IO, where the IO
> is not completing because CPU is being used up
> spinning.

So the stronger guarantee seems necessary.

Now what should host userspace do if the user is trying to run an
existing configuration where the CPUID hint was set but memory is
not pinned?

-- 
Eduardo

Re: [PATCH v7 2/2] iommu/amd: Add basic debugfs infrastructure for AMD IOMMU

2018-05-18 Thread Randy Dunlap

On 05/18/2018 08:20 AM, Gary R Hook wrote:
> On 05/15/2018 08:46 AM, Joerg Roedel wrote:
>> On Mon, May 14, 2018 at 03:00:50PM -0500, Gary R Hook wrote:
>>> This was brought up a few weeks ago in, I believe, version 3 of this patch.
>>> That question was discussed (because that's what I did the first time out),
>>> and _someone_ _else_ asked about why I didn't just do it the way I've done
>>> it here.
>>
>> You don't have this problem if you put the code in amd_iommu.c in an
>> IOMMU_DEBUGFS ifdef.
> 
> Of course. My preference, however, is a separate file to avoid size creep. 
> That's why I've done it this way.
> 
> To whit: there have been threads discussing the advisability/acceptability of 
> using #ifdefs for debug code. My take-away was to avoid them. Perhaps I 
> misunderstood.
> 
> So: I don't understand your comment. Is this an observation, or is it an 
> imperative statement? I'd like for a maintainer to clearly indicate what is 
> acceptable, and I'll do it.
> 
> 

Hi,
I looked back at Robin Murphy's comments on April 17:


Well, you could do a makefile-level dependency i.e.:

ifeq ($(CONFIG_IOMMU_DEBUG), y)
obj-$(CONFIG_AMD_IOMMU) += amd_iommu_debugfs.o
obj-$(CONFIG_BLAH_IOMMU) += blah_iommu_debugfs.o
...
endif

Or alternatively have an intermediate silent Kconfig option:

config AMD_IOMMU_DEBUG
def_bool y
depends on AMD_IOMMU && IOMMU_DEBUG

The makefile option is arguably ugly, but does at least scale better ;)



I think the Kconfig option would have been the correct choice.

-- 
~Randy

Should new code have forward declarations of static functions or not?

2018-05-18 Thread Simon Que

Is it preferred to have forward declarations of static funcs, or to omit
them altogether?

I know that different files in kernel code follow one style or the other.
Just wondering if there's a preferred style for new code.

Simon

[PATCH 01/11] coresight: ETM: Add support for Arm Cortex-A73 and Cortex-A35

Add ETM PIDs of the Arm cortex-A CPUs to the white list of ETMs.
While at it, also add description of the CPU to which the ETM belongs,
to make it easier to identify the ETM devices.

Cc: Mathieu Poirier 
Signed-off-by: Suzuki K Poulose 
---
 drivers/hwtracing/coresight/coresight-etm4x.c | 32 +--
 1 file changed, 15 insertions(+), 17 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c 
b/drivers/hwtracing/coresight/coresight-etm4x.c
index cf364a5..fe5b41c 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -1034,7 +1034,8 @@ static int etm4_probe(struct amba_device *adev, const 
struct amba_id *id)
}
 
pm_runtime_put(&adev->dev);
-   dev_info(dev, "%s initialized\n", (char *)id->data);
+   dev_info(dev, "CPU%d: %s initialized\n",
+   drvdata->cpu, (char *)id->data);
 
if (boot_enable) {
coresight_enable(drvdata->csdev);
@@ -1052,23 +1053,20 @@ static int etm4_probe(struct amba_device *adev, const 
struct amba_id *id)
return ret;
 }
 
+#define ETM4_AMBA_ID(cpu, pid) \
+   {   \
+   .id = pid,  \
+   .mask   = 0x000f,   \
+   .data   = #cpu " ETM v4.x", \
+   }
+
 static const struct amba_id etm4_ids[] = {
-   {   /* ETM 4.0 - Cortex-A53  */
-   .id = 0x000bb95d,
-   .mask   = 0x000f,
-   .data   = "ETM 4.0",
-   },
-   {   /* ETM 4.0 - Cortex-A57 */
-   .id = 0x000bb95e,
-   .mask   = 0x000f,
-   .data   = "ETM 4.0",
-   },
-   {   /* ETM 4.0 - A72, Maia, HiSilicon */
-   .id = 0x000bb95a,
-   .mask = 0x000f,
-   .data = "ETM 4.0",
-   },
-   { 0, 0},
+   ETM4_AMBA_ID(Cortex-A53, 0x000bb95d),
+   ETM4_AMBA_ID(Cortex-A57, 0x000bb95e),
+   ETM4_AMBA_ID(Cortex-A72, 0x000bb95a),
+   ETM4_AMBA_ID(Cortex-A73, 0x000bb959),
+   ETM4_AMBA_ID(Cortex-A35, 0x000bb9da),
+   {},
 };
 
 static struct amba_driver etm4x_driver = {
-- 
2.7.4

[PATCH 04/11] coresight: tmc-etr: Disallow perf mode

We don't support ETR in perf mode yet. So, don't
even try to enable the hardware, even by mistake.

Cc: Mathieu Poirier 
Signed-off-by: Suzuki K Poulose 
---
 drivers/hwtracing/coresight/coresight-tmc-etr.c | 28 ++---
 1 file changed, 2 insertions(+), 26 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c 
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index c73bcb3..6c5e8d1 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -223,32 +223,8 @@ static int tmc_enable_etr_sink_sysfs(struct 
coresight_device *csdev)
 
 static int tmc_enable_etr_sink_perf(struct coresight_device *csdev)
 {
-   int ret = 0;
-   unsigned long flags;
-   struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
-
-   spin_lock_irqsave(&drvdata->spinlock, flags);
-   if (drvdata->reading) {
-   ret = -EINVAL;
-   goto out;
-   }
-
-   /*
-* In Perf mode there can be only one writer per sink.  There
-* is also no need to continue if the ETR is already operated
-* from sysFS.
-*/
-   if (drvdata->mode != CS_MODE_DISABLED) {
-   ret = -EINVAL;
-   goto out;
-   }
-
-   drvdata->mode = CS_MODE_PERF;
-   tmc_etr_enable_hw(drvdata);
-out:
-   spin_unlock_irqrestore(&drvdata->spinlock, flags);
-
-   return ret;
+   /* We don't support perf mode yet ! */
+   return -EINVAL;
 }
 
 static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode)
-- 
2.7.4

[PATCH 03/11] coresight: tmc-etr: Do not clean trace buffer

We zero out the entire trace buffer used for ETR before it is enabled,
for helping with debugging. With the addition of scatter-gather mode,
the buffer could be bigger and non-contiguous.

Get rid of this step; if someone wants to debug, they can always add it
as and when needed.

Cc: Mathieu Poirier 
Signed-off-by: Suzuki K Poulose 
---
 drivers/hwtracing/coresight/coresight-tmc-etr.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c 
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index d3c2b04..c73bcb3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -24,9 +24,6 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 {
u32 axictl, sts;
 
-   /* Zero out the memory to help with debug */
-   memset(drvdata->vaddr, 0, drvdata->size);
-
CS_UNLOCK(drvdata->base);
 
/* Wait for TMCSReady bit to be set */
@@ -352,9 +349,8 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)
if (drvdata->mode == CS_MODE_SYSFS) {
/*
 * The trace run will continue with the same allocated trace
-* buffer. The trace buffer is cleared in tmc_etr_enable_hw(),
-* so we don't have to explicitly clear it. Also, since the
-* tracer is still enabled drvdata::buf can't be NULL.
+* buffer. Since the tracer is still enabled drvdata::buf can't
+* be NULL.
 */
tmc_etr_enable_hw(drvdata);
} else {
-- 
2.7.4

Re: [PATCH -mm] mm, huge page: Copy to access sub-page last when copy huge page

2018-05-18 Thread Mike Kravetz

On 05/17/2018 11:24 PM, Michal Hocko wrote:
> On Fri 18-05-18 11:03:16, Huang, Ying wrote:
> [...]
>> The patch is a generic optimization which should benefit quite some
>> workloads, not for a specific use case.  To demonstrate the performance
>> benefit of the patch, we tested it with vm-scalability run on
>> transparent huge page.
> 
> It is also adds quite some non-intuitive code. So is this worth? Does
> any _real_ workload benefits from the change?

One way to 'add less code' would be to create a helper routine that
indicates the order in which sub-pages are to be copied.  IIUC, you
added the same algorithm for sub-page ordering to copy_huge_page()
that was previously added to clear_huge_page().  Correct?  If so,
then perhaps a common helper could be used by both the clear and copy
huge page routines.  It would also make maintenance easier.

-- 
Mike Kravetz

Re: [PATCH v3 0/5]

2018-05-18 Thread Marc Zyngier

[/me beats himself for not writing a subject line...]

On 18/05/18 17:29, Vince Weaver wrote:
> On Fri, 18 May 2018, Marc Zyngier wrote:
> 
>> There is also the case of people natively running 32bit kernels on
>> 64bit HW and trying to upstream unspeakable hacks, hoping that the
>> stars will align and that they'll win the lottery (see [1]).
> 
> I've tested these patches on a Raspberry Pi 3B running a 32-bit upstream 
> (4.17-rc5-git) kernel and they work.
> 
> [0.472906] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 
> counters available
> 
> I only needed to add this to the devicetree
> 
>   arm-pmu {
>   compatible = "arm,cortex-a53-pmu";
>   interrupt-parent = <&local_intc>;
>   interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
>   };

That's definitely the sensible thing to have on such hardware. Why isn't
it in the upstream DT already, irrespective of the state of the kernel
support?

> Tested-by: Vince Weaver 

Thanks a lot for testing.

M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v5 2/4] Documentation: bindings: add phy_config for Rockchip USB Type-C PHY

On Thu, May 17, 2018 at 05:17:58PM +0800, Lin Huang wrote:
> If want to do training outside DP Firmware, need phy voltage swing
> and pre_emphasis value.

"dt-bindings: phy: ..." for the subject please.

> 
> Signed-off-by: Lin Huang 
> ---
> Changes in v2:
> - None 
> Changes in v3:
> - modify property description and add this property to Example
> Change in v4:
> - None
> Change in v5:
> - None
> 
>  .../devicetree/bindings/phy/phy-rockchip-typec.txt | 29 
> +-
>  1 file changed, 28 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt 
> b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> index 960da7f..af298f2 100644
> --- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
> @@ -17,7 +17,8 @@ Required properties:
>  
>  Optional properties:
>   - extcon : extcon specifier for the Power Delivery
> -
> + - rockchip,phy_config : A list of voltage swing(mv) and pre-emphasis
> + (dB) pairs.

rockchip,phy-config

>  Required nodes : a sub-node is required for each port the phy provides.
>The sub-node name is used to identify dp or usb3 port,
>and shall be the following entries:
> @@ -50,6 +51,19 @@ Example:
><&cru SRST_P_UPHY0_TCPHY>;
>   reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
>  
> + rockchip,phy_config =<0x2a 0x00

space ^

And format with inner <> ("< <0 1> <0 2> ... >") to show the pairs.

> + 0x1f 0x15
> + 0x14 0x22
> + 0x02 0x2b
> + 0x21 0x00
> + 0x12 0x15
> + 0x02 0x22
> + 0 0
> + 0x15 0x00
> + 0x00 0x15
> + 0 0
> + 0 0>;

Since you have <0 0> multiple times, I presume the index is significant 
and the length is fixed. Please define the index meaning and length 
above.

> +
>   tcphy0_dp: dp-port {
>   #phy-cells = <0>;
>   };
> @@ -74,6 +88,19 @@ Example:
><&cru SRST_P_UPHY1_TCPHY>;
>   reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
>  
> + rockchip,phy_config =<0x2a 0x00
> + 0x1f 0x15
> + 0x14 0x22
> + 0x02 0x2b
> + 0x21 0x00
> + 0x12 0x15
> + 0x02 0x22
> + 0 0
> + 0x15 0x00
> + 0x00 0x15
> + 0 0
> + 0 0>;
> +
>   tcphy1_dp: dp-port {
>   #phy-cells = <0>;
>   };
> -- 
> 2.7.4
>

[PATCH 07/11] dts: juno: Add scatter-gather support for all revisions

Advertise that the scatter-gather is properly integrated on
all revisions of Juno board.

Cc: Mathieu Poirier 
Cc: Sudeep Holla 
Cc: Liviu Dudau 
Cc: Lorenzo Pieralisi 
Signed-off-by: Suzuki K Poulose 
---
 arch/arm64/boot/dts/arm/juno-base.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi 
b/arch/arm64/boot/dts/arm/juno-base.dtsi
index eb749c5..6ce9090 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -198,6 +198,7 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
+   arm,scatter-gather;
port {
etr_in_port: endpoint {
slave-mode;
-- 
2.7.4

[PATCH 05/11] coresight: Add helper for inserting synchronization packets

Right now we open code filling the trace buffer with synchronization
packets when the circular buffer wraps around in different drivers.
Move this to a common place. While at it, clean up the barrier_pkt
array to strip off the trailing '\0'.

Cc: Mathieu Poirier 
Cc: Mike Leach 
Signed-off-by: Suzuki K Poulose 
---
 drivers/hwtracing/coresight/coresight-etb10.c   | 12 ---
 drivers/hwtracing/coresight/coresight-priv.h| 10 -
 drivers/hwtracing/coresight/coresight-tmc-etf.c | 27 -
 drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 +---
 drivers/hwtracing/coresight/coresight.c |  3 +--
 5 files changed, 23 insertions(+), 42 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etb10.c 
b/drivers/hwtracing/coresight/coresight-etb10.c
index 580cd38..74232e6 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -202,7 +202,6 @@ static void etb_dump_hw(struct etb_drvdata *drvdata)
bool lost = false;
int i;
u8 *buf_ptr;
-   const u32 *barrier;
u32 read_data, depth;
u32 read_ptr, write_ptr;
u32 frame_off, frame_endoff;
@@ -233,19 +232,16 @@ static void etb_dump_hw(struct etb_drvdata *drvdata)
 
depth = drvdata->buffer_depth;
buf_ptr = drvdata->buf;
-   barrier = barrier_pkt;
for (i = 0; i < depth; i++) {
read_data = readl_relaxed(drvdata->base +
  ETB_RAM_READ_DATA_REG);
-   if (lost && *barrier) {
-   read_data = *barrier;
-   barrier++;
-   }
-
*(u32 *)buf_ptr = read_data;
buf_ptr += 4;
}
 
+   if (lost)
+   coresight_insert_barrier_packet(drvdata->buf);
+
if (frame_off) {
buf_ptr -= (frame_endoff * 4);
for (i = 0; i < frame_endoff; i++) {
@@ -454,7 +450,7 @@ static void etb_update_buffer(struct coresight_device 
*csdev,
buf_ptr = buf->data_pages[cur] + offset;
read_data = readl_relaxed(drvdata->base +
  ETB_RAM_READ_DATA_REG);
-   if (lost && *barrier) {
+   if (lost && i < CORESIGHT_BARRIER_PKT_SIZE) {
read_data = *barrier;
barrier++;
}
diff --git a/drivers/hwtracing/coresight/coresight-priv.h 
b/drivers/hwtracing/coresight/coresight-priv.h
index f1d0e21d..2bb0a15 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -64,7 +64,8 @@ static DEVICE_ATTR_RO(name)
 #define coresight_simple_reg64(type, name, lo_off, hi_off) \
__coresight_simple_func(type, NULL, name, lo_off, hi_off)
 
-extern const u32 barrier_pkt[5];
+extern const u32 barrier_pkt[4];
+#define CORESIGHT_BARRIER_PKT_SIZE (sizeof(barrier_pkt))
 
 enum etm_addr_type {
ETM_ADDR_TYPE_NONE,
@@ -98,6 +99,13 @@ struct cs_buffers {
void**data_pages;
 };
 
+static inline void coresight_insert_barrier_packet(void *buf)
+{
+   if (buf)
+   memcpy(buf, barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
+}
+
+
 static inline void CS_LOCK(void __iomem *addr)
 {
do {
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c 
b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index e5edf46..f30e5d8 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -43,39 +43,28 @@ static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
 
 static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
 {
-   bool lost = false;
char *bufp;
-   const u32 *barrier;
-   u32 read_data, status;
+   u32 read_data, lost;
int i;
 
-   /*
-* Get a hold of the status register and see if a wrap around
-* has occurred.
-*/
-   status = readl_relaxed(drvdata->base + TMC_STS);
-   if (status & TMC_STS_FULL)
-   lost = true;
-
+   /* Check if the buffer wrapped around. */
+   lost = readl_relaxed(drvdata->base + TMC_STS) & TMC_STS_FULL;
bufp = drvdata->buf;
drvdata->len = 0;
-   barrier = barrier_pkt;
while (1) {
for (i = 0; i < drvdata->memwidth; i++) {
read_data = readl_relaxed(drvdata->base + TMC_RRD);
if (read_data == 0x)
-   return;
-
-   if (lost && *barrier) {
-   read_data = *barrier;
-   barrier++;
-   }
-
+   goto done;
memcpy(bufp, &read_data, 4);
bufp += 4;
drvdata->len += 4;
}
}
+done:
+

[PATCH 09/11] coresight: Add support for TMC ETR SG unit

This patch adds support for setting up an SG table used by the
TMC ETR inbuilt SG unit. The TMC ETR uses 4K page sized tables
to hold pointers to the 4K data pages with the last entry in a
table pointing to the next table with the entries, by kind of
chaining. The 2 LSBs determine the type of the table entry, to
one of :

 Normal - Points to a 4KB data page.
 Last   - Points to a 4KB data page, but is the last entry in the
  page table.
 Link   - Points to another 4KB table page with pointers to data.

The code takes care of handling the system page size which could
be different than 4K. So we could end up putting multiple ETR
SG tables in a single system page, vice versa for the data pages.

Cc: Mathieu Poirier 
Signed-off-by: Suzuki K Poulose 
---
 drivers/hwtracing/coresight/coresight-tmc-etr.c | 263 
 1 file changed, 263 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c 
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 1e844f8..7ab0fd1 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -22,6 +22,87 @@
 #include "coresight-tmc.h"
 
 /*
+ * The TMC ETR SG has a page size of 4K. The SG table contains pointers
+ * to 4KB buffers. However, the OS may use a PAGE_SIZE different from
+ * 4K (i.e, 16KB or 64KB). This implies that a single OS page could
+ * contain more than one SG buffer and tables.
+ *
+ * A table entry has the following format:
+ *
+ * ---Bit31Bit4---Bit1-Bit0--
+ * | Address[39:12]| SBZ |  Entry Type  |
+ * --
+ *
+ * Address: Bits [39:12] of a physical page address. Bits [11:0] are
+ * always zero.
+ *
+ * Entry type:
+ * b00 - Reserved.
+ * b01 - Last entry in the tables, points to 4K page buffer.
+ * b10 - Normal entry, points to 4K page buffer.
+ * b11 - Link. The address points to the base of next table.
+ */
+
+typedef u32 sgte_t;
+
+#define ETR_SG_PAGE_SHIFT  12
+#define ETR_SG_PAGE_SIZE   (1UL << ETR_SG_PAGE_SHIFT)
+#define ETR_SG_PAGES_PER_SYSPAGE   (PAGE_SIZE / ETR_SG_PAGE_SIZE)
+#define ETR_SG_PTRS_PER_PAGE   (ETR_SG_PAGE_SIZE / sizeof(sgte_t))
+#define ETR_SG_PTRS_PER_SYSPAGE(PAGE_SIZE / sizeof(sgte_t))
+
+#define ETR_SG_ET_MASK 0x3
+#define ETR_SG_ET_LAST 0x1
+#define ETR_SG_ET_NORMAL   0x2
+#define ETR_SG_ET_LINK 0x3
+
+#define ETR_SG_ADDR_SHIFT  4
+
+#define ETR_SG_ENTRY(addr, type) \
+   (sgte_t)addr) >> ETR_SG_PAGE_SHIFT) << ETR_SG_ADDR_SHIFT) | \
+(type & ETR_SG_ET_MASK))
+
+#define ETR_SG_ADDR(entry) \
+   (((dma_addr_t)(entry) >> ETR_SG_ADDR_SHIFT) << ETR_SG_PAGE_SHIFT)
+#define ETR_SG_ET(entry)   ((entry) & ETR_SG_ET_MASK)
+
+/*
+ * struct etr_sg_table : ETR SG Table
+ * @sg_table:  Generic SG Table holding the data/table pages.
+ * @hwaddr:hwaddress used by the TMC, which is the base
+ * address of the table.
+ */
+struct etr_sg_table {
+   struct tmc_sg_table *sg_table;
+   dma_addr_t  hwaddr;
+};
+
+/*
+ * tmc_etr_sg_table_entries: Total number of table entries required to map
+ * @nr_pages system pages.
+ *
+ * We need to map @nr_pages * ETR_SG_PAGES_PER_SYSPAGE data pages.
+ * Each TMC page can map (ETR_SG_PTRS_PER_PAGE - 1) buffer pointers,
+ * with the last entry pointing to another page of table entries.
+ * If we spill over to a new page for mapping 1 entry, we could as
+ * well replace the link entry of the previous page with the last entry.
+ */
+static inline unsigned long __attribute_const__
+tmc_etr_sg_table_entries(int nr_pages)
+{
+   unsigned long nr_sgpages = nr_pages * ETR_SG_PAGES_PER_SYSPAGE;
+   unsigned long nr_sglinks = nr_sgpages / (ETR_SG_PTRS_PER_PAGE - 1);
+   /*
+* If we spill over to a new page for 1 entry, we could as well
+* make it the LAST entry in the previous page, skipping the Link
+* address.
+*/
+   if (nr_sglinks && (nr_sgpages % (ETR_SG_PTRS_PER_PAGE - 1) < 2))
+   nr_sglinks--;
+   return nr_sgpages + nr_sglinks;
+}
+
+/*
  * tmc_pages_get_offset:  Go through all the pages in the tmc_pages
  * and map the device address @addr to an offset within the virtual
  * contiguous buffer.
@@ -310,6 +391,188 @@ ssize_t tmc_sg_table_get_data(struct tmc_sg_table 
*sg_table,
return len;
 }
 
+#ifdef ETR_SG_DEBUG
+/* Map a dma address to virtual address */
+static unsigned long
+tmc_sg_daddr_to_vaddr(struct tmc_sg_table *sg_table,
+ dma_addr_t addr, bool table)
+{
+   long offset;
+   unsigned long base;
+   struct tmc_pages *tmc_pages;
+
+   if (table) {
+   tmc_pages = &sg_table->table_pages;
+   base = (unsigned long)sg_table->table_vaddr;
+   } else {
+

[PATCH 11/11] coresight: tmc: Add configuration support for trace buffer size

Now that we can dynamically switch between contiguous memory and
SG table depending on the trace buffer size, provide the support
for selecting an appropriate buffer size.

Cc: Mathieu Poirier 
Signed-off-by: Suzuki K Poulose 
---
 .../ABI/testing/sysfs-bus-coresight-devices-tmc|  8 ++
 .../devicetree/bindings/arm/coresight.txt  |  3 +-
 drivers/hwtracing/coresight/coresight-tmc.c| 33 ++
 3 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc 
b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc
index 4fe677e..ea78714 100644
--- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc
@@ -83,3 +83,11 @@ KernelVersion:   4.7
 Contact:   Mathieu Poirier 
 Description:   (R) Indicates the capabilities of the Coresight TMC.
The value is read directly from the DEVID register, 0xFC8,
+
+What:  /sys/bus/coresight/devices/.tmc/buffer_size
+Date:  August 2018
+KernelVersion: 4.18
+Contact:   Mathieu Poirier 
+Description:   (RW) Size of the trace buffer for TMC-ETR when used in SYSFS
+   mode. Writable only for TMC-ETR configurations. The value
+   should be aligned to the kernel pagesize.
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt 
b/Documentation/devicetree/bindings/arm/coresight.txt
index 603d3c6..9aa30a1 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -84,7 +84,8 @@ its hardware characteristcs.
 * Optional property for TMC:
 
* arm,buffer-size: size of contiguous buffer space for TMC ETR
-(embedded trace router)
+ (embedded trace router). This property is obsolete. The buffer size
+ can be configured dynamically via buffer_size property in sysfs.
 
* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
  use the SG mode on this system.
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c 
b/drivers/hwtracing/coresight/coresight-tmc.c
index 7d8331d..57b6621 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -285,8 +285,41 @@ static ssize_t trigger_cntr_store(struct device *dev,
 }
 static DEVICE_ATTR_RW(trigger_cntr);
 
+static ssize_t buffer_size_show(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+   return sprintf(buf, "%#x\n", drvdata->size);
+}
+
+static ssize_t buffer_size_store(struct device *dev,
+struct device_attribute *attr,
+const char *buf, size_t size)
+{
+   int ret;
+   unsigned long val;
+   struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+   /* Only permitted for TMC-ETRs */
+   if (drvdata->config_type != TMC_CONFIG_TYPE_ETR)
+   return -EPERM;
+
+   ret = kstrtoul(buf, 0, &val);
+   if (ret)
+   return ret;
+   /* The buffer size should be page aligned */
+   if (val & (PAGE_SIZE - 1))
+   return -EINVAL;
+   drvdata->size = val;
+   return size;
+}
+
+static DEVICE_ATTR_RW(buffer_size);
+
 static struct attribute *coresight_tmc_attrs[] = {
&dev_attr_trigger_cntr.attr,
+   &dev_attr_buffer_size.attr,
NULL,
 };
 
-- 
2.7.4

[PATCH 10/11] coresight: tmc-etr: Add transparent buffer management

At the moment we always use contiguous memory for TMC ETR tracing
when used from sysfs. The size of the buffer is fixed at boot time
and can only be changed by modifiying the DT. With the introduction
of SG support we could support really large buffers in that mode.
This patch abstracts the buffer used for ETR to switch between a
contiguous buffer or a SG table depending on the availability of
the memory.

This also enables the sysfs mode to use the ETR in SG mode depending
on configured the trace buffer size. Also, since ETR will use the
new infrastructure to manage the buffer, we can get rid of some
of the members in the tmc_drvdata and clean up the fields a bit.

Cc: Mathieu Poirier 
Signed-off-by: Suzuki K Poulose 
---
 drivers/hwtracing/coresight/coresight-tmc-etr.c | 450 +++-
 drivers/hwtracing/coresight/coresight-tmc.h |  57 ++-
 2 files changed, 418 insertions(+), 89 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c 
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 7ab0fd1..143afba 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -17,10 +17,18 @@
 
 #include 
 #include 
+#include 
 #include 
 #include "coresight-priv.h"
 #include "coresight-tmc.h"
 
+struct etr_flat_buf {
+   struct device   *dev;
+   dma_addr_t  daddr;
+   void*vaddr;
+   size_t  size;
+};
+
 /*
  * The TMC ETR SG has a page size of 4K. The SG table contains pointers
  * to 4KB buffers. However, the OS may use a PAGE_SIZE different from
@@ -541,7 +549,7 @@ static void tmc_etr_sg_table_populate(struct etr_sg_table 
*etr_table)
  * @size   - Total size of the data buffer
  * @pages  - Optional list of page virtual address
  */
-static struct etr_sg_table __maybe_unused *
+static struct etr_sg_table *
 tmc_init_etr_sg_table(struct device *dev, int node,
  unsigned long size, void **pages)
 {
@@ -573,16 +581,307 @@ tmc_init_etr_sg_table(struct device *dev, int node,
return etr_table;
 }
 
+/*
+ * tmc_etr_alloc_flat_buf: Allocate a contiguous DMA buffer.
+ */
+static int tmc_etr_alloc_flat_buf(struct tmc_drvdata *drvdata,
+ struct etr_buf *etr_buf, int node,
+ void **pages)
+{
+   struct etr_flat_buf *flat_buf;
+
+   /* We cannot reuse existing pages for flat buf */
+   if (pages)
+   return -EINVAL;
+
+   flat_buf = kzalloc(sizeof(*flat_buf), GFP_KERNEL);
+   if (!flat_buf)
+   return -ENOMEM;
+
+   flat_buf->vaddr = dma_alloc_coherent(drvdata->dev, etr_buf->size,
+  &flat_buf->daddr, GFP_KERNEL);
+   if (!flat_buf->vaddr) {
+   kfree(flat_buf);
+   return -ENOMEM;
+   }
+
+   flat_buf->size = etr_buf->size;
+   flat_buf->dev = drvdata->dev;
+   etr_buf->hwaddr = flat_buf->daddr;
+   etr_buf->mode = ETR_MODE_FLAT;
+   etr_buf->private = flat_buf;
+   return 0;
+}
+
+static void tmc_etr_free_flat_buf(struct etr_buf *etr_buf)
+{
+   struct etr_flat_buf *flat_buf = etr_buf->private;
+
+   if (flat_buf && flat_buf->daddr)
+   dma_free_coherent(flat_buf->dev, flat_buf->size,
+ flat_buf->vaddr, flat_buf->daddr);
+   kfree(flat_buf);
+}
+
+static void tmc_etr_sync_flat_buf(struct etr_buf *etr_buf, u64 rrp, u64 rwp)
+{
+   /*
+* Adjust the buffer to point to the beginning of the trace data
+* and update the available trace data.
+*/
+   etr_buf->offset = rrp - etr_buf->hwaddr;
+   if (etr_buf->full)
+   etr_buf->len = etr_buf->size;
+   else
+   etr_buf->len = rwp - rrp;
+}
+
+static ssize_t tmc_etr_get_data_flat_buf(struct etr_buf *etr_buf,
+u64 offset, size_t len, char **bufpp)
+{
+   struct etr_flat_buf *flat_buf = etr_buf->private;
+
+   *bufpp = (char *)flat_buf->vaddr + offset;
+   /*
+* tmc_etr_buf_get_data already adjusts the length to handle
+* buffer wrapping around.
+*/
+   return len;
+}
+
+static const struct etr_buf_operations etr_flat_buf_ops = {
+   .alloc = tmc_etr_alloc_flat_buf,
+   .free = tmc_etr_free_flat_buf,
+   .sync = tmc_etr_sync_flat_buf,
+   .get_data = tmc_etr_get_data_flat_buf,
+};
+
+/*
+ * tmc_etr_alloc_sg_buf: Allocate an SG buf @etr_buf. Setup the parameters
+ * appropriately.
+ */
+static int tmc_etr_alloc_sg_buf(struct tmc_drvdata *drvdata,
+   struct etr_buf *etr_buf, int node,
+   void **pages)
+{
+   struct etr_sg_table *etr_table;
+
+   etr_table = tmc_init_etr_sg_table(drvdata->dev, node,
+ etr_buf->size, pages);
+   if (IS_ERR(etr_table))
+   return -ENOMEM;
+   etr_buf

[PATCH 08/11] coresight: Add generic TMC sg table framework

This patch introduces a generic sg table data structure and
associated operations. An SG table can be used to map a set
of Data pages where the trace data could be stored by the TMC
ETR. The information about the data pages could be stored in
different formats, depending on the type of the underlying
SG mechanism (e.g, TMC ETR SG vs Coresight CATU). The generic
structure provides book keeping of the pages used for the data
as well as the table contents. The table should be filled by
the user of the infrastructure.

A table can be created by specifying the number of data pages
as well as the number of table pages required to hold the
pointers, where the latter could be different for different
types of tables. The pages are mapped in the appropriate dma
data direction mode (i.e, DMA_TO_DEVICE for table pages
and DMA_FROM_DEVICE for data pages).  The framework can optionally
accept a set of allocated data pages (e.g, perf ring buffer) and
map them accordingly. The table and data pages are vmap'ed to allow
easier access by the drivers. The framework also provides helpers to
sync the data written to the pages with appropriate directions.

This will be later used by the TMC ETR SG unit and CATU.

Cc: Mathieu Poirier 
Signed-off-by: Suzuki K Poulose 
---
Changes since v1:
 - Address code style issues, more comments
---
 drivers/hwtracing/coresight/coresight-tmc-etr.c | 290 
 drivers/hwtracing/coresight/coresight-tmc.h |  50 
 2 files changed, 340 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c 
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 9780798..1e844f8 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -17,9 +17,299 @@
 
 #include 
 #include 
+#include 
 #include "coresight-priv.h"
 #include "coresight-tmc.h"
 
+/*
+ * tmc_pages_get_offset:  Go through all the pages in the tmc_pages
+ * and map the device address @addr to an offset within the virtual
+ * contiguous buffer.
+ */
+static long
+tmc_pages_get_offset(struct tmc_pages *tmc_pages, dma_addr_t addr)
+{
+   int i;
+   dma_addr_t page_start;
+
+   for (i = 0; i < tmc_pages->nr_pages; i++) {
+   page_start = tmc_pages->daddrs[i];
+   if (addr >= page_start && addr < (page_start + PAGE_SIZE))
+   return i * PAGE_SIZE + (addr - page_start);
+   }
+
+   return -EINVAL;
+}
+
+/*
+ * tmc_pages_free : Unmap and free the pages used by tmc_pages.
+ * If the pages were not allocated in tmc_pages_alloc(), we would
+ * simply drop the refcount.
+ */
+static void tmc_pages_free(struct tmc_pages *tmc_pages,
+  struct device *dev, enum dma_data_direction dir)
+{
+   int i;
+
+   for (i = 0; i < tmc_pages->nr_pages; i++) {
+   if (tmc_pages->daddrs && tmc_pages->daddrs[i])
+   dma_unmap_page(dev, tmc_pages->daddrs[i],
+PAGE_SIZE, dir);
+   if (tmc_pages->pages && tmc_pages->pages[i])
+   __free_page(tmc_pages->pages[i]);
+   }
+
+   kfree(tmc_pages->pages);
+   kfree(tmc_pages->daddrs);
+   tmc_pages->pages = NULL;
+   tmc_pages->daddrs = NULL;
+   tmc_pages->nr_pages = 0;
+}
+
+/*
+ * tmc_pages_alloc : Allocate and map pages for a given @tmc_pages.
+ * If @pages is not NULL, the list of page virtual addresses are
+ * used as the data pages. The pages are then dma_map'ed for @dev
+ * with dma_direction @dir.
+ *
+ * Returns 0 upon success, else the error number.
+ */
+static int tmc_pages_alloc(struct tmc_pages *tmc_pages,
+  struct device *dev, int node,
+  enum dma_data_direction dir, void **pages)
+{
+   int i, nr_pages;
+   dma_addr_t paddr;
+   struct page *page;
+
+   nr_pages = tmc_pages->nr_pages;
+   tmc_pages->daddrs = kcalloc(nr_pages, sizeof(*tmc_pages->daddrs),
+GFP_KERNEL);
+   if (!tmc_pages->daddrs)
+   return -ENOMEM;
+   tmc_pages->pages = kcalloc(nr_pages, sizeof(*tmc_pages->pages),
+GFP_KERNEL);
+   if (!tmc_pages->pages) {
+   kfree(tmc_pages->daddrs);
+   tmc_pages->daddrs = NULL;
+   return -ENOMEM;
+   }
+
+   for (i = 0; i < nr_pages; i++) {
+   if (pages && pages[i]) {
+   page = virt_to_page(pages[i]);
+   /* Hold a refcount on the page */
+   get_page(page);
+   } else {
+   page = alloc_pages_node(node,
+   GFP_KERNEL | __GFP_ZERO, 0);
+   }
+   paddr = dma_map_page(dev, page, 0, PAGE_SIZE, dir);
+   if (dma_mapping_error(dev, paddr))
+   goto err;
+   tmc_pages-

[PATCH 06/11] dts: bindings: Restrict coresight tmc-etr scatter-gather mode

We are about to add the support for ETR builtin scatter-gather mode
for dealing with large amount of trace buffers. However, on some of
the platforms, using the ETR SG mode can lock up the system due to
the way the ETR is connected to the memory subsystem.

In SG mode, the ETR performs READ from the scatter-gather table to
fetch the next page and regular WRITE of trace data. If the READ
operation doesn't complete(due to the memory subsystem issues,
which we have seen on a couple of platforms) the trace WRITE
cannot proceed leading to issues. So, we by default do not
use the SG mode, unless it is known to be safe on the platform.
We define a DT property for the TMC node to specify whether we
have a proper SG mode.

Cc: Mathieu Poirier 
Cc: Mike Leach 
Cc: Mark Rutland 
Cc: John Horley 
Cc: Robert Walker 
Cc: devicet...@vger.kernel.org
Cc: frowand.l...@gmail.com
Cc: Rob Herring 
Signed-off-by: Suzuki K Poulose 
---
 Documentation/devicetree/bindings/arm/coresight.txt | 2 ++
 drivers/hwtracing/coresight/coresight-tmc.c | 9 -
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/coresight.txt 
b/Documentation/devicetree/bindings/arm/coresight.txt
index 15ac8e8..603d3c6 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -86,6 +86,8 @@ its hardware characteristcs.
* arm,buffer-size: size of contiguous buffer space for TMC ETR
 (embedded trace router)
 
+   * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
+ use the SG mode on this system.
 
 Example:
 
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c 
b/drivers/hwtracing/coresight/coresight-tmc.c
index 93c5bfc..7d8331d 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -304,6 +305,12 @@ const struct attribute_group *coresight_tmc_groups[] = {
NULL,
 };
 
+static inline bool tmc_etr_can_use_sg(struct tmc_drvdata *drvdata)
+{
+   return fwnode_property_present(drvdata->dev->fwnode,
+  "arm,scatter-gather");
+}
+
 /* Detect and initialise the capabilities of a TMC ETR */
 static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata,
 u32 devid, void *dev_caps)
@@ -313,7 +320,7 @@ static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata,
/* Set the unadvertised capabilities */
tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
 
-   if (!(devid & TMC_DEVID_NOSCAT))
+   if (!(devid & TMC_DEVID_NOSCAT) && tmc_etr_can_use_sg(drvdata))
tmc_etr_set_cap(drvdata, TMC_ETR_SG);
 
/* Check if the AXI address width is available */
-- 
2.7.4

[PATCH 00/11] coresight: tmc-etr Transparent buffer management

This series is split of the Coresight ETR perf support patches posted
here [0]. The CATU support and perf backend support will be posted as
separate series for better management and review of the patches.

This series adds the support for TMC ETR Scatter-Gather mode to allow
using physical non-contiguous buffer for holding the trace data. It
also adds a layer to handle the buffer management in a transparent
manner, independent of the underlying mode used by the TMC ETR.
The layer chooses the ETR mode based on different parameters (size,
re-using a set of pages, presence of an SMMU etc.).

Finally we add a sysfs parameter to tune the buffer size for ETR in
sysfs-mode.

During the testing, we found out that if the TMC ETR is not properly
connected to the memory subsystem, the ETR could lock-up the system
while waiting for the "read" transactions to complete in scatter-gather
mode. So, we do not use the mode on a system unless it is safe to do
so. This is specified by a DT property "arm,scatter-gather".

Applies on v4.17-rc4

Changes since v2 in [0] :
 - Split the series in [0]
 - Address comments on v2
 - Rename DT property "scatter-gather" to "arm,scatter-gather"
 - Add ETM PID for Cortex-A35, use macros to make the listing easier

[0] - http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/574875.html

Suzuki K Poulose (11):
  coresight: ETM: Add support for Arm Cortex-A73 and Cortex-A35
  coresight: tmc: Hide trace buffer handling for file read
  coresight: tmc-etr: Do not clean trace buffer
  coresight: tmc-etr: Disallow perf mode
  coresight: Add helper for inserting synchronization packets
  dts: bindings: Restrict coresight tmc-etr scatter-gather mode
  dts: juno: Add scatter-gather support for all revisions
  coresight: Add generic TMC sg table framework
  coresight: Add support for TMC ETR SG unit
  coresight: tmc-etr: Add transparent buffer management
  coresight: tmc: Add configuration support for trace buffer size

 .../ABI/testing/sysfs-bus-coresight-devices-tmc|8 +
 .../devicetree/bindings/arm/coresight.txt  |5 +-
 arch/arm64/boot/dts/arm/juno-base.dtsi |1 +
 drivers/hwtracing/coresight/coresight-etb10.c  |   12 +-
 drivers/hwtracing/coresight/coresight-etm4x.c  |   32 +-
 drivers/hwtracing/coresight/coresight-priv.h   |   10 +-
 drivers/hwtracing/coresight/coresight-tmc-etf.c|   45 +-
 drivers/hwtracing/coresight/coresight-tmc-etr.c| 1032 ++--
 drivers/hwtracing/coresight/coresight-tmc.c|   83 +-
 drivers/hwtracing/coresight/coresight-tmc.h|  111 ++-
 drivers/hwtracing/coresight/coresight.c|3 +-
 11 files changed, 1169 insertions(+), 173 deletions(-)

-- 
2.7.4

[PATCH 02/11] coresight: tmc: Hide trace buffer handling for file read

At the moment we adjust the buffer pointers for reading the trace
data via misc device in the common code for ETF/ETB and ETR. Since
we are going to change how we manage the buffer for ETR, let us
move the buffer manipulation to the respective driver files, hiding
it from the common code. We do so by adding type specific helpers
for finding the length of data and the pointer to the buffer,
for a given length at a file position.

Cc: Mathieu Poirier 
Signed-off-by: Suzuki K Poulose 
---
 drivers/hwtracing/coresight/coresight-tmc-etf.c | 18 +++
 drivers/hwtracing/coresight/coresight-tmc-etr.c | 34 
 drivers/hwtracing/coresight/coresight-tmc.c | 41 ++---
 drivers/hwtracing/coresight/coresight-tmc.h |  4 +++
 4 files changed, 79 insertions(+), 18 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c 
b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index e2513b7..e5edf46 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -120,6 +120,24 @@ static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
CS_LOCK(drvdata->base);
 }
 
+/*
+ * Return the available trace data in the buffer from @pos, with
+ * a maximum limit of @len, updating the @bufpp on where to
+ * find it.
+ */
+ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata,
+   loff_t pos, size_t len, char **bufpp)
+{
+   ssize_t actual = len;
+
+   /* Adjust the len to available size @pos */
+   if (pos + actual > drvdata->len)
+   actual = drvdata->len - pos;
+   if (actual > 0)
+   *bufpp = drvdata->buf + pos;
+   return actual;
+}
+
 static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev)
 {
int ret = 0;
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c 
b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 68fbc8f..d3c2b04 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -69,6 +69,40 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
CS_LOCK(drvdata->base);
 }
 
+/*
+ * Return the available trace data in the buffer @pos, with a maximum
+ * limit of @len, also updating the @bufpp on where to find it.
+ */
+ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
+   loff_t pos, size_t len, char **bufpp)
+{
+   ssize_t actual = len;
+   char *bufp = drvdata->buf + pos;
+   char *bufend = (char *)(drvdata->vaddr + drvdata->size);
+
+   /* Adjust the len to available size @pos */
+   if (pos + actual > drvdata->len)
+   actual = drvdata->len - pos;
+
+   if (actual <= 0)
+   return actual;
+
+   /*
+* Since we use a circular buffer, with trace data starting
+* @drvdata->buf, possibly anywhere in the buffer @drvdata->vaddr,
+* wrap the current @pos to within the buffer.
+*/
+   if (bufp >= bufend)
+   bufp -= drvdata->size;
+   /*
+* For simplicity, avoid copying over a wrapped around buffer.
+*/
+   if ((bufp + actual) > bufend)
+   actual = bufend - bufp;
+   *bufpp = bufp;
+   return actual;
+}
+
 static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
 {
const u32 *barrier;
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c 
b/drivers/hwtracing/coresight/coresight-tmc.c
index 0ea04f5..93c5bfc 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -131,35 +131,40 @@ static int tmc_open(struct inode *inode, struct file 
*file)
return 0;
 }
 
+static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata,
+ loff_t pos, size_t len, char **bufpp)
+{
+   switch (drvdata->config_type) {
+   case TMC_CONFIG_TYPE_ETB:
+   case TMC_CONFIG_TYPE_ETF:
+   return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp);
+   case TMC_CONFIG_TYPE_ETR:
+   return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
+   }
+
+   return -EINVAL;
+}
+
 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
loff_t *ppos)
 {
+   char *bufp;
+   ssize_t actual;
struct tmc_drvdata *drvdata = container_of(file->private_data,
   struct tmc_drvdata, miscdev);
-   char *bufp = drvdata->buf + *ppos;
+   actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp);
+   if (actual <= 0)
+   return 0;
 
-   if (*ppos + len > drvdata->len)
-   len = drvdata->len - *ppos;
-
-   if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
-   if (bufp == (char *)(drvdata->vaddr + drvdata->size))
-   bufp = drvdata->vaddr;
-   else

Re: [PATCH] net: ethernet: ti: cpsw: fix packet leaking in dual_mac mode

2018-05-18 Thread Grygorii Strashko




On 05/17/2018 02:10 PM, Greg Kroah-Hartman wrote:

On Thu, May 17, 2018 at 11:18:16PM +0530, Naresh Kamboju wrote:

On 2 May 2018 at 20:38, David Miller  wrote:

From: Grygorii Strashko 
Date: Tue, 1 May 2018 12:41:22 -0500



Signed-off-by: Grygorii Strashko 


Applied and queued up for -stable, thank you.


4.4 stable-rc build failed for arm32.
MACHINE=am57xx-evm

Build error log:

drivers/net/ethernet/ti/cpsw.c:
  In function 'cpsw_add_dual_emac_def_ale_entries':
drivers/net/ethernet/ti/cpsw.c:1112:23:
  error: 'cpsw' undeclared (first use in this function)
cpsw_ale_control_set(cpsw->ale, slave_port,
 ^~~~
drivers/net/ethernet/ti/cpsw.c:1112:23: note:
  each undeclared identifier is reported only once for each function it appears
  in
scripts/Makefile.build:269: recipe for target 'drivers/net/ethernet/ti/cpsw.o'
  failed
  make[6]: *** [drivers/net/ethernet/ti/cpsw.o] Error 1
scripts/Makefile.build:476: recipe for target 'drivers/net/ethernet/ti' failed
  make[5]: *** [drivers/net/ethernet/ti] Error 2



Now dropped, it's nice to see I got 3 reports about this :)



Sry, my bad. I've tested till 4.4 if it can be applied without 
conflicts, but not tested build.


--
regards,
-grygorii

Re: [PATCH v5 4/4] drm/rockchip: support dp training outside dp firmware

2018-05-18 Thread Heiko Stuebner

Am Freitag, 18. Mai 2018, 17:36:56 CEST schrieb Sean Paul:
> On Fri, May 18, 2018 at 10:52:17AM +0200, Heiko Stuebner wrote:
> > Am Freitag, 18. Mai 2018, 03:45:46 CEST schrieb Brian Norris:
> > > On Thu, May 17, 2018 at 6:41 PM, hl  wrote:
> > > > On Thursday, May 17, 2018 09:51 PM, Sean Paul wrote:
> > > >> On Thu, May 17, 2018 at 05:18:00PM +0800, Lin Huang wrote:
> > > >>> DP firmware uses fixed phy config values to do training, but some
> > > >>> boards need to adjust these values to fit for their unique hardware
> > > >>> design. So get phy config values from dts and use software link 
> > > >>> training
> > > >>> instead of relying on firmware, if software training fail, keep 
> > > >>> firmware
> > > >>> training as a fallback if sw training fails.
> > > >>>
> > > >>> Signed-off-by: Chris Zhong 
> > > >>> Signed-off-by: Lin Huang 
> > > >>> ---
> > > >>> Changes in v2:
> > > >>> - update patch following Enric suggest
> > > >>> Changes in v3:
> > > >>> - use variable fw_training instead sw_training_success
> > > >>> - base on DP SPCE, if training fail use lower link rate to retry 
> > > >>> training
> > > >>> Changes in v4:
> > > >>> - improve cdn_dp_get_lower_link_rate() and 
> > > >>> cdn_dp_software_train_link() follow Sean suggest
> > > >>> Changes in v5:
> > > >>> - fix some whitespcae issue
> > > >>>
> > > >>>   drivers/gpu/drm/rockchip/Makefile   |   3 +-
> > > >>>   drivers/gpu/drm/rockchip/cdn-dp-core.c  |  24 +-
> > > >>>   drivers/gpu/drm/rockchip/cdn-dp-core.h  |   2 +
> > > >>>   drivers/gpu/drm/rockchip/cdn-dp-link-training.c | 420 
> > > >>> 
> > > >>>   drivers/gpu/drm/rockchip/cdn-dp-reg.c   |  31 +-
> > > >>>   drivers/gpu/drm/rockchip/cdn-dp-reg.h   |  38 ++-
> > > >>>   6 files changed, 505 insertions(+), 13 deletions(-)
> > > >>>   create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-link-training.c
> > > >>>
> > > ...
> > > >>> diff --git a/drivers/gpu/drm/rockchip/cdn-dp-link-training.c 
> > > >>> b/drivers/gpu/drm/rockchip/cdn-dp-link-training.c
> > > >>> new file mode 100644
> > > >>> index 000..73c3290
> > > >>> --- /dev/null
> > > >>> +++ b/drivers/gpu/drm/rockchip/cdn-dp-link-training.c
> > > >>> @@ -0,0 +1,420 @@
> > > >>> +// SPDX-License-Identifier: GPL-2.0
> > > >>> +/*
> > > >>> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
> > > >>> + * Author: Chris Zhong 
> > > >>> + */
> > > >>> +
> > > >>> +#include 
> > > >>> +#include 
> > > >>> +#include 
> > > >>> +#include 
> > > >>> +
> > > >>> +#include "cdn-dp-core.h"
> > > >>> +#include "cdn-dp-reg.h"
> > > >>> +
> > > >>> +static void cdn_dp_set_signal_levels(struct cdn_dp_device *dp)
> > > >>> +{
> > > >>> +   struct cdn_dp_port *port = dp->port[dp->active_port];
> > > >>> +   struct rockchip_typec_phy *tcphy = phy_get_drvdata(port->phy);
> > > >>
> > > >> You ignored Brian's comment on the previous patch:
> > > >>This is still antithetical to the PHY framework; you're assuming 
> > > >> that
> > > >>this is a particular type of PHY here.
> > > >>
> > > >> FWIW, the mediatek drm driver also assumes a certain PHY type. A quick 
> > > >> grep of
> > > >> drivers/ shows that the only other non-phy/ driver using this function
> > > >> (pinctrl-tegra-xusb.c) also casts it.
> > > >>
> > > >> Sean
> > > >
> > > > Thanks Sean, except phy framework have new API to handle it, i have not
> > > > idea how to do it in a better way.
> > > 
> > > Well, if Mediatek can do it for their MIPI and HDMI, then maybe we just 
> > > do it...
> > 
> > I'd think so too. This is in Rockchip-specific code so it will always be
> > possible to easily get the soc-type and thus phy-type, if that combination
> > really changes down the road.
> > 
> 
> So in the absence of a better solution, and with prior art,
> 
> Reviewed-by: Sean Paul 
> 
> 
> We just need some eyes on the dt and phy changes in this set. Heiko, can you
> help out with that?

done, but both the binding + phy changes should also get Acks from
Rob (dt) and Kishon (phy). Especially as the binding change is a bit more
than a new simple property.


Heiko

Re: [PATCH v5 3/9] dt-bindings: input: touchscreen: add minimum pressure touchscreen property

On Thu, May 10, 2018 at 01:45:08PM +0300, Eugen Hristev wrote:
> Add a common touchscreen optional property that will specify
> the minimum pressure applied to the screen that is needed
> such that the driver will report the touch event.
> 
> Signed-off-by: Eugen Hristev 
> ---
> Changes in v5:
>  - Modified property name to touchscreen-min-pressure from
> touchscreen-threshold-property
> 
>  Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt | 3 +++
>  1 file changed, 3 insertions(+)

Reviewed-by: Rob Herring

Re: [PATCH v6 2/4] rtc: ds1307: support m41t11 variant

On Wed, May 16, 2018 at 11:08:40PM +0200, Giulio Benetti wrote:
> The m41t11 variant is very similar to the already supported m41t00 and
> m41t0, but it has also 56 bytes of NVRAM.
> 
> Add it to driver taking into account NVRAM section.
> 
> Signed-off-by: Giulio Benetti 
> ---
>  .../devicetree/bindings/rtc/rtc-ds1307.txt |  1 +
>  drivers/rtc/rtc-ds1307.c   | 14 ++
>  2 files changed, 15 insertions(+)

Reviewed-by: Rob Herring

Re: [PATCH] audit: add containerid support for IMA-audit

2018-05-18 Thread Mimi Zohar

On Fri, 2018-05-18 at 11:56 -0400, Richard Guy Briggs wrote:
> On 2018-05-18 10:39, Mimi Zohar wrote:
> > On Fri, 2018-05-18 at 09:54 -0400, Stefan Berger wrote:
> > > On 05/18/2018 08:53 AM, Mimi Zohar wrote:
> > 
> > [..]
> > 
> > >  If so, which ones? We could probably refactor the current
> > >  integrity_audit_message() and have ima_parse_rule() call into it to 
> > >  get
> > >  those fields as well. I suppose adding new fields to it wouldn't be
> > >  considered breaking user space?
> > > >>> Changing the order of existing fields or inserting fields could break
> > > >>> stuff and is strongly discouraged without a good reason, but appending
> > > >>> fields is usually the right way to add information.
> > > >>>
> > > >>> There are exceptions, and in this case, I'd pick the "more standard" 
> > > >>> of
> > > >>> the formats for AUDIT_INTEGRITY_RULE (ima_audit_measurement?) and 
> > > >>> stick
> > > >>> with that, abandoning the other format, renaming the less standard
> > > >>> version of the record (ima_parse_rule?) and perhpas adopting that
> > > >>> abandonned format for the new record type while using
> > > >>> current->audit_context.
> > > > This sounds right, other than "type=INTEGRITY_RULE" (1805) for
> > > > ima_audit_measurement().  Could we rename type=1805 to be
> > > 
> > > So do we want to change both? I thought that what 
> > > ima_audit_measurement() produces looks ok but may not have a good name 
> > > for the 'type'. Now in this case I would not want to 'break user space'.
> > > The only change I was going to make was to what ima_parse_rule() produces.
> > 
> > The only change for now is separating the IMA policy rules from the
> > IMA-audit messages.
> > 
> > Richard, when the containerid is appended to the IMA-audit messages,
> > would we make the audit type name change then?
> 
> No, go ahead and make the change now.  I'm expecting that the
> containerid record will just be another auxiliary record and should not
> affect you folks.

To summarize, we need to disambiguate the 1805, as both
ima_parse_rule() and ima_audit_measurement() are using the same number
with different formats.  The main usage of 1805 that we are aware of
is ima_audit_measurement().  Yet the "type=" name for
ima_audit_measurement() should be INTEGRITY_IMA_AUDIT, not
INTEGRITY_RULE.

option 1: breaks both uses
1805 - INTEGRITY_IMA_AUDIT - ima_audit_measurement()
1806 - INTEGRITY_POLICY_RULE - ima_parse_rule()

option 2: breaks the most common usage
1805 - INTEGRITY_RULE - ima_parse_rule()
1806 - INTEGRITY_IMA_AUDIT - ima_audit_measurement()

option 3: leaves the most common usage with the wrong name, and breaks
the other less common usage
1805 - INTEGRITY_RULE - ima_audit_measurement()
1806 - INTEGRITY_POLICY_RULE - ima_parse_rule()

So option 3 is the best option?

Mimi

Re: [PATCH v5 3/4] phy: rockchip-typec: support variable phy config value

2018-05-18 Thread Heiko Stuebner

Hi,

Am Donnerstag, 17. Mai 2018, 11:17:59 CEST schrieb Lin Huang:
> the phy config values used to fix in dp firmware, but some boards
> need change these values to do training and get the better eye diagram
> result. So support that in phy driver.
> 
> Signed-off-by: Chris Zhong 
> Signed-off-by: Lin Huang 

I don't see anything obvious.

One could argue, that splitting out of the structs into the header could
be a separate patch, especially as the reason for it is not spelled out
in the commit message at all - and the reason only becomes visible when
also reading patch4.

But what is even more important is keeping Kishon as the phy-maintainer
in the loop. I've done that here, but please make sure that following
versions also get a Cc to
Kishon Vijay Abraham I 

As the patch will probably need an Ack to get through the drm-tree.


Heiko



> ---
> Changes in v2:
> - update patch following Enric suggest
> Changes in v3:
> - delete need_software_training variable
> - add default phy config value, if dts do not define phy config value, use 
> these value
> Changes in v4:
> - rename variable config to tcphy_default_config
> Changes in v5:
> - None
> 
>  drivers/phy/rockchip/phy-rockchip-typec.c | 306 
> --
>  include/soc/rockchip/rockchip_phy_typec.h |  63 ++
>  2 files changed, 271 insertions(+), 98 deletions(-)
>  create mode 100644 include/soc/rockchip/rockchip_phy_typec.h
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c 
> b/drivers/phy/rockchip/phy-rockchip-typec.c
> index 76a4b58..5d8692d 100644
> --- a/drivers/phy/rockchip/phy-rockchip-typec.c
> +++ b/drivers/phy/rockchip/phy-rockchip-typec.c
> @@ -63,6 +63,7 @@
>  
>  #include 
>  #include 
> +#include 
>  
>  #define CMN_SSM_BANDGAP  (0x21 << 2)
>  #define CMN_SSM_BIAS (0x22 << 2)
> @@ -323,21 +324,29 @@
>   * clock 0: PLL 0 div 1
>   * clock 1: PLL 1 div 2
>   */
> -#define CLK_PLL_CONFIG   0X30
> +#define CLK_PLL1_DIV10x20
> +#define CLK_PLL1_DIV20x30
>  #define CLK_PLL_MASK 0x33
>  
>  #define CMN_READYBIT(0)
>  
> +#define DP_PLL_CLOCK_ENABLE_ACK  BIT(3)
>  #define DP_PLL_CLOCK_ENABLE  BIT(2)
> +#define DP_PLL_ENABLE_ACKBIT(1)
>  #define DP_PLL_ENABLEBIT(0)
>  #define DP_PLL_DATA_RATE_RBR ((2 << 12) | (4 << 8))
>  #define DP_PLL_DATA_RATE_HBR ((2 << 12) | (4 << 8))
>  #define DP_PLL_DATA_RATE_HBR2((1 << 12) | (2 << 8))
> +#define DP_PLL_DATA_RATE_MASK0xff00
>  
> -#define DP_MODE_A0   BIT(4)
> -#define DP_MODE_A2   BIT(6)
> -#define DP_MODE_ENTER_A0 0xc101
> -#define DP_MODE_ENTER_A2 0xc104
> +#define DP_MODE_MASK 0xf
> +#define DP_MODE_ENTER_A0 BIT(0)
> +#define DP_MODE_ENTER_A2 BIT(2)
> +#define DP_MODE_ENTER_A3 BIT(3)
> +#define DP_MODE_A0_ACK   BIT(4)
> +#define DP_MODE_A2_ACK   BIT(6)
> +#define DP_MODE_A3_ACK   BIT(7)
> +#define DP_LINK_RESET_DEASSERTED BIT(8)
>  
>  #define PHY_MODE_SET_TIMEOUT 10
>  
> @@ -349,51 +358,7 @@
>  #define MODE_DFP_USB BIT(1)
>  #define MODE_DFP_DP  BIT(2)
>  
> -struct usb3phy_reg {
> - u32 offset;
> - u32 enable_bit;
> - u32 write_enable;
> -};
> -
> -/**
> - * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
> - * @reg: the base address for usb3-phy config.
> - * @typec_conn_dir: the register of type-c connector direction.
> - * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
> - * @external_psm: the register of type-c phy external psm clock.
> - * @pipe_status: the register of type-c phy pipe status.
> - * @usb3_host_disable: the register of type-c usb3 host disable.
> - * @usb3_host_port: the register of type-c usb3 host port.
> - * @uphy_dp_sel: the register of type-c phy DP select control.
> - */
> -struct rockchip_usb3phy_port_cfg {
> - unsigned int reg;
> - struct usb3phy_reg typec_conn_dir;
> - struct usb3phy_reg usb3tousb2_en;
> - struct usb3phy_reg external_psm;
> - struct usb3phy_reg pipe_status;
> - struct usb3phy_reg usb3_host_disable;
> - struct usb3phy_reg usb3_host_port;
> - struct usb3phy_reg uphy_dp_sel;
> -};
> -
> -struct rockchip_typec_phy {
> - struct device *dev;
> - void __iomem *base;
> - struct extcon_dev *extcon;
> - struct regmap *grf_regs;
> - struct clk *clk_core;
> - struct clk *clk_ref;
> - struct reset_control *uphy_rst;
> - struct reset_control *pipe_rst;
> - struct reset_control *tcphy_rst;
> - const struct rockchip_usb3phy_port_cfg *port_cfgs;
> - /* mutex to protect access to individual PHYs */
> - struct mutex lock;
> -
> - bool flip;
>

Re: [PATCH v6 8/9] counter: stm32-lptimer: add counter device

On Wed, May 16, 2018 at 01:52:27PM -0400, William Breathitt Gray wrote:
> From: Fabrice Gasnier 
> 
> Add support for new counter device to stm32-lptimer.
> 
> Signed-off-by: Fabrice Gasnier 
> Signed-off-by: William Breathitt Gray 
> ---
>  .../{iio => }/counter/stm32-lptimer-cnt.txt   |   0
>  .../devicetree/bindings/mfd/stm32-lptimer.txt |   2 +-

Please split bindings to separate patch.

>  drivers/counter/Kconfig   |  10 +
>  drivers/counter/Makefile  |   1 +
>  drivers/counter/stm32-lptimer-cnt.c   | 722 ++
>  drivers/iio/counter/Kconfig   |   9 -
>  drivers/iio/counter/Makefile  |   2 -
>  drivers/iio/counter/stm32-lptimer-cnt.c   | 382 -
>  8 files changed, 734 insertions(+), 394 deletions(-)
>  rename Documentation/devicetree/bindings/{iio => 
> }/counter/stm32-lptimer-cnt.txt (100%)
>  create mode 100644 drivers/counter/stm32-lptimer-cnt.c
>  delete mode 100644 drivers/iio/counter/stm32-lptimer-cnt.c

Re: [PATCH 00/10] Misc block layer patches for bcachefs

2018-05-18 Thread Jens Axboe

On 5/18/18 10:23 AM, Christoph Hellwig wrote:
> On Fri, May 11, 2018 at 03:13:38PM -0600, Jens Axboe wrote:
>> Looked over the series, and looks like both good cleanups and optimizations.
>> If we can get the mempool patch sorted, I can apply this for 4.18.
> 
> FYI, I agree on the actual cleanups and optimization, but we really
> shouldn't add new functions or even just exports without the code
> using them.  I think it is enough if we can collect ACKs on them, but
> there is no point in using them.  Especially as I'd really like to see
> the users for some of them first.

I certainly agree on that in general, but at the same time it makes the
expected submission of bcachefs not having to carry a number of
(essentially) unrelated patches. I'm assuming the likelihood of bcachefs
being submitted soonish is high, hence we won't have exports that don't
have in-kernel users in the longer term.

-- 
Jens Axboe

[PATCH] tc-testing: fix ip address in u32 test

2018-05-18 Thread Vlad Buslov

Fix expected ip address to actually match configured ip address.
Fix test to expect single matched filter.

Signed-off-by: Vlad Buslov 
---
 tools/testing/selftests/tc-testing/tc-tests/filters/tests.json | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/tc-testing/tc-tests/filters/tests.json 
b/tools/testing/selftests/tc-testing/tc-tests/filters/tests.json
index 5fa02d8..99a5ffc 100644
--- a/tools/testing/selftests/tc-testing/tc-tests/filters/tests.json
+++ b/tools/testing/selftests/tc-testing/tc-tests/filters/tests.json
@@ -12,8 +12,8 @@
 "cmdUnderTest": "$TC filter add dev $DEV1 parent : protocol ip 
prio 1 u32 match ip src 127.0.0.1/32 flowid 1:1 action ok",
 "expExitCode": "0",
 "verifyCmd": "$TC filter show dev $DEV1 parent :",
-"matchPattern": "match 7f02/ at 12",
-"matchCount": "0",
+"matchPattern": "match 7f01/ at 12",
+"matchCount": "1",
 "teardown": [
 "$TC qdisc del dev $DEV1 ingress"
 ]
-- 
2.7.5

Re: [PATCH 2/6] x86: bug: prevent gcc distortions

2018-05-18 Thread Nadav Amit

Borislav Petkov  wrote:

> On Fri, May 18, 2018 at 03:46:33PM +, Nadav Amit wrote:
>> In case you didn’t read the cover-letter: the patch-set does give a 2%
>> performance improvement for #PF-MADV_DONTNEED microbenchmark loop.
> 
> I saw it but *micro*-benchmark doesn't tell me a whole lot. If that
> "improvement" is not visible in real workloads/benchmarks, then I'm just
> as unimpressed.

Funny. I found in my mailbox that you once wrote me: "It is a dumb idea, it
doesn't bring us anything besides some superficial readability which you
don't really need.”

To the point, I think you exaggerate with the effect of the patch on the
code readability: it is not much uglier than it was before, and the change
is in a very specific point in the code.

Re: [PATCH v3 0/5]

2018-05-18 Thread Vince Weaver

On Fri, 18 May 2018, Marc Zyngier wrote:

> There is also the case of people natively running 32bit kernels on
> 64bit HW and trying to upstream unspeakable hacks, hoping that the
> stars will align and that they'll win the lottery (see [1]).

I've tested these patches on a Raspberry Pi 3B running a 32-bit upstream 
(4.17-rc5-git) kernel and they work.

[0.472906] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 
counters available

I only needed to add this to the devicetree

arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupt-parent = <&local_intc>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
};


Tested-by: Vince Weaver 

Vince

Re: [PATCH v6 6/9] dt-bindings: counter: Document stm32 quadrature encoder