Re: [PATCH v1 2/2] vfio/mdev: Removed unused and redundant API for mdev UUID

[Cornelia Huck]

On Tue,  6 Aug 2019 09:18:26 -0500
Parav Pandit  wrote:

> There is no single production driver who is interested in mdev device
> uuid. Currently UUID is mainly used to derive a device name.
> Additionally mdev device name is already available using core kernel
> API dev_name().

Well, the mdev code actually uses the uuid to check for duplicates
before registration with the driver core would fail... I'd just drop
the two sentences talking about the device name, IMHO they don't really
add useful information; but I'll leave that decision to the maintainers.

> 
> Hence removed unused exported symbol.
> 
> Signed-off-by: Parav Pandit 
> ---
> Changelog:
> v0->v1:
>  - Updated commit log to address comments from Cornelia
> ---
>  drivers/vfio/mdev/mdev_core.c | 6 --
>  include/linux/mdev.h  | 1 -
>  2 files changed, 7 deletions(-)

Reviewed-by: Cornelia Huck 

Re: [PATCH 4/5] media/ivtv: Reduce default FIFO priority

[Hans Verkuil]

On 8/2/19 10:58 AM, Peter Zijlstra wrote:
> On Thu, Aug 01, 2019 at 02:38:06PM +0200, Peter Zijlstra wrote:
>> If the consumer of the data are RT tasks as well (I hadn't expected that
>> from a TV capture device) then I'd propose to use FIFO-50 as default.
>>
>> The thing is, the moment you're doing actual proper RT, the admin needs
>> to configure things anyway, which then very much includes setting the
>> priority of interrupt threads and the like.
>>
>> (that is exacty why pretty much everything defaults to FIFO-50)
> 
> Is the below acceptible?

I think this should be OK. ivtv is real-time sensitive since certain
tasks have to happen within (if I remember correctly) 1/60th of a second
(the time it takes to capture a single video field). Data is lost if it
can't be done within that time.

Using FIFO-50 means that it competes with other irq threads, and since
irq threads shouldn't take up much time anyway this should be OK.

Andy, what do you think?

Regards,

Hans

> 
> ---
> Subject: media/ivtv: Reduce default FIFO priority
> From: Peter Zijlstra 
> Date: Thu Aug  1 12:56:40 CEST 2019
> 
> The ivtv driver creates a FIFO-99 thread by default, reduce this to
> FIFO-50.
> 
> FIFO-99 is the very highest priority available to SCHED_FIFO and
> it not a suitable default; it would indicate the ivtv work is the
> most important work on the machine.
> 
> Cc: Andy Walls 
> Cc: Mauro Carvalho Chehab 
> Cc: linux-me...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: Thomas Gleixner 
> Signed-off-by: Peter Zijlstra (Intel) 
> ---
>  drivers/media/pci/ivtv/ivtv-driver.c |2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> --- a/drivers/media/pci/ivtv/ivtv-driver.c
> +++ b/drivers/media/pci/ivtv/ivtv-driver.c
> @@ -738,7 +738,7 @@ static void ivtv_process_options(struct
>   */
>  static int ivtv_init_struct1(struct ivtv *itv)
>  {
> - struct sched_param param = { .sched_priority = 99 };
> + struct sched_param param = { .sched_priority = MAX_RT_PRIO / 2 };
>  
>   itv->base_addr = pci_resource_start(itv->pdev, 0);
>   itv->enc_mbox.max_mbox = 2; /* the encoder has 3 mailboxes (0-2) */
> 

Re: [PATCH v2] bcache: fix deadlock in bcache_allocator

[Andrea Righi]

On Tue, Aug 06, 2019 at 07:36:48PM +0200, Andrea Righi wrote:
> On Tue, Aug 06, 2019 at 11:18:01AM +0200, Andrea Righi wrote:
> > bcache_allocator() can call the following:
> > 
> >  bch_allocator_thread()
> >   -> bch_prio_write()
> >  -> bch_bucket_alloc()
> > -> wait on >set->bucket_wait
> > 
> > But the wake up event on bucket_wait is supposed to come from
> > bch_allocator_thread() itself => deadlock:
> > 
> > [ 1158.490744] INFO: task bcache_allocato:15861 blocked for more than 10 
> > seconds.
> > [ 1158.495929]   Not tainted 5.3.0-050300rc3-generic #201908042232
> > [ 1158.500653] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables 
> > this message.
> > [ 1158.504413] bcache_allocato D0 15861  2 0x80004000
> > [ 1158.504419] Call Trace:
> > [ 1158.504429]  __schedule+0x2a8/0x670
> > [ 1158.504432]  schedule+0x2d/0x90
> > [ 1158.504448]  bch_bucket_alloc+0xe5/0x370 [bcache]
> > [ 1158.504453]  ? wait_woken+0x80/0x80
> > [ 1158.504466]  bch_prio_write+0x1dc/0x390 [bcache]
> > [ 1158.504476]  bch_allocator_thread+0x233/0x490 [bcache]
> > [ 1158.504491]  kthread+0x121/0x140
> > [ 1158.504503]  ? invalidate_buckets+0x890/0x890 [bcache]
> > [ 1158.504506]  ? kthread_park+0xb0/0xb0
> > [ 1158.504510]  ret_from_fork+0x35/0x40
> > 
> > Fix by making the call to bch_prio_write() non-blocking, so that
> > bch_allocator_thread() never waits on itself.
> > 
> > Moreover, make sure to wake up the garbage collector thread when
> > bch_prio_write() is failing to allocate buckets.
> > 
> > BugLink: https://bugs.launchpad.net/bugs/1784665
> > BugLink: https://bugs.launchpad.net/bugs/1796292
> > Signed-off-by: Andrea Righi 
> > ---
> > Changes in v2:
> >  - prevent retry_invalidate busy loop in bch_allocator_thread()
> > 
> >  drivers/md/bcache/alloc.c  |  5 -
> >  drivers/md/bcache/bcache.h |  2 +-
> >  drivers/md/bcache/super.c  | 13 +
> >  3 files changed, 14 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/md/bcache/alloc.c b/drivers/md/bcache/alloc.c
> > index 6f776823b9ba..a1df0d95151c 100644
> > --- a/drivers/md/bcache/alloc.c
> > +++ b/drivers/md/bcache/alloc.c
> > @@ -377,7 +377,10 @@ static int bch_allocator_thread(void *arg)
> > if (!fifo_full(>free_inc))
> > goto retry_invalidate;
> >  
> > -   bch_prio_write(ca);
> > +   if (bch_prio_write(ca, false) < 0) {
> > +   ca->invalidate_needs_gc = 1;
> > +   wake_up_gc(ca->set);
> > +   }
> > }
> > }
> >  out:
> > diff --git a/drivers/md/bcache/bcache.h b/drivers/md/bcache/bcache.h
> > index 013e35a9e317..deb924e1d790 100644
> > --- a/drivers/md/bcache/bcache.h
> > +++ b/drivers/md/bcache/bcache.h
> > @@ -977,7 +977,7 @@ bool bch_cached_dev_error(struct cached_dev *dc);
> >  __printf(2, 3)
> >  bool bch_cache_set_error(struct cache_set *c, const char *fmt, ...);
> >  
> > -void bch_prio_write(struct cache *ca);
> > +int bch_prio_write(struct cache *ca, bool wait);
> >  void bch_write_bdev_super(struct cached_dev *dc, struct closure *parent);
> >  
> >  extern struct workqueue_struct *bcache_wq;
> > diff --git a/drivers/md/bcache/super.c b/drivers/md/bcache/super.c
> > index 20ed838e9413..716ea272fb55 100644
> > --- a/drivers/md/bcache/super.c
> > +++ b/drivers/md/bcache/super.c
> > @@ -529,7 +529,7 @@ static void prio_io(struct cache *ca, uint64_t bucket, 
> > int op,
> > closure_sync(cl);
> >  }
> >  
> > -void bch_prio_write(struct cache *ca)
> > +int bch_prio_write(struct cache *ca, bool wait)
> >  {
> > int i;
> > struct bucket *b;
> > @@ -564,8 +564,12 @@ void bch_prio_write(struct cache *ca)
> > p->magic= pset_magic(>sb);
> > p->csum = bch_crc64(>magic, bucket_bytes(ca) - 8);
> >  
> > -   bucket = bch_bucket_alloc(ca, RESERVE_PRIO, true);
> > -   BUG_ON(bucket == -1);
> > +   bucket = bch_bucket_alloc(ca, RESERVE_PRIO, wait);
> > +   if (bucket == -1) {
> > +   if (!wait)
> > +   return -ENOMEM;
> > +   BUG_ON(1);
> > +   }
> 
> Coly,
> 
> looking more at this change, I think we should handle the failure path
> properly or we may leak buckets, am I right? (sorry for not realizing
> this before). Maybe we need something like the following on top of my
> previous patch.
> 
> I'm going to run more stress tests with this patch applied and will try
> to figure out if we're actually leaking buckets without it.
> 
> ---
> Subject: bcache: prevent leaking buckets in bch_prio_write()
> 
> Handle the allocation failure path properly in bch_prio_write() to avoid
> leaking buckets from the previous successful iterations.
> 
> Signed-off-by: Andrea Righi 

Coly, ignore this one please. A v3 of the previous patch with a better
fix for this potential buckets leak is on the way.

Thanks,
-Andrea

Re: [PATCH] arm64: mm: add missing PTE_SPECIAL in pte_mkdevmap on arm64

[Catalin Marinas]

On Wed, Aug 07, 2019 at 10:09:29AM +0100, Will Deacon wrote:
> On Wed, Aug 07, 2019 at 12:58:51PM +0800, Jia He wrote:
> > diff --git a/arch/arm64/include/asm/pgtable.h 
> > b/arch/arm64/include/asm/pgtable.h
> > index 5fdcfe237338..e09760ece844 100644
> > --- a/arch/arm64/include/asm/pgtable.h
> > +++ b/arch/arm64/include/asm/pgtable.h
> > @@ -209,7 +209,7 @@ static inline pmd_t pmd_mkcont(pmd_t pmd)
> >  
> >  static inline pte_t pte_mkdevmap(pte_t pte)
> >  {
> > -   return set_pte_bit(pte, __pgprot(PTE_DEVMAP));
> > +   return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
> >  }
> >  
> >  static inline void set_pte(pte_t *ptep, pte_t pte)
> > @@ -396,7 +396,10 @@ static inline int pmd_protnone(pmd_t pmd)
> >  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> >  #define pmd_devmap(pmd)pte_devmap(pmd_pte(pmd))
> >  #endif
> > -#define pmd_mkdevmap(pmd)  pte_pmd(pte_mkdevmap(pmd_pte(pmd)))
> > +static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> > +{
> > +   return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
> > +}
> >  
> >  #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
> >  #define __phys_to_pmd_val(phys)__phys_to_pte_val(phys)
> 
> Acked-by: Will Deacon 
> 
> I think Catalin can take this as a fix, although the commit message should
> probably be trimmed down a bit to remove the two call traces etc.

I'll queue this for -rc4 and sort out the commit message. Thanks.

-- 
Catalin

RE: [PATCH v2 1/5] firmware: arm_scmi: Add discovery of SCMI v2.0 performance fastchannels

[Peng Fan]

> Subject: [PATCH v2 1/5] firmware: arm_scmi: Add discovery of SCMI v2.0
> performance fastchannels
> 
> SCMI v2.0 adds support for "FastChannel", a lightweight unidirectional
> channel that is dedicated to a single SCMI message type for controlling a
> specific platform resource. They do not use a message header as they are
> specialized for a single message.
> 
> Only PERFORMANCE_LIMITS_{SET,GET} and
> PERFORMANCE_LEVEL_{SET,GET} commands are supported over
> fastchannels. As they are optional, they need to be discovered by
> PERFORMANCE_DESCRIBE_FASTCHANNEL command.
> Further {LIMIT,LEVEL}_SET commands can have optional doorbell support.
> 
> Add support for discovery of these fastchannels.
> 
> Cc: Ionela Voinescu 
> Cc: Chris Redpath 
> Cc: Quentin Perret 
> Signed-off-by: Sudeep Holla 
> ---
>  drivers/firmware/arm_scmi/perf.c | 153
> ++-
>  1 file changed, 149 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/firmware/arm_scmi/perf.c
> b/drivers/firmware/arm_scmi/perf.c
> index 3c8ae7cc35de..6cce3e82e81e 100644
> --- a/drivers/firmware/arm_scmi/perf.c
> +++ b/drivers/firmware/arm_scmi/perf.c
> @@ -5,7 +5,9 @@
>   * Copyright (C) 2018 ARM Ltd.
>   */
> 
> +#include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -21,6 +23,7 @@ enum scmi_performance_protocol_cmd {
>   PERF_LEVEL_GET = 0x8,
>   PERF_NOTIFY_LIMITS = 0x9,
>   PERF_NOTIFY_LEVEL = 0xa,
> + PERF_DESCRIBE_FASTCHANNEL = 0xb,
>  };
> 
>  struct scmi_opp {
> @@ -44,6 +47,7 @@ struct scmi_msg_resp_perf_domain_attributes {
>  #define SUPPORTS_SET_PERF_LVL(x) ((x) & BIT(30))
>  #define SUPPORTS_PERF_LIMIT_NOTIFY(x)((x) & BIT(29))
>  #define SUPPORTS_PERF_LEVEL_NOTIFY(x)((x) & BIT(28))
> +#define SUPPORTS_PERF_FASTCHANNELS(x)((x) & BIT(27))
>   __le32 rate_limit_us;
>   __le32 sustained_freq_khz;
>   __le32 sustained_perf_level;
> @@ -87,17 +91,56 @@ struct scmi_msg_resp_perf_describe_levels {
>   } opp[0];
>  };
> 
> +struct scmi_perf_get_fc_info {
> + __le32 domain;
> + __le32 message_id;
> +};
> +
> +struct scmi_msg_resp_perf_desc_fc {
> + __le32 attr;
> +#define SUPPORTS_DOORBELL(x) ((x) & BIT(0))
> +#define DOORBELL_REG_WIDTH(x)FIELD_GET(GENMASK(2, 1), (x))
> + __le32 rate_limit;
> + __le32 chan_addr_low;
> + __le32 chan_addr_high;
> + __le32 chan_size;
> + __le32 db_addr_low;
> + __le32 db_addr_high;
> + __le32 db_set_lmask;
> + __le32 db_set_hmask;
> + __le32 db_preserve_lmask;
> + __le32 db_preserve_hmask;
> +};
> +
> +struct scmi_fc_db_info {
> + int width;
> + u64 set;
> + u64 mask;
> + void __iomem *addr;
> +};
> +
> +struct scmi_fc_info {
> + void __iomem *level_set_addr;
> + void __iomem *limit_set_addr;
> + void __iomem *level_get_addr;
> + void __iomem *limit_get_addr;
> + struct scmi_fc_db_info *level_set_db;
> + struct scmi_fc_db_info *limit_set_db;
> +};
> +
>  struct perf_dom_info {
>   bool set_limits;
>   bool set_perf;
>   bool perf_limit_notify;
>   bool perf_level_notify;
> + bool perf_fastchannels;
>   u32 opp_count;
>   u32 sustained_freq_khz;
>   u32 sustained_perf_level;
>   u32 mult_factor;
>   char name[SCMI_MAX_STR_SIZE];
>   struct scmi_opp opp[MAX_OPPS];
> + struct scmi_fc_info *fc_info;
>  };
> 
>  struct scmi_perf_info {
> @@ -162,6 +205,7 @@ scmi_perf_domain_attributes_get(const struct
> scmi_handle *handle, u32 domain,
>   dom_info->set_perf = SUPPORTS_SET_PERF_LVL(flags);
>   dom_info->perf_limit_notify =
> SUPPORTS_PERF_LIMIT_NOTIFY(flags);
>   dom_info->perf_level_notify =
> SUPPORTS_PERF_LEVEL_NOTIFY(flags);
> + dom_info->perf_fastchannels =
> SUPPORTS_PERF_FASTCHANNELS(flags);
>   dom_info->sustained_freq_khz =
>   le32_to_cpu(attr->sustained_freq_khz);
>   dom_info->sustained_perf_level =
> @@ -250,7 +294,7 @@ scmi_perf_describe_levels_get(const struct
> scmi_handle *handle, u32 domain,  }
> 
>  static int scmi_perf_limits_set(const struct scmi_handle *handle, u32
> domain,
> - u32 max_perf, u32 min_perf)
> +u32 max_perf, u32 min_perf)
>  {
>   int ret;
>   struct scmi_xfer *t;
> @@ -273,7 +317,7 @@ static int scmi_perf_limits_set(const struct
> scmi_handle *handle, u32 domain,  }
> 
>  static int scmi_perf_limits_get(const struct scmi_handle *handle, u32
> domain,
> - u32 *max_perf, u32 *min_perf)
> +u32 *max_perf, u32 *min_perf)
>  {
>   int ret;
>   struct scmi_xfer *t;
> @@ -299,7 +343,7 @@ static int scmi_perf_limits_get(const struct
> scmi_handle *handle, u32 domain,  }
> 
>  static int scmi_perf_level_set(const struct scmi_handle *handle, u32
> domain,
> -

Re: [PATCH -next] iwlwifi: dbg: work around clang bug by marking debug strings static

[Joe Perches]

On Tue, 2019-08-06 at 22:15 -0700, Nathan Chancellor wrote:
> Just for everyone else (since I commented on our issue tracker), this is
> now fixed in Linus's tree as of commit  1f6607250331 ("iwlwifi: dbg_ini:
> fix compile time assert build errors").

I think this change is incomplete and suggest you add this
to remove the use of another const char * format.

---
 drivers/net/wireless/intel/iwlwifi/fw/dbg.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/net/wireless/intel/iwlwifi/fw/dbg.c 
b/drivers/net/wireless/intel/iwlwifi/fw/dbg.c
index 4d81776f576d..6b15e2e8cd37 100644
--- a/drivers/net/wireless/intel/iwlwifi/fw/dbg.c
+++ b/drivers/net/wireless/intel/iwlwifi/fw/dbg.c
@@ -2593,20 +2593,20 @@ static void iwl_fw_dbg_update_regions(struct 
iwl_fw_runtime *fwrt,
 {
void *iter = (void *)tlv->region_config;
int i, size = le32_to_cpu(tlv->num_regions);
-   const char *err_st =
-   "WRT: ext=%d. Invalid region %s %d for apply point %d\n";
 
for (i = 0; i < size; i++) {
struct iwl_fw_ini_region_cfg *reg = iter, **active;
int id = le32_to_cpu(reg->region_id);
u32 type = le32_to_cpu(reg->region_type);
 
-   if (WARN(id >= ARRAY_SIZE(fwrt->dump.active_regs), err_st, ext,
-"id", id, pnt))
+   if (WARN(id >= ARRAY_SIZE(fwrt->dump.active_regs),
+"WRT: ext=%d. Invalid region id %d for apply point 
%d\n",
+ext, id, pnt))
break;
 
-   if (WARN(type == 0 || type >= IWL_FW_INI_REGION_NUM, err_st,
-ext, "type", type, pnt))
+   if (WARN(type == 0 || type >= IWL_FW_INI_REGION_NUM,
+"WRT: ext=%d. Invalid region type %d for apply point 
%d\n",
+ext, type, pnt))
break;
 
active = >dump.active_regs[id];

Re: [PATCH V2 08/10] x86/resctrl: Support pseudo-lock regions spanning resources

[Borislav Petkov]

On Tue, Jul 30, 2019 at 10:29:42AM -0700, Reinette Chatre wrote:
> Currently cache pseudo-locked regions only consider one cache level but
> cache pseudo-locked regions may span multiple cache levels.
> 
> In preparation for support of pseudo-locked regions spanning multiple
> cache levels pseudo-lock 'portions' are introduced. A 'portion' of a
> pseudo-locked region is the portion of a pseudo-locked region that
> belongs to a specific resource. Each pseudo-locked portion is identified
> with the resource (for example, L2 or L3 cache), the domain (the
> specific cache instance), and the capacity bitmask that specifies which
> region of the cache is used by the pseudo-locked region.
> 
> In support of pseudo-locked regions spanning multiple cache levels a
> pseudo-locked region could have multiple 'portions' but in this
> introduction only single portions are allowed.
> 
> Signed-off-by: Reinette Chatre 
> ---
>  arch/x86/kernel/cpu/resctrl/ctrlmondata.c |  26 +++-
>  arch/x86/kernel/cpu/resctrl/internal.h|  32 ++--
>  arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 180 --
>  arch/x86/kernel/cpu/resctrl/rdtgroup.c|  44 --
>  4 files changed, 211 insertions(+), 71 deletions(-)

This patch kinda got pretty big and is hard to review. Can
you split it pls? The addition of pseudo_lock_portion and
pseudo_lock_single_portion_valid() look like a separate patch to me.

> diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c 
> b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
> index a0383ff80afe..a60fb38a4d20 100644
> --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
> +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
> @@ -207,7 +207,7 @@ int parse_cbm(struct rdt_parse_data *data, struct 
> rdt_resource *r,
>* hierarchy.
>*/
>   if (rdtgrp->mode == RDT_MODE_PSEUDO_LOCKSETUP &&
> - rdtgroup_pseudo_locked_in_hierarchy(d)) {
> + rdtgroup_pseudo_locked_in_hierarchy(rdtgrp, d)) {
>   rdt_last_cmd_puts("Pseudo-locked region in hierarchy\n");
>   return -EINVAL;
>   }
> @@ -282,6 +282,7 @@ static int parse_line(char *line, struct rdt_resource *r,
>   if (r->parse_ctrlval(, r, d))
>   return -EINVAL;
>   if (rdtgrp->mode ==  RDT_MODE_PSEUDO_LOCKSETUP) {
> + struct pseudo_lock_portion *p;
>   /*
>* In pseudo-locking setup mode and just
>* parsed a valid CBM that should be
> @@ -290,9 +291,15 @@ static int parse_line(char *line, struct rdt_resource *r,
>* the required initialization for single
>* region and return.
>*/
> - rdtgrp->plr->r = r;
> - rdtgrp->plr->d_id = d->id;
> - rdtgrp->plr->cbm = d->new_ctrl;
> + p = kzalloc(sizeof(*p), GFP_KERNEL);
> + if (!p) {
> + rdt_last_cmd_puts("Unable to allocate 
> memory for pseudo-lock portion\n");
> + return -ENOMEM;
> + }
> + p->r = r;
> + p->d_id = d->id;
> + p->cbm = d->new_ctrl;
> + list_add(>list, >plr->portions);
>   return 0;
>   }

Looking at the indentation level of this, it is basically begging to
become a separate, helper function...

>   goto next;
> @@ -410,8 +417,11 @@ ssize_t rdtgroup_schemata_write(struct kernfs_open_file 
> *of,
>   goto out;
>   }
>   ret = rdtgroup_parse_resource(resname, tok, rdtgrp);
> - if (ret)
> + if (ret) {
> + if (rdtgrp->mode == RDT_MODE_PSEUDO_LOCKSETUP)
> + pseudo_lock_region_clear(rdtgrp->plr);
>   goto out;
> + }
>   }
>  
>   for_each_alloc_enabled_rdt_resource(r) {
> @@ -459,6 +469,7 @@ static void show_doms(struct seq_file *s, struct 
> rdt_resource *r, int closid)
>  int rdtgroup_schemata_show(struct kernfs_open_file *of,
>  struct seq_file *s, void *v)
>  {
> + struct pseudo_lock_portion *p;
>   struct rdtgroup *rdtgrp;
>   struct rdt_resource *r;
>   int ret = 0;
> @@ -470,8 +481,9 @@ int rdtgroup_schemata_show(struct kernfs_open_file *of,
>   for_each_alloc_enabled_rdt_resource(r)
>   seq_printf(s, "%s:uninitialized\n", r->name);
>   } else if (rdtgrp->mode == RDT_MODE_PSEUDO_LOCKED) {
> - seq_printf(s, "%s:%d=%x\n", rdtgrp->plr->r->name,
> -

Re: [RFC PATCH] pciehp: use completion to wait irq_thread 'pciehp_ist'

[Lukas Wunner]

On Wed, Aug 07, 2019 at 04:28:32PM +0800, Xiongfeng Wang wrote:
> On 2019/8/6 15:24, Lukas Wunner wrote:
> > I'd suggest something like the below instead, could you give it a whirl
> > and see if it reliably fixes the issue for you?
> 
> I tested the below patch. It can fix the issue.

Thank you!  I'll submit it as a proper patch then.


> I am not sure whether the following sequence will be a problem.
> * pciehp_ist() is running, and 'ctrl->pending_events' is cleared
> * a request to disable the slot is submitted via sysfs.
>   'ctrl->pending_events' is set and the irq_thread 'pciehp_ist' is waken up.
>   But pciehp_ist() is running. So it doesn't take effect.
>   'ctrl->pending_events' is not cleared until next time pciehp_ist() is
>   waken up. So pciehp_sysfs_enable_slot() will wait until next
>   pciehp_ist() is waken up. I am not sure how 'irq_wake_thread()' will
>   effect the running irq_thread.

That's not a problem.  If irq_wake_thread() is called while pciehp_ist()
is running, the latter will automatically perform another iteration.
It's the same situation if an interrupt is received while pciehp_ist()
is running.

irq_wake_thread() sets the IRQTF_RUNTHREAD flag and irq_wait_for_interrupt()
checks that flag and causes irq_thread() to perform another invocation
of handler_fn(), which is pciehp_ist() in this case.

So pciehp basically treats a user request like an interrupt received from
the hardware.  It's meant to simplify the pciehp code.  But it's non-trivial
to understand because one needs to have an understanding of the genirq
code to appreciate the simplicity.

Let me know if this explanation wasn't clear enough and you have further
questions.


> How about making the process synchronous instead of waking up the
> irq_thread?

That's what we had before, but it has its own problems since it requires
locking and interaction between the IRQ thread and the sysfs entry points.

Thanks,

Lukas

[PATCH v3] ALSA: hiface: fix multiple memory leak bugs

[Wenwen Wang]

In hiface_pcm_init(), 'rt' is firstly allocated through kzalloc(). Later
on, hiface_pcm_init_urb() is invoked to initialize 'rt->out_urbs[i]'. In
hiface_pcm_init_urb(), 'rt->out_urbs[i].buffer' is allocated through
kzalloc().  However, if hiface_pcm_init_urb() fails, both 'rt' and
'rt->out_urbs[i].buffer' are not deallocated, leading to memory leak bugs.
Also, 'rt->out_urbs[i].buffer' is not deallocated if snd_pcm_new() fails.

To fix the above issues, free 'rt' and 'rt->out_urbs[i].buffer'.

Signed-off-by: Wenwen Wang 
---
 sound/usb/hiface/pcm.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/sound/usb/hiface/pcm.c b/sound/usb/hiface/pcm.c
index 14fc1e1..c406497 100644
--- a/sound/usb/hiface/pcm.c
+++ b/sound/usb/hiface/pcm.c
@@ -600,14 +600,13 @@ int hiface_pcm_init(struct hiface_chip *chip, u8 
extra_freq)
ret = hiface_pcm_init_urb(>out_urbs[i], chip, OUT_EP,
hiface_pcm_out_urb_handler);
if (ret < 0)
-   return ret;
+   goto error;
}
 
ret = snd_pcm_new(chip->card, "USB-SPDIF Audio", 0, 1, 0, );
if (ret < 0) {
-   kfree(rt);
dev_err(>dev->dev, "Cannot create pcm instance\n");
-   return ret;
+   goto error;
}
 
pcm->private_data = rt;
@@ -620,4 +619,10 @@ int hiface_pcm_init(struct hiface_chip *chip, u8 
extra_freq)
 
chip->pcm = rt;
return 0;
+
+error:
+   for (i = 0; i < PCM_N_URBS; i++)
+   kfree(rt->out_urbs[i].buffer);
+   kfree(rt);
+   return ret;
 }
-- 
2.7.4

Re: [PATCH 3/8] mtd: nand: create ONFI table parsing instance

[Miquel Raynal]

Hi Shiva,

shiva.linuxwo...@gmail.com wrote on Mon, 22 Jul 2019 07:56:16 +0200:

> From: Shivamurthy Shastri 

"Create one generic ONFI table parsing instance"

> 
> ONFI table parsing is common, as most of the variables are common
> between raw and SPI NAND. The parsing function is instantiated in
> onfi.c, which fills ONFI parameters into nand_memory_organization.

... into nand_memory_organization just as before.

> 
> Signed-off-by: Shivamurthy Shastri 
> ---
>  drivers/mtd/nand/onfi.c  | 32 
>  drivers/mtd/nand/raw/nand_onfi.c | 22 ++
>  include/linux/mtd/onfi.h |  2 ++
>  3 files changed, 36 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/mtd/nand/onfi.c b/drivers/mtd/nand/onfi.c
> index 7aaf36dfc5e0..e78700894aea 100644
> --- a/drivers/mtd/nand/onfi.c
> +++ b/drivers/mtd/nand/onfi.c
> @@ -87,3 +87,35 @@ void sanitize_string(u8 *s, size_t len)
>   strim(s);
>  }
>  EXPORT_SYMBOL_GPL(sanitize_string);
> +
> +/**
> + * fill_nand_memorg() - Parse ONFI table and fill memorg

  ^ parse_onfi_params() - Parse an ONFI table and fill a memory
  organization structure

> + * @memorg: NAND memorg to be filled

memory organization core structure to be filled

> + * @p: ONFI table to be parsed
> + *
> + */
> +void parse_onfi_params(struct nand_memory_organization *memorg,
> +struct nand_onfi_params *p)
> +{
> + memorg->pagesize = le32_to_cpu(p->byte_per_page);
> +
> + /*
> +  * pages_per_block and blocks_per_lun may not be a power-of-2 size
> +  * (don't ask me who thought of this...). MTD assumes that these
> +  * dimensions will be power-of-2, so just truncate the remaining area.
> +  */
> + memorg->pages_per_eraseblock =
> + 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
> +
> + memorg->oobsize = le16_to_cpu(p->spare_bytes_per_page);
> +
> + memorg->luns_per_target = p->lun_count;
> + memorg->planes_per_lun = 1 << p->interleaved_bits;
> +
> + /* See erasesize comment */
> + memorg->eraseblocks_per_lun =
> + 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
> + memorg->max_bad_eraseblocks_per_lun = le32_to_cpu(p->blocks_per_lun);
> + memorg->bits_per_cell = p->bits_per_cell;
> +}
> +EXPORT_SYMBOL_GPL(parse_onfi_params);
> diff --git a/drivers/mtd/nand/raw/nand_onfi.c 
> b/drivers/mtd/nand/raw/nand_onfi.c
> index 2e8edfa636ef..263796d3298c 100644
> --- a/drivers/mtd/nand/raw/nand_onfi.c
> +++ b/drivers/mtd/nand/raw/nand_onfi.c
> @@ -181,30 +181,12 @@ int nand_onfi_detect(struct nand_chip *chip)
>   goto free_onfi_param_page;
>   }
>  
> - memorg->pagesize = le32_to_cpu(p->byte_per_page);
> - mtd->writesize = memorg->pagesize;
> + parse_onfi_params(memorg, p);
>  
> - /*
> -  * pages_per_block and blocks_per_lun may not be a power-of-2 size
> -  * (don't ask me who thought of this...). MTD assumes that these
> -  * dimensions will be power-of-2, so just truncate the remaining area.
> -  */
> - memorg->pages_per_eraseblock =
> - 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
> + mtd->writesize = memorg->pagesize;
>   mtd->erasesize = memorg->pages_per_eraseblock * memorg->pagesize;
> -
> - memorg->oobsize = le16_to_cpu(p->spare_bytes_per_page);
>   mtd->oobsize = memorg->oobsize;
>  
> - memorg->luns_per_target = p->lun_count;
> - memorg->planes_per_lun = 1 << p->interleaved_bits;
> -
> - /* See erasesize comment */
> - memorg->eraseblocks_per_lun =
> - 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
> - memorg->max_bad_eraseblocks_per_lun = le32_to_cpu(p->blocks_per_lun);
> - memorg->bits_per_cell = p->bits_per_cell;
> -
>   if (le16_to_cpu(p->features) & ONFI_FEATURE_16_BIT_BUS)
>   chip->options |= NAND_BUSWIDTH_16;
>  
> diff --git a/include/linux/mtd/onfi.h b/include/linux/mtd/onfi.h
> index 2c8a05a02bb0..4cacf4e9db6d 100644
> --- a/include/linux/mtd/onfi.h
> +++ b/include/linux/mtd/onfi.h
> @@ -183,5 +183,7 @@ void nand_bit_wise_majority(const void **srcbufs,
>   void *dstbuf,
>   unsigned int bufsize);
>  void sanitize_string(u8 *s, size_t len);
> +void parse_onfi_params(struct nand_memory_organization *memorg,
> +struct nand_onfi_params *p);
>  
>  #endif /* __LINUX_MTD_ONFI_H */




Thanks,
Miquèl

Re: [PATCH] arm64: mm: add missing PTE_SPECIAL in pte_mkdevmap on arm64

[Will Deacon]

On Wed, Aug 07, 2019 at 12:58:51PM +0800, Jia He wrote:
> diff --git a/arch/arm64/include/asm/pgtable.h 
> b/arch/arm64/include/asm/pgtable.h
> index 5fdcfe237338..e09760ece844 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -209,7 +209,7 @@ static inline pmd_t pmd_mkcont(pmd_t pmd)
>  
>  static inline pte_t pte_mkdevmap(pte_t pte)
>  {
> - return set_pte_bit(pte, __pgprot(PTE_DEVMAP));
> + return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
>  }
>  
>  static inline void set_pte(pte_t *ptep, pte_t pte)
> @@ -396,7 +396,10 @@ static inline int pmd_protnone(pmd_t pmd)
>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
>  #define pmd_devmap(pmd)  pte_devmap(pmd_pte(pmd))
>  #endif
> -#define pmd_mkdevmap(pmd)pte_pmd(pte_mkdevmap(pmd_pte(pmd)))
> +static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> +{
> + return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
> +}
>  
>  #define __pmd_to_phys(pmd)   __pte_to_phys(pmd_pte(pmd))
>  #define __phys_to_pmd_val(phys)  __phys_to_pte_val(phys)

Acked-by: Will Deacon 

I think Catalin can take this as a fix, although the commit message should
probably be trimmed down a bit to remove the two call traces etc.

Will

Re: [PATCH v2 1/2] mmc: sdhci: Add PLL Enable support to internal clock setup

[Adrian Hunter]

On 26/07/19 5:07 AM, Michael K. Johnson wrote:
> The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable
> setup as part of the internal clock setup as described in 3.2.1 Internal
> Clock Setup Sequence of SD Host Controller Simplified Specification
> Version 4.20.  This changes the timeouts to the new specification of
> 150ms for each step and is documented as safe for "prior versions which
> do not support PLL Enable."
> 
> Signed-off-by: Ben Chuang 
> Co-developed-by: Michael K Johnson 
> Signed-off-by: Michael K Johnson 
> 
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 59acf8e3331e..14957578bf2e 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1636,8 +1636,8 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
>   clk |= SDHCI_CLOCK_INT_EN;
>   sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
>  
> - /* Wait max 20 ms */
> - timeout = ktime_add_ms(ktime_get(), 20);
> + /* Wait max 150 ms */
> + timeout = ktime_add_ms(ktime_get(), 150);
>   while (1) {
>   bool timedout = ktime_after(ktime_get(), timeout);
>  
> @@ -1650,7 +1650,28 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
>   sdhci_dumpregs(host);
>   return;
>   }
> - udelay(10);
> + usleep_range(10,15);

There is still one place that calls ->set_clock() under spinlock, so that
needs to stay udelay(10) for now.

> + }
> +

PLL Enable is only valid from v4.1 i.e.

if (host->version >= SDHCI_SPEC_410 && host->v4_mode)


> + clk |= SDHCI_CLOCK_PLL_EN;
> + clk &= ~SDHCI_CLOCK_INT_STABLE;
> + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +
> + /* Wait max 150 ms */
> + timeout = ktime_add_ms(ktime_get(), 150);
> + while (1) {
> + bool timedout = ktime_after(ktime_get(), timeout);
> +
> + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> + if (clk & SDHCI_CLOCK_INT_STABLE)
> + break;
> + if (timedout) {
> + pr_err("%s: PLL clock never stabilised.\n",
> +mmc_hostname(host->mmc));
> + sdhci_dumpregs(host);
> + return;
> + }
> + usleep_range(10,15);
>   }
>  
>   clk |= SDHCI_CLOCK_CARD_EN;
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index 199712e7adbb..72601a4d2e95 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -114,6 +114,7 @@
>  #define  SDHCI_DIV_HI_MASK   0x300
>  #define  SDHCI_PROG_CLOCK_MODE   0x0020
>  #define  SDHCI_CLOCK_CARD_EN 0x0004
> +#define  SDHCI_CLOCK_PLL_EN  0x0008
>  #define  SDHCI_CLOCK_INT_STABLE  0x0002
>  #define  SDHCI_CLOCK_INT_EN  0x0001
>  
> 

Re: [PATCH] cpufreq: mediatek-cpufreq: Add compatible for MT8516

[Viresh Kumar]

On 06-08-19, 11:50, Fabien Parent wrote:
> Add the compatible for MT8516 in order to take advantage of the
> MediaTek CPUFreq driver for Mediatek's MT8516 SoC.
> 
> Signed-off-by: Fabien Parent 
> ---
>  drivers/cpufreq/mediatek-cpufreq.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/cpufreq/mediatek-cpufreq.c 
> b/drivers/cpufreq/mediatek-cpufreq.c
> index f14f3a85f2f7..10bc06f5dd45 100644
> --- a/drivers/cpufreq/mediatek-cpufreq.c
> +++ b/drivers/cpufreq/mediatek-cpufreq.c
> @@ -535,6 +535,7 @@ static const struct of_device_id mtk_cpufreq_machines[] 
> __initconst = {
>   { .compatible = "mediatek,mt817x", },
>   { .compatible = "mediatek,mt8173", },
>   { .compatible = "mediatek,mt8176", },
> + { .compatible = "mediatek,mt8516", },
>  
>   { }
>  };

Applied. Thanks.

-- 
viresh

Re: [PATCH 2/8] mtd: nand: move support functions for ONFI to nand/onfi.c

[Miquel Raynal]

Hi shiva.linuxwo...@gmail.com,

shiva.linuxwo...@gmail.com wrote on Mon, 22 Jul 2019 07:56:15 +0200:

> From: Shivamurthy Shastri 

"mtd: nand: move ONFI specific helpers to nand/onfi.c"?

> 
> These functions are support functions for enabling ONFI standard and
> common between raw NAND and SPI NAND.

"
These are ONFI specific helpers that might be shared between raw and
SPI NAND logics, move them to a generic place.

While at it, add kernel doc on the function parameters.
"

> 
> Signed-off-by: Shivamurthy Shastri 
> ---
>  drivers/mtd/nand/Makefile|  2 +-
>  drivers/mtd/nand/onfi.c  | 89 
>  drivers/mtd/nand/raw/nand_base.c | 18 ---
>  drivers/mtd/nand/raw/nand_onfi.c | 43 ---
>  4 files changed, 90 insertions(+), 62 deletions(-)
>  create mode 100644 drivers/mtd/nand/onfi.c
> 
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index 7ecd80c0a66e..221945c223c3 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -1,6 +1,6 @@
>  # SPDX-License-Identifier: GPL-2.0
>  
> -nandcore-objs := core.o bbt.o
> +nandcore-objs := core.o bbt.o onfi.o
>  obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
>  
>  obj-y+= onenand/
> diff --git a/drivers/mtd/nand/onfi.c b/drivers/mtd/nand/onfi.c
> new file mode 100644
> index ..7aaf36dfc5e0
> --- /dev/null
> +++ b/drivers/mtd/nand/onfi.c
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#define pr_fmt(fmt) "nand-onfi: " fmt
> +
> +#include 
> +#include 
> +
> +/**
> + * onfi_crc16() - Check CRC of ONFI table

There is no check in this function.

 Derive the CRC of an ONFI table

> + * @crc: base CRC
> + * @p: buffer pointing to ONFI table
^ the
> + * @len: length of ONFI table
 ^the
> + *
> + * Return: CRC of the ONFI table
  @return: the CRC of the given ONFI table

> + */
> +u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
> +{
> + int i;
> +
> + while (len--) {
> + crc ^= *p++ << 8;
> + for (i = 0; i < 8; i++)
> + crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
> + }
> +
> + return crc;
> +}
> +EXPORT_SYMBOL_GPL(onfi_crc16);
> +
> +/**
> + * nand_bit_wise_majority() - Recover data with bit-wise majority
> + * @srcbufs: buffer pointing to ONFI table
> + * @nsrcbufs: length of ONFI table
 ^the
> + * @dstbuf: valid ONFI table to be returned
> + * @bufsize: length og valid ONFI table
   of the valid...
> + *

Extra line

> + */
> +void nand_bit_wise_majority(const void **srcbufs,
> + unsigned int nsrcbufs,
> + void *dstbuf,
> + unsigned int bufsize)
> +{
> + int i, j, k;
> +
> + for (i = 0; i < bufsize; i++) {
> + u8 val = 0;
> +
> + for (j = 0; j < 8; j++) {
> + unsigned int cnt = 0;
> +
> + for (k = 0; k < nsrcbufs; k++) {
> + const u8 *srcbuf = srcbufs[k];
> +
> + if (srcbuf[i] & BIT(j))
> + cnt++; 
> + }
> +
> + if (cnt > nsrcbufs / 2)
> + val |= BIT(j);
> + }
> +
> + ((u8 *)dstbuf)[i] = val;
> + }
> +}
> +EXPORT_SYMBOL_GPL(nand_bit_wise_majority);
> +
> +/**
> + * sanitize_string() - Sanitize ONFI strings so we can safely print them

It is used by JEDEC logic so this should be moved elsewhere and not
refer to any ONFI naming.

> + * @s: string to be sanitized
> + * @len: length of the string
> + *
> + */
> +void sanitize_string(u8 *s, size_t len)
> +{
> + ssize_t i;
> +
> + /* Null terminate */
> + s[len - 1] = 0;
> +
> + /* Remove non printable chars */
> + for (i = 0; i < len - 1; i++) {
> + if (s[i] < ' ' || s[i] > 127)
> + s[i] = '?';
> + }
> +
> + /* Remove trailing spaces */
> + strim(s);
> +}
> +EXPORT_SYMBOL_GPL(sanitize_string);
> diff --git a/drivers/mtd/nand/raw/nand_base.c 
> b/drivers/mtd/nand/raw/nand_base.c
> index 6ecd1c496ce3..c198829bcd79 100644
> --- a/drivers/mtd/nand/raw/nand_base.c
> +++ b/drivers/mtd/nand/raw/nand_base.c
> @@ -4375,24 +4375,6 @@ static void nand_set_defaults(struct nand_chip *chip)
>   chip->buf_align = 1;
>  }
>  
> -/* Sanitize ONFI strings so we can safely print them */
> -void sanitize_string(uint8_t *s, size_t len)
> -{
> - ssize_t i;
> -
> - /* Null terminate */
> - s[len - 1] = 0;
> -
> - /* Remove non printable chars */
> - for (i = 0; i < len - 1; i++) {
> - if (s[i] < ' ' || s[i] > 127)
> - s[i] = '?';
> - }
> -
> - /* Remove trailing spaces */
> - strim(s);
> -}
> -
>  /*
>   * nand_id_has_period - Check if an ID string has a given 

Re: [PATCH v2 03/24] EDAC, ghes: Remove pvt->detail_location string

[Robert Richter]

On 02.08.19 18:04:46, James Morse wrote:
> On 24/06/2019 16:08, Robert Richter wrote:
> > The detail_location[] string in struct ghes_edac_pvt is complete
> > useless and data is just copied around. Put everything into
> > e->other_detail from the beginning.

I am updating the description here to clarify it is only the internal
buffer that is removed. The other_detail[] string still provides a
decoded information of the apei error record.

> > 
> > Signed-off-by: Robert Richter 
> > ---
> 
> 
> > diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c
> > index d095d98d6a8d..049de73c3bad 100644
> > --- a/drivers/edac/ghes_edac.c
> > +++ b/drivers/edac/ghes_edac.c
> > @@ -21,8 +21,7 @@ struct ghes_edac_pvt {
> > struct mem_ctl_info *mci;
> >  
> > /* Buffers for the error handling routine */
> > -   char detail_location[240];
> > -   char other_detail[160];
> > +   char other_detail[400];
> > char msg[80];
> >  };
> >  
> > @@ -224,13 +223,14 @@ void ghes_edac_report_mem_error(int sev, struct 
> > cper_sec_mem_err *mem_err)
> > e->error_count = 1;
> > e->grain = 1;
> > strcpy(e->label, "unknown label");
> > -   e->msg = pvt->msg;
> > -   e->other_detail = pvt->other_detail;
> > e->top_layer = -1;
> > e->mid_layer = -1;
> > e->low_layer = -1;
> > -   *pvt->other_detail = '\0';
> > +   e->msg = pvt->msg;
> > +   e->other_detail = pvt->other_detail;
> > +
> > *pvt->msg = '\0';
> > +   *pvt->other_detail = '\0';

There are not code changes here, just a reordering for better
comparization with its counterpart in edac_mc.c. However, I am
removing this hunk here.

> >  
> > switch (sev) {
> > case GHES_SEV_CORRECTED:
> > @@ -361,6 +361,8 @@ void ghes_edac_report_mem_error(int sev, struct 
> > cper_sec_mem_err *mem_err)
> >  
> > /* All other fields are mapped on e->other_detail */
> > p = pvt->other_detail;
> > +   p += snprintf(p, sizeof(pvt->other_detail),
> > +   "APEI location: %s ", e->location);
> > if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
> > u64 status = mem_err->error_status;
> >  
> > @@ -443,12 +445,10 @@ void ghes_edac_report_mem_error(int sev, struct 
> > cper_sec_mem_err *mem_err)
> > grain_bits = fls_long(e->grain - 1);
> >  
> > /* Generate the trace event */
> > -   snprintf(pvt->detail_location, sizeof(pvt->detail_location),
> > -"APEI location: %s %s", e->location, e->other_detail);
> > trace_mc_event(type, e->msg, e->label, e->error_count,
> >mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
> >(e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
> > -  grain_bits, e->syndrome, pvt->detail_location);
> > +  grain_bits, e->syndrome, e->other_detail);
> >  
> > edac_raw_mc_handle_error(type, mci, e);
> > spin_unlock_irqrestore(_lock, flags);
> 
> After a game of spot-the-difference: you added a newline.
> Reviewed-by: James Morse 
> 
> Previously here:
> https://lore.kernel.org/linux-edac/7017c91e-8923-c8d2-26ca-875328ab8...@arm.com/
> 
> Please pick up tags when posting a new version.

Let me know what you mean with this, I would like to ease review for
you. I tried to describe changes for v2 as detailed as possible.

Thank you.

-Robert

Re: [RFC PATCH v3 00/16] Core scheduling v3

[Dario Faggioli]

Hello everyone,

This is Dario, from SUSE. I'm also interesting in core-scheduling, and
using it in virtualization use cases.

Just for context, I'm working in virt since a few years, mostly on Xen,
but I've done Linux stuff before, and I am getting back at it.

For now, I've been looking at the core-scheduling code, and run some
benchmarks myself.

On Fri, 2019-08-02 at 11:37 -0400, Julien Desfossez wrote:
> We tested both Aaron's and Tim's patches and here are our results.
> 
> Test setup:
> - 2 1-thread sysbench, one running the cpu benchmark, the other one
> the
>   mem benchmark
> - both started at the same time
> - both are pinned on the same core (2 hardware threads)
> - 10 30-seconds runs
> - test script: https://paste.debian.net/plainh/834cf45c
> - only showing the CPU events/sec (higher is better)
> - tested 4 tag configurations:
>   - no tag
>   - sysbench mem untagged, sysbench cpu tagged
>   - sysbench mem tagged, sysbench cpu untagged
>   - both tagged with a different tag
> - "Alone" is the sysbench CPU running alone on the core, no tag
> - "nosmt" is both sysbench pinned on the same hardware thread, no tag
> - "Tim's full patchset + sched" is an experiment with Tim's patchset
>   combined with Aaron's "hack patch" to get rid of the remaining deep
>   idle cases
> - In all test cases, both tasks can run simultaneously (which was not
>   the case without those patches), but the standard deviation is a
>   pretty good indicator of the fairness/consistency.
> 
This, and of course the numbers below too, is very interesting.

So, here comes my question: I've done a benchmarking campaign (yes,
I'll post numbers soon) using this branch:

https://github.com/digitalocean/linux-coresched.git  
vpillai/coresched-v3-v5.1.5-test
https://github.com/digitalocean/linux-coresched/tree/vpillai/coresched-v3-v5.1.5-test

Last commit:
7feb1007f274 "Fix stalling of untagged processes competing with tagged
processes"

Since I see that, in this thread, there are various patches being
proposed and discussed... should I rerun my benchmarks with them
applied? If yes, which ones? And is there, by any chance, one (or maybe
more than one) updated git branch(es)?

Thanks in advance and Regards
-- 
Dario Faggioli, Ph.D
http://about.me/dario.faggioli
Virtualization Software Engineer
SUSE Labs, SUSE https://www.suse.com/
---
<> (Raistlin Majere)



signature.asc
Description: This is a digitally signed message part

[PATCH 1/2] habanalabs: fix endianness handling for packets from user

[Oded Gabbay]

From: Ben Segal 

Packets that arrive from the user and need to be parsed by the driver are
assumed to be in LE format.

This patch fix all the places where the code handles these packets and use
the correct endianness macros to handle them, as the driver handles the
packets in CPU format (LE or BE depending on the arch).

Signed-off-by: Ben Segal 
Reviewed-by: Oded Gabbay 
Signed-off-by: Oded Gabbay 
---
 drivers/misc/habanalabs/goya/goya.c   | 32 +++
 .../habanalabs/include/goya/goya_packets.h| 13 
 2 files changed, 32 insertions(+), 13 deletions(-)

diff --git a/drivers/misc/habanalabs/goya/goya.c 
b/drivers/misc/habanalabs/goya/goya.c
index a0e181714891..e8b1142910e0 100644
--- a/drivers/misc/habanalabs/goya/goya.c
+++ b/drivers/misc/habanalabs/goya/goya.c
@@ -3428,12 +3428,13 @@ static int goya_validate_cb(struct hl_device *hdev,
while (cb_parsed_length < parser->user_cb_size) {
enum packet_id pkt_id;
u16 pkt_size;
-   void *user_pkt;
+   struct goya_packet *user_pkt;
 
-   user_pkt = (void *) (uintptr_t)
+   user_pkt = (struct goya_packet *) (uintptr_t)
(parser->user_cb->kernel_address + cb_parsed_length);
 
-   pkt_id = (enum packet_id) (((*(u64 *) user_pkt) &
+   pkt_id = (enum packet_id) (
+   (le64_to_cpu(user_pkt->header) &
PACKET_HEADER_PACKET_ID_MASK) >>
PACKET_HEADER_PACKET_ID_SHIFT);
 
@@ -3453,7 +3454,8 @@ static int goya_validate_cb(struct hl_device *hdev,
 * need to validate here as well because patch_cb() is
 * not called in MMU path while this function is called
 */
-   rc = goya_validate_wreg32(hdev, parser, user_pkt);
+   rc = goya_validate_wreg32(hdev,
+   parser, (struct packet_wreg32 *) user_pkt);
break;
 
case PACKET_WREG_BULK:
@@ -3481,10 +3483,10 @@ static int goya_validate_cb(struct hl_device *hdev,
case PACKET_LIN_DMA:
if (is_mmu)
rc = goya_validate_dma_pkt_mmu(hdev, parser,
-   user_pkt);
+   (struct packet_lin_dma *) user_pkt);
else
rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
-   user_pkt);
+   (struct packet_lin_dma *) user_pkt);
break;
 
case PACKET_MSG_LONG:
@@ -3657,15 +3659,16 @@ static int goya_patch_cb(struct hl_device *hdev,
enum packet_id pkt_id;
u16 pkt_size;
u32 new_pkt_size = 0;
-   void *user_pkt, *kernel_pkt;
+   struct goya_packet *user_pkt, *kernel_pkt;
 
-   user_pkt = (void *) (uintptr_t)
+   user_pkt = (struct goya_packet *) (uintptr_t)
(parser->user_cb->kernel_address + cb_parsed_length);
-   kernel_pkt = (void *) (uintptr_t)
+   kernel_pkt = (struct goya_packet *) (uintptr_t)
(parser->patched_cb->kernel_address +
cb_patched_cur_length);
 
-   pkt_id = (enum packet_id) (((*(u64 *) user_pkt) &
+   pkt_id = (enum packet_id) (
+   (le64_to_cpu(user_pkt->header) &
PACKET_HEADER_PACKET_ID_MASK) >>
PACKET_HEADER_PACKET_ID_SHIFT);
 
@@ -3680,15 +3683,18 @@ static int goya_patch_cb(struct hl_device *hdev,
 
switch (pkt_id) {
case PACKET_LIN_DMA:
-   rc = goya_patch_dma_packet(hdev, parser, user_pkt,
-   kernel_pkt, _pkt_size);
+   rc = goya_patch_dma_packet(hdev, parser,
+   (struct packet_lin_dma *) user_pkt,
+   (struct packet_lin_dma *) kernel_pkt,
+   _pkt_size);
cb_patched_cur_length += new_pkt_size;
break;
 
case PACKET_WREG_32:
memcpy(kernel_pkt, user_pkt, pkt_size);
cb_patched_cur_length += pkt_size;
-   rc = goya_validate_wreg32(hdev, parser, kernel_pkt);
+   rc = goya_validate_wreg32(hdev, parser,
+   (struct packet_wreg32 *) kernel_pkt);
break;
 
case PACKET_WREG_BULK:
diff --git 

[PATCH 2/2] habanalabs: fix completion queue handling when host is BE

[Oded Gabbay]

From: Ben Segal 

This patch fix the CQ irq handler to work in hosts with BE architecture.
It adds the correct endian-swapping macros around the relevant memory
accesses.

Signed-off-by: Ben Segal 
Reviewed-by: Oded Gabbay 
Signed-off-by: Oded Gabbay 
---
 drivers/misc/habanalabs/irq.c | 27 +--
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/misc/habanalabs/irq.c b/drivers/misc/habanalabs/irq.c
index ea9f72ff456c..199791b57caf 100644
--- a/drivers/misc/habanalabs/irq.c
+++ b/drivers/misc/habanalabs/irq.c
@@ -80,8 +80,7 @@ irqreturn_t hl_irq_handler_cq(int irq, void *arg)
struct hl_cs_job *job;
bool shadow_index_valid;
u16 shadow_index;
-   u32 *cq_entry;
-   u32 *cq_base;
+   struct hl_cq_entry *cq_entry, *cq_base;
 
if (hdev->disabled) {
dev_dbg(hdev->dev,
@@ -90,29 +89,29 @@ irqreturn_t hl_irq_handler_cq(int irq, void *arg)
return IRQ_HANDLED;
}
 
-   cq_base = (u32 *) (uintptr_t) cq->kernel_address;
+   cq_base = (struct hl_cq_entry *) (uintptr_t) cq->kernel_address;
 
while (1) {
-   bool entry_ready = ((cq_base[cq->ci] & CQ_ENTRY_READY_MASK)
+   bool entry_ready = ((le32_to_cpu(cq_base[cq->ci].data) &
+   CQ_ENTRY_READY_MASK)
>> CQ_ENTRY_READY_SHIFT);
 
if (!entry_ready)
break;
 
-   cq_entry = (u32 *) _base[cq->ci];
+   cq_entry = (struct hl_cq_entry *) _base[cq->ci];
 
-   /*
-* Make sure we read CQ entry contents after we've
+   /* Make sure we read CQ entry contents after we've
 * checked the ownership bit.
 */
dma_rmb();
 
-   shadow_index_valid =
-   ((*cq_entry & CQ_ENTRY_SHADOW_INDEX_VALID_MASK)
+   shadow_index_valid = ((le32_to_cpu(cq_entry->data) &
+   CQ_ENTRY_SHADOW_INDEX_VALID_MASK)
>> CQ_ENTRY_SHADOW_INDEX_VALID_SHIFT);
 
-   shadow_index = (u16)
-   ((*cq_entry & CQ_ENTRY_SHADOW_INDEX_MASK)
+   shadow_index = (u16) ((le32_to_cpu(cq_entry->data) &
+   CQ_ENTRY_SHADOW_INDEX_MASK)
>> CQ_ENTRY_SHADOW_INDEX_SHIFT);
 
queue = >kernel_queues[cq->hw_queue_id];
@@ -122,8 +121,7 @@ irqreturn_t hl_irq_handler_cq(int irq, void *arg)
queue_work(hdev->cq_wq, >finish_work);
}
 
-   /*
-* Update ci of the context's queue. There is no
+   /* Update ci of the context's queue. There is no
 * need to protect it with spinlock because this update is
 * done only inside IRQ and there is a different IRQ per
 * queue
@@ -131,7 +129,8 @@ irqreturn_t hl_irq_handler_cq(int irq, void *arg)
queue->ci = hl_queue_inc_ptr(queue->ci);
 
/* Clear CQ entry ready bit */
-   cq_base[cq->ci] &= ~CQ_ENTRY_READY_MASK;
+   cq_entry->data = cpu_to_le32(le32_to_cpu(cq_entry->data) &
+   ~CQ_ENTRY_READY_MASK);
 
cq->ci = hl_cq_inc_ptr(cq->ci);
 
-- 
2.17.1

Re: [PATCH v2 1/1] ixgbe: sync the first fragment unconditionally

[Firo Yang]

The 08/07/2019 15:56, Jacob Wen wrote:
> I think the description is not correct. Consider using something like below.
Thank you for comments. 

> 
> In Xen environment, due to memory fragmentation ixgbe may allocate a 'DMA'
> buffer with pages that are not physically contiguous.
Actually, I didn't look into the reason why ixgbe got a DMA buffer which
was mapped to Xen-swiotlb area.

But I don't think this issue relates to phsical memory contiguity because, in
our case, one ixgbe_rx_buffer only associates at most one page.

If you take a look at the related code, you will find there are several reasons
for mapping a DMA buffer to Xen-swiotlb area:
static dma_addr_t xen_swiotlb_map_page(struct device *dev, struct page *page,
 */
if (dma_capable(dev, dev_addr, size) &&
!range_straddles_page_boundary(phys, size) &&
!xen_arch_need_swiotlb(dev, phys, dev_addr) &&
swiotlb_force != SWIOTLB_FORCE)
goto done;

// Firo
> 
> A NIC doesn't support directly write such buffer. So xen-swiotlb would use
> the pages, which are physically contiguous, from the swiotlb buffer for the
> NIC.
> 
> The unmap operation is used to copy the swiotlb buffer to the pages that are
> allocated by ixgbe.
> 
> On 8/7/19 10:49 AM, Firo Yang wrote:
> > In Xen environment, if Xen-swiotlb is enabled, ixgbe driver
> > could possibly allocate a page, DMA memory buffer, for the first
> > fragment which is not suitable for Xen-swiotlb to do DMA operations.
> > Xen-swiotlb have to internally allocate another page for doing DMA
> > operations. It requires syncing between those two pages. However,
> > since commit f3213d932173 ("ixgbe: Update driver to make use of DMA
> > attributes in Rx path"), the unmap operation is performed with
> > DMA_ATTR_SKIP_CPU_SYNC. As a result, the sync is not performed.
> > 
> > To fix this problem, always sync before possibly performing a page
> > unmap operation.
> > 
> > Fixes: f3213d932173 ("ixgbe: Update driver to make use of DMA
> > attributes in Rx path")
> > Reviewed-by: Alexander Duyck 
> > Signed-off-by: Firo Yang 
> > ---
> > 
> > Changes from v1:
> >   * Imporved the patch description.
> >   * Added Reviewed-by: and Fixes: as suggested by Alexander Duyck
> > 
> >   drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 16 +---
> >   1 file changed, 9 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c 
> > b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
> > index cbaf712d6529..200de9838096 100644
> > --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
> > +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
> > @@ -1825,13 +1825,7 @@ static void ixgbe_pull_tail(struct ixgbe_ring 
> > *rx_ring,
> >   static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
> > struct sk_buff *skb)
> >   {
> > -   /* if the page was released unmap it, else just sync our portion */
> > -   if (unlikely(IXGBE_CB(skb)->page_released)) {
> > -   dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
> > -ixgbe_rx_pg_size(rx_ring),
> > -DMA_FROM_DEVICE,
> > -IXGBE_RX_DMA_ATTR);
> > -   } else if (ring_uses_build_skb(rx_ring)) {
> > +   if (ring_uses_build_skb(rx_ring)) {
> > unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK;
> > dma_sync_single_range_for_cpu(rx_ring->dev,
> > @@ -1848,6 +1842,14 @@ static void ixgbe_dma_sync_frag(struct ixgbe_ring 
> > *rx_ring,
> >   skb_frag_size(frag),
> >   DMA_FROM_DEVICE);
> > }
> > +
> > +   /* If the page was released, just unmap it. */
> > +   if (unlikely(IXGBE_CB(skb)->page_released)) {
> > +   dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
> > +ixgbe_rx_pg_size(rx_ring),
> > +DMA_FROM_DEVICE,
> > +IXGBE_RX_DMA_ATTR);
> > +   }
> >   }
> >   /**
> 

[PATCH v6 3/3] drm/mediatek: add mipi_tx driver for mt8183

[Jitao Shi]

This patch add mt8183 mipi_tx driver.
And also support other chips that use the same binding and driver.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/Makefile |   1 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c|   2 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|   1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 150 ++
 4 files changed, 154 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index 2c8de1f5a5ee..8067a4be8311 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,6 +13,7 @@ mediatek-drm-y := mtk_disp_color.o \
  mtk_dsi.o \
  mtk_mipi_tx.o \
  mtk_mt8173_mipi_tx.o \
+ mtk_mt8183_mipi_tx.o \
  mtk_dpi.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index 77b9a185e970..e4d34484ecc8 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -175,6 +175,8 @@ static const struct of_device_id mtk_mipi_tx_match[] = {
  .data = _mipitx_data },
{ .compatible = "mediatek,mt8173-mipi-tx",
  .data = _mipitx_data },
+   { .compatible = "mediatek,mt8183-mipi-tx",
+ .data = _mipitx_data },
{ },
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 4f905313564f..413f35d86219 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -44,5 +44,6 @@ unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
 
 extern const struct mtk_mipitx_data mt2701_mipitx_data;
 extern const struct mtk_mipitx_data mt8173_mipitx_data;
+extern const struct mtk_mipitx_data mt8183_mipitx_data;
 
 #endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
new file mode 100644
index ..db13ebdbe262
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: jitao.shi 
+ */
+
+#include "mtk_mipi_tx.h"
+
+#define MIPITX_LANE_CON0x000c
+#define RG_DSI_CPHY_T1DRV_EN   BIT(0)
+#define RG_DSI_ANA_CK_SEL  BIT(1)
+#define RG_DSI_PHY_CK_SEL  BIT(2)
+#define RG_DSI_CPHY_EN BIT(3)
+#define RG_DSI_PHYCK_INV_ENBIT(4)
+#define RG_DSI_PWR04_ENBIT(5)
+#define RG_DSI_BG_LPF_EN   BIT(6)
+#define RG_DSI_BG_CORE_EN  BIT(7)
+#define RG_DSI_PAD_TIEL_SELBIT(8)
+
+#define MIPITX_PLL_PWR 0x0028
+#define MIPITX_PLL_CON00x002c
+#define MIPITX_PLL_CON10x0030
+#define MIPITX_PLL_CON20x0034
+#define MIPITX_PLL_CON30x0038
+#define MIPITX_PLL_CON40x003c
+#define RG_DSI_PLL_IBIAS   (3 << 10)
+
+#define MIPITX_D2_SW_CTL_EN0x0144
+#define MIPITX_D0_SW_CTL_EN0x0244
+#define MIPITX_CK_CKMODE_EN0x0328
+#define DSI_CK_CKMODE_EN   BIT(0)
+#define MIPITX_CK_SW_CTL_EN0x0344
+#define MIPITX_D1_SW_CTL_EN0x0444
+#define MIPITX_D3_SW_CTL_EN0x0544
+#define DSI_SW_CTL_EN  BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON  BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN  BIT(1)
+
+#define RG_DSI_PLL_EN  BIT(4)
+#define RG_DSI_PLL_POSDIV  (0x7 << 8)
+
+static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
+{
+   struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+   unsigned int txdiv, txdiv0;
+   u64 pcw;
+
+   dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate);
+
+   if (mipi_tx->data_rate >= 20) {
+   txdiv = 1;
+   txdiv0 = 0;
+   } else if (mipi_tx->data_rate >= 10) {
+   txdiv = 2;
+   txdiv0 = 1;
+   } else if (mipi_tx->data_rate >= 5) {
+   txdiv = 4;
+   txdiv0 = 2;
+   } else if (mipi_tx->data_rate > 25000) {
+   txdiv = 8;
+   txdiv0 = 3;
+   } else if (mipi_tx->data_rate >= 12500) {
+   txdiv = 16;
+   txdiv0 = 4;
+   } else {
+   return -EINVAL;
+   }
+
+   mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
+
+   mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+   mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+   udelay(1);
+   mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
+   pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 2600);
+   writel(pcw, mipi_tx->regs + MIPITX_PLL_CON0);
+   mtk_mipi_tx_update_bits(mipi_tx, MIPITX_PLL_CON1, 

[PATCH v3 3/3] clocksource/drivers/ostm: Use unique device name instead of ostm

[Geert Uytterhoeven]

Currently all OSTM devices are called "ostm", also in kernel messages.

As there can be multiple instances in an SoC, this can confuse the user.
Hence construct a unique name from the DT node name, like is done for
platform devices.

On RSK+RZA1, the boot log changes like:

-clocksource: ostm: mask: 0x max_cycles: 0x, max_idle_ns: 
57352151442 ns
+clocksource: ostm fcfec000.timer: mask: 0x max_cycles: 0x, 
max_idle_ns: 57352151442 ns
 sched_clock: 32 bits at 33MHz, resolution 30ns, wraps every 64440619504ns
-ostm: used for clocksource
-ostm: used for clock events
+ostm fcfec000.timer: used for clocksource
+ostm fcfec400.timer: used for clock events

Signed-off-by: Geert Uytterhoeven 
---
v3:
  - Make the name format similar to the one used for platform devices,
  - Use kasprintf() instead of buffer size guessing,
  - Use a real example from rskrza1.

v2 (by Jacopo):
  - Use np->full_name.
---
 drivers/clocksource/renesas-ostm.c | 45 --
 1 file changed, 30 insertions(+), 15 deletions(-)

diff --git a/drivers/clocksource/renesas-ostm.c 
b/drivers/clocksource/renesas-ostm.c
index 1e22e54d7b0df40d..659e3ec7b86714e3 100644
--- a/drivers/clocksource/renesas-ostm.c
+++ b/drivers/clocksource/renesas-ostm.c
@@ -25,6 +25,7 @@
  */
 
 struct ostm_device {
+   const char *name;
void __iomem *base;
unsigned long ticks_per_jiffy;
struct clock_event_device ced;
@@ -79,9 +80,8 @@ static int __init ostm_init_clksrc(struct ostm_device *ostm, 
unsigned long rate)
writeb(CTL_FREERUN, ostm->base + OSTM_CTL);
writeb(TS, ostm->base + OSTM_TS);
 
-   return clocksource_mmio_init(ostm->base + OSTM_CNT,
-   "ostm", rate,
-   300, 32, clocksource_mmio_readl_up);
+   return clocksource_mmio_init(ostm->base + OSTM_CNT, ostm->name, rate,
+300, 32, clocksource_mmio_readl_up);
 }
 
 static u64 notrace ostm_read_sched_clock(void)
@@ -161,15 +161,14 @@ static int __init ostm_init_clkevt(struct ostm_device 
*ostm, unsigned int irq,
struct clock_event_device *ced = >ced;
int ret = -ENXIO;
 
-   ret = request_irq(irq, ostm_timer_interrupt,
- IRQF_TIMER | IRQF_IRQPOLL,
- "ostm", ostm);
+   ret = request_irq(irq, ostm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
+ ostm->name, ostm);
if (ret) {
-   pr_err("ostm: failed to request irq\n");
+   pr_err("%s: Failed to request irq\n", ostm->name);
return ret;
}
 
-   ced->name = "ostm";
+   ced->name = ostm->name;
ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
ced->set_state_shutdown = ostm_shutdown;
ced->set_state_periodic = ostm_set_periodic;
@@ -187,6 +186,7 @@ static int __init ostm_init(struct device_node *np)
 {
struct clk *ostm_clk = NULL;
struct ostm_device *ostm;
+   struct resource res;
unsigned long rate;
unsigned int irq;
int ret;
@@ -195,22 +195,35 @@ static int __init ostm_init(struct device_node *np)
if (!ostm)
return -ENOMEM;
 
-   ostm->base = of_iomap(np, 0);
-   if (!ostm->base) {
+   ret = of_address_to_resource(np, 0, );
+   if (ret) {
+   pr_err("ostm: Failed to obtain I/O memory\n");
+   goto err_free;
+   }
+
+   ostm->name = kasprintf(GFP_KERNEL, "ostm %llx.%s",
+  (unsigned long long)res.start, np->name);
+   if (!ostm->name) {
ret = -ENOMEM;
goto err_free;
}
 
+   ostm->base = ioremap(res.start, resource_size());
+   if (!ostm->base) {
+   ret = -ENOMEM;
+   goto err_free_name;
+   }
+
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
-   pr_err("ostm: Failed to get irq\n");
+   pr_err("%s: Failed to get irq\n", ostm->name);
ret = -EINVAL;
goto err_unmap;
}
 
ostm_clk = of_clk_get(np, 0);
if (IS_ERR(ostm_clk)) {
-   pr_err("ostm: Failed to get clock\n");
+   pr_err("%s: Failed to get clock\n", ostm->name);
ostm_clk = NULL;
ret = PTR_ERR(ostm_clk);
goto err_unmap;
@@ -218,7 +231,7 @@ static int __init ostm_init(struct device_node *np)
 
ret = clk_prepare_enable(ostm_clk);
if (ret) {
-   pr_err("ostm: Failed to enable clock\n");
+   pr_err("%s: Failed to enable clock\n", ostm->name);
goto err_clk_put;
}
 
@@ -235,13 +248,13 @@ static int __init ostm_init(struct device_node *np)
goto err_clk_disable;
 
ostm_init_sched_clock(ostm, rate);
-   pr_info("ostm: used for 

[PATCH v3 2/3] clocksource/drivers/renesas-ostm: Fix probe error path

[Geert Uytterhoeven]

Fix various issues in the error path of ostm_init():
  1. Drop error message printing on of_iomap() failure, as the memory
 allocation core already takes of that,
  2. Handle irq_of_parse_and_map() failures correctly: it returns
 unsigned int, hence make irq unsigned int, and zero is an error,
  3. Propagate/return appropriate error codes instead of -EFAULT.
  4. Add a missing clk_put(),
  5. Split the single cleanup block in separate phases, to avoid
 clk_put() calling WARN() when passed an error pointer.

Signed-off-by: Geert Uytterhoeven 
---
v3:
  - New.
---
 drivers/clocksource/renesas-ostm.c | 54 --
 1 file changed, 29 insertions(+), 25 deletions(-)

diff --git a/drivers/clocksource/renesas-ostm.c 
b/drivers/clocksource/renesas-ostm.c
index 37c39b901bb12b38..1e22e54d7b0df40d 100644
--- a/drivers/clocksource/renesas-ostm.c
+++ b/drivers/clocksource/renesas-ostm.c
@@ -155,7 +155,7 @@ static irqreturn_t ostm_timer_interrupt(int irq, void 
*dev_id)
return IRQ_HANDLED;
 }
 
-static int __init ostm_init_clkevt(struct ostm_device *ostm, int irq,
+static int __init ostm_init_clkevt(struct ostm_device *ostm, unsigned int irq,
unsigned long rate)
 {
struct clock_event_device *ced = >ced;
@@ -185,11 +185,11 @@ static int __init ostm_init_clkevt(struct ostm_device 
*ostm, int irq,
 
 static int __init ostm_init(struct device_node *np)
 {
-   struct ostm_device *ostm;
-   int ret = -EFAULT;
struct clk *ostm_clk = NULL;
-   int irq;
+   struct ostm_device *ostm;
unsigned long rate;
+   unsigned int irq;
+   int ret;
 
ostm = kzalloc(sizeof(*ostm), GFP_KERNEL);
if (!ostm)
@@ -197,27 +197,29 @@ static int __init ostm_init(struct device_node *np)
 
ostm->base = of_iomap(np, 0);
if (!ostm->base) {
-   pr_err("ostm: failed to remap I/O memory\n");
-   goto err;
+   ret = -ENOMEM;
+   goto err_free;
}
 
irq = irq_of_parse_and_map(np, 0);
-   if (irq < 0) {
+   if (!irq) {
pr_err("ostm: Failed to get irq\n");
-   goto err;
+   ret = -EINVAL;
+   goto err_unmap;
}
 
ostm_clk = of_clk_get(np, 0);
if (IS_ERR(ostm_clk)) {
pr_err("ostm: Failed to get clock\n");
ostm_clk = NULL;
-   goto err;
+   ret = PTR_ERR(ostm_clk);
+   goto err_unmap;
}
 
ret = clk_prepare_enable(ostm_clk);
if (ret) {
pr_err("ostm: Failed to enable clock\n");
-   goto err;
+   goto err_clk_put;
}
 
rate = clk_get_rate(ostm_clk);
@@ -229,28 +231,30 @@ static int __init ostm_init(struct device_node *np)
 */
if (!system_clock) {
ret = ostm_init_clksrc(ostm, rate);
+   if (ret)
+   goto err_clk_disable;
 
-   if (!ret) {
-   ostm_init_sched_clock(ostm, rate);
-   pr_info("ostm: used for clocksource\n");
-   }
-
+   ostm_init_sched_clock(ostm, rate);
+   pr_info("ostm: used for clocksource\n");
} else {
ret = ostm_init_clkevt(ostm, irq, rate);
+   if (ret)
+   goto err_clk_disable;
 
-   if (!ret)
-   pr_info("ostm: used for clock events\n");
-   }
-
-err:
-   if (ret) {
-   clk_disable_unprepare(ostm_clk);
-   iounmap(ostm->base);
-   kfree(ostm);
-   return ret;
+   pr_info("ostm: used for clock events\n");
}
 
return 0;
+
+err_clk_disable:
+   clk_disable_unprepare(ostm_clk);
+err_clk_put:
+   clk_put(ostm_clk);
+err_unmap:
+   iounmap(ostm->base);
+err_free:
+   kfree(ostm);
+   return ret;
 }
 
 TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init);
-- 
2.17.1

[PATCH v3 1/3] clocksource/drivers/renesas-ostm: Use DIV_ROUND_CLOSEST() helper

[Geert Uytterhoeven]

Use the DIV_ROUND_CLOSEST() helper instead of open-coding the same
operation.

Signed-off-by: Geert Uytterhoeven 
---
v3:
  - New.
---
 drivers/clocksource/renesas-ostm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/renesas-ostm.c 
b/drivers/clocksource/renesas-ostm.c
index 61d5f3b539ce23df..37c39b901bb12b38 100644
--- a/drivers/clocksource/renesas-ostm.c
+++ b/drivers/clocksource/renesas-ostm.c
@@ -221,7 +221,7 @@ static int __init ostm_init(struct device_node *np)
}
 
rate = clk_get_rate(ostm_clk);
-   ostm->ticks_per_jiffy = (rate + HZ / 2) / HZ;
+   ostm->ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
 
/*
 * First probed device will be used as system clocksource. Any
-- 
2.17.1

[PATCH v3 0/3] clocksource/drivers/ostm: Miscellaneous improvements

[Geert Uytterhoeven]

Hi all,

This patch series contains various improvements for the Renesas OSTM
timer driver, as used on the RZ/A1 and RZ/A2 SoCs.

The last patch is v3 of a patch that was sent before to a limited
audience:
  - 
https://lore.kernel.org/linux-renesas-soc/1507727130-17641-1-git-send-email-jacopo+rene...@jmondi.org/
  - 
https://lore.kernel.org/linux-renesas-soc/1507725113-18070-1-git-send-email-geert+rene...@glider.be/

Thanks!

Geert Uytterhoeven (3):
  clocksource/drivers/renesas-ostm: Use DIV_ROUND_CLOSEST() helper
  clocksource/drivers/renesas-ostm: Fix probe error path
  clocksource/drivers/ostm: Use unique device name instead of ostm

 drivers/clocksource/renesas-ostm.c | 95 ++
 1 file changed, 57 insertions(+), 38 deletions(-)

-- 
2.17.1

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCHv2] mm/migrate: clean up useless code in migrate_vma_collect_pmd()

[Pingfan Liu]

Clean up useless 'pfn' variable.

Signed-off-by: Pingfan Liu 
Cc: "Jérôme Glisse" 
Cc: Andrew Morton 
Cc: Mel Gorman 
Cc: Jan Kara 
Cc: "Kirill A. Shutemov" 
Cc: Michal Hocko 
Cc: Mike Kravetz 
Cc: Andrea Arcangeli 
Cc: Matthew Wilcox 
To: linux...@kvack.org
Cc: linux-kernel@vger.kernel.org
---
 mm/migrate.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/mm/migrate.c b/mm/migrate.c
index 8992741..d483a55 100644
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -2225,17 +2225,15 @@ static int migrate_vma_collect_pmd(pmd_t *pmdp,
pte_t pte;
 
pte = *ptep;
-   pfn = pte_pfn(pte);
 
if (pte_none(pte)) {
mpfn = MIGRATE_PFN_MIGRATE;
migrate->cpages++;
-   pfn = 0;
goto next;
}
 
if (!pte_present(pte)) {
-   mpfn = pfn = 0;
+   mpfn = 0;
 
/*
 * Only care about unaddressable device page special
@@ -2252,10 +2250,10 @@ static int migrate_vma_collect_pmd(pmd_t *pmdp,
if (is_write_device_private_entry(entry))
mpfn |= MIGRATE_PFN_WRITE;
} else {
+   pfn = pte_pfn(pte);
if (is_zero_pfn(pfn)) {
mpfn = MIGRATE_PFN_MIGRATE;
migrate->cpages++;
-   pfn = 0;
goto next;
}
page = vm_normal_page(migrate->vma, addr, pte);
@@ -2265,10 +2263,9 @@ static int migrate_vma_collect_pmd(pmd_t *pmdp,
 
/* FIXME support THP */
if (!page || !page->mapping || PageTransCompound(page)) {
-   mpfn = pfn = 0;
+   mpfn = 0;
goto next;
}
-   pfn = page_to_pfn(page);
 
/*
 * By getting a reference on the page we pin it and that blocks
-- 
2.7.5

linux-next: Tree for Aug 7

[Stephen Rothwell]

Hi all,

Changes since 20190806:

The arm64 tree introduced a patch that stopped the powerpc ppc64_defconfig
build from completing so I reverted that commit.

The mips tree gained a conflict against Linus' tree.

The crypto tree still had its build failure for which I applied a patch.

The drm-misc tree gained a conflict and a sematic conflct against the
amdgpu tree.

The integrity tree lost its build failure.

The akpm-current tree gained a conflict against the arm64 tree and a
build failure for which I reverted a commit.

The akpm tree lost a patch that turned up elsewhere.

Non-merge commits (relative to Linus' tree): 4586
 4952 files changed, 265168 insertions(+), 120665 deletions(-)



I have created today's linux-next tree at
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
(patches at http://www.kernel.org/pub/linux/kernel/next/ ).  If you
are tracking the linux-next tree using git, you should not use "git pull"
to do so as that will try to merge the new linux-next release with the
old one.  You should use "git fetch" and checkout or reset to the new
master.

You can see which trees have been included by looking in the Next/Trees
file in the source.  There are also quilt-import.log and merge.log
files in the Next directory.  Between each merge, the tree was built
with a ppc64_defconfig for powerpc, an allmodconfig for x86_64, a
multi_v7_defconfig for arm and a native build of tools/perf. After
the final fixups (if any), I do an x86_64 modules_install followed by
builds for x86_64 allnoconfig, powerpc allnoconfig (32 and 64 bit),
ppc44x_defconfig, allyesconfig and pseries_le_defconfig and i386, sparc
and sparc64 defconfig. And finally, a simple boot test of the powerpc
pseries_le_defconfig kernel in qemu (with and without kvm enabled).

Below is a summary of the state of the merge.

I am currently merging 304 trees (counting Linus' and 74 trees of bug
fix patches pending for the current merge release).

Stats about the size of the tree over time can be seen at
http://neuling.org/linux-next-size.html .

Status of my local build tests will be at
http://kisskb.ellerman.id.au/linux-next .  If maintainers want to give
advice about cross compilers/configs that work, we are always open to add
more builds.

Thanks to Randy Dunlap for doing many randconfig builds.  And to Paul
Gortmaker for triage and bug fixes.

-- 
Cheers,
Stephen Rothwell

$ git checkout master
$ git reset --hard stable
Merging origin/master (76d7961ff4ee Merge tag 'mips_fixes_5.3_1' of 
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux)
Merging fixes/master (609488bc979f Linux 5.3-rc2)
Merging kbuild-current/fixes (8bf63e8da5e5 kbuild: revive single target %.ko)
Merging arc-current/for-curr (e86d94fdda8e ARC: unwind: Mark expected switch 
fall-throughs)
Merging arm-current/fixes (c5d0e49e8d8f ARM: 8867/1: vdso: pass --be8 to linker 
if necessary)
Merging arm-soc-fixes/arm/fixes (7bd9d465140a Merge tag 'imx-fixes-5.3' of 
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes)
Merging arm64-fixes/for-next/fixes (d8bb6718c4db arm64: Make debug exception 
handlers visible from RCU)
Merging m68k-current/for-linus (f28a1f16135c m68k: Don't select 
ARCH_HAS_DMA_PREP_COHERENT for nommu or coldfire)
Merging powerpc-fixes/fixes (d7e23b887f67 powerpc/kasan: fix early boot failure 
on PPC32)
Merging s390-fixes/fixes (24350fdadbde s390: put _stext and _etext into .text 
section)
Merging sparc/master (038029c03e21 sparc: remove unneeded uapi/asm/statfs.h)
Merging fscrypt-current/for-stable (ae64f9bd1d36 Linux 4.15-rc2)
Merging net/master (feac1d680233 Merge branch 'sja1105-fixes')
Merging bpf/master (f1fc7249dddc selftests/bpf: tests for jmp to 1st insn)
Merging ipsec/master (22d6552f827e xfrm interface: fix management of phydev)
Merging netfilter/master (589b474a4b7c netfilter: nf_flow_table: fix offload 
for flows that are subject to xfrm)
Merging ipvs/master (58e8b37069ff Merge branch 'net-phy-dp83867-add-some-fixes')
Merging wireless-drivers/master (1f6607250331 iwlwifi: dbg_ini: fix compile 
time assert build errors)
Merging mac80211/master (d8a1de3d5bb8 isdn: hfcsusb: Fix mISDN driver crash 
caused by transfer buffer on the stack)
Merging rdma-fixes/for-rc (e21a712a9685 Linux 5.3-rc3)
Merging sound-current/for-linus (c1c6c877b0c7 ALSA: hda - Don't override global 
PCM hw info flag)
Merging sound-asoc-fixes/for-linus (3b97d1599f04 Merge branch 'asoc-5.3' into 
asoc-linus)
Merging regmap-fixes/for-linus (609488bc979f Linux 5.3-rc2)
Merging regulator-fixes/for-linus (0151f77cffe3 Merge branch 'regulator-5.3' 
into regulator-linus)
Merging spi-fixes/for-linus (6a2c4358f940 Merge branch 'spi-5.3' into spi-linus)
Merging pci-current/for-linus (5f9e832c1370 Linus 5.3-rc1)
Merging driver-core.current/driver-core-linus (cc798c83898e kernfs: fix memleak 
in kernel_ops_readdir())
Merging tty.current/tty-linus (81eaadcae81b kgdboc: 

[PATCH] net: fix semicolon.cocci warnings

[kbuild test robot]

From: kbuild test robot 

drivers/target/iscsi/cxgbit/cxgbit_target.c:1451:47-48: Unneeded semicolon


 Remove unneeded semicolon.

Generated by: scripts/coccinelle/misc/semicolon.cocci

Fixes: d7840976e391 ("net: Use skb accessors in network drivers")
CC: Matthew Wilcox (Oracle) 
Signed-off-by: kbuild test robot 
---

tree:   
https://kernel.googlesource.com/pub/scm/linux/kernel/git/next/linux-next.git 
master
head:   958eb4327c1761c609bde8e9f7c04e9d1c6fbb96
commit: d7840976e3915669382c62ddd1700960f348328e [1656/4974] net: Use skb 
accessors in network drivers

 cxgbit_target.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/target/iscsi/cxgbit/cxgbit_target.c
+++ b/drivers/target/iscsi/cxgbit/cxgbit_target.c
@@ -1448,7 +1448,7 @@ cxgbit_lro_skb_merge(struct cxgbit_sock
hpdu_cb->frags++;
hpdu_cb->hfrag_idx = hfrag_idx;
 
-   len = skb_frag_size(>frags[hfrag_idx]);;
+   len = skb_frag_size(>frags[hfrag_idx]);
hskb->len += len;
hskb->data_len += len;
hskb->truesize += len;

Re: [PATCH 1/8] mtd: nand: move ONFI related functions to onfi.h

[Miquel Raynal]

Hi Shiva,

shiva.linuxwo...@gmail.com wrote on Mon, 22 Jul 2019 07:56:14 +0200:

> From: Shivamurthy Shastri 
> 
> These functions will be used by both raw NAND and SPI NAND, which
> supports ONFI like standards.

This is not exactly what you do. Why not:

mtd: nand: export ONFI related functions to onfi.h

These functions can be used by all flavors of NAND chips (raw, SPI)
which may all follow ONFI standards. Export the related functions in
the onfi.h generic file.

> 
> Signed-off-by: Shivamurthy Shastri 
> ---
>  drivers/mtd/nand/raw/internals.h | 1 -
>  include/linux/mtd/onfi.h | 9 +
>  2 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/raw/internals.h 
> b/drivers/mtd/nand/raw/internals.h
> index cba6fe7dd8c4..ed323087d884 100644
> --- a/drivers/mtd/nand/raw/internals.h
> +++ b/drivers/mtd/nand/raw/internals.h
> @@ -140,7 +140,6 @@ void nand_legacy_adjust_cmdfunc(struct nand_chip *chip);
>  int nand_legacy_check_hooks(struct nand_chip *chip);
>  
>  /* ONFI functions */
> -u16 onfi_crc16(u16 crc, u8 const *p, size_t len);
>  int nand_onfi_detect(struct nand_chip *chip);
>  
>  /* JEDEC functions */
> diff --git a/include/linux/mtd/onfi.h b/include/linux/mtd/onfi.h
> index 339ac798568e..2c8a05a02bb0 100644
> --- a/include/linux/mtd/onfi.h
> +++ b/include/linux/mtd/onfi.h
> @@ -10,6 +10,7 @@
>  #ifndef __LINUX_MTD_ONFI_H
>  #define __LINUX_MTD_ONFI_H
>  
> +#include 

This should be removed, or at least not added at this moment.

>  #include 
>  
>  /* ONFI version bits */
> @@ -175,4 +176,12 @@ struct onfi_params {
>   u8 vendor[88];
>  };
>  
> +/* ONFI functions */
> +u16 onfi_crc16(u16 crc, u8 const *p, size_t len);
> +void nand_bit_wise_majority(const void **srcbufs,
> + unsigned int nsrcbufs,
> + void *dstbuf,
> + unsigned int bufsize);

Don't export this function while you don't use it from elsewhere.

> +void sanitize_string(u8 *s, size_t len);

This one is used by jedec code and has no onfi-related logic, so you
may want to export it (only when you will use it) in another header
like linux/mtd/nand.h

> +
>  #endif /* __LINUX_MTD_ONFI_H */

Thanks,
Miquèl

Re: [RFC PATCH] pciehp: use completion to wait irq_thread 'pciehp_ist'

[Xiongfeng Wang]

Hi, Lukas

On 2019/8/6 15:24, Lukas Wunner wrote:
> On Thu, Jul 04, 2019 at 03:50:38PM +0800, Xiongfeng Wang wrote:
>> When I use the following command to power on a slot which has been
>> powered off already.
>> echo 1 > /sys/bus/pci/slots/22/power
>> It prints the following error:
>> -bash: echo: write error: No such device
>> But the slot is actually powered on and the devices is probed.
>>
>> In function 'pciehp_sysfs_enable_slot()', we use 'wait_event()' to wait
>> until 'ctrl->pending_events' is cleared in 'pciehp_ist()'. But in some
>> situation, when 'pciehp_ist()' is woken up on a nearby CPU after
>> 'pciehp_request' is called, 'ctrl->pending_events' is cleared before we
>> go into sleep state. 'wait_event()' will check the condition before
>> going into sleep. So we return immediately and '-ENODEV' is return.
>>
>> This patch use struct completion to wait until irq_thread 'pciehp_ist'
>> is completed.
> 
> Thank you, good catch.
> 
> Unfortunately your patch still allows the following race AFAICS:
> 
> * pciehp_ist() is running (e.g. due to a hotplug operation)
> * a request to disable or enable the slot is submitted via sysfs,
>   the completion is reinitialized
> * pciehp_ist() finishes, signals completion
> * the sysfs request returns to user space prematurely
> * pciehp_ist() is run, handles the sysfs request, signals completion again
> 
> I'd suggest something like the below instead, could you give it a whirl
> and see if it reliably fixes the issue for you?

I tested the below patch. It can fix the issue.

I am not sure whether the following sequence will be a problem.
* pciehp_ist() is running, and 'ctrl->pending_events' is cleared
* a request to disable the slot is submitted via sysfs. 'ctrl->pending_events'
  is set and the irq_thread 'pciehp_ist' is waken up. But pciehp_ist() is 
running.
  So it doesn't take effect. 'ctrl->pending_events' is not cleared until next 
time
  pciehp_ist() is waken up. So pciehp_sysfs_enable_slot() will wait until next
  pciehp_ist() is waken up. I am not sure how 'irq_wake_thread()' will effect
  the running irq_thread.

How about making the process synchronous instead of waking up the irq_thread ?


Thanks,
Xiongfeng.

> 
> -- >8 --
> 
> Subject: [PATCH] PCI: pciehp: Avoid returning prematurely from sysfs requests
> 
> A sysfs request to enable or disable a PCIe hotplug slot should not
> return before it has been carried out.  That is sought to be achieved
> by waiting until the controller's "pending_events" have been cleared.
> 
> However the IRQ thread pciehp_ist() clears the "pending_events" before
> it acts on them.  If pciehp_sysfs_enable_slot() / _disable_slot() happen
> to check the "pending_events" after they have been cleared but while
> pciehp_ist() is still running, the functions may return prematurely
> with an incorrect return value.
> 
> Fix by introducing an "ist_running" flag which must be false before a
> sysfs request is allowed to return.
> 
> Fixes: 32a8cef274fe ("PCI: pciehp: Enable/disable exclusively from IRQ 
> thread")
> Link: 
> https://lore.kernel.org/linux-pci/1562226638-54134-1-git-send-email-wangxiongfe...@huawei.com
> Reported-by: Xiongfeng Wang 
> Signed-off-by: Lukas Wunner 
> Cc: sta...@vger.kernel.org # v4.19+
> ---
>  drivers/pci/hotplug/pciehp.h  | 2 ++
>  drivers/pci/hotplug/pciehp_ctrl.c | 6 --
>  drivers/pci/hotplug/pciehp_hpc.c  | 2 ++
>  3 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h
> index 8c51a04b8083..e316bde45c7b 100644
> --- a/drivers/pci/hotplug/pciehp.h
> +++ b/drivers/pci/hotplug/pciehp.h
> @@ -72,6 +72,7 @@ extern int pciehp_poll_time;
>   * @reset_lock: prevents access to the Data Link Layer Link Active bit in the
>   *   Link Status register and to the Presence Detect State bit in the Slot
>   *   Status register during a slot reset which may cause them to flap
> + * @ist_running: flag to keep user request waiting while IRQ thread is 
> running
>   * @request_result: result of last user request submitted to the IRQ thread
>   * @requester: wait queue to wake up on completion of user request,
>   *   used for synchronous slot enable/disable request via sysfs
> @@ -101,6 +102,7 @@ struct controller {
>  
>   struct hotplug_slot hotplug_slot;   /* hotplug core interface */
>   struct rw_semaphore reset_lock;
> + unsigned int ist_running;
>   int request_result;
>   wait_queue_head_t requester;
>  };
> diff --git a/drivers/pci/hotplug/pciehp_ctrl.c 
> b/drivers/pci/hotplug/pciehp_ctrl.c
> index 631ced0ab28a..1ce9ce335291 100644
> --- a/drivers/pci/hotplug/pciehp_ctrl.c
> +++ b/drivers/pci/hotplug/pciehp_ctrl.c
> @@ -368,7 +368,8 @@ int pciehp_sysfs_enable_slot(struct hotplug_slot 
> *hotplug_slot)
>   ctrl->request_result = -ENODEV;
>   pciehp_request(ctrl, PCI_EXP_SLTSTA_PDC);
>   wait_event(ctrl->requester,
> -

[PATCH v3 03/21] ARM: dts: imx7-colibri: prepare module device tree for FlexCAN

[Philippe Schenker]

Prepare FlexCAN use on SODIMM 55/63 178/188. Those SODIMM pins are
compatible for CAN bus use with several modules from the Colibri
family.
Add Better drivestrength and also add flexcan2.

Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx7-colibri.dtsi | 35 -
 1 file changed, 30 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi 
b/arch/arm/boot/dts/imx7-colibri.dtsi
index f7c9ce5bed47..52046085ce6f 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -117,6 +117,18 @@
fsl,magic-packet;
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_flexcan1>;
+   status = "disabled";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_flexcan2>;
+   status = "disabled";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_gpmi_nand>;
@@ -330,12 +342,11 @@
 
  {
pinctrl-names = "default";
-   pinctrl-0 = <_gpio1 _gpio2 _gpio3 
_gpio4>;
+   pinctrl-0 = <_gpio1 _gpio2 _gpio3 _gpio4
+_gpio7>;
 
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
-   MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 
55 */
-   MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x74 /* SODIMM 
63 */
MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16   0x14 /* SODIMM 
77 */
MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 
89 */
MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 
91 */
@@ -416,6 +427,13 @@
>;
};
 
+   pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */
+   fsl,pins = <
+   MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 
55 */
+   MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 
63 */
+   >;
+   };
+
pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
fsl,pins = <
MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
@@ -459,10 +477,17 @@
>;
};
 
+   pinctrl_flexcan1: flexcan1-grp {
+   fsl,pins = <
+   MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX   0x79 /* SODIMM 
55 */
+   MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX   0x79 /* SODIMM 
63 */
+   >;
+   };
+
pinctrl_flexcan2: flexcan2-grp {
fsl,pins = <
-   MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX0x59
-   MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX0x59
+   MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX0x79 /* SODIMM 
188 */
+   MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX0x79 /* SODIMM 
178 */
>;
};
 
-- 
2.22.0

[PATCH v3 04/21] ARM: dts: imx7-colibri: Add sleep mode to ethernet

[Philippe Schenker]

Add sleep pinmux to the fec so it can properly sleep.

Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx7-colibri.dtsi | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi 
b/arch/arm/boot/dts/imx7-colibri.dtsi
index 52046085ce6f..a8d992f3e897 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -101,8 +101,9 @@
 };
 
  {
-   pinctrl-names = "default";
+   pinctrl-names = "default", "sleep";
pinctrl-0 = <_enet1>;
+   pinctrl-1 = <_enet1_sleep>;
clocks = < IMX7D_ENET_AXI_ROOT_CLK>,
< IMX7D_ENET_AXI_ROOT_CLK>,
< IMX7D_ENET1_TIME_ROOT_CLK>,
@@ -463,6 +464,22 @@
>;
};
 
+   pinctrl_enet1_sleep: enet1sleepgrp {
+   fsl,pins = <
+   MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4  0x0
+   MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0
+   MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0
+   MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0
+
+   MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0
+   MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0
+   MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0
+   MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0
+   MX7D_PAD_SD2_CD_B__GPIO5_IO90x0
+   MX7D_PAD_SD2_WP__GPIO5_IO10 0x0
+   >;
+   };
+
pinctrl_ecspi3_cs: ecspi3-cs-grp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__GPIO4_IO11   0x14
-- 
2.22.0

[PATCH v3 11/21] ARM: dts: imx6qdl-apalis: Add sleep state to can interfaces

[Philippe Schenker]

This patch prepares the devicetree for the new Ixora V1.2 where we are
able to turn off the supply of the can transceiver. This implies to use
a sleep state on transmission pins in order to prevent backfeeding.

Signed-off-by: Philippe Schenker 

---

Changes in v3: None
Changes in v2:
- Changed commit title to '...imx6qdl-apalis:...'

 arch/arm/boot/dts/imx6qdl-apalis.dtsi | 27 +--
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi 
b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 7c4ad541c3f5..59ed2e4a1fd1 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -148,14 +148,16 @@
 };
 
  {
-   pinctrl-names = "default";
-   pinctrl-0 = <_flexcan1>;
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <_flexcan1_default>;
+   pinctrl-1 = <_flexcan1_sleep>;
status = "disabled";
 };
 
  {
-   pinctrl-names = "default";
-   pinctrl-0 = <_flexcan2>;
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <_flexcan2_default>;
+   pinctrl-1 = <_flexcan2_sleep>;
status = "disabled";
 };
 
@@ -599,19 +601,32 @@
>;
};
 
-   pinctrl_flexcan1: flexcan1grp {
+   pinctrl_flexcan1_default: flexcan1defgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
>;
};
 
-   pinctrl_flexcan2: flexcan2grp {
+   pinctrl_flexcan1_sleep: flexcan1slpgrp {
+   fsl,pins = <
+   MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0
+   MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0
+   >;
+   };
+
+   pinctrl_flexcan2_default: flexcan2defgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
>;
};
+   pinctrl_flexcan2_sleep: flexcan2slpgrp {
+   fsl,pins = <
+   MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0
+   MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
+   >;
+   };
 
pinctrl_gpio_bl_on: gpioblon {
fsl,pins = <
-- 
2.22.0

[PATCH v3 12/21] ARM: dts: imx6-apalis: Add touchscreens used on Toradex eval boards

[Philippe Schenker]

This commit adds the touchscreens from Toradex so one can enable it.

Signed-off-by: Philippe Schenker 

---

Changes in v3:
- Fix commit title to "...imx6-apalis:..."

Changes in v2:
- Deleted touchrevolution downstream stuff
- Use generic node name
- Put a better comment in there

 arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts  | 31 +++
 arch/arm/boot/dts/imx6q-apalis-eval.dts   | 13 
 arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 13 
 arch/arm/boot/dts/imx6q-apalis-ixora.dts  | 13 
 4 files changed, 70 insertions(+)

diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts 
b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index 9a5d6c94cca4..763fb5e90bd3 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -168,6 +168,21 @@
  {
status = "okay";
 
+   /*
+* Touchscreen is using SODIMM 28/30, also used for PWM, PWM,
+* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+*/
+   touchscreen@4a {
+   compatible = "atmel,maxtouch";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pcap_1>;
+   reg = <0x4a>;
+   interrupt-parent = <>;
+   interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
+   reset-gpios = < 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
+   status = "disabled";
+   };
+
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
@@ -175,6 +190,22 @@
};
 };
 
+ {
+   pinctrl_pcap_1: pcap-1 {
+   fsl,pins = <
+   MX6QDL_PAD_GPIO_9__GPIO1_IO09   0x1b0b0 /* SODIMM 28 */
+   MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */
+   >;
+   };
+
+   pinctrl_mxt_ts: mxt-ts {
+   fsl,pins = <
+   MX6QDL_PAD_EIM_CS1__GPIO2_IO24  0x130b0 /* SODIMM 107 */
+   MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */
+   >;
+   };
+};
+
 _di0_disp0 {
remote-endpoint = <_display_in>;
 };
diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts 
b/arch/arm/boot/dts/imx6q-apalis-eval.dts
index 0edd3043d9c1..4665e15b196d 100644
--- a/arch/arm/boot/dts/imx6q-apalis-eval.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts
@@ -167,6 +167,19 @@
  {
status = "okay";
 
+   /*
+* Touchscreen is using SODIMM 28/30, also used for PWM, PWM,
+* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+*/
+   touchscreen@4a {
+   compatible = "atmel,maxtouch";
+   reg = <0x4a>;
+   interrupt-parent = <>;
+   interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+   reset-gpios = < 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
+   status = "disabled";
+   };
+
pcie-switch@58 {
compatible = "plx,pex8605";
reg = <0x58>;
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts 
b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
index b94bb687be6b..a3fa04a97d81 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
@@ -172,6 +172,19 @@
  {
status = "okay";
 
+   /*
+* Touchscreen is using SODIMM 28/30, also used for PWM, PWM,
+* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+*/
+   touchscreen@4a {
+   compatible = "atmel,maxtouch";
+   reg = <0x4a>;
+   interrupt-parent = <>;
+   interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+   reset-gpios = < 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
+   status = "disabled";
+   };
+
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts 
b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
index 302fd6adc8a7..5ba49d0f4880 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
@@ -171,6 +171,19 @@
  {
status = "okay";
 
+   /*
+* Touchscreen is using SODIMM 28/30, also used for PWM, PWM,
+* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+*/
+   touchscreen@4a {
+   compatible = "atmel,maxtouch";
+   reg = <0x4a>;
+   interrupt-parent = <>;
+   interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+   reset-gpios = < 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
+   status = "disabled";
+   };
+
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
-- 
2.22.0

[PATCH v3 08/21] ARM: dts: imx7-colibri: Add touch controllers

[Philippe Schenker]

Add touch controller that is connected over an I2C bus.

Signed-off-by: Philippe Schenker 

---

Changes in v3:
- Fix commit message

Changes in v2:
- Deleted touchrevolution downstream stuff
- Use generic node name
- Better comment

 arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 24 +
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi 
b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
index d4dbc4fc1adf..576dec9ff81c 100644
--- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
@@ -145,6 +145,21 @@
  {
status = "okay";
 
+   /*
+* Touchscreen is using SODIMM 28/30, also used for PWM, PWM,
+* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+*/
+   touchscreen@4a {
+   compatible = "atmel,maxtouch";
+   pinctrl-names = "default";
+   pinctrl-0 = <_gpiotouch>;
+   reg = <0x4a>;
+   interrupt-parent = <>;
+   interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
+   reset-gpios = < 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
+   status = "disabled";
+   };
+
/* M41T0M6 real time clock on carrier board */
rtc: m41t0m6@68 {
compatible = "st,m41t0";
@@ -200,3 +215,12 @@
vmmc-supply = <_3v3>;
status = "okay";
 };
+
+ {
+   pinctrl_gpiotouch: touchgpios {
+   fsl,pins = <
+   MX7D_PAD_GPIO1_IO09__GPIO1_IO9  0x74
+   MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14
+   >;
+   };
+};
-- 
2.22.0

[PATCH v3 10/21] ARM: dts: imx6qdl-colibri: Add missing pin declaration in iomuxc

[Philippe Schenker]

This adds the muxing for the optional pins usb-oc (overcurrent) and
usb-id.

Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx6qdl-colibri.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi 
b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
index 019dda6b88ad..9a63debab0b5 100644
--- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -615,6 +615,13 @@
>;
};
 
+   pinctrl_usbh_oc_1: usbh_oc-1 {
+   fsl,pins = <
+   /* USBH_OC */
+   MX6QDL_PAD_EIM_D30__GPIO3_IO30  0x1b0b0
+   >;
+   };
+
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
@@ -681,6 +688,13 @@
>;
};
 
+   pinctrl_usbc_id_1: usbc_id-1 {
+   fsl,pins = <
+   /* USBC_ID */
+   MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+   >;
+   };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
-- 
2.22.0

[PATCH v3 19/21] ARM: dts: imx6/7-colibri: switch dr_mode to otg

[Philippe Schenker]

In order for the otg ports, that these modules support, it is needed
that dr_mode is on otg. Switch to use that feature.

Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx6qdl-colibri.dtsi | 2 +-
 arch/arm/boot/dts/imx7-colibri.dtsi| 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi 
b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
index 9a63debab0b5..6674198346d2 100644
--- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -388,7 +388,7 @@
  {
pinctrl-names = "default";
disable-over-current;
-   dr_mode = "peripheral";
+   dr_mode = "otg";
status = "disabled";
 };
 
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi 
b/arch/arm/boot/dts/imx7-colibri.dtsi
index 67f5e0c87fdc..42478f1aa146 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -320,7 +320,7 @@
 };
 
  {
-   dr_mode = "host";
+   dr_mode = "otg";
 };
 
  {
-- 
2.22.0

[PATCH v3 07/21] ARM: dts: imx7-colibri: fix 1.8V/UHS support

[Philippe Schenker]

From: Stefan Agner 

Add pinmuxing and do not specify voltage restrictions for the usdhc
instance available on the modules edge connector. This allows to use
SD-cards with higher transfer modes if supported by the carrier board.

Signed-off-by: Stefan Agner 
Signed-off-by: Philippe Schenker 

---

Changes in v3:
- Add new commit message from Stefan's proposal on ML

Changes in v2: None

 arch/arm/boot/dts/imx7-colibri.dtsi | 23 ++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi 
b/arch/arm/boot/dts/imx7-colibri.dtsi
index 16d1a1ed1aff..67f5e0c87fdc 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -326,7 +326,6 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_usdhc1 _cd_usdhc1>;
-   no-1-8-v;
cd-gpios = < 0 GPIO_ACTIVE_LOW>;
disable-wp;
vqmmc-supply = <_LDO2>;
@@ -671,6 +670,28 @@
>;
};
 
+   pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+   fsl,pins = <
+   MX7D_PAD_SD1_CMD__SD1_CMD   0x5a
+   MX7D_PAD_SD1_CLK__SD1_CLK   0x1a
+   MX7D_PAD_SD1_DATA0__SD1_DATA0   0x5a
+   MX7D_PAD_SD1_DATA1__SD1_DATA1   0x5a
+   MX7D_PAD_SD1_DATA2__SD1_DATA2   0x5a
+   MX7D_PAD_SD1_DATA3__SD1_DATA3   0x5a
+   >;
+   };
+
+   pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+   fsl,pins = <
+   MX7D_PAD_SD1_CMD__SD1_CMD   0x5b
+   MX7D_PAD_SD1_CLK__SD1_CLK   0x1b
+   MX7D_PAD_SD1_DATA0__SD1_DATA0   0x5b
+   MX7D_PAD_SD1_DATA1__SD1_DATA1   0x5b
+   MX7D_PAD_SD1_DATA2__SD1_DATA2   0x5b
+   MX7D_PAD_SD1_DATA3__SD1_DATA3   0x5b
+   >;
+   };
+
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD   0x59
-- 
2.22.0

[PATCH v3 18/21] ARM: dts: imx6ull-colibri: Add general wakeup key used on Colibri

[Philippe Schenker]

This adds the possibility to wake the module with an external signal
as defined in the Colibri standard

Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi 
b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
index 3bee37c75aa6..d3c4809f140e 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -8,6 +8,20 @@
stdout-path = "serial0:115200n8";
};
 
+   gpio-keys {
+   compatible = "gpio-keys";
+   pinctrl-names = "default";
+   pinctrl-0 = <_snvs_gpiokeys>;
+
+   power {
+   label = "Wake-Up";
+   gpios = < 1 GPIO_ACTIVE_HIGH>;
+   linux,code = ;
+   debounce-interval = <10>;
+   wakeup-source;
+   };
+   };
+
/* fixed crystal dedicated to mcp2515 */
clk16m: clk16m {
compatible = "fixed-clock";
-- 
2.22.0

Re: [PATCH v2 3/5] dt-bindings: arm: Extend SCMI to support new reset protocol

[Philipp Zabel]

On Tue, 2019-08-06 at 18:02 +0100, Sudeep Holla wrote:
> SCMIv2.0 adds a new Reset Management Protocol to manage various reset
> states a given device or domain can enter. Extend the existing SCMI
> bindings to add reset protocol support by re-using the reset bindings
> for bothe reset providers and consumers.
  ^
typo

> 
> Cc: Philipp Zabel 

regards
Philipp

[PATCH v3 16/21] ARM: dts: imx6ull-colibri: Add watchdog

[Philippe Schenker]

This patch adds the watchdog to the imx6ull-colibri devicetree

Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx6ull-colibri.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi 
b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 1f112ec55e5c..e3220298dd6f 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -199,6 +199,12 @@
assigned-clock-rates = <0>, <19800>;
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_wdog>;
+   fsl,ext-reset-output;
+};
+
  {
pinctrl_can_int: canint-grp {
fsl,pins = <
@@ -506,6 +512,12 @@
MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT0x14
>;
};
+
+   pinctrl_wdog: wdog-grp {
+   fsl,pins = <
+   MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY0x30b0
+   >;
+   };
 };
 
 _snvs {
-- 
2.22.0

[PATCH v3 17/21] ARM: dts: imx6ull: improve can templates

[Philippe Schenker]

From: Max Krummenacher 

Add the pinmuxing and a inactive node for flexcan1 on SODIMM 55/63
and move the inactive flexcan nodes to imx6ull-colibri-eval-v3.dtsi
where they belong.

Note that this commit does not enable flexcan functionality, but rather
eases the effort needed to do so.

Signed-off-by: Max Krummenacher 
Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 12 
 arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi |  2 +-
 arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi|  2 +-
 arch/arm/boot/dts/imx6ull-colibri.dtsi | 16 ++--
 4 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi 
b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
index b6147c76d159..3bee37c75aa6 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -83,6 +83,18 @@
};
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_flexcan1>;
+   status = "disabled";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_flexcan2>;
+   status = "disabled";
+};
+
  {
status = "okay";
 
diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi 
b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
index fb213bec4654..95a11b8bcbdb 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
@@ -15,7 +15,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_gpio1 _gpio2 _gpio3
-   _gpio4 _gpio5 _gpio6>;
+   _gpio4 _gpio5 _gpio6 _gpio7>;
 };
 
 _snvs {
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi 
b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
index 038d8c90f6df..a0545431b3dc 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
@@ -26,7 +26,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_gpio1 _gpio2 _gpio3
-   _gpio4 _gpio5>;
+   _gpio4 _gpio5 _gpio7>;
 
 };
 
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi 
b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index e3220298dd6f..553d4c1f80e9 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -256,6 +256,13 @@
>;
};
 
+   pinctrl_flexcan1: flexcan1-grp {
+   fsl,pins = <
+   MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX   0x1b020
+   MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX   0x1b020
+   >;
+   };
+
pinctrl_flexcan2: flexcan2-grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX   0x1b020
@@ -271,8 +278,6 @@
 
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
-   MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO000x74 /* SODIMM 
55 */
-   MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO010x74 /* SODIMM 
63 */
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 
77 */
MX6UL_PAD_JTAG_TCK__GPIO1_IO14  0x14 /* SODIMM 
99 */
MX6UL_PAD_NAND_CE1_B__GPIO4_IO140x14 /* SODIMM 
133 */
@@ -325,6 +330,13 @@
>;
};
 
+   pinctrl_gpio7: gpio7-grp { /* CAN1 */
+   fsl,pins = <
+   MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO000x74 /* SODIMM 
55 */
+   MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO010x74 /* SODIMM 
63 */
+   >;
+   };
+
pinctrl_gpmi_nand: gpmi-nand-grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x100a9
-- 
2.22.0

[PATCH v3 20/21] ARM: dts: imx6ull-colibri: Add touchscreen used with Eval Board

[Philippe Schenker]

This adds the common touchscreen that is used with Toradex's
Eval Boards.

Signed-off-by: Philippe Schenker 

---

Changes in v3: None
Changes in v2:
- Removed f0710a, that is downstream only
- Changed to generic node name
- Better comment

 .../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 24 +++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi 
b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
index d3c4809f140e..78e74bfeca1b 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -112,6 +112,21 @@
  {
status = "okay";
 
+   /*
+* Touchscreen is using SODIMM 28/30, also used for PWM, PWM,
+* aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+*/
+   touchscreen@4a {
+   compatible = "atmel,maxtouch";
+   pinctrl-names = "default";
+   pinctrl-0 = <_gpiotouch>;
+   reg = <0x4a>;
+   interrupt-parent = <>;
+   interrupts = <16 IRQ_TYPE_EDGE_FALLING>;/* SODIMM 28 */
+   reset-gpios = < 5 GPIO_ACTIVE_HIGH>;  /* SODIMM 30 */
+   status = "disabled";
+   };
+
/* M41T0M6 real time clock on carrier board */
m41t0m6: rtc@68 {
compatible = "st,m41t0";
@@ -188,3 +203,12 @@
sd-uhs-sdr104;
status = "okay";
 };
+
+ {
+   pinctrl_gpiotouch: touchgpios {
+   fsl,pins = <
+   MX6UL_PAD_NAND_DQS__GPIO4_IO16  0x74
+   MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05   0x14
+   >;
+   };
+};
-- 
2.22.0

[PATCH v3 15/21] ARM: dts: imx6ull-colibri: reduce v_batt current in power off

[Philippe Schenker]

From: Max Krummenacher 

Reduce the current drawn from VCC_BATT when the main power on the 3V3
pins to the module are switched off.

This switches off SoC internal pull resistors which are provided on the
module for TAMPER7 and TAMPER9 SoC pin and switches on a pull down
instead of a pullup for the USBC_DET module pin (TAMPER2).

Signed-off-by: Max Krummenacher 
Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx6ull-colibri.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi 
b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 1019ce69a242..1f112ec55e5c 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -533,19 +533,19 @@
 
pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
fsl,pins = <
-   MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
+   MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0
>;
};
 
pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
fsl,pins = <
-   MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0
+   MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0
>;
};
 
pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
fsl,pins = <
-   MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
+   MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0
>;
};
 
-- 
2.22.0

[PATCH v3 21/21] ARM: dts: imx7-colibri: Add UHS support to eval board

[Philippe Schenker]

This commit adds UHS capability to Toradex Eval Boards

Signed-off-by: Philippe Schenker 

---

Changes in v3:
- New patch to make use of ARM: dts: imx7-colibri: fix 1.8V/UHS support

Changes in v2: None

 arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi 
b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
index 576dec9ff81c..90121fbe561f 100644
--- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
@@ -210,9 +210,16 @@
 };
 
  {
-   keep-power-in-suspend;
-   wakeup-source;
+   pinctrl-names = "default", "state_100mhz", "state_200mhz";
+   pinctrl-0 = <_usdhc1 _cd_usdhc1>;
+   pinctrl-1 = <_usdhc1_100mhz _cd_usdhc1>;
+   pinctrl-2 = <_usdhc1_200mhz _cd_usdhc1>;
vmmc-supply = <_3v3>;
+   vqmmc-supply = <_LDO2>;
+   cd-gpios = < 0 GPIO_ACTIVE_LOW>;
+   disable-wp;
+   enable-sdio-wakeup;
+   keep-power-in-suspend;
status = "okay";
 };
 
-- 
2.22.0

[PATCH v3 02/21] ARM: dts: imx7-colibri: disable HS400

[Philippe Schenker]

From: Stefan Agner 

Force HS200 by masking bit 63 of the SDHCI capability register.
The i.MX ESDHC driver uses SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400. With
that the stack checks bit 63 to descide whether HS400 is available.
Using sdhci-caps-mask allows to mask bit 63. The stack then selects
HS200 as operating mode.

This prevents rare communication errors with minimal effect on
performance:
sdhci-esdhc-imx 30b6.usdhc: warning! HS400 strobe DLL
status REF not lock!

Signed-off-by: Stefan Agner 
Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx7-colibri.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi 
b/arch/arm/boot/dts/imx7-colibri.dtsi
index f1c1971f2160..f7c9ce5bed47 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -325,6 +325,7 @@
vmmc-supply = <_module_3v3>;
vqmmc-supply = <_DCDC3>;
non-removable;
+   sdhci-caps-mask = <0x8000 0x0>;
 };
 
  {
-- 
2.22.0

[PATCH v3 09/21] ARM: dts: imx6qdl-colibri: add phy to fec

[Philippe Schenker]

Add the phy-node and mdio bus to the fec-node, represented as is on
hardware.
This commit includes micrel,led-mode that is set to the default
value, prepared for someone who wants to change this.

Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx6qdl-colibri.dtsi | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi 
b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
index 1beac22266ed..019dda6b88ad 100644
--- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -140,7 +140,18 @@
pinctrl-names = "default";
pinctrl-0 = <_enet>;
phy-mode = "rmii";
+   phy-handle = <>;
status = "okay";
+
+   mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethphy: ethernet-phy@0 {
+   reg = <0>;
+   micrel,led-mode = <0>;
+   };
+   };
 };
 
  {
-- 
2.22.0

[PATCH v3 14/21] ARM: dts: imx6ull-colibri: Add sleep mode to fec

[Philippe Schenker]

Do not change the clock as the power for this phy is switched
with that clock.

Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx6ull-colibri.dtsi | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi 
b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index d56728f03c35..1019ce69a242 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -62,8 +62,9 @@
 };
 
  {
-   pinctrl-names = "default";
+   pinctrl-names = "default", "sleep";
pinctrl-0 = <_enet2>;
+   pinctrl-1 = <_enet2_sleep>;
phy-mode = "rmii";
phy-handle = <>;
status = "okay";
@@ -220,6 +221,21 @@
>;
};
 
+   pinctrl_enet2_sleep: enet2sleepgrp {
+   fsl,pins = <
+   MX6UL_PAD_GPIO1_IO06__GPIO1_IO060x0
+   MX6UL_PAD_GPIO1_IO07__GPIO1_IO070x0
+   MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO080x0
+   MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO090x0
+   MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10   0x0
+   MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15   0x0
+   MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
+   MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO110x0
+   MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO120x0
+   MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13   0x0
+   >;
+   };
+
pinctrl_ecspi1_cs: ecspi1-cs-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA21__GPIO3_IO260x000a0
-- 
2.22.0

[PATCH v3 13/21] ARM: dts: imx6-colibri: Add missing pinmuxing to Toradex eval board

[Philippe Schenker]

This patch adds some missing pinmuxing that is in the colibri
standard to the dts.

Signed-off-by: Philippe Schenker 

---

Changes in v3: None
Changes in v2:
- Commit title

 arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts 
b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index 763fb5e90bd3..e7a2d8c3b2d4 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -191,6 +191,14 @@
 };
 
  {
+   pinctrl-names = "default";
+   pinctrl-0 = <
+   _weim_gpio_1 _weim_gpio_2
+   _weim_gpio_3 _weim_gpio_4
+   _weim_gpio_5 _weim_gpio_6
+   _usbh_oc_1 _usbc_id_1
+   >;
+
pinctrl_pcap_1: pcap-1 {
fsl,pins = <
MX6QDL_PAD_GPIO_9__GPIO1_IO09   0x1b0b0 /* SODIMM 28 */
-- 
2.22.0

[PATCH v3 01/21] ARM: dts: imx7-colibri: make sure module supplies are always on

[Philippe Schenker]

From: Marcel Ziswiler 

Prevent regulators from being switched off.

Signed-off-by: Marcel Ziswiler 
Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx7-colibri.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi 
b/arch/arm/boot/dts/imx7-colibri.dtsi
index 895fbde4d433..f1c1971f2160 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -54,6 +54,7 @@
regulator-name = "+V3.3";
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
+   regulator-always-on;
};
 
reg_module_3v3_avdd: regulator-module-3v3-avdd {
@@ -61,6 +62,7 @@
regulator-name = "+V3.3_AVDD_AUDIO";
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
+   regulator-always-on;
};
 
sound {
-- 
2.22.0

[PATCH v3 05/21] ARM: dts: add recovery for I2C for iMX7

[Philippe Schenker]

From: Oleksandr Suvorov 

- add recovery mode for applicable i2c buses for
  Colibri iMX7 module.

Signed-off-by: Oleksandr Suvorov 
Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx7-colibri.dtsi | 25 +++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi 
b/arch/arm/boot/dts/imx7-colibri.dtsi
index a8d992f3e897..2480623c92ff 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -140,8 +140,12 @@
 
  {
clock-frequency = <10>;
-   pinctrl-names = "default";
+   pinctrl-names = "default", "gpio";
pinctrl-0 = <_i2c1 _i2c1_int>;
+   pinctrl-1 = <_i2c1_recovery _i2c1_int>;
+   scl-gpios = < 4 GPIO_ACTIVE_HIGH>;
+   sda-gpios = < 5 GPIO_ACTIVE_HIGH>;
+
status = "okay";
 
codec: sgtl5000@a {
@@ -242,8 +246,11 @@
 
  {
clock-frequency = <10>;
-   pinctrl-names = "default";
+   pinctrl-names = "default", "gpio";
pinctrl-0 = <_i2c4>;
+   pinctrl-1 = <_i2c4_recovery>;
+   scl-gpios = < 8 GPIO_ACTIVE_HIGH>;
+   sda-gpios = < 9 GPIO_ACTIVE_HIGH>;
 };
 
  {
@@ -540,6 +547,13 @@
>;
};
 
+   pinctrl_i2c4_recovery: i2c4-recoverygrp {
+   fsl,pins = <
+   MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x407f
+   MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x407f
+   >;
+   };
+
pinctrl_lcdif_dat: lcdif-dat-grp {
fsl,pins = <
MX7D_PAD_LCD_DATA00__LCD_DATA0  0x79
@@ -740,6 +754,13 @@
>;
};
 
+   pinctrl_i2c1_recovery: i2c1-recoverygrp {
+   fsl,pins = <
+   MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x407f
+   MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x407f
+   >;
+   };
+
pinctrl_cd_usdhc1: usdhc1-cd-grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */
-- 
2.22.0

[PATCH v3 06/21] ARM: dts: imx7-colibri: add GPIO wakeup key

[Philippe Schenker]

From: Stefan Agner 

Add wakeup GPIO key which is able to wake the system from sleep
modes (e.g. Suspend-to-Memory).

Signed-off-by: Stefan Agner 
Signed-off-by: Philippe Schenker 
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 14 ++
 arch/arm/boot/dts/imx7-colibri.dtsi |  7 ++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi 
b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
index 3f2746169181..d4dbc4fc1adf 100644
--- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
@@ -52,6 +52,20 @@
clock-frequency = <1600>;
};
 
+   gpio-keys {
+   compatible = "gpio-keys";
+   pinctrl-names = "default";
+   pinctrl-0 = <_gpiokeys>;
+
+   power {
+   label = "Wake-Up";
+   gpios = < 1 GPIO_ACTIVE_HIGH>;
+   linux,code = ;
+   debounce-interval = <10>;
+   gpio-key,wakeup;
+   };
+   };
+
panel: panel {
compatible = "edt,et057090dhu";
backlight = <>;
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi 
b/arch/arm/boot/dts/imx7-colibri.dtsi
index 2480623c92ff..16d1a1ed1aff 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -741,12 +741,17 @@
 
pinctrl_gpio_lpsr: gpio1-grp {
fsl,pins = <
-   MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x59
MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59
MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59
>;
};
 
+   pinctrl_gpiokeys: gpiokeysgrp {
+   fsl,pins = <
+   MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19
+   >;
+   };
+
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA  0x407f
-- 
2.22.0

[PATCH v3 00/21] Common patches from downstream development

[Philippe Schenker]

This patchset holds some common changes that were never upstreamed.
With latest downstream kernel upgrade, I took the aproach to select
mainline devicetrees and atomically add missing stuff for downstream.

These patches I send here are separated out with changes that also
have a benfit for mainline.

Philippe

Changes in v3:
- Add new commit message from Stefan's proposal on ML
- Fix commit message
- Fix commit title to "...imx6-apalis:..."
- New patch to make use of ARM: dts: imx7-colibri: fix 1.8V/UHS support

Changes in v2:
- Deleted touchrevolution downstream stuff
- Use generic node name
- Better comment
- Changed commit title to '...imx6qdl-apalis:...'
- Deleted touchrevolution downstream stuff
- Use generic node name
- Put a better comment in there
- Commit title
- Removed f0710a, that is downstream only
- Changed to generic node name
- Better comment

Marcel Ziswiler (1):
  ARM: dts: imx7-colibri: make sure module supplies are always on

Max Krummenacher (2):
  ARM: dts: imx6ull-colibri: reduce v_batt current in power off
  ARM: dts: imx6ull: improve can templates

Oleksandr Suvorov (1):
  ARM: dts: add recovery for I2C for iMX7

Philippe Schenker (14):
  ARM: dts: imx7-colibri: prepare module device tree for FlexCAN
  ARM: dts: imx7-colibri: Add sleep mode to ethernet
  ARM: dts: imx7-colibri: Add touch controllers
  ARM: dts: imx6qdl-colibri: add phy to fec
  ARM: dts: imx6qdl-colibri: Add missing pin declaration in iomuxc
  ARM: dts: imx6qdl-apalis: Add sleep state to can interfaces
  ARM: dts: imx6-apalis: Add touchscreens used on Toradex eval boards
  ARM: dts: imx6-colibri: Add missing pinmuxing to Toradex eval board
  ARM: dts: imx6ull-colibri: Add sleep mode to fec
  ARM: dts: imx6ull-colibri: Add watchdog
  ARM: dts: imx6ull-colibri: Add general wakeup key used on Colibri
  ARM: dts: imx6/7-colibri: switch dr_mode to otg
  ARM: dts: imx6ull-colibri: Add touchscreen used with Eval Board
  ARM: dts: imx7-colibri: Add UHS support to eval board

Stefan Agner (3):
  ARM: dts: imx7-colibri: disable HS400
  ARM: dts: imx7-colibri: add GPIO wakeup key
  ARM: dts: imx7-colibri: fix 1.8V/UHS support

 arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts  |  39 ++
 arch/arm/boot/dts/imx6q-apalis-eval.dts   |  13 ++
 arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts |  13 ++
 arch/arm/boot/dts/imx6q-apalis-ixora.dts  |  13 ++
 arch/arm/boot/dts/imx6qdl-apalis.dtsi |  27 -
 arch/arm/boot/dts/imx6qdl-colibri.dtsi|  27 -
 .../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi |  50 
 .../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi |   2 +-
 arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi   |   2 +-
 arch/arm/boot/dts/imx6ull-colibri.dtsi|  52 +++-
 arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi   |  49 +++-
 arch/arm/boot/dts/imx7-colibri.dtsi   | 114 --
 12 files changed, 373 insertions(+), 28 deletions(-)

-- 
2.22.0

[PATCH] rtc: mxc: use spin_lock_irqsave instead of spin_lock_irq in IRQ context

[Fuqian Huang]

As spin_unlock_irq will enable interrupts.
mxc_rtc_irq_enable is called from interrupt handler mxc_rtc_interrupt.
Interrupts are enabled in interrupt handler.
Use spin_lock_irqsave/spin_unlock_irqrestore instead of spin_(un)lock_irq
in IRQ context to avoid this.

Signed-off-by: Fuqian Huang 
---
 drivers/rtc/rtc-mxc.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/rtc/rtc-mxc.c b/drivers/rtc/rtc-mxc.c
index e697e96612bb..902d57dcd0d4 100644
--- a/drivers/rtc/rtc-mxc.c
+++ b/drivers/rtc/rtc-mxc.c
@@ -184,8 +184,9 @@ static void mxc_rtc_irq_enable(struct device *dev, unsigned 
int bit,
struct rtc_plat_data *pdata = dev_get_drvdata(dev);
void __iomem *ioaddr = pdata->ioaddr;
u32 reg;
+   unsigned long flags;
 
-   spin_lock_irq(>rtc->irq_lock);
+   spin_lock_irqsave(>rtc->irq_lock, flags);
reg = readw(ioaddr + RTC_RTCIENR);
 
if (enabled)
@@ -194,7 +195,7 @@ static void mxc_rtc_irq_enable(struct device *dev, unsigned 
int bit,
reg &= ~bit;
 
writew(reg, ioaddr + RTC_RTCIENR);
-   spin_unlock_irq(>rtc->irq_lock);
+   spin_unlock_irqrestore(>rtc->irq_lock, flags);
 }
 
 /* This function is the RTC interrupt service routine. */
-- 
2.11.0

Re: Odroid-XU4 sound issue after suspend-resume

[Sylwester Nawrocki]

Hi Jaafar, 

On 8/5/19 15:27, Jaafar Ali wrote:
> Dear All,
> Kernel 5.3-rc1
> OS: ubuntu 18.04
> Hardware: Odroid-XU4
> The sound of Odroid-XU4 after suspend/resume cycle is choppy and slow. 
> I have found a workaround, the I2SMOD register value should be set to 
> zero after resume to force using internal codec clock (cdclkcon bit = 0),
> also the rclk_srcrate which is obtained from the function 
> *clk_get_rate(rclksrc) *inside *hw_params* function is not correct and 
> must be divided by 2 to obtain proper value, i2s_resume function 
> is modified to:
> 
> static int i2s_resume(struct snd_soc_dai *dai)
> {
>         struct samsung_i2s_priv *priv = dev_get_drvdata(dai->dev);
>         priv->suspend_i2smod = 0;//workaround-1 ,
>         return pm_runtime_force_resume(dai->dev);
> 
> }
> 
> inside hw_params function, the rclk_srcrate must be halved to solve 
> unknown problem of clock shift, so before return from hw_params we 
> must insert:
> if(mod == 0){
>   priv->rclk_srcrate = priv->rclk_srcrate / 2; //workaround-2, 
> }
> 
> With these two workaround sound issue was solved, but I hope we can 
> get concrete fix.
Thank you for the bug report. I spent some time on debugging this and
it turned out that there is a clock mux between EPLL and the audio 
subsystem which looses its configuration during suspend/resume cycle.
So we end up with the I2S controller clocked from the main oscillator
clock (24 MHz) rather than the EPLL (196.608 MHz) after system suspend/
resume. I will post a patch for clk-exynos5420 driver shortly.

-- 
Regards,
Sylwester

Re: [PATCH 2/6] ARM: cpuidle: Remove overzealous error logging

[Daniel Lezcano]

On 22/07/2019 17:37, Lorenzo Pieralisi wrote:
> CPUidle back-end operations are not implemented in some platforms
> but this should not be considered an error serious enough to be
> logged. Check the arm_cpuidle_init() return value to detect whether
> the failure must be reported or not in the kernel log and do
> not log it if the platform does not support CPUidle operations.
> 
> Signed-off-by: Lorenzo Pieralisi 
> Cc: Ulf Hansson 
> Cc: Sudeep Holla 
> Cc: Daniel Lezcano 
> Cc: "Rafael J. Wysocki" 

Acked-by: Daniel Lezcano 


-- 
  Linaro.org │ Open source software for ARM SoCs

Follow Linaro:   Facebook |
 Twitter |
 Blog

Re: [PATCH 1/6] ARM: cpuidle: Remove useless header include

[Daniel Lezcano]

On 22/07/2019 17:37, Lorenzo Pieralisi wrote:
> The generic ARM CPUidle driver includes  by mistake.
> 
> Remove the topology header include.
> 
> Signed-off-by: Lorenzo Pieralisi 
> Cc: Ulf Hansson 
> Cc: Sudeep Holla 
> Cc: Daniel Lezcano 
> Cc: "Rafael J. Wysocki" 

Acked-by: Daniel Lezcano 



-- 
  Linaro.org │ Open source software for ARM SoCs

Follow Linaro:   Facebook |
 Twitter |
 Blog

Re: [PATCH v2 4/5] firmware: arm_scmi: Add RESET protocol in SCMI v2.0

[Philipp Zabel]

On Tue, 2019-08-06 at 18:02 +0100, Sudeep Holla wrote:
> SCMIv2.0 adds a new Reset Management Protocol to manage various reset
> states a given device or domain can enter. Device(s) that can be
> collectively reset through a common reset signal constitute a reset
> domain for the firmware.
> 
> A reset domain can be reset autonomously or explicitly through assertion
> and de-assertion of the signal. When autonomous reset is chosen, the
> firmware is responsible for taking the necessary steps to reset the
> domain and to subsequently bring it out of reset. When explicit reset is
> chosen, the caller has to specifically assert and then de-assert the
> reset signal by issuing two separate RESET commands.
> 
> Add the basic SCMI reset infrastructure that can be used by Linux
> reset controller driver.
> 
> Cc: Philipp Zabel 
> Signed-off-by: Sudeep Holla 
> ---
>  drivers/firmware/arm_scmi/Makefile |   2 +-
>  drivers/firmware/arm_scmi/reset.c  | 231 +
>  include/linux/scmi_protocol.h  |  26 
>  3 files changed, 258 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/firmware/arm_scmi/reset.c
> 
> diff --git a/drivers/firmware/arm_scmi/Makefile 
> b/drivers/firmware/arm_scmi/Makefile
> index c47d28d556b6..5f298f00a82e 100644
> --- a/drivers/firmware/arm_scmi/Makefile
> +++ b/drivers/firmware/arm_scmi/Makefile
> @@ -2,5 +2,5 @@
>  obj-y= scmi-bus.o scmi-driver.o scmi-protocols.o
>  scmi-bus-y = bus.o
>  scmi-driver-y = driver.o
> -scmi-protocols-y = base.o clock.o perf.o power.o sensors.o
> +scmi-protocols-y = base.o clock.o perf.o power.o reset.o sensors.o
>  obj-$(CONFIG_ARM_SCMI_POWER_DOMAIN) += scmi_pm_domain.o
> diff --git a/drivers/firmware/arm_scmi/reset.c 
> b/drivers/firmware/arm_scmi/reset.c
> new file mode 100644
> index ..11cb8b5ccf34
> --- /dev/null
> +++ b/drivers/firmware/arm_scmi/reset.c
> @@ -0,0 +1,231 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * System Control and Management Interface (SCMI) Reset Protocol
> + *
> + * Copyright (C) 2019 ARM Ltd.
> + */
> +
> +#include "common.h"
> +
> +enum scmi_reset_protocol_cmd {
> + RESET_DOMAIN_ATTRIBUTES = 0x3,
> + RESET = 0x4,
> + RESET_NOTIFY = 0x5,
> +};
> +
> +enum scmi_reset_protocol_notify {
> + RESET_ISSUED = 0x0,
> +};
> +
> +#define NUM_RESET_DOMAIN_MASK0x
> +#define RESET_NOTIFY_ENABLE  BIT(0)
> +
> +struct scmi_msg_resp_reset_domain_attributes {
> + __le32 attributes;
> +#define SUPPORTS_ASYNC_RESET(x)  ((x) & BIT(31))
> +#define SUPPORTS_NOTIFY_RESET(x) ((x) & BIT(30))
> + __le32 latency;
> + u8 name[SCMI_MAX_STR_SIZE];
> +};
> +
> +struct scmi_msg_reset_domain_reset {
> + __le32 domain_id;
> + __le32 flags;
> +#define AUTONOMOUS_RESET BIT(0)
> +#define EXPLICIT_RESET_ASSERTBIT(1)
> +#define ASYNCHRONOUS_RESET   BIT(2)
> + __le32 reset_state;
> +#define ARCH_RESET_TYPE  BIT(31)
> +#define COLD_RESET_STATE BIT(0)
> +#define ARCH_COLD_RESET  (ARCH_RESET_TYPE | COLD_RESET_STATE)
> +};
> +
> +struct reset_dom_info {
> + bool async_reset;
> + bool reset_notify;
> + u32 latency_us;
> + char name[SCMI_MAX_STR_SIZE];
> +};
> +
> +struct scmi_reset_info {
> + int num_domains;
> + struct reset_dom_info *dom_info;
> +};
> +
> +static int scmi_reset_attributes_get(const struct scmi_handle *handle,
> +  struct scmi_reset_info *pi)
> +{
> + int ret;
> + struct scmi_xfer *t;
> + u32 *attr;
> +
> + ret = scmi_xfer_get_init(handle, PROTOCOL_ATTRIBUTES,
> +  SCMI_PROTOCOL_RESET, 0, sizeof(*attr), );
> + if (ret)
> + return ret;
> +
> + attr = t->rx.buf;
> +
> + ret = scmi_do_xfer(handle, t);
> + if (!ret)
> + pi->num_domains = le32_to_cpu(*attr) & NUM_RESET_DOMAIN_MASK;
> +
> + scmi_xfer_put(handle, t);
> + return ret;
> +}
> +
> +static int
> +scmi_reset_domain_attributes_get(const struct scmi_handle *handle, u32 
> domain,
> +  struct reset_dom_info *dom_info)
> +{
> + int ret;
> + struct scmi_xfer *t;
> + struct scmi_msg_resp_reset_domain_attributes *attr;
> +
> + ret = scmi_xfer_get_init(handle, RESET_DOMAIN_ATTRIBUTES,
> +  SCMI_PROTOCOL_RESET, sizeof(domain),
> +  sizeof(*attr), );
> + if (ret)
> + return ret;
> +
> + *(__le32 *)t->tx.buf = cpu_to_le32(domain);

Should this use
put_unaligned_le32(domain, t->tx.buf);
? Either way,

Reviewed-by: Philipp Zabel 

regards
Philipp

next-20190806: arm64: adv7511 3-0039: failed to find dsi host

[Naresh Kamboju]

arm64 devices dragonboard 410c (QC410E) and hi6220-hikey running Linux
next-20190806 loading modules causing floods of kernel messages.

We have enabled few extra kernel configs for testing.
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_I2C_ADV7511_CEC=y
...

Please find below boot log and config file link.

[0.00] Linux version 5.3.0-rc3-next-20190806 (oe-user@oe-host)
(gcc version 7.3.0 (GCC)) #1 SMP PREEMPT Tue Aug 6 05:49:36 UTC 2019
[0.00] Machine model: Qualcomm Technologies, Inc. APQ 8016 SBC

[   10.051193] adv7511 3-0039: 3-0039 supply dvdd not found, using
dummy regulator
[   10.051633] adv7511 3-0039: 3-0039 supply pvdd not found, using
dummy regulator
[   10.076257] adreno 1c0.gpu: Adding to iommu group 0
[   10.090929] adv7511 3-0039: 3-0039 supply a2vdd not found, using
dummy regulator
[   10.101703] msm_mdp 1a01000.mdp: Adding to iommu group 1
[   10.102563] msm_mdp 1a01000.mdp: No interconnect support may cause
display underflows!
[   10.139492] adv7511 3-0039: failed to find dsi host
...
[   33.065744] adv7511 3-0039: failed to find dsi host
[   33.076721] msm 1a0.mdss: 1a0.mdss supply vdd not found,
using dummy regulator
[   33.078344] msm_mdp 1a01000.mdp: [drm:mdp5_bind [msm]] MDP5 version v1.6
[   33.083862] msm 1a0.mdss: bound 1a01000.mdp (ops mdp5_ops [msm])
[   33.090892] msm_dsi 1a98000.dsi: 1a98000.dsi supply gdsc not found,
using dummy regulator
[   33.097756] msm_dsi 1a98000.dsi: 1a98000.dsi supply gdsc not found,
using dummy regulator
[   33.106606] msm_dsi_manager_register: failed to register mipi dsi
host for DSI 0
[   33.114579] msm 1a0.mdss: failed to bind 1a98000.dsi (ops
dsi_ops [msm]): -517
[   33.121263] msm 1a0.mdss: master bind failed: -517
[   33.135547] adv7511 3-0039: 3-0039 supply dvdd not found, using
dummy regulator
[   33.139360] adv7511 3-0039: 3-0039 supply pvdd not found, using
dummy regulator
[   33.143646] adv7511 3-0039: 3-0039 supply a2vdd not found, using
dummy regulator

Full test log
https://lkft.validation.linaro.org/scheduler/job/860208#L956

metadata:
  git branch: master
  git repo: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
  git commit: 958eb4327c1761c609bde8e9f7c04e9d1c6fbb96
  git describe: next-20190806
  make_kernelversion: 5.3.0-rc3
  kernel-config:
http://snapshots.linaro.org/openembedded/lkft/lkft/sumo/dragonboard-410c/lkft/linux-next/579/config
  kernel-defconfig:
http://snapshots.linaro.org/openembedded/lkft/lkft/sumo/dragonboard-410c/lkft/linux-next/579/defconfig
  build-location:
http://snapshots.linaro.org/openembedded/lkft/lkft/sumo/dragonboard-410c/lkft/linux-next/579

Best regards
Naresh Kamboju

Re: Fw: Looking for Odenix developers.

[Ywe Cærlyn]

I now also have a new mail, at my new domain OdenixDev.eu. Which we´ll 
see if maybe some more things get installed on the server there. 
Particulary something less macho than text-only mailing list.. ;)


I see Thunderbird  team is asking for donations aswell on their page. 
This is all solved with Odenix Net-Trade Patchclass, fair labour 
compliant, and well-grounded in sound philosophy, and accepted fair 
labour politics, going all the way back to Odenic Intercultural Trade, 
with the same principles.


Peace (Go With Thee).
Ywe Cærlyn
Odenix Net-Trade Patchclass for BSD.
https://www.youtube.com/channel/UCR3gmLVjHS5A702wo4bol_Q

Den 07.08.2019 10:00, skrev Ywe Cærlyn:




Sent with ProtonMail Secure Email.

‐‐‐ Original Message ‐‐‐
On Saturday 3. August 2019 kl. 12:33, Ywe Cærlyn  wrote:


Hello.

I am Ywe Cærlyn, from Norway, known in the Indie Computer Usergroup Scene, 
since the early 90s with top results. Now as part of my research, that was top 
1% on academia.edu, I suggest a Fair Labour compliant patchclass for BSD, with 
integrated online currency, for those with netjob skills.

Meaning for instance finely presented news, where reporters can upload their 
media, set attributes for re-use and not, and get royalites automatically, and 
everyone potentially could be part of this, and all content creators.

Representing a universalized and well indexed file directory for all files 
published:

OTTP://Category/Subcategory/Country/15.000km2 zone/Person/Groupings(can be 
several) (Odenic Transfer Text Protocol)

With pop statistics pr. folder, and file information field with commentary 
option, neatly presented.

Supporting 4K (8K subpixel precise), small form factor, 24bit audio, low-jitter 
I/O (200uS max OS jitter).

Peace (Go With Thee).
Ywe Cærlyn
Odenix Net-Trade Patchclass for BSD.
https://www.youtube.com/channel/UCR3gmLVjHS5A702wo4bol_Q

Re: [PATCH v2 5/5] reset: Add support for resets provided by SCMI

[Philipp Zabel]

On Tue, 2019-08-06 at 18:02 +0100, Sudeep Holla wrote:
> On some ARM based systems, a separate Cortex-M based System Control
> Processor(SCP) provides the overall power, clock, reset and system
> control. System Control and Management Interface(SCMI) Message Protocol
> is defined for the communication between the Application Cores(AP)
> and the SCP.
> 
> Adds support for the resets provided using SCMI protocol for performing
> reset management of various devices present on the SoC. Various reset
> functionalities are achieved by the means of different ARM SCMI device
> operations provided by the ARM SCMI framework.
> 
> Cc: Philipp Zabel 
> Signed-off-by: Sudeep Holla 
> ---
>  MAINTAINERS|   1 +
>  drivers/reset/Kconfig  |  11 
>  drivers/reset/Makefile |   1 +
>  drivers/reset/reset-scmi.c | 126 +
>  4 files changed, 139 insertions(+)
>  create mode 100644 drivers/reset/reset-scmi.c
> 
> v1->v2:
>   - Renamed RESET_ARM_SCMI to RESET_SCMI and reworded Kconfig text
>   - Dropped unused struct device pointer from scmi_reset_data
>   - Added to_scmi_handle which helped to remove some repetitive code
>   - Fixed some doxygen comments
>   - Initialised rcdev.nr_resets
>   - Fixed MODULE_DESCRIPTION
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 6426db5198f0..f4af5c59c116 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -15545,6 +15545,7 @@ F:drivers/clk/clk-sc[mp]i.c
>  F:   drivers/cpufreq/sc[mp]i-cpufreq.c
>  F:   drivers/firmware/arm_scpi.c
>  F:   drivers/firmware/arm_scmi/
> +F:   drivers/reset/reset-scmi.c
>  F:   include/linux/sc[mp]i_protocol.h
>  
>  SYSTEM RESET/SHUTDOWN DRIVERS
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 21efb7d39d62..4178ac11ba85 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -116,6 +116,17 @@ config RESET_QCOM_PDC
> to control reset signals provided by PDC for Modem, Compute,
> Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
>  
> +config RESET_SCMI
> + tristate "Reset driver controlled via ARM SCMI interface"
> + depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
> + default ARM_SCMI_PROTOCOL
> + help
> +   This driver provides support for reset signal/domains that are
> +   controlled by firmware that implements the SCMI interface.
> +
> +   This driver uses SCMI Message Protocol to interact with the
> +   firmware controlling all the reset signals.
> +
>  config RESET_SIMPLE
>   bool "Simple Reset Controller Driver" if COMPILE_TEST
>   default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || 
> ARCH_ASPEED || ARCH_BITMAIN
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 61456b8f659c..cf60ce526064 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
>  obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
>  obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
>  obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
> +obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
>  obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
>  obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
>  obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
> diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c
> new file mode 100644
> index ..5e976a02a6cc
> --- /dev/null
> +++ b/drivers/reset/reset-scmi.c
> @@ -0,0 +1,126 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * ARM System Control and Management Interface (ARM SCMI) reset driver
> + *
> + * Copyright (C) 2019 ARM Ltd.
> + */
> +
> +#include 
> +#include 

You can drop mutex.h, it is unused.

> +#include 
> +#include 

This is not a platform device driver. Better replace this with

#include 

> +#include 
> +#include 
> +
> +/**
> + * struct scmi_reset_data - reset controller information structure
> + * @rcdev: reset controller entity
> + * @handle: ARM SCMI handle used for communication with system controller
> + * @dev: reset controller device pointer

Drop this line, dev has been removed from struct scmi_reset_data.

> + */
> +struct scmi_reset_data {
> + struct reset_controller_dev rcdev;
> + const struct scmi_handle *handle;
> +};
> +
> +#define to_scmi_reset_data(p)container_of((p), struct 
> scmi_reset_data, rcdev)
> +#define to_scmi_handle(p)(to_scmi_reset_data(p)->handle)
[...]

Apart from these,
Reviewed-by: Philipp Zabel 

regards
Philipp

[PATCH net-next v3 05/10] net: stmmac: selftests: Add RSS test

[Jose Abreu]

Add a test for RSS in the stmmac selftests.

Signed-off-by: Jose Abreu 

---
Cc: Giuseppe Cavallaro 
Cc: Alexandre Torgue 
Cc: Jose Abreu 
Cc: "David S. Miller" 
Cc: Maxime Coquelin 
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../net/ethernet/stmicro/stmmac/stmmac_selftests.c| 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c
index a97b1ea76438..83b775a8cedc 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c
@@ -700,6 +700,21 @@ static int stmmac_test_flowctrl(struct stmmac_priv *priv)
return ret;
 }
 
+static int stmmac_test_rss(struct stmmac_priv *priv)
+{
+   struct stmmac_packet_attrs attr = { };
+
+   if (!priv->dma_cap.rssen || !priv->rss.enable)
+   return -EOPNOTSUPP;
+
+   attr.dst = priv->dev->dev_addr;
+   attr.exp_hash = true;
+   attr.sport = 0x321;
+   attr.dport = 0x123;
+
+   return __stmmac_test_loopback(priv, );
+}
+
 #define STMMAC_LOOPBACK_NONE   0
 #define STMMAC_LOOPBACK_MAC1
 #define STMMAC_LOOPBACK_PHY2
@@ -745,6 +760,10 @@ static const struct stmmac_test {
.name = "Flow Control ",
.lb = STMMAC_LOOPBACK_PHY,
.fn = stmmac_test_flowctrl,
+   }, {
+   .name = "RSS  ",
+   .lb = STMMAC_LOOPBACK_PHY,
+   .fn = stmmac_test_rss,
},
 };
 
-- 
2.7.4

[PATCH net-next v3 07/10] net: stmmac: selftests: Add test for VLAN and Double VLAN Filtering

[Jose Abreu]

Add a selftest for VLAN and Double VLAN Filtering in stmmac.

Signed-off-by: Jose Abreu 

---
Cc: Giuseppe Cavallaro 
Cc: Alexandre Torgue 
Cc: Jose Abreu 
Cc: "David S. Miller" 
Cc: Maxime Coquelin 
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../net/ethernet/stmicro/stmmac/stmmac_selftests.c | 205 +
 1 file changed, 205 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c
index 83b775a8cedc..6b08bb15af15 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c
@@ -715,6 +715,203 @@ static int stmmac_test_rss(struct stmmac_priv *priv)
return __stmmac_test_loopback(priv, );
 }
 
+static int stmmac_test_vlan_validate(struct sk_buff *skb,
+struct net_device *ndev,
+struct packet_type *pt,
+struct net_device *orig_ndev)
+{
+   struct stmmac_test_priv *tpriv = pt->af_packet_priv;
+   struct stmmachdr *shdr;
+   struct ethhdr *ehdr;
+   struct udphdr *uhdr;
+   struct iphdr *ihdr;
+
+   skb = skb_unshare(skb, GFP_ATOMIC);
+   if (!skb)
+   goto out;
+
+   if (skb_linearize(skb))
+   goto out;
+   if (skb_headlen(skb) < (STMMAC_TEST_PKT_SIZE - ETH_HLEN))
+   goto out;
+
+   ehdr = (struct ethhdr *)skb_mac_header(skb);
+   if (!ether_addr_equal(ehdr->h_dest, tpriv->packet->dst))
+   goto out;
+
+   ihdr = ip_hdr(skb);
+   if (tpriv->double_vlan)
+   ihdr = (struct iphdr *)(skb_network_header(skb) + 4);
+   if (ihdr->protocol != IPPROTO_UDP)
+   goto out;
+
+   uhdr = (struct udphdr *)((u8 *)ihdr + 4 * ihdr->ihl);
+   if (uhdr->dest != htons(tpriv->packet->dport))
+   goto out;
+
+   shdr = (struct stmmachdr *)((u8 *)uhdr + sizeof(*uhdr));
+   if (shdr->magic != cpu_to_be64(STMMAC_TEST_PKT_MAGIC))
+   goto out;
+
+   tpriv->ok = true;
+   complete(>comp);
+
+out:
+   kfree_skb(skb);
+   return 0;
+}
+
+static int stmmac_test_vlanfilt(struct stmmac_priv *priv)
+{
+   struct stmmac_packet_attrs attr = { };
+   struct stmmac_test_priv *tpriv;
+   struct sk_buff *skb = NULL;
+   int ret = 0, i;
+
+   if (!priv->dma_cap.vlhash)
+   return -EOPNOTSUPP;
+
+   tpriv = kzalloc(sizeof(*tpriv), GFP_KERNEL);
+   if (!tpriv)
+   return -ENOMEM;
+
+   tpriv->ok = false;
+   init_completion(>comp);
+
+   tpriv->pt.type = htons(ETH_P_IP);
+   tpriv->pt.func = stmmac_test_vlan_validate;
+   tpriv->pt.dev = priv->dev;
+   tpriv->pt.af_packet_priv = tpriv;
+   tpriv->packet = 
+
+   /*
+* As we use HASH filtering, false positives may appear. This is a
+* specially chosen ID so that adjacent IDs (+4) have different
+* HASH values.
+*/
+   tpriv->vlan_id = 0x123;
+   dev_add_pack(>pt);
+
+   ret = vlan_vid_add(priv->dev, htons(ETH_P_8021Q), tpriv->vlan_id);
+   if (ret)
+   goto cleanup;
+
+   for (i = 0; i < 4; i++) {
+   attr.vlan = 1;
+   attr.vlan_id_out = tpriv->vlan_id + i;
+   attr.dst = priv->dev->dev_addr;
+   attr.sport = 9;
+   attr.dport = 9;
+
+   skb = stmmac_test_get_udp_skb(priv, );
+   if (!skb) {
+   ret = -ENOMEM;
+   goto vlan_del;
+   }
+
+   skb_set_queue_mapping(skb, 0);
+   ret = dev_queue_xmit(skb);
+   if (ret)
+   goto vlan_del;
+
+   wait_for_completion_timeout(>comp, STMMAC_LB_TIMEOUT);
+   ret = !tpriv->ok;
+   if (ret && !i) {
+   goto vlan_del;
+   } else if (!ret && i) {
+   ret = -1;
+   goto vlan_del;
+   } else {
+   ret = 0;
+   }
+
+   tpriv->ok = false;
+   }
+
+vlan_del:
+   vlan_vid_del(priv->dev, htons(ETH_P_8021Q), tpriv->vlan_id);
+cleanup:
+   dev_remove_pack(>pt);
+   kfree(tpriv);
+   return ret;
+}
+
+static int stmmac_test_dvlanfilt(struct stmmac_priv *priv)
+{
+   struct stmmac_packet_attrs attr = { };
+   struct stmmac_test_priv *tpriv;
+   struct sk_buff *skb = NULL;
+   int ret = 0, i;
+
+   if (!priv->dma_cap.vlhash)
+   return -EOPNOTSUPP;
+
+   tpriv = kzalloc(sizeof(*tpriv), GFP_KERNEL);
+   if (!tpriv)
+   return -ENOMEM;
+
+   tpriv->ok = false;
+   tpriv->double_vlan = true;
+   init_completion(>comp);
+
+   

[PATCH net-next v3 00/10] net: stmmac: Improvements for -next

[Jose Abreu]

[ This is just a rebase of v2 into latest -next in order to avoid a merge
conflict ]

Couple of improvements for -next tree. More info in commit logs.

---
Cc: Giuseppe Cavallaro 
Cc: Alexandre Torgue 
Cc: Jose Abreu 
Cc: "David S. Miller" 
Cc: Maxime Coquelin 
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---

Jose Abreu (10):
  net: stmmac: xgmac: Implement MMC counters
  net: stmmac: xgmac: Implement set_mtl_tx_queue_weight()
  net: stmmac: xgmac: Implement tx_queue_prio()
  net: stmmac: Implement RSS and enable it in XGMAC core
  net: stmmac: selftests: Add RSS test
  net: stmmac: Implement VLAN Hash Filtering in XGMAC
  net: stmmac: selftests: Add test for VLAN and Double VLAN Filtering
  net: stmmac: Implement Safety Features in XGMAC core
  net: stmmac: Add Flexible RX Parser support in XGMAC
  net: stmmac: selftests: Add a selftest for Flexible RX Parser

 drivers/net/ethernet/stmicro/stmmac/common.h   |   6 +
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h |  76 ++-
 .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c| 605 -
 .../net/ethernet/stmicro/stmmac/dwxgmac2_descs.c   |  29 +
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c |  10 +
 drivers/net/ethernet/stmicro/stmmac/hwif.c |   4 +-
 drivers/net/ethernet/stmicro/stmmac/hwif.h |  17 +
 drivers/net/ethernet/stmicro/stmmac/mmc.h  |   9 +
 drivers/net/ethernet/stmicro/stmmac/mmc_core.c | 192 +++
 drivers/net/ethernet/stmicro/stmmac/stmmac.h   |  11 +
 .../net/ethernet/stmicro/stmmac/stmmac_ethtool.c   |  81 +++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 120 +++-
 .../net/ethernet/stmicro/stmmac/stmmac_selftests.c | 322 ++-
 include/linux/stmmac.h |   1 +
 14 files changed, 1474 insertions(+), 9 deletions(-)

-- 
2.7.4

[PATCH net-next v3 03/10] net: stmmac: xgmac: Implement tx_queue_prio()

[Jose Abreu]

Implement the TX Queue Priority callback in XGMAC core.

Signed-off-by: Jose Abreu 

---
Cc: Giuseppe Cavallaro 
Cc: Alexandre Torgue 
Cc: Jose Abreu 
Cc: "David S. Miller" 
Cc: Maxime Coquelin 
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h  |  4 
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 19 ++-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h 
b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index 86a42bc39d21..b77091161765 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -127,6 +127,10 @@
 #define XGMAC_MTL_RXQ_DMA_MAP1 0x1034
 #define XGMAC_QxMDMACH(x)  GENMASK((x) * 8 + 3, (x) * 8)
 #define XGMAC_QxMDMACH_SHIFT(x)((x) * 8)
+#define XGMAC_TC_PRTY_MAP0 0x1040
+#define XGMAC_TC_PRTY_MAP1 0x1044
+#define XGMAC_PSTC(x)  GENMASK((x) * 8 + 7, (x) * 8)
+#define XGMAC_PSTC_SHIFT(x)((x) * 8)
 #define XGMAC_MTL_TXQ_OPMODE(x)(0x1100 + (0x80 * (x)))
 #define XGMAC_TQS  GENMASK(25, 16)
 #define XGMAC_TQS_SHIFT16
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c 
b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index ce6503dfc86d..bfbd5ae11540 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
@@ -118,6 +118,23 @@ static void dwxgmac2_rx_queue_prio(struct mac_device_info 
*hw, u32 prio,
writel(value, ioaddr + reg);
 }
 
+static void dwxgmac2_tx_queue_prio(struct mac_device_info *hw, u32 prio,
+  u32 queue)
+{
+   void __iomem *ioaddr = hw->pcsr;
+   u32 value, reg;
+
+   reg = (queue < 4) ? XGMAC_TC_PRTY_MAP0 : XGMAC_TC_PRTY_MAP1;
+   if (queue >= 4)
+   queue -= 4;
+
+   value = readl(ioaddr + reg);
+   value &= ~XGMAC_PSTC(queue);
+   value |= (prio << XGMAC_PSTC_SHIFT(queue)) & XGMAC_PSTC(queue);
+
+   writel(value, ioaddr + reg);
+}
+
 static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,
u32 rx_alg)
 {
@@ -428,7 +445,7 @@ const struct stmmac_ops dwxgmac210_ops = {
.rx_ipc = dwxgmac2_rx_ipc,
.rx_queue_enable = dwxgmac2_rx_queue_enable,
.rx_queue_prio = dwxgmac2_rx_queue_prio,
-   .tx_queue_prio = NULL,
+   .tx_queue_prio = dwxgmac2_tx_queue_prio,
.rx_queue_routing = NULL,
.prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,
.prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,
-- 
2.7.4

Re: [PATCH v4 1/4] RISC-V: Remove per cpu clocksource

[Daniel Lezcano]

On 06/08/2019 23:37, Paul Walmsley wrote:
> On Fri, 2 Aug 2019, Atish Patra wrote:
> 
>> There is only one clocksource in RISC-V. The boot cpu initializes
>> that clocksource. No need to keep a percpu data structure.
>>
>> Signed-off-by: Atish Patra 
> 
> Thanks, queued for v5.3-rc4.

Please, in the future wait for my:

Acked-by: Daniel Lezcano 


-- 
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[PATCH net-next v3 06/10] net: stmmac: Implement VLAN Hash Filtering in XGMAC

[Jose Abreu]

Implement the VLAN Hash Filtering feature in XGMAC core.

Signed-off-by: Jose Abreu 

---
Cc: Giuseppe Cavallaro 
Cc: Alexandre Torgue 
Cc: Jose Abreu 
Cc: "David S. Miller" 
Cc: Maxime Coquelin 
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 drivers/net/ethernet/stmicro/stmmac/common.h   |  1 +
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 10 +++
 .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c| 41 +++
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c |  1 +
 drivers/net/ethernet/stmicro/stmmac/hwif.h |  5 ++
 drivers/net/ethernet/stmicro/stmmac/stmmac.h   |  2 +
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 79 ++
 7 files changed, 139 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h 
b/drivers/net/ethernet/stmicro/stmmac/common.h
index 45a997fe571c..e1e6f67041ec 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -355,6 +355,7 @@ struct dma_features {
unsigned int frpes;
unsigned int addr64;
unsigned int rssen;
+   unsigned int vlhash;
 };
 
 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h 
b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index ed3a85f73a72..bae0b01000cc 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -44,6 +44,7 @@
 #define XGMAC_CORE_INIT_RX 0
 #define XGMAC_PACKET_FILTER0x0008
 #define XGMAC_FILTER_RABIT(31)
+#define XGMAC_FILTER_VTFE  BIT(16)
 #define XGMAC_FILTER_HPF   BIT(10)
 #define XGMAC_FILTER_PCF   BIT(7)
 #define XGMAC_FILTER_PMBIT(4)
@@ -51,6 +52,14 @@
 #define XGMAC_FILTER_PRBIT(0)
 #define XGMAC_HASH_TABLE(x)(0x0010 + (x) * 4)
 #define XGMAC_MAX_HASH_TABLE   8
+#define XGMAC_VLAN_TAG 0x0050
+#define XGMAC_VLAN_EDVLP   BIT(26)
+#define XGMAC_VLAN_VTHMBIT(25)
+#define XGMAC_VLAN_DOVLTC  BIT(20)
+#define XGMAC_VLAN_ESVLBIT(18)
+#define XGMAC_VLAN_ETV BIT(16)
+#define XGMAC_VLAN_VID GENMASK(15, 0)
+#define XGMAC_VLAN_HASH_TABLE  0x0058
 #define XGMAC_RXQ_CTRL00x00a0
 #define XGMAC_RXQEN(x) GENMASK((x) * 2 + 1, (x) * 2)
 #define XGMAC_RXQEN_SHIFT(x)   ((x) * 2)
@@ -87,6 +96,7 @@
 #define XGMAC_HWFEAT_MMCSELBIT(8)
 #define XGMAC_HWFEAT_MGKSELBIT(7)
 #define XGMAC_HWFEAT_RWKSELBIT(6)
+#define XGMAC_HWFEAT_VLHASHBIT(4)
 #define XGMAC_HWFEAT_GMIISEL   BIT(1)
 #define XGMAC_HW_FEATURE1  0x0120
 #define XGMAC_HWFEAT_RSSEN BIT(20)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c 
b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index 04eec85acc59..e2dbebeb59e9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
@@ -490,6 +490,46 @@ static int dwxgmac2_rss_configure(struct mac_device_info 
*hw,
return 0;
 }
 
+static void dwxgmac2_update_vlan_hash(struct mac_device_info *hw, u32 hash,
+ bool is_double)
+{
+   void __iomem *ioaddr = hw->pcsr;
+
+   writel(hash, ioaddr + XGMAC_VLAN_HASH_TABLE);
+
+   if (hash) {
+   u32 value = readl(ioaddr + XGMAC_PACKET_FILTER);
+
+   value |= XGMAC_FILTER_VTFE;
+
+   writel(value, ioaddr + XGMAC_PACKET_FILTER);
+
+   value |= XGMAC_VLAN_VTHM | XGMAC_VLAN_ETV;
+   if (is_double) {
+   value |= XGMAC_VLAN_EDVLP;
+   value |= XGMAC_VLAN_ESVL;
+   value |= XGMAC_VLAN_DOVLTC;
+   }
+
+   writel(value, ioaddr + XGMAC_VLAN_TAG);
+   } else {
+   u32 value = readl(ioaddr + XGMAC_PACKET_FILTER);
+
+   value &= ~XGMAC_FILTER_VTFE;
+
+   writel(value, ioaddr + XGMAC_PACKET_FILTER);
+
+   value = readl(ioaddr + XGMAC_VLAN_TAG);
+
+   value &= ~(XGMAC_VLAN_VTHM | XGMAC_VLAN_ETV);
+   value &= ~(XGMAC_VLAN_EDVLP | XGMAC_VLAN_ESVL);
+   value &= ~XGMAC_VLAN_DOVLTC;
+   value &= ~XGMAC_VLAN_VID;
+
+   writel(value, ioaddr + XGMAC_VLAN_TAG);
+   }
+}
+
 const struct stmmac_ops dwxgmac210_ops = {
.core_init = dwxgmac2_core_init,
.set_mac = dwxgmac2_set_mac,
@@ -521,6 +561,7 @@ const struct stmmac_ops dwxgmac210_ops = {
.set_filter = dwxgmac2_set_filter,
.set_mac_loopback = dwxgmac2_set_mac_loopback,

[PATCH net-next v3 02/10] net: stmmac: xgmac: Implement set_mtl_tx_queue_weight()

[Jose Abreu]

Implement the TX Queue Weight callback. In order for this to be active
we also need to set ETS algorithm when configuring Queue.

Signed-off-by: Jose Abreu 

---
Cc: Giuseppe Cavallaro 
Cc: Alexandre Torgue 
Cc: Jose Abreu 
Cc: "David S. Miller" 
Cc: Maxime Coquelin 
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c| 22 +-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c 
b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index 85c68b7ee8c6..ce6503dfc86d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
@@ -144,7 +144,9 @@ static void dwxgmac2_prog_mtl_tx_algorithms(struct 
mac_device_info *hw,
u32 tx_alg)
 {
void __iomem *ioaddr = hw->pcsr;
+   bool ets = true;
u32 value;
+   int i;
 
value = readl(ioaddr + XGMAC_MTL_OPMODE);
value &= ~XGMAC_ETSALG;
@@ -160,10 +162,28 @@ static void dwxgmac2_prog_mtl_tx_algorithms(struct 
mac_device_info *hw,
value |= XGMAC_DWRR;
break;
default:
+   ets = false;
break;
}
 
writel(value, ioaddr + XGMAC_MTL_OPMODE);
+
+   /* Set ETS if desired */
+   for (i = 0; i < MTL_MAX_TX_QUEUES; i++) {
+   value = readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(i));
+   value &= ~XGMAC_TSA;
+   if (ets)
+   value |= XGMAC_ETS;
+   writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(i));
+   }
+}
+
+static void dwxgmac2_set_mtl_tx_queue_weight(struct mac_device_info *hw,
+u32 weight, u32 queue)
+{
+   void __iomem *ioaddr = hw->pcsr;
+
+   writel(weight, ioaddr + XGMAC_MTL_TCx_QUANTUM_WEIGHT(queue));
 }
 
 static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue,
@@ -412,7 +432,7 @@ const struct stmmac_ops dwxgmac210_ops = {
.rx_queue_routing = NULL,
.prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,
.prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,
-   .set_mtl_tx_queue_weight = NULL,
+   .set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,
.map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,
.config_cbs = dwxgmac2_config_cbs,
.dump_regs = NULL,
-- 
2.7.4

[PATCH net-next v3 10/10] net: stmmac: selftests: Add a selftest for Flexible RX Parser

[Jose Abreu]

Add a selftest for the Flexible RX Parser feature.

Signed-off-by: Jose Abreu 

---
Cc: Giuseppe Cavallaro 
Cc: Alexandre Torgue 
Cc: Jose Abreu 
Cc: "David S. Miller" 
Cc: Maxime Coquelin 
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 .../net/ethernet/stmicro/stmmac/stmmac_selftests.c | 98 +-
 1 file changed, 97 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c
index 6b08bb15af15..abab84f2ef8b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c
@@ -11,8 +11,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
 #include "stmmac.h"
 
 struct stmmachdr {
@@ -229,7 +231,7 @@ static int stmmac_test_loopback_validate(struct sk_buff 
*skb,
goto out;
}
if (tpriv->packet->src) {
-   if (!ether_addr_equal(ehdr->h_source, orig_ndev->dev_addr))
+   if (!ether_addr_equal(ehdr->h_source, tpriv->packet->src))
goto out;
}
 
@@ -912,6 +914,96 @@ static int stmmac_test_dvlanfilt(struct stmmac_priv *priv)
return ret;
 }
 
+#ifdef CONFIG_NET_CLS_ACT
+static int stmmac_test_rxp(struct stmmac_priv *priv)
+{
+   unsigned char addr[ETH_ALEN] = {0xde, 0xad, 0xbe, 0xef, 0x00, 0x00};
+   struct tc_cls_u32_offload cls_u32 = { };
+   struct stmmac_packet_attrs attr = { };
+   struct tc_action **actions, *act;
+   struct tc_u32_sel *sel;
+   struct tcf_exts *exts;
+   int ret, i, nk = 1;
+
+   if (!tc_can_offload(priv->dev))
+   return -EOPNOTSUPP;
+   if (!priv->dma_cap.frpsel)
+   return -EOPNOTSUPP;
+
+   sel = kzalloc(sizeof(*sel) + nk * sizeof(struct tc_u32_key), 
GFP_KERNEL);
+   if (!sel)
+   return -ENOMEM;
+
+   exts = kzalloc(sizeof(*exts), GFP_KERNEL);
+   if (!exts) {
+   ret = -ENOMEM;
+   goto cleanup_sel;
+   }
+
+   actions = kzalloc(nk * sizeof(*actions), GFP_KERNEL);
+   if (!actions) {
+   ret = -ENOMEM;
+   goto cleanup_exts;
+   }
+
+   act = kzalloc(nk * sizeof(*act), GFP_KERNEL);
+   if (!act) {
+   ret = -ENOMEM;
+   goto cleanup_actions;
+   }
+
+   cls_u32.command = TC_CLSU32_NEW_KNODE;
+   cls_u32.common.chain_index = 0;
+   cls_u32.common.protocol = htons(ETH_P_ALL);
+   cls_u32.knode.exts = exts;
+   cls_u32.knode.sel = sel;
+   cls_u32.knode.handle = 0x123;
+
+   exts->nr_actions = nk;
+   exts->actions = actions;
+   for (i = 0; i < nk; i++) {
+   struct tcf_gact *gact = to_gact([i]);
+
+   actions[i] = [i];
+   gact->tcf_action = TC_ACT_SHOT;
+   }
+
+   sel->nkeys = nk;
+   sel->offshift = 0;
+   sel->keys[0].off = 6;
+   sel->keys[0].val = htonl(0xdeadbeef);
+   sel->keys[0].mask = ~0x0;
+
+   ret = stmmac_tc_setup_cls_u32(priv, priv, _u32);
+   if (ret)
+   goto cleanup_act;
+
+   attr.dst = priv->dev->dev_addr;
+   attr.src = addr;
+
+   ret = __stmmac_test_loopback(priv, );
+   ret = !ret; /* Shall NOT receive packet */
+
+   cls_u32.command = TC_CLSU32_DELETE_KNODE;
+   stmmac_tc_setup_cls_u32(priv, priv, _u32);
+
+cleanup_act:
+   kfree(act);
+cleanup_actions:
+   kfree(actions);
+cleanup_exts:
+   kfree(exts);
+cleanup_sel:
+   kfree(sel);
+   return ret;
+}
+#else
+static int stmmac_test_rxp(struct stmmac_priv *priv)
+{
+   return -EOPNOTSUPP;
+}
+#endif
+
 #define STMMAC_LOOPBACK_NONE   0
 #define STMMAC_LOOPBACK_MAC1
 #define STMMAC_LOOPBACK_PHY2
@@ -969,6 +1061,10 @@ static const struct stmmac_test {
.name = "Double VLAN Filtering",
.lb = STMMAC_LOOPBACK_PHY,
.fn = stmmac_test_dvlanfilt,
+   }, {
+   .name = "Flexible RX Parser   ",
+   .lb = STMMAC_LOOPBACK_PHY,
+   .fn = stmmac_test_rxp,
},
 };
 
-- 
2.7.4

[PATCH net-next v3 01/10] net: stmmac: xgmac: Implement MMC counters

[Jose Abreu]

Implement the MMC counters feature in XGMAC core.

Signed-off-by: Jose Abreu 

---
Cc: Giuseppe Cavallaro 
Cc: Alexandre Torgue 
Cc: Jose Abreu 
Cc: "David S. Miller" 
Cc: Maxime Coquelin 
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h |   1 +
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c |   1 +
 drivers/net/ethernet/stmicro/stmmac/hwif.c |   4 +-
 drivers/net/ethernet/stmicro/stmmac/hwif.h |   1 +
 drivers/net/ethernet/stmicro/stmmac/mmc.h  |   9 +
 drivers/net/ethernet/stmicro/stmmac/mmc_core.c | 192 +
 .../net/ethernet/stmicro/stmmac/stmmac_ethtool.c   |   6 +
 7 files changed, 212 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h 
b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index 3174b701aa90..86a42bc39d21 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -84,6 +84,7 @@
 #define XGMAC_HWFEAT_AVSEL BIT(11)
 #define XGMAC_HWFEAT_RAVSELBIT(10)
 #define XGMAC_HWFEAT_ARPOFFSEL BIT(9)
+#define XGMAC_HWFEAT_MMCSELBIT(8)
 #define XGMAC_HWFEAT_MGKSELBIT(7)
 #define XGMAC_HWFEAT_RWKSELBIT(6)
 #define XGMAC_HWFEAT_GMIISEL   BIT(1)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c 
b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index a4f236e3593e..0f1c772e892a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
@@ -356,6 +356,7 @@ static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
dma_cap->av &= (hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10;
+   dma_cap->rmon = (hw_cap & XGMAC_HWFEAT_MMCSEL) >> 8;
dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c 
b/drivers/net/ethernet/stmicro/stmmac/hwif.c
index 6c61b753b55e..3af2e5015245 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
@@ -201,7 +201,7 @@ static const struct stmmac_hwif_entry {
.min_id = DWXGMAC_CORE_2_10,
.regs = {
.ptp_off = PTP_XGMAC_OFFSET,
-   .mmc_off = 0,
+   .mmc_off = MMC_XGMAC_OFFSET,
},
.desc = _desc_ops,
.dma = _dma_ops,
@@ -209,7 +209,7 @@ static const struct stmmac_hwif_entry {
.hwtimestamp = _ptp,
.mode = NULL,
.tc = _tc_ops,
-   .mmc = NULL,
+   .mmc = _mmc_ops,
.setup = dwxgmac2_setup,
.quirks = NULL,
},
diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h 
b/drivers/net/ethernet/stmicro/stmmac/hwif.h
index 278c0dbec9d9..00539a09d1db 100644
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.h
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h
@@ -503,6 +503,7 @@ extern const struct stmmac_ops dwxgmac210_ops;
 extern const struct stmmac_dma_ops dwxgmac210_dma_ops;
 extern const struct stmmac_desc_ops dwxgmac210_desc_ops;
 extern const struct stmmac_mmc_ops dwmac_mmc_ops;
+extern const struct stmmac_mmc_ops dwxgmac_mmc_ops;
 
 #define GMAC_VERSION   0x0020  /* GMAC CORE Version */
 #define GMAC4_VERSION  0x0110  /* GMAC4+ CORE Version */
diff --git a/drivers/net/ethernet/stmicro/stmmac/mmc.h 
b/drivers/net/ethernet/stmicro/stmmac/mmc.h
index 3587ceb9faf5..a0c05925883e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/mmc.h
+++ b/drivers/net/ethernet/stmicro/stmmac/mmc.h
@@ -24,6 +24,7 @@
 
 #define MMC_GMAC4_OFFSET   0x700
 #define MMC_GMAC3_X_OFFSET 0x100
+#define MMC_XGMAC_OFFSET   0x800
 
 struct stmmac_counters {
unsigned int mmc_tx_octetcount_gb;
@@ -116,6 +117,14 @@ struct stmmac_counters {
unsigned int mmc_rx_tcp_err_octets;
unsigned int mmc_rx_icmp_gd_octets;
unsigned int mmc_rx_icmp_err_octets;
+
+   /* FPE */
+   unsigned int mmc_tx_fpe_fragment_cntr;
+   unsigned int mmc_tx_hold_req_cntr;
+   unsigned int mmc_rx_packet_assembly_err_cntr;
+   unsigned int mmc_rx_packet_smd_err_cntr;
+   unsigned int mmc_rx_packet_assembly_ok_cntr;
+   unsigned int mmc_rx_fpe_fragment_cntr;
 };
 
 #endif /* __MMC_H__ */
diff --git a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c 
b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
index a471db6d7b11..a223584f5f9a 100644
--- 

[PATCH net-next v3 08/10] net: stmmac: Implement Safety Features in XGMAC core

[Jose Abreu]

XGMAC also supports Safety Features. This patch implements the
configuration and handling of this feature in XGMAC core.

Signed-off-by: Jose Abreu 

---
Cc: Giuseppe Cavallaro 
Cc: Alexandre Torgue 
Cc: Jose Abreu 
Cc: "David S. Miller" 
Cc: Maxime Coquelin 
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h |  26 ++
 .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c| 281 +
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c |   4 +
 3 files changed, 311 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h 
b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index bae0b01000cc..34a53f2141dc 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -110,6 +110,12 @@
 #define XGMAC_HWFEAT_RXCHCNT   GENMASK(15, 12)
 #define XGMAC_HWFEAT_TXQCNTGENMASK(9, 6)
 #define XGMAC_HWFEAT_RXQCNTGENMASK(3, 0)
+#define XGMAC_HW_FEATURE3  0x0128
+#define XGMAC_HWFEAT_ASP   GENMASK(15, 14)
+#define XGMAC_MAC_DPP_FSM_INT_STATUS   0x0150
+#define XGMAC_MAC_FSM_CONTROL  0x0158
+#define XGMAC_PRTYEN   BIT(1)
+#define XGMAC_TMOUTEN  BIT(0)
 #define XGMAC_MDIO_ADDR0x0200
 #define XGMAC_MDIO_DATA0x0204
 #define XGMAC_MDIO_C22P0x0220
@@ -154,6 +160,16 @@
 #define XGMAC_TC_PRTY_MAP1 0x1044
 #define XGMAC_PSTC(x)  GENMASK((x) * 8 + 7, (x) * 8)
 #define XGMAC_PSTC_SHIFT(x)((x) * 8)
+#define XGMAC_MTL_ECC_CONTROL  0x10c0
+#define XGMAC_MTL_SAFETY_INT_STATUS0x10c4
+#define XGMAC_MEUISBIT(1)
+#define XGMAC_MECISBIT(0)
+#define XGMAC_MTL_ECC_INT_ENABLE   0x10c8
+#define XGMAC_RPCEIE   BIT(12)
+#define XGMAC_ECEIEBIT(8)
+#define XGMAC_RXCEIE   BIT(4)
+#define XGMAC_TXCEIE   BIT(0)
+#define XGMAC_MTL_ECC_INT_STATUS   0x10cc
 #define XGMAC_MTL_TXQ_OPMODE(x)(0x1100 + (0x80 * (x)))
 #define XGMAC_TQS  GENMASK(25, 16)
 #define XGMAC_TQS_SHIFT16
@@ -218,6 +234,16 @@
 #define XGMAC_TDPS GENMASK(29, 0)
 #define XGMAC_RX_EDMA_CTRL 0x3044
 #define XGMAC_RDPS GENMASK(29, 0)
+#define XGMAC_DMA_SAFETY_INT_STATUS0x3064
+#define XGMAC_MCSISBIT(31)
+#define XGMAC_MSUISBIT(29)
+#define XGMAC_MSCISBIT(28)
+#define XGMAC_DEUISBIT(1)
+#define XGMAC_DECISBIT(0)
+#define XGMAC_DMA_ECC_INT_ENABLE   0x3068
+#define XGMAC_DCEIEBIT(1)
+#define XGMAC_TCEIEBIT(0)
+#define XGMAC_DMA_ECC_INT_STATUS   0x306c
 #define XGMAC_DMA_CH_CONTROL(x)(0x3100 + (0x80 * (x)))
 #define XGMAC_PBLx8BIT(16)
 #define XGMAC_DMA_CH_TX_CONTROL(x) (0x3104 + (0x80 * (x)))
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c 
b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index e2dbebeb59e9..19dfb72cab11 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
@@ -530,6 +530,284 @@ static void dwxgmac2_update_vlan_hash(struct 
mac_device_info *hw, u32 hash,
}
 }
 
+struct dwxgmac3_error_desc {
+   bool valid;
+   const char *desc;
+   const char *detailed_desc;
+};
+
+#define STAT_OFF(field)offsetof(struct stmmac_safety_stats, 
field)
+
+static void dwxgmac3_log_error(struct net_device *ndev, u32 value, bool corr,
+  const char *module_name,
+  const struct dwxgmac3_error_desc *desc,
+  unsigned long field_offset,
+  struct stmmac_safety_stats *stats)
+{
+   unsigned long loc, mask;
+   u8 *bptr = (u8 *)stats;
+   unsigned long *ptr;
+
+   ptr = (unsigned long *)(bptr + field_offset);
+
+   mask = value;
+   for_each_set_bit(loc, , 32) {
+   netdev_err(ndev, "Found %s error in %s: '%s: %s'\n", corr ?
+   "correctable" : "uncorrectable", module_name,
+   desc[loc].desc, desc[loc].detailed_desc);
+
+   /* Update counters */
+   ptr[loc]++;
+   }
+}
+
+static const struct dwxgmac3_error_desc dwxgmac3_mac_errors[32]= {
+   { true, "ATPES", "Application Transmit Interface Parity Check Error" },
+   { true, "DPES", "Descriptor Cache Data Path Parity Check Error" },
+   { true, "TPES", "TSO Data 

[PATCH net-next v3 04/10] net: stmmac: Implement RSS and enable it in XGMAC core

[Jose Abreu]

Implement the RSS functionality and add the corresponding callbacks in
XGMAC core.

Changes from v1:
- Do not use magic constants (Jakub)
- Use ethtool_rxfh_indir_default() (Jakub)

Signed-off-by: Jose Abreu 

---
Cc: Giuseppe Cavallaro 
Cc: Alexandre Torgue 
Cc: Jose Abreu 
Cc: "David S. Miller" 
Cc: Maxime Coquelin 
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: Jakub Kicinski 
---
 drivers/net/ethernet/stmicro/stmmac/common.h   |  5 ++
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 22 ++-
 .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c| 52 +++
 .../net/ethernet/stmicro/stmmac/dwxgmac2_descs.c   | 29 +
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c |  1 +
 drivers/net/ethernet/stmicro/stmmac/hwif.h | 11 
 drivers/net/ethernet/stmicro/stmmac/stmmac.h   |  9 +++
 .../net/ethernet/stmicro/stmmac/stmmac_ethtool.c   | 75 ++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 41 +++-
 include/linux/stmmac.h |  1 +
 10 files changed, 242 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h 
b/drivers/net/ethernet/stmicro/stmmac/common.h
index ed872eed1cab..45a997fe571c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -354,6 +354,7 @@ struct dma_features {
unsigned int frpbs;
unsigned int frpes;
unsigned int addr64;
+   unsigned int rssen;
 };
 
 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
@@ -381,6 +382,10 @@ struct dma_features {
 
 #define JUMBO_LEN  9000
 
+/* Receive Side Scaling */
+#define STMMAC_RSS_HASH_KEY_SIZE   40
+#define STMMAC_RSS_MAX_TABLE_SIZE  256
+
 extern const struct stmmac_desc_ops enh_desc_ops;
 extern const struct stmmac_desc_ops ndesc_ops;
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h 
b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index b77091161765..ed3a85f73a72 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -89,6 +89,7 @@
 #define XGMAC_HWFEAT_RWKSELBIT(6)
 #define XGMAC_HWFEAT_GMIISEL   BIT(1)
 #define XGMAC_HW_FEATURE1  0x0120
+#define XGMAC_HWFEAT_RSSEN BIT(20)
 #define XGMAC_HWFEAT_TSOEN BIT(18)
 #define XGMAC_HWFEAT_ADDR64GENMASK(15, 14)
 #define XGMAC_HWFEAT_TXFIFOSIZEGENMASK(10, 6)
@@ -109,6 +110,17 @@
 #define XGMAC_DCS_SHIFT16
 #define XGMAC_ADDRx_LOW(x) (0x0304 + (x) * 0x8)
 #define XGMAC_ARP_ADDR 0x0c10
+#define XGMAC_RSS_CTRL 0x0c80
+#define XGMAC_UDP4TE   BIT(3)
+#define XGMAC_TCP4TE   BIT(2)
+#define XGMAC_IP2TEBIT(1)
+#define XGMAC_RSSE BIT(0)
+#define XGMAC_RSS_ADDR 0x0c88
+#define XGMAC_RSSIA_SHIFT  8
+#define XGMAC_ADDRTBIT(2)
+#define XGMAC_CT   BIT(1)
+#define XGMAC_OB   BIT(0)
+#define XGMAC_RSS_DATA 0x0c8c
 #define XGMAC_TIMESTAMP_STATUS 0x0d20
 #define XGMAC_TXTSCBIT(15)
 #define XGMAC_TXTIMESTAMP_NSEC 0x0d30
@@ -125,8 +137,9 @@
 #define XGMAC_MTL_INT_STATUS   0x1020
 #define XGMAC_MTL_RXQ_DMA_MAP0 0x1030
 #define XGMAC_MTL_RXQ_DMA_MAP1 0x1034
-#define XGMAC_QxMDMACH(x)  GENMASK((x) * 8 + 3, (x) * 8)
+#define XGMAC_QxMDMACH(x)  GENMASK((x) * 8 + 7, (x) * 8)
 #define XGMAC_QxMDMACH_SHIFT(x)((x) * 8)
+#define XGMAC_QDDMACH  BIT(7)
 #define XGMAC_TC_PRTY_MAP0 0x1040
 #define XGMAC_TC_PRTY_MAP1 0x1044
 #define XGMAC_PSTC(x)  GENMASK((x) * 8 + 7, (x) * 8)
@@ -261,6 +274,13 @@
 #define XGMAC_RDES3_IOCBIT(30)
 #define XGMAC_RDES3_LD BIT(28)
 #define XGMAC_RDES3_CDABIT(27)
+#define XGMAC_RDES3_RSVBIT(26)
+#define XGMAC_RDES3_L34T   GENMASK(23, 20)
+#define XGMAC_RDES3_L34T_SHIFT 20
+#define XGMAC_L34T_IP4TCP  0x1
+#define XGMAC_L34T_IP4UDP  0x2
+#define XGMAC_L34T_IP6TCP  0x9
+#define XGMAC_L34T_IP6UDP  0xA
 #define XGMAC_RDES3_ES BIT(15)
 #define XGMAC_RDES3_PL GENMASK(13, 0)
 #define XGMAC_RDES3_TSDBIT(6)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c 
b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index bfbd5ae11540..04eec85acc59 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ 

[PATCH net-next v3 09/10] net: stmmac: Add Flexible RX Parser support in XGMAC

[Jose Abreu]

XGMAC cores also support the Flexible RX Parser feature. Add the support
for it in the XGMAC core.

Signed-off-by: Jose Abreu 

---
Cc: Giuseppe Cavallaro 
Cc: Alexandre Torgue 
Cc: Jose Abreu 
Cc: "David S. Miller" 
Cc: Maxime Coquelin 
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h |  13 ++
 .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c| 190 +
 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c |   3 +
 3 files changed, 206 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h 
b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index 34a53f2141dc..429c94e40c73 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -112,6 +112,9 @@
 #define XGMAC_HWFEAT_RXQCNTGENMASK(3, 0)
 #define XGMAC_HW_FEATURE3  0x0128
 #define XGMAC_HWFEAT_ASP   GENMASK(15, 14)
+#define XGMAC_HWFEAT_FRPES GENMASK(12, 11)
+#define XGMAC_HWFEAT_FRPPB GENMASK(10, 9)
+#define XGMAC_HWFEAT_FRPSELBIT(3)
 #define XGMAC_MAC_DPP_FSM_INT_STATUS   0x0150
 #define XGMAC_MAC_FSM_CONTROL  0x0158
 #define XGMAC_PRTYEN   BIT(1)
@@ -145,6 +148,7 @@
 
 /* MTL Registers */
 #define XGMAC_MTL_OPMODE   0x1000
+#define XGMAC_FRPE BIT(15)
 #define XGMAC_ETSALG   GENMASK(6, 5)
 #define XGMAC_WRR  (0x0 << 5)
 #define XGMAC_WFQ  (0x1 << 5)
@@ -160,6 +164,15 @@
 #define XGMAC_TC_PRTY_MAP1 0x1044
 #define XGMAC_PSTC(x)  GENMASK((x) * 8 + 7, (x) * 8)
 #define XGMAC_PSTC_SHIFT(x)((x) * 8)
+#define XGMAC_MTL_RXP_CONTROL_STATUS   0x10a0
+#define XGMAC_RXPI BIT(31)
+#define XGMAC_NPE  GENMASK(23, 16)
+#define XGMAC_NVE  GENMASK(7, 0)
+#define XGMAC_MTL_RXP_IACC_CTRL_ST 0x10b0
+#define XGMAC_STARTBUSYBIT(31)
+#define XGMAC_WRRDNBIT(16)
+#define XGMAC_ADDR GENMASK(9, 0)
+#define XGMAC_MTL_RXP_IACC_DATA0x10b4
 #define XGMAC_MTL_ECC_CONTROL  0x10c0
 #define XGMAC_MTL_SAFETY_INT_STATUS0x10c4
 #define XGMAC_MEUISBIT(1)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c 
b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index 19dfb72cab11..767f3fe5efaa 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
@@ -808,6 +808,195 @@ static int dwxgmac3_safety_feat_dump(struct 
stmmac_safety_stats *stats,
return 0;
 }
 
+static int dwxgmac3_rxp_disable(void __iomem *ioaddr)
+{
+   u32 val = readl(ioaddr + XGMAC_MTL_OPMODE);
+
+   val &= ~XGMAC_FRPE;
+   writel(val, ioaddr + XGMAC_MTL_OPMODE);
+
+   return 0;
+}
+
+static void dwxgmac3_rxp_enable(void __iomem *ioaddr)
+{
+   u32 val;
+
+   val = readl(ioaddr + XGMAC_MTL_OPMODE);
+   val |= XGMAC_FRPE;
+   writel(val, ioaddr + XGMAC_MTL_OPMODE);
+}
+
+static int dwxgmac3_rxp_update_single_entry(void __iomem *ioaddr,
+   struct stmmac_tc_entry *entry,
+   int pos)
+{
+   int ret, i;
+
+   for (i = 0; i < (sizeof(entry->val) / sizeof(u32)); i++) {
+   int real_pos = pos * (sizeof(entry->val) / sizeof(u32)) + i;
+   u32 val;
+
+   /* Wait for ready */
+   ret = readl_poll_timeout(ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST,
+val, !(val & XGMAC_STARTBUSY), 1, 
1);
+   if (ret)
+   return ret;
+
+   /* Write data */
+   val = *((u32 *)>val + i);
+   writel(val, ioaddr + XGMAC_MTL_RXP_IACC_DATA);
+
+   /* Write pos */
+   val = real_pos & XGMAC_ADDR;
+   writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
+
+   /* Write OP */
+   val |= XGMAC_WRRDN;
+   writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
+
+   /* Start Write */
+   val |= XGMAC_STARTBUSY;
+   writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
+
+   /* Wait for done */
+   ret = readl_poll_timeout(ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST,
+val, !(val & XGMAC_STARTBUSY), 1, 
1);
+   if (ret)
+   return ret;
+   }
+
+   return 0;
+}
+
+static struct stmmac_tc_entry *
+dwxgmac3_rxp_get_next_entry(struct stmmac_tc_entry *entries,
+   unsigned int count, u32 curr_prio)
+{
+   struct stmmac_tc_entry 

Re: [PATCH 1/2] kbuild: add OBJSIZE variable for the size tool

[Vasily Gorbik]

On Wed, Aug 07, 2019 at 11:32:04AM +0900, Masahiro Yamada wrote:
> Hi.
> 
> On Tue, Aug 6, 2019 at 7:56 PM Vasily Gorbik  wrote:
> >
> > Define and export OBJSIZE variable for "size" tool from binutils to be
> > used in architecture specific Makefiles (naming the variable just "SIZE"
> > would be too risky). In particular this tool is useful to perform checks
> > that early boot code is not using bss section (which might have not been
> > zeroed yet or intersects with initrd or other files boot loader might
> > have put right after the linux kernel).
> >
> > Signed-off-by: Vasily Gorbik 
> 
> I think you want to apply both to the s390 tree. If so,
> 
> Acked-by: Masahiro Yamada 
> 
> Thanks.

Yes, I would take it via s390 tree. Thank you!

Re: [PATCH] tty: serial: Introduce uart_tx_stoppped_or_empty()

[Andy Shevchenko]

On Wed, Aug 7, 2019 at 4:20 AM Andrey Smirnov  wrote:
> On Mon, Aug 5, 2019 at 11:48 PM Andy Shevchenko
>  wrote:
> > On Mon, Aug 5, 2019 at 10:36 PM Andrey Smirnov  
> > wrote:

> > > The vast majority of the serial drivers check for
> > >
> > > uart_tx_stopped(>port) || uart_circ_empty(xmit)
> > >
> > > condition one or more times. Create a dedicated helper function and
> > > convert drivers to use it.
> >
> > Sometimes the arguments are swapped. It means that in case of first
> > being false the second is aslo going to be checked.
> > So, does ordering have any side effect?
> >
> > Please, elaborate this in the commit message.
> >
>
> Neither  uart_tx_stopped() nor uart_circ_empty() should have any side
> effects. I also didn't see any comments indicating that ordering is
> important. Is that enough of a justification?

The problem here is the word 'should' which implies the doubt.
Can you simple check this and elaborate in the commit message, like
"foo() checks X while bar() checks Y which are orthogonal to each
other and thus have no side effect on ordering"?

If it's not the case (for example, one of them does something under
lock, while the other is not, or barriers are in place) then we need
to keep ordering as in the original cases.

(Personally I believe there is no ordering issues, though I didn't
check this to be sure)

> > >  drivers/tty/serial/8250/8250_dma.c  |  2 +-
> > >  drivers/tty/serial/8250/8250_omap.c |  7 +++
> > >  drivers/tty/serial/sc16is7xx.c  |  2 +-
> >
> > For the drivers I care about (see above) I prefer to see conversion on
> > per driver basis. Of course, if Greg is okay with the current, I won't
> > object.
>
> I am more than happy to split this any way necessary.

Perhaps the best approach is to introduce a helper (patch 1) and do
few conversions as examples (patches 2-...), probably the ones that
reduce amount of lines.

> > > -   if (uart_tx_stopped(>port) ||
> > > -   uart_circ_empty(>port.state->xmit)) {
> > > +   if (uart_tx_stopped_or_empty(>port)) {
> >
> > Yes, it becomes one line, but...
> >
> > > -   if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(>port) ||
> > > -   uart_circ_empty(>port.state->xmit)) {
> > > +   if (!(dmacr & UART011_TXDMAE) ||
> > > +   uart_tx_stopped_or_empty(>port)) {
> >
> > ...wouldn't be the case here as well? And perhaps in other places?
>
> Hmm, not sure I am reading this comment right. Are we talking purely
> about formatting here? If we are, yeah, I probably can make this into
> a single line.

Yes, it's about pure style (also consider in some cases it's better to
have ~83 character line than split).

> Not sure if there any other places like that,
> sirfsoc_uart.c perhaps?

Maybe, above is the fist of which my eye is stumbled.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 06/16] net: phy: adin: support PHY mode converters

[Ardelean, Alexandru]

On Tue, 2019-08-06 at 17:39 +0200, Andrew Lunn wrote:
> [External]
> 
> On Tue, Aug 06, 2019 at 06:47:08AM +, Ardelean, Alexandru wrote:
> > On Mon, 2019-08-05 at 16:51 +0200, Andrew Lunn wrote:
> > > [External]
> > > 
> > > On Mon, Aug 05, 2019 at 07:54:43PM +0300, Alexandru Ardelean wrote:
> > > > Sometimes, the connection between a MAC and PHY is done via a
> > > > mode/interface converter. An example is a GMII-to-RGMII converter, which
> > > > would mean that the MAC operates in GMII mode while the PHY operates in
> > > > RGMII. In this case there is a discrepancy between what the MAC expects 
> > > > &
> > > > what the PHY expects and both need to be configured in their respective
> > > > modes.
> > > > 
> > > > Sometimes, this converter is specified via a board/system configuration 
> > > > (in
> > > > the device-tree for example). But, other times it can be left 
> > > > unspecified.
> > > > The use of these converters is common in boards that have FPGA on them.
> > > > 
> > > > This patch also adds support for a `adi,phy-mode-internal` property that
> > > > can be used in these (implicit convert) cases. The internal PHY mode 
> > > > will
> > > > be used to specify the correct register settings for the PHY.
> > > > 
> > > > `fwnode_handle` is used, since this property may be specified via ACPI 
> > > > as
> > > > well in other setups, but testing has been done in DT context.
> > > 
> > > Looking at the patch, you seems to assume phy-mode is what the MAC is
> > > using? That seems rather odd, given the name. It seems like a better
> > > solution would be to add a mac-mode, which the MAC uses to configure
> > > its side of the link. The MAC driver would then implement this
> > > property.
> > > 
> > 
> > actually, that's a pretty good idea;
> > i guess i was narrow-minded when writing the driver, and got stuck on phy 
> > specifics, and forgot about the MAC-side;
> > [ i also catch these design elements when reviewing, but i also seem to 
> > miss them when writing stuff sometimes ]
> > 
> 
> Hi Ardelean
> 
> We should also consider the media converter itself. It is passive, or
> does it need a driver. You seems to be considering GMII-to-RGMII. But
> what about RGMII to SGMII? or RGMII to 1000Base-KX etc? Ideally we
> want a generic solution and we need to think about all the parts in
> the system.

In our case the GMII-to-RGMII converter is passive and does not need a driver.
It's an HDL/FPGA block.
There may be other converters that do need a driver.
To be honest, the multitude of possible configurations [given that it's FPGA] 
can be... a lot.

In one of our cases, specifying the MAC mode to be different than PHY mode 
[which assumes that there is an implicit
passive media converter in-between] works.

I admit that a generic solution would be nice.
Is it ok if we defer the solution for this drivers/patchset?

If you propose something, I can take a look as part of a different/new 
discussion.

No guarrantees about how soon it would be implemented.

Thanks
Alex

> 
>  Andrew

linux-next: build warning after merge of the akpm-current tree

[Stephen Rothwell]

Hi all,

After merging the akpm-current tree, today's linux-next build (x86_64
allmodconfig) failed like this:

In file included from include/linux/bits.h:22,
 from arch/x86/include/asm/msr-index.h:5,
 from arch/x86/boot/cpucheck.c:28:
include/linux/build_bug.h:49: warning: "BUILD_BUG_ON" redefined
 #define BUILD_BUG_ON(condition) \
 
In file included from arch/x86/boot/cpucheck.c:22:
arch/x86/boot/boot.h:31: note: this is the location of the previous definition
 #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))

Caused by commit

  d72f2a993607 ("linux/bits.h: add compile time sanity check of GENMASK inputs")

-- 
Cheers,
Stephen Rothwell


pgplHaF4AYS3z.pgp
Description: OpenPGP digital signature

Re: Let's talk about the elephant in the room - the Linux kernel's inability to gracefully handle low memory pressure

[Michal Hocko]

On Tue 06-08-19 18:01:50, Johannes Weiner wrote:
> On Tue, Aug 06, 2019 at 09:27:05AM -0700, Suren Baghdasaryan wrote:
[...]
> > > > I'm not sure 10s is the perfect value here, but I do think the kernel
> > > > should try to get out of such a state, where interacting with the
> > > > system is impossible, within a reasonable amount of time.
> > > >
> > > > It could be a little too short for non-interactive number-crunching
> > > > systems...
> > >
> > > Would it be possible to have a module with tunning knobs as parameters
> > > and hook into the PSI infrastructure? People can play with the setting
> > > to their need, we wouldn't really have think about the user visible API
> > > for the tuning and this could be easily adopted as an opt-in mechanism
> > > without a risk of regressions.
> 
> It's relatively easy to trigger a livelock that disables the entire
> system for good, as a regular user. It's a little weird to make the
> bug fix for that an opt-in with an extensive configuration interface.

Yes, I definitely do agree that this is a bug fix more than a
feature. The thing is that we do not know what the proper default is for
a wide variety of workloads so some way of configurability is needed
(level and period).  If making this a module would require a lot of
additional code then we need a kernel command line parameter at least.

A module would have a nice advantage that you can change your
configuration without rebooting. The same can be achieved by a sysfs on
the other hand.
-- 
Michal Hocko
SUSE Labs

Re: [LKP] [SUNRPC] 0472e47660: fsmark.app_overhead 16.0% regression

[Xing Zhengjun]

On 7/24/2019 1:17 PM, Xing Zhengjun wrote:



On 7/12/2019 2:42 PM, Xing Zhengjun wrote:

Hi Trond,

 I attached perf-profile part big changes, hope it is useful for 
analyzing the issue.


Ping...


ping...






In testcase: fsmark
on test machine: 40 threads Intel(R) Xeon(R) CPU E5-2690 v2 @ 3.00GHz 
with 384G memory

with following parameters:

 iterations: 20x
 nr_threads: 64t
 disk: 1BRD_48G
 fs: xfs
 fs2: nfsv4
 filesize: 4M
 test_size: 80G
 sync_method: fsyncBeforeClose
 cpufreq_governor: performance

test-description: The fsmark is a file system benchmark to test 
synchronous write workloads, for example, mail servers workload.

test-url: https://sourceforge.net/projects/fsmark/

commit:
   e791f8e938 ("SUNRPC: Convert xs_send_kvec() to use iov_iter_kvec()")
   0472e47660 ("SUNRPC: Convert socket page send code to use iov_iter()")

e791f8e9380d945e 0472e476604998c127f3c80d291
 ---
  %stddev %change %stddev
  \  |    \
 527.29   -22.6% 407.96    fsmark.files_per_sec
   1.97 ± 11%  +0.9    2.88 ±  4% 
perf-profile.calltrace.cycles-pp.smp_apic_timer_interrupt.apic_timer_interrupt.cpuidle_enter_state.do_idle.cpu_startup_entry 

   0.00    +0.9    0.93 ±  4% 
perf-profile.calltrace.cycles-pp.tcp_write_xmit.tcp_sendmsg_locked.tcp_sendmsg.sock_sendmsg.xs_sendpages 

   2.11 ± 10%  +0.9    3.05 ±  4% 
perf-profile.calltrace.cycles-pp.apic_timer_interrupt.cpuidle_enter_state.do_idle.cpu_startup_entry.start_secondary 

   5.29 ±  2%  +1.2    6.46 ±  7% 
perf-profile.calltrace.cycles-pp.svc_recv.nfsd.kthread.ret_from_fork
   9.61 ±  5%  +3.1   12.70 ±  2% 
perf-profile.calltrace.cycles-pp.worker_thread.kthread.ret_from_fork
   9.27 ±  5%  +3.1   12.40 ±  2% 
perf-profile.calltrace.cycles-pp.process_one_work.worker_thread.kthread.ret_from_fork 

  34.52 ±  4%  +3.3   37.78 ±  2% 
perf-profile.calltrace.cycles-pp.ret_from_fork
  34.52 ±  4%  +3.3   37.78 ±  2% 
perf-profile.calltrace.cycles-pp.kthread.ret_from_fork
   0.00    +3.4    3.41 ±  4% 
perf-profile.calltrace.cycles-pp.memcpy_erms.memcpy_from_page._copy_from_iter_full.tcp_sendmsg_locked.tcp_sendmsg 

   0.00    +3.4    3.44 ±  4% 
perf-profile.calltrace.cycles-pp.memcpy_from_page._copy_from_iter_full.tcp_sendmsg_locked.tcp_sendmsg.sock_sendmsg 

   0.00    +3.5    3.54 ±  4% 
perf-profile.calltrace.cycles-pp._copy_from_iter_full.tcp_sendmsg_locked.tcp_sendmsg.sock_sendmsg.xs_sendpages 

   2.30 ±  5%  +3.7    6.02 ±  3% 
perf-profile.calltrace.cycles-pp.__rpc_execute.rpc_async_schedule.process_one_work.worker_thread.kthread 

   2.30 ±  5%  +3.7    6.02 ±  3% 
perf-profile.calltrace.cycles-pp.rpc_async_schedule.process_one_work.worker_thread.kthread.ret_from_fork 

   1.81 ±  4%  +3.8    5.59 ±  4% 
perf-profile.calltrace.cycles-pp.call_transmit.__rpc_execute.rpc_async_schedule.process_one_work.worker_thread 

   1.80 ±  3%  +3.8    5.59 ±  3% 
perf-profile.calltrace.cycles-pp.xprt_transmit.call_transmit.__rpc_execute.rpc_async_schedule.process_one_work 

   1.73 ±  4%  +3.8    5.54 ±  4% 
perf-profile.calltrace.cycles-pp.xs_tcp_send_request.xprt_transmit.call_transmit.__rpc_execute.rpc_async_schedule 

   1.72 ±  4%  +3.8    5.54 ±  4% 
perf-profile.calltrace.cycles-pp.xs_sendpages.xs_tcp_send_request.xprt_transmit.call_transmit.__rpc_execute 

   0.00    +5.4    5.42 ±  4% 
perf-profile.calltrace.cycles-pp.tcp_sendmsg_locked.tcp_sendmsg.sock_sendmsg.xs_sendpages.xs_tcp_send_request 

   0.00    +5.5    5.52 ±  4% 
perf-profile.calltrace.cycles-pp.tcp_sendmsg.sock_sendmsg.xs_sendpages.xs_tcp_send_request.xprt_transmit 

   0.00    +5.5    5.53 ±  4% 
perf-profile.calltrace.cycles-pp.sock_sendmsg.xs_sendpages.xs_tcp_send_request.xprt_transmit.call_transmit 

   9.61 ±  5%  +3.1   12.70 ±  2% 
perf-profile.children.cycles-pp.worker_thread
   9.27 ±  5%  +3.1   12.40 ±  2% 
perf-profile.children.cycles-pp.process_one_work
   6.19    +3.2    9.40 ±  4% 
perf-profile.children.cycles-pp.memcpy_erms
  34.53 ±  4%  +3.3   37.78 ±  2% 
perf-profile.children.cycles-pp.ret_from_fork
  34.52 ±  4%  +3.3   37.78 ±  2% 
perf-profile.children.cycles-pp.kthread
   0.00    +3.5    3.46 ±  4% 
perf-profile.children.cycles-pp.memcpy_from_page
   0.00    +3.6    3.56 ±  4% 
perf-profile.children.cycles-pp._copy_from_iter_full
   2.47 ±  4%  +3.7    6.18 ±  3% 
perf-profile.children.cycles-pp.__rpc_execute
   2.30 ±  5%  +3.7    6.02 ±  3% 
perf-profile.children.cycles-pp.rpc_async_schedule
   

Re: [PATCH v2 1/1] ixgbe: sync the first fragment unconditionally

[Jacob Wen]

I think the description is not correct. Consider using something like below.


In Xen environment, due to memory fragmentation ixgbe may allocate a 
'DMA' buffer with pages that are not physically contiguous.


A NIC doesn't support directly write such buffer. So xen-swiotlb would 
use the pages, which are physically contiguous, from the swiotlb buffer 
for the NIC.


The unmap operation is used to copy the swiotlb buffer to the pages that 
are allocated by ixgbe.


On 8/7/19 10:49 AM, Firo Yang wrote:

In Xen environment, if Xen-swiotlb is enabled, ixgbe driver
could possibly allocate a page, DMA memory buffer, for the first
fragment which is not suitable for Xen-swiotlb to do DMA operations.
Xen-swiotlb have to internally allocate another page for doing DMA
operations. It requires syncing between those two pages. However,
since commit f3213d932173 ("ixgbe: Update driver to make use of DMA
attributes in Rx path"), the unmap operation is performed with
DMA_ATTR_SKIP_CPU_SYNC. As a result, the sync is not performed.

To fix this problem, always sync before possibly performing a page
unmap operation.

Fixes: f3213d932173 ("ixgbe: Update driver to make use of DMA
attributes in Rx path")
Reviewed-by: Alexander Duyck 
Signed-off-by: Firo Yang 
---

Changes from v1:
  * Imporved the patch description.
  * Added Reviewed-by: and Fixes: as suggested by Alexander Duyck

  drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 16 +---
  1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c 
b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index cbaf712d6529..200de9838096 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -1825,13 +1825,7 @@ static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
  static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
struct sk_buff *skb)
  {
-   /* if the page was released unmap it, else just sync our portion */
-   if (unlikely(IXGBE_CB(skb)->page_released)) {
-   dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
-ixgbe_rx_pg_size(rx_ring),
-DMA_FROM_DEVICE,
-IXGBE_RX_DMA_ATTR);
-   } else if (ring_uses_build_skb(rx_ring)) {
+   if (ring_uses_build_skb(rx_ring)) {
unsigned long offset = (unsigned long)(skb->data) & ~PAGE_MASK;
  
  		dma_sync_single_range_for_cpu(rx_ring->dev,

@@ -1848,6 +1842,14 @@ static void ixgbe_dma_sync_frag(struct ixgbe_ring 
*rx_ring,
  skb_frag_size(frag),
  DMA_FROM_DEVICE);
}
+
+   /* If the page was released, just unmap it. */
+   if (unlikely(IXGBE_CB(skb)->page_released)) {
+   dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
+ixgbe_rx_pg_size(rx_ring),
+DMA_FROM_DEVICE,
+IXGBE_RX_DMA_ATTR);
+   }
  }
  
  /**

Re: [PATCH 2/2] s390/build: use size command to perform empty .bss check

[Vasily Gorbik]

On Wed, Aug 07, 2019 at 11:33:40AM +0900, Masahiro Yamada wrote:
> On Tue, Aug 6, 2019 at 7:56 PM Vasily Gorbik  wrote:
> >
> > Currently empty .bss checks performed do not pay attention to "common
> > objects" in object files which end up in .bss section eventually.
> >
> > The "size" tool is a part of binutils and since version 2.18 provides
> > "--common" command line option, which allows to account "common objects"
> > sizes in .bss section size. Utilize "size --common" to perform accurate
> > check that .bss section is unused. Besides that the size tool handles
> > object files without .bss section gracefully and doesn't require
> > additional objdump run.
> >
> > The linux kernel requires binutils 2.20 since 4.13.
> >
> > Kbuild exports OBJSIZE to reference the right size tool.
> >
> > Signed-off-by: Vasily Gorbik 
> > ---
> >  arch/s390/scripts/Makefile.chkbss | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/arch/s390/scripts/Makefile.chkbss 
> > b/arch/s390/scripts/Makefile.chkbss
> > index 884a9caff5fb..ba1d7a8a242f 100644
> > --- a/arch/s390/scripts/Makefile.chkbss
> > +++ b/arch/s390/scripts/Makefile.chkbss
> > @@ -11,8 +11,7 @@ chkbss: $(addprefix $(obj)/, $(chkbss-files))
> >
> >  quiet_cmd_chkbss = CHKBSS  $<
> >cmd_chkbss = \
> > -   if $(OBJDUMP) -h $< | grep -q "\.bss" && \
> > -  ! $(OBJDUMP) -j .bss -w -h $< | awk 'END { if ($$3) exit 1 }'; 
> > then \
> > +   if ! $(OBJSIZE) --common $< | awk 'END { if ($$3) exit 1 }'; then \
> 
> While you are touching this line,
> you may also want to replace 'awk' with $(AWK),
> which is defined in the top-level Makefile.

Indeed, thank you!

[PATCH v4 1/4] nvme-pci: Pass the queue to SQ_SIZE/CQ_SIZE macros

[Benjamin Herrenschmidt]

This will make it easier to handle variable queue entry sizes
later. No functional change.

Signed-off-by: Benjamin Herrenschmidt 
Reviewed-by: Christoph Hellwig 
Reviewed-by: Minwoo Im 
---
 drivers/nvme/host/pci.c | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 362a1a9ced36..b5b296984aa1 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -28,8 +28,8 @@
 #include "trace.h"
 #include "nvme.h"
 
-#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
-#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
+#define SQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_command))
+#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
 
 #define SGES_PER_PAGE  (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
 
@@ -1344,16 +1344,16 @@ static enum blk_eh_timer_return nvme_timeout(struct 
request *req, bool reserved)
 
 static void nvme_free_queue(struct nvme_queue *nvmeq)
 {
-   dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth),
+   dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
(void *)nvmeq->cqes, nvmeq->cq_dma_addr);
if (!nvmeq->sq_cmds)
return;
 
if (test_and_clear_bit(NVMEQ_SQ_CMB, >flags)) {
pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
-   nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
+   nvmeq->sq_cmds, SQ_SIZE(nvmeq));
} else {
-   dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth),
+   dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
nvmeq->sq_cmds, nvmeq->sq_dma_addr);
}
 }
@@ -1433,12 +1433,12 @@ static int nvme_cmb_qdepth(struct nvme_dev *dev, int 
nr_io_queues,
 }
 
 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
-   int qid, int depth)
+   int qid)
 {
struct pci_dev *pdev = to_pci_dev(dev->dev);
 
if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
-   nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
+   nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
if (nvmeq->sq_cmds) {
nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
nvmeq->sq_cmds);
@@ -1447,11 +1447,11 @@ static int nvme_alloc_sq_cmds(struct nvme_dev *dev, 
struct nvme_queue *nvmeq,
return 0;
}
 
-   pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(depth));
+   pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
}
}
 
-   nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
+   nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
>sq_dma_addr, GFP_KERNEL);
if (!nvmeq->sq_cmds)
return -ENOMEM;
@@ -1465,12 +1465,13 @@ static int nvme_alloc_queue(struct nvme_dev *dev, int 
qid, int depth)
if (dev->ctrl.queue_count > qid)
return 0;
 
-   nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
+   nvmeq->q_depth = depth;
+   nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
 >cq_dma_addr, GFP_KERNEL);
if (!nvmeq->cqes)
goto free_nvmeq;
 
-   if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
+   if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
goto free_cqdma;
 
nvmeq->dev = dev;
@@ -1479,15 +1480,14 @@ static int nvme_alloc_queue(struct nvme_dev *dev, int 
qid, int depth)
nvmeq->cq_head = 0;
nvmeq->cq_phase = 1;
nvmeq->q_db = >dbs[qid * 2 * dev->db_stride];
-   nvmeq->q_depth = depth;
nvmeq->qid = qid;
dev->ctrl.queue_count++;
 
return 0;
 
  free_cqdma:
-   dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
-   nvmeq->cq_dma_addr);
+   dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
+ nvmeq->cq_dma_addr);
  free_nvmeq:
return -ENOMEM;
 }
@@ -1515,7 +1515,7 @@ static void nvme_init_queue(struct nvme_queue *nvmeq, u16 
qid)
nvmeq->cq_head = 0;
nvmeq->cq_phase = 1;
nvmeq->q_db = >dbs[qid * 2 * dev->db_stride];
-   memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
+   memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
nvme_dbbuf_init(dev, nvmeq, qid);
dev->online_queues++;
wmb(); /* ensure the first interrupt sees the initialization */
-- 
2.17.1

[PATCH v4 0/4] nvme-pci: Support for Apple 201+ (T2 chip)

[Benjamin Herrenschmidt]

This series combines the original series and an updated version of the
shared tags patch, and is rebased on nvme-5.4.

This adds support for the controller found in recent Apple machines
which is basically a SW emulated NVME controller in the T2 chip.

The original reverse engineering work was done by
Paul Pawlowski .

Re: [PATCH 0/4] x86/mce: protect nr_cpus from rebooting by broadcast mce

[Pingfan Liu]

On Wed, Aug 07, 2019 at 11:00:41AM +0800, Dave Young wrote:
> Add Tony and Xunlei in cc.
> On 08/05/19 at 04:58pm, Pingfan Liu wrote:
> > This series include two related groups:
> > [1-3/4]: protect nr_cpus from rebooting by broadcast mce
> > [4/4]: improve "kexec -l" robustness against broadcast mce
> > 
> > When I tried to fix [1], Thomas raised concern about the nr_cpus' 
> > vulnerability
> > to unexpected rebooting by broadcast mce. After analysis, I think only the
> > following first case suffers from the rebooting by broadcast mce. [1-3/4] 
> > aims
> > to fix that issue.
> 
> I did not understand and read the MCE details, but we previously had a
> MCE problem, Xunlei fixed in below commit:
> commit 5bc329503e8191c91c4c40836f062ef771d8ba83
> Author: Xunlei Pang 
> Date:   Mon Mar 13 10:50:19 2017 +0100
> 
> x86/mce: Handle broadcasted MCE gracefully with kexec
> 
> I wonder if this is same issue or not. Also the old discussion is in
> below thread:
> https://lore.kernel.org/patchwork/patch/753530/
> 
> Tony raised similar questions, but I'm not sure if it is still a problem
> or it has been fixed.
> 
Xunlei's patch is the precondition of the stability for the case 2: boot up by 
"kexec -p nr_cpus="

For case1/3, extra effort is needed.

Thanks,
Pingfan
> > 
> > *** Back ground ***
> > 
> > On x86 it's required to have all logical CPUs set CR4.MCE=1. Otherwise, a
> > broadcast MCE observing CR4.MCE=0b on any core will shutdown the machine.
> > 
> > The option 'nosmt' has already complied with the above rule by Thomas's 
> > patch.
> > For detail, refer to 506a66f3748 (Revert "x86/apic: Ignore secondary 
> > threads if
> > nosmt=force")
> > 
> > But for nr_cpus option, the exposure to broadcast MCE is a little 
> > complicated,
> > and can be categorized into three cases.
> > 
> > -1. boot up by BIOS. Since no one set CR4.MCE=1, nr_cpus risks rebooting by
> > broadcast MCE.
> > 
> > -2. boot up by "kexec -p nr_cpus=".  Since the 1st kernel has all cpus'
> > CR4.MCE=1 set before kexec -p, nr_cpus is free of rebooting by broadcast 
> > MCE.
> > Furthermore, the crashed kernel's wreckage, including page table and text, 
> > is
> > not touched by capture kernel. Hence if MCE event happens on capped cpu,
> > do_machine_check->__mc_check_crashing_cpu() runs smoothly and returns
> > immediately, the capped cpu is still pinned on "halt".
> > 
> > -3. boot up by "kexec -l nr_cpus=". As "kexec -p", it is free of rebooting 
> > by
> > broadcast MCE. But the 1st kernel's wreckage is discarded and changed.  when
> > capped cpus execute do_machine_check(), they may crack the new kernel.  But
> > this is not related with broadcast MCE, and need an extra fix.
> > 
> > *** Solution ***
> > "nr_cpus" can not follow the same way as "nosmt".  Because nr_cpus limits 
> > the
> > allocation of percpu area and some other kthread memory, which is critical 
> > to
> > cpu hotplug framework.  Instead, developing a dedicated SIPI callback
> > make_capped_cpu_stable() for capped cpu, which does not lean on percpu area 
> > to
> > work.
> > 
> > [1]: https://lkml.org/lkml/2019/7/5/3
> > 
> > To: Gleixner 
> > To: Andy Lutomirski 
> > Cc: Ingo Molnar 
> > Cc: Borislav Petkov 
> > Cc: "H. Peter Anvin" 
> > Cc: Dave Hansen 
> > Cc: Peter Zijlstra 
> > To: x...@kernel.org
> > Cc: Masami Hiramatsu 
> > Cc: Qian Cai 
> > Cc: Vlastimil Babka 
> > Cc: Daniel Drake 
> > Cc: Jacob Pan 
> > Cc: Michal Hocko 
> > Cc: Eric Biederman 
> > Cc: linux-kernel@vger.kernel.org
> > Cc: Dave Young 
> > Cc: Baoquan He 
> > Cc: ke...@lists.infradead.org
> > 
> > ---
> > Pingfan Liu (4):
> >   x86/apic: correct the ENO in generic_processor_info()
> >   x86/apic: record capped cpu in generic_processor_info()
> >   x86/smp: send capped cpus to a stable state when smp_init()
> >   x86/smp: disallow MCE handler on rebooting AP
> > 
> >  arch/x86/include/asm/apic.h  |  1 +
> >  arch/x86/include/asm/smp.h   |  3 ++
> >  arch/x86/kernel/apic/apic.c  | 23 
> >  arch/x86/kernel/cpu/common.c |  7 
> >  arch/x86/kernel/smp.c|  8 +
> >  arch/x86/kernel/smpboot.c| 83 
> > 
> >  kernel/smp.c |  6 
> >  7 files changed, 124 insertions(+), 7 deletions(-)
> > 
> > -- 
> > 2.7.5
> > 
> 
> Thanks
> Dave

Re: [PATCH 15/16] net: phy: adin: add ethtool get_stats support

[Ardelean, Alexandru]

On Tue, 2019-08-06 at 17:46 +0200, Andrew Lunn wrote:
> [External]
> 
> On Tue, Aug 06, 2019 at 07:11:57AM +, Ardelean, Alexandru wrote:
> > On Mon, 2019-08-05 at 17:28 +0200, Andrew Lunn wrote:
> > > [External]
> > > 
> > > > +struct adin_hw_stat {
> > > > +   const char *string;
> > > > +static void adin_get_strings(struct phy_device *phydev, u8 *data)
> > > > +{
> > > > +   int i;
> > > > +
> > > > +   for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) {
> > > > +   memcpy(data + i * ETH_GSTRING_LEN,
> > > > +  adin_hw_stats[i].string, ETH_GSTRING_LEN);
> > > 
> > > You define string as a char *. So it will be only as long as it should
> > > be. However memcpy always copies ETH_GSTRING_LEN bytes, doing off the
> > > end of the string and into whatever follows.
> > > 
> > 
> > hmm, will use strlcpy()
> > i blindedly copied memcpy() from some other driver
> 
> Hopefully that driver used const char string[ETH_GSTRING_LEN]. Then a
> memcpy is safe. If not, please let me know what driver you copied.

It was an older Marvell PHY driver (marvell.c) ; in version 4.14.
I used that as an initial work-base for writing the driver.
Then I did the conversion to a newer kernel, then I also had to also consider 
an older kernel, then I got confused :)

Well, in any case, I am solely considering net-next master (now) for 
upstreaming this.

> 
> > i'm afraid i don't understand about the snapshot feature you are mentioning;
> > i.e. i don't remember seeing it in other chips;
> 
> It is frequency done at the MAC layer for statistics. You tell the
> hardware to snapshot all the statistics. It atomically makes a copy of
> all the statistics into a set of registers. These values are then
> static, and consistent between counters. You can read them out knowing
> they are not going to change.
> 
> > regarding the danger that stat->reg1 rolls over, i guess that is
> > possible, but it's a bit hard to guard against;
> 
> The normal solution is the read the MSB, the LSB and then the MSB
> again. If the MSB value has changed between the two reads, you know a
> roll over has happened, and you need to do it all again.

hmm; ok
I'll try to look for an existing example for this.

> 
>  Andrew

[PATCH v4 4/4] nvme-pci: Support shared tags across queues for Apple 2018 controllers

[Benjamin Herrenschmidt]

Another issue with the Apple T2 based 2018 controllers seem to be
that they blow up (and shut the machine down) if there's a tag
collision between the IO queue and the Admin queue.

My suspicion is that they use our tags for their internal tracking
and don't mix them with the queue id. They also seem to not like
when tags go beyond the IO queue depth, ie 128 tags.

This adds a quirk that marks tags 0..31 of the IO queue reserved

Signed-off-by: Benjamin Herrenschmidt 
Reviewed-by: Ming Lei 
Acked-by: Keith Busch 
---
 drivers/nvme/host/nvme.h |  5 +
 drivers/nvme/host/pci.c  | 31 ++-
 2 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
index 0925f7fc13ff..3e64f7187e70 100644
--- a/drivers/nvme/host/nvme.h
+++ b/drivers/nvme/host/nvme.h
@@ -102,6 +102,11 @@ enum nvme_quirks {
 * Use non-standard 128 bytes SQEs.
 */
NVME_QUIRK_128_BYTES_SQES   = (1 << 11),
+
+   /*
+* Prevent tag overlap between queues
+*/
+   NVME_QUIRK_SHARED_TAGS  = (1 << 12),
 };
 
 /*
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index c683263cdf60..de8c170d5abc 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -2106,6 +2106,14 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
unsigned long size;
 
nr_io_queues = max_io_queues();
+
+   /*
+* If tags are shared with admin queue (Apple bug), then
+* make sure we only use one IO queue.
+*/
+   if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
+   nr_io_queues = 1;
+
result = nvme_set_queue_count(>ctrl, _io_queues);
if (result < 0)
return result;
@@ -2276,6 +2284,14 @@ static int nvme_dev_add(struct nvme_dev *dev)
dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
dev->tagset.driver_data = dev;
 
+   /*
+* Some Apple controllers requires tags to be unique
+* across admin and IO queue, so reserve the first 32
+* tags of the IO queue.
+*/
+   if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
+   dev->tagset.reserved_tags = NVME_AQ_DEPTH;
+
ret = blk_mq_alloc_tag_set(>tagset);
if (ret) {
dev_warn(dev->ctrl.device,
@@ -2356,6 +2372,18 @@ static int nvme_pci_enable(struct nvme_dev *dev)
 "set queue depth=%u\n", dev->q_depth);
}
 
+   /*
+* Controllers with the shared tags quirk need the IO queue to be
+* big enough so that we get 32 tags for the admin queue
+*/
+   if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
+   (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
+   dev->q_depth = NVME_AQ_DEPTH + 2;
+   dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
+dev->q_depth);
+   }
+
+
nvme_map_cmb(dev);
 
pci_enable_pcie_error_reporting(pdev);
@@ -3057,7 +3085,8 @@ static const struct pci_device_id nvme_id_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
.driver_data = NVME_QUIRK_SINGLE_VECTOR |
-   NVME_QUIRK_128_BYTES_SQES },
+   NVME_QUIRK_128_BYTES_SQES |
+   NVME_QUIRK_SHARED_TAGS },
{ 0, }
 };
 MODULE_DEVICE_TABLE(pci, nvme_id_table);
-- 
2.17.1

[PATCH v4 2/4] nvme-pci: Add support for variable IO SQ element size

[Benjamin Herrenschmidt]

The size of a submission queue element should always be 6 (64 bytes)
by spec.

However some controllers such as Apple's are not properly implementing
the standard and require a different size.

This provides the ground work for the subsequent quirks for these
controllers.

Signed-off-by: Benjamin Herrenschmidt 
Reviewed-by: Minwoo Im 
---
 drivers/nvme/host/pci.c | 11 ---
 include/linux/nvme.h|  1 +
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index b5b296984aa1..78a660e229d9 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -28,7 +28,7 @@
 #include "trace.h"
 #include "nvme.h"
 
-#define SQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_command))
+#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
 
 #define SGES_PER_PAGE  (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
@@ -100,6 +100,7 @@ struct nvme_dev {
unsigned io_queues[HCTX_MAX_TYPES];
unsigned int num_vecs;
int q_depth;
+   int io_sqes;
u32 db_stride;
void __iomem *bar;
unsigned long bar_mapped_size;
@@ -162,7 +163,7 @@ static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl 
*ctrl)
 struct nvme_queue {
struct nvme_dev *dev;
spinlock_t sq_lock;
-   struct nvme_command *sq_cmds;
+   void *sq_cmds;
 /* only used for poll queues: */
spinlock_t cq_poll_lock cacheline_aligned_in_smp;
volatile struct nvme_completion *cqes;
@@ -178,6 +179,7 @@ struct nvme_queue {
u16 last_cq_head;
u16 qid;
u8 cq_phase;
+   u8 sqes;
unsigned long flags;
 #define NVMEQ_ENABLED  0
 #define NVMEQ_SQ_CMB   1
@@ -488,7 +490,8 @@ static void nvme_submit_cmd(struct nvme_queue *nvmeq, 
struct nvme_command *cmd,
bool write_sq)
 {
spin_lock(>sq_lock);
-   memcpy(>sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
+   memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
+  cmd, sizeof(*cmd));
if (++nvmeq->sq_tail == nvmeq->q_depth)
nvmeq->sq_tail = 0;
nvme_write_sq_db(nvmeq, write_sq);
@@ -1465,6 +1468,7 @@ static int nvme_alloc_queue(struct nvme_dev *dev, int 
qid, int depth)
if (dev->ctrl.queue_count > qid)
return 0;
 
+   nvmeq->sqes = qid ? dev->io_sqes : NVME_NVM_ADMSQES;
nvmeq->q_depth = depth;
nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
 >cq_dma_addr, GFP_KERNEL);
@@ -2317,6 +2321,7 @@ static int nvme_pci_enable(struct nvme_dev *dev)
dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
dev->dbs = dev->bar + 4096;
+   dev->io_sqes = NVME_NVM_IOSQES;
 
/*
 * Temporary fix for the Apple controller found in the MacBook8,1 and
diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index 01aa6a6c241d..d5a4bc21f36b 100644
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -140,6 +140,7 @@ enum {
  * Submission and Completion Queue Entry Sizes for the NVM command set.
  * (In bytes and specified as a power of two (2^n)).
  */
+#define NVME_NVM_ADMSQES   6
 #define NVME_NVM_IOSQES6
 #define NVME_NVM_IOCQES4
 
-- 
2.17.1

[PATCH v4 3/4] nvme-pci: Add support for Apple 2018+ models

[Benjamin Herrenschmidt]

Based on reverse engineering and original patch by

Paul Pawlowski 

This adds support for Apple weird implementation of NVME in their
2018 or later machines. It accounts for the twice-as-big SQ entries
for the IO queues, and the fact that only interrupt vector 0 appears
to function properly.

Signed-off-by: Benjamin Herrenschmidt 
Reviewed-by: Minwoo Im 
---
 drivers/nvme/host/nvme.h | 10 ++
 drivers/nvme/host/pci.c  | 21 -
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
index 8dc010ca30e5..0925f7fc13ff 100644
--- a/drivers/nvme/host/nvme.h
+++ b/drivers/nvme/host/nvme.h
@@ -92,6 +92,16 @@ enum nvme_quirks {
 * Broken Write Zeroes.
 */
NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9),
+
+   /*
+* Use only one interrupt vector for all queues
+*/
+   NVME_QUIRK_SINGLE_VECTOR= (1 << 10),
+
+   /*
+* Use non-standard 128 bytes SQEs.
+*/
+   NVME_QUIRK_128_BYTES_SQES   = (1 << 11),
 };
 
 /*
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 78a660e229d9..c683263cdf60 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -2081,6 +2081,13 @@ static int nvme_setup_irqs(struct nvme_dev *dev, 
unsigned int nr_io_queues)
dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
dev->io_queues[HCTX_TYPE_READ] = 0;
 
+   /*
+* Some Apple controllers require all queues to use the
+* first vector.
+*/
+   if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
+   irq_queues = 1;
+
return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
  PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, );
 }
@@ -2321,7 +2328,16 @@ static int nvme_pci_enable(struct nvme_dev *dev)
dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
dev->dbs = dev->bar + 4096;
-   dev->io_sqes = NVME_NVM_IOSQES;
+
+   /*
+* Some Apple controllers require a non-standard SQE size.
+* Interestingly they also seem to ignore the CC:IOSQES register
+* so we don't bother updating it here.
+*/
+   if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
+   dev->io_sqes = 7;
+   else
+   dev->io_sqes = NVME_NVM_IOSQES;
 
/*
 * Temporary fix for the Apple controller found in the MacBook8,1 and
@@ -3039,6 +3055,9 @@ static const struct pci_device_id nvme_id_table[] = {
{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xff) },
{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
+   { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
+   .driver_data = NVME_QUIRK_SINGLE_VECTOR |
+   NVME_QUIRK_128_BYTES_SQES },
{ 0, }
 };
 MODULE_DEVICE_TABLE(pci, nvme_id_table);
-- 
2.17.1

Re: [PATCH] mm/mmap.c: refine data locality of find_vma_prev

[Michal Hocko]

On Wed 07-08-19 08:31:09, Wei Yang wrote:
> On Tue, Aug 06, 2019 at 11:29:52AM +0200, Vlastimil Babka wrote:
> >On 8/6/19 10:11 AM, Wei Yang wrote:
> >> When addr is out of the range of the whole rb_tree, pprev will points to
> >> the biggest node. find_vma_prev gets is by going through the right most
> >
> >s/biggest/last/ ? or right-most?
> >
> >> node of the tree.
> >> 
> >> Since only the last node is the one it is looking for, it is not
> >> necessary to assign pprev to those middle stage nodes. By assigning
> >> pprev to the last node directly, it tries to improve the function
> >> locality a little.
> >
> >In the end, it will always write to the cacheline of pprev. The caller has 
> >most
> >likely have it on stack, so it's already hot, and there's no other CPU 
> >stealing
> >it. So I don't understand where the improved locality comes from. The 
> >compiler
> >can also optimize the patched code so the assembly is identical to the 
> >previous
> >code, or vice versa. Did you check for differences?
> 
> Vlastimil
> 
> Thanks for your comment.
> 
> I believe you get a point. I may not use the word locality. This patch tries
> to reduce some unnecessary assignment of pprev.
> 
> Original code would assign the value on each node during iteration, this is
> what I want to reduce.

Is there any measurable difference (on micro benchmarks or regular
workloads)?
-- 
Michal Hocko
SUSE Labs

[PATCH 1/2] riscv: Add memmove string operation.

[Nick Hu]

There are some features which need this string operation for compilation,
like KASAN. So the purpose of this porting is for the features like KASAN
which cannot be compiled without it.

KASAN's string operations would replace the original string operations and
call for the architecture defined string operations. Since we don't have
this in current kernel, this patch provides the implementation.

This porting refers to the 'arch/nds32/lib/memmove.S'.

Signed-off-by: Nick Hu 
---
 arch/riscv/include/asm/string.h |3 ++
 arch/riscv/kernel/riscv_ksyms.c |1 +
 arch/riscv/lib/Makefile |1 +
 arch/riscv/lib/memmove.S|   63 +++
 4 files changed, 68 insertions(+), 0 deletions(-)
 create mode 100644 arch/riscv/lib/memmove.S

diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h
index 1b5d445..11210f1 100644
--- a/arch/riscv/include/asm/string.h
+++ b/arch/riscv/include/asm/string.h
@@ -15,4 +15,7 @@
 #define __HAVE_ARCH_MEMCPY
 extern asmlinkage void *memcpy(void *, const void *, size_t);
 
+#define __HAVE_ARCH_MEMMOVE
+extern asmlinkage void *memmove(void *, const void *, size_t);
+
 #endif /* _ASM_RISCV_STRING_H */
diff --git a/arch/riscv/kernel/riscv_ksyms.c b/arch/riscv/kernel/riscv_ksyms.c
index 4800cf7..ffabaf1 100644
--- a/arch/riscv/kernel/riscv_ksyms.c
+++ b/arch/riscv/kernel/riscv_ksyms.c
@@ -14,3 +14,4 @@
 EXPORT_SYMBOL(__asm_copy_from_user);
 EXPORT_SYMBOL(memset);
 EXPORT_SYMBOL(memcpy);
+EXPORT_SYMBOL(memmove);
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 8e364eb..9a4d5b3 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -2,6 +2,7 @@
 lib-y  += delay.o
 lib-y  += memcpy.o
 lib-y  += memset.o
+lib-y  += memmove.o
 lib-y  += uaccess.o
 
 lib-$(CONFIG_64BIT) += tishift.o
diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S
new file mode 100644
index 000..3657a06
--- /dev/null
+++ b/arch/riscv/lib/memmove.S
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include 
+#include 
+
+ENTRY(memmove)
+   movet0, a0
+   movet1, a1
+
+   beq a0, a1, exit_memcpy
+   beqza2, exit_memcpy
+   srlit2, a2, 0x2
+
+   slt t3, a0, a1
+   beqzt3, do_reverse
+
+   andia2, a2, 0x3
+   li  t4, 1
+   beqzt2, byte_copy
+
+word_copy:
+   lw  t3, 0(a1)
+   addit2, t2, -1
+   addia1, a1, 4
+   sw  t3, 0(a0)
+   addia0, a0, 4
+   bnezt2, word_copy
+   beqza2, exit_memcpy
+   j   byte_copy
+
+do_reverse:
+   add a0, a0, a2
+   add a1, a1, a2
+   andia2, a2, 0x3
+   li  t4, -1
+   beqzt2, reverse_byte_copy
+
+reverse_word_copy:
+   addia1, a1, -4
+   addit2, t2, -1
+   lw  t3, 0(a1)
+   addia0, a0, -4
+   sw  t3, 0(a0)
+   bnezt2, reverse_word_copy
+   beqza2, exit_memcpy
+
+reverse_byte_copy:
+   addia0, a0, -1
+   addia1, a1, -1
+byte_copy:
+   lb  t3, 0(a1)
+   addia2, a2, -1
+   sb  t3, 0(a0)
+   add a1, a1, t4
+   add a0, a0, t4
+   bneza2, byte_copy
+
+exit_memcpy:
+   move a0, t0
+   move a1, t1
+   ret
+
+END(memmove)
-- 
1.7.1

[PATCH 2/2] riscv: Add KASAN support

[Nick Hu]

This patch ports the feature Kernel Address SANitizer (KASAN).

Note: The start address of shadow memory is at the beginning of kernel
space, which is 2^64 - (2^39 / 2) in SV39. The size of the kernel space
is 2^38 bytes so the size of shadow memory should be 2^38 / 8. Thus, the
shadow memory would not overlap with the fixmap area.

There are currently two limitations in this port,

1. RV64 only: KASAN need large address space for extra shadow memory
region.

2. KASAN can't debug the modules since the modules are allocated in VMALLOC
area. We mapped the shadow memory, which corresponding to VMALLOC area,
to the kasan_early_shadow_page because we don't have enough physical space
for all the shadow memory corresponding to VMALLOC area.

Signed-off-by: Nick Hu 
---
 arch/riscv/Kconfig  |2 +
 arch/riscv/include/asm/kasan.h  |   26 +
 arch/riscv/include/asm/pgtable-64.h |5 ++
 arch/riscv/include/asm/string.h |7 +++
 arch/riscv/kernel/head.S|3 +
 arch/riscv/kernel/riscv_ksyms.c |3 +
 arch/riscv/kernel/setup.c   |9 +++
 arch/riscv/kernel/vmlinux.lds.S |1 +
 arch/riscv/lib/memcpy.S |5 +-
 arch/riscv/lib/memmove.S|5 +-
 arch/riscv/lib/memset.S |5 +-
 arch/riscv/mm/Makefile  |6 ++
 arch/riscv/mm/kasan_init.c  |  102 +++
 13 files changed, 173 insertions(+), 6 deletions(-)
 create mode 100644 arch/riscv/include/asm/kasan.h
 create mode 100644 arch/riscv/mm/kasan_init.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 59a4727..4878b7a 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -54,6 +54,8 @@ config RISCV
select EDAC_SUPPORT
select ARCH_HAS_GIGANTIC_PAGE
select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
+   select GENERIC_STRNCPY_FROM_USER if KASAN
+   select HAVE_ARCH_KASAN if MMU
 
 config MMU
def_bool y
diff --git a/arch/riscv/include/asm/kasan.h b/arch/riscv/include/asm/kasan.h
new file mode 100644
index 000..e0c1f27
--- /dev/null
+++ b/arch/riscv/include/asm/kasan.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_KASAN_H
+#define __ASM_KASAN_H
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_KASAN
+
+#include 
+
+#define KASAN_SHADOW_SCALE_SHIFT   3
+
+#define KASAN_SHADOW_SIZE  (UL(1) << (38 - KASAN_SHADOW_SCALE_SHIFT))
+#define KASAN_SHADOW_START 0xffc0 // 2^64 - 2^38
+#define KASAN_SHADOW_END   (KASAN_SHADOW_START + KASAN_SHADOW_SIZE)
+
+#define KASAN_SHADOW_OFFSET(KASAN_SHADOW_END - (1ULL << \
+   (64 - KASAN_SHADOW_SCALE_SHIFT)))
+
+void kasan_init(void);
+asmlinkage void kasan_early_init(void);
+
+#endif
+#endif
+#endif
diff --git a/arch/riscv/include/asm/pgtable-64.h 
b/arch/riscv/include/asm/pgtable-64.h
index 7df8daa..777a1dd 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -59,6 +59,11 @@ static inline unsigned long pud_page_vaddr(pud_t pud)
return (unsigned long)pfn_to_virt(pud_val(pud) >> _PAGE_PFN_SHIFT);
 }
 
+static inline struct page *pud_page(pud_t pud)
+{
+   return pfn_to_page(pud_val(pud) >> _PAGE_PFN_SHIFT);
+}
+
 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
 
 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h
index 11210f1..ab90f44 100644
--- a/arch/riscv/include/asm/string.h
+++ b/arch/riscv/include/asm/string.h
@@ -11,11 +11,18 @@
 
 #define __HAVE_ARCH_MEMSET
 extern asmlinkage void *memset(void *, int, size_t);
+extern asmlinkage void *__memset(void *, int, size_t);
 
 #define __HAVE_ARCH_MEMCPY
 extern asmlinkage void *memcpy(void *, const void *, size_t);
+extern asmlinkage void *__memcpy(void *, const void *, size_t);
 
 #define __HAVE_ARCH_MEMMOVE
 extern asmlinkage void *memmove(void *, const void *, size_t);
+extern asmlinkage void *__memmove(void *, const void *, size_t);
+
+#define memcpy(dst, src, len) __memcpy(dst, src, len)
+#define memmove(dst, src, len) __memmove(dst, src, len)
+#define memset(s, c, n) __memset(s, c, n)
 
 #endif /* _ASM_RISCV_STRING_H */
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 0f1ba17..2f7bc8b 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -97,6 +97,9 @@ clear_bss_done:
sw zero, TASK_TI_CPU(tp)
la sp, init_thread_union + THREAD_SIZE
 
+#ifdef CONFIG_KASAN
+   call kasan_early_init
+#endif
/* Start the kernel */
call parse_dtb
tail start_kernel
diff --git a/arch/riscv/kernel/riscv_ksyms.c b/arch/riscv/kernel/riscv_ksyms.c
index ffabaf1..ad9f007 100644
--- a/arch/riscv/kernel/riscv_ksyms.c
+++ b/arch/riscv/kernel/riscv_ksyms.c
@@ -15,3 +15,6 @@
 EXPORT_SYMBOL(memset);
 EXPORT_SYMBOL(memcpy);
 EXPORT_SYMBOL(memmove);
+EXPORT_SYMBOL(__memset);

[PATCH 0/2] KASAN support for RISC-V

[Nick Hu]

KASAN is an important runtime memory debugging feature
in linux kernel which can detect use-after-free and out-of-
bounds problems.

There are two patches in this letter:
1. Porting the memmove string operation.
2. Porting the feature KASAN.

Nick Hu (2):
  riscv: Add memmove string operation.
  riscv: Add KASAN support

 arch/riscv/Kconfig  |2 +
 arch/riscv/include/asm/kasan.h  |   26 +
 arch/riscv/include/asm/pgtable-64.h |5 ++
 arch/riscv/include/asm/string.h |   10 
 arch/riscv/kernel/head.S|3 +
 arch/riscv/kernel/riscv_ksyms.c |4 ++
 arch/riscv/kernel/setup.c   |9 +++
 arch/riscv/kernel/vmlinux.lds.S |1 +
 arch/riscv/lib/Makefile |1 +
 arch/riscv/lib/memcpy.S |5 +-
 arch/riscv/lib/memmove.S|   64 ++
 arch/riscv/lib/memset.S |5 +-
 arch/riscv/mm/Makefile  |6 ++
 arch/riscv/mm/kasan_init.c  |  102 +++
 14 files changed, 239 insertions(+), 4 deletions(-)
 create mode 100644 arch/riscv/include/asm/kasan.h
 create mode 100644 arch/riscv/lib/memmove.S
 create mode 100644 arch/riscv/mm/kasan_init.c

Re: linux-next: manual merge of the mips tree with Linus' tree

[Arnd Bergmann]

On Wed, Aug 7, 2019 at 2:25 AM Stephen Rothwell  wrote:
>
> Hi all,
>
> Today's linux-next merge of the mips tree got a conflict in:
>
>   arch/mips/include/asm/vdso/vdso.h
> ( arch/mips/vdso/vdso.h in Linus' tree)
>
> between commit:
>
>   ee38d94a0ad8 ("page flags: prioritize kasan bits over last-cpuid")
>
> from Linus' tree and commit:
>
>   6393e6064486 ("mips: fix vdso32 build, again")
>
> from the mips tree.
>
> I fixed it up (I just used the mips tree version) and can carry the fix
> as necessary. This is now fixed as far as linux-next is concerned, but
> any non trivial conflicts should be mentioned to your upstream maintainer
> when your tree is submitted for merging.  You may also want to consider
> cooperating with the maintainer of the conflicting tree to minimise any
> particularly complex conflicts.

Yes, that resolution is correct. My original fix for the issue in ee38d94a0ad8
got folded into that patch when it was merged, but as the vdso is now
completely different in the mips tree, the newer fix is needed there
compared to what is in Linus' tree.

   Arnd

[PATCH] net: tundra: tsi108: use spin_lock_irqsave instead of spin_lock_irq in IRQ context

[Fuqian Huang]

As spin_unlock_irq will enable interrupts.
Function tsi108_stat_carry is called from interrupt handler tsi108_irq.
Interrupts are enabled in interrupt handler.
Use spin_lock_irqsave/spin_unlock_irqrestore instead of spin_(un)lock_irq
in IRQ context to avoid this.

Signed-off-by: Fuqian Huang 
---
 drivers/net/ethernet/tundra/tsi108_eth.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/tundra/tsi108_eth.c 
b/drivers/net/ethernet/tundra/tsi108_eth.c
index 78a7de3fb622..14215979d07e 100644
--- a/drivers/net/ethernet/tundra/tsi108_eth.c
+++ b/drivers/net/ethernet/tundra/tsi108_eth.c
@@ -372,8 +372,9 @@ static void tsi108_stat_carry(struct net_device *dev)
 {
struct tsi108_prv_data *data = netdev_priv(dev);
u32 carry1, carry2;
+   unsigned long flags;
 
-   spin_lock_irq(>misclock);
+   spin_lock_irqsave(>misclock, flags);
 
carry1 = TSI_READ(TSI108_STAT_CARRY1);
carry2 = TSI_READ(TSI108_STAT_CARRY2);
@@ -441,7 +442,7 @@ static void tsi108_stat_carry(struct net_device *dev)
  TSI108_STAT_TXPAUSEDROP_CARRY,
  >tx_pause_drop);
 
-   spin_unlock_irq(>misclock);
+   spin_unlock_irqrestore(>misclock, flags);
 }
 
 /* Read a stat counter atomically with respect to carries.
-- 
2.11.0

Re: [PATCH v1] perf record: Add an option to take an AUX snapshot on exit

[Adrian Hunter]

On 6/08/19 5:41 PM, Alexander Shishkin wrote:
> It is sometimes useful to generate a snapshot when perf record exits;
> I've been using a wrapper script around the workload that would do a
> killall -USR2 perf when the workload exits.
> 
> This patch makes it easier and also works when perf record is attached
> to a pre-existing task. A new snapshot option 'e' can be specified in
> -S to enable this behavior:
> 
> root@elsewhere:~# perf record -e intel_pt// -Se sleep 1
> [ perf record: Woken up 2 times to write data ]
> [ perf record: Captured and wrote 0.085 MB perf.data ]
> 
> Signed-off-by: Alexander Shishkin 
> Co-developed-by: Adrian Hunter 

checkpatch says:
WARNING: Co-developed-by: must be immediately followed by Signed-off-by

> ---
>  tools/perf/Documentation/perf-record.txt | 11 +---
>  tools/perf/builtin-record.c  | 34 +---
>  tools/perf/perf.h|  1 +
>  tools/perf/util/auxtrace.c   | 14 --
>  tools/perf/util/auxtrace.h   |  2 +-
>  5 files changed, 52 insertions(+), 10 deletions(-)
> 
> diff --git a/tools/perf/Documentation/perf-record.txt 
> b/tools/perf/Documentation/perf-record.txt
> index 15e0fa87241b..d5e58e0a2bca 100644
> --- a/tools/perf/Documentation/perf-record.txt
> +++ b/tools/perf/Documentation/perf-record.txt
> @@ -422,9 +422,14 @@ CLOCK_BOOTTIME, CLOCK_REALTIME and CLOCK_TAI.
>  -S::
>  --snapshot::
>  Select AUX area tracing Snapshot Mode. This option is valid only with an
> -AUX area tracing event. Optionally the number of bytes to capture per
> -snapshot can be specified. In Snapshot Mode, trace data is captured only when
> -signal SIGUSR2 is received.
> +AUX area tracing event. Optionally, certain snapshot capturing parameters
> +can be specified in a string that follows this option:
> +  'e': take one last snapshot on exit; guarantees that there is at least one
> +   snapshot in the output file;
> +  : if the PMU supports this, specify the desired snapshot size.
> +
> +In Snapshot Mode trace data is captured only when signal SIGUSR2 is received
> +and on exit if the above 'e' option is given.
>  
>  --proc-map-timeout::
>  When processing pre-existing threads /proc/XXX/mmap, it may take a long time,
> diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c
> index d31d7a5a1be3..e9a2525ecfcc 100644
> --- a/tools/perf/builtin-record.c
> +++ b/tools/perf/builtin-record.c
> @@ -613,19 +613,35 @@ static int record__auxtrace_read_snapshot_all(struct 
> record *rec)
>   return rc;
>  }
>  
> -static void record__read_auxtrace_snapshot(struct record *rec)
> +static void record__read_auxtrace_snapshot(struct record *rec, bool on_exit)
>  {
>   pr_debug("Recording AUX area tracing snapshot\n");
>   if (record__auxtrace_read_snapshot_all(rec) < 0) {
>   trigger_error(_snapshot_trigger);
>   } else {
> - if (auxtrace_record__snapshot_finish(rec->itr))
> + if (auxtrace_record__snapshot_finish(rec->itr, on_exit))
>   trigger_error(_snapshot_trigger);
>   else
>   trigger_ready(_snapshot_trigger);
>   }
>  }
>  
> +static int record__auxtrace_snapshot_exit(struct record *rec)
> +{
> + if (trigger_is_error(_snapshot_trigger))
> + return 0;
> +
> + if (!auxtrace_record__snapshot_started &&
> + auxtrace_record__snapshot_start(rec->itr))
> + return -1;
> +
> + record__read_auxtrace_snapshot(rec, true);

Buffers can get un-mapped earlier as tasks exit.  Refer
perf_evlist__filter_pollfd() -> perf_evlist__munmap_filtered().
Maybe we should prevent that for this case.
e.g. do perf_mmap__get()'s on the mmaps at the start, and then 'put' them
all here.

> + if (trigger_is_error(_snapshot_trigger))
> + return -1;
> +
> + return 0;
> +}
> +
>  static int record__auxtrace_init(struct record *rec)
>  {
>   int err;
> @@ -654,7 +670,7 @@ int record__auxtrace_mmap_read(struct record *rec 
> __maybe_unused,
>  }
>  
>  static inline
> -void record__read_auxtrace_snapshot(struct record *rec __maybe_unused)
> +void record__read_auxtrace_snapshot(struct record *rec __maybe_unused, bool 
> on_exit)
>  {
>  }
>  
> @@ -664,6 +680,12 @@ int auxtrace_record__snapshot_start(struct 
> auxtrace_record *itr __maybe_unused)
>   return 0;
>  }
>  
> +static inline
> +int record__auxtrace_snapshot_exit(struct record *rec)
> +{
> + return 0;
> +}
> +
>  static int record__auxtrace_init(struct record *rec __maybe_unused)
>  {
>   return 0;
> @@ -1536,7 +1558,7 @@ static int __cmd_record(struct record *rec, int argc, 
> const char **argv)
>   if (auxtrace_record__snapshot_started) {
>   auxtrace_record__snapshot_started = 0;
>   if (!trigger_is_error(_snapshot_trigger))
> - record__read_auxtrace_snapshot(rec);
> + 

net-next/master boot bisection: v5.3-rc1-460-g05bb520376af on meson-gxm-khadas-vim2

[kernelci.org bot]

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* This automated bisection report was sent to you on the basis  *
* that you may be involved with the breaking commit it has  *
* found.  No manual investigation has been done to verify it,   *
* and the root cause of the problem may be somewhere else.  *
*   *
* If you do send a fix, please include this trailer:*
*   Reported-by: "kernelci.org bot"   *
*   *
* Hope this helps!  *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

net-next/master boot bisection: v5.3-rc1-460-g05bb520376af on 
meson-gxm-khadas-vim2

Summary:
  Start:  05bb520376af Merge branch '40GbE' of 
git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue
  Details:https://kernelci.org/boot/id/5d4a3a6759b51422d431b28d
  Plain log:  
https://storage.kernelci.org//net-next/master/v5.3-rc1-460-g05bb520376af/arm64/defconfig/gcc-8/lab-baylibre/boot-meson-gxm-khadas-vim2.txt
  HTML log:   
https://storage.kernelci.org//net-next/master/v5.3-rc1-460-g05bb520376af/arm64/defconfig/gcc-8/lab-baylibre/boot-meson-gxm-khadas-vim2.html
  Result: b27223591606 i40e: verify string count matches even on early 
return

Checks:
  revert: PASS
  verify: PASS

Parameters:
  Tree:   net-next
  URL:git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git
  Branch: master
  Target: meson-gxm-khadas-vim2
  CPU arch:   arm64
  Lab:lab-baylibre
  Compiler:   gcc-8
  Config: defconfig
  Test suite: boot

Breaking commit found:

---
commit b27223591606f59c1f7c042b8e3dc74affadf492
Author: Jacob Keller 
Date:   Tue Jul 2 08:22:58 2019 -0400

i40e: verify string count matches even on early return

Similar to i40e_get_ethtool_stats, add a goto to verify that the data
pointer for the strings lines up with the expected stats count. This
helps ensure that bugs are not introduced when adding stats.

Signed-off-by: Jacob Keller 
Tested-by: Andrew Bowers 
Signed-off-by: Jeff Kirsher 

diff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c 
b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
index ceca57a261dc..01e4615b1b4b 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
@@ -2342,7 +2342,7 @@ static void i40e_get_stat_strings(struct net_device 
*netdev, u8 *data)
}
 
if (vsi != pf->vsi[pf->lan_vsi] || pf->hw.partition_id != 1)
-   return;
+   goto check_data_pointer;
 
i40e_add_stat_strings(, i40e_gstrings_veb_stats);
 
@@ -2354,6 +2354,7 @@ static void i40e_get_stat_strings(struct net_device 
*netdev, u8 *data)
for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
i40e_add_stat_strings(, i40e_gstrings_pfc_stats, i);
 
+check_data_pointer:
WARN_ONCE(data - p != i40e_get_stats_count(netdev) * ETH_GSTRING_LEN,
  "stat strings count mismatch!");
 }
---


Git bisection log:

---
git bisect start
# good: [9e8fb25254f76cb483303d8e9a97ed80a65418fe] Merge branch 
'net-l3-l4-functional-tests'
git bisect good 9e8fb25254f76cb483303d8e9a97ed80a65418fe
# bad: [05bb520376af2c5146d3c44832c22ec3bb54d778] Merge branch '40GbE' of 
git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue
git bisect bad 05bb520376af2c5146d3c44832c22ec3bb54d778
# good: [c4ed52538cd012bd9dfe97beda6802454d367e70] Merge branch 
'drop_monitor-Various-improvements-and-cleanups'
git bisect good c4ed52538cd012bd9dfe97beda6802454d367e70
# good: [fb1b775a247ee8d846152841f780eba6cb71bcfc] net: sched: add skbedit of 
ptype action to hardware IR
git bisect good fb1b775a247ee8d846152841f780eba6cb71bcfc
# good: [ef68de56c7ad6f708bee8db5e08b83013083e757] Merge branch 
'Support-tunnels-over-VLAN-in-NFP'
git bisect good ef68de56c7ad6f708bee8db5e08b83013083e757
# good: [0969402fd5dd57268bb7547d7e5ece8fcd81157d] i40e: Update visual effect 
for advertised FEC mode.
git bisect good 0969402fd5dd57268bb7547d7e5ece8fcd81157d
# bad: [b27223591606f59c1f7c042b8e3dc74affadf492] i40e: verify string count 
matches even on early return
git bisect bad b27223591606f59c1f7c042b8e3dc74affadf492
# good: [b603f9dc20afed5e442c8713cafb94a23058] i40e: Log info when PF is 
entering and leaving Allmulti mode.
git bisect good b603f9dc20afed5e442c8713cafb94a23058
# first bad commit: [b27223591606f59c1f7c042b8e3dc74affadf492] i40e: verify 
string count matches even on early return
---

Re: [PATCH v2] asm-generic: fix variable 'p4d' set but not used

[Arnd Bergmann]

On Wed, Aug 7, 2019 at 1:29 AM Qian Cai  wrote:
>
> A compiler throws a warning on an arm64 system since the
> commit 9849a5697d3d ("arch, mm: convert all architectures to use
> 5level-fixup.h"),
>
> mm/kasan/init.c: In function 'kasan_free_p4d':
> mm/kasan/init.c:344:9: warning: variable 'p4d' set but not used
> [-Wunused-but-set-variable]
>  p4d_t *p4d;
> ^~~
>
> because p4d_none() in "5level-fixup.h" is compiled away while it is a
> static inline function in "pgtable-nopud.h". However, if converted
> p4d_none() to a static inline there, powerpc would be unhappy as it
> reads those in assembler language in
> "arch/powerpc/include/asm/book3s/64/pgtable.h", so it needs to skip
> assembly include for the static inline C function. While at it,
> converted a few similar functions to be consistent with the ones in
> "pgtable-nopud.h".
>
> Signed-off-by: Qian Cai 

Acked-by: Arnd Bergmann 

linux-next: build failure after merge of the akpm-current tree

[Stephen Rothwell]

Hi all,

After merging the akpm-current tree, today's linux-next build (arm
multi_v7_defconfig) failed like this:

In file included from include/linux/kernel.h:11,
 from kernel/events/uprobes.c:12:
kernel/events/uprobes.c: In function 'uprobe_write_opcode':
include/linux/compiler.h:350:38: error: call to '__compiletime_assert_557' 
declared with attribute error: BUILD_BUG failed
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^
include/linux/compiler.h:331:4: note: in definition of macro 
'__compiletime_assert'
prefix ## suffix();\
^~
include/linux/compiler.h:350:2: note: in expansion of macro 
'_compiletime_assert'
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^~~
include/linux/build_bug.h:39:37: note: in expansion of macro 
'compiletime_assert'
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
 ^~
include/linux/build_bug.h:59:21: note: in expansion of macro 'BUILD_BUG_ON_MSG'
 #define BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed")
 ^~~~
include/linux/huge_mm.h:272:27: note: in expansion of macro 'BUILD_BUG'
 #define HPAGE_PMD_MASK ({ BUILD_BUG(); 0; })
   ^
kernel/events/uprobes.c:557:39: note: in expansion of macro 'HPAGE_PMD_MASK'
   collapse_pte_mapped_thp(mm, vaddr & HPAGE_PMD_MASK);
   ^~

Caused by commit

  9cc0b998b380 ("uprobe: collapse THP pmd after removing all uprobes")

I have reverted that commit for today.

-- 
Cheers,
Stephen Rothwell


pgph5VGQgzDpW.pgp
Description: OpenPGP digital signature

Re: [PATCH v2] ALSA: pcm: fix multiple memory leak bugs

[Wenwen Wang]

On Wed, Aug 7, 2019 at 3:18 AM Takashi Iwai  wrote:
>
> On Wed, 07 Aug 2019 09:09:59 +0200,
> Wenwen Wang wrote:
> >
> > In hiface_pcm_init(), 'rt' is firstly allocated through kzalloc(). Later
> > on, hiface_pcm_init_urb() is invoked to initialize 'rt->out_urbs[i]'. In
> > hiface_pcm_init_urb(), 'rt->out_urbs[i].buffer' is allocated through
> > kzalloc().  However, if hiface_pcm_init_urb() fails, both 'rt' and
> > 'rt->out_urbs[i].buffer' are not deallocated, leading to memory leak bugs.
> > Also, 'rt->out_urbs[i].buffer' is not deallocated if snd_pcm_new() fails.
> >
> > To fix the above issues, free 'rt' and 'rt->out_urbs[i].buffer'.
> >
> > Signed-off-by: Wenwen Wang 
> > ---
> >  sound/usb/hiface/pcm.c | 8 +++-
> >  1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/sound/usb/hiface/pcm.c b/sound/usb/hiface/pcm.c
> > index 14fc1e1..9b132aa 100644
> > --- a/sound/usb/hiface/pcm.c
> > +++ b/sound/usb/hiface/pcm.c
> > @@ -599,12 +599,18 @@ int hiface_pcm_init(struct hiface_chip *chip, u8
> > extra_freq)
> > for (i = 0; i < PCM_N_URBS; i++) {
> > ret = hiface_pcm_init_urb(>out_urbs[i], chip, OUT_EP,
> > hiface_pcm_out_urb_handler);
> > -   if (ret < 0)
> > +   if (ret < 0) {
> > +   for (; i >= 0; i--)
> > +   kfree(rt->out_urbs[i].buffer);
> > +   kfree(rt);
> > return ret;
> > +   }
> > }
> >
> > ret = snd_pcm_new(chip->card, "USB-SPDIF Audio", 0, 1, 0, );
> > if (ret < 0) {
> > +   for (i = 0; i < PCM_N_URBS; i++)
> > +   kfree(rt->out_urbs[i].buffer);
> > kfree(rt);
> > dev_err(>dev->dev, "Cannot create pcm instance\n");
> > return ret;
>
> The fixes look correct, but since we can unconditionally call kfree()
> for NULL, both error paths can be unified as:
>
> for (i = 0; i < PCM_N_URBS; i++)
> kfree(rt->out_urbs[i].buffer);
> kfree(rt);
>
> and this would be better to be put in the common path at the end and
> do "goto error" or such from both places.

I will rework the patch and revise the subject line.

> BTW, your patch doesn't seem cleanly applicable in anyway because the
> tabs are converted to spaces.  Please check the mail setup.
>
> Also, please try to make the subject line more unique.  This is about
> hiface driver, so "ALSA: hiface: xxx" should be more appropriate.

I will also check my mail setup. Thanks!

Wenwen

Re: [Intel-wired-lan] MDI errors during resume from ACPI S3 (suspend to ram)

[Neftin, Sasha]

On 8/6/2019 18:53, mario.limoncie...@dell.com wrote:

-Original Message-
From: Paul Menzel 
Sent: Tuesday, August 6, 2019 10:36 AM
To: Jeff Kirsher
Cc: intel-wired-...@lists.osuosl.org; Linux Kernel Mailing List; Limonciello, 
Mario
Subject: MDI errors during resume from ACPI S3 (suspend to ram)

Dear Linux folks,


Trying to decrease the resume time of Linux 5.3-rc3 on the Dell OptiPlex
5040 with the device below

 $ lspci -nn -s 00:1f.6
 00:1f.6 Ethernet controller [0200]: Intel Corporation Ethernet Connection 
(2)
I219-V [8086:15b8] (rev 31)

pm-graph’s script `sleepgraph.py` shows, that the driver *e1000e* takes
around 400 ms, which is quite a lot. The call graph trace shows that
`e1000e_read_phy_reg_mdic()` is responsible for a lot of those. From
`drivers/net/ethernet/intel/e1000e/phy.c` [1]:

 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
 udelay(50);
 mdic = er32(MDIC);
 if (mdic & E1000_MDIC_READY)
 break;
 }
 if (!(mdic & E1000_MDIC_READY)) {
 e_dbg("MDI Read did not complete\n");
 return -E1000_ERR_PHY;
 }
 if (mdic & E1000_MDIC_ERROR) {
 e_dbg("MDI Error\n");
 return -E1000_ERR_PHY;
 }

Unfortunately, errors are not logged if dynamic debug is disabled,
so rebuilding the Linux kernel with `CONFIG_DYNAMIC_DEBUG`, and

 echo "file drivers/net/ethernet/* +p" | sudo tee
/sys/kernel/debug/dynamic_debug/control

I got the messages below.

 [ 4159.204192] e1000e :00:1f.6 net00: MDI Error
 [ 4160.267950] e1000e :00:1f.6 net00: MDI Write did not complete
 [ 4160.359855] e1000e :00:1f.6 net00: MDI Error

Can you please shed a little more light into these errors? Please
find the full log attached.


Kind regards,

Paul


[1]:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/n
et/ethernet/intel/e1000e/phy.c#n206


Strictly as a reference point you may consider trying the out-of-tree driver to 
see if these
behaviors persist.

https://sourceforge.net/projects/e1000/

___
Intel-wired-lan mailing list
intel-wired-...@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan

We are using external PHY. Required ~200 ms to complete MDIC transaction 
(depended on the project). You need to take to consider this time before 
access to the PHY. I do not recommend decrease timer in a 
'e1000e_read_phy_reg_mdic()' method. We could hit on wrong MDI access.

Re: [PATCH v2] ALSA: pcm: fix multiple memory leak bugs

[Takashi Iwai]

On Wed, 07 Aug 2019 09:09:59 +0200,
Wenwen Wang wrote:
> 
> In hiface_pcm_init(), 'rt' is firstly allocated through kzalloc(). Later
> on, hiface_pcm_init_urb() is invoked to initialize 'rt->out_urbs[i]'. In
> hiface_pcm_init_urb(), 'rt->out_urbs[i].buffer' is allocated through
> kzalloc().  However, if hiface_pcm_init_urb() fails, both 'rt' and
> 'rt->out_urbs[i].buffer' are not deallocated, leading to memory leak bugs.
> Also, 'rt->out_urbs[i].buffer' is not deallocated if snd_pcm_new() fails.
> 
> To fix the above issues, free 'rt' and 'rt->out_urbs[i].buffer'.
> 
> Signed-off-by: Wenwen Wang 
> ---
>  sound/usb/hiface/pcm.c | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/sound/usb/hiface/pcm.c b/sound/usb/hiface/pcm.c
> index 14fc1e1..9b132aa 100644
> --- a/sound/usb/hiface/pcm.c
> +++ b/sound/usb/hiface/pcm.c
> @@ -599,12 +599,18 @@ int hiface_pcm_init(struct hiface_chip *chip, u8
> extra_freq)
> for (i = 0; i < PCM_N_URBS; i++) {
> ret = hiface_pcm_init_urb(>out_urbs[i], chip, OUT_EP,
> hiface_pcm_out_urb_handler);
> -   if (ret < 0)
> +   if (ret < 0) {
> +   for (; i >= 0; i--)
> +   kfree(rt->out_urbs[i].buffer);
> +   kfree(rt);
> return ret;
> +   }
> }
> 
> ret = snd_pcm_new(chip->card, "USB-SPDIF Audio", 0, 1, 0, );
> if (ret < 0) {
> +   for (i = 0; i < PCM_N_URBS; i++)
> +   kfree(rt->out_urbs[i].buffer);
> kfree(rt);
> dev_err(>dev->dev, "Cannot create pcm instance\n");
> return ret;

The fixes look correct, but since we can unconditionally call kfree()
for NULL, both error paths can be unified as:

for (i = 0; i < PCM_N_URBS; i++)
kfree(rt->out_urbs[i].buffer);
kfree(rt);

and this would be better to be put in the common path at the end and
do "goto error" or such from both places.


BTW, your patch doesn't seem cleanly applicable in anyway because the
tabs are converted to spaces.  Please check the mail setup.

Also, please try to make the subject line more unique.  This is about
hiface driver, so "ALSA: hiface: xxx" should be more appropriate.


thanks,

Takashi