date:20210323



s/unconditonally/unconditionally/

Signed-off-by: Bhaskar Chowdhury 
---
 sound/core/pcm_native.c | 80 -
 1 file changed, 40 insertions(+), 40 deletions(-)

diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
index 17a85f4815d5..9884961bca7d 100644
--- a/sound/core/pcm_native.c
+++ b/sound/core/pcm_native.c

-   return 0; /* unconditonally stop all substreams */
+   return 0; /* unconditionally stop all substreams */
 }

--
2.30.1

Re: [PATCH RESEND 0/7] gpio-rockchip driver

2021-03-23 Thread jay...@rock-chips.com

I'm forget to send-to include Bartosz, I'll remember in next version

--
jay...@rock-chips.com
>Separate gpio driver from pinctrl driver, and support v2 controller.
>
>Jianqun Xu (7):
>  pinctrl/rockchip: separate struct rockchip_pin_bank to a head file
>  pinctrl/pinctrl-rockchip.h: add pinctrl device to gpio bank struct
>  gpio: separate gpio driver from pinctrl-rockchip driver
>  gpio/rockchip: use struct rockchip_gpio_regs for gpio controller
>  gpio/rockchip: support next version gpio controller
>  gpio/rockchip: always enable clock for gpio controller
>  gpio/rockchip: drop irq_gc_lock/irq_gc_unlock for irq set type
>
> drivers/gpio/Kconfig   |   8 +
> drivers/gpio/Makefile  |   1 +
> drivers/gpio/gpio-rockchip.c   | 758 
> drivers/pinctrl/pinctrl-rockchip.c | 909 +
> drivers/pinctrl/pinctrl-rockchip.h | 286 +
> 5 files changed, 1072 insertions(+), 890 deletions(-)
> create mode 100644 drivers/gpio/gpio-rockchip.c
> create mode 100644 drivers/pinctrl/pinctrl-rockchip.h
>
>--
>2.25.1
>
>
>

Re: [PATCH 6/6] arm64: dts: qcom: sc7280: Add nodes to boot WPSS

2021-03-23 Thread Sibi Sankar


On 2021-03-24 03:36, Stephen Boyd wrote:

Quoting Bjorn Andersson (2021-03-13 20:16:39)

On Sat 13 Mar 15:46 CST 2021, Stephen Boyd wrote:

> Quoting Sibi Sankar (2021-03-08 21:51:51)
> > Add miscellaneous nodes to boot the Wireless Processor Subsystem on
>
> Maybe add (WPSS) after the name so we know they're related.
>
> > SC7280 SoCs.
> >
> > Signed-off-by: Sibi Sankar 
> > ---
> >
> > https://patchwork.kernel.org/project/linux-arm-msm/list/?series=438217
> > Depends on ipcc dt node enablement from ^^
> >
> >  arch/arm64/boot/dts/qcom/sc7280.dtsi | 143 
+++
> >  1 file changed, 143 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index 18637c369c1d..4f03c468df51 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -244,12 +251,131 @@
> > reg = <0 0x8000 0 0>;
> > };
> >
> > +   tcsr_mutex: hwlock {
> > +   compatible = "qcom,tcsr-mutex";
> > +   syscon = <&tcsr_mutex_regs 0 0x1000>;
> > +   #hwlock-cells = <1>;
> > +   };
>
> Is this node in the right place? I think the node above it is 'memory'?
> In which case 'hwlock' comes before 'memory' alphabetically.
>

Thanks for spotting this, as it's no longer acceptable to have a
standalone "syscon" node I was asked to rewrite the binding for this a
few months ago. So the tcsr_mutex should now be represented with a reg
under /soc.


Oh nice, I wasn't aware.


> > +   #interrupt-cells = <2>;
> > +   };
> > +   };
> > +
> > +   smp2p-mpss {
> > +   compatible = "qcom,smp2p";
> > +   qcom,smem = <435>, <428>;
> > +   interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
> > +IPCC_MPROC_SIGNAL_SMP2P
> > +IRQ_TYPE_EDGE_RISING>;
> > +   mboxes = <&ipcc IPCC_CLIENT_MPSS
> > +   IPCC_MPROC_SIGNAL_SMP2P>;
> > +
> > +   qcom,local-pid = <0>;
> > +   qcom,remote-pid = <1>;
> > +
> > +   modem_smp2p_out: master-kernel {
> > +   qcom,entry-name = "master-kernel";
> > +   #qcom,smem-state-cells = <1>;
> > +   };
> > +
> > +   modem_smp2p_in: slave-kernel {
> > +   qcom,entry-name = "slave-kernel";
>
> Do these names need to have 'master' and 'slave' in them? We're trying
> to avoid these terms. See Documentation/process/coding-style.rst Section
> 4 naming.
>

They need to match the naming in the firmware, but I would welcome a
future change to something in line with the coding style and simply 
more

descriptive.



Sibi can this be done? I think it's still pretty early days for the
firmware so hopefully the terms can be replaced with something
different.


I'll discuss the ask with the modem fw team and
get back.

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.

linux-next: build warning after merge of the amdgpu tree

2021-03-23 Thread Stephen Rothwell

Hi all,

After merging the amdgpu tree, today's linux-next build (htmldocs)
produced this warning:

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:398: warning: Incorrect use 
of kernel-doc format:  * @crc_rd_wrk

Introduced by commit

  bbf514b0c626 ("drm/amd/display: Add kernel doc to crc_rd_wrk field")

It is missing a ':' after 'crc_rd_wrk'.

-- 
Cheers,
Stephen Rothwell


pgp5sMbR0RMBB.pgp
Description: OpenPGP digital signature

Re: [PATCH] lib: fix kconfig dependency on ARCH_WANT_FRAME_POINTERS

2021-03-23 Thread Julian Braha

On Monday, March 22, 2021 3:43:41 AM EDT you wrote:
> Hi Julian,
> 
> On Sun, Mar 21, 2021 at 11:40 PM Julian Braha  wrote:
> > On Sunday, March 21, 2021 2:28:43 PM EDT you wrote:
> > > On Sat, Mar 20, 2021 at 1:17 AM Julian Braha  
> > > wrote:
> > > > When LATENCYTOP is enabled and ARCH_WANT_FRAME_POINTERS
> > > > is disabled, Kbuild gives the following warning:
> > > >
> > > > WARNING: unmet direct dependencies detected for FRAME_POINTER
> > > >   Depends on [n]: DEBUG_KERNEL [=y] && (M68K || UML || SUPERH) || 
> > > > ARCH_WANT_FRAME_POINTERS [=n] || MCOUNT [=n]
> > > >   Selected by [y]:
> > > >   - LATENCYTOP [=y] && DEBUG_KERNEL [=y] && STACKTRACE_SUPPORT [=y] && 
> > > > PROC_FS [=y] && !MIPS && !PPC && !S390 && !MICROBLAZE && !ARM && !ARC 
> > > > && !X86
> > > >
> > > > This is because LATENCYTOP selects FRAME_POINTER,
> > > > without selecting or depending on ARCH_WANT_FRAME_POINTERS,
> > > > despite FRAME_POINTER depending on ARCH_WANT_FRAME_POINTERS.
> > > >
> > > > Signed-off-by: Julian Braha 
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/lib/Kconfig.debug
> > > > +++ b/lib/Kconfig.debug
> > > > @@ -1675,6 +1675,7 @@ config LATENCYTOP
> > > > depends on DEBUG_KERNEL
> > > > depends on STACKTRACE_SUPPORT
> > > > depends on PROC_FS
> > > > +   select ARCH_WANT_FRAME_POINTERS if !MIPS && !PPC && !S390 && 
> > > > !MICROBLAZE && !ARM && !ARC && !X86
> > >
> > > ARCH_WANT_FRAME_POINTERS is a symbol that is only to be selected by
> > > architecture-specific configuration, and must not be overridden:
> > >
> > > # Select this config option from the architecture Kconfig, if it
> > > # is preferred to always offer frame pointers as a config
> > > # option on the architecture (regardless of KERNEL_DEBUG):
> > >
> > > Probably this should be turned into a depends instead?
> > >
> > > > select FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE 
> > > > && !ARM && !ARC && !X86
> > > > select KALLSYMS
> > > > select KALLSYMS_ALL
> 
> > Making this a 'depends' causes a recursive dependency error.
> > Any other ideas?
> 
> What about
> 
> -select FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE &&
> !ARM && !ARC && !X86
> +depends on FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE
> && !ARM && !ARC && !X86
> 
> ?
> 
> Gr{oetje,eeting}s,
> 
> Geert
> 
> 

Hi Geert,

Sadly, this won't work either. In Kconfig, 'depends' cannot have an 'if' after 
it (only 'select' can.)
Kbuild gives an error for this.

- Julian Braha

[PATCH 7/7] gpio/rockchip: drop irq_gc_lock/irq_gc_unlock for irq set type

There has spin lock for irq set type already, so drop irq_gc_lock and
irq_gc_unlock.

Signed-off-by: Jianqun Xu 
---
 drivers/gpio/gpio-rockchip.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index 048e7eecddba..c9c55614bbef 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -406,7 +406,6 @@ static int rockchip_irq_set_type(struct irq_data *d, 
unsigned int type)
irq_set_handler_locked(d, handle_level_irq);
 
raw_spin_lock_irqsave(&bank->slock, flags);
-   irq_gc_lock(gc);
 
level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
@@ -461,7 +460,6 @@ static int rockchip_irq_set_type(struct irq_data *d, 
unsigned int type)
rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
 out:
-   irq_gc_unlock(gc);
raw_spin_unlock_irqrestore(&bank->slock, flags);
 
return ret;
-- 
2.25.1

[PATCH 6/7] gpio/rockchip: always enable clock for gpio controller

Since gate and ungate pclk of gpio has very litte benifit for system
power consumption, just keep it always ungate.

Signed-off-by: Jianqun Xu 
---
 drivers/gpio/gpio-rockchip.c | 68 +---
 1 file changed, 9 insertions(+), 59 deletions(-)

diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index 92aaf1848449..048e7eecddba 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -139,17 +139,8 @@ static int rockchip_gpio_get_direction(struct gpio_chip 
*chip,
 {
struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
u32 data;
-   int ret;
 
-   ret = clk_enable(bank->clk);
-   if (ret < 0) {
-   dev_err(bank->drvdata->dev,
-   "failed to enable clock for bank %s\n", bank->name);
-   return ret;
-   }
data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
-   clk_disable(bank->clk);
-
if (data & BIT(offset))
return GPIO_LINE_DIRECTION_OUT;
 
@@ -163,11 +154,9 @@ static int rockchip_gpio_set_direction(struct gpio_chip 
*chip,
unsigned long flags;
u32 data = input ? 0 : 1;
 
-   clk_enable(bank->clk);
raw_spin_lock_irqsave(&bank->slock, flags);
rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
raw_spin_unlock_irqrestore(&bank->slock, flags);
-   clk_disable(bank->clk);
 
return 0;
 }
@@ -178,11 +167,9 @@ static void rockchip_gpio_set(struct gpio_chip *gc, 
unsigned int offset,
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
unsigned long flags;
 
-   clk_enable(bank->clk);
raw_spin_lock_irqsave(&bank->slock, flags);
rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
raw_spin_unlock_irqrestore(&bank->slock, flags);
-   clk_disable(bank->clk);
 }
 
 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
@@ -190,11 +177,10 @@ static int rockchip_gpio_get(struct gpio_chip *gc, 
unsigned int offset)
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
u32 data;
 
-   clk_enable(bank->clk);
data = readl(bank->reg_base + bank->gpio_regs->ext_port);
-   clk_disable(bank->clk);
data >>= offset;
data &= 1;
+
return data;
 }
 
@@ -315,9 +301,7 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, 
unsigned int offset)
if (!bank->domain)
return -ENXIO;
 
-   clk_enable(bank->clk);
virq = irq_create_mapping(bank->domain, offset);
-   clk_disable(bank->clk);
 
return (virq) ? : -ENXIO;
 }
@@ -409,7 +393,6 @@ static int rockchip_irq_set_type(struct irq_data *d, 
unsigned int type)
unsigned long flags;
int ret = 0;
 
-   clk_enable(bank->clk);
raw_spin_lock_irqsave(&bank->slock, flags);
 
rockchip_gpio_writel_bit(bank, d->hwirq, 0,
@@ -480,7 +463,6 @@ static int rockchip_irq_set_type(struct irq_data *d, 
unsigned int type)
 out:
irq_gc_unlock(gc);
raw_spin_unlock_irqrestore(&bank->slock, flags);
-   clk_disable(bank->clk);
 
return ret;
 }
@@ -490,10 +472,8 @@ static void rockchip_irq_suspend(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
 
-   clk_enable(bank->clk);
bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
-   clk_disable(bank->clk);
 }
 
 static void rockchip_irq_resume(struct irq_data *d)
@@ -501,27 +481,7 @@ static void rockchip_irq_resume(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
 
-   clk_enable(bank->clk);
irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
-   clk_disable(bank->clk);
-}
-
-static void rockchip_irq_enable(struct irq_data *d)
-{
-   struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-   struct rockchip_pin_bank *bank = gc->private;
-
-   clk_enable(bank->clk);
-   irq_gc_mask_clr_bit(d);
-}
-
-static void rockchip_irq_disable(struct irq_data *d)
-{
-   struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-   struct rockchip_pin_bank *bank = gc->private;
-
-   irq_gc_mask_set_bit(d);
-   clk_disable(bank->clk);
 }
 
 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
@@ -530,19 +490,11 @@ static int rockchip_interrupts_register(struct 
rockchip_pin_bank *bank)
struct irq_chip_generic *gc;
int ret;
 
-   ret = clk_enable(bank->clk);
-   if (ret) {
-   dev_err(bank->dev, "failed to enable clock for bank %s\n",
-   bank->name);
-   return -EINVAL;
-   }
-
bank->domain = irq_doma

[PATCH 5/7] gpio/rockchip: support next version gpio controller

The next version gpio controller on SoCs like rk3568 have more write
mask bits for registers.

Signed-off-by: Jianqun Xu 
---
 drivers/gpio/gpio-rockchip.c   | 280 ++---
 drivers/pinctrl/pinctrl-rockchip.h |   2 +
 2 files changed, 215 insertions(+), 67 deletions(-)

diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index b12db3a523d0..92aaf1848449 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -25,6 +25,7 @@
 #include "../pinctrl/pinctrl-rockchip.h"
 
 #define GPIO_TYPE_V1   (0)   /* GPIO Version ID reserved */
+#define GPIO_TYPE_V2   (0x01000C2B)  /* GPIO Version ID 0x01000C2B */
 
 static const struct rockchip_gpio_regs gpio_regs_v1 = {
.port_dr = 0x00,
@@ -40,6 +41,99 @@ static const struct rockchip_gpio_regs gpio_regs_v1 = {
.ext_port = 0x50,
 };
 
+static const struct rockchip_gpio_regs gpio_regs_v2 = {
+   .port_dr = 0x00,
+   .port_ddr = 0x08,
+   .int_en = 0x10,
+   .int_mask = 0x18,
+   .int_type = 0x20,
+   .int_polarity = 0x28,
+   .int_bothedge = 0x30,
+   .int_status = 0x50,
+   .int_rawstatus = 0x58,
+   .debounce = 0x38,
+   .dbclk_div_en = 0x40,
+   .dbclk_div_con = 0x48,
+   .port_eoi = 0x60,
+   .ext_port = 0x70,
+   .version_id = 0x78,
+};
+
+static inline void gpio_writel_v2(u32 val, void __iomem *reg)
+{
+   writel((val & 0x) | 0x, reg);
+   writel((val >> 16) | 0x, reg + 0x4);
+}
+
+static inline u32 gpio_readl_v2(void __iomem *reg)
+{
+   return readl(reg + 0x4) << 16 | readl(reg);
+}
+
+static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
+   u32 value, unsigned int offset)
+{
+   void __iomem *reg = bank->reg_base + offset;
+
+   if (bank->gpio_type == GPIO_TYPE_V2)
+   gpio_writel_v2(value, reg);
+   else
+   writel(value, reg);
+}
+
+static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
+ unsigned int offset)
+{
+   void __iomem *reg = bank->reg_base + offset;
+   u32 value;
+
+   if (bank->gpio_type == GPIO_TYPE_V2)
+   value = gpio_readl_v2(reg);
+   else
+   value = readl(reg);
+
+   return value;
+}
+
+static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
+   u32 bit, u32 value,
+   unsigned int offset)
+{
+   void __iomem *reg = bank->reg_base + offset;
+   u32 data;
+
+   if (bank->gpio_type == GPIO_TYPE_V2) {
+   if (value)
+   data = BIT(bit % 16) | BIT(bit % 16 + 16);
+   else
+   data = BIT(bit % 16 + 16);
+   writel(data, bit >= 16 ? reg + 0x4 : reg);
+   } else {
+   data = readl(reg);
+   data &= ~BIT(bit);
+   if (value)
+   data |= BIT(bit);
+   writel(data, reg);
+   }
+}
+
+static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
+ u32 bit, unsigned int offset)
+{
+   void __iomem *reg = bank->reg_base + offset;
+   u32 data;
+
+   if (bank->gpio_type == GPIO_TYPE_V2) {
+   data = readl(bit >= 16 ? reg + 0x4 : reg);
+   data >>= bit % 16;
+   } else {
+   data = readl(reg);
+   data >>= bit;
+   }
+
+   return data & (0x1);
+}
+
 static int rockchip_gpio_get_direction(struct gpio_chip *chip,
   unsigned int offset)
 {
@@ -53,7 +147,7 @@ static int rockchip_gpio_get_direction(struct gpio_chip 
*chip,
"failed to enable clock for bank %s\n", bank->name);
return ret;
}
-   data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
+   data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
clk_disable(bank->clk);
 
if (data & BIT(offset))
@@ -67,19 +161,11 @@ static int rockchip_gpio_set_direction(struct gpio_chip 
*chip,
 {
struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
unsigned long flags;
-   u32 data;
+   u32 data = input ? 0 : 1;
 
clk_enable(bank->clk);
raw_spin_lock_irqsave(&bank->slock, flags);
-
-   data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
-   /* set bit to 1 for output, 0 for input */
-   if (!input)
-   data |= BIT(offset);
-   else
-   data &= ~BIT(offset);
-   writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr);
-
+   rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
raw_spin_unlock_irqrestore(&bank->slock, flags);
clk_disable(bank->clk);
 
@@ -90,19 +176,11 @@ static

[PATCH 1/7] pinctrl/rockchip: separate struct rockchip_pin_bank to a head file

Separate struct rockchip_pin_bank to pinctrl-rockchip.h file, which will
be used by gpio-rockchip driver in the future.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 224 +-
 drivers/pinctrl/pinctrl-rockchip.h | 244 +
 2 files changed, 245 insertions(+), 223 deletions(-)
 create mode 100644 drivers/pinctrl/pinctrl-rockchip.h

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index deabfbc74a01..625ebc1cdfd5 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -37,6 +37,7 @@
 
 #include "core.h"
 #include "pinconf.h"
+#include "pinctrl-rockchip.h"
 
 /* GPIO control registers */
 #define GPIO_SWPORT_DR 0x00
@@ -52,19 +53,6 @@
 #define GPIO_EXT_PORT  0x50
 #define GPIO_LS_SYNC   0x60
 
-enum rockchip_pinctrl_type {
-   PX30,
-   RV1108,
-   RK2928,
-   RK3066B,
-   RK3128,
-   RK3188,
-   RK3288,
-   RK3308,
-   RK3368,
-   RK3399,
-};
-
 /*
  * Encode variants of iomux registers into a type variable
  */
@@ -75,103 +63,6 @@ enum rockchip_pinctrl_type {
 #define IOMUX_WIDTH_3BIT   BIT(4)
 #define IOMUX_WIDTH_2BIT   BIT(5)
 
-/**
- * struct rockchip_iomux
- * @type: iomux variant using IOMUX_* constants
- * @offset: if initialized to -1 it will be autocalculated, by specifying
- * an initial offset value the relevant source offset can be reset
- * to a new value for autocalculating the following iomux registers.
- */
-struct rockchip_iomux {
-   int type;
-   int offset;
-};
-
-/*
- * enum type index corresponding to rockchip_perpin_drv_list arrays index.
- */
-enum rockchip_pin_drv_type {
-   DRV_TYPE_IO_DEFAULT = 0,
-   DRV_TYPE_IO_1V8_OR_3V0,
-   DRV_TYPE_IO_1V8_ONLY,
-   DRV_TYPE_IO_1V8_3V0_AUTO,
-   DRV_TYPE_IO_3V3_ONLY,
-   DRV_TYPE_MAX
-};
-
-/*
- * enum type index corresponding to rockchip_pull_list arrays index.
- */
-enum rockchip_pin_pull_type {
-   PULL_TYPE_IO_DEFAULT = 0,
-   PULL_TYPE_IO_1V8_ONLY,
-   PULL_TYPE_MAX
-};
-
-/**
- * struct rockchip_drv
- * @drv_type: drive strength variant using rockchip_perpin_drv_type
- * @offset: if initialized to -1 it will be autocalculated, by specifying
- * an initial offset value the relevant source offset can be reset
- * to a new value for autocalculating the following drive strength
- * registers. if used chips own cal_drv func instead to calculate
- * registers offset, the variant could be ignored.
- */
-struct rockchip_drv {
-   enum rockchip_pin_drv_type  drv_type;
-   int offset;
-};
-
-/**
- * struct rockchip_pin_bank
- * @reg_base: register base of the gpio bank
- * @regmap_pull: optional separate register for additional pull settings
- * @clk: clock of the gpio bank
- * @irq: interrupt of the gpio bank
- * @saved_masks: Saved content of GPIO_INTEN at suspend time.
- * @pin_base: first pin number
- * @nr_pins: number of pins in this bank
- * @name: name of the bank
- * @bank_num: number of the bank, to account for holes
- * @iomux: array describing the 4 iomux sources of the bank
- * @drv: array describing the 4 drive strength sources of the bank
- * @pull_type: array describing the 4 pull type sources of the bank
- * @valid: is all necessary information present
- * @of_node: dt node of this bank
- * @drvdata: common pinctrl basedata
- * @domain: irqdomain of the gpio bank
- * @gpio_chip: gpiolib chip
- * @grange: gpio range
- * @slock: spinlock for the gpio bank
- * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
- * @recalced_mask: bit mask to indicate a need to recalulate the mask
- * @route_mask: bits describing the routing pins of per bank
- */
-struct rockchip_pin_bank {
-   void __iomem*reg_base;
-   struct regmap   *regmap_pull;
-   struct clk  *clk;
-   int irq;
-   u32 saved_masks;
-   u32 pin_base;
-   u8  nr_pins;
-   char*name;
-   u8  bank_num;
-   struct rockchip_iomux   iomux[4];
-   struct rockchip_drv drv[4];
-   enum rockchip_pin_pull_type pull_type[4];
-   boolvalid;
-   struct device_node  *of_node;
-   struct rockchip_pinctrl *drvdata;
-   struct irq_domain   *domain;
-   struct gpio_chipgpio_chip;
-   struct pinctrl_gpio_range   grange;
-   raw_spinlock_t  slock;
-   u32 toggle_edge_mode;
-   u32 recalced_mask;
-   u32

[PATCH] scsi: lpfc: A mundane typo fix



s/conditons/conditions/

Signed-off-by: Bhaskar Chowdhury 
---
 drivers/scsi/lpfc/lpfc_els.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/scsi/lpfc/lpfc_els.c b/drivers/scsi/lpfc/lpfc_els.c
index f0a758138ae8..04fb95edc5b0 100644
--- a/drivers/scsi/lpfc/lpfc_els.c
+++ b/drivers/scsi/lpfc/lpfc_els.c
@@ -1912,7 +1912,7 @@ lpfc_cmpl_els_rrq(struct lpfc_hba *phba, struct 
lpfc_iocbq *cmdiocb,
  * ndlp on the vport node list that matches the remote node ID from the
  * PLOGI response IOCB. If such ndlp does not exist, the PLOGI is simply
  * ignored and command IOCB released. The PLOGI response IOCB status is
- * checked for error conditons. If there is error status reported, PLOGI
+ * checked for error conditions. If there is error status reported, PLOGI
  * retry shall be attempted by invoking the lpfc_els_retry() routine.
  * Otherwise, the lpfc_plogi_confirm_nport() routine shall be invoked on
  * the ndlp and the NLP_EVT_CMPL_PLOGI state to the Discover State Machine
--
2.30.1

[PATCH 4/7] gpio/rockchip: use struct rockchip_gpio_regs for gpio controller

Store register offsets in the struct rockchip_gpio_regs, this patch
prepare for the driver update for new gpio controller.

Signed-off-by: Jianqun Xu 
---
 drivers/gpio/gpio-rockchip.c   | 85 --
 drivers/pinctrl/pinctrl-rockchip.h | 38 +
 2 files changed, 84 insertions(+), 39 deletions(-)

diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index 03a3d251faae..b12db3a523d0 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -24,19 +24,21 @@
 #include "../pinctrl/core.h"
 #include "../pinctrl/pinctrl-rockchip.h"
 
-/* GPIO control registers */
-#define GPIO_SWPORT_DR 0x00
-#define GPIO_SWPORT_DDR0x04
-#define GPIO_INTEN 0x30
-#define GPIO_INTMASK   0x34
-#define GPIO_INTTYPE_LEVEL 0x38
-#define GPIO_INT_POLARITY  0x3c
-#define GPIO_INT_STATUS0x40
-#define GPIO_INT_RAWSTATUS 0x44
-#define GPIO_DEBOUNCE  0x48
-#define GPIO_PORTS_EOI 0x4c
-#define GPIO_EXT_PORT  0x50
-#define GPIO_LS_SYNC   0x60
+#define GPIO_TYPE_V1   (0)   /* GPIO Version ID reserved */
+
+static const struct rockchip_gpio_regs gpio_regs_v1 = {
+   .port_dr = 0x00,
+   .port_ddr = 0x04,
+   .int_en = 0x30,
+   .int_mask = 0x34,
+   .int_type = 0x38,
+   .int_polarity = 0x3c,
+   .int_status = 0x40,
+   .int_rawstatus = 0x44,
+   .debounce = 0x48,
+   .port_eoi = 0x4c,
+   .ext_port = 0x50,
+};
 
 static int rockchip_gpio_get_direction(struct gpio_chip *chip,
   unsigned int offset)
@@ -51,7 +53,7 @@ static int rockchip_gpio_get_direction(struct gpio_chip *chip,
"failed to enable clock for bank %s\n", bank->name);
return ret;
}
-   data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
+   data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
clk_disable(bank->clk);
 
if (data & BIT(offset))
@@ -70,13 +72,13 @@ static int rockchip_gpio_set_direction(struct gpio_chip 
*chip,
clk_enable(bank->clk);
raw_spin_lock_irqsave(&bank->slock, flags);
 
-   data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
+   data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
/* set bit to 1 for output, 0 for input */
if (!input)
data |= BIT(offset);
else
data &= ~BIT(offset);
-   writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
+   writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr);
 
raw_spin_unlock_irqrestore(&bank->slock, flags);
clk_disable(bank->clk);
@@ -88,7 +90,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned 
int offset,
  int value)
 {
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
-   void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
+   void __iomem *reg = bank->reg_base + bank->gpio_regs->port_dr;
unsigned long flags;
u32 data;
 
@@ -111,7 +113,7 @@ static int rockchip_gpio_get(struct gpio_chip *gc, unsigned 
int offset)
u32 data;
 
clk_enable(bank->clk);
-   data = readl(bank->reg_base + GPIO_EXT_PORT);
+   data = readl(bank->reg_base + bank->gpio_regs->ext_port);
clk_disable(bank->clk);
data >>= offset;
data &= 1;
@@ -122,7 +124,7 @@ static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
   unsigned int offset, bool enable)
 {
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
-   void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
+   void __iomem *reg = bank->reg_base + bank->gpio_regs->debounce;
unsigned long flags;
u32 data;
 
@@ -226,7 +228,7 @@ static void rockchip_irq_demux(struct irq_desc *desc)
 
chained_irq_enter(chip, desc);
 
-   pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
+   pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
 
while (pend) {
unsigned int irq, virq;
@@ -250,24 +252,26 @@ static void rockchip_irq_demux(struct irq_desc *desc)
u32 data, data_old, polarity;
unsigned long flags;
 
-   data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
+   data = readl_relaxed(bank->reg_base +
+bank->gpio_regs->ext_port);
do {
raw_spin_lock_irqsave(&bank->slock, flags);
 
polarity = readl_relaxed(bank->reg_base +
-GPIO_INT_POLARITY);
+
bank->gpio_regs->int_polarity);
if (data & BIT(irq))

[PATCH 3/7] gpio: separate gpio driver from pinctrl-rockchip driver

Separate the gpio driver from the pinctrl driver.

Signed-off-by: Jianqun Xu 
---
 drivers/gpio/Kconfig   |   8 +
 drivers/gpio/Makefile  |   1 +
 drivers/gpio/gpio-rockchip.c   | 657 +++
 drivers/pinctrl/pinctrl-rockchip.c | 685 +
 4 files changed, 684 insertions(+), 667 deletions(-)
 create mode 100644 drivers/gpio/gpio-rockchip.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e3607ec4c2e8..702fb6db3e46 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -508,6 +508,14 @@ config GPIO_REG
  A 32-bit single register GPIO fixed in/out implementation.  This
  can be used to represent any register as a set of GPIO signals.
 
+config GPIO_ROCKCHIP
+   tristate "Rockchip GPIO support"
+   depends on ARCH_ROCKCHIP || COMPILE_TEST
+   select GPIOLIB_IRQCHIP
+   default ARCH_ROCKCHIP
+   help
+ Say yes here to support GPIO on Rockchip SoCs.
+
 config GPIO_SAMA5D2_PIOBU
tristate "SAMA5D2 PIOBU GPIO support"
depends on MFD_SYSCON
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index c58a90a3c3b1..1432694f3b3a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -125,6 +125,7 @@ obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
 obj-$(CONFIG_GPIO_RDA) += gpio-rda.o
 obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
 obj-$(CONFIG_GPIO_REG) += gpio-reg.o
+obj-$(CONFIG_GPIO_ROCKCHIP)+= gpio-rockchip.o
 obj-$(CONFIG_ARCH_SA1100)  += gpio-sa1100.o
 obj-$(CONFIG_GPIO_SAMA5D2_PIOBU)   += gpio-sama5d2-piobu.o
 obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
new file mode 100644
index ..03a3d251faae
--- /dev/null
+++ b/drivers/gpio/gpio-rockchip.c
@@ -0,0 +1,657 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner 
+ *
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pinctrl/core.h"
+#include "../pinctrl/pinctrl-rockchip.h"
+
+/* GPIO control registers */
+#define GPIO_SWPORT_DR 0x00
+#define GPIO_SWPORT_DDR0x04
+#define GPIO_INTEN 0x30
+#define GPIO_INTMASK   0x34
+#define GPIO_INTTYPE_LEVEL 0x38
+#define GPIO_INT_POLARITY  0x3c
+#define GPIO_INT_STATUS0x40
+#define GPIO_INT_RAWSTATUS 0x44
+#define GPIO_DEBOUNCE  0x48
+#define GPIO_PORTS_EOI 0x4c
+#define GPIO_EXT_PORT  0x50
+#define GPIO_LS_SYNC   0x60
+
+static int rockchip_gpio_get_direction(struct gpio_chip *chip,
+  unsigned int offset)
+{
+   struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
+   u32 data;
+   int ret;
+
+   ret = clk_enable(bank->clk);
+   if (ret < 0) {
+   dev_err(bank->drvdata->dev,
+   "failed to enable clock for bank %s\n", bank->name);
+   return ret;
+   }
+   data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
+   clk_disable(bank->clk);
+
+   if (data & BIT(offset))
+   return GPIO_LINE_DIRECTION_OUT;
+
+   return GPIO_LINE_DIRECTION_IN;
+}
+
+static int rockchip_gpio_set_direction(struct gpio_chip *chip,
+  unsigned int offset, bool input)
+{
+   struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
+   unsigned long flags;
+   u32 data;
+
+   clk_enable(bank->clk);
+   raw_spin_lock_irqsave(&bank->slock, flags);
+
+   data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
+   /* set bit to 1 for output, 0 for input */
+   if (!input)
+   data |= BIT(offset);
+   else
+   data &= ~BIT(offset);
+   writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
+
+   raw_spin_unlock_irqrestore(&bank->slock, flags);
+   clk_disable(bank->clk);
+
+   return 0;
+}
+
+static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
+ int value)
+{
+   struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
+   void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
+   unsigned long flags;
+   u32 data;
+
+   clk_enable(bank->clk);
+   raw_spin_lock_irqsave(&bank->slock, flags);
+
+   data = readl(reg);
+   data &= ~BIT(offset);
+   if (value)
+   data |= BIT(offset);
+   writel(data, reg);
+
+   raw_spin_unlock_irqrestore(&bank->slock, flags);
+   clk_disable(bank->clk);
+}
+
+static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+   struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
+

[PATCH RESEND 0/7] gpio-rockchip driver

Separate gpio driver from pinctrl driver, and support v2 controller.

Jianqun Xu (7):
  pinctrl/rockchip: separate struct rockchip_pin_bank to a head file
  pinctrl/pinctrl-rockchip.h: add pinctrl device to gpio bank struct
  gpio: separate gpio driver from pinctrl-rockchip driver
  gpio/rockchip: use struct rockchip_gpio_regs for gpio controller
  gpio/rockchip: support next version gpio controller
  gpio/rockchip: always enable clock for gpio controller
  gpio/rockchip: drop irq_gc_lock/irq_gc_unlock for irq set type

 drivers/gpio/Kconfig   |   8 +
 drivers/gpio/Makefile  |   1 +
 drivers/gpio/gpio-rockchip.c   | 758 
 drivers/pinctrl/pinctrl-rockchip.c | 909 +
 drivers/pinctrl/pinctrl-rockchip.h | 286 +
 5 files changed, 1072 insertions(+), 890 deletions(-)
 create mode 100644 drivers/gpio/gpio-rockchip.c
 create mode 100644 drivers/pinctrl/pinctrl-rockchip.h

-- 
2.25.1

[PATCH 2/7] pinctrl/pinctrl-rockchip.h: add pinctrl device to gpio bank struct

Store a pointer from the pinctrl device for the gpio bank.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.h 
b/drivers/pinctrl/pinctrl-rockchip.h
index ba4afab2845f..20f734ce3933 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -80,6 +80,7 @@ struct rockchip_drv {
 
 /**
  * struct rockchip_pin_bank
+ * @dev: the pinctrl device bind to the bank
  * @reg_base: register base of the gpio bank
  * @regmap_pull: optional separate register for additional pull settings
  * @clk: clock of the gpio bank
@@ -104,6 +105,7 @@ struct rockchip_drv {
  * @route_mask: bits describing the routing pins of per bank
  */
 struct rockchip_pin_bank {
+   struct device   *dev;
void __iomem*reg_base;
struct regmap   *regmap_pull;
struct clk  *clk;
-- 
2.25.1

Re: [PATCH v10] i2c: virtio: add a virtio i2c frontend driver

2021-03-23 Thread Viresh Kumar

On 24-03-21, 14:41, Jie Deng wrote:
> 
> On 2021/3/24 14:09, Viresh Kumar wrote:
> > On 24-03-21, 14:05, Jie Deng wrote:
> > Or, now that I think about it a bit more, another thing we can do here is 
> > see if
> > virtqueue_get_buf() returns NULL, if it does then we should keep expecting 
> > more
> > messages as it may be early interrupt. What do you say ?
> 
> I don't think we really need this because for this device, early interrupt
> is a bad operation
> which should be avoided. I can't think of why this device need to send early
> interrupt, what
> we can do is to clarify that this means loss of the remaining requests. A
> device should never
> do this, if it does then loss is the expected result.

Fair enough.

-- 
viresh

[syzbot] possible deadlock in scheduler_tick

2021-03-23 Thread syzbot

Hello,

syzbot found the following issue on:

HEAD commit:1c273e10 Merge tag 'zonefs-5.12-rc4' of git://git.kernel.o..
git tree:   upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=13c0414ed0
kernel config:  https://syzkaller.appspot.com/x/.config?x=6abda3336c698a07
dashboard link: https://syzkaller.appspot.com/bug?extid=b282b65c2c68492df769
userspace arch: i386
syz repro:  https://syzkaller.appspot.com/x/repro.syz?x=17d86ad6d0
C reproducer:   https://syzkaller.appspot.com/x/repro.c?x=17b8497cd0

IMPORTANT: if you fix the issue, please add the following tag to the commit:
Reported-by: syzbot+b282b65c2c68492df...@syzkaller.appspotmail.com

=
WARNING: HARDIRQ-safe -> HARDIRQ-unsafe lock order detected
5.12.0-rc3-syzkaller #0 Not tainted
-
syz-executor030/8435 [HC0[0]:SC0[0]:HE0:SE1] is trying to acquire:
c90001a2a230 (&kvm->arch.pvclock_gtod_sync_lock){+.+.}-{2:2}, at: spin_lock 
include/linux/spinlock.h:354 [inline]
c90001a2a230 (&kvm->arch.pvclock_gtod_sync_lock){+.+.}-{2:2}, at: 
get_kvmclock_ns+0x25/0x390 arch/x86/kvm/x86.c:2587

and this task is already holding:
8880b9d35198 (&rq->lock){-.-.}-{2:2}, at: rq_lock kernel/sched/sched.h:1321 
[inline]
8880b9d35198 (&rq->lock){-.-.}-{2:2}, at: __schedule+0x21c/0x21b0 
kernel/sched/core.c:4990
which would create a new lock dependency:
 (&rq->lock){-.-.}-{2:2} -> (&kvm->arch.pvclock_gtod_sync_lock){+.+.}-{2:2}

but this new dependency connects a HARDIRQ-irq-safe lock:
 (&rq->lock){-.-.}-{2:2}

... which became HARDIRQ-irq-safe at:
  lock_acquire kernel/locking/lockdep.c:5510 [inline]
  lock_acquire+0x1ab/0x740 kernel/locking/lockdep.c:5475
  __raw_spin_lock include/linux/spinlock_api_smp.h:142 [inline]
  _raw_spin_lock+0x2a/0x40 kernel/locking/spinlock.c:151
  rq_lock kernel/sched/sched.h:1321 [inline]
  scheduler_tick+0xa4/0x4b0 kernel/sched/core.c:4538
  update_process_times+0x191/0x200 kernel/time/timer.c:1801
  tick_periodic+0x79/0x230 kernel/time/tick-common.c:100
  tick_handle_periodic+0x41/0x120 kernel/time/tick-common.c:112
  timer_interrupt+0x3f/0x60 arch/x86/kernel/time.c:57
  __handle_irq_event_percpu+0x303/0x8f0 kernel/irq/handle.c:156
  handle_irq_event_percpu kernel/irq/handle.c:196 [inline]
  handle_irq_event+0x102/0x290 kernel/irq/handle.c:213
  handle_level_irq+0x256/0x6e0 kernel/irq/chip.c:650
  generic_handle_irq_desc include/linux/irqdesc.h:158 [inline]
  handle_irq arch/x86/kernel/irq.c:231 [inline]
  __common_interrupt+0x9e/0x200 arch/x86/kernel/irq.c:250
  common_interrupt+0x9f/0xd0 arch/x86/kernel/irq.c:240
  asm_common_interrupt+0x1e/0x40 arch/x86/include/asm/idtentry.h:623
  __raw_spin_unlock_irqrestore include/linux/spinlock_api_smp.h:161 [inline]
  _raw_spin_unlock_irqrestore+0x38/0x70 kernel/locking/spinlock.c:191
  __setup_irq+0xc72/0x1ce0 kernel/irq/manage.c:1737
  request_threaded_irq+0x28a/0x3b0 kernel/irq/manage.c:2127
  request_irq include/linux/interrupt.h:160 [inline]
  setup_default_timer_irq arch/x86/kernel/time.c:70 [inline]
  hpet_time_init+0x28/0x42 arch/x86/kernel/time.c:82
  x86_late_time_init+0x58/0x94 arch/x86/kernel/time.c:94
  start_kernel+0x3ee/0x496 init/main.c:1028
  secondary_startup_64_no_verify+0xb0/0xbb

to a HARDIRQ-irq-unsafe lock:
 (&kvm->arch.pvclock_gtod_sync_lock){+.+.}-{2:2}

... which became HARDIRQ-irq-unsafe at:
...
  lock_acquire kernel/locking/lockdep.c:5510 [inline]
  lock_acquire+0x1ab/0x740 kernel/locking/lockdep.c:5475
  __raw_spin_lock include/linux/spinlock_api_smp.h:142 [inline]
  _raw_spin_lock+0x2a/0x40 kernel/locking/spinlock.c:151
  spin_lock include/linux/spinlock.h:354 [inline]
  kvm_synchronize_tsc+0x459/0x1230 arch/x86/kvm/x86.c:2332
  kvm_arch_vcpu_postcreate+0x73/0x180 arch/x86/kvm/x86.c:10183
  kvm_vm_ioctl_create_vcpu arch/x86/kvm/../../../virt/kvm/kvm_main.c:3239 
[inline]
  kvm_vm_ioctl+0x1b2d/0x2800 arch/x86/kvm/../../../virt/kvm/kvm_main.c:3839
  kvm_vm_compat_ioctl+0x125/0x230 arch/x86/kvm/../../../virt/kvm/kvm_main.c:4052
  __do_compat_sys_ioctl+0x1d3/0x230 fs/ioctl.c:842
  do_syscall_32_irqs_on arch/x86/entry/common.c:77 [inline]
  __do_fast_syscall_32+0x56/0x90 arch/x86/entry/common.c:140
  do_fast_syscall_32+0x2f/0x70 arch/x86/entry/common.c:165
  entry_SYSENTER_compat_after_hwframe+0x4d/0x5c

other info that might help us debug this:

 Possible interrupt unsafe locking scenario:

   CPU0CPU1
   
  lock(&kvm->arch.pvclock_gtod_sync_lock);
   local_irq_disable();
   lock(&rq->lock);
   lock(&kvm->arch.pvclock_gtod_sync_lock);
  
lock(&rq->lock);

 *** DEADLOCK ***

1 lock held by syz-executor030/8435:
 #0: 8880b9d35198 (&rq->lock){-.-.}-{2:2}, at: rq_lock 
kernel/sched/sched.h:1321 [inline]
 #0: 8880b9d35198 (&rq->lock){-.-.}-{2:2}, at: __schedule+0x21c/0x21b0

Re: [PATCH v10] i2c: virtio: add a virtio i2c frontend driver

2021-03-23 Thread Jie Deng




On 2021/3/24 14:09, Viresh Kumar wrote:

On 24-03-21, 14:05, Jie Deng wrote:
Or, now that I think about it a bit more, another thing we can do here is see if
virtqueue_get_buf() returns NULL, if it does then we should keep expecting more
messages as it may be early interrupt. What do you say ?


I don't think we really need this because for this device, early 
interrupt is a bad operation
which should be avoided. I can't think of why this device need to send 
early interrupt, what
we can do is to clarify that this means loss of the remaining requests. 
A device should never

do this, if it does then loss is the expected result.

Re: [PATCH v3 2/3] dt-bindings: power: rockchip: Convert to json-schema and extend

2021-03-23 Thread Johan Jonker

On 3/24/21 4:23 AM, Elaine Zhang wrote:
> Convert the soc/rockchip/power_domain.txt binding document to
> json-schema and move to the power bindings directory.
> Add RK3568 SoCs for rockchip power binding document.
> 
> Signed-off-by: Enric Balletbo i Serra 
> Signed-off-by: Elaine Zhang 
> ---
>  .../power/rockchip,power-controller.yaml  | 286 ++
>  .../bindings/soc/rockchip/power_domain.txt| 136 -
>  2 files changed, 286 insertions(+), 136 deletions(-)
>  create mode 100644 
> Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
>  delete mode 100644 
> Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
> 
> diff --git 
> a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml 
> b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
> new file mode 100644
> index ..0d6b8962d098
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
> @@ -0,0 +1,286 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip Power Domains
> +
> +maintainers:
> +  - Elaine Zhang 
> +  - Rob Herring 
> +  - Heiko Stuebner 
> +
> +description: |
> +  Rockchip processors include support for multiple power domains which can be

> +  powered up/down by software based on different application scenes to save 
> power.

scenes > scenarios ??

This is not a theater.
=
Scenes:
1. Something seen by a viewer; a view or prospect.
2. The place where an action or event occurs: the scene of the crime.
=
Scenarios:
1. An expected or supposed situation or sequence of events

> +
> +  Power domains contained within power-controller node are generic power 
> domain
> +  providers documented in 
> Documentation/devicetree/bindings/power/power-domain.yaml.
> +
> +  IP cores belonging to a power domain should contain a 'power-domains'
> +  property that is a phandle for the power domain node representing the 
> domain.
> +
> +properties:
> +  $nodename:
> +const: power-controller
> +
> +  compatible:
> +enum:
> +  - rockchip,px30-power-controller
> +  - rockchip,rk3036-power-controller
> +  - rockchip,rk3066-power-controller
> +  - rockchip,rk3128-power-controller
> +  - rockchip,rk3188-power-controller
> +  - rockchip,rk3228-power-controller
> +  - rockchip,rk3288-power-controller
> +  - rockchip,rk3328-power-controller
> +  - rockchip,rk3366-power-controller
> +  - rockchip,rk3368-power-controller
> +  - rockchip,rk3399-power-controller

> +  - rockchip,rk3568-power-controller

Use separate patches for a YAML conversion and adding new compatibility
strings. One action per patch.

> +
> +  '#power-domain-cells':
> +const: 1
> +
> +  '#address-cells':
> +const: 1
> +
> +  '#size-cells':
> +const: 0
> +
> +patternProperties:

> +  "^pd_[0-9a-z_]{2,10}@[0-9a-f]+$":

Here you are using "", but elsewhere in this document '' is used.
Change all to "".

> +type: object
> +description: |
> +  Represents the power domains within the power controller node as 
> documented
> +  in Documentation/devicetree/bindings/power/power-domain.yaml.
> +
> +properties:
> +
> +  '#power-domain-cells':
> +description:
> +  Must be 0 for nodes representing a single PM domain and 1 for nodes
> +  providing multiple PM domains.
> +
> +  '#address-cells':
> +const: 1
> +
> +  '#size-cells':
> +const: 0
> +
> +  reg:
> +maxItems: 1
> +description: |
> +  Power domain index. Valid values are defined in:

remove ":"

> +  "include/dt-bindings/power/px30-power.h"
> +  "include/dt-bindings/power/rk3036-power.h"
> +  "include/dt-bindings/power/rk3066-power.h"
> +  "include/dt-bindings/power/rk3128-power.h"
> +  "include/dt-bindings/power/rk3188-power.h"
> +  "include/dt-bindings/power/rk3228-power.h"
> +  "include/dt-bindings/power/rk3288-power.h"
> +  "include/dt-bindings/power/rk3328-power.h"
> +  "include/dt-bindings/power/rk3366-power.h"
> +  "include/dt-bindings/power/rk3368-power.h"
> +  "include/dt-bindings/power/rk3399-power.h"

> +  "include/dt-bindings/power/rk3399-power.h"

rk3399 > rk3568

  "include/dt-bindings/power/rk3568-power.h"

Use separate patches for a YAML conversion and adding new compatibility
strings. One action per patch.

> +
> +  clocks:
> +description: |
> +  A number of phandles to clocks that need to be enabled while power 
> domain
> +  switches state.
> +
> +  pm_qos:
> +description: |
> +  A number of phandles to qos blocks which need to be saved and 
> restored
> +  while power domain switches state.
> +
>

[tip:x86/boot] BUILD SUCCESS 4c674481dcf9974834b96622fa4b079c176f36f9

2021-03-23 Thread kernel test robot

tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 
x86/boot
branch HEAD: 4c674481dcf9974834b96622fa4b079c176f36f9  x86/setup: Merge several 
reservations of start of memory

elapsed time: 724m

configs tested: 113
configs skipped: 62

The following configs have been built successfully.
More configs may be tested in the coming days.

gcc tested configs:
arm defconfig
arm64allyesconfig
arm64   defconfig
arm  allyesconfig
arm  allmodconfig
x86_64   allyesconfig
riscvallmodconfig
i386 allyesconfig
riscvallyesconfig
powerpc redwood_defconfig
mipsar7_defconfig
m68kmac_defconfig
arm  imote2_defconfig
mips cu1000-neo_defconfig
mips  bmips_stb_defconfig
arm   milbeaut_m10v_defconfig
arm mv78xx0_defconfig
arm   h5000_defconfig
armspear3xx_defconfig
h8300   h8s-sim_defconfig
ia64defconfig
mips  pic32mzda_defconfig
arm   versatile_defconfig
shsh7785lcr_defconfig
arm  collie_defconfig
powerpcsocrates_defconfig
arm   imx_v6_v7_defconfig
armneponset_defconfig
shhp6xx_defconfig
arm orion5x_defconfig
nds32 allnoconfig
openriscdefconfig
pariscgeneric-32bit_defconfig
armmulti_v5_defconfig
mipse55_defconfig
arm  pxa910_defconfig
arm  tct_hammer_defconfig
arm lpc32xx_defconfig
powerpc mpc834x_mds_defconfig
arm pxa_defconfig
powerpc tqm8555_defconfig
powerpc   eiger_defconfig
arm  pxa168_defconfig
ia64 allmodconfig
ia64 allyesconfig
m68k allmodconfig
m68kdefconfig
m68k allyesconfig
nios2   defconfig
arc  allyesconfig
nds32   defconfig
nios2allyesconfig
cskydefconfig
alpha   defconfig
alphaallyesconfig
xtensa   allyesconfig
h8300allyesconfig
arc defconfig
sh   allmodconfig
parisc  defconfig
s390 allyesconfig
s390 allmodconfig
parisc   allyesconfig
s390defconfig
i386   tinyconfig
i386defconfig
sparcallyesconfig
sparc   defconfig
mips allyesconfig
mips allmodconfig
powerpc  allyesconfig
powerpc  allmodconfig
powerpc   allnoconfig
i386 randconfig-a003-20210323
i386 randconfig-a004-20210323
i386 randconfig-a001-20210323
i386 randconfig-a002-20210323
i386 randconfig-a006-20210323
i386 randconfig-a005-20210323
i386 randconfig-a004-20210324
i386 randconfig-a003-20210324
i386 randconfig-a001-20210324
i386 randconfig-a002-20210324
i386 randconfig-a006-20210324
i386 randconfig-a005-20210324
x86_64   randconfig-a002-20210323
x86_64   randconfig-a003-20210323
x86_64   randconfig-a006-20210323
x86_64   randconfig-a001-20210323
x86_64   randconfig-a004-20210323
x86_64   randconfig-a005-20210323
i386 randconfig-a014-20210323
i386 randconfig-a011-20210323
i386 randconfig-a015-20210323
i386 randconfig-a016-20210323
i386 randconfig-a012-20210323
i386 randconfig-a013-20210323
riscvnommu_k210_defconfig
riscvnommu_virt_defconfig
riscv allnoconfig
riscv

[PATCH v8 3/3] arm64: dts: ti: k3-j7200: Add support for higher speed modes and update delay select values for MMCSD subsystems

The following speed modes are now supported in J7200 SoC,
- HS200 and HS400 modes at 1.8 V card voltage, in MMCSD0 subsystem [1].
- UHS-I speed modes in MMCSD1 subsystem [1].

Add support for UHS-I modes by adding voltage regulator device tree nodes
and corresponding pinmux details, to power cycle and voltage switch cards.
Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
device tree nodes.

Also update the delay values for various speed modes supported, based on
the revised january 2021 J7200 datasheet[2].

[1] - section 12.3.6.1.1 MMCSD Features, in
  https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf,
  (SPRUIU1A – JULY 2020 – REVISED JANUARY 2021)

[2] - https://www.ti.com/lit/ds/symlink/dra821u.pdf,
  (SPRSP57B – APRIL 2020 – REVISED JANUARY 2021)

Signed-off-by: Aswath Govindraju 
---
 .../dts/ti/k3-j7200-common-proc-board.dts | 78 +++
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 14 +++-
 2 files changed, 90 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts 
b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index b493f939b09a..a069787e1783 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -16,6 +16,65 @@
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 
earlycon=ns16550a,mmio32,0x0280";
};
+
+   evm_12v0: fixedregulator-evm12v0 {
+   /* main supply */
+   compatible = "regulator-fixed";
+   regulator-name = "evm_12v0";
+   regulator-min-microvolt = <1200>;
+   regulator-max-microvolt = <1200>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   vsys_3v3: fixedregulator-vsys3v3 {
+   /* Output of LMS140 */
+   compatible = "regulator-fixed";
+   regulator-name = "vsys_3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   vin-supply = <&evm_12v0>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   vsys_5v0: fixedregulator-vsys5v0 {
+   /* Output of LM5140 */
+   compatible = "regulator-fixed";
+   regulator-name = "vsys_5v0";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   vin-supply = <&evm_12v0>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   vdd_mmc1: fixedregulator-sd {
+   /* Output of TPS22918  */
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_mmc1";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   enable-active-high;
+   vin-supply = <&vsys_3v3>;
+   gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
+   };
+
+   vdd_sd_dv: gpio-regulator-vdd-sd-dv {
+   /* Output of TLV71033 */
+   compatible = "regulator-gpio";
+   regulator-name = "vdd_sd_dv";
+   pinctrl-names = "default";
+   pinctrl-0 = <&vdd_sd_dv_pins_default>;
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   vin-supply = <&vsys_5v0>;
+   gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
+   states = <180 0x0>,
+<330 0x1>;
+   };
 };
 
 &wkup_pmx0 {
@@ -45,6 +104,13 @@
 };
 
 &main_pmx0 {
+   main_i2c0_pins_default: main-i2c0-pins-default {
+   pinctrl-single,pins = <
+   J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL 
*/
+   J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA 
*/
+   >;
+   };
+
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) 
ECAP0_IN_APWM_OUT.I2C1_SCL */
@@ -70,6 +136,12 @@
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS 
*/
>;
};
+
+   vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+   pinctrl-single,pins = <
+   J721E_IOPAD(0xd0, PIN_INPUT, 7) /* (T5) 
SPI0_D1.GPIO0_55 */
+   >;
+   };
 };
 
 &wkup_uart0 {
@@ -157,6 +229,10 @@
 };
 
 &main_i2c0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&main_i2c0_pins_default>;
+   clock-frequency = <40>;
+
exp1: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
@@ -206,6 +282,8 @@
/* SD card */
pinctrl-0 = <&main_mmc1_pins_default>;
pinctrl-na

[PATCH v8 2/3] arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio modules

From: Faiz Abbas 

There are 6 gpio instances inside SoC with 2 groups as show below:
Group one: wkup_gpio0, wkup_gpio1
Group two: main_gpio0, main_gpio2, main_gpio4, main_gpio6

Only one instance from each group can be used at a time. So use main_gpio0
and wkup_gpio0 in current linux context and disable the rest of the nodes.

Signed-off-by: Faiz Abbas 
Signed-off-by: Sekhar Nori 
Signed-off-by: Aswath Govindraju 
Reviewed-by: Grygorii Strashko 
---
 .../boot/dts/ti/k3-j7200-common-proc-board.dts   | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts 
b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 4a7182abccf5..b493f939b09a 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -122,6 +122,22 @@
status = "disabled";
 };
 
+&main_gpio2 {
+   status = "disabled";
+};
+
+&main_gpio4 {
+   status = "disabled";
+};
+
+&main_gpio6 {
+   status = "disabled";
+};
+
+&wkup_gpio1 {
+   status = "disabled";
+};
+
 &mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
-- 
2.17.1

[PATCH v8 1/3] arm64: dts: ti: k3-j7200: Add gpio nodes

From: Faiz Abbas 

There are 4 instances of gpio modules in main domain:
gpio0, gpio2, gpio4 and gpio6

Groups are created to provide protection between different processor
virtual worlds. Each of these modules I/O pins are muxed within the
group. Exactly one module can be selected to control the corresponding
pin by selecting it in the pad mux configuration registers.

This group in main domain pins out 69 lines (5 banks). Add DT modes for
each module instance in the main domain.

Similar to the gpio groups in main domain, there is one gpio group in
wakeup domain with 2 module instances in it.

The gpio group pins out 72 pins (6 banks) of the first 85 gpio lines. Add
DT nodes for each module instance in the wakeup domain.

Signed-off-by: Faiz Abbas 
Signed-off-by: Sekhar Nori 
Signed-off-by: Aswath Govindraju 
Reviewed-by: Grygorii Strashko 
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 72 +++
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi  | 34 +
 2 files changed, 106 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi 
b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 17477ab0fd8e..e60650a62b14 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -672,6 +672,78 @@
};
};
 
+   main_gpio0: gpio@60 {
+   compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+   reg = <0x00 0x0060 0x00 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-parent = <&main_gpio_intr>;
+   interrupts = <145>, <146>, <147>, <148>,
+<149>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   #address-cells = <0>;
+   ti,ngpio = <69>;
+   ti,davinci-gpio-unbanked = <0>;
+   power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+   clocks = <&k3_clks 105 0>;
+   clock-names = "gpio";
+   };
+
+   main_gpio2: gpio@61 {
+   compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+   reg = <0x00 0x0061 0x00 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-parent = <&main_gpio_intr>;
+   interrupts = <154>, <155>, <156>, <157>,
+<158>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   #address-cells = <0>;
+   ti,ngpio = <69>;
+   ti,davinci-gpio-unbanked = <0>;
+   power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+   clocks = <&k3_clks 107 0>;
+   clock-names = "gpio";
+   };
+
+   main_gpio4: gpio@62 {
+   compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+   reg = <0x00 0x0062 0x00 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-parent = <&main_gpio_intr>;
+   interrupts = <163>, <164>, <165>, <166>,
+<167>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   #address-cells = <0>;
+   ti,ngpio = <69>;
+   ti,davinci-gpio-unbanked = <0>;
+   power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+   clocks = <&k3_clks 109 0>;
+   clock-names = "gpio";
+   };
+
+   main_gpio6: gpio@63 {
+   compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+   reg = <0x00 0x0063 0x00 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-parent = <&main_gpio_intr>;
+   interrupts = <172>, <173>, <174>, <175>,
+<176>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   #address-cells = <0>;
+   ti,ngpio = <69>;
+   ti,davinci-gpio-unbanked = <0>;
+   power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+   clocks = <&k3_clks 111 0>;
+   clock-names = "gpio";
+   };
+
main_r5fss0: r5fss@5c0 {
compatible = "ti,j7200-r5fss";
ti,cluster-mode = <1>;
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi 
b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 5408ec815d58..4e4ea7655fe2 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -107,6 +107,40 @@
ti,interrupt-ranges = <16 960 16>;
};
 
+   wkup_gpio0: gpio@4211 {
+   compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+   reg = <0x00 0x4211 0x00 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-parent = <&wkup_gpio_intr>;
+   interrupts =

[PATCH v8 0/3] J7200: Add support for GPIO and higher speed modes in MMCSD subsystems

The following series of patches
- Add support for GPIO subsystem in main and wakeup domains.
- Add voltage regulator device tree nodes and their corresponding pinmux
  to support power cycle and voltage switch required for UHS-I modes
- sets respective tags in sdhci0 node to support higher speeds
- remove no-1-8-v tag from sdhci1 node to support UHS-I modes
- Update delay values for various speed modes supported.


test logs
- eMMC HS400 speed mode
  https://pastebin.ubuntu.com/p/pRzV2ZvSJZ/

- SD SDR104 speed mode
  https://pastebin.ubuntu.com/p/n64PNdDy2v/  
  
- GPIO logs
  https://pastebin.ubuntu.com/p/HDBBMwMcdj/

Changes since v7:
- Added the voltage regulator nodes to indicate the complete
  power flow for MMCSD1 subsystem
- Corrected minor errors in DT nodes
- Reran the tests.
- Rebased the series

Changes since v6:
- Corrected the node name from vdd_sd_dv_pins_default to
  vdd-sd-dv-pins-default

Changes since v5:
- Corrected the link in patch 3 as it broken.
- Added the version number for the references used in patch 3.
- picked up reviewed-by from grygorii for patches 1 and 2.

Changes since v4:
- Added main_i2c0 pinmux required for doing power cycles to MMCSD1
  subsystem
- Updated delay values for various speed modes supported
- Corrected the ti,ngpio property to indicate highest gpio lines that
  can be accessed.
- Reran the performace tests

Changes since v3:
- Removed patch (1 in v3).
- Rebased and included patches that add support for GPIO from series [1].
- Re-ran the performace tests for SD and eMMC.

Changes since v2:
- Added main_gpio0 DT node
- Added voltage regulator device tree nodes required to support UHS-I modes

Changes since v1:
- squashed the two patches into one
- added performance logs for the above mentioned speed modes


Aswath Govindraju (1):
  arm64: dts: ti: k3-j7200: Add support for higher speed modes and
update delay select values for MMCSD subsystems

Faiz Abbas (2):
  arm64: dts: ti: k3-j7200: Add gpio nodes
  arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio
modules

 .../dts/ti/k3-j7200-common-proc-board.dts | 94 +++
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 86 -
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi  | 34 +++
 3 files changed, 212 insertions(+), 2 deletions(-)

-- 
2.17.1

[PATCH v5 1/2] usbip: tools: add options and examples in man page related to device mode

2021-03-23 Thread Hongren Zheng (Zenithal)

The commit e0546fd8b748 ("usbip: tools: Start using VUDC backend in
usbip tools") implemented device mode for user space tools, however the
corresponding options are not documented in man page.

This commit documents the options and provides examples on device mode.
Also the command `usbip port` is documented.

Signed-off-by: Hongren Zheng 
---
 tools/usb/usbip/doc/usbip.8  | 42 +++-
 tools/usb/usbip/doc/usbipd.8 | 26 ++
 2 files changed, 67 insertions(+), 1 deletion(-)

PATCH v2:
 Add signed-off-by line

PATCH v3:
 Move patch changelog after the marker line
 Remove nickname in signed-off-by line

PATCH v4:
 Use commit short hash and message instead of long hash only when
   referring to commit in the kernel

PATCH v5:
Add documentation of `usbip port` and its usage in examples
Add flow of detaching in examples
Rephrase some description and add punctuations
Fix typo of `usbip attach --ev-id` to `--dev-id`

diff --git a/tools/usb/usbip/doc/usbip.8 b/tools/usb/usbip/doc/usbip.8
index a15d20063b98..1f26e4a00638 100644
--- a/tools/usb/usbip/doc/usbip.8
+++ b/tools/usb/usbip/doc/usbip.8
@@ -49,10 +49,17 @@ then exit.
 Attach a remote USB device.
 .PP
 
+.HP
+\fBattach\fR \-\-remote=<\fIhost\fR> \-\-device=<\fIdev_id\fR>
+.IP
+Attach a remote USB gadget.
+Only used when the remote usbipd is in device mode.
+.PP
+
 .HP
 \fBdetach\fR \-\-port=<\fIport\fR>
 .IP
-Detach an imported USB device.
+Detach an imported USB device/gadget.
 .PP
 
 .HP
@@ -73,12 +80,26 @@ Stop exporting a device so it can be used by a local driver.
 List USB devices exported by a remote host.
 .PP
 
+.HP
+\fBlist\fR \-\-device
+.IP
+List USB gadgets of local usbip-vudc.
+Only used when the local usbipd is in device mode.
+Note that this can not list usbip-vudc USB gadgets of the remote device mode 
usbipd.
+.PP
+
 .HP
 \fBlist\fR \-\-local
 .IP
 List local USB devices.
 .PP
 
+.HP
+\fBport\fR
+.IP
+List imported devices/gadgets.
+.PP
+
 
 .SH EXAMPLES
 
@@ -90,8 +111,27 @@ List local USB devices.
 client:# usbip attach --remote=server --busid=1-2
 - Connect the remote USB device.
 
+client:# usbip port
+- List imported devices/gadgets.
+
 client:# usbip detach --port=0
 - Detach the usb device.
 
+The following example shows the usage of device mode
+
+server:# usbip list --device
+- List gadgets exported by local usbipd server.
+
+client:# modprobe vhci-hcd
+
+client:# usbip attach --remote=server --device=usbip-vudc.0
+- Connect the remote USB gadget.
+
+client:# usbip port
+- List imported devices/gadgets.
+
+client:# usbip detach --port=0
+- Detach the usb gadget.
+
 .SH "SEE ALSO"
 \fBusbipd\fP\fB(8)\fB\fP
diff --git a/tools/usb/usbip/doc/usbipd.8 b/tools/usb/usbip/doc/usbipd.8
index fb62a756893b..d974394f86a1 100644
--- a/tools/usb/usbip/doc/usbipd.8
+++ b/tools/usb/usbip/doc/usbipd.8
@@ -29,6 +29,12 @@ Bind to IPv4. Default is both.
 Bind to IPv6. Default is both.
 .PP
 
+.HP
+\fB\-e\fR, \fB\-\-device\fR
+.IP
+Run in device mode. Rather than drive an attached device, create a virtual UDC 
to bind gadgets to.
+.PP
+
 .HP
 \fB\-D\fR, \fB\-\-daemon\fR
 .IP
@@ -86,6 +92,26 @@ USB/IP client can connect and use exported devices.
 - A usb device 1-2 is now exportable to other hosts!
 - Use 'usbip unbind --busid=1-2' when you want to shutdown exporting 
and use the device locally.
 
+The following example shows the usage of device mode
+
+server:# modprobe usbip-vudc
+- Use /sys/class/udc/ interface.
+- usbip-host is independent of this module.
+
+server:# usbipd -e -D
+- Start usbip daemon in device mode.
+
+server:# modprobe g_mass_storage file=/tmp/tmp.img
+- Bind a gadget to usbip-vudc.
+- in this example, a mass storage gadget is bound.
+
+server:# usbip list --device
+- List gadgets exported by local usbipd server.
+
+server:# modprobe -r g_mass_storage
+- Unbind a gadget from usbip-vudc.
+- in this example, the previous mass storage gadget is unbound.
+
 .SH "SEE ALSO"
 \fBusbip\fP\fB(8)\fB\fP
 
-- 
2.30.1

[PATCH] drm/nouveau/bios/init: A typo fix



s/conditon/condition/

Signed-off-by: Bhaskar Chowdhury 
---
 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c 
b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
index 9de74f41dcd2..142079403864 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c
@@ -401,7 +401,7 @@ init_table_(struct nvbios_init *init, u16 offset, const 
char *name)
 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
-#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag 
conditon table")
+#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag 
condition table")
 #define init_function_table(b) init_table_((b), 0x0c, "function table")
 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");

--
2.30.1

Re: [PATCH] media: venus : hfi: add venus image info into smem

2021-03-23 Thread Stephen Boyd

Quoting Dikshita Agarwal (2021-03-23 22:40:57)
> fill fw version info into smem to be printed as part of

s/fill/Fill/

> soc info.
> 
> Signed-off-by: Dikshita Agarwal 
> ---
>  drivers/media/platform/qcom/venus/hfi_msgs.c | 36 
> ++--
>  1 file changed, 34 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/venus/hfi_msgs.c 
> b/drivers/media/platform/qcom/venus/hfi_msgs.c
> index 06a1908..0e94921 100644
> --- a/drivers/media/platform/qcom/venus/hfi_msgs.c
> +++ b/drivers/media/platform/qcom/venus/hfi_msgs.c
> @@ -239,15 +242,44 @@ static void
>  sys_get_prop_image_version(struct device *dev,
>struct hfi_msg_sys_property_info_pkt *pkt)
>  {
> +   u32 i = 0;
> +   size_t smem_block_size = 0;
> +   u8 *smem_table_ptr;
> +   char version[256];
> +   const u32 version_string_size = 128;
> +   const u32 smem_image_index_venus = 14 * 128;

Can these be #defines instead of local const variables?

> +   u8 *str_image_version;
> int req_bytes;
>  
> req_bytes = pkt->hdr.size - sizeof(*pkt);
>  
> -   if (req_bytes < 128 || !pkt->data[1] || pkt->num_properties > 1)
> +   if (req_bytes < version_string_size || !pkt->data[1] || 
> pkt->num_properties > 1)
> /* bad packet */
> return;
>  
> -   dev_dbg(dev, VDBGL "F/W version: %s\n", (u8 *)&pkt->data[1]);

Why is pkt->data not already a u8?

> +   str_image_version = (u8 *)&pkt->data[1];
> +
> +   /*
> +* The version string returned by firmware includes null
> +* characters at the start and in between. Replace the null
> +* characters with space, to print the version info.
> +*/
> +   for (i = 0; i < version_string_size; i++) {
> +   if (str_image_version[i] != '\0')
> +   version[i] = str_image_version[i];
> +   else
> +   version[i] = ' ';
> +   }
> +
> +   version[i] = '\0';
> +   dev_dbg(dev, VDBGL "F/W version: %s\n", version);

Instead of replacing the string with spaces can we find the first
non-null character up to version_string_size and then stash a pointer to
that and print it out with dev_dbg()? That would save 256 bytes on the
stack for something that is presumably a string and will be NUL
terminated.

> +
> +   smem_table_ptr = qcom_smem_get(QCOM_SMEM_HOST_ANY,
> +  SMEM_IMAGE_VERSION_TABLE, 
> &smem_block_size);
> +   if ((smem_image_index_venus + version_string_size) <= smem_block_size 
> &&
> +   smem_table_ptr)
> +   memcpy(smem_table_ptr + smem_image_index_venus,
> +  str_image_version, version_string_size);

It would be nice to have shorter variable names so this was an

if (condition1 && condition2)
memcpy();

Re: [PATCH] scripts: Fix incremental build header re-generation

2021-03-23 Thread Masahiro Yamada

On Thu, Mar 18, 2021 at 11:55 AM Jeevan Shriram  wrote:
>
>
> On 3/1/2021 7:36 PM, Masahiro Yamada wrote:
> > On Mon, Mar 1, 2021 at 11:23 PM Jeevan Shriram  
> > wrote:
> >> compile.h and autoconf.h are ignored when checking headers sha as they
> >> are always re-generated for every kernel compilation. However,
> >> these two headers are packaged into kheaders tar. During incremental
> >> compilation of kernel, kheaders tar file is always generated and 
> >> re-packaged
> >> irrespective of the changes in headers.
> >
> > I do not see this problem.
> > Could you describe the steps to reproduce it, please?
> >
> Without making any changes in the kernel or it's headers, re-compile the 
> kernel. i.e.,incremental kernel build without any changes.
> I have added following log in gen_kheaders.sh script for confirming the hash 
> differences.


Of course they are different because you are comparing
the hashes of two different files.



>
> diff --git a/kernel/gen_kheaders.sh b/kernel/gen_kheaders.sh
> index b7425a0..ee542a0 100755
> --- a/kernel/gen_kheaders.sh
> +++ b/kernel/gen_kheaders.sh
> @@ -40,6 +40,10 @@ obj_files_md5="$(find $dir_list -name "*.h"
>  |
>   # Any changes to this script will also cause a rebuild of the archive.
>   this_file_md5="$(ls -l $sfile | md5sum | cut -d ' ' -f1)"
>   if [ -f $tarfile ]; then tarfile_md5="$(md5sum $tarfile | cut -d ' ' -f1)"; 
> fi
> +
> +echo "Old Tar file $tarfile_md5"


This is the hash of kernel/kheaders_data.tar.xz


> +echo "New Tar file hash $this_file_md5"


This is the hash of kernel/gen_kheaders.sh




> +
>   if [ -f kernel/kheaders.md5 ] &&
>  [ "$(cat kernel/kheaders.md5|head -1)" == "$src_files_md5" ] &&
>  [ "$(cat kernel/kheaders.md5|head -2|tail -1)" == "$obj_files_md5" ] 
> &&
>
> log output :
> 89306 19:29:02.109961   CHK kernel/kheaders_data.tar.xz
> 89307 19:29:02.109971 Old Tar file 2aa6990e4183c31a862951f4bcac037e
> 89308 19:29:02.109982 New Tar file hash ecf84e700c7cacfe8b35a0905859582d


I do not understand what your claim is.



CHK kernel/kheaders_data.tar.xz

is displayed when it is checking the hash in order to
determine if the tarball should be updated.


GEN kernel/kheaders_data.tar.xz

is displayed when the tarball is really updated.





[Incremental build with no change]


masahiro@oscar:~/ref/linux$ make -j24
  DESCEND  objtool
  CALLscripts/atomic/check-atomics.sh
  CALLscripts/checksyscalls.sh
  CHK include/generated/compile.h
  CHK kernel/kheaders_data.tar.xz
Kernel: arch/x86/boot/bzImage is ready  (#2)


[Touch one header and rebuild]

masahiro@oscar:~/ref/linux$ touch include/uapi/drm/exynos_drm.h
masahiro@oscar:~/ref/linux$ make -j24
  DESCEND  objtool
  CALLscripts/atomic/check-atomics.sh
  CALLscripts/checksyscalls.sh
  CHK include/generated/compile.h
  CHK kernel/kheaders_data.tar.xz
  GEN kernel/kheaders_data.tar.xz
  CC  kernel/kheaders.o
  AR  kernel/built-in.a
  GEN .version
  CHK include/generated/compile.h
  UPD include/generated/compile.h
  CC  init/version.o
  AR  init/built-in.a
  LD  vmlinux.o
  MODPOST vmlinux.symvers
  MODINFO modules.builtin.modinfo
  GEN modules.builtin
  LD  .tmp_vmlinux.kallsyms1
  KSYMS   .tmp_vmlinux.kallsyms1.S
  AS  .tmp_vmlinux.kallsyms1.S
  LD  .tmp_vmlinux.kallsyms2
  KSYMS   .tmp_vmlinux.kallsyms2.S
  AS  .tmp_vmlinux.kallsyms2.S
  LD  vmlinux
  SORTTAB vmlinux
  SYSMAP  System.map
  MODPOST Module.symvers
  CC  arch/x86/boot/version.o
  VOFFSET arch/x86/boot/compressed/../voffset.h
  OBJCOPY arch/x86/boot/compressed/vmlinux.bin
  RELOCS  arch/x86/boot/compressed/vmlinux.relocs
  CC  arch/x86/boot/compressed/kaslr.o
  CC  arch/x86/boot/compressed/misc.o
  GZIParch/x86/boot/compressed/vmlinux.bin.gz
  MKPIGGY arch/x86/boot/compressed/piggy.S
  AS  arch/x86/boot/compressed/piggy.o
  LD  arch/x86/boot/compressed/vmlinux
  ZOFFSET arch/x86/boot/zoffset.h
  OBJCOPY arch/x86/boot/vmlinux.bin
  AS  arch/x86/boot/header.o
  LD  arch/x86/boot/setup.elf
  OBJCOPY arch/x86/boot/setup.bin
  BUILD   arch/x86/boot/bzImage
Kernel: arch/x86/boot/bzImage is ready  (#3)







> >> Change-Id: I7a64faebb81df44c32230b0fea1d6df09d7ce66f
> >> Signed-off-by: Jeevan Shriram 
> >> ---
> >>   kernel/gen_kheaders.sh | 3 +--
> >>   1 file changed, 1 insertion(+), 2 deletions(-)
> >>
> >> diff --git a/kernel/gen_kheaders.sh b/kernel/gen_kheaders.sh
> >> index c1510f0..5499f72 100755
> >> --- a/kernel/gen_kheaders.sh
> >> +++ b/kernel/gen_kheaders.sh
> >> @@ -51,8 +51,7 @@ this_file_md5="$(ls -l $sfile | md5sum | cut -d ' ' -f1)"
> >>   if [ -f $tarfile ]; then tarfile_md5="$(md5sum $tarfile | cut -d ' ' 
> >> -f1)"; fi
> >>   if [ -f kernel/kheaders.md5 ] &&
> >>  [ "$(head -n 1 kernel/kheaders.md5)" = "$headers_md5" ] &&
> >> -   [ "$(head -n 2 kernel/kheaders.md5 | tail -n 1)" = 
> >> "$this_file_md5" ] &&
> >> -   [ "$(ta

[PATCH] misc: genwqe: Rudimentary typo fixes



s/requsted/requested/  .two different places.
s/equests/requests/
s/occured/occurred/..two different places.
s/conditon/condition/
s/requestors/requesters/


Signed-off-by: Bhaskar Chowdhury 
---
 drivers/misc/genwqe/card_ddcb.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/misc/genwqe/card_ddcb.c b/drivers/misc/genwqe/card_ddcb.c
index 0db4000dedf2..98f6cd3fc66a 100644
--- a/drivers/misc/genwqe/card_ddcb.c
+++ b/drivers/misc/genwqe/card_ddcb.c
@@ -316,7 +316,7 @@ static int enqueue_ddcb(struct genwqe_dev *cd, struct 
ddcb_queue *queue,

 /**
  * copy_ddcb_results() - Copy output state from real DDCB to request
- * @req:pointer to requsted DDCB parameters
+ * @req:pointer to requested DDCB parameters
  * @ddcb_no:pointer to ddcb number being tapped
  *
  * Copy DDCB ASV to request struct. There is no endian
@@ -356,7 +356,7 @@ static void copy_ddcb_results(struct ddcb_requ *req, int 
ddcb_no)
 }

 /**
- * genwqe_check_ddcb_queue() - Checks DDCB queue for completed work equests.
+ * genwqe_check_ddcb_queue() - Checks DDCB queue for completed work requests.
  * @cd: pointer to genwqe device descriptor
  * @queue: queue to be checked
  *
@@ -460,7 +460,7 @@ static int genwqe_check_ddcb_queue(struct genwqe_dev *cd,
 /**
  * __genwqe_wait_ddcb(): Waits until DDCB is completed
  * @cd: pointer to genwqe device descriptor
- * @req:pointer to requsted DDCB parameters
+ * @req:pointer to requested DDCB parameters
  *
  * The Service Layer will update the RETC in DDCB when processing is
  * pending or done.
@@ -498,7 +498,7 @@ int __genwqe_wait_ddcb(struct genwqe_dev *cd, struct 
ddcb_requ *req)

/*
 * We need to distinguish 3 cases here:
-*   1. rc == 0  timeout occured
+*   1. rc == 0  timeout occurred
 *   2. rc == -ERESTARTSYS   signal received
 *   3. rc > 0   remaining jiffies condition is true
 */
@@ -543,7 +543,7 @@ int __genwqe_wait_ddcb(struct genwqe_dev *cd, struct 
ddcb_requ *req)
return -EINVAL;
}

-   /* Severe error occured. Driver is forced to stop operation */
+   /* Severe error occurred. Driver is forced to stop operation */
if (cd->card_state != GENWQE_CARD_USED) {
dev_err(&pci_dev->dev,
"[%s] err: DDCB#%d forced to stop (rc=%d)\n",
@@ -1002,7 +1002,7 @@ static int genwqe_next_ddcb_ready(struct genwqe_dev *cd)
  * @cd: pointer to genwqe device descriptor
  *
  * Keep track on the number of DDCBs which ware currently in the
- * queue. This is needed for statistics as well as conditon if we want
+ * queue. This is needed for statistics as well as condition if we want
  * to wait or better do polling in case of no interrupts available.
  */
 int genwqe_ddcbs_in_flight(struct genwqe_dev *cd)
@@ -1182,7 +1182,7 @@ static irqreturn_t genwqe_vf_isr(int irq, void *dev_id)
  *
  * The idea is to check if there are DDCBs in processing. If there are
  * some finished DDCBs, we process them and wakeup the
- * requestors. Otherwise we give other processes time using
+ * requesters. Otherwise we give other processes time using
  * cond_resched().
  */
 static int genwqe_card_thread(void *data)
--
2.30.1

Re: [PATCH v6] mm: cma: support sysfs

2021-03-23 Thread John Hubbard


On 3/23/21 10:44 PM, Minchan Kim wrote:

On Tue, Mar 23, 2021 at 09:47:27PM -0700, John Hubbard wrote:

On 3/23/21 8:27 PM, Minchan Kim wrote:
...

+static int __init cma_sysfs_init(void)
+{
+   unsigned int i;
+
+   cma_kobj_root = kobject_create_and_add("cma", mm_kobj);
+   if (!cma_kobj_root)
+   return -ENOMEM;
+
+   for (i = 0; i < cma_area_count; i++) {
+   int err;
+   struct cma *cma;
+   struct cma_kobject *cma_kobj;
+
+   cma_kobj = kzalloc(sizeof(*cma_kobj), GFP_KERNEL);
+   if (!cma_kobj) {
+   kobject_put(cma_kobj_root);
+   return -ENOMEM;


This leaks little cma_kobj's all over the floor. :)


I thought kobject_put(cma_kobj_root) should deal with it. No?


If this fails when i > 0, there will be cma_kobj instances that
were stashed in the cma_areas[] array. But this code only deletes
the most recently allocated cma_kobj, not anything allocated on
previous iterations of the loop.


Oh, I misunderstood that destroying of root kobject will release
children recursively. Seems not true. Go back to old version.


index 16c81c9cb9b7..418951a3f138 100644
--- a/mm/cma_sysfs.c
+++ b/mm/cma_sysfs.c
@@ -80,20 +80,19 @@ static struct kobj_type cma_ktype = {
  static int __init cma_sysfs_init(void)
  {
 unsigned int i;
+   int err;
+   struct cma *cma;
+   struct cma_kobject *cma_kobj;

 cma_kobj_root = kobject_create_and_add("cma", mm_kobj);
 if (!cma_kobj_root)
 return -ENOMEM;

 for (i = 0; i < cma_area_count; i++) {
-   int err;
-   struct cma *cma;
-   struct cma_kobject *cma_kobj;
-
 cma_kobj = kzalloc(sizeof(*cma_kobj), GFP_KERNEL);
 if (!cma_kobj) {
-   kobject_put(cma_kobj_root);
-   return -ENOMEM;
+   err = -ENOMEM;
+   goto out;
 }

 cma = &cma_areas[i];
@@ -103,11 +102,21 @@ static int __init cma_sysfs_init(void)
cma_kobj_root, "%s", cma->name);
 if (err) {
 kobject_put(&cma_kobj->kobj);
-   kobject_put(cma_kobj_root);
-   return err;
+   goto out;
 }
 }

 return 0;
+out:
+   while (--i >= 0) {
+   cma = &cma_areas[i];
+
+   kobject_put(&cma->kobj->kobj);



OK. As long as you are spinning a new version, let's fix up the naming to
be a little better, too. In this case, with a mildly dizzying mix of cma's
and kobjects, it actually makes a real difference. I wouldn't have asked,
but the above cma->kobj->kobj chain really made it obvious for me just now.

So instead of this (in cma.h):

struct cma_kobject {
struct cma *cma;
struct kobject kobj;
};

struct cma {
...
struct cma_kobject *kobj;
};

, how about approximately this:

struct cma_kobject_wrapper {
struct cma *parent;
struct kobject kobj;
};

struct cma {
...
struct cma_kobject_wrapper *cma_kobj_wrapper;
};


...thus allowing readers of cma_sysfs.c to read that file more easily.



+   kfree(cma->kobj);
+   cma->kobj = NULL;
+   }
+   kobject_put(cma_kobj_root);
+
+   return err;
  }
  subsys_initcall(cma_sysfs_init);





thanks,
--
John Hubbard
NVIDIA

Re: [PATCH v5 00/27] Memory Folios

2021-03-23 Thread Matthew Wilcox

On Tue, Mar 23, 2021 at 08:29:16PM -0400, Johannes Weiner wrote:
> On Mon, Mar 22, 2021 at 06:47:44PM +, Matthew Wilcox wrote:
> > On Mon, Mar 22, 2021 at 01:59:24PM -0400, Johannes Weiner wrote:
> > > On Sat, Mar 20, 2021 at 05:40:37AM +, Matthew Wilcox (Oracle) wrote:
> > > > This series introduces the 'struct folio' as a replacement for
> > > > head-or-base pages.  This initial set reduces the kernel size by
> > > > approximately 6kB, although its real purpose is adding infrastructure
> > > > to enable further use of the folio.
> > > > 
> > > > The intent is to convert all filesystems and some device drivers to work
> > > > in terms of folios.  This series contains a lot of explicit conversions,
> > > > but it's important to realise it's removing a lot of implicit 
> > > > conversions
> > > > in some relatively hot paths.  There will be very few conversions from
> > > > folios when this work is completed; filesystems, the page cache, the
> > > > LRU and so on will generally only deal with folios.
> > > 
> > > If that is the case, shouldn't there in the long term only be very
> > > few, easy to review instances of things like compound_head(),
> > > PAGE_SIZE etc. deep in the heart of MM? And everybody else should 1)
> > > never see tail pages and 2) never assume a compile-time page size?
> > 
> > I don't know exactly where we get to eventually.  There are definitely
> > some aspects of the filesystem<->mm interface which are page-based
> > (eg ->fault needs to look up the exact page, regardless of its
> > head/tail/base nature), while ->readpage needs to talk in terms of
> > folios.
> 
> I can imagine we'd eventually want fault handlers that can also fill
> in larger chunks of data if the file is of the right size and the MM
> is able to (and policy/heuristics determine to) go with a huge page.

Oh yes, me too!

The way I think this works is that the VM asks for the specific
page, just as it does today and the ->fault handler returns the page.
Then the VM looks up the folio for that page, and asks the arch to map
the entire folio.  How the arch does that is up to the arch -- if it's
PMD sized and aligned, it can do that; if the arch knows that it should
use 8 consecutive PTE entries to map 32KiB all at once, it can do that.

But I think we need the ->fault handler to return the specific page,
because that's how we can figure out whether this folio is mapped at the
appropriate alignment to make this work.  If the fault handler returns
the folio, I don't think we can figure out if the alignment is correct.
Maybe we can for the page cache, but a device driver might have a compound
page allocated for its own purposes, and it might not be amenable to
the same rules as the page cache.

> > https://git.infradead.org/users/willy/pagecache.git/commitdiff/047e9185dc146b18f56c6df0b49fe798f1805c7b
> > 
> > It deals mostly in terms of folios, but when it needs to kmap() and
> > memcmp(), then it needs to work in terms of pages.  I don't think it's
> > avoidable (maybe we bury the "dealing with pages" inside a kmap()
> > wrapper somewhere, but I'm not sure that's better).
> 
> Yeah it'd be nice to get low-level, PAGE_SIZE pages out of there. We
> may be able to just kmap whole folios too, which are more likely to be
> small pages on highmem systems anyway.

I got told "no" when asking for kmap_local() of a compound page.
Maybe that's changeable, but I'm assuming that kmap() space will
continue to be tight for the foreseeable future (until we can
kill highmem forever).

> > > Some compound_head() that are currently in the codebase are already
> > > unnecessary. Like the one in activate_page().
> > 
> > Right!  And it's hard to find & remove them without very careful analysis,
> > or particularly deep knowledge.  With folios, we can remove them without
> > terribly deep thought.
> 
> True. It definitely also helps mark the places that have been
> converted from the top down and which ones haven't. Without that you
> need to think harder about the context ("How would a tail page even
> get here?" vs. "No page can get here, only folios" ;-))

Exactly!  Take a look at page_mkclean().  Its implementation strongly
suggests that it expects a head page, but I think it'll unmap a single
page if passed a tail page ... and it's not clear to me that isn't the
behaviour that pagecache_isize_extended() would prefer.  Tricky.

> > I mean, I already tried what you're suggesting.  It's really freaking
> > hard.  It's hard to do, it's hard to explain, it's hard to know if you
> > got it right.  With folios, I've got the compiler working for me, telling
> > me that I got some of the low-level bits right (or wrong), leaving me
> > free to notice "Oh, wait, we got the accounting wrong because writeback
> > assumes that a page is only PAGE_SIZE bytes".  I would _never_ have
> > noticed that with the THP tree.  I only noticed it because transitioning
> > things to folios made me read the writeback code and wonder about the
> > 'inc_w

Re: [PATCH v1 0/3] KEYS: trusted: Introduce support for NXP CAAM-based trusted keys

2021-03-23 Thread Sumit Garg

On Tue, 23 Mar 2021 at 22:04, Ahmad Fatoum  wrote:
>
> Hello Horia,
>
> On 21.03.21 21:01, Horia Geantă wrote:
> > On 3/16/2021 7:02 PM, Ahmad Fatoum wrote:
> >> This patch series builds on top of Sumit's rework to have the CAAM as yet 
> >> another
> >> trusted key backend.
> >>
> > Shouldn't the description under TRUSTED_KEYS (in security/keys/Kconfig)
> > be updated to reflect the availability of multiple backends?
>
> This is indeed no longer correct. It also depends on TCG_TPM, which AFAIU
> is not really needed for the new TEE backend.
>
> @Sumit, can you confirm?
>

Yes, that's correct. Let me share a separate patch to fix that.

-Sumit

> --
> Pengutronix e.K.   | |
> Steuerwalder Str. 21   | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany  | Phone: +49-5121-206917-0|
> Amtsgericht Hildesheim, HRA 2686   | Fax:   +49-5121-206917- |

Re: [PATCH v2 -next] powerpc: kernel/time.c - cleanup warnings

2021-03-23 Thread Christophe Leroy

Le 24/03/2021 à 07:14, Christophe Leroy a écrit :

Le 24/03/2021 à 00:05, Alexandre Belloni a écrit :

On 23/03/2021 23:18:17+0100, Alexandre Belloni wrote:

Hello,

On 23/03/2021 05:12:57-0400, He Ying wrote:

We found these warnings in arch/powerpc/kernel/time.c as follows:
warning: symbol 'decrementer_max' was not declared. Should it be static?
warning: symbol 'rtc_lock' was not declared. Should it be static?
warning: symbol 'dtl_consumer' was not declared. Should it be static?

Declare 'decrementer_max' and 'rtc_lock' in powerpc asm/time.h.
Rename 'rtc_lock' in drviers/rtc/rtc-vr41xx.c to 'vr41xx_rtc_lock' to
avoid the conflict with the variable in powerpc asm/time.h.
Move 'dtl_consumer' definition behind "include " because it
is declared there.

Reported-by: Hulk Robot
Signed-off-by: He Ying
---
v2:
- Instead of including linux/mc146818rtc.h in powerpc kernel/time.c, declare
rtc_lock in powerpc asm/time.h.

V1 was actually the correct thing to do. rtc_lock is there exactly
because chrp and maple are using mc146818 compatible RTCs. This is then
useful because then drivers/char/nvram.c is enabled. The proper fix
would be to scrap all of that and use rtc-cmos for those platforms as
this drives the RTC properly and exposes the NVRAM for the mc146818.

Or at least, if there are no users for the char/nvram driver on those
two platforms, remove the spinlock and stop enabling CONFIG_NVRAM or
more likely rename the symbol as it seems to be abused by both chrp and
powermac.

Ok so rtc_lock is not even used by the char/nvram.c driver as it is
completely compiled out.

I guess it is fine having it move to the individual platform as looking
very quickly at the Kconfig, it is not possible to select both
simultaneously. Tentative patch:

Looking at it once more, it looks like including linux/mc146818rtc.h is the thing to do, at least
for now. Several platforms are defining the rtc_lock exactly the same way as powerpc does, and
including mc146818rtc.h

I think that to get it clean, this change should go in a dedicated patch and do a bit more and
explain exactly what is being do and why. I'll try to draft something for it.

He Y., can you make a version v3 of your patch excluding the rtc_lock change ?

Finally, I think there is not enough changes to justify a separate patch.

So you can send a V3 based on your V1. In addition to the changes you had in V1, please remove the
declaration of rfc_lock in arch/powerpc/platforms/chrp/chrp.h

Christophe

[PATCH net-next] rds: Fix some typos for rds

s/alloced/allocated/
s/synching/syncing/
s/connction/connection/
s/beween/between/

Reported-by: Hulk Robot 
Signed-off-by: Wang Hai 
---
 net/rds/ib_ring.c  | 2 +-
 net/rds/ib_send.c  | 2 +-
 net/rds/send.c | 4 ++--
 net/rds/tcp_recv.c | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/net/rds/ib_ring.c b/net/rds/ib_ring.c
index ff97e8eda858..006b2e441418 100644
--- a/net/rds/ib_ring.c
+++ b/net/rds/ib_ring.c
@@ -141,7 +141,7 @@ int rds_ib_ring_low(struct rds_ib_work_ring *ring)
 }
 
 /*
- * returns the oldest alloced ring entry.  This will be the next one
+ * returns the oldest allocated ring entry.  This will be the next one
  * freed.  This can't be called if there are none allocated.
  */
 u32 rds_ib_ring_oldest(struct rds_ib_work_ring *ring)
diff --git a/net/rds/ib_send.c b/net/rds/ib_send.c
index 92b4a8689aae..0ad8c685621d 100644
--- a/net/rds/ib_send.c
+++ b/net/rds/ib_send.c
@@ -109,7 +109,7 @@ static void rds_ib_send_unmap_rdma(struct rds_ib_connection 
*ic,
 * Note: There's no need to explicitly sync any RDMA buffers using
 * ib_dma_sync_sg_for_cpu - the completion for the RDMA
 * operation itself unmapped the RDMA buffers, which takes care
-* of synching.
+* of syncing.
 */
rds_ib_send_complete(container_of(op, struct rds_message, rdma),
 wc_status, rds_rdma_send_complete);
diff --git a/net/rds/send.c b/net/rds/send.c
index 985d0b7713ac..ea6301c4001a 100644
--- a/net/rds/send.c
+++ b/net/rds/send.c
@@ -233,7 +233,7 @@ int rds_send_xmit(struct rds_conn_path *cp)
 * If not already working on one, grab the next message.
 *
 * cp_xmit_rm holds a ref while we're sending this message down
-* the connction.  We can use this ref while holding the
+* the connection.  We can use this ref while holding the
 * send_sem.. rds_send_reset() is serialized with it.
 */
if (!rm) {
@@ -1225,7 +1225,7 @@ int rds_sendmsg(struct socket *sock, struct msghdr *msg, 
size_t payload_len)
}
/* If the socket is already bound to a link local address,
 * it can only send to peers on the same link.  But allow
-* communicating beween link local and non-link local address.
+* communicating between link local and non-link local address.
 */
if (scope_id != rs->rs_bound_scope_id) {
if (!scope_id) {
diff --git a/net/rds/tcp_recv.c b/net/rds/tcp_recv.c
index 42c5ff1eda95..f4ee13da90c7 100644
--- a/net/rds/tcp_recv.c
+++ b/net/rds/tcp_recv.c
@@ -177,7 +177,7 @@ static int rds_tcp_data_recv(read_descriptor_t *desc, 
struct sk_buff *skb,
goto out;
}
tc->t_tinc = tinc;
-   rdsdebug("alloced tinc %p\n", tinc);
+   rdsdebug("allocated tinc %p\n", tinc);
rds_inc_path_init(&tinc->ti_inc, cp,
  &cp->cp_conn->c_faddr);
tinc->ti_inc.i_rx_lat_trace[RDS_MSG_RX_HDR] =
-- 
2.17.1

[PATCH net-next] 6lowpan: Fix some typos in nhc_udp.c

s/Orignal/Original/
s/infered/inferred/

Reported-by: Hulk Robot 
Signed-off-by: Wang Hai 
---
 net/6lowpan/nhc_udp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/net/6lowpan/nhc_udp.c b/net/6lowpan/nhc_udp.c
index 8a3507524f7b..33f17bd8cda7 100644
--- a/net/6lowpan/nhc_udp.c
+++ b/net/6lowpan/nhc_udp.c
@@ -5,7 +5,7 @@
  * Authors:
  * Alexander Aring 
  *
- * Orignal written by:
+ * Original written by:
  * Alexander Smirnov 
  * Jon Smirl 
  */
@@ -82,7 +82,7 @@ static int udp_uncompress(struct sk_buff *skb, size_t needed)
if (fail)
return -EINVAL;
 
-   /* UDP length needs to be infered from the lower layers
+   /* UDP length needs to be inferred from the lower layers
 * here, we obtain the hint from the remaining size of the
 * frame
 */
-- 
2.17.1

[PATCH net-next] net/packet: Fix a typo in af_packet.c

s/sequencially/sequentially/

Reported-by: Hulk Robot 
Signed-off-by: Wang Hai 
---
 net/packet/af_packet.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
index 6bbc7a448593..fe29fc1b8b9d 100644
--- a/net/packet/af_packet.c
+++ b/net/packet/af_packet.c
@@ -2057,7 +2057,7 @@ static int packet_rcv_vnet(struct msghdr *msg, const 
struct sk_buff *skb,
  * and skb->cb are mangled. It works because (and until) packets
  * falling here are owned by current CPU. Output packets are cloned
  * by dev_queue_xmit_nit(), input packets are processed by net_bh
- * sequencially, so that if we return skb to original state on exit,
+ * sequentially, so that if we return skb to original state on exit,
  * we will not harm anyone.
  */
 
-- 
2.17.1

RE: [PATCH v3] dt-binding: leds: Document leds-multi-gpio bindings

2021-03-23 Thread Alexander Dahl

Hello,

> Hermes Zhang  hat am 24.03.2021 07:04 geschrieben:
> 
>  
> > >
> > > Notes:
> > > Add maxItems
> > 
> > What about the other part of the series? I think you should send both
> > patches together with an introduction message on both. If you only change
> > one patch for a new version spin of the series, just send the other one
> > unchanged.
> > 
> > (It makes no sense to merge the binding as long as the driver is not merged,
> > otherwise you would end up with a binding without driver. So keeping them
> > together should help reviewers and maintainers.)
> > 
> 
> Hi Alexander,
> 
> The other part is here: https://lore.kernel.org/patchwork/patch/1399875/, so 
> do you mean I need to combine these two as one commit? Or is there anyway to 
> link them together? Thanks.

Two commits.

For sending more than one patch in a series call `git format-patch` with the 
option --cover-letter. Please have a look at documentation on `git 
format-patch` and `git send-email` again.

You can see how it looks if you look out for other patch series on the from the 
past, especially those with subjects like "[PATCH 0/x] ...". An e-mail client 
supporting threaded view helps a lot.

> I'm first time to commit a new driver, sorry for that.

Thanks for trying. No need to be sorry, the tools are hard and expectations are 
high. In the end it's all about efficiency.

Have a nice day
Alex

Re: [PATCH v2 -next] powerpc: kernel/time.c - cleanup warnings

2021-03-23 Thread Christophe Leroy

Le 24/03/2021 à 00:05, Alexandre Belloni a écrit :

On 23/03/2021 23:18:17+0100, Alexandre Belloni wrote:

Hello,

On 23/03/2021 05:12:57-0400, He Ying wrote:

Reported-by: Hulk Robot
Signed-off-by: He Ying
---
v2:
- Instead of including linux/mc146818rtc.h in powerpc kernel/time.c, declare
rtc_lock in powerpc asm/time.h.

Ok so rtc_lock is not even used by the char/nvram.c driver as it is
completely compiled out.

I guess it is fine having it move to the individual platform as looking
very quickly at the Kconfig, it is not possible to select both
simultaneously. Tentative patch:

I think that to get it clean, this change should go in a dedicated patch and do a bit more and
explain exactly what is being do and why. I'll try to draft something for it.

He Y., can you make a version v3 of your patch excluding the rtc_lock change ?

Christophe

[PATCH net-next] net/tls: Fix a typo in tls_device.c

s/beggining/beginning/

Reported-by: Hulk Robot 
Signed-off-by: Wang Hai 
---
 net/tls/tls_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/tls/tls_device.c b/net/tls/tls_device.c
index f7fb7d2c1de1..89a5d4fad0a2 100644
--- a/net/tls/tls_device.c
+++ b/net/tls/tls_device.c
@@ -601,7 +601,7 @@ struct tls_record_info *tls_get_record(struct 
tls_offload_context_tx *context,
if (!info ||
before(seq, info->end_seq - info->len)) {
/* if retransmit_hint is irrelevant start
-* from the beggining of the list
+* from the beginning of the list
 */
info = list_first_entry_or_null(&context->records_list,
struct tls_record_info, list);
-- 
2.17.1

[PATCH] scsi: esp_scsi: Trivial typo fixes



s/conditon/condition/
s/pecularity/peculiarity/

Signed-off-by: Bhaskar Chowdhury 
---
 drivers/scsi/esp_scsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/scsi/esp_scsi.c b/drivers/scsi/esp_scsi.c
index 007ccef5d1e2..342535ac0570 100644
--- a/drivers/scsi/esp_scsi.c
+++ b/drivers/scsi/esp_scsi.c
@@ -647,7 +647,7 @@ static void esp_unmap_sense(struct esp *esp, struct 
esp_cmd_entry *ent)
ent->sense_ptr = NULL;
 }

-/* When a contingent allegiance conditon is created, we force feed a
+/* When a contingent allegiance condition is created, we force feed a
  * REQUEST_SENSE command to the device to fetch the sense data.  I
  * tried many other schemes, relying on the scsi error handling layer
  * to send out the REQUEST_SENSE automatically, but this was difficult
@@ -1341,7 +1341,7 @@ static int esp_data_bytes_sent(struct esp *esp, struct 
esp_cmd_entry *ent,
bytes_sent -= esp->send_cmd_residual;

/*
-* The am53c974 has a DMA 'pecularity'. The doc states:
+* The am53c974 has a DMA 'peculiarity'. The doc states:
 * In some odd byte conditions, one residual byte will
 * be left in the SCSI FIFO, and the FIFO Flags will
 * never count to '0 '. When this happens, the residual
--
2.30.1

Re: [PATCH v10] i2c: virtio: add a virtio i2c frontend driver

2021-03-23 Thread Viresh Kumar

On 24-03-21, 14:05, Jie Deng wrote:
> For simplicity, the original patch sent only 1 message to vq each time . I
> changed the way to send

I missed those earlier discussions :)

> a batch of requests in one time in order to improve efficiency according to
> Jason' suggestion.

I agree.

> As we discussed in the previous emails, the device can raise interrupt when
> some requests are still not completed
> 
> though this is not a good operation.  In this case, the remaining requests
> in the vq will be ignored and
> 
> the i2c_algorithm. master_xfer will return 1 for your example. I will
> clarify this in the specs.

Right, this needs to be clarified that the receiver shall generate the interrupt
only once the virtqueue is empty, not in the middle of it.

Or, now that I think about it a bit more, another thing we can do here is see if
virtqueue_get_buf() returns NULL, if it does then we should keep expecting more
messages as it may be early interrupt. What do you say ?

-- 
viresh

RE: [PATCH 2/9] watchdog: of_xilinx_wdt: Used BIT macro

2021-03-23 Thread Srinivas Neeli

Hi,

> -Original Message-
> From: Guenter Roeck  On Behalf Of Guenter Roeck
> Sent: Tuesday, March 16, 2021 7:53 AM
> To: Srinivas Neeli ; Michal Simek ;
> Shubhrajyoti Datta ; Srinivas Goud
> 
> Cc: w...@linux-watchdog.org; linux-watch...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; git
> ; Srinivas Goud 
> Subject: Re: [PATCH 2/9] watchdog: of_xilinx_wdt: Used BIT macro
> 
> On 3/15/21 3:46 AM, Srinivas Neeli wrote:
> > From: Srinivas Goud 
> >
> > Used BIT macro instead of mask value.
> >
> > Signed-off-by: Srinivas Goud 
> > Signed-off-by: Michal Simek 
> > Signed-off-by: Srinivas Neeli 
> > ---
> >  drivers/watchdog/of_xilinx_wdt.c | 8 
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/watchdog/of_xilinx_wdt.c
> > b/drivers/watchdog/of_xilinx_wdt.c
> > index 00549164b3d7..0d7df2370db7 100644
> > --- a/drivers/watchdog/of_xilinx_wdt.c
> > +++ b/drivers/watchdog/of_xilinx_wdt.c
> > @@ -24,12 +24,12 @@
> >  #define XWT_TBR_OFFSET  0x8 /* Timebase Register Offset */
> >
> >  /* Control/Status Register Masks  */
> > -#define XWT_CSR0_WRS_MASK   0x0008 /* Reset status */
> > -#define XWT_CSR0_WDS_MASK   0x0004 /* Timer state  */
> > -#define XWT_CSR0_EWDT1_MASK 0x0002 /* Enable bit 1 */
> > +#define XWT_CSR0_WRS_MASK  BIT(3) /* Reset status */
> > +#define XWT_CSR0_WDS_MASK  BIT(2) /* Timer state  */
> > +#define XWT_CSR0_EWDT1_MASKBIT(1) /* Enable bit 1 */
> >
> >  /* Control/Status Register 0/1 bits  */ -#define XWT_CSRX_EWDT2_MASK
> > 0x0001 /* Enable bit 2 */
> > +#define XWT_CSRX_EWDT2_MASKBIT(0) /* Enable bit 2 */
> >
> 
> Requires #include 

Will update in V2 series.

> 
> >  /* SelfTest constants */
> >  #define XWT_MAX_SELFTEST_LOOP_COUNT 0x0001
> >

Re: [PATCH v10] i2c: virtio: add a virtio i2c frontend driver

2021-03-23 Thread Jie Deng




On 2021/3/24 12:20, Viresh Kumar wrote:

On 23-03-21, 22:19, Jie Deng wrote:

+static int virtio_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int 
num)
+{
+   struct virtio_i2c *vi = i2c_get_adapdata(adap);
+   struct virtqueue *vq = vi->vq;
+   struct virtio_i2c_req *reqs;
+   unsigned long time_left;
+   int ret, nr;
+
+   reqs = kcalloc(num, sizeof(*reqs), GFP_KERNEL);
+   if (!reqs)
+   return -ENOMEM;
+
+   mutex_lock(&vi->lock);
+
+   ret = virtio_i2c_send_reqs(vq, reqs, msgs, num);
+   if (ret == 0)
+   goto err_unlock_free;
+
+   nr = ret;
+   reinit_completion(&vi->completion);
+   virtqueue_kick(vq);

Coming back to this again, what is the expectation from the other side for this
? I mean there is no obvious relation between the *msgs* which we are going to
transfer (from the other side's or host's point of view). When should the host
OS call its virtqueue_kick() counterpart ?

Lemme give an example for this. Lets say that we need to transfer 3 messages
here in this routine. What we did was we prepared virtqueue for all 3 messages
together and then called virtqueue_kick().

Now if the other side (host) processes the first message and sends its reply
(with virtqueue_kick() counterpart) before processing the other two messages,
then it will end up calling virtio_i2c_msg_done() here. That will make us call
virtio_i2c_complete_reqs(), while only the first messages is processed until
now and so we will fail for the other two messages straight away.

Should we send only 1 message from i2c-virtio linux driver and then wait for
virtio_i2c_msg_done() to be called, before sending the next message to make sure
it doesn't break ?



For simplicity, the original patch sent only 1 message to vq each time . 
I changed the way to send


a batch of requests in one time in order to improve efficiency according 
to Jason' suggestion.


As we discussed in the previous emails, the device can raise interrupt 
when some requests are still not completed


though this is not a good operation.  In this case, the remaining 
requests in the vq will be ignored and


the i2c_algorithm. master_xfer will return 1 for your example. I will 
clarify this in the specs.

Re: [PATCH 1/3] tty: serial: Add UART driver for Cortina-Access platform

2021-03-23 Thread Greg Kroah-Hartman

On Tue, Mar 23, 2021 at 07:28:51PM +, Alex Nemirovsky wrote:
> 
> 
> > On Mar 23, 2021, at 2:22 AM, Greg Kroah-Hartman 
> >  wrote:
> > 
> > On Thu, Feb 18, 2021 at 06:42:09PM -0800, Alex Nemirovsky wrote:
> >> From: Jason Li 
> >> 
> >> This driver supports Cortina Access UART IP integrated
> >> in most all CA line of SoCs. Earlycom is also supported
> >> 
> >> Signed-off-by: Jason Li 
> >> Reviewed-by: Alex Nemirovsky 
> >> ---
> >> MAINTAINERS|   5 +
> >> drivers/tty/serial/Kconfig |  19 +
> >> drivers/tty/serial/Makefile|   1 +
> >> drivers/tty/serial/serial_cortina-access.c | 798 
> >> +
> >> include/uapi/linux/serial_core.h   |   3 +
> >> 5 files changed, 826 insertions(+)
> >> create mode 100644 drivers/tty/serial/serial_cortina-access.c
> >> 
> >> Change log
> >>  drivers/tty/serial/serial_cortina-access.c
> >>   v3:
> >>- Remove usage of uintptr_t. Change to pointer to driver's private
> >>  structure instead.
> > 
> > Is this really a "v3"?  The subject lines do not show that, so I'm
> > totally confused as to what to review and what has been reviewed here.
> > 
> > Please fix this up and submit a "v4" so we know what is going on :)
> 
> Could you recommend a method or a tool to update the commit subject id with a 
> version prefix?
> Currently we are doing a git format-patch and the subject line is 
> automatically created without a 
> version number. Do you just go in manual and edit the resulting patch 
> contents file or do you use a 
> tool to assist in this?

This is only 3 patches, they are easy to edit by hand...  :)

Anyway 'git format-patch' can do this automatically for you if you want,
see the -v or --reroll-count option.

thanks,

greg k-h

Re: [PATCH 1/3] tty: serial: Add UART driver for Cortina-Access platform

2021-03-23 Thread Greg Kroah-Hartman

On Tue, Mar 23, 2021 at 07:25:58PM +, Alex Nemirovsky wrote:
> Hi Greg,
> 
> > On Mar 23, 2021, at 2:24 AM, Greg Kroah-Hartman 
> >  wrote:
> > 
> > On Thu, Feb 18, 2021 at 06:42:09PM -0800, Alex Nemirovsky wrote:
> >> +static struct cortina_uart_port *cortina_uart_ports;
> > 
> > Why is this not a per-device pointer?
> > 
> >> +static void __exit cortina_uart_exit(void)
> >> +{
> >> +  platform_driver_unregister(&serial_cortina_driver);
> >> +  uart_unregister_driver(&cortina_uart_driver);
> >> +  kfree(cortina_uart_ports);
> > 
> > Should not need to free this here, it should be tied to the device, not
> > the driver.
> 
> Would it be possible to provide a reference to an example 
> of a good way to do it.

You have a device-specific data structure, put this information there.

> >> +}
> >> +
> >> +module_init(cortina_uart_init);
> >> +module_exit(cortina_uart_exit);
> >> +
> >> +MODULE_AUTHOR("Cortina-Access Inc.");
> >> +MODULE_DESCRIPTION(" Cortina-Access UART driver");
> >> +MODULE_LICENSE("GPL");
> >> diff --git a/include/uapi/linux/serial_core.h 
> >> b/include/uapi/linux/serial_core.h
> >> index 62c2204..1931892 100644
> >> --- a/include/uapi/linux/serial_core.h
> >> +++ b/include/uapi/linux/serial_core.h
> >> @@ -277,4 +277,7 @@
> >> /* Freescale LINFlexD UART */
> >> #define PORT_LINFLEXUART   122
> >> 
> >> +/* Cortina-Access UART */
> >> +#define PORT_CORTINA_ACCESS   123
> > 
> > Also, no need for this, right?  I would prefer to not add new ids if at
> > all possible.
> 
> Could you explain why these are no longer required and what has 
> been done in the tty design to make this obsolete?

What do you use in userspace that requires this information to be sent
from the kernel?

thanks,

greg k-h

RE: [PATCH 7/9] watchdog: of_xilinx_wdt: Add Versal Window watchdog support

2021-03-23 Thread Srinivas Neeli

Hi Guenter,

Thanks for review

> -Original Message-
> From: Guenter Roeck  On Behalf Of Guenter Roeck
> Sent: Tuesday, March 16, 2021 8:01 AM
> To: Srinivas Neeli ; Michal Simek ;
> Shubhrajyoti Datta ; Srinivas Goud
> 
> Cc: w...@linux-watchdog.org; linux-watch...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; git
> 
> Subject: Re: [PATCH 7/9] watchdog: of_xilinx_wdt: Add Versal Window
> watchdog support
> 
> On 3/15/21 3:46 AM, Srinivas Neeli wrote:
> > Versal watchdog driver uses Window watchdog mode. Window watchdog
> > timer(WWDT) contains closed(first) and open(second) window with
> > 32 bit width. WWDT will generate an interrupt after the first window
> > timeout and reset signal after the second window timeout. Timeout and
> > Pre-timeout configuration, Stop and Refresh trigger only in open
> > window.
> >
> > Signed-off-by: Srinivas Neeli 
> 
> I think this should be a separate watchdog driver. There is pretty much no
> overlap with the existing driver.

Xilinx AXI Timebase Watchdog Timer supports two independent modes
1)Timebase Watchdog Mode
2)Window Watchdog Timer Mode.
Current of_xilinx_wdt.c driver already have support for Timebase Watchdog Mode, 
but Window watchdog timer Mode feature is missing.
Versal platform contains customized AXI Timebase Watchdog Timer, which supports 
Window Watchdog Timer Mode.
For that reason we are creating common driver for both the modes.

Thanks
Srinivas Neeli
> 
> Guenter
> 
> > ---
> >  drivers/watchdog/of_xilinx_wdt.c | 285
> > ++-
> >  1 file changed, 283 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/watchdog/of_xilinx_wdt.c
> > b/drivers/watchdog/of_xilinx_wdt.c
> > index 3b93b60f1a00..3656e716b4f7 100644
> > --- a/drivers/watchdog/of_xilinx_wdt.c
> > +++ b/drivers/watchdog/of_xilinx_wdt.c
> > @@ -2,10 +2,11 @@
> >  /*
> >   * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
> >   *
> > - * (C) Copyright 2013 - 2014 Xilinx, Inc.
> > + * (C) Copyright 2013 - 2021 Xilinx, Inc.
> >   * (C) Copyright 2011 (Alejandro Cabrera )
> >   */
> >
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -17,6 +18,11 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +
> > +#define XWT_WWDT_DEFAULT_TIMEOUT   10
> > +#define XWT_WWDT_MIN_TIMEOUT   1
> > +#define XWT_WWDT_MAX_TIMEOUT   42
> >
> >  /* Register offsets for the Wdt device */
> >  #define XWT_TWCSR0_OFFSET   0x0 /* Control/Status Register0 */
> > @@ -35,15 +41,44 @@
> >  #define XWT_MAX_SELFTEST_LOOP_COUNT 0x0001
> >  #define XWT_TIMER_FAILED0x
> >
> > +/* Register offsets for the WWdt device */
> > +#define XWT_WWDT_MWR_OFFSET0x00
> > +#define XWT_WWDT_ESR_OFFSET0x04
> > +#define XWT_WWDT_FCR_OFFSET0x08
> > +#define XWT_WWDT_FWR_OFFSET0x0c
> > +#define XWT_WWDT_SWR_OFFSET0x10
> > +
> > +/* Master Write Control Register Masks */
> > +#define XWT_WWDT_MWR_MASK  BIT(0)
> > +
> > +/* Enable and Status Register Masks */
> > +#define XWT_WWDT_ESR_WINT_MASK BIT(16)
> > +#define XWT_WWDT_ESR_WSW_MASK  BIT(8)
> > +#define XWT_WWDT_ESR_WEN_MASK  BIT(0)
> > +
> > +/* Function control Register Masks */
> > +#define XWT_WWDT_SBC_MASK  0xFF00
> > +#define XWT_WWDT_SBC_SHIFT 16
> > +#define XWT_WWDT_BSS_MASK  0xC0
> > +
> >  #define WATCHDOG_NAME "Xilinx Watchdog"
> >
> > +static int wdt_timeout;
> > +
> > +module_param(wdt_timeout, int, 0644);
> MODULE_PARM_DESC(wdt_timeout,
> > +"Watchdog time in seconds. (default="
> > +__MODULE_STRING(XWT_WWDT_DEFAULT_TIMEOUT) ")");
> > +
> >  /**
> >   * enum xwdt_ip_type - WDT IP type.
> >   *
> >   * @XWDT_WDT: Soft wdt ip.
> > + * @XWDT_WWDT: Window wdt ip.
> >   */
> >  enum xwdt_ip_type {
> > XWDT_WDT = 0,
> > +   XWDT_WWDT = 1,
> >  };
> >
> >  struct xwdt_devtype_data {
> > @@ -58,6 +93,7 @@ struct xwdt_device {
> > spinlock_t spinlock; /* spinlock for register handling */
> > struct watchdog_device xilinx_wdt_wdd;
> > struct clk  *clk;
> > +   int irq;
> >  };
> >
> >  static int xilinx_wdt_start(struct watchdog_device *wdd) @@ -145,6
> > +181,220 @@ static const struct watchdog_ops xilinx_wdt_ops = {
> > .ping = xilinx_wdt_keepalive,
> >  };
> >
> > +static int is_wwdt_in_closed_window(struct watchdog_device *wdd) {
> > +   u32 control_status_reg;
> > +   struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
> > +
> > +   control_status_reg = ioread32(xdev->base +
> XWT_WWDT_ESR_OFFSET);
> > +   if (control_status_reg & XWT_WWDT_ESR_WEN_MASK)
> > +   if (!(control_status_reg & XWT_WWDT_ESR_WSW_MASK))
> > +   return 0;
> > +
> > +   return 1;
> > +}
> > +
> > +static int xilinx_wwdt_start(struct watchdog_device *wdd) {
> > +   int ret;
> > +   u32 control_status_reg, fcr;
> > +   u64 time_out, pre_timeout, count;
> > +   struct xwdt_device *xdev = watchdog_get_drvdata

RE: [PATCH v3] dt-binding: leds: Document leds-multi-gpio bindings

2021-03-23 Thread Hermes Zhang

> >
> > Notes:
> > Add maxItems
> 
> What about the other part of the series? I think you should send both
> patches together with an introduction message on both. If you only change
> one patch for a new version spin of the series, just send the other one
> unchanged.
> 
> (It makes no sense to merge the binding as long as the driver is not merged,
> otherwise you would end up with a binding without driver. So keeping them
> together should help reviewers and maintainers.)
> 

Hi Alexander,

The other part is here: https://lore.kernel.org/patchwork/patch/1399875/, so do 
you mean I need to combine these two as one commit? Or is there anyway to link 
them together? Thanks.

I'm first time to commit a new driver, sorry for that.

Best Regards,
Hermes

Re: [PATCH 2/2] streamline_config.pl: Add softtabstop=4 for vim users

2021-03-23 Thread Masahiro Yamada

On Tue, Mar 23, 2021 at 6:40 AM Steven Rostedt  wrote:
>
> From: "Steven Rostedt (VMware)" 
>
> The tab stop for Perl files is by default (at least in emacs) to be 4
> spaces, where a tab is used for all 8 spaces. Add a local variable comment
> to make vim do the same by default, and this will help keep the file
> consistent in the future when others edit it via vim and not emacs.
>
> Signed-off-by: Steven Rostedt (VMware) 


Documentation/process/coding-style.rst says "do not do this".

Rather, I want to remove this ugly stuff entirely.
https://lore.kernel.org/patchwork/patch/1401439/

Adding .editorconfig seems OK to me, but
Doing this in individual files in an editor-specific
manner is a horror.





> ---
>  scripts/kconfig/streamline_config.pl | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/scripts/kconfig/streamline_config.pl 
> b/scripts/kconfig/streamline_config.pl
> index 059061b6daef..044829972ba5 100755
> --- a/scripts/kconfig/streamline_config.pl
> +++ b/scripts/kconfig/streamline_config.pl
> @@ -702,3 +702,5 @@ foreach my $module (keys(%modules)) {
> print STDERR "\n";
>  }
>  }
> +
> +# vim: softtabstop=4
> --
> 2.30.1
>
>


-- 
Best Regards
Masahiro Yamada

[PATCH] sparc/traps_64.c: Mundane typo fixes

s/conditon/condition/
s/periof/period/

Signed-off-by: Bhaskar Chowdhury 
---
 arch/sparc/kernel/traps_64.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/sparc/kernel/traps_64.c b/arch/sparc/kernel/traps_64.c
index a850dccd78ea..2353ba7e1469 100644
--- a/arch/sparc/kernel/traps_64.c
+++ b/arch/sparc/kernel/traps_64.c

-/* Return the highest priority error conditon mentioned. */
+/* Return the highest priority error condition mentioned. */
@@ -1853,7 +1853,7 @@ struct sun4v_error_entry {
/* ID of the CPU */
 /*0x24*/u16err_cpu;

-   /* Grace periof for shutdown, in seconds */
+   /* Grace period for shutdown, in seconds */
 /*0x26*/u16err_secs;

/* Value of the %asi register */
--
2.30.1

Re: [PATCH v3] dt-binding: leds: Document leds-multi-gpio bindings

2021-03-23 Thread Alexander Dahl

Hello Hermes,

> Hermes Zhang  hat am 24.03.2021 03:48 geschrieben:
> 
>  
> From: Hermes Zhang 
> 
> Document the device tree bindings of the multiple GPIOs LED driver
> Documentation/devicetree/bindings/leds/leds-multi-gpio.yaml.
> 
> Signed-off-by: Hermes Zhang 
> ---
> 
> Notes:
> Add maxItems

What about the other part of the series? I think you should send both patches 
together with an introduction message on both. If you only change one patch for 
a new version spin of the series, just send the other one unchanged.

(It makes no sense to merge the binding as long as the driver is not merged, 
otherwise you would end up with a binding without driver. So keeping them 
together should help reviewers and maintainers.)

Greets
Alex

> 
>  .../bindings/leds/leds-multi-gpio.yaml| 50 +++
>  1 file changed, 50 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/leds/leds-multi-gpio.yaml
> 
> diff --git a/Documentation/devicetree/bindings/leds/leds-multi-gpio.yaml 
> b/Documentation/devicetree/bindings/leds/leds-multi-gpio.yaml
> new file mode 100644
> index ..6f2b47487b90
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/leds/leds-multi-gpio.yaml
> @@ -0,0 +1,50 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/leds/leds-multi-gpio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Multiple GPIOs LED driver
> +
> +maintainers:
> +  - Hermes Zhang 
> +
> +description:
> +  This will support some LED made of multiple GPIOs and the brightness of the
> +  LED could map to different states of the GPIOs.
> +
> +properties:
> +  compatible:
> +const: multi-gpio-led
> +
> +  led-gpios:
> +description: Array of one or more GPIOs pins used to control the LED.
> +minItems: 1
> +maxItems: 8  # Should be enough
> +
> +  led-states:
> +description: |
> +  The array list the supported states here which will map to brightness
> +  from 0 to maximum. Each item in the array will present all the GPIOs
> +  value by bit.
> +$ref: /schemas/types.yaml#/definitions/uint8-array
> +minItems: 1
> +maxItems: 16 # Should be enough
> +
> +required:
> +  - compatible
> +  - led-gpios
> +  - led-states
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +gpios-led {
> +  compatible = "multi-gpio-led";
> +
> +  led-gpios = <&gpio0 23 0x1>,
> +  <&gpio0 24 0x1>;
> +  led-states = /bits/ 8 <0x00 0x01 0x02 0x03>;
> +};
> +...
> -- 
> 2.20.1

ERROR: "devm_platform_ioremap_resource" undefined!

2021-03-23 Thread kernel test robot

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
master
head:   7acac4b3196caee5e21fb5ea53f8bc124e6a16fc
commit: a9c56721d6ae99b22e983d0722e6b1b53a11dd59 dmaengine: dw: platform: Use 
devm_platform_ioremap_resource()
date:   1 year, 7 months ago
config: s390-randconfig-r013-20210324 (attached as .config)
compiler: s390-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a9c56721d6ae99b22e983d0722e6b1b53a11dd59
git remote add linus 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout a9c56721d6ae99b22e983d0722e6b1b53a11dd59
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross 
ARCH=s390 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

>> ERROR: "devm_platform_ioremap_resource" [drivers/dma/dw/dw_dmac.ko] 
>> undefined!

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org


.config.gz
Description: application/gzip

Re: [PATCH v2 0/7] remove different PHY fixups

2021-03-23 Thread Oleksij Rempel

Hi Shawn,

ping, do this patches need some ACK from some one?

Regards,
Oleksij

On Tue, Mar 09, 2021 at 12:26:08PM +0100, Oleksij Rempel wrote:
> changes v2:
> - rebase against latest kernel
> - fix networking on RIoTBoard
> 
> This patch series tries to remove most of the imx6 and imx7 board
> specific PHY configuration via fixup, as this breaks the PHYs when
> connected to switch chips or USB Ethernet MACs.
> 
> Each patch has the possibility to break boards, but contains a
> recommendation to fix the problem in a more portable and future-proof
> way.
> 
> regards,
> Oleksij
> 
> Oleksij Rempel (7):
>   ARM: imx6q: remove PHY fixup for KSZ9031
>   ARM: imx6q: remove TX clock delay of ar8031_phy_fixup()
>   ARM: imx6q: remove hand crafted PHY power up in ar8035_phy_fixup()
>   ARM: imx6q: remove clk-out fixup for the Atheros AR8031 and AR8035
> PHYs
>   ARM: imx6q: remove Atheros AR8035 SmartEEE fixup
>   ARM: imx6sx: remove Atheros AR8031 PHY fixup
>   ARM: imx7d: remove Atheros AR8031 PHY fixup
> 
>  arch/arm/boot/dts/imx6dl-riotboard.dts  |  2 +
>  arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts |  2 +-
>  arch/arm/mach-imx/mach-imx6q.c  | 85 -
>  arch/arm/mach-imx/mach-imx6sx.c | 26 
>  arch/arm/mach-imx/mach-imx7d.c  | 22 ---
>  5 files changed, 3 insertions(+), 134 deletions(-)
> 
> -- 
> 2.29.2
> 
> 

-- 
Pengutronix e.K.   | |
Steuerwalder Str. 21   | http://www.pengutronix.de/  |
31137 Hildesheim, Germany  | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686   | Fax:   +49-5121-206917- |

Re: [PATCH 2/3] s390/vdso: fix arch_data access for __arch_get_hw_counter()

2021-03-23 Thread Heiko Carstens

On Tue, Mar 23, 2021 at 10:58:18PM +0100, Heiko Carstens wrote:
> Li Wang reported that clock_gettime(CLOCK_MONOTONIC_RAW, ...) returns
> incorrect values when time is provided via vdso instead of system call:
> 
> vdso_ts_nsec = 4484351380985507, vdso_ts.tv_sec = 4484351, vdso_ts.tv_nsec = 
> 380985507
> sys_ts_nsec  = 1446923235377, sys_ts.tv_sec  = 1446, sys_ts.tv_nsec  = 
> 923235377
> 
> Within the s390 specific vdso function __arch_get_hw_counter() tries
> to read tod clock steering values from the arch_data member of the
> passed in vdso_data structure.
> However only the arch_data member of the first clock source base
> (CS_HRES_COARSE) is initialized. For CS_RAW arch_data is not at all
> initialized, which explains the incorrect returned values.
> 
> It is a bit odd to provide the required tod clock steering parameters
> only within the first element of the _vdso_data array. However for
> time namespaces even no member of the _timens_data array contains the
> required data, which would make fixing __arch_get_hw_counter() quite
> complicated.
> 
> Therefore simply add an s390 specific vdso data page which contains
> the tod clock steering parameters. Everything else seems to be
> unnecessary complex.
> 
> Reported-by: Li Wang 
> Fixes: 1ba2d6c0fd4e ("s390/vdso: simplify __arch_get_hw_counter()")
> Fixes: eeab78b05d20 ("s390/vdso: implement generic vdso time namespace 
> support")
> Link: https://lore.kernel.org/linux-s390/YFnxr1ZlMIOIqjfq@osiris
> Signed-off-by: Heiko Carstens 
> ---
>  arch/s390/Kconfig |  1 -
>  arch/s390/include/asm/vdso.h  |  4 +++-
>  arch/s390/include/asm/vdso/data.h | 13 
>  arch/s390/include/asm/vdso/datapage.h | 17 +++
>  arch/s390/include/asm/vdso/gettimeofday.h | 11 --
>  arch/s390/kernel/time.c   |  6 +++---
>  arch/s390/kernel/vdso.c   | 25 ---
>  arch/s390/kernel/vdso64/vdso64.lds.S  |  3 ++-
>  8 files changed, 56 insertions(+), 24 deletions(-)
>  delete mode 100644 arch/s390/include/asm/vdso/data.h
>  create mode 100644 arch/s390/include/asm/vdso/datapage.h

FWIW, alternatively to this and the third patch we could also do the
much shorter and simpler variant below. What I personally don't like
is that data is duplicated.
But on the other hand it is much shorter, and the more I think of it
this seems to be the way to go.
Opinions?

diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index e37285a5101b..fa095ecf0349 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -80,10 +80,12 @@ void __init time_early_init(void)
 {
struct ptff_qto qto;
struct ptff_qui qui;
+   int i;
 
/* Initialize TOD steering parameters */
tod_steering_end = tod_clock_base.tod;
-   vdso_data->arch_data.tod_steering_end = tod_steering_end;
+   for (i = 0; i < CS_BASES; i++)
+   vdso_data[i].arch_data.tod_steering_end = tod_steering_end;
 
if (!test_facility(28))
return;
@@ -366,6 +368,7 @@ static void clock_sync_global(unsigned long delta)
 {
unsigned long now, adj;
struct ptff_qto qto;
+   int i;
 
/* Fixup the monotonic sched clock. */
tod_clock_base.eitod += delta;
@@ -381,8 +384,10 @@ static void clock_sync_global(unsigned long delta)
panic("TOD clock sync offset %li is too large to drift\n",
  tod_steering_delta);
tod_steering_end = now + (abs(tod_steering_delta) << 15);
-   vdso_data->arch_data.tod_steering_end = tod_steering_end;
-   vdso_data->arch_data.tod_steering_delta = tod_steering_delta;
+   for (i = 0; i < CS_BASES; i++) {
+   vdso_data[i].arch_data.tod_steering_end = tod_steering_end;
+   vdso_data[i].arch_data.tod_steering_delta = tod_steering_delta;
+   }
 
/* Update LPAR offset. */
if (ptff_query(PTFF_QTO) && ptff(&qto, sizeof(qto), PTFF_QTO) == 0)

[PATCH] arc/kernel/signal.c: Fix couple of typos



s/unconditonally/unconditionally/
s/gaurantees/guarantees/

Signed-off-by: Bhaskar Chowdhury 
---
 arch/arc/kernel/signal.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
index a78d8f745a67..cf1788fd3812 100644
--- a/arch/arc/kernel/signal.c
+++ b/arch/arc/kernel/signal.c
@@ -259,7 +259,7 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct 
pt_regs *regs)
regs->r2 = (unsigned long)&sf->uc;

/*
-* small optim to avoid unconditonally calling do_sigaltstack
+* small optim to avoid unconditionally calling do_sigaltstack
 * in sigreturn path, now that we only have rt_sigreturn
 */
magic = MAGIC_SIGALTSTK;
@@ -391,7 +391,7 @@ void do_signal(struct pt_regs *regs)
 void do_notify_resume(struct pt_regs *regs)
 {
/*
-* ASM glue gaurantees that this is only called when returning to
+* ASM glue guarantees that this is only called when returning to
 * user mode
 */
if (test_thread_flag(TIF_NOTIFY_RESUME))
--
2.30.1

[PATCH v2 0/3] add one regulator used to power up pcie phy

Changes:
v1 --> v2:
Suggested by Lucas, don't use the boolean property to specify the
different power supplies to PCIe PHY.
Use one regulator to power up PCIe PHY, and the regulator APIs to
get the voltage of it.

[PATCH v2 1/3] dt-bindings: imx6q-pcie: add one regulator used to
[PATCH v2 2/3] arm64: dts: imx8mq-evk: add one regulator used to
[PATCH v2 3/3] PCI: imx: clear vreg bypass when pcie vph voltage is

[PATCH v2 3/3] PCI: imx: clear vreg bypass when pcie vph voltage is 3v3

Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu 
---
 drivers/pci/controller/dwc/pci-imx6.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c 
b/drivers/pci/controller/dwc/pci-imx6.c
index 853ea8e82952..beca085a9300 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -37,6 +37,7 @@
 #define IMX8MQ_GPR_PCIE_REF_USE_PADBIT(9)
 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_ENBIT(10)
 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE   BIT(11)
+#define IMX8MQ_GPR_PCIE_VREG_BYPASSBIT(12)
 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPEGENMASK(11, 8)
 #define IMX8MQ_PCIE2_BASE_ADDR 0x33c0
 
@@ -80,6 +81,7 @@ struct imx6_pcie {
u32 tx_swing_full;
u32 tx_swing_low;
struct regulator*vpcie;
+   struct regulator*vph;
void __iomem*phy_base;
 
/* power domain for pcie */
@@ -611,6 +613,8 @@ static void imx6_pcie_configure_type(struct imx6_pcie 
*imx6_pcie)
 
 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 {
+   int phy_uv;
+
switch (imx6_pcie->drvdata->variant) {
case IMX8MQ:
/*
@@ -621,6 +625,18 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
   imx6_pcie_grp_offset(imx6_pcie),
   IMX8MQ_GPR_PCIE_REF_USE_PAD,
   IMX8MQ_GPR_PCIE_REF_USE_PAD);
+   /*
+* Regarding to the datasheet, the PCIE_VPH is suggested
+* to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
+* VREG_BYPASS should be cleared to zero.
+*/
+   if (imx6_pcie->vph)
+   phy_uv = regulator_get_voltage(imx6_pcie->vph);
+   if (phy_uv > 300)
+   regmap_update_bits(imx6_pcie->iomuxc_gpr,
+  imx6_pcie_grp_offset(imx6_pcie),
+  IMX8MQ_GPR_PCIE_VREG_BYPASS,
+  0);
break;
case IMX7D:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
@@ -1130,6 +1146,13 @@ static int imx6_pcie_probe(struct platform_device *pdev)
imx6_pcie->vpcie = NULL;
}
 
+   imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
+   if (IS_ERR(imx6_pcie->vph)) {
+   if (PTR_ERR(imx6_pcie->vph) != -ENODEV)
+   return PTR_ERR(imx6_pcie->vph);
+   imx6_pcie->vph = NULL;
+   }
+
platform_set_drvdata(pdev, imx6_pcie);
 
ret = imx6_pcie_attach_pd(dev);
-- 
2.17.1

[PATCH v2 1/3] dt-bindings: imx6q-pcie: add one regulator used to power up pcie phy

Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu 
---
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt 
b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index de4b2baf91e8..3248b7192ced 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -38,6 +38,12 @@ Optional properties:
   The regulator will be enabled when initializing the PCIe host and
   disabled either as part of the init process or when shutting down the
   host.
+- vph-supply: Should specify the regulator in charge of PCIe PHY power.
+  On i.MX8MQ, both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe
+  PHY. In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
+  sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, the
+  VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1
+  to 1b'0.
 
 Additional required properties for imx6sx-pcie:
 - clock names: Must include the following additional entries:
-- 
2.17.1

[PATCH v2 2/3] arm64: dts: imx8mq-evk: add one regulator used to power up pcie phy

Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu 
---
 arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts 
b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 85b045253a0e..4d2035e3dd7c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -318,6 +318,7 @@
 <&clk IMX8MQ_CLK_PCIE1_PHY>,
 <&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+   vph-supply = <&vgen5_reg>;
status = "okay";
 };
 
-- 
2.17.1

Re: [PATCH 02/10] ARM: disable CONFIG_IDE in footbridge_defconfig

2021-03-23 Thread Cye Borg

Sure, here it is:
snow / # lspci -vxxx -s 7.0
00:07.0 ISA bridge: Contaq Microsystems 82c693
Flags: bus master, medium devsel, latency 0
Kernel modules: pata_cypress
00: 80 10 93 c6 47 00 80 02 00 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 03 02 00 00 26 60 00 01 f0 60 00 80 80 71 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Best regards,
Barnabas

ps.: let me know, if anything else I can do.

On Tue, Mar 23, 2021 at 7:43 PM Russell King - ARM Linux admin
 wrote:
>
> On Mon, Mar 22, 2021 at 06:10:01PM +0100, Cye Borg wrote:
> > PWS 500au:
> >
> > snow / # lspci -vvx -s 7.1
> > 00:07.1 IDE interface: Contaq Microsystems 82c693 (prog-if 80 [ISA
> > Compatibility mode-only controller, supports bus mastering])
> > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop-
> > ParErr+ Stepping- SERR- FastB2B- DisINTx-
> > Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium
> > >TAbort- SERR-  > Latency: 0
> > Interrupt: pin A routed to IRQ 0
> > Region 0: I/O ports at 01f0 [size=8]
> > Region 1: I/O ports at 03f4
> > Region 4: I/O ports at 9080 [size=16]
> > Kernel driver in use: pata_cypress
> > Kernel modules: pata_cypress
> > 00: 80 10 93 c6 45 00 80 02 00 80 01 01 00 00 80 00
> > 10: f1 01 00 00 f5 03 00 00 00 00 00 00 00 00 00 00
> > 20: 81 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00
> >
> > snow / # lspci -vvx -s 7.2
> > 00:07.2 IDE interface: Contaq Microsystems 82c693 (prog-if 00 [ISA
> > Compatibility mode-only controller])
> > Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop-
> > ParErr+ Stepping- SERR- FastB2B- DisINTx-
> > Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium
> > >TAbort- SERR-  > Latency: 0
> > Interrupt: pin B routed to IRQ 0
> > Region 0: I/O ports at 0170 [size=8]
> > Region 1: I/O ports at 0374
> > Region 4: Memory at 0c24 (32-bit, non-prefetchable)
> > [disabled] [size=64K]
> > Kernel modules: pata_cypress
> > 00: 80 10 93 c6 45 00 80 02 00 00 01 01 00 00 80 00
> > 10: 71 01 00 00 75 03 00 00 00 00 00 00 00 00 00 00
> > 20: 00 00 24 0c 00 00 00 00 00 00 00 00 00 00 00 00
> > 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00
>
> Thanks very much.
>
> Could I also ask for the output of:
>
> # lspci -vxxx -s 7.0
>
> as well please - this will dump all 256 bytes for the ISA bridge, which
> contains a bunch of configuration registers. Thanks.
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

[PATCH] drivers:staging: Simplify the if condition

2021-03-23 Thread caizhichao

From: Zhichao Cai 

Fixes coccicheck warning:
drivers/staging/media/atomisp/pci/sh_css_params.c:4652:24-26: WARNING !A || A 
&& B is equivalent to !A || B

Signed-off-by: Zhichao Cai 
---
 drivers/staging/media/atomisp/pci/sh_css_params.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/staging/media/atomisp/pci/sh_css_params.c 
b/drivers/staging/media/atomisp/pci/sh_css_params.c
index 9fad28b..7467256 100644
--- a/drivers/staging/media/atomisp/pci/sh_css_params.c
+++ b/drivers/staging/media/atomisp/pci/sh_css_params.c
@@ -4649,10 +4649,8 @@ struct ia_css_dvs_6axis_config *
params = stream->isp_params_configs;
 
/* Backward compatibility by default consider pipe as Video*/
-   if (!params || (params &&
-   !params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO])) {
+   if (!params || !params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO])
goto err;
-   }
 
dvs_config = kvcalloc(1, sizeof(struct ia_css_dvs_6axis_config),
  GFP_KERNEL);
-- 
1.9.1

[PATCH] treewide: remove editor modelines and cruft

2021-03-23 Thread Masahiro Yamada

The section "19) Editor modelines and other cruft" in
Documentation/process/coding-style.rst clearly says,
"Do not include any of these in source files."

I recently receive a patch to explicitly add a new one.

Let's do treewide cleanups, otherwise some people follow the existing
code and attempt to upstream their favoriate editor setups.

It is even nicer if scripts/checkpatch.pl can check it.

If we like to impose coding style in an editor-independent manner,
I think editorconfig (patch [1]) is a saner solution.

[1] https://lore.kernel.org/lkml/20200703073143.423557-1-da...@kdrag0n.dev/

Signed-off-by: Masahiro Yamada 
---

You might wonder if I worked on this huge patch manually or generated it by
a tool. I wrote a Python script to generate this patch, but not from a scratch.
I contributed a similar tool to U-Boot some years ago.
(https://github.com/u-boot/u-boot/commit/8ba1f5de4571566be12efaffdad404a506b978e3)
I reused and modified it.

For completeness, this is the code I wrote (ugly since this is not intended for 
upstream)


#!/usr/bin/env python3

import copy
import os
import re
import sys

pattern_local_variables = re.compile(r'Local (V|v)ariables')
pattern_end = re.compile(r'End:')
pattern_blank = re.compile(r'^\s*$')#  empty line
pattern_comment_begin = re.compile(r'^(\s*)/\*')
pattern_comment_end = re.compile(r'\*/$')
pattern_comment_null = re.compile(r' \*$')
pattern_dash = re.compile(r'---')

def extend_matched_lines(lines, matched, pre_patterns, post_patterns, 
extend_pre,
 extend_post):
extended_matched = []

j = matched[0]

for i in matched:
if i == 0 or i < j:
continue
j = i
while j in matched:
j += 1
if j >= len(lines):
break

for p in pre_patterns:
if p.search(lines[i - 1]):
break
else:
# not matched
continue

for p in post_patterns:
if p.search(lines[j]):
break
else:
# not matched
continue

if extend_pre:
extended_matched.append(i - 1)
if extend_post:
extended_matched.append(j)

matched += extended_matched
matched.sort()


def cleanup_one_file(filepath, patterns):

#print(filepath)
with open(filepath) as f:
lines = f.readlines()

matched = []
for i, line in enumerate(lines):
if i - 1 in matched and lines[i - 1][-2:] == '\\\n':
matched.append(i)
continue
for pattern in patterns:
if pattern.search(line):
#print("hit {}".format(line), end='')
m = pattern_comment_begin.match(line)
if m and not pattern_comment_end.search(line):
#print("replace {}".format(line), end='')
lines[i] = m.group(1) + '/*\n'
if i + 1 < len(lines) and 
pattern_comment_end.search(lines[i + 1]):
matched.append(i)
matched.append(i + 1)
else:
matched.append(i)
break

if not matched:
return

while True:
old_matched = copy.copy(matched)
extend_matched_lines(lines, matched, [pattern_local_variables],
 [pattern_end], True, True)

extend_matched_lines(lines, matched, [pattern_comment_begin],
 [pattern_comment_end], True, True)
extend_matched_lines(lines, matched, [pattern_blank, pattern_dash],
 [pattern_comment_end], True, False)
extend_matched_lines(lines, matched, [pattern_comment_begin, 
pattern_comment_null],
 [pattern_comment_null], False, True)
extend_matched_lines(lines, matched, [pattern_blank],
 [pattern_blank], False, True)
if matched == old_matched:
break

# remove blank lines at the end of file
if matched and matched[-1] == len(lines) -1:
i = matched[-1] - 1
while i >= 0 and (i in matched or pattern_blank.search(lines[i])):
matched.append(i)
i -= 1
matched.sort()

with open(filepath, 'w') as f:
for i, line in enumerate(lines):
if i not in matched:
f.write(line)

def main():

cwd = os.getcwd()

if len(sys.argv) > 1:
topdir = os.path.join(cwd, sys.argv[1])
else:
topdir = cwd

exclude_dirs = [ os.path.join(cwd, d) for d in ('.git', 'Documentation') ]

# patterns to remove
strings = ('c-indent-level:', 'tab-width:',
   'vim:', 'version-control:', 'c-basic-offset:',
   'indent-tabs-mode:', 'c-file-style:', 'fill-column:', 
'kept-new-versions:',
   'ispell-local-dictionary', r'mode: (C|c)$', 'Emacs about 
preferred coding style',

Re: [PATCH v5] mm: cma: support sysfs

2021-03-23 Thread Minchan Kim

On Wed, Mar 24, 2021 at 04:34:34AM +, Matthew Wilcox wrote:
> On Tue, Mar 23, 2021 at 08:31:31PM -0700, Minchan Kim wrote:
> > On Wed, Mar 24, 2021 at 03:02:24AM +, Matthew Wilcox wrote:
> > > On Tue, Mar 23, 2021 at 12:50:50PM -0700, Minchan Kim wrote:
> > > > +   /* the number of CMA page successful allocations */
> > > > +   atomic64_t nr_pages_succeeded;
> > > 
> > > > +void cma_sysfs_alloc_pages_count(struct cma *cma, size_t count)
> > > > +{
> > > > +   atomic64_add(count, &cma->nr_pages_succeeded);
> > > > +}
> > > 
> > > I don't understand.  A size_t is a byte count.  But the variable is called
> > > 'nr_pages'.  So which is it, a byte count or a page count?
> > 
> > It's page count. I followed the cma_alloc interface since it has
> > size_t count variable for nr_pages.
> 
> That's very confusing.  cma_alloc is wrong; if it needs to be an
> unsigned long, that's fine.  But it shouldn't be size_t.
> 
> 7.17 of n1256 defines:
> 
>   size_t
> which is the unsigned integer type of the result of the sizeof operator
> 
> Do you want to submit a patch to fix cma_alloc as well?

Sure, but it will be separate patch.

> 
> > Let's go with unsigned long nr_pages:
> > void cma_sysfs_alloc_pages_count(struct cma *cma, unsigned long
> > nr_pages)
> 
> Works for me!

Thanks for review!

Re: [PATCH v6] mm: cma: support sysfs

2021-03-23 Thread Minchan Kim

On Tue, Mar 23, 2021 at 09:47:27PM -0700, John Hubbard wrote:
> On 3/23/21 8:27 PM, Minchan Kim wrote:
> ...
> > > > +static int __init cma_sysfs_init(void)
> > > > +{
> > > > +   unsigned int i;
> > > > +
> > > > +   cma_kobj_root = kobject_create_and_add("cma", mm_kobj);
> > > > +   if (!cma_kobj_root)
> > > > +   return -ENOMEM;
> > > > +
> > > > +   for (i = 0; i < cma_area_count; i++) {
> > > > +   int err;
> > > > +   struct cma *cma;
> > > > +   struct cma_kobject *cma_kobj;
> > > > +
> > > > +   cma_kobj = kzalloc(sizeof(*cma_kobj), GFP_KERNEL);
> > > > +   if (!cma_kobj) {
> > > > +   kobject_put(cma_kobj_root);
> > > > +   return -ENOMEM;
> > > 
> > > This leaks little cma_kobj's all over the floor. :)
> > 
> > I thought kobject_put(cma_kobj_root) should deal with it. No?
> > 
> If this fails when i > 0, there will be cma_kobj instances that
> were stashed in the cma_areas[] array. But this code only deletes
> the most recently allocated cma_kobj, not anything allocated on
> previous iterations of the loop.

Oh, I misunderstood that destroying of root kobject will release
children recursively. Seems not true. Go back to old version.


index 16c81c9cb9b7..418951a3f138 100644
--- a/mm/cma_sysfs.c
+++ b/mm/cma_sysfs.c
@@ -80,20 +80,19 @@ static struct kobj_type cma_ktype = {
 static int __init cma_sysfs_init(void)
 {
unsigned int i;
+   int err;
+   struct cma *cma;
+   struct cma_kobject *cma_kobj;

cma_kobj_root = kobject_create_and_add("cma", mm_kobj);
if (!cma_kobj_root)
return -ENOMEM;

for (i = 0; i < cma_area_count; i++) {
-   int err;
-   struct cma *cma;
-   struct cma_kobject *cma_kobj;
-
cma_kobj = kzalloc(sizeof(*cma_kobj), GFP_KERNEL);
if (!cma_kobj) {
-   kobject_put(cma_kobj_root);
-   return -ENOMEM;
+   err = -ENOMEM;
+   goto out;
}

cma = &cma_areas[i];
@@ -103,11 +102,21 @@ static int __init cma_sysfs_init(void)
   cma_kobj_root, "%s", cma->name);
if (err) {
kobject_put(&cma_kobj->kobj);
-   kobject_put(cma_kobj_root);
-   return err;
+   goto out;
}
}

return 0;
+out:
+   while (--i >= 0) {
+   cma = &cma_areas[i];
+
+   kobject_put(&cma->kobj->kobj);
+   kfree(cma->kobj);
+   cma->kobj = NULL;
+   }
+   kobject_put(cma_kobj_root);
+
+   return err;
 }
 subsys_initcall(cma_sysfs_init);

Re: [PATCH v4 RESEND 3/5] perf/x86/lbr: Move cpuc->lbr_xsave allocation out of sleeping region

2021-03-23 Thread Like Xu


On 2021/3/24 12:04, Namhyung Kim wrote:

On Wed, Mar 24, 2021 at 12:47 PM Like Xu  wrote:


Hi Namhyung,

On 2021/3/24 9:32, Namhyung Kim wrote:

Hello,

On Mon, Mar 22, 2021 at 3:14 PM Like Xu  wrote:

+void reserve_lbr_buffers(struct perf_event *event)
+{
+   struct kmem_cache *kmem_cache = x86_get_pmu()->task_ctx_cache;
+   struct cpu_hw_events *cpuc;
+   int cpu;
+
+   if (!static_cpu_has(X86_FEATURE_ARCH_LBR))
+   return;
+
+   for_each_possible_cpu(cpu) {
+   cpuc = per_cpu_ptr(&cpu_hw_events, cpu);
+   if (kmem_cache && !cpuc->lbr_xsave && !event->attr.precise_ip)
+   cpuc->lbr_xsave = kmem_cache_alloc(kmem_cache, 
GFP_KERNEL);
+   }
+}


I think we should use kmem_cache_alloc_node().


"kmem_cache_alloc_node - Allocate an object on the specified node"

The reserve_lbr_buffers() is called in __x86_pmu_event_init().
When the LBR perf_event is scheduled to another node, it seems
that we will not call init() and allocate again.

Do you mean use kmem_cache_alloc_node() for each numa_nodes_parsed ?


I assume cpuc->lbr_xsave will be accessed for that cpu only.
Then it needs to allocate it in the node that cpu belongs to.
Something like below..

 cpuc->lbr_xsave = kmem_cache_alloc_node(kmem_cache, GFP_KERNEL,
cpu_to_node(cpu));


Thanks, it helps and I will apply it in the next version.



Thanks,
Namhyung

[PATCH] media: venus : hfi: add venus image info into smem

2021-03-23 Thread Dikshita Agarwal

fill fw version info into smem to be printed as part of
soc info.

Signed-off-by: Dikshita Agarwal 
---
 drivers/media/platform/qcom/venus/hfi_msgs.c | 36 ++--
 1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/qcom/venus/hfi_msgs.c 
b/drivers/media/platform/qcom/venus/hfi_msgs.c
index 06a1908..0e94921 100644
--- a/drivers/media/platform/qcom/venus/hfi_msgs.c
+++ b/drivers/media/platform/qcom/venus/hfi_msgs.c
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "core.h"
@@ -14,6 +15,8 @@
 #include "hfi_msgs.h"
 #include "hfi_parser.h"
 
+#define SMEM_IMAGE_VERSION_TABLE 469
+
 static void event_seq_changed(struct venus_core *core, struct venus_inst *inst,
  struct hfi_msg_event_notify_pkt *pkt)
 {
@@ -239,15 +242,44 @@ static void
 sys_get_prop_image_version(struct device *dev,
   struct hfi_msg_sys_property_info_pkt *pkt)
 {
+   u32 i = 0;
+   size_t smem_block_size = 0;
+   u8 *smem_table_ptr;
+   char version[256];
+   const u32 version_string_size = 128;
+   const u32 smem_image_index_venus = 14 * 128;
+   u8 *str_image_version;
int req_bytes;
 
req_bytes = pkt->hdr.size - sizeof(*pkt);
 
-   if (req_bytes < 128 || !pkt->data[1] || pkt->num_properties > 1)
+   if (req_bytes < version_string_size || !pkt->data[1] || 
pkt->num_properties > 1)
/* bad packet */
return;
 
-   dev_dbg(dev, VDBGL "F/W version: %s\n", (u8 *)&pkt->data[1]);
+   str_image_version = (u8 *)&pkt->data[1];
+
+   /*
+* The version string returned by firmware includes null
+* characters at the start and in between. Replace the null
+* characters with space, to print the version info.
+*/
+   for (i = 0; i < version_string_size; i++) {
+   if (str_image_version[i] != '\0')
+   version[i] = str_image_version[i];
+   else
+   version[i] = ' ';
+   }
+
+   version[i] = '\0';
+   dev_dbg(dev, VDBGL "F/W version: %s\n", version);
+
+   smem_table_ptr = qcom_smem_get(QCOM_SMEM_HOST_ANY,
+  SMEM_IMAGE_VERSION_TABLE, 
&smem_block_size);
+   if ((smem_image_index_venus + version_string_size) <= smem_block_size &&
+   smem_table_ptr)
+   memcpy(smem_table_ptr + smem_image_index_venus,
+  str_image_version, version_string_size);
 }
 
 static void hfi_sys_property_info(struct venus_core *core,
-- 
2.7.4

[PATCH v2] locking/mutex: Remove repeated declaration

2021-03-23 Thread Shaokun Zhang

Commit 0cd39f4600ed ("locking/seqlock, headers: Untangle the spaghetti monster")
introduces 'struct ww_acquire_ctx' again, remove the repeated declaration and 
move
the pre-declarations to the top.

Cc: Peter Zijlstra 
Cc: Ingo Molnar 
Cc: Will Deacon 
Cc: Waiman Long 
Cc: Boqun Feng 
Acked-by: Waiman Long 
Signed-off-by: Shaokun Zhang 
---
 include/linux/mutex.h | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/include/linux/mutex.h b/include/linux/mutex.h
index 0cd631a19727..e7a126796937 100644
--- a/include/linux/mutex.h
+++ b/include/linux/mutex.h
@@ -20,6 +20,7 @@
 #include 
 #include 
 
+struct ww_class;
 struct ww_acquire_ctx;
 
 /*
@@ -65,9 +66,6 @@ struct mutex {
 #endif
 };
 
-struct ww_class;
-struct ww_acquire_ctx;
-
 struct ww_mutex {
struct mutex base;
struct ww_acquire_ctx *ctx;
-- 
2.7.4

[PATCH V4 XRT Alveo 20/20] fpga: xrt: Kconfig and Makefile updates for XRT drivers

Update fpga Kconfig/Makefile and add Kconfig/Makefile for new drivers.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 MAINTAINERS| 11 +++
 drivers/Makefile   |  1 +
 drivers/fpga/Kconfig   |  2 ++
 drivers/fpga/Makefile  |  5 +
 drivers/fpga/xrt/Kconfig   |  8 
 drivers/fpga/xrt/lib/Kconfig   | 17 +
 drivers/fpga/xrt/lib/Makefile  | 30 ++
 drivers/fpga/xrt/metadata/Kconfig  | 12 
 drivers/fpga/xrt/metadata/Makefile | 16 
 drivers/fpga/xrt/mgmt/Kconfig  | 15 +++
 drivers/fpga/xrt/mgmt/Makefile | 19 +++
 11 files changed, 136 insertions(+)
 create mode 100644 drivers/fpga/xrt/Kconfig
 create mode 100644 drivers/fpga/xrt/lib/Kconfig
 create mode 100644 drivers/fpga/xrt/lib/Makefile
 create mode 100644 drivers/fpga/xrt/metadata/Kconfig
 create mode 100644 drivers/fpga/xrt/metadata/Makefile
 create mode 100644 drivers/fpga/xrt/mgmt/Kconfig
 create mode 100644 drivers/fpga/xrt/mgmt/Makefile

diff --git a/MAINTAINERS b/MAINTAINERS
index aa84121c5611..44ccc52987ac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7009,6 +7009,17 @@ F:   Documentation/fpga/
 F: drivers/fpga/
 F: include/linux/fpga/
 
+FPGA XRT DRIVERS
+M: Lizhi Hou 
+R: Max Zhen 
+R: Sonal Santan 
+L: linux-f...@vger.kernel.org
+S: Maintained
+W: https://github.com/Xilinx/XRT
+F: Documentation/fpga/xrt.rst
+F: drivers/fpga/xrt/
+F: include/uapi/linux/xrt/
+
 FPU EMULATOR
 M: Bill Metzenthen 
 S: Maintained
diff --git a/drivers/Makefile b/drivers/Makefile
index 6fba7daba591..dbb3b727fc7a 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -179,6 +179,7 @@ obj-$(CONFIG_STM)   += hwtracing/stm/
 obj-$(CONFIG_ANDROID)  += android/
 obj-$(CONFIG_NVMEM)+= nvmem/
 obj-$(CONFIG_FPGA) += fpga/
+obj-$(CONFIG_FPGA_XRT_METADATA) += fpga/
 obj-$(CONFIG_FSI)  += fsi/
 obj-$(CONFIG_TEE)  += tee/
 obj-$(CONFIG_MULTIPLEXER)  += mux/
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 5ff9438b7b46..01410ff000b9 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -227,4 +227,6 @@ config FPGA_MGR_ZYNQMP_FPGA
  to configure the programmable logic(PL) through PS
  on ZynqMP SoC.
 
+source "drivers/fpga/xrt/Kconfig"
+
 endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 18dc9885883a..4b887bf95cb3 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -48,3 +48,8 @@ obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)   += 
dfl-n3000-nios.o
 
 # Drivers for FPGAs which implement DFL
 obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
+
+# XRT drivers for Alveo
+obj-$(CONFIG_FPGA_XRT_METADATA)+= xrt/metadata/
+obj-$(CONFIG_FPGA_XRT_LIB) += xrt/lib/
+obj-$(CONFIG_FPGA_XRT_XMGMT)   += xrt/mgmt/
diff --git a/drivers/fpga/xrt/Kconfig b/drivers/fpga/xrt/Kconfig
new file mode 100644
index ..0e2c59589ddd
--- /dev/null
+++ b/drivers/fpga/xrt/Kconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Xilinx Alveo FPGA device configuration
+#
+
+source "drivers/fpga/xrt/metadata/Kconfig"
+source "drivers/fpga/xrt/lib/Kconfig"
+source "drivers/fpga/xrt/mgmt/Kconfig"
diff --git a/drivers/fpga/xrt/lib/Kconfig b/drivers/fpga/xrt/lib/Kconfig
new file mode 100644
index ..935369fad570
--- /dev/null
+++ b/drivers/fpga/xrt/lib/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# XRT Alveo FPGA device configuration
+#
+
+config FPGA_XRT_LIB
+   tristate "XRT Alveo Driver Library"
+   depends on HWMON && PCI && HAS_IOMEM
+   select FPGA_XRT_METADATA
+   select REGMAP_MMIO
+   help
+ Select this option to enable Xilinx XRT Alveo driver library. This
+ library is core infrastructure of XRT Alveo FPGA drivers which
+ provides functions for working with device nodes, iteration and
+ lookup of platform devices, common interfaces for platform devices,
+ plumbing of function call and ioctls between platform devices and
+ parent partitions.
diff --git a/drivers/fpga/xrt/lib/Makefile b/drivers/fpga/xrt/lib/Makefile
new file mode 100644
index ..58563416efbf
--- /dev/null
+++ b/drivers/fpga/xrt/lib/Makefile
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved.
+#
+# Authors: sonal.san...@xilinx.com
+#
+
+FULL_XRT_PATH=$(srctree)/$(src)/..
+FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt
+
+obj-$(CONFIG_FPGA_XRT_LIB) += xrt-lib.o
+
+xrt-lib-objs :=\
+   lib-drv.o   \
+   xroot.o \
+   xclbin.o\
+   subdev.o\
+   cdev.o  \
+

[PATCH V4 XRT Alveo 18/20] fpga: xrt: DDR calibration platform driver

Add DDR calibration driver. DDR calibration is a hardware function
discovered by walking firmware metadata. A platform device node will
be created for it. Hardware provides DDR calibration status through
this function.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 .../fpga/xrt/include/xleaf/ddr_calibration.h  |  28 +++
 drivers/fpga/xrt/lib/xleaf/ddr_calibration.c  | 226 ++
 2 files changed, 254 insertions(+)
 create mode 100644 drivers/fpga/xrt/include/xleaf/ddr_calibration.h
 create mode 100644 drivers/fpga/xrt/lib/xleaf/ddr_calibration.c

diff --git a/drivers/fpga/xrt/include/xleaf/ddr_calibration.h 
b/drivers/fpga/xrt/include/xleaf/ddr_calibration.h
new file mode 100644
index ..878740c26ca2
--- /dev/null
+++ b/drivers/fpga/xrt/include/xleaf/ddr_calibration.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Cheng Zhen 
+ */
+
+#ifndef _XRT_DDR_CALIBRATION_H_
+#define _XRT_DDR_CALIBRATION_H_
+
+#include "xleaf.h"
+#include 
+
+/*
+ * Memory calibration driver leaf calls.
+ */
+enum xrt_calib_results {
+   XRT_CALIB_UNKNOWN = 0,
+   XRT_CALIB_SUCCEEDED,
+   XRT_CALIB_FAILED,
+};
+
+enum xrt_calib_leaf_cmd {
+   XRT_CALIB_RESULT = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */
+};
+
+#endif /* _XRT_DDR_CALIBRATION_H_ */
diff --git a/drivers/fpga/xrt/lib/xleaf/ddr_calibration.c 
b/drivers/fpga/xrt/lib/xleaf/ddr_calibration.c
new file mode 100644
index ..5a9fa82946cb
--- /dev/null
+++ b/drivers/fpga/xrt/lib/xleaf/ddr_calibration.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA memory calibration driver
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * memory calibration
+ *
+ * Authors:
+ *  Lizhi Hou
+ */
+#include 
+#include 
+#include "xclbin-helper.h"
+#include "metadata.h"
+#include "xleaf/ddr_calibration.h"
+
+#define XRT_CALIB  "xrt_calib"
+
+#define XRT_CALIB_STATUS_REG   0
+#define XRT_CALIB_READ_RETRIES 20
+#define XRT_CALIB_READ_INTERVAL500 /* ms */
+
+static const struct regmap_config calib_regmap_config = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .max_register = 0x1000,
+};
+
+struct calib_cache {
+   struct list_headlink;
+   const char  *ep_name;
+   char*data;
+   u32 data_size;
+};
+
+struct calib {
+   struct platform_device  *pdev;
+   struct regmap   *regmap;
+   struct mutexlock; /* calibration dev lock */
+   struct list_headcache_list;
+   u32 cache_num;
+   enum xrt_calib_results  result;
+};
+
+static void __calib_cache_clean_nolock(struct calib *calib)
+{
+   struct calib_cache *cache, *temp;
+
+   list_for_each_entry_safe(cache, temp, &calib->cache_list, link) {
+   vfree(cache->data);
+   list_del(&cache->link);
+   vfree(cache);
+   }
+   calib->cache_num = 0;
+}
+
+static void calib_cache_clean(struct calib *calib)
+{
+   mutex_lock(&calib->lock);
+   __calib_cache_clean_nolock(calib);
+   mutex_unlock(&calib->lock);
+}
+
+static int calib_calibration(struct calib *calib)
+{
+   u32 times = XRT_CALIB_READ_RETRIES;
+   u32 status;
+   int ret;
+
+   while (times != 0) {
+   ret = regmap_read(calib->regmap, XRT_CALIB_STATUS_REG, &status);
+   if (ret) {
+   xrt_err(calib->pdev, "failed to read status reg %d", 
ret);
+   return ret;
+   }
+
+   if (status & BIT(0))
+   break;
+   msleep(XRT_CALIB_READ_INTERVAL);
+   times--;
+   }
+
+   if (!times) {
+   xrt_err(calib->pdev,
+   "MIG calibration timeout after bitstream download");
+   return -ETIMEDOUT;
+   }
+
+   xrt_info(calib->pdev, "took %dms", (XRT_CALIB_READ_RETRIES - times) *
+XRT_CALIB_READ_INTERVAL);
+   return 0;
+}
+
+static void xrt_calib_event_cb(struct platform_device *pdev, void *arg)
+{
+   struct calib *calib = platform_get_drvdata(pdev);
+   struct xrt_event *evt = (struct xrt_event *)arg;
+   enum xrt_events e = evt->xe_evt;
+   enum xrt_subdev_id id;
+   int ret;
+
+   id = evt->xe_subdev.xevt_subdev_id;
+
+   switch (e) {
+   case XRT_EVENT_POST_CREATION:
+   if (id == XRT_SUBDEV_UCS) {
+   ret = calib_calibration(calib);
+   if (ret)
+   calib->result = XRT_CALIB_FAILED;
+   else
+   calib->result = XRT_CALIB_SUCCEEDED;
+   }
+   break;
+   default:
+   xrt_dbg(pdev, "ignored event %d", e)

[PATCH V4 XRT Alveo 17/20] fpga: xrt: clock frequency counter platform driver

Add clock frequency counter driver. Clock frequency counter is
a hardware function discovered by walking xclbin metadata. A platform
device node will be created for it. Other part of driver can read the
actual clock frequency through clock frequency counter driver.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/include/xleaf/clkfreq.h |  21 ++
 drivers/fpga/xrt/lib/xleaf/clkfreq.c | 240 +++
 2 files changed, 261 insertions(+)
 create mode 100644 drivers/fpga/xrt/include/xleaf/clkfreq.h
 create mode 100644 drivers/fpga/xrt/lib/xleaf/clkfreq.c

diff --git a/drivers/fpga/xrt/include/xleaf/clkfreq.h 
b/drivers/fpga/xrt/include/xleaf/clkfreq.h
new file mode 100644
index ..005441d5df78
--- /dev/null
+++ b/drivers/fpga/xrt/include/xleaf/clkfreq.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Lizhi Hou 
+ */
+
+#ifndef _XRT_CLKFREQ_H_
+#define _XRT_CLKFREQ_H_
+
+#include "xleaf.h"
+
+/*
+ * CLKFREQ driver leaf calls.
+ */
+enum xrt_clkfreq_leaf_cmd {
+   XRT_CLKFREQ_READ = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */
+};
+
+#endif /* _XRT_CLKFREQ_H_ */
diff --git a/drivers/fpga/xrt/lib/xleaf/clkfreq.c 
b/drivers/fpga/xrt/lib/xleaf/clkfreq.c
new file mode 100644
index ..49473adde3fd
--- /dev/null
+++ b/drivers/fpga/xrt/lib/xleaf/clkfreq.c
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA Clock Frequency Counter Driver
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ *  Lizhi Hou
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "metadata.h"
+#include "xleaf.h"
+#include "xleaf/clkfreq.h"
+
+#define CLKFREQ_ERR(clkfreq, fmt, arg...)   \
+   xrt_err((clkfreq)->pdev, fmt "\n", ##arg)
+#define CLKFREQ_WARN(clkfreq, fmt, arg...)  \
+   xrt_warn((clkfreq)->pdev, fmt "\n", ##arg)
+#define CLKFREQ_INFO(clkfreq, fmt, arg...)  \
+   xrt_info((clkfreq)->pdev, fmt "\n", ##arg)
+#define CLKFREQ_DBG(clkfreq, fmt, arg...)   \
+   xrt_dbg((clkfreq)->pdev, fmt "\n", ##arg)
+
+#define XRT_CLKFREQ"xrt_clkfreq"
+
+#define XRT_CLKFREQ_CONTROL_STATUS_MASK0x
+
+#define XRT_CLKFREQ_CONTROL_START  0x1
+#define XRT_CLKFREQ_CONTROL_DONE   0x2
+#define XRT_CLKFREQ_V5_CLK0_ENABLED0x1
+
+#define XRT_CLKFREQ_CONTROL_REG0
+#define XRT_CLKFREQ_COUNT_REG  0x8
+#define XRT_CLKFREQ_V5_COUNT_REG   0x10
+
+#define XRT_CLKFREQ_READ_RETRIES   10
+
+static const struct regmap_config clkfreq_regmap_config = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .max_register = 0x1000,
+};
+
+struct clkfreq {
+   struct platform_device  *pdev;
+   struct regmap   *regmap;
+   const char  *clkfreq_ep_name;
+   struct mutexclkfreq_lock; /* clock counter dev lock */
+};
+
+static int clkfreq_read(struct clkfreq *clkfreq, u32 *freq)
+{
+   int times = XRT_CLKFREQ_READ_RETRIES;
+   u32 status;
+   int ret;
+
+   *freq = 0;
+   mutex_lock(&clkfreq->clkfreq_lock);
+   ret = regmap_write(clkfreq->regmap, XRT_CLKFREQ_CONTROL_REG, 
XRT_CLKFREQ_CONTROL_START);
+   if (ret) {
+   CLKFREQ_INFO(clkfreq, "write start to control reg failed %d", 
ret);
+   goto failed;
+   }
+   while (times != 0) {
+   ret = regmap_read(clkfreq->regmap, XRT_CLKFREQ_CONTROL_REG, 
&status);
+   if (ret) {
+   CLKFREQ_INFO(clkfreq, "read control reg failed %d", 
ret);
+   goto failed;
+   }
+   if ((status & XRT_CLKFREQ_CONTROL_STATUS_MASK) == 
XRT_CLKFREQ_CONTROL_DONE)
+   break;
+   mdelay(1);
+   times--;
+   };
+
+   if (!times) {
+   ret = -ETIMEDOUT;
+   goto failed;
+   }
+
+   if (status & XRT_CLKFREQ_V5_CLK0_ENABLED)
+   ret = regmap_read(clkfreq->regmap, XRT_CLKFREQ_V5_COUNT_REG, 
freq);
+   else
+   ret = regmap_read(clkfreq->regmap, XRT_CLKFREQ_COUNT_REG, freq);
+   if (ret) {
+   CLKFREQ_INFO(clkfreq, "read count failed %d", ret);
+   goto failed;
+   }
+
+   mutex_unlock(&clkfreq->clkfreq_lock);
+
+   return 0;
+
+failed:
+   mutex_unlock(&clkfreq->clkfreq_lock);
+
+   return ret;
+}
+
+static ssize_t freq_show(struct device *dev, struct device_attribute *attr, 
char *buf)
+{
+   struct clkfreq *clkfreq = platform_get_drvdata(to_platform_device(dev));
+   ssize_t count;
+   u32 freq;
+
+   if (clkfreq_read(clkfreq, &freq))
+   return -EINVAL;
+
+   count = snprintf(buf, 64, "%u\n", freq);
+
+   return count;
+}
+static DEVICE_ATTR_RO(freq);
+
+static struct attribute *clkfreq_attrs[] = {
+   &d

[PATCH V4 XRT Alveo 19/20] fpga: xrt: partition isolation platform driver

Add partition isolation platform driver. partition isolation is
a hardware function discovered by walking firmware metadata.
A platform device node will be created for it. Partition isolation
function isolate the different fpga regions

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/include/xleaf/axigate.h |  23 ++
 drivers/fpga/xrt/lib/xleaf/axigate.c | 342 +++
 2 files changed, 365 insertions(+)
 create mode 100644 drivers/fpga/xrt/include/xleaf/axigate.h
 create mode 100644 drivers/fpga/xrt/lib/xleaf/axigate.c

diff --git a/drivers/fpga/xrt/include/xleaf/axigate.h 
b/drivers/fpga/xrt/include/xleaf/axigate.h
new file mode 100644
index ..58f32c76dca1
--- /dev/null
+++ b/drivers/fpga/xrt/include/xleaf/axigate.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Lizhi Hou 
+ */
+
+#ifndef _XRT_AXIGATE_H_
+#define _XRT_AXIGATE_H_
+
+#include "xleaf.h"
+#include "metadata.h"
+
+/*
+ * AXIGATE driver leaf calls.
+ */
+enum xrt_axigate_leaf_cmd {
+   XRT_AXIGATE_CLOSE = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */
+   XRT_AXIGATE_OPEN,
+};
+
+#endif /* _XRT_AXIGATE_H_ */
diff --git a/drivers/fpga/xrt/lib/xleaf/axigate.c 
b/drivers/fpga/xrt/lib/xleaf/axigate.c
new file mode 100644
index ..231bb0335278
--- /dev/null
+++ b/drivers/fpga/xrt/lib/xleaf/axigate.c
@@ -0,0 +1,342 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA AXI Gate Driver
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ *  Lizhi Hou
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "metadata.h"
+#include "xleaf.h"
+#include "xleaf/axigate.h"
+
+#define XRT_AXIGATE "xrt_axigate"
+
+#define XRT_AXIGATE_WRITE_REG  0
+#define XRT_AXIGATE_READ_REG   8
+
+#define XRT_AXIGATE_CTRL_CLOSE 0
+#define XRT_AXIGATE_CTRL_OPEN_BIT0 1
+#define XRT_AXIGATE_CTRL_OPEN_BIT1 2
+
+#define XRT_AXIGATE_INTERVAL   500 /* ns */
+
+struct xrt_axigate {
+   struct platform_device  *pdev;
+   struct regmap   *regmap;
+   struct mutexgate_lock; /* gate dev lock */
+
+   void*evt_hdl;
+   const char  *ep_name;
+
+   boolgate_closed;
+};
+
+static const struct regmap_config axigate_regmap_config = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .max_register = 0x1000,
+};
+
+/* the ep names are in the order of hardware layers */
+static const char * const xrt_axigate_epnames[] = {
+   XRT_MD_NODE_GATE_PLP, /* PLP: Provider Logic Partition */
+   XRT_MD_NODE_GATE_ULP  /* ULP: User Logic Partition */
+};
+
+static inline int close_gate(struct xrt_axigate *gate)
+{
+   u32 val;
+   int ret;
+
+   ret = regmap_write(gate->regmap, XRT_AXIGATE_WRITE_REG, 
XRT_AXIGATE_CTRL_CLOSE);
+   if (ret) {
+   xrt_err(gate->pdev, "write gate failed %d", ret);
+   return ret;
+   }
+   ndelay(XRT_AXIGATE_INTERVAL);
+   /*
+* Legacy hardware requires extra read work properly.
+* This is not on critical path, thus the extra read should not impact 
performance much.
+*/
+   ret = regmap_read(gate->regmap, XRT_AXIGATE_READ_REG, &val);
+   if (ret) {
+   xrt_err(gate->pdev, "read gate failed %d", ret);
+   return ret;
+   }
+
+   return 0;
+}
+
+static inline int open_gate(struct xrt_axigate *gate)
+{
+   u32 val;
+   int ret;
+
+   ret = regmap_write(gate->regmap, XRT_AXIGATE_WRITE_REG, 
XRT_AXIGATE_CTRL_OPEN_BIT1);
+   if (ret) {
+   xrt_err(gate->pdev, "write 2 failed %d", ret);
+   return ret;
+   }
+   ndelay(XRT_AXIGATE_INTERVAL);
+   /*
+* Legacy hardware requires extra read work properly.
+* This is not on critical path, thus the extra read should not impact 
performance much.
+*/
+   ret = regmap_read(gate->regmap, XRT_AXIGATE_READ_REG, &val);
+   if (ret) {
+   xrt_err(gate->pdev, "read 2 failed %d", ret);
+   return ret;
+   }
+   ret = regmap_write(gate->regmap, XRT_AXIGATE_WRITE_REG,
+  XRT_AXIGATE_CTRL_OPEN_BIT0 | 
XRT_AXIGATE_CTRL_OPEN_BIT1);
+   if (ret) {
+   xrt_err(gate->pdev, "write 3 failed %d", ret);
+   return ret;
+   }
+   ndelay(XRT_AXIGATE_INTERVAL);
+   ret = regmap_read(gate->regmap, XRT_AXIGATE_READ_REG, &val);
+   if (ret) {
+   xrt_err(gate->pdev, "read 3 failed %d", ret);
+   return ret;
+   }
+
+   return 0;
+}
+
+static int xrt_axigate_epname_idx(struct platform_device *pdev)
+{
+   struct resource *res;
+   int ret, i;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   if (!res)

[PATCH V4 XRT Alveo 15/20] fpga: xrt: devctl platform driver

Add devctl driver. devctl is a type of hardware function which only has
few registers to read or write. They are discovered by walking firmware
metadata. A platform device node will be created for them.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/include/xleaf/devctl.h |  40 ++
 drivers/fpga/xrt/lib/xleaf/devctl.c | 183 
 2 files changed, 223 insertions(+)
 create mode 100644 drivers/fpga/xrt/include/xleaf/devctl.h
 create mode 100644 drivers/fpga/xrt/lib/xleaf/devctl.c

diff --git a/drivers/fpga/xrt/include/xleaf/devctl.h 
b/drivers/fpga/xrt/include/xleaf/devctl.h
new file mode 100644
index ..b97f3b6d9326
--- /dev/null
+++ b/drivers/fpga/xrt/include/xleaf/devctl.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Lizhi Hou 
+ */
+
+#ifndef _XRT_DEVCTL_H_
+#define _XRT_DEVCTL_H_
+
+#include "xleaf.h"
+
+/*
+ * DEVCTL driver leaf calls.
+ */
+enum xrt_devctl_leaf_cmd {
+   XRT_DEVCTL_READ = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */
+};
+
+enum xrt_devctl_id {
+   XRT_DEVCTL_ROM_UUID = 0,
+   XRT_DEVCTL_DDR_CALIB,
+   XRT_DEVCTL_GOLDEN_VER,
+   XRT_DEVCTL_MAX
+};
+
+struct xrt_devctl_rw {
+   u32 xdr_id;
+   void*xdr_buf;
+   u32 xdr_len;
+   u32 xdr_offset;
+};
+
+struct xrt_devctl_intf_uuid {
+   u32 uuid_num;
+   uuid_t  *uuids;
+};
+
+#endif /* _XRT_DEVCTL_H_ */
diff --git a/drivers/fpga/xrt/lib/xleaf/devctl.c 
b/drivers/fpga/xrt/lib/xleaf/devctl.c
new file mode 100644
index ..ae086d7c431d
--- /dev/null
+++ b/drivers/fpga/xrt/lib/xleaf/devctl.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA devctl Driver
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ *  Lizhi Hou
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "metadata.h"
+#include "xleaf.h"
+#include "xleaf/devctl.h"
+
+#define XRT_DEVCTL "xrt_devctl"
+
+struct xrt_name_id {
+   char *ep_name;
+   int id;
+};
+
+static struct xrt_name_id name_id[XRT_DEVCTL_MAX] = {
+   { XRT_MD_NODE_BLP_ROM, XRT_DEVCTL_ROM_UUID },
+   { XRT_MD_NODE_GOLDEN_VER, XRT_DEVCTL_GOLDEN_VER },
+};
+
+static const struct regmap_config devctl_regmap_config = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+};
+
+struct xrt_devctl {
+   struct platform_device  *pdev;
+   struct regmap   *regmap[XRT_DEVCTL_MAX];
+   ulong   sizes[XRT_DEVCTL_MAX];
+};
+
+static int xrt_devctl_name2id(struct xrt_devctl *devctl, const char *name)
+{
+   int i;
+
+   for (i = 0; i < XRT_DEVCTL_MAX && name_id[i].ep_name; i++) {
+   if (!strncmp(name_id[i].ep_name, name, 
strlen(name_id[i].ep_name) + 1))
+   return name_id[i].id;
+   }
+
+   return -EINVAL;
+}
+
+static int
+xrt_devctl_leaf_call(struct platform_device *pdev, u32 cmd, void *arg)
+{
+   struct xrt_devctl *devctl;
+   int ret = 0;
+
+   devctl = platform_get_drvdata(pdev);
+
+   switch (cmd) {
+   case XRT_XLEAF_EVENT:
+   /* Does not handle any event. */
+   break;
+   case XRT_DEVCTL_READ: {
+   struct xrt_devctl_rw *rw_arg = arg;
+
+   if (rw_arg->xdr_len & 0x3) {
+   xrt_err(pdev, "invalid len %d", rw_arg->xdr_len);
+   return -EINVAL;
+   }
+
+   if (rw_arg->xdr_id >= XRT_DEVCTL_MAX) {
+   xrt_err(pdev, "invalid id %d", rw_arg->xdr_id);
+   return -EINVAL;
+   }
+
+   if (!devctl->regmap[rw_arg->xdr_id]) {
+   xrt_err(pdev, "io not found, id %d",
+   rw_arg->xdr_id);
+   return -EINVAL;
+   }
+
+   ret = regmap_bulk_read(devctl->regmap[rw_arg->xdr_id], 
rw_arg->xdr_offset,
+  rw_arg->xdr_buf,
+  rw_arg->xdr_len / 
devctl_regmap_config.reg_stride);
+   break;
+   }
+   default:
+   xrt_err(pdev, "unsupported cmd %d", cmd);
+   return -EINVAL;
+   }
+
+   return ret;
+}
+
+static int xrt_devctl_probe(struct platform_device *pdev)
+{
+   struct xrt_devctl *devctl = NULL;
+   void __iomem *base = NULL;
+   struct resource *res;
+   int i, id, ret = 0;
+
+   devctl = devm_kzalloc(&pdev->dev, sizeof(*devctl), GFP_KERNEL);
+   if (!devctl)
+   return -ENOMEM;
+
+   devctl->pdev = pdev;
+   platform_set_drvdata(pdev, devctl);
+
+   xrt_info(pdev, "probing...");
+   for (i = 0, res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   res;
+   res = platform_get_resource(pdev, IORESOURCE_MEM, ++

[PATCH V4 XRT Alveo 16/20] fpga: xrt: clock platform driver

Add clock driver. Clock is a hardware function discovered by walking
xclbin metadata. A platform device node will be created for it. Other
part of driver configures clock through clock driver.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/include/xleaf/clock.h |  29 ++
 drivers/fpga/xrt/lib/xleaf/clock.c | 669 +
 2 files changed, 698 insertions(+)
 create mode 100644 drivers/fpga/xrt/include/xleaf/clock.h
 create mode 100644 drivers/fpga/xrt/lib/xleaf/clock.c

diff --git a/drivers/fpga/xrt/include/xleaf/clock.h 
b/drivers/fpga/xrt/include/xleaf/clock.h
new file mode 100644
index ..6858473fd096
--- /dev/null
+++ b/drivers/fpga/xrt/include/xleaf/clock.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Lizhi Hou 
+ */
+
+#ifndef _XRT_CLOCK_H_
+#define _XRT_CLOCK_H_
+
+#include "xleaf.h"
+#include 
+
+/*
+ * CLOCK driver leaf calls.
+ */
+enum xrt_clock_leaf_cmd {
+   XRT_CLOCK_SET = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */
+   XRT_CLOCK_GET,
+   XRT_CLOCK_VERIFY,
+};
+
+struct xrt_clock_get {
+   u16 freq;
+   u32 freq_cnter;
+};
+
+#endif /* _XRT_CLOCK_H_ */
diff --git a/drivers/fpga/xrt/lib/xleaf/clock.c 
b/drivers/fpga/xrt/lib/xleaf/clock.c
new file mode 100644
index ..071485e4bf65
--- /dev/null
+++ b/drivers/fpga/xrt/lib/xleaf/clock.c
@@ -0,0 +1,669 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA Clock Wizard Driver
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ *  Lizhi Hou
+ *  Sonal Santan 
+ *  David Zhang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "metadata.h"
+#include "xleaf.h"
+#include "xleaf/clock.h"
+#include "xleaf/clkfreq.h"
+
+/* XRT_CLOCK_MAX_NUM_CLOCKS should be a concept from XCLBIN_ in the future */
+#define XRT_CLOCK_MAX_NUM_CLOCKS   4
+#define XRT_CLOCK_STATUS_MASK  0x
+#define XRT_CLOCK_STATUS_MEASURE_START 0x1
+#define XRT_CLOCK_STATUS_MEASURE_DONE  0x2
+
+#define XRT_CLOCK_STATUS_REG   0x4
+#define XRT_CLOCK_CLKFBOUT_REG 0x200
+#define XRT_CLOCK_CLKOUT0_REG  0x208
+#define XRT_CLOCK_LOAD_SADDR_SEN_REG   0x25C
+#define XRT_CLOCK_DEFAULT_EXPIRE_SECS  1
+
+#define CLOCK_ERR(clock, fmt, arg...)  \
+   xrt_err((clock)->pdev, fmt "\n", ##arg)
+#define CLOCK_WARN(clock, fmt, arg...) \
+   xrt_warn((clock)->pdev, fmt "\n", ##arg)
+#define CLOCK_INFO(clock, fmt, arg...) \
+   xrt_info((clock)->pdev, fmt "\n", ##arg)
+#define CLOCK_DBG(clock, fmt, arg...)  \
+   xrt_dbg((clock)->pdev, fmt "\n", ##arg)
+
+#define XRT_CLOCK  "xrt_clock"
+
+static const struct regmap_config clock_regmap_config = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .max_register = 0x1000,
+};
+
+struct clock {
+   struct platform_device  *pdev;
+   struct regmap   *regmap;
+   struct mutexclock_lock; /* clock dev lock */
+
+   const char  *clock_ep_name;
+};
+
+/*
+ * Precomputed table with config0 and config2 register values together with
+ * target frequency. The steps are approximately 5 MHz apart. Table is
+ * generated by platform creation tool.
+ */
+static const struct xmgmt_ocl_clockwiz {
+   /* target frequency */
+   u16 ocl;
+   /* config0 register */
+   u32 config0;
+   /* config2 register */
+   u32 config2;
+} frequency_table[] = {
+   /*1275.000*/ { 10, 0x02EE0C01, 0x0001F47F },
+   /*1575.000*/ { 15, 0x02EE0F01, 0x0069},
+   /*1600.000*/ { 20, 0x1001, 0x0050},
+   /*1600.000*/ { 25, 0x1001, 0x0040},
+   /*1575.000*/ { 30, 0x02EE0F01, 0x0001F434},
+   /*1575.000*/ { 35, 0x02EE0F01, 0x002D},
+   /*1600.000*/ { 40, 0x1001, 0x0028},
+   /*1575.000*/ { 45, 0x02EE0F01, 0x0023},
+   /*1600.000*/ { 50, 0x1001, 0x0020},
+   /*1512.500*/ { 55, 0x007D0F01, 0x0001F41B},
+   /*1575.000*/ { 60, 0x02EE0F01, 0xFA1A},
+   /*1462.500*/ { 65, 0x02710E01, 0x0001F416},
+   /*1575.000*/ { 70, 0x02EE0F01, 0x0001F416},
+   /*1575.000*/ { 75, 0x02EE0F01, 0x0015},
+   /*1600.000*/ { 80, 0x1001, 0x0014},
+   /*1487.500*/ { 85, 0x036B0E01, 0x0001F411},
+   /*1575.000*/ { 90, 0x02EE0F01, 0x0001F411},
+   /*1425.000*/ { 95, 0x00FA0E01, 0x000F},
+   /*1600.000*/ { 100, 0x1001, 0x0010},
+   /*1575.000*/ { 105, 0x02EE0F01, 0x000F},
+   /*1512.500*/ { 110, 0x007D0F01, 0x0002EE0D},
+   /*1437.500*/ { 115, 0x01770E01, 0x0001F40C},
+   /*1575.000*/ { 120, 0x02EE0F01, 0x7D0D},
+   /*1562.500*/ { 125, 0x02710F01, 0x0001F40C},
+   /*1462.500*/ { 130, 0x02710E01, 0xFA0B},
+   /*1350.000*/ { 135, 0x01F40D01, 0x000A},
+   /*1575.000*/ { 140, 0x02EE0F01, 0xFA0B},
+   /*1450.000*/

[PATCH V4 XRT Alveo 13/20] fpga: xrt: User Clock Subsystem platform driver

Add User Clock Subsystem (UCS) driver. UCS is a hardware function
discovered by walking xclbin metadata. A platform device node will be
created for it.  UCS enables/disables the dynamic region clocks.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/lib/xleaf/ucs.c | 167 +++
 1 file changed, 167 insertions(+)
 create mode 100644 drivers/fpga/xrt/lib/xleaf/ucs.c

diff --git a/drivers/fpga/xrt/lib/xleaf/ucs.c b/drivers/fpga/xrt/lib/xleaf/ucs.c
new file mode 100644
index ..d91ee229e7cb
--- /dev/null
+++ b/drivers/fpga/xrt/lib/xleaf/ucs.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA UCS Driver
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ *  Lizhi Hou
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "metadata.h"
+#include "xleaf.h"
+#include "xleaf/clock.h"
+
+#define UCS_ERR(ucs, fmt, arg...)   \
+   xrt_err((ucs)->pdev, fmt "\n", ##arg)
+#define UCS_WARN(ucs, fmt, arg...)  \
+   xrt_warn((ucs)->pdev, fmt "\n", ##arg)
+#define UCS_INFO(ucs, fmt, arg...)  \
+   xrt_info((ucs)->pdev, fmt "\n", ##arg)
+#define UCS_DBG(ucs, fmt, arg...)   \
+   xrt_dbg((ucs)->pdev, fmt "\n", ##arg)
+
+#define XRT_UCS"xrt_ucs"
+
+#define XRT_UCS_CHANNEL1_REG   0
+#define XRT_UCS_CHANNEL2_REG   8
+
+#define CLK_MAX_VALUE  6400
+
+static const struct regmap_config ucs_regmap_config = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .max_register = 0x1000,
+};
+
+struct xrt_ucs {
+   struct platform_device  *pdev;
+   struct regmap   *regmap;
+   struct mutexucs_lock; /* ucs dev lock */
+};
+
+static void xrt_ucs_event_cb(struct platform_device *pdev, void *arg)
+{
+   struct xrt_event *evt = (struct xrt_event *)arg;
+   enum xrt_events e = evt->xe_evt;
+   struct platform_device *leaf;
+   enum xrt_subdev_id id;
+   int instance;
+
+   id = evt->xe_subdev.xevt_subdev_id;
+   instance = evt->xe_subdev.xevt_subdev_instance;
+
+   if (e != XRT_EVENT_POST_CREATION) {
+   xrt_dbg(pdev, "ignored event %d", e);
+   return;
+   }
+
+   if (id != XRT_SUBDEV_CLOCK)
+   return;
+
+   leaf = xleaf_get_leaf_by_id(pdev, XRT_SUBDEV_CLOCK, instance);
+   if (!leaf) {
+   xrt_err(pdev, "does not get clock subdev");
+   return;
+   }
+
+   xleaf_call(leaf, XRT_CLOCK_VERIFY, NULL);
+   xleaf_put_leaf(pdev, leaf);
+}
+
+static int ucs_enable(struct xrt_ucs *ucs)
+{
+   int ret;
+
+   mutex_lock(&ucs->ucs_lock);
+   ret = regmap_write(ucs->regmap, XRT_UCS_CHANNEL2_REG, 1);
+   mutex_unlock(&ucs->ucs_lock);
+
+   return ret;
+}
+
+static int
+xrt_ucs_leaf_call(struct platform_device *pdev, u32 cmd, void *arg)
+{
+   switch (cmd) {
+   case XRT_XLEAF_EVENT:
+   xrt_ucs_event_cb(pdev, arg);
+   break;
+   default:
+   xrt_err(pdev, "unsupported cmd %d", cmd);
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
+static int ucs_probe(struct platform_device *pdev)
+{
+   struct xrt_ucs *ucs = NULL;
+   void __iomem *base = NULL;
+   struct resource *res;
+
+   ucs = devm_kzalloc(&pdev->dev, sizeof(*ucs), GFP_KERNEL);
+   if (!ucs)
+   return -ENOMEM;
+
+   platform_set_drvdata(pdev, ucs);
+   ucs->pdev = pdev;
+   mutex_init(&ucs->ucs_lock);
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   if (!res)
+   return -EINVAL;
+
+   base = devm_ioremap_resource(&pdev->dev, res);
+   if (IS_ERR(base))
+   return PTR_ERR(base);
+
+   ucs->regmap = devm_regmap_init_mmio(&pdev->dev, base, 
&ucs_regmap_config);
+   if (IS_ERR(ucs->regmap)) {
+   UCS_ERR(ucs, "map base %pR failed", res);
+   return PTR_ERR(ucs->regmap);
+   }
+   ucs_enable(ucs);
+
+   return 0;
+}
+
+static struct xrt_subdev_endpoints xrt_ucs_endpoints[] = {
+   {
+   .xse_names = (struct xrt_subdev_ep_names[]) {
+   { .ep_name = XRT_MD_NODE_UCS_CONTROL_STATUS },
+   { NULL },
+   },
+   .xse_min_ep = 1,
+   },
+   { 0 },
+};
+
+static struct xrt_subdev_drvdata xrt_ucs_data = {
+   .xsd_dev_ops = {
+   .xsd_leaf_call = xrt_ucs_leaf_call,
+   },
+};
+
+static const struct platform_device_id xrt_ucs_table[] = {
+   { XRT_UCS, (kernel_ulong_t)&xrt_ucs_data },
+   { },
+};
+
+static struct platform_driver xrt_ucs_driver = {
+   .driver = {
+   .name = XRT_UCS,
+   },
+   .probe = ucs_probe,
+   .id_table = xrt_ucs_table,
+};
+
+XRT_LEAF_INIT_FINI_FUNC(XRT_SUBDEV_UCS, ucs);
-- 
2.27.0

[PATCH V4 XRT Alveo 14/20] fpga: xrt: ICAP platform driver

ICAP stands for Hardware Internal Configuration Access Port. ICAP is
discovered by walking firmware metadata. A platform device node will be
created for it. FPGA bitstream is written to hardware through ICAP.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/include/xleaf/icap.h |  27 ++
 drivers/fpga/xrt/lib/xleaf/icap.c | 344 ++
 2 files changed, 371 insertions(+)
 create mode 100644 drivers/fpga/xrt/include/xleaf/icap.h
 create mode 100644 drivers/fpga/xrt/lib/xleaf/icap.c

diff --git a/drivers/fpga/xrt/include/xleaf/icap.h 
b/drivers/fpga/xrt/include/xleaf/icap.h
new file mode 100644
index ..96d39a8934fa
--- /dev/null
+++ b/drivers/fpga/xrt/include/xleaf/icap.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Lizhi Hou 
+ */
+
+#ifndef _XRT_ICAP_H_
+#define _XRT_ICAP_H_
+
+#include "xleaf.h"
+
+/*
+ * ICAP driver leaf calls.
+ */
+enum xrt_icap_leaf_cmd {
+   XRT_ICAP_WRITE = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */
+   XRT_ICAP_GET_IDCODE,
+};
+
+struct xrt_icap_wr {
+   void*xiiw_bit_data;
+   u32 xiiw_data_len;
+};
+
+#endif /* _XRT_ICAP_H_ */
diff --git a/drivers/fpga/xrt/lib/xleaf/icap.c 
b/drivers/fpga/xrt/lib/xleaf/icap.c
new file mode 100644
index ..13db2b759138
--- /dev/null
+++ b/drivers/fpga/xrt/lib/xleaf/icap.c
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA ICAP Driver
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ *  Lizhi Hou
+ *  Sonal Santan 
+ *  Max Zhen 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "metadata.h"
+#include "xleaf.h"
+#include "xleaf/icap.h"
+#include "xclbin-helper.h"
+
+#define XRT_ICAP "xrt_icap"
+
+#define ICAP_ERR(icap, fmt, arg...)\
+   xrt_err((icap)->pdev, fmt "\n", ##arg)
+#define ICAP_WARN(icap, fmt, arg...)   \
+   xrt_warn((icap)->pdev, fmt "\n", ##arg)
+#define ICAP_INFO(icap, fmt, arg...)   \
+   xrt_info((icap)->pdev, fmt "\n", ##arg)
+#define ICAP_DBG(icap, fmt, arg...)\
+   xrt_dbg((icap)->pdev, fmt "\n", ##arg)
+
+/*
+ * AXI-HWICAP IP register layout. Please see
+ * 
https://www.xilinx.com/support/documentation/ip_documentation/axi_hwicap/v3_0/pg134-axi-hwicap.pdf
+ */
+#define ICAP_REG_GIER  0x1C
+#define ICAP_REG_ISR   0x20
+#define ICAP_REG_IER   0x28
+#define ICAP_REG_WF0x100
+#define ICAP_REG_RF0x104
+#define ICAP_REG_SZ0x108
+#define ICAP_REG_CR0x10C
+#define ICAP_REG_SR0x110
+#define ICAP_REG_WFV   0x114
+#define ICAP_REG_RFO   0x118
+#define ICAP_REG_ASR   0x11C
+
+#define ICAP_STATUS_EOS0x4
+#define ICAP_STATUS_DONE   0x1
+
+/*
+ * Canned command sequence to obtain IDCODE of the FPGA
+ */
+static const u32 idcode_stream[] = {
+   /* dummy word */
+   cpu_to_be32(0x),
+   /* sync word */
+   cpu_to_be32(0xaa995566),
+   /* NOP word */
+   cpu_to_be32(0x2000),
+   /* NOP word */
+   cpu_to_be32(0x2000),
+   /* ID code */
+   cpu_to_be32(0x28018001),
+   /* NOP word */
+   cpu_to_be32(0x2000),
+   /* NOP word */
+   cpu_to_be32(0x2000),
+};
+
+static const struct regmap_config icap_regmap_config = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .max_register = 0x1000,
+};
+
+struct icap {
+   struct platform_device  *pdev;
+   struct regmap   *regmap;
+   struct mutexicap_lock; /* icap dev lock */
+
+   u32 idcode;
+};
+
+static int wait_for_done(const struct icap *icap)
+{
+   int i = 0;
+   int ret;
+   u32 w;
+
+   for (i = 0; i < 10; i++) {
+   /*
+* it requires few micro seconds for ICAP to process incoming 
data.
+* Polling every 5us for 10 times would be good enough.
+*/
+   udelay(5);
+   ret = regmap_read(icap->regmap, ICAP_REG_SR, &w);
+   if (ret)
+   return ret;
+   ICAP_INFO(icap, "XHWICAP_SR: %x", w);
+   if (w & (ICAP_STATUS_EOS | ICAP_STATUS_DONE))
+   return 0;
+   }
+
+   ICAP_ERR(icap, "bitstream download timeout");
+   return -ETIMEDOUT;
+}
+
+static int icap_write(const struct icap *icap, const u32 *word_buf, int size)
+{
+   u32 value = 0;
+   int ret;
+   int i;
+
+   for (i = 0; i < size; i++) {
+   value = be32_to_cpu(word_buf[i]);
+   ret = regmap_write(icap->regmap, ICAP_REG_WF, value);
+   if (ret)
+   return ret;
+   }
+
+   ret = regmap_write(icap->regmap, ICAP_REG_CR, 0x1);
+   if (ret)
+   return ret;
+
+

[PATCH V4 XRT Alveo 12/20] fpga: xrt: VSEC platform driver

Add VSEC driver. VSEC is a hardware function discovered by walking
PCI Express configure space. A platform device node will be created
for it. VSEC provides board logic UUID and few offset of other hardware
functions.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/lib/xleaf/vsec.c | 388 ++
 1 file changed, 388 insertions(+)
 create mode 100644 drivers/fpga/xrt/lib/xleaf/vsec.c

diff --git a/drivers/fpga/xrt/lib/xleaf/vsec.c 
b/drivers/fpga/xrt/lib/xleaf/vsec.c
new file mode 100644
index ..8595d23f5710
--- /dev/null
+++ b/drivers/fpga/xrt/lib/xleaf/vsec.c
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA VSEC Driver
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ *  Lizhi Hou
+ */
+
+#include 
+#include 
+#include "metadata.h"
+#include "xleaf.h"
+
+#define XRT_VSEC "xrt_vsec"
+
+#define VSEC_TYPE_UUID 0x50
+#define VSEC_TYPE_FLASH0x51
+#define VSEC_TYPE_PLATINFO 0x52
+#define VSEC_TYPE_MAILBOX  0x53
+#define VSEC_TYPE_END  0xff
+
+#define VSEC_UUID_LEN  16
+
+#define VSEC_REG_FORMAT0x0
+#define VSEC_REG_LENGTH0x4
+#define VSEC_REG_ENTRY 0x8
+
+struct xrt_vsec_header {
+   u32 format;
+   u32 length;
+   u32 entry_sz;
+   u32 rsvd;
+} __packed;
+
+struct xrt_vsec_entry {
+   u8  type;
+   u8  bar_rev;
+   u16 off_lo;
+   u32 off_hi;
+   u8  ver_type;
+   u8  minor;
+   u8  major;
+   u8  rsvd0;
+   u32 rsvd1;
+} __packed;
+
+struct vsec_device {
+   u8  type;
+   char*ep_name;
+   ulong   size;
+   char*regmap;
+};
+
+static struct vsec_device vsec_devs[] = {
+   {
+   .type = VSEC_TYPE_UUID,
+   .ep_name = XRT_MD_NODE_BLP_ROM,
+   .size = VSEC_UUID_LEN,
+   .regmap = "vsec-uuid",
+   },
+   {
+   .type = VSEC_TYPE_FLASH,
+   .ep_name = XRT_MD_NODE_FLASH_VSEC,
+   .size = 4096,
+   .regmap = "vsec-flash",
+   },
+   {
+   .type = VSEC_TYPE_PLATINFO,
+   .ep_name = XRT_MD_NODE_PLAT_INFO,
+   .size = 4,
+   .regmap = "vsec-platinfo",
+   },
+   {
+   .type = VSEC_TYPE_MAILBOX,
+   .ep_name = XRT_MD_NODE_MAILBOX_VSEC,
+   .size = 48,
+   .regmap = "vsec-mbx",
+   },
+};
+
+static const struct regmap_config vsec_regmap_config = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .max_register = 0x1000,
+};
+
+struct xrt_vsec {
+   struct platform_device  *pdev;
+   struct regmap   *regmap;
+   u32 length;
+
+   char*metadata;
+   charuuid[VSEC_UUID_LEN];
+   int group;
+};
+
+static inline int vsec_read_entry(struct xrt_vsec *vsec, u32 index, struct 
xrt_vsec_entry *entry)
+{
+   int ret;
+
+   ret = regmap_bulk_read(vsec->regmap, sizeof(struct xrt_vsec_header) +
+  index * sizeof(struct xrt_vsec_entry), entry,
+  sizeof(struct xrt_vsec_entry) /
+  vsec_regmap_config.reg_stride);
+
+   return ret;
+}
+
+static inline u32 vsec_get_bar(struct xrt_vsec_entry *entry)
+{
+   return ((entry)->bar_rev >> 4) & 0xf;
+}
+
+static inline u64 vsec_get_bar_off(struct xrt_vsec_entry *entry)
+{
+   return (entry)->off_lo | ((u64)(entry)->off_hi << 16);
+}
+
+static inline u32 vsec_get_rev(struct xrt_vsec_entry *entry)
+{
+   return (entry)->bar_rev & 0xf;
+}
+
+static char *type2epname(u32 type)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(vsec_devs); i++) {
+   if (vsec_devs[i].type == type)
+   return (vsec_devs[i].ep_name);
+   }
+
+   return NULL;
+}
+
+static ulong type2size(u32 type)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(vsec_devs); i++) {
+   if (vsec_devs[i].type == type)
+   return (vsec_devs[i].size);
+   }
+
+   return 0;
+}
+
+static char *type2regmap(u32 type)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(vsec_devs); i++) {
+   if (vsec_devs[i].type == type)
+   return (vsec_devs[i].regmap);
+   }
+
+   return NULL;
+}
+
+static int xrt_vsec_add_node(struct xrt_vsec *vsec,
+void *md_blob, struct xrt_vsec_entry *p_entry)
+{
+   struct xrt_md_endpoint ep;
+   char regmap_ver[64];
+   int ret;
+
+   if (!type2epname(p_entry->type))
+   return -EINVA

[PATCH V4 XRT Alveo 11/20] fpga: xrt: fpga-mgr and region implementation for xclbin download

fpga-mgr and region implementation for xclbin download which will be
called from main platform driver

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/mgmt/fmgr-drv.c| 191 +++
 drivers/fpga/xrt/mgmt/fmgr.h|  19 ++
 drivers/fpga/xrt/mgmt/main-region.c | 483 
 3 files changed, 693 insertions(+)
 create mode 100644 drivers/fpga/xrt/mgmt/fmgr-drv.c
 create mode 100644 drivers/fpga/xrt/mgmt/fmgr.h
 create mode 100644 drivers/fpga/xrt/mgmt/main-region.c

diff --git a/drivers/fpga/xrt/mgmt/fmgr-drv.c b/drivers/fpga/xrt/mgmt/fmgr-drv.c
new file mode 100644
index ..12e1cc788ad9
--- /dev/null
+++ b/drivers/fpga/xrt/mgmt/fmgr-drv.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * FPGA Manager Support for Xilinx Alveo Management Function Driver
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors: sonal.san...@xilinx.com
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "xclbin-helper.h"
+#include "xleaf.h"
+#include "fmgr.h"
+#include "xleaf/axigate.h"
+#include "xleaf/icap.h"
+#include "xmgnt.h"
+
+struct xfpga_class {
+   const struct platform_device *pdev;
+   char  name[64];
+};
+
+/*
+ * xclbin download plumbing -- find the download subsystem, ICAP and
+ * pass the xclbin for heavy lifting
+ */
+static int xmgmt_download_bitstream(struct platform_device *pdev,
+   const struct axlf *xclbin)
+
+{
+   struct xclbin_bit_head_info bit_header = { 0 };
+   struct platform_device *icap_leaf = NULL;
+   struct xrt_icap_wr arg;
+   char *bitstream = NULL;
+   u64 bit_len;
+   int ret;
+
+   ret = xrt_xclbin_get_section(DEV(pdev), xclbin, BITSTREAM, (void 
**)&bitstream, &bit_len);
+   if (ret) {
+   xrt_err(pdev, "bitstream not found");
+   return -ENOENT;
+   }
+   ret = xrt_xclbin_parse_bitstream_header(DEV(pdev), bitstream,
+   XCLBIN_HWICAP_BITFILE_BUF_SZ,
+   &bit_header);
+   if (ret) {
+   ret = -EINVAL;
+   xrt_err(pdev, "invalid bitstream header");
+   goto fail;
+   }
+   if (bit_header.header_length + bit_header.bitstream_length > bit_len) {
+   ret = -EINVAL;
+   xrt_err(pdev, "invalid bitstream length. header %d, bitstream 
%d, section len %lld",
+   bit_header.header_length, bit_header.bitstream_length, 
bit_len);
+   goto fail;
+   }
+
+   icap_leaf = xleaf_get_leaf_by_id(pdev, XRT_SUBDEV_ICAP, 
PLATFORM_DEVID_NONE);
+   if (!icap_leaf) {
+   ret = -ENODEV;
+   xrt_err(pdev, "icap does not exist");
+   goto fail;
+   }
+   arg.xiiw_bit_data = bitstream + bit_header.header_length;
+   arg.xiiw_data_len = bit_header.bitstream_length;
+   ret = xleaf_call(icap_leaf, XRT_ICAP_WRITE, &arg);
+   if (ret) {
+   xrt_err(pdev, "write bitstream failed, ret = %d", ret);
+   xleaf_put_leaf(pdev, icap_leaf);
+   goto fail;
+   }
+
+   xleaf_put_leaf(pdev, icap_leaf);
+   vfree(bitstream);
+
+   return 0;
+
+fail:
+   vfree(bitstream);
+
+   return ret;
+}
+
+/*
+ * There is no HW prep work we do here since we need the full
+ * xclbin for its sanity check.
+ */
+static int xmgmt_pr_write_init(struct fpga_manager *mgr,
+  struct fpga_image_info *info,
+  const char *buf, size_t count)
+{
+   const struct axlf *bin = (const struct axlf *)buf;
+   struct xfpga_class *obj = mgr->priv;
+
+   if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+   xrt_info(obj->pdev, "%s only supports partial 
reconfiguration\n", obj->name);
+   return -EINVAL;
+   }
+
+   if (count < sizeof(struct axlf))
+   return -EINVAL;
+
+   if (count > bin->header.length)
+   return -EINVAL;
+
+   xrt_info(obj->pdev, "Prepare download of xclbin %pUb of length %lld B",
+&bin->header.uuid, bin->header.length);
+
+   return 0;
+}
+
+/*
+ * The implementation requries full xclbin image before we can start
+ * programming the hardware via ICAP subsystem. The full image is required
+ * for checking the validity of xclbin and walking the sections to
+ * discover the bitstream.
+ */
+static int xmgmt_pr_write(struct fpga_manager *mgr,
+ const char *buf, size_t count)
+{
+   const struct axlf *bin = (const struct axlf *)buf;
+   struct xfpga_class *obj = mgr->priv;
+
+   if (bin->header.length != count)
+   return -EINVAL;
+
+   return xmgmt_download_bitstream((void *)obj->pdev, bin);
+}
+
+static int xmgmt_pr_write_complete(struct fpga_manager *mgr,
+

[PATCH V4 XRT Alveo 09/20] fpga: xrt: management physical function driver (root)

The PCIE device driver which attaches to management function on Alveo
devices. It instantiates one or more group drivers which, in turn,
instantiate platform drivers. The instantiation of group and platform
drivers is completely dtb driven.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/mgmt/root.c | 333 +++
 1 file changed, 333 insertions(+)
 create mode 100644 drivers/fpga/xrt/mgmt/root.c

diff --git a/drivers/fpga/xrt/mgmt/root.c b/drivers/fpga/xrt/mgmt/root.c
new file mode 100644
index ..f97f92807c01
--- /dev/null
+++ b/drivers/fpga/xrt/mgmt/root.c
@@ -0,0 +1,333 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo Management Function Driver
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Cheng Zhen 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "xroot.h"
+#include "xmgnt.h"
+#include "metadata.h"
+
+#define XMGMT_MODULE_NAME  "xrt-mgmt"
+#define XMGMT_DRIVER_VERSION   "4.0.0"
+
+#define XMGMT_PDEV(xm) ((xm)->pdev)
+#define XMGMT_DEV(xm)  (&(XMGMT_PDEV(xm)->dev))
+#define xmgmt_err(xm, fmt, args...)\
+   dev_err(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args)
+#define xmgmt_warn(xm, fmt, args...)   \
+   dev_warn(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args)
+#define xmgmt_info(xm, fmt, args...)   \
+   dev_info(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args)
+#define xmgmt_dbg(xm, fmt, args...)\
+   dev_dbg(XMGMT_DEV(xm), "%s: " fmt, __func__, ##args)
+#define XMGMT_DEV_ID(_pcidev)  \
+   ({ typeof(_pcidev) (pcidev) = (_pcidev);\
+   ((pci_domain_nr((pcidev)->bus) << 16) | \
+   PCI_DEVID((pcidev)->bus->number, 0)); })
+
+static struct class *xmgmt_class;
+
+/* PCI Device IDs */
+#define PCI_DEVICE_ID_U50_GOLDEN   0xD020
+#define PCI_DEVICE_ID_U50  0x5020
+static const struct pci_device_id xmgmt_pci_ids[] = {
+   { PCI_DEVICE(PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_U50_GOLDEN), }, /* 
Alveo U50 (golden) */
+   { PCI_DEVICE(PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_U50), }, /* Alveo U50 
*/
+   { 0, }
+};
+
+struct xmgmt {
+   struct pci_dev *pdev;
+   void *root;
+
+   bool ready;
+};
+
+static int xmgmt_config_pci(struct xmgmt *xm)
+{
+   struct pci_dev *pdev = XMGMT_PDEV(xm);
+   int rc;
+
+   rc = pcim_enable_device(pdev);
+   if (rc < 0) {
+   xmgmt_err(xm, "failed to enable device: %d", rc);
+   return rc;
+   }
+
+   rc = pci_enable_pcie_error_reporting(pdev);
+   if (rc)
+   xmgmt_warn(xm, "failed to enable AER: %d", rc);
+
+   pci_set_master(pdev);
+
+   rc = pcie_get_readrq(pdev);
+   if (rc > 512)
+   pcie_set_readrq(pdev, 512);
+   return 0;
+}
+
+static int xmgmt_match_slot_and_save(struct device *dev, void *data)
+{
+   struct xmgmt *xm = data;
+   struct pci_dev *pdev = to_pci_dev(dev);
+
+   if (XMGMT_DEV_ID(pdev) == XMGMT_DEV_ID(xm->pdev)) {
+   pci_cfg_access_lock(pdev);
+   pci_save_state(pdev);
+   }
+
+   return 0;
+}
+
+static void xmgmt_pci_save_config_all(struct xmgmt *xm)
+{
+   bus_for_each_dev(&pci_bus_type, NULL, xm, xmgmt_match_slot_and_save);
+}
+
+static int xmgmt_match_slot_and_restore(struct device *dev, void *data)
+{
+   struct xmgmt *xm = data;
+   struct pci_dev *pdev = to_pci_dev(dev);
+
+   if (XMGMT_DEV_ID(pdev) == XMGMT_DEV_ID(xm->pdev)) {
+   pci_restore_state(pdev);
+   pci_cfg_access_unlock(pdev);
+   }
+
+   return 0;
+}
+
+static void xmgmt_pci_restore_config_all(struct xmgmt *xm)
+{
+   bus_for_each_dev(&pci_bus_type, NULL, xm, xmgmt_match_slot_and_restore);
+}
+
+static void xmgmt_root_hot_reset(struct pci_dev *pdev)
+{
+   struct xmgmt *xm = pci_get_drvdata(pdev);
+   struct pci_bus *bus;
+   u8 pci_bctl;
+   u16 pci_cmd, devctl;
+   int i, ret;
+
+   xmgmt_info(xm, "hot reset start");
+
+   xmgmt_pci_save_config_all(xm);
+
+   pci_disable_device(pdev);
+
+   bus = pdev->bus;
+
+   /*
+* When flipping the SBR bit, device can fall off the bus. This is
+* usually no problem at all so long as drivers are working properly
+* after SBR. However, some systems complain bitterly when the device
+* falls off the bus.
+* The quick solution is to temporarily disable the SERR reporting of
+* switch port during SBR.
+*/
+
+   pci_read_config_word(bus->self, PCI_COMMAND, &pci_cmd);
+   pci_write_config_word(bus->self, PCI_COMMAND, (pci_cmd & 
~PCI_COMMAND_SERR));
+   pcie_capability_read_word(bus->self, PCI_EXP_DEVCTL, &devctl);
+   pcie_capability_write_word(bus->self, PCI_EXP_DEVCTL, (devctl & 
~PCI_EXP_DEVCTL_FERE));
+   pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
+   pci_write_config_by

[PATCH V4 XRT Alveo 10/20] fpga: xrt: main platform driver for management function device

platform driver that handles IOCTLs, such as hot reset and xclbin download.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/include/xmgmt-main.h |  34 ++
 drivers/fpga/xrt/mgmt/main.c  | 670 ++
 drivers/fpga/xrt/mgmt/xmgnt.h |  34 ++
 include/uapi/linux/xrt/xmgmt-ioctl.h  |  46 ++
 4 files changed, 784 insertions(+)
 create mode 100644 drivers/fpga/xrt/include/xmgmt-main.h
 create mode 100644 drivers/fpga/xrt/mgmt/main.c
 create mode 100644 drivers/fpga/xrt/mgmt/xmgnt.h
 create mode 100644 include/uapi/linux/xrt/xmgmt-ioctl.h

diff --git a/drivers/fpga/xrt/include/xmgmt-main.h 
b/drivers/fpga/xrt/include/xmgmt-main.h
new file mode 100644
index ..dce9f0d1a0dc
--- /dev/null
+++ b/drivers/fpga/xrt/include/xmgmt-main.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Cheng Zhen 
+ */
+
+#ifndef _XMGMT_MAIN_H_
+#define _XMGMT_MAIN_H_
+
+#include 
+#include "xleaf.h"
+
+enum xrt_mgmt_main_leaf_cmd {
+   XRT_MGMT_MAIN_GET_AXLF_SECTION = XRT_XLEAF_CUSTOM_BASE, /* See comments 
in xleaf.h */
+   XRT_MGMT_MAIN_GET_VBNV,
+};
+
+/* There are three kind of partitions. Each of them is programmed 
independently. */
+enum provider_kind {
+   XMGMT_BLP, /* Base Logic Partition */
+   XMGMT_PLP, /* Provider Logic Partition */
+   XMGMT_ULP, /* User Logic Partition */
+};
+
+struct xrt_mgmt_main_get_axlf_section {
+   enum provider_kind xmmigas_axlf_kind;
+   enum axlf_section_kind xmmigas_section_kind;
+   void *xmmigas_section;
+   u64 xmmigas_section_size;
+};
+
+#endif /* _XMGMT_MAIN_H_ */
diff --git a/drivers/fpga/xrt/mgmt/main.c b/drivers/fpga/xrt/mgmt/main.c
new file mode 100644
index ..f3b46e1fd78b
--- /dev/null
+++ b/drivers/fpga/xrt/mgmt/main.c
@@ -0,0 +1,670 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA MGMT PF entry point driver
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Sonal Santan 
+ */
+
+#include 
+#include 
+#include "xclbin-helper.h"
+#include "metadata.h"
+#include "xleaf.h"
+#include 
+#include "xleaf/devctl.h"
+#include "xmgmt-main.h"
+#include "fmgr.h"
+#include "xleaf/icap.h"
+#include "xleaf/axigate.h"
+#include "xmgnt.h"
+
+#define XMGMT_MAIN "xmgmt_main"
+#define XMGMT_SUPP_XCLBIN_MAJOR 2
+
+#define XMGMT_FLAG_FLASH_READY 1
+#define XMGMT_FLAG_DEVCTL_READY2
+
+#define XMGMT_UUID_STR_LEN 80
+
+struct xmgmt_main {
+   struct platform_device *pdev;
+   struct axlf *firmware_blp;
+   struct axlf *firmware_plp;
+   struct axlf *firmware_ulp;
+   u32 flags;
+   struct fpga_manager *fmgr;
+   struct mutex lock; /* busy lock */
+
+   uuid_t *blp_interface_uuids;
+   u32 blp_interface_uuid_num;
+};
+
+/*
+ * VBNV stands for Vendor, BoardID, Name, Version. It is a string
+ * which describes board and shell.
+ *
+ * Caller is responsible for freeing the returned string.
+ */
+char *xmgmt_get_vbnv(struct platform_device *pdev)
+{
+   struct xmgmt_main *xmm = platform_get_drvdata(pdev);
+   const char *vbnv;
+   char *ret;
+   int i;
+
+   if (xmm->firmware_plp)
+   vbnv = xmm->firmware_plp->header.platform_vbnv;
+   else if (xmm->firmware_blp)
+   vbnv = xmm->firmware_blp->header.platform_vbnv;
+   else
+   return NULL;
+
+   ret = kstrdup(vbnv, GFP_KERNEL);
+   if (!ret)
+   return NULL;
+
+   for (i = 0; i < strlen(ret); i++) {
+   if (ret[i] == ':' || ret[i] == '.')
+   ret[i] = '_';
+   }
+   return ret;
+}
+
+static int get_dev_uuid(struct platform_device *pdev, char *uuidstr, size_t 
len)
+{
+   struct xrt_devctl_rw devctl_arg = { 0 };
+   struct platform_device *devctl_leaf;
+   char uuid_buf[UUID_SIZE];
+   uuid_t uuid;
+   int err;
+
+   devctl_leaf = xleaf_get_leaf_by_epname(pdev, XRT_MD_NODE_BLP_ROM);
+   if (!devctl_leaf) {
+   xrt_err(pdev, "can not get %s", XRT_MD_NODE_BLP_ROM);
+   return -EINVAL;
+   }
+
+   devctl_arg.xdr_id = XRT_DEVCTL_ROM_UUID;
+   devctl_arg.xdr_buf = uuid_buf;
+   devctl_arg.xdr_len = sizeof(uuid_buf);
+   devctl_arg.xdr_offset = 0;
+   err = xleaf_call(devctl_leaf, XRT_DEVCTL_READ, &devctl_arg);
+   xleaf_put_leaf(pdev, devctl_leaf);
+   if (err) {
+   xrt_err(pdev, "can not get uuid: %d", err);
+   return err;
+   }
+   import_uuid(&uuid, uuid_buf);
+   xrt_md_trans_uuid2str(&uuid, uuidstr);
+
+   return 0;
+}
+
+int xmgmt_hot_reset(struct platform_device *pdev)
+{
+   int ret = xleaf_broadcast_event(pdev, XRT_EVENT_PRE_HOT_RESET, false);
+
+   if (ret) {
+   xrt_err(pdev, "offline failed, hot reset is canceled");
+   return ret;
+   }
+
+   xleaf_hot_reset(pdev

[PATCH V4 XRT Alveo 07/20] fpga: xrt: root driver infrastructure

Contains common code for all root drivers and handles root calls from
platform drivers. This is part of root driver infrastructure.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/include/events.h  |  45 +++
 drivers/fpga/xrt/include/xroot.h   | 117 ++
 drivers/fpga/xrt/lib/subdev_pool.h |  53 +++
 drivers/fpga/xrt/lib/xroot.c   | 589 +
 4 files changed, 804 insertions(+)
 create mode 100644 drivers/fpga/xrt/include/events.h
 create mode 100644 drivers/fpga/xrt/include/xroot.h
 create mode 100644 drivers/fpga/xrt/lib/subdev_pool.h
 create mode 100644 drivers/fpga/xrt/lib/xroot.c

diff --git a/drivers/fpga/xrt/include/events.h 
b/drivers/fpga/xrt/include/events.h
new file mode 100644
index ..775171a47c8e
--- /dev/null
+++ b/drivers/fpga/xrt/include/events.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Cheng Zhen 
+ */
+
+#ifndef _XRT_EVENTS_H_
+#define _XRT_EVENTS_H_
+
+#include "subdev_id.h"
+
+/*
+ * Event notification.
+ */
+enum xrt_events {
+   XRT_EVENT_TEST = 0, /* for testing */
+   /*
+* Events related to specific subdev
+* Callback arg: struct xrt_event_arg_subdev
+*/
+   XRT_EVENT_POST_CREATION,
+   XRT_EVENT_PRE_REMOVAL,
+   /*
+* Events related to change of the whole board
+* Callback arg: 
+*/
+   XRT_EVENT_PRE_HOT_RESET,
+   XRT_EVENT_POST_HOT_RESET,
+   XRT_EVENT_PRE_GATE_CLOSE,
+   XRT_EVENT_POST_GATE_OPEN,
+};
+
+struct xrt_event_arg_subdev {
+   enum xrt_subdev_id xevt_subdev_id;
+   int xevt_subdev_instance;
+};
+
+struct xrt_event {
+   enum xrt_events xe_evt;
+   struct xrt_event_arg_subdev xe_subdev;
+};
+
+#endif /* _XRT_EVENTS_H_ */
diff --git a/drivers/fpga/xrt/include/xroot.h b/drivers/fpga/xrt/include/xroot.h
new file mode 100644
index ..91c0aeb30bf8
--- /dev/null
+++ b/drivers/fpga/xrt/include/xroot.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Cheng Zhen 
+ */
+
+#ifndef _XRT_ROOT_H_
+#define _XRT_ROOT_H_
+
+#include 
+#include 
+#include "subdev_id.h"
+#include "events.h"
+
+typedef bool (*xrt_subdev_match_t)(enum xrt_subdev_id,
+   struct platform_device *, void *);
+#define XRT_SUBDEV_MATCH_PREV  ((xrt_subdev_match_t)-1)
+#define XRT_SUBDEV_MATCH_NEXT  ((xrt_subdev_match_t)-2)
+
+/*
+ * Root calls.
+ */
+enum xrt_root_cmd {
+   /* Leaf actions. */
+   XRT_ROOT_GET_LEAF = 0,
+   XRT_ROOT_PUT_LEAF,
+   XRT_ROOT_GET_LEAF_HOLDERS,
+
+   /* Group actions. */
+   XRT_ROOT_CREATE_GROUP,
+   XRT_ROOT_REMOVE_GROUP,
+   XRT_ROOT_LOOKUP_GROUP,
+   XRT_ROOT_WAIT_GROUP_BRINGUP,
+
+   /* Event actions. */
+   XRT_ROOT_EVENT_SYNC,
+   XRT_ROOT_EVENT_ASYNC,
+
+   /* Device info. */
+   XRT_ROOT_GET_RESOURCE,
+   XRT_ROOT_GET_ID,
+
+   /* Misc. */
+   XRT_ROOT_HOT_RESET,
+   XRT_ROOT_HWMON,
+};
+
+struct xrt_root_get_leaf {
+   struct platform_device *xpigl_caller_pdev;
+   xrt_subdev_match_t xpigl_match_cb;
+   void *xpigl_match_arg;
+   struct platform_device *xpigl_tgt_pdev;
+};
+
+struct xrt_root_put_leaf {
+   struct platform_device *xpipl_caller_pdev;
+   struct platform_device *xpipl_tgt_pdev;
+};
+
+struct xrt_root_lookup_group {
+   struct platform_device *xpilp_pdev; /* caller's pdev */
+   xrt_subdev_match_t xpilp_match_cb;
+   void *xpilp_match_arg;
+   int xpilp_grp_inst;
+};
+
+struct xrt_root_get_holders {
+   struct platform_device *xpigh_pdev; /* caller's pdev */
+   char *xpigh_holder_buf;
+   size_t xpigh_holder_buf_len;
+};
+
+struct xrt_root_get_res {
+   struct resource *xpigr_res;
+};
+
+struct xrt_root_get_id {
+   unsigned short  xpigi_vendor_id;
+   unsigned short  xpigi_device_id;
+   unsigned short  xpigi_sub_vendor_id;
+   unsigned short  xpigi_sub_device_id;
+};
+
+struct xrt_root_hwmon {
+   bool xpih_register;
+   const char *xpih_name;
+   void *xpih_drvdata;
+   const struct attribute_group **xpih_groups;
+   struct device *xpih_hwmon_dev;
+};
+
+/*
+ * Callback for leaf to make a root request. Arguments are: parent device, 
parent cookie, req,
+ * and arg.
+ */
+typedef int (*xrt_subdev_root_cb_t)(struct device *, void *, u32, void *);
+int xrt_subdev_root_request(struct platform_device *self, u32 cmd, void *arg);
+
+/*
+ * Defines physical function (MPF / UPF) specific operations
+ * needed in common root driver.
+ */
+struct xroot_physical_function_callback {
+   void (*xpc_hot_reset)(struct pci_dev *pdev);
+};
+
+int xroot_probe(struct pci_dev *pdev, struct xroot_physical_function_callback 
*cb, void **root);
+void xroot_remove(void *root);
+bool xroot_wait_for_bringup(void *root);
+int xroot_add_vsec_node(void

[PATCH V4 XRT Alveo 08/20] fpga: xrt: platform driver infrastructure

Infrastructure code providing APIs for managing leaf driver instance
groups, facilitating inter-leaf driver calls and root calls.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/lib/subdev.c | 865 ++
 1 file changed, 865 insertions(+)
 create mode 100644 drivers/fpga/xrt/lib/subdev.c

diff --git a/drivers/fpga/xrt/lib/subdev.c b/drivers/fpga/xrt/lib/subdev.c
new file mode 100644
index ..6428b183fee3
--- /dev/null
+++ b/drivers/fpga/xrt/lib/subdev.c
@@ -0,0 +1,865 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Cheng Zhen 
+ */
+
+#include 
+#include 
+#include 
+#include "xleaf.h"
+#include "subdev_pool.h"
+#include "lib-drv.h"
+#include "metadata.h"
+
+#define IS_ROOT_DEV(dev) ((dev)->bus == &pci_bus_type)
+static inline struct device *find_root(struct platform_device *pdev)
+{
+   struct device *d = DEV(pdev);
+
+   while (!IS_ROOT_DEV(d))
+   d = d->parent;
+   return d;
+}
+
+/*
+ * It represents a holder of a subdev. One holder can repeatedly hold a subdev
+ * as long as there is a unhold corresponding to a hold.
+ */
+struct xrt_subdev_holder {
+   struct list_head xsh_holder_list;
+   struct device *xsh_holder;
+   int xsh_count;
+   struct kref xsh_kref;
+};
+
+/*
+ * It represents a specific instance of platform driver for a subdev, which
+ * provides services to its clients (another subdev driver or root driver).
+ */
+struct xrt_subdev {
+   struct list_head xs_dev_list;
+   struct list_head xs_holder_list;
+   enum xrt_subdev_id xs_id;   /* type of subdev */
+   struct platform_device *xs_pdev;/* a particular subdev inst */
+   struct completion xs_holder_comp;
+};
+
+static struct xrt_subdev *xrt_subdev_alloc(void)
+{
+   struct xrt_subdev *sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
+
+   if (!sdev)
+   return NULL;
+
+   INIT_LIST_HEAD(&sdev->xs_dev_list);
+   INIT_LIST_HEAD(&sdev->xs_holder_list);
+   init_completion(&sdev->xs_holder_comp);
+   return sdev;
+}
+
+static void xrt_subdev_free(struct xrt_subdev *sdev)
+{
+   kfree(sdev);
+}
+
+int xrt_subdev_root_request(struct platform_device *self, u32 cmd, void *arg)
+{
+   struct device *dev = DEV(self);
+   struct xrt_subdev_platdata *pdata = DEV_PDATA(self);
+
+   WARN_ON(!pdata->xsp_root_cb);
+   return (*pdata->xsp_root_cb)(dev->parent, pdata->xsp_root_cb_arg, cmd, 
arg);
+}
+
+/*
+ * Subdev common sysfs nodes.
+ */
+static ssize_t holders_show(struct device *dev, struct device_attribute *attr, 
char *buf)
+{
+   ssize_t len;
+   struct platform_device *pdev = to_platform_device(dev);
+   struct xrt_root_get_holders holders = { pdev, buf, 1024 };
+
+   len = xrt_subdev_root_request(pdev, XRT_ROOT_GET_LEAF_HOLDERS, 
&holders);
+   if (len >= holders.xpigh_holder_buf_len)
+   return len;
+   buf[len] = '\n';
+   return len + 1;
+}
+static DEVICE_ATTR_RO(holders);
+
+static struct attribute *xrt_subdev_attrs[] = {
+   &dev_attr_holders.attr,
+   NULL,
+};
+
+static ssize_t metadata_output(struct file *filp, struct kobject *kobj,
+  struct bin_attribute *attr, char *buf, loff_t 
off, size_t count)
+{
+   struct device *dev = kobj_to_dev(kobj);
+   struct platform_device *pdev = to_platform_device(dev);
+   struct xrt_subdev_platdata *pdata = DEV_PDATA(pdev);
+   unsigned char *blob;
+   unsigned long  size;
+   ssize_t ret = 0;
+
+   blob = pdata->xsp_dtb;
+   size = xrt_md_size(dev, blob);
+   if (size == XRT_MD_INVALID_LENGTH) {
+   ret = -EINVAL;
+   goto failed;
+   }
+
+   if (off >= size)
+   goto failed;
+
+   if (off + count > size)
+   count = size - off;
+   memcpy(buf, blob + off, count);
+
+   ret = count;
+failed:
+   return ret;
+}
+
+static struct bin_attribute meta_data_attr = {
+   .attr = {
+   .name = "metadata",
+   .mode = 0400
+   },
+   .read = metadata_output,
+   .size = 0
+};
+
+static struct bin_attribute  *xrt_subdev_bin_attrs[] = {
+   &meta_data_attr,
+   NULL,
+};
+
+static const struct attribute_group xrt_subdev_attrgroup = {
+   .attrs = xrt_subdev_attrs,
+   .bin_attrs = xrt_subdev_bin_attrs,
+};
+
+/*
+ * Given the device metadata, parse it to get IO ranges and construct
+ * resource array.
+ */
+static int
+xrt_subdev_getres(struct device *parent, enum xrt_subdev_id id,
+ char *dtb, struct resource **res, int *res_num)
+{
+   struct xrt_subdev_platdata *pdata;
+   struct resource *pci_res = NULL;
+   const u64 *bar_range;
+   const u32 *bar_idx;
+   char *ep_name = NULL, *regmap = NULL;
+   uint bar;
+   int count1 = 0, count2 = 0, ret

[PATCH V4 XRT Alveo 06/20] fpga: xrt: char dev node helper functions

Helper functions for char device node creation / removal for platform
drivers. This is part of platform driver infrastructure.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/lib/cdev.c | 232 
 1 file changed, 232 insertions(+)
 create mode 100644 drivers/fpga/xrt/lib/cdev.c

diff --git a/drivers/fpga/xrt/lib/cdev.c b/drivers/fpga/xrt/lib/cdev.c
new file mode 100644
index ..38efd24b6e10
--- /dev/null
+++ b/drivers/fpga/xrt/lib/cdev.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA device node helper functions.
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Cheng Zhen 
+ */
+
+#include "xleaf.h"
+
+extern struct class *xrt_class;
+
+#define XRT_CDEV_DIR   "xfpga"
+#define INODE2PDATA(inode) \
+   container_of((inode)->i_cdev, struct xrt_subdev_platdata, xsp_cdev)
+#define INODE2PDEV(inode)  \
+   to_platform_device(kobj_to_dev((inode)->i_cdev->kobj.parent))
+#define CDEV_NAME(sysdev)  (strchr((sysdev)->kobj.name, '!') + 1)
+
+/* Allow it to be accessed from cdev. */
+static void xleaf_devnode_allowed(struct platform_device *pdev)
+{
+   struct xrt_subdev_platdata *pdata = DEV_PDATA(pdev);
+
+   /* Allow new opens. */
+   mutex_lock(&pdata->xsp_devnode_lock);
+   pdata->xsp_devnode_online = true;
+   mutex_unlock(&pdata->xsp_devnode_lock);
+}
+
+/* Turn off access from cdev and wait for all existing user to go away. */
+static int xleaf_devnode_disallowed(struct platform_device *pdev)
+{
+   int ret = 0;
+   struct xrt_subdev_platdata *pdata = DEV_PDATA(pdev);
+
+   mutex_lock(&pdata->xsp_devnode_lock);
+
+   /* Prevent new opens. */
+   pdata->xsp_devnode_online = false;
+   /* Wait for existing user to close. */
+   while (!ret && pdata->xsp_devnode_ref) {
+   int rc;
+
+   mutex_unlock(&pdata->xsp_devnode_lock);
+   rc = wait_for_completion_killable(&pdata->xsp_devnode_comp);
+   mutex_lock(&pdata->xsp_devnode_lock);
+
+   if (rc == -ERESTARTSYS) {
+   /* Restore online state. */
+   pdata->xsp_devnode_online = true;
+   xrt_err(pdev, "%s is in use, ref=%d",
+   CDEV_NAME(pdata->xsp_sysdev),
+   pdata->xsp_devnode_ref);
+   ret = -EBUSY;
+   }
+   }
+
+   mutex_unlock(&pdata->xsp_devnode_lock);
+
+   return ret;
+}
+
+static struct platform_device *
+__xleaf_devnode_open(struct inode *inode, bool excl)
+{
+   struct xrt_subdev_platdata *pdata = INODE2PDATA(inode);
+   struct platform_device *pdev = INODE2PDEV(inode);
+   bool opened = false;
+
+   mutex_lock(&pdata->xsp_devnode_lock);
+
+   if (pdata->xsp_devnode_online) {
+   if (excl && pdata->xsp_devnode_ref) {
+   xrt_err(pdev, "%s has already been opened exclusively",
+   CDEV_NAME(pdata->xsp_sysdev));
+   } else if (!excl && pdata->xsp_devnode_excl) {
+   xrt_err(pdev, "%s has been opened exclusively",
+   CDEV_NAME(pdata->xsp_sysdev));
+   } else {
+   pdata->xsp_devnode_ref++;
+   pdata->xsp_devnode_excl = excl;
+   opened = true;
+   xrt_info(pdev, "opened %s, ref=%d",
+CDEV_NAME(pdata->xsp_sysdev),
+pdata->xsp_devnode_ref);
+   }
+   } else {
+   xrt_err(pdev, "%s is offline", CDEV_NAME(pdata->xsp_sysdev));
+   }
+
+   mutex_unlock(&pdata->xsp_devnode_lock);
+
+   pdev = opened ? pdev : NULL;
+   return pdev;
+}
+
+struct platform_device *
+xleaf_devnode_open_excl(struct inode *inode)
+{
+   return __xleaf_devnode_open(inode, true);
+}
+
+struct platform_device *
+xleaf_devnode_open(struct inode *inode)
+{
+   return __xleaf_devnode_open(inode, false);
+}
+EXPORT_SYMBOL_GPL(xleaf_devnode_open);
+
+void xleaf_devnode_close(struct inode *inode)
+{
+   struct xrt_subdev_platdata *pdata = INODE2PDATA(inode);
+   struct platform_device *pdev = INODE2PDEV(inode);
+   bool notify = false;
+
+   mutex_lock(&pdata->xsp_devnode_lock);
+
+   WARN_ON(pdata->xsp_devnode_ref == 0);
+   pdata->xsp_devnode_ref--;
+   if (pdata->xsp_devnode_ref == 0) {
+   pdata->xsp_devnode_excl = false;
+   notify = true;
+   }
+   if (notify) {
+   xrt_info(pdev, "closed %s, ref=%d",
+CDEV_NAME(pdata->xsp_sysdev), pdata->xsp_devnode_ref);
+   } else {
+   xrt_info(pdev, "closed %s, notifying waiter",
+CDEV_NAME(pdata->xsp_sysdev));
+   }
+
+   mut

[PATCH V4 XRT Alveo 04/20] fpga: xrt: xrt-lib platform driver manager

xrt-lib kernel module infrastructure code to register and manage all
leaf driver modules.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/include/subdev_id.h |  38 
 drivers/fpga/xrt/include/xleaf.h | 264 +
 drivers/fpga/xrt/lib/lib-drv.c   | 277 +++
 drivers/fpga/xrt/lib/lib-drv.h   |  17 ++
 4 files changed, 596 insertions(+)
 create mode 100644 drivers/fpga/xrt/include/subdev_id.h
 create mode 100644 drivers/fpga/xrt/include/xleaf.h
 create mode 100644 drivers/fpga/xrt/lib/lib-drv.c
 create mode 100644 drivers/fpga/xrt/lib/lib-drv.h

diff --git a/drivers/fpga/xrt/include/subdev_id.h 
b/drivers/fpga/xrt/include/subdev_id.h
new file mode 100644
index ..42fbd6f5e80a
--- /dev/null
+++ b/drivers/fpga/xrt/include/subdev_id.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Cheng Zhen 
+ */
+
+#ifndef _XRT_SUBDEV_ID_H_
+#define _XRT_SUBDEV_ID_H_
+
+/*
+ * Every subdev driver has an ID for others to refer to it. There can be 
multiple number of
+ * instances of a subdev driver. A  tuple is a 
unique identification
+ * of a specific instance of a subdev driver.
+ */
+enum xrt_subdev_id {
+   XRT_SUBDEV_GRP = 0,
+   XRT_SUBDEV_VSEC = 1,
+   XRT_SUBDEV_VSEC_GOLDEN = 2,
+   XRT_SUBDEV_DEVCTL = 3,
+   XRT_SUBDEV_AXIGATE = 4,
+   XRT_SUBDEV_ICAP = 5,
+   XRT_SUBDEV_TEST = 6,
+   XRT_SUBDEV_MGMT_MAIN = 7,
+   XRT_SUBDEV_QSPI = 8,
+   XRT_SUBDEV_MAILBOX = 9,
+   XRT_SUBDEV_CMC = 10,
+   XRT_SUBDEV_CALIB = 11,
+   XRT_SUBDEV_CLKFREQ = 12,
+   XRT_SUBDEV_CLOCK = 13,
+   XRT_SUBDEV_SRSR = 14,
+   XRT_SUBDEV_UCS = 15,
+   XRT_SUBDEV_NUM = 16, /* Total number of subdevs. */
+   XRT_ROOT = -1, /* Special ID for root driver. */
+};
+
+#endif /* _XRT_SUBDEV_ID_H_ */
diff --git a/drivers/fpga/xrt/include/xleaf.h b/drivers/fpga/xrt/include/xleaf.h
new file mode 100644
index ..acb500df04b0
--- /dev/null
+++ b/drivers/fpga/xrt/include/xleaf.h
@@ -0,0 +1,264 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ *Cheng Zhen 
+ *Sonal Santan 
+ */
+
+#ifndef _XRT_XLEAF_H_
+#define _XRT_XLEAF_H_
+
+#include 
+#include 
+#include 
+#include "subdev_id.h"
+#include "xroot.h"
+#include "events.h"
+
+/* All subdev drivers should use below common routines to print out msg. */
+#define DEV(pdev)  (&(pdev)->dev)
+#define DEV_PDATA(pdev)\
+   ((struct xrt_subdev_platdata *)dev_get_platdata(DEV(pdev)))
+#define DEV_DRVDATA(pdev)  \
+   ((struct xrt_subdev_drvdata *)  \
+   platform_get_device_id(pdev)->driver_data)
+#define FMT_PRT(prt_fn, pdev, fmt, args...)\
+   ({typeof(pdev) (_pdev) = (pdev);\
+   prt_fn(DEV(_pdev), "%s %s: " fmt,   \
+   DEV_PDATA(_pdev)->xsp_root_name, __func__, ##args); })
+#define xrt_err(pdev, fmt, args...) FMT_PRT(dev_err, pdev, fmt, ##args)
+#define xrt_warn(pdev, fmt, args...) FMT_PRT(dev_warn, pdev, fmt, ##args)
+#define xrt_info(pdev, fmt, args...) FMT_PRT(dev_info, pdev, fmt, ##args)
+#define xrt_dbg(pdev, fmt, args...) FMT_PRT(dev_dbg, pdev, fmt, ##args)
+
+enum {
+   /* Starting cmd for common leaf cmd implemented by all leaves. */
+   XRT_XLEAF_COMMON_BASE = 0,
+   /* Starting cmd for leaves' specific leaf cmds. */
+   XRT_XLEAF_CUSTOM_BASE = 64,
+};
+
+enum xrt_xleaf_common_leaf_cmd {
+   XRT_XLEAF_EVENT = XRT_XLEAF_COMMON_BASE,
+};
+
+/*
+ * If populated by subdev driver, infra will handle the mechanics of
+ * char device (un)registration.
+ */
+enum xrt_subdev_file_mode {
+   /* Infra create cdev, default file name */
+   XRT_SUBDEV_FILE_DEFAULT = 0,
+   /* Infra create cdev, need to encode inst num in file name */
+   XRT_SUBDEV_FILE_MULTI_INST,
+   /* No auto creation of cdev by infra, leaf handles it by itself */
+   XRT_SUBDEV_FILE_NO_AUTO,
+};
+
+struct xrt_subdev_file_ops {
+   const struct file_operations xsf_ops;
+   dev_t xsf_dev_t;
+   const char *xsf_dev_name;
+   enum xrt_subdev_file_mode xsf_mode;
+};
+
+/*
+ * Subdev driver callbacks populated by subdev driver.
+ */
+struct xrt_subdev_drv_ops {
+   /*
+* Per driver instance callback. The pdev points to the instance.
+* If defined, these are called by other leaf drivers.
+* Note that root driver may call into xsd_leaf_call of a group driver.
+*/
+   int (*xsd_leaf_call)(struct platform_device *pdev, u32 cmd, void *arg);
+};
+
+/*
+ * Defined and populated by subdev driver, exported as driver_data in
+ * struct platform_device_id.
+ */
+struct xrt_subdev_drvdata {
+   struct xrt_subdev_file_ops xsd_file_ops;
+   struct xrt_subdev_drv_ops xsd_

[PATCH V4 XRT Alveo 05/20] fpga: xrt: group platform driver

group driver that manages life cycle of a bunch of leaf driver instances
and bridges them with root.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/include/group.h |  25 +++
 drivers/fpga/xrt/lib/group.c | 286 +++
 2 files changed, 311 insertions(+)
 create mode 100644 drivers/fpga/xrt/include/group.h
 create mode 100644 drivers/fpga/xrt/lib/group.c

diff --git a/drivers/fpga/xrt/include/group.h b/drivers/fpga/xrt/include/group.h
new file mode 100644
index ..09e9d03f53fe
--- /dev/null
+++ b/drivers/fpga/xrt/include/group.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Cheng Zhen 
+ */
+
+#ifndef _XRT_GROUP_H_
+#define _XRT_GROUP_H_
+
+#include "xleaf.h"
+
+/*
+ * Group driver leaf calls.
+ */
+enum xrt_group_leaf_cmd {
+   XRT_GROUP_GET_LEAF = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h 
*/
+   XRT_GROUP_PUT_LEAF,
+   XRT_GROUP_INIT_CHILDREN,
+   XRT_GROUP_FINI_CHILDREN,
+   XRT_GROUP_TRIGGER_EVENT,
+};
+
+#endif /* _XRT_GROUP_H_ */
diff --git a/drivers/fpga/xrt/lib/group.c b/drivers/fpga/xrt/lib/group.c
new file mode 100644
index ..7b8716569641
--- /dev/null
+++ b/drivers/fpga/xrt/lib/group.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA Group Driver
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ * Cheng Zhen 
+ */
+
+#include 
+#include 
+#include "xleaf.h"
+#include "subdev_pool.h"
+#include "group.h"
+#include "metadata.h"
+#include "lib-drv.h"
+
+#define XRT_GRP "xrt_group"
+
+struct xrt_group {
+   struct platform_device *pdev;
+   struct xrt_subdev_pool leaves;
+   bool leaves_created;
+   struct mutex lock; /* lock for group */
+};
+
+static int xrt_grp_root_cb(struct device *dev, void *parg,
+  enum xrt_root_cmd cmd, void *arg)
+{
+   int rc;
+   struct platform_device *pdev =
+   container_of(dev, struct platform_device, dev);
+   struct xrt_group *xg = (struct xrt_group *)parg;
+
+   switch (cmd) {
+   case XRT_ROOT_GET_LEAF_HOLDERS: {
+   struct xrt_root_get_holders *holders =
+   (struct xrt_root_get_holders *)arg;
+   rc = xrt_subdev_pool_get_holders(&xg->leaves,
+holders->xpigh_pdev,
+holders->xpigh_holder_buf,
+holders->xpigh_holder_buf_len);
+   break;
+   }
+   default:
+   /* Forward parent call to root. */
+   rc = xrt_subdev_root_request(pdev, cmd, arg);
+   break;
+   }
+
+   return rc;
+}
+
+/*
+ * Cut subdev's dtb from group's dtb based on passed-in endpoint descriptor.
+ * Return the subdev's dtb through dtbp, if found.
+ */
+static int xrt_grp_cut_subdev_dtb(struct xrt_group *xg, struct 
xrt_subdev_endpoints *eps,
+ char *grp_dtb, char **dtbp)
+{
+   int ret, i, ep_count = 0;
+   char *dtb = NULL;
+
+   ret = xrt_md_create(DEV(xg->pdev), &dtb);
+   if (ret)
+   return ret;
+
+   for (i = 0; eps->xse_names[i].ep_name || eps->xse_names[i].regmap_name; 
i++) {
+   const char *ep_name = eps->xse_names[i].ep_name;
+   const char *reg_name = eps->xse_names[i].regmap_name;
+
+   if (!ep_name)
+   xrt_md_get_compatible_endpoint(DEV(xg->pdev), grp_dtb, 
reg_name, &ep_name);
+   if (!ep_name)
+   continue;
+
+   ret = xrt_md_copy_endpoint(DEV(xg->pdev), dtb, grp_dtb, 
ep_name, reg_name, NULL);
+   if (ret)
+   continue;
+   xrt_md_del_endpoint(DEV(xg->pdev), grp_dtb, ep_name, reg_name);
+   ep_count++;
+   }
+   /* Found enough endpoints, return the subdev's dtb. */
+   if (ep_count >= eps->xse_min_ep) {
+   *dtbp = dtb;
+   return 0;
+   }
+
+   /* Cleanup - Restore all endpoints that has been deleted, if any. */
+   if (ep_count > 0) {
+   xrt_md_copy_endpoint(DEV(xg->pdev), grp_dtb, dtb,
+XRT_MD_NODE_ENDPOINTS, NULL, NULL);
+   }
+   vfree(dtb);
+   *dtbp = NULL;
+   return 0;
+}
+
+static int xrt_grp_create_leaves(struct xrt_group *xg)
+{
+   struct xrt_subdev_platdata *pdata = DEV_PDATA(xg->pdev);
+   struct xrt_subdev_endpoints *eps = NULL;
+   int ret = 0, failed = 0;
+   enum xrt_subdev_id did;
+   char *grp_dtb = NULL;
+   unsigned long mlen;
+
+   if (!pdata)
+   return -EINVAL;
+
+   mlen = xrt_md_size(DEV(xg->pdev), pdata->xsp_dtb);
+   if (mlen == XRT_MD_INVALID_LENGTH) {
+   xrt_err(xg->pdev, "invalid dtb

[PATCH V4 XRT Alveo 02/20] fpga: xrt: driver metadata helper functions

XRT drivers use device tree as metadata format to discover HW subsystems
behind PCIe BAR. Thus libfdt functions are called for the driver to parse
device tree blob.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/include/metadata.h  | 233 
 drivers/fpga/xrt/metadata/metadata.c | 545 +++
 2 files changed, 778 insertions(+)
 create mode 100644 drivers/fpga/xrt/include/metadata.h
 create mode 100644 drivers/fpga/xrt/metadata/metadata.c

diff --git a/drivers/fpga/xrt/include/metadata.h 
b/drivers/fpga/xrt/include/metadata.h
new file mode 100644
index ..479e47960c61
--- /dev/null
+++ b/drivers/fpga/xrt/include/metadata.h
@@ -0,0 +1,233 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ *  Lizhi Hou 
+ */
+
+#ifndef _XRT_METADATA_H
+#define _XRT_METADATA_H
+
+#include 
+#include 
+#include 
+
+#define XRT_MD_INVALID_LENGTH (~0UL)
+
+/* metadata properties */
+#define XRT_MD_PROP_BAR_IDX "pcie_bar_mapping"
+#define XRT_MD_PROP_COMPATIBLE "compatible"
+#define XRT_MD_PROP_HWICAP "axi_hwicap"
+#define XRT_MD_PROP_INTERFACE_UUID "interface_uuid"
+#define XRT_MD_PROP_INTERRUPTS "interrupts"
+#define XRT_MD_PROP_IO_OFFSET "reg"
+#define XRT_MD_PROP_LOGIC_UUID "logic_uuid"
+#define XRT_MD_PROP_PDI_CONFIG "pdi_config_mem"
+#define XRT_MD_PROP_PF_NUM "pcie_physical_function"
+#define XRT_MD_PROP_VERSION_MAJOR "firmware_version_major"
+
+/* non IP nodes */
+#define XRT_MD_NODE_ENDPOINTS "addressable_endpoints"
+#define XRT_MD_NODE_FIRMWARE "firmware"
+#define XRT_MD_NODE_INTERFACES "interfaces"
+#define XRT_MD_NODE_PARTITION_INFO "partition_info"
+
+/*
+ * IP nodes
+ * AF:  AXI Firewall
+ * CMC: Card Management Controller
+ * ERT: Embedded Runtime
+ * PLP: Provider Reconfigurable Partition
+ * ULP: User Reconfigurable Partition
+ */
+#define XRT_MD_NODE_ADDR_TRANSLATOR "ep_remap_data_c2h_00"
+#define XRT_MD_NODE_AF_BLP_CTRL_MGMT "ep_firewall_blp_ctrl_mgmt_00"
+#define XRT_MD_NODE_AF_BLP_CTRL_USER "ep_firewall_blp_ctrl_user_00"
+#define XRT_MD_NODE_AF_CTRL_DEBUG "ep_firewall_ctrl_debug_00"
+#define XRT_MD_NODE_AF_CTRL_MGMT "ep_firewall_ctrl_mgmt_00"
+#define XRT_MD_NODE_AF_CTRL_USER "ep_firewall_ctrl_user_00"
+#define XRT_MD_NODE_AF_DATA_C2H "ep_firewall_data_c2h_00"
+#define XRT_MD_NODE_AF_DATA_H2C "ep_firewall_data_h2c_00"
+#define XRT_MD_NODE_AF_DATA_M2M "ep_firewall_data_m2m_00"
+#define XRT_MD_NODE_AF_DATA_P2P "ep_firewall_data_p2p_00"
+#define XRT_MD_NODE_CLKFREQ_HBM "ep_freq_cnt_aclk_hbm_00"
+#define XRT_MD_NODE_CLKFREQ_K1 "ep_freq_cnt_aclk_kernel_00"
+#define XRT_MD_NODE_CLKFREQ_K2 "ep_freq_cnt_aclk_kernel_01"
+#define XRT_MD_NODE_CLK_KERNEL1 "ep_aclk_kernel_00"
+#define XRT_MD_NODE_CLK_KERNEL2 "ep_aclk_kernel_01"
+#define XRT_MD_NODE_CLK_KERNEL3 "ep_aclk_hbm_00"
+#define XRT_MD_NODE_CLK_SHUTDOWN "ep_aclk_shutdown_00"
+#define XRT_MD_NODE_CMC_FW_MEM "ep_cmc_firmware_mem_00"
+#define XRT_MD_NODE_CMC_MUTEX "ep_cmc_mutex_00"
+#define XRT_MD_NODE_CMC_REG "ep_cmc_regmap_00"
+#define XRT_MD_NODE_CMC_RESET "ep_cmc_reset_00"
+#define XRT_MD_NODE_DDR_CALIB "ep_ddr_mem_calib_00"
+#define XRT_MD_NODE_DDR4_RESET_GATE "ep_ddr_mem_srsr_gate_00"
+#define XRT_MD_NODE_ERT_BASE "ep_ert_base_address_00"
+#define XRT_MD_NODE_ERT_CQ_MGMT "ep_ert_command_queue_mgmt_00"
+#define XRT_MD_NODE_ERT_CQ_USER "ep_ert_command_queue_user_00"
+#define XRT_MD_NODE_ERT_FW_MEM "ep_ert_firmware_mem_00"
+#define XRT_MD_NODE_ERT_RESET "ep_ert_reset_00"
+#define XRT_MD_NODE_ERT_SCHED "ep_ert_sched_00"
+#define XRT_MD_NODE_FLASH "ep_card_flash_program_00"
+#define XRT_MD_NODE_FPGA_CONFIG "ep_fpga_configuration_00"
+#define XRT_MD_NODE_GAPPING "ep_gapping_demand_00"
+#define XRT_MD_NODE_GATE_PLP "ep_pr_isolate_plp_00"
+#define XRT_MD_NODE_GATE_ULP "ep_pr_isolate_ulp_00"
+#define XRT_MD_NODE_KDMA_CTRL "ep_kdma_ctrl_00"
+#define XRT_MD_NODE_MAILBOX_MGMT "ep_mailbox_mgmt_00"
+#define XRT_MD_NODE_MAILBOX_USER "ep_mailbox_user_00"
+#define XRT_MD_NODE_MAILBOX_XRT "ep_mailbox_user_to_ert_00"
+#define XRT_MD_NODE_MSIX "ep_msix_00"
+#define XRT_MD_NODE_P2P "ep_p2p_00"
+#define XRT_MD_NODE_PCIE_MON "ep_pcie_link_mon_00"
+#define XRT_MD_NODE_PMC_INTR   "ep_pmc_intr_00"
+#define XRT_MD_NODE_PMC_MUX"ep_pmc_mux_00"
+#define XRT_MD_NODE_QDMA "ep_qdma_00"
+#define XRT_MD_NODE_QDMA4 "ep_qdma4_00"
+#define XRT_MD_NODE_REMAP_P2P "ep_remap_p2p_00"
+#define XRT_MD_NODE_STM "ep_stream_traffic_manager_00"
+#define XRT_MD_NODE_STM4 "ep_stream_traffic_manager4_00"
+#define XRT_MD_NODE_SYSMON "ep_cmp_sysmon_00"
+#define XRT_MD_NODE_XDMA "ep_xdma_00"
+#define XRT_MD_NODE_XVC_PUB "ep_debug_bscan_user_00"
+#define XRT_MD_NODE_XVC_PRI "ep_debug_bscan_mgmt_00"
+#define XRT_MD_NODE_UCS_CONTROL_STATUS "ep_ucs_control_status_00"
+
+/* endpoint regmaps */
+#define XRT_MD_REGMAP_DDR_SRSR "drv_ddr_srsr"
+#define XRT_MD_REGMAP_CLKFREQ "freq_cnt"
+
+/* driver defined endpoints */
+#define XRT_MD_NODE_BLP_ROM "drv_ep_blp_rom_00"
+

[PATCH V4 XRT Alveo 03/20] fpga: xrt: xclbin file helper functions

Alveo FPGA firmware and partial reconfigure file are in xclbin format. This
code enumerates and extracts sections from xclbin files. xclbin.h is cross
platform and used across all platforms and OS.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 drivers/fpga/xrt/include/xclbin-helper.h |  48 +++
 drivers/fpga/xrt/lib/xclbin.c| 369 
 include/uapi/linux/xrt/xclbin.h  | 409 +++
 3 files changed, 826 insertions(+)
 create mode 100644 drivers/fpga/xrt/include/xclbin-helper.h
 create mode 100644 drivers/fpga/xrt/lib/xclbin.c
 create mode 100644 include/uapi/linux/xrt/xclbin.h

diff --git a/drivers/fpga/xrt/include/xclbin-helper.h 
b/drivers/fpga/xrt/include/xclbin-helper.h
new file mode 100644
index ..382b1de97b0a
--- /dev/null
+++ b/drivers/fpga/xrt/include/xclbin-helper.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ *David Zhang 
+ *Sonal Santan 
+ */
+
+#ifndef _XCLBIN_HELPER_H_
+#define _XCLBIN_HELPER_H_
+
+#include 
+#include 
+#include 
+
+#define XCLBIN_VERSION2"xclbin2"
+#define XCLBIN_HWICAP_BITFILE_BUF_SZ 1024
+#define XCLBIN_MAX_SIZE (1024 * 1024 * 1024) /* Assuming xclbin <= 1G, always 
*/
+
+enum axlf_section_kind;
+struct axlf;
+
+/**
+ * Bitstream header information as defined by Xilinx tools.
+ * Please note that this struct definition is not owned by the driver.
+ */
+struct xclbin_bit_head_info {
+   u32 header_length;  /* Length of header in 32 bit words */
+   u32 bitstream_length;   /* Length of bitstream to read in bytes 
*/
+   const unchar *design_name;  /* Design name get from bitstream */
+   const unchar *part_name;/* Part name read from bitstream */
+   const unchar *date; /* Date read from bitstream header */
+   const unchar *time; /* Bitstream creation time */
+   u32 magic_length;   /* Length of the magic numbers */
+   const unchar *version;  /* Version string */
+};
+
+/* caller must free the allocated memory for **data. len could be NULL. */
+int xrt_xclbin_get_section(struct device *dev,  const struct axlf *xclbin,
+  enum axlf_section_kind kind, void **data,
+  uint64_t *len);
+int xrt_xclbin_get_metadata(struct device *dev, const struct axlf *xclbin, 
char **dtb);
+int xrt_xclbin_parse_bitstream_header(struct device *dev, const unchar *data,
+ u32 size, struct xclbin_bit_head_info 
*head_info);
+const char *xrt_clock_type2epname(enum XCLBIN_CLOCK_TYPE type);
+
+#endif /* _XCLBIN_HELPER_H_ */
diff --git a/drivers/fpga/xrt/lib/xclbin.c b/drivers/fpga/xrt/lib/xclbin.c
new file mode 100644
index ..31b363c014a3
--- /dev/null
+++ b/drivers/fpga/xrt/lib/xclbin.c
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA Driver XCLBIN parser
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors: David Zhang 
+ */
+
+#include 
+#include 
+#include 
+#include "xclbin-helper.h"
+#include "metadata.h"
+
+/* Used for parsing bitstream header */
+#define BITSTREAM_EVEN_MAGIC_BYTE  0x0f
+#define BITSTREAM_ODD_MAGIC_BYTE   0xf0
+
+static int xrt_xclbin_get_section_hdr(const struct axlf *xclbin,
+ enum axlf_section_kind kind,
+ const struct axlf_section_header **header)
+{
+   const struct axlf_section_header *phead = NULL;
+   u64 xclbin_len;
+   int i;
+
+   *header = NULL;
+   for (i = 0; i < xclbin->header.num_sections; i++) {
+   if (xclbin->sections[i].section_kind == kind) {
+   phead = &xclbin->sections[i];
+   break;
+   }
+   }
+
+   if (!phead)
+   return -ENOENT;
+
+   xclbin_len = xclbin->header.length;
+   if (xclbin_len > XCLBIN_MAX_SIZE ||
+   phead->section_offset + phead->section_size > xclbin_len)
+   return -EINVAL;
+
+   *header = phead;
+   return 0;
+}
+
+static int xrt_xclbin_section_info(const struct axlf *xclbin,
+  enum axlf_section_kind kind,
+  u64 *offset, u64 *size)
+{
+   const struct axlf_section_header *mem_header = NULL;
+   int rc;
+
+   rc = xrt_xclbin_get_section_hdr(xclbin, kind, &mem_header);
+   if (rc)
+   return rc;
+
+   *offset = mem_header->section_offset;
+   *size = mem_header->section_size;
+
+   return 0;
+}
+
+/* caller must free the allocated memory for **data */
+int xrt_xclbin_get_section(struct device *dev,
+  const struct axlf *buf,
+  enum axlf_section_kind kind,
+  void **data, u64 *len)
+{
+   const struct axlf *xc

[PATCH V4 XRT Alveo 01/20] Documentation: fpga: Add a document describing XRT Alveo drivers

Describe XRT driver architecture and provide basic overview of
Xilinx Alveo platform.

Signed-off-by: Sonal Santan 
Signed-off-by: Max Zhen 
Signed-off-by: Lizhi Hou 
---
 Documentation/fpga/index.rst |   1 +
 Documentation/fpga/xrt.rst   | 844 +++
 2 files changed, 845 insertions(+)
 create mode 100644 Documentation/fpga/xrt.rst

diff --git a/Documentation/fpga/index.rst b/Documentation/fpga/index.rst
index f80f95667ca2..30134357b70d 100644
--- a/Documentation/fpga/index.rst
+++ b/Documentation/fpga/index.rst
@@ -8,6 +8,7 @@ fpga
 :maxdepth: 1
 
 dfl
+xrt
 
 .. only::  subproject and html
 
diff --git a/Documentation/fpga/xrt.rst b/Documentation/fpga/xrt.rst
new file mode 100644
index ..0f7977464270
--- /dev/null
+++ b/Documentation/fpga/xrt.rst
@@ -0,0 +1,844 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+==
+XRTV2 Linux Kernel Driver Overview
+==
+
+Authors:
+
+* Sonal Santan 
+* Max Zhen 
+* Lizhi Hou 
+
+XRTV2 drivers are second generation `XRT `_
+drivers which support `Alveo 
`_
+PCIe platforms from Xilinx.
+
+XRTV2 drivers support *subsystem* style data driven platforms where driver's
+configuration and behavior is determined by meta data provided by the platform
+(in *device tree* format). Primary management physical function (MPF) driver
+is called **xmgmt**. Primary user physical function (UPF) driver is called
+**xuser** and is under development. xrt driver framework and HW subsystem
+drivers are packaged into a library module called **xrt-lib**, which is
+shared by **xmgmt** and **xuser** (under development). The xrt driver framework
+implements a pseudo-bus which is used to discover HW subsystems and facilitate
+inter HW subsystem interaction.
+
+Driver Modules
+==
+
+xrt-lib.ko
+--
+
+Repository of all subsystem drivers and pure software modules that can 
potentially
+be shared between xmgmt and xuser. All these drivers are structured as Linux
+*platform driver* and are instantiated by xmgmt (or xuser under development) 
based
+on meta data associated with the hardware. The metadata is in the form of a 
device
+tree as mentioned before. Each platform driver statically defines a subsystem 
node
+array by using node name or a string in its ``compatible`` property. And this
+array is eventually translated to IOMEM resources of the platform device.
+
+The xrt-lib core infrastructure provides hooks to platform drivers for device 
node
+management, user file operations and ioctl callbacks. The core infrastructure 
also
+provides pseudo-bus functionality for platform driver registration, discovery 
and
+inter platform driver ioctl calls.
+
+.. note::
+   See code in ``include/xleaf.h``
+
+
+xmgmt.ko
+
+
+The xmgmt driver is a PCIe device driver driving MPF found on Xilinx's Alveo
+PCIE device. It consists of one *root* driver, one or more *group* drivers
+and one or more *xleaf* drivers. The root and MPF specific xleaf drivers are
+in xmgmt.ko. The group driver and other xleaf drivers are in xrt-lib.ko.
+
+The instantiation of specific group driver or xleaf driver is completely data
+driven based on meta data (mostly in device tree format) found through VSEC
+capability and inside firmware files, such as platform xsabin or user xclbin 
file.
+The root driver manages the life cycle of multiple group drivers, which, in 
turn,
+manages multiple xleaf drivers. This allows a single set of drivers to support
+all kinds of subsystems exposed by different shells. The difference among all
+these subsystems will be handled in xleaf drivers with root and group drivers
+being part of the infrastructure and provide common services for all leaves
+found on all platforms.
+
+The driver object model looks like the following::
+
++---+
+|   xroot   |
++-+-+
+  |
+  +---+---+
+  |   |
+  v   v
++---+  +---+
+|   group   |...   |   group   |
++-+-+  +--++
+  |   |
+  |   |
++-+++-++
+|  ||  |
+v  vv  v
++---+  +---++---+  +---+
+| xleaf |..| xleaf || xleaf |..| xleaf |
++---+  +---++---+  +---+
+
+As an example for Xilinx Alveo U50 before user xclbin download, the tree
+looks like the following::
+
++---+
+|   xmgmt   |
++-+-+
+  |
++-

[PATCH V4 XRT Alveo 00/20] XRT Alveo driver overview