Re: [PATCH v2] drm/connector: Add of_drm_find_connector
ping
On 7/3/20 5:45 PM, Andy Yan wrote:
Add a function to look up a connector by
device tree node, like what of_drm_find_bridge/panel
does.
Signed-off-by: Andy Yan
Reported-by: kernel test robot
---
Changes in v2:
- Add function declaration
drivers/gpu/drm/drm_connector.c | 33 +
include/drm/drm_connector.h | 14 ++
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index d877ddc6dc57..516376cd1868 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -743,6 +743,39 @@ void drm_connector_list_iter_end(struct
drm_connector_list_iter *iter)
}
EXPORT_SYMBOL(drm_connector_list_iter_end);
+#ifdef CONFIG_OF
+/**
+ * of_drm_find_connector - look up a connector using a device tree node
+ * @np: device tree node of the connector
+ *
+ *
+ * Return: A pointer to the connector which match the specified device tree
+ * node or NULL if no panel matching the device tree node can be found, or
+ * -ENODEV: the device is not available (status != "okay" or "ok")
+ */
+struct drm_connector *of_drm_find_connector(struct drm_device *dev, const
struct device_node *np)
+{
+ struct drm_connector *connector;
+ struct drm_connector_list_iter conn_iter;
+
+ if (!of_device_is_available(np))
+ return ERR_PTR(-ENODEV);
+
+ drm_connector_list_iter_begin(dev, _iter);
+ drm_for_each_connector_iter(connector, _iter) {
+ if (connector->of_node == np) {
+ drm_connector_list_iter_end(_iter);
+ return connector;
+ }
+ }
+ drm_connector_list_iter_end(_iter);
+
+ return NULL;
+}
+EXPORT_SYMBOL(of_drm_find_connector);
+#endif
+
+
static const struct drm_prop_enum_list drm_subpixel_enum_list[] = {
{ SubPixelUnknown, "Unknown" },
{ SubPixelHorizontalRGB, "Horizontal RGB" },
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index fd543d1db9b2..d249e0498375 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -1129,6 +1129,9 @@ struct drm_connector {
/** @attr: sysfs attributes */
struct device_attribute *attr;
+ /** @of_node: device tree node */
+ struct device_node *of_node;
+
/**
* @head:
*
@@ -1647,6 +1650,17 @@ void drm_connector_list_iter_end(struct
drm_connector_list_iter *iter);
bool drm_connector_has_possible_encoder(struct drm_connector *connector,
struct drm_encoder *encoder);
+#if defined(CONFIG_OF)
+struct drm_connector *
+of_drm_find_connector(struct drm_device *dev, const struct device_node *np);
+#else
+static inline struct drm_connector *
+of_drm_find_connector(struct drm_device *dev, const struct device_node *np)
+{
+ return ERR_PTR(-ENODEV);
+}
+#endif
+
/**
* drm_for_each_connector_iter - connector_list iterator macro
* @connector: drm_connector pointer used as cursor
Re: [PATCH 2/5] drm: rockchip: add missing registers for RK3188【请注意，邮件由linux-rockchip-bounces+andy.yan=rock-chips....@lists.infradead.org代发】
Hi Alex:
On 7/20/20 10:46 PM, Alex Bee wrote:
Hi Andy,
Am 20.07.20 um 10:22 schrieb Andy Yan:
Hi Alex:
On 7/19/20 4:03 AM, Alex Bee wrote:
This patch adds dither_up, dsp_lut_en, data_blank and dsp_data_swap
registers to enable their respective functionality for RK3188's VOP.
Signed-off-by: Alex Bee
---
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index b046910129fb..971a6bda7458 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -512,6 +512,10 @@ static const struct vop_common rk3188_common = {
.dither_down_en = VOP_REG(RK3188_DSP_CTRL0, 0x1, 11),
.dither_down_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 10),
.dsp_blank = VOP_REG(RK3188_DSP_CTRL1, 0x3, 24),
+ .dither_up = VOP_REG(RK3188_DSP_CTRL0, 0x1, 9),
+ .dsp_lut_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 28),
+ .data_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 25),
+ .dsp_data_swap = VOP_REG(RK3188_DSP_CTRL1, 0x1f, 26),
I can't find the definition of dsp_data_swap, or I missed something?
Note that .dsp_data_swap is not defined with that name in TRM (as it
is not in RK3288/RK3328), since potentially more the one bit would
have to be set for this (currently only RB_SWAP (0x2) is implemented
in the VOP driver).
I mean I didn't find the definition of dsp_data_swap in struct
vop_comm, I even search drm-misc-next tree.
To be some kind of future proof (if BG_SWAP, RG_SWAP, DELTA_SWAP or
DUMMY_SWAP ever get implemented) it should be aligned with what is
defined for RK3288/RK3328 now to automatically benefit from that
additions. And it would, since RK3288_DSP_CTRL0 BIT12, BIT13, BIT14,
BIT15, BIT16 exactly matches with RK3188_DSP_CTRL1 BIT26, BIT27,
BIT28, BIT29, BIT30.
Current implementation sets BIT13 for RK3288 and with this patch BIT27
for RK3188 to enable RB_SWAP.
};
static const struct vop_win_data rk3188_vop_win_data[] = {
Regards,
Alex
Re: [PATCH 2/5] drm: rockchip: add missing registers for RK3188【请注意，邮件由linux-rockchip-bounces+andy.yan=rock-chips....@lists.infradead.org代发】
Hi Alex:
On 7/19/20 4:03 AM, Alex Bee wrote:
This patch adds dither_up, dsp_lut_en, data_blank and dsp_data_swap
registers to enable their respective functionality for RK3188's VOP.
Signed-off-by: Alex Bee
---
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index b046910129fb..971a6bda7458 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -512,6 +512,10 @@ static const struct vop_common rk3188_common = {
.dither_down_en = VOP_REG(RK3188_DSP_CTRL0, 0x1, 11),
.dither_down_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 10),
.dsp_blank = VOP_REG(RK3188_DSP_CTRL1, 0x3, 24),
+ .dither_up = VOP_REG(RK3188_DSP_CTRL0, 0x1, 9),
+ .dsp_lut_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 28),
+ .data_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 25),
+ .dsp_data_swap = VOP_REG(RK3188_DSP_CTRL1, 0x1f, 26),
I can't find the definition of dsp_data_swap, or I missed something?
};
static const struct vop_win_data rk3188_vop_win_data[] = {
[PATCH v2] drm/connector: Add of_drm_find_connector
Add a function to look up a connector by
device tree node, like what of_drm_find_bridge/panel
does.
Signed-off-by: Andy Yan
Reported-by: kernel test robot
---
Changes in v2:
- Add function declaration
drivers/gpu/drm/drm_connector.c | 33 +
include/drm/drm_connector.h | 14 ++
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index d877ddc6dc57..516376cd1868 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -743,6 +743,39 @@ void drm_connector_list_iter_end(struct
drm_connector_list_iter *iter)
}
EXPORT_SYMBOL(drm_connector_list_iter_end);
+#ifdef CONFIG_OF
+/**
+ * of_drm_find_connector - look up a connector using a device tree node
+ * @np: device tree node of the connector
+ *
+ *
+ * Return: A pointer to the connector which match the specified device tree
+ * node or NULL if no panel matching the device tree node can be found, or
+ * -ENODEV: the device is not available (status != "okay" or "ok")
+ */
+struct drm_connector *of_drm_find_connector(struct drm_device *dev, const
struct device_node *np)
+{
+ struct drm_connector *connector;
+ struct drm_connector_list_iter conn_iter;
+
+ if (!of_device_is_available(np))
+ return ERR_PTR(-ENODEV);
+
+ drm_connector_list_iter_begin(dev, _iter);
+ drm_for_each_connector_iter(connector, _iter) {
+ if (connector->of_node == np) {
+ drm_connector_list_iter_end(_iter);
+ return connector;
+ }
+ }
+ drm_connector_list_iter_end(_iter);
+
+ return NULL;
+}
+EXPORT_SYMBOL(of_drm_find_connector);
+#endif
+
+
static const struct drm_prop_enum_list drm_subpixel_enum_list[] = {
{ SubPixelUnknown, "Unknown" },
{ SubPixelHorizontalRGB, "Horizontal RGB" },
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index fd543d1db9b2..d249e0498375 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -1129,6 +1129,9 @@ struct drm_connector {
/** @attr: sysfs attributes */
struct device_attribute *attr;
+ /** @of_node: device tree node */
+ struct device_node *of_node;
+
/**
* @head:
*
@@ -1647,6 +1650,17 @@ void drm_connector_list_iter_end(struct
drm_connector_list_iter *iter);
bool drm_connector_has_possible_encoder(struct drm_connector *connector,
struct drm_encoder *encoder);
+#if defined(CONFIG_OF)
+struct drm_connector *
+of_drm_find_connector(struct drm_device *dev, const struct device_node *np);
+#else
+static inline struct drm_connector *
+of_drm_find_connector(struct drm_device *dev, const struct device_node *np)
+{
+ return ERR_PTR(-ENODEV);
+}
+#endif
+
/**
* drm_for_each_connector_iter - connector_list iterator macro
* @connector: drm_connector pointer used as cursor
--
2.17.1
Re: [PATCH 1/2] arm64: dts: rockchip: Add core dts for RK3308 SOC
Hi Heiko:
Thanks for your kindly review.
On 10/18/19 7:30 AM, Heiko Stuebner wrote:
Hi Andy,
Am Donnerstag, 17. Oktober 2019, 05:04:49 CEST schrieb Andy Yan:
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
Please also provide a ATF implementation for the rk3308 :-)
[Not a requirement for getting this merged, but it would be
really cool to have sources for the full stack]
Tony's team has the plan to do it.
+
+ ramoops_mem: ramoops_mem {
+ reg = <0x0 0x11 0x0 0xf>;
+ reg-names = "ramoops_mem";
+ };
+
+ ramoops: ramoops {
+ compatible = "ramoops";
+ record-size = <0x0 0x3>;
+ console-size = <0x0 0xc>;
+ ftrace-size = <0x0 0x0>;
+ pmsg-size = <0x0 0x0>;
+ memory-region = <_mem>;
+ };
I think ramoops are more a per-board thing, like for the evb.
As they'll require cooperation with bootloaders to not mangle that
memory area. For this please also coordinate with Kever because
I somehow remember we have u-boot sometimes at 0x10.
I removed it in V2.
+ grf: grf@ff00 {
+ compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
Please add a patch adding the rockchip,rk3308-grf compatible to
Documentation/devicetree/bindings/soc/rockchip/grf.txt
Done
+ reg = <0x0 0xff00 0x0 0x1>;
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x500>;
+ mode-bootloader = ;
+ mode-loader = ;
+ mode-normal = ;
+ mode-recovery = ;
+ mode-fastboot = ;
+ };
+ };
+
+ detect_grf: syscon@ff00b000 {
+ compatible = "syscon", "simple-mfd";
compatible = "rockchip,rk3308-detect-grf", "syscon"
+ add the rk3308-detect-grf to the binding
Done
+ reg = <0x0 0xff00b000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ core_grf: syscon@ff00c000 {
+ compatible = "syscon", "simple-mfd";
same as detect_grf
Done
+ reg = <0x0 0xff00c000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ };
+
+ i2c0: i2c@ff04 {
+ compatible = "rockchip,rk3399-i2c";
compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
Same for all i2c controllers.
Done
+ reg = <0x0 0xff04 0x0 0x1000>;
+ clocks = < SCLK_I2C0>, < PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ interrupts = ;
+ pinctrl-names = "default";
+ pinctrl-0 = <_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ spi0: spi@ff12 {
+ compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xff12 0x0 0x1000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_SPI0>, < PCLK_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = < 0>, < 1>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "high_speed";
there is no high_speed pinctrl defined for the Rockchip spi driver
in mainline, so this part should go away in a first step.
Same for the other spi controllers.
Removed
+ pinctrl-0 = <_clk _csn0 _miso _mosi>;
+ pinctrl-1 = <_clk_hs _csn0 _miso_hs
_mosi_hs>;
+ status = "disabled";
+ };
+ rktimer: rktimer@ff1a {
+ compatible = "rockchip,rk3288-timer";
compatible = "rockchip,rk3308-timer", "rockchip,rk3288-timer";
Done
+ reg = <0x0 0xff1a 0x0 0x20>;
+ interrupts = ;
+ clocks = < PCLK_TIMER>, < SCLK_TIMER0>;
+ clock-names = "pclk", "timer";
+ };
+ amba {
+ compatible = "arm,amba-bus";
compatible = "simple-bus";
Done
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+
[PATCH v2 2/4] arm64: dts: rockchip: Add core dts for RK3308 SOC
RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.
This patch add basic core dtsi file for it.
Signed-off-by: Andy Yan
---
Changes in v2:
- Address Heiko's comments in V1
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1838 ++
1 file changed, 1838 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3308.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
new file mode 100644
index ..c38acc7dd275
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -0,0 +1,1838 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "rockchip,rk3308";
+
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ serial4 =
+ spi0 =
+ spi1 =
+ spi2 =
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ clocks = < ARMCLK>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <90>;
+ operating-points-v2 = <_opp_table>;
+ cpu-idle-states = <_SLEEP>;
+ next-level-cache = <>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ operating-points-v2 = <_opp_table>;
+ cpu-idle-states = <_SLEEP>;
+ next-level-cache = <>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ operating-points-v2 = <_opp_table>;
+ cpu-idle-states = <_SLEEP>;
+ next-level-cache = <>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ operating-points-v2 = <_opp_table>;
+ cpu-idle-states = <_SLEEP>;
+ next-level-cache = <>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x001>;
+ entry-latency-us = <120>;
+ exit-latency-us = <250>;
+ min-residency-us = <900>;
+ };
+ };
+
+ l2: l2-cache {
+ compatible = "cache";
+ };
+ };
+
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-40800 {
+ opp-hz = /bits/ 64 <40800>;
+ opp-microvolt = <95 95 134>;
+ clock-latency-ns = <4>;
+ opp-suspend;
+ };
+ opp-6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <95 95 134>;
+ clock-latency-ns = <4>;
+ };
+ opp-81600 {
+ opp-hz =
[PATCH v2 0/4] Add basic dts support for RK3308
RK3308 is a quad Cortex A35 based SOC with rich audio interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which designed for intelligent voice interaction and audio input/output processing. As the clk and pinctrl drivers are landed, we post the basic dts support, make it convenient for other module development. Changes in v2: - Address Heiko's comments in V1 - Split with the dts file - Split binding to a separate patch - Power tree update. Andy Yan (4): dt-bindings: Add doc about rk3308 General Register Files arm64: dts: rockchip: Add core dts for RK3308 SOC dt-bindings: Add doc for rk3308-evb arm64: dts: rockchip: Add basic dts for RK3308 EVB .../devicetree/bindings/arm/rockchip.yaml |5 + .../devicetree/bindings/soc/rockchip/grf.txt | 11 + arch/arm64/boot/dts/rockchip/Makefile |1 + arch/arm64/boot/dts/rockchip/rk3308-evb.dts | 230 +++ arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1838 + 5 files changed, 2085 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3308-evb.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3308.dtsi -- 2.17.1
[PATCH v2 4/4] arm64: dts: rockchip: Add basic dts for RK3308 EVB
This board use uart4 as debug port and arm core voltage
is modulated by pwm, logic voltage is fixed to 1.05V.
Signed-off-by: Andy Yan
---
Changes in v2:
- Split binding to a separate patch
- Power tree update.
arch/arm64/boot/dts/rockchip/Makefile | 1 +
arch/arm64/boot/dts/rockchip/rk3308-evb.dts | 230
2 files changed, 231 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3308-evb.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile
b/arch/arm64/boot/dts/rockchip/Makefile
index 1f18a9392d15..a959434ad46e 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb.dts
b/arch/arm64/boot/dts/rockchip/rk3308-evb.dts
new file mode 100644
index ..124a24086684
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3308-evb.dts
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ */
+
+/dts-v1/;
+#include
+#include "rk3308.dtsi"
+
+/ {
+ model = "Rockchip RK3308 EVB";
+ compatible = "rockchip,rk3308-evb", "rockchip,rk3308";
+
+ chosen {
+ stdout-path = "serial4:150n8";
+ };
+
+ adc-keys0 {
+ compatible = "adc-keys";
+ io-channels = < 0>;
+ io-channel-names = "buttons";
+ poll-interval = <100>;
+ keyup-threshold-microvolt = <180>;
+
+ func-key {
+ linux,code = ;
+ label = "function";
+ press-threshold-microvolt = <18000>;
+ };
+ };
+
+ adc-keys1 {
+ compatible = "adc-keys";
+ io-channels = < 1>;
+ io-channel-names = "buttons";
+ poll-interval = <100>;
+ keyup-threshold-microvolt = <180>;
+
+ esc-key {
+ linux,code = ;
+ label = "micmute";
+ press-threshold-microvolt = <113>;
+ };
+
+ home-key {
+ linux,code = ;
+ label = "mode";
+ press-threshold-microvolt = <901000>;
+ };
+
+ menu-key {
+ linux,code = ;
+ label = "play";
+ press-threshold-microvolt = <624000>;
+ };
+
+ vol-down-key {
+ linux,code = ;
+ label = "volume down";
+ press-threshold-microvolt = <30>;
+ };
+
+ vol-up-key {
+ linux,code = ;
+ label = "volume up";
+ press-threshold-microvolt = <18000>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_key>;
+
+ power {
+ gpios = < RK_PA6 GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ label = "GPIO Key Power";
+ wakeup-source;
+ debounce-interval = <100>;
+ };
+ };
+
+ vcc12v_dcin: vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_dcin>;
+ };
+
+ vdd_core: vdd-core {
+ compatible = "pwm-regulator";
+ pwms = < 0 5000 1>;
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <827000>;
+ regulator-max-microvolt = &l
[PATCH v2 3/4] dt-bindings: Add doc for rk3308-evb
Add compatible for RK3308 Evaluation board Signed-off-by: Andy Yan --- Changes in v2: - Split with the dts file Documentation/devicetree/bindings/arm/rockchip.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index c82c5e57d44c..b680c4b8b2c9 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -447,6 +447,11 @@ properties: - const: rockchip,r88 - const: rockchip,rk3368 + - description: Rockchip RK3308 Evaluation board +items: + - const: rockchip,rk3308-evb + - const: rockchip,rk3308 + - description: Rockchip RK3228 Evaluation board items: - const: rockchip,rk3228-evb -- 2.17.1
[PATCH v2 1/4] dt-bindings: Add doc about rk3308 General Register Files
RK3308 GRF is divided into four sections: GRF, SGRF, DETECTGRF, COREGRF. This patch add documentation for it. Signed-off-by: Andy Yan --- Changes in v2: None .../devicetree/bindings/soc/rockchip/grf.txt | 11 +++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt index d7debec26ba4..61d89749918a 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt @@ -10,6 +10,12 @@ From RK3368 SoCs, the GRF is divided into two sections, On RK3328 SoCs, the GRF adds a section for USB2PHYGRF, +ON RK3308 SoC, the GRF is divided into four sections: +- GRF, used for general non-secure system, +- SGRF, used for general secure system, +- DETECTGRF, used for audio codec system, +- COREGRF, used for pvtm, + Required Properties: - compatible: GRF should be one of the following: @@ -19,10 +25,15 @@ Required Properties: - "rockchip,rk3188-grf", "syscon": for rk3188 - "rockchip,rk3228-grf", "syscon": for rk3228 - "rockchip,rk3288-grf", "syscon": for rk3288 + - "rockchip,rk3308-grf", "syscon": for rk3308 - "rockchip,rk3328-grf", "syscon": for rk3328 - "rockchip,rk3368-grf", "syscon": for rk3368 - "rockchip,rk3399-grf", "syscon": for rk3399 - "rockchip,rv1108-grf", "syscon": for rv1108 +- compatible: DETECTGRF should be one of the following: + - "rockchip,rk3308-detect-grf", "syscon": for rk3308 +- compatilbe: COREGRF should be one of the following: + - "rockchip,rk3308-core-grf", "syscon": for rk3308 - compatible: PMUGRF should be one of the following: - "rockchip,px30-pmugrf", "syscon": for px30 - "rockchip,rk3368-pmugrf", "syscon": for rk3368 -- 2.17.1
[PATCH 0/2] Add basic dts support for RK3308
RK3308 is a quad Cortex A35 based SOC with rich audio interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which designed for intelligent voice interaction and audio input/output processing. As the clk and pinctrl drivers are landed, we post the basic dts support, make it convenient for other module development. Andy Yan (2): arm64: dts: rockchip: Add core dts for RK3308 SOC arm64: dts: rockchip: Add basic dts for RK3308 EVB .../devicetree/bindings/arm/rockchip.yaml |5 + arch/arm64/boot/dts/rockchip/Makefile |1 + arch/arm64/boot/dts/rockchip/rk3308-evb.dts | 206 ++ arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1875 + 4 files changed, 2087 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3308-evb.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3308.dtsi -- 2.17.1
[PATCH 2/2] arm64: dts: rockchip: Add basic dts for RK3308 EVB
This board use uart4 as debug port and arm core voltage
is modulated by pwm.
Signed-off-by: Andy Yan
---
.../devicetree/bindings/arm/rockchip.yaml | 5 +
arch/arm64/boot/dts/rockchip/Makefile | 1 +
arch/arm64/boot/dts/rockchip/rk3308-evb.dts | 206 ++
3 files changed, 212 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3308-evb.dts
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml
b/Documentation/devicetree/bindings/arm/rockchip.yaml
index c82c5e57d44c..b680c4b8b2c9 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -447,6 +447,11 @@ properties:
- const: rockchip,r88
- const: rockchip,rk3368
+ - description: Rockchip RK3308 Evaluation board
+items:
+ - const: rockchip,rk3308-evb
+ - const: rockchip,rk3308
+
- description: Rockchip RK3228 Evaluation board
items:
- const: rockchip,rk3228-evb
diff --git a/arch/arm64/boot/dts/rockchip/Makefile
b/arch/arm64/boot/dts/rockchip/Makefile
index 1f18a9392d15..a959434ad46e 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3308-evb.dts
b/arch/arm64/boot/dts/rockchip/rk3308-evb.dts
new file mode 100644
index ..16be04f38b30
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3308-evb.dts
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ */
+
+/dts-v1/;
+#include
+#include "rk3308.dtsi"
+
+/ {
+ model = "Rockchip RK3308 EVB";
+ compatible = "rockchip,rk3308-evb", "rockchip,rk3308";
+
+ chosen {
+ stdout-path = "serial4:150n8";
+ };
+
+ adc-keys0 {
+ compatible = "adc-keys";
+ io-channels = < 0>;
+ io-channel-names = "buttons";
+ poll-interval = <100>;
+ keyup-threshold-microvolt = <180>;
+
+ func-key {
+ linux,code = ;
+ label = "function";
+ press-threshold-microvolt = <18000>;
+ };
+ };
+
+ adc-keys1 {
+ compatible = "adc-keys";
+ io-channels = < 1>;
+ io-channel-names = "buttons";
+ poll-interval = <100>;
+ keyup-threshold-microvolt = <180>;
+
+ esc-key {
+ linux,code = ;
+ label = "micmute";
+ press-threshold-microvolt = <113>;
+ };
+
+ home-key {
+ linux,code = ;
+ label = "mode";
+ press-threshold-microvolt = <901000>;
+ };
+
+ menu-key {
+ linux,code = ;
+ label = "play";
+ press-threshold-microvolt = <624000>;
+ };
+
+ vol-down-key {
+ linux,code = ;
+ label = "volume down";
+ press-threshold-microvolt = <30>;
+ };
+
+ vol-up-key {
+ linux,code = ;
+ label = "volume up";
+ press-threshold-microvolt = <18000>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_key>;
+
+ power {
+ gpios = < RK_PA6 GPIO_ACTIVE_LOW>;
+ linux,code = ;
+ label = "GPIO Key Power";
+ wakeup-source;
+ debounce-interval = <100>;
+ };
+ };
+
+ vdd_log: vdd_core: vdd-core {
+ compatible = "pwm-regulator";
+ pwms = < 0 5000 1>;
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <827000>;
+ regulator-max-microvolt = <134>;
+ regulator-init-microvolt = <1015000>;
+ regulator-early-min-microvolt = <1015000>;
+
[PATCH 1/2] arm64: dts: rockchip: Add core dts for RK3308 SOC
RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.
This patch add basic core dtsi file for it.
Signed-off-by: Andy Yan
---
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1875 ++
1 file changed, 1875 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3308.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
new file mode 100644
index ..cda63ffb0d2f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -0,0 +1,1875 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "rockchip,rk3308";
+
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 =
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ serial4 =
+ spi0 =
+ spi1 =
+ spi2 =
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ clocks = < ARMCLK>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <90>;
+ operating-points-v2 = <_opp_table>;
+ cpu-idle-states = <_SLEEP>;
+ next-level-cache = <>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ operating-points-v2 = <_opp_table>;
+ cpu-idle-states = <_SLEEP>;
+ next-level-cache = <>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ operating-points-v2 = <_opp_table>;
+ cpu-idle-states = <_SLEEP>;
+ next-level-cache = <>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ operating-points-v2 = <_opp_table>;
+ cpu-idle-states = <_SLEEP>;
+ next-level-cache = <>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x001>;
+ entry-latency-us = <120>;
+ exit-latency-us = <250>;
+ min-residency-us = <900>;
+ };
+ };
+
+ l2: l2-cache {
+ compatible = "cache";
+ };
+ };
+
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-40800 {
+ opp-hz = /bits/ 64 <40800>;
+ opp-microvolt = <95 95 134>;
+ clock-latency-ns = <4>;
+ opp-suspend;
+ };
+ opp-6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <95 95 134>;
+ clock-latency-ns = <4>;
+ };
+ opp-81600 {
+ opp-hz = /bi
[PATCH v2] arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC
P710 is a RK3399 based SBC, designed by Leez [0].
Specification
- Rockchip RK3399
- 4/2GB LPDDR4
- TF sd scard slot
- eMMC
- M.2 B-Key for 4G LTE
- AP6256 for WiFi + BT
- Gigabit ethernet
- HDMI out
- 40 pin header
- USB 2.0 x 2
- USB 3.0 x 1
- USB 3.0 Type-C x 1
- TYPE-C Power supply
[0]https://leez.lenovo.com
Signed-off-by: Andy Yan
---
Changes in v2:
- Add vendor entry for Leez
- Rework the regulator tree
- Fix some pinctrl names
.../devicetree/bindings/arm/rockchip.yaml | 5 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3399-leez-p710.dts| 645 ++
4 files changed, 653 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml
b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 34865042f4e4..da9cd947abfa 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -329,6 +329,11 @@ properties:
- khadas,edge-v
- const: rockchip,rk3399
+ - description: Leez RK3399 P710
+items:
+ - const: leez,p710
+ - const: rockchip,rk3399
+
- description: mqmaker MiQi
items:
- const: mqmaker,miqi
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 6992ffab..4be4d9c367b9 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -503,6 +503,8 @@ patternProperties:
description: Lantiq Semiconductor
"^lattice,.*":
description: Lattice Semiconductor
+ "^leez,.*":
+description: Leez
"^lego,.*":
description: LEGO Systems A/S
"^lemaker,.*":
diff --git a/arch/arm64/boot/dts/rockchip/Makefile
b/arch/arm64/boot/dts/rockchip/Makefile
index daa2c78e22c3..1f18a9392d15 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -20,6 +20,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
new file mode 100644
index ..32baa57b9481
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
@@ -0,0 +1,645 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Andy Yan
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Leez RK3399 P710";
+ compatible = "leez,p710", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = < 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_on_h>;
+ reset-gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ dc5v_adp: dc5v-adp {
+ compatible = "regulator-fixed";
+ regulator-name = "dc5v_adapter";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_adp>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt
[PATCH] arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC
Leez P710 is a RK3399 based SBC, designed by Leez team
from lenovo [0].
Specification
- Rockchip RK3399
- 4/2GB LPDDR4
- TF sd scard slot
- eMMC
- M.2 B-Key for 4G LTE
- AP6256 for WiFi + BT
- Gigabit ethernet
- HDMI out
- 40 pin header
- TYPE-C Power supply
[0] https://leez.lenovo.com
Signed-off-by: Andy Yan
---
.../devicetree/bindings/arm/rockchip.yaml | 5 +
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3399-leez-p710.dts| 635 ++
3 files changed, 641 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml
b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 34865042f4e4..da9cd947abfa 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -329,6 +329,11 @@ properties:
- khadas,edge-v
- const: rockchip,rk3399
+ - description: Leez RK3399 P710
+items:
+ - const: leez,p710
+ - const: rockchip,rk3399
+
- description: mqmaker MiQi
items:
- const: mqmaker,miqi
diff --git a/arch/arm64/boot/dts/rockchip/Makefile
b/arch/arm64/boot/dts/rockchip/Makefile
index daa2c78e22c3..1f18a9392d15 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -20,6 +20,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
new file mode 100644
index ..b342f5e8692b
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
@@ -0,0 +1,635 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Andy Yan
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Leez RK3399 P710";
+ compatible = "leez,p710", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = < 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <_enable_h>;
+ reset-gpios = < RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ dc5v_adp: dc-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc5v_adapter";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+
+ vcc5v0_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_adp>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <_sys>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = < RK_PA2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ vin-supply = <_sys>;
+ };
+
+ vcc_lan: vcc3v3-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_lan";
+ regulator-always-on;
+ regulator-boot-on;
+ reg
[PATCH v8 3/3] ARM: dts: rockchip: enable sfc for rv1108 evb
Enable the sfc support for rv1108 evaluation board.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 10 ++
arch/arm/boot/dts/rv1108.dtsi| 13 +
2 files changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index ac27e11..5d0ebe3 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -239,6 +239,16 @@
};
};
+ {
+ status = "okay";
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <1>;
+ m25p,fast-read;
+ reg = <0>;
+ };
+};
+
{
status = "okay";
};
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 76ea246..30435fc 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -554,6 +554,19 @@
status = "disabled";
};
+ sfc: sfc@301c {
+ compatible = "rockchip,rv1108-sfc", "rockchip,sfc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_SFC>, < HCLK_SFC>;
+ clock-names = "sfc", "hsfc";
+ interrupts = ;
+ reg = <0x301c 0x1000>;
+ /* If you want to use PIO mode, activate this */
+ /*rockchip,sfc-no-dma;*/
+ status = "disabled";
+ };
+
gic: interrupt-controller@3201 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.7.4
[PATCH v8 3/3] ARM: dts: rockchip: enable sfc for rv1108 evb
Enable the sfc support for rv1108 evaluation board.
Signed-off-by: Andy Yan
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 10 ++
arch/arm/boot/dts/rv1108.dtsi| 13 +
2 files changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index ac27e11..5d0ebe3 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -239,6 +239,16 @@
};
};
+ {
+ status = "okay";
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <1>;
+ m25p,fast-read;
+ reg = <0>;
+ };
+};
+
{
status = "okay";
};
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 76ea246..30435fc 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -554,6 +554,19 @@
status = "disabled";
};
+ sfc: sfc@301c {
+ compatible = "rockchip,rv1108-sfc", "rockchip,sfc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_SFC>, < HCLK_SFC>;
+ clock-names = "sfc", "hsfc";
+ interrupts = ;
+ reg = <0x301c 0x1000>;
+ /* If you want to use PIO mode, activate this */
+ /*rockchip,sfc-no-dma;*/
+ status = "disabled";
+ };
+
gic: interrupt-controller@3201 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.7.4
[PATCH v8 1/3] mtd: spi-nor: Bindings for Rockchip serial flash controller
From: Shawn Lin <shawn@rock-chips.com>
Add binding document for the Rockchip serial flash controller.
Signed-off-by: Shawn Lin <shawn@rock-chips.com>
Acked-by: Marek Vasut <marek.va...@gmail.com>
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/mtd/rockchip-sfc.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/rockchip-sfc.txt
diff --git a/Documentation/devicetree/bindings/mtd/rockchip-sfc.txt
b/Documentation/devicetree/bindings/mtd/rockchip-sfc.txt
new file mode 100644
index 000..1e449b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/rockchip-sfc.txt
@@ -0,0 +1,31 @@
+Rockchip Serial Flash Controller
+
+Required properties:
+- compatible : Should be
+ "rockchip,rv1108-sfc", "rockchip,sfc" for ROCKCHIP RV1108.
+- address-cells : Should be 1.
+- size-cells : Should be 0.
+- clocks: Must contain two entries for each entry in clock-names.
+- clock-names: Shall be "sfc" for the transfer-clock, and "hsfc" for
+ the peripheral clock.
+- interrupts : Should contain the interrupt for the device.
+- reg: Physical base address of the controller and length of memory mapped.
+
+Optional properties:
+- rockchip,sfc-no-dma: Indicate the controller doesn't support DMA transfer.
+
+Example:
+nor_flash: sfc@301c {
+ compatible = "rockchip,rv1108-sfc", "rockchip,sfc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_SFC>, < HCLK_SFC>;
+ clock-names = "sfc", "hsfc";
+ interrupts = ;
+ reg = <0x301c 0x1000>;
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <1200>;
+ reg = <0>;
+ };
+};
--
2.7.4
[PATCH v8 1/3] mtd: spi-nor: Bindings for Rockchip serial flash controller
From: Shawn Lin
Add binding document for the Rockchip serial flash controller.
Signed-off-by: Shawn Lin
Acked-by: Marek Vasut
Acked-by: Rob Herring
Signed-off-by: Andy Yan
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/mtd/rockchip-sfc.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/rockchip-sfc.txt
diff --git a/Documentation/devicetree/bindings/mtd/rockchip-sfc.txt
b/Documentation/devicetree/bindings/mtd/rockchip-sfc.txt
new file mode 100644
index 000..1e449b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/rockchip-sfc.txt
@@ -0,0 +1,31 @@
+Rockchip Serial Flash Controller
+
+Required properties:
+- compatible : Should be
+ "rockchip,rv1108-sfc", "rockchip,sfc" for ROCKCHIP RV1108.
+- address-cells : Should be 1.
+- size-cells : Should be 0.
+- clocks: Must contain two entries for each entry in clock-names.
+- clock-names: Shall be "sfc" for the transfer-clock, and "hsfc" for
+ the peripheral clock.
+- interrupts : Should contain the interrupt for the device.
+- reg: Physical base address of the controller and length of memory mapped.
+
+Optional properties:
+- rockchip,sfc-no-dma: Indicate the controller doesn't support DMA transfer.
+
+Example:
+nor_flash: sfc@301c {
+ compatible = "rockchip,rv1108-sfc", "rockchip,sfc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_SFC>, < HCLK_SFC>;
+ clock-names = "sfc", "hsfc";
+ interrupts = ;
+ reg = <0x301c 0x1000>;
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <1200>;
+ reg = <0>;
+ };
+};
--
2.7.4
[PATCH v8 2/3] mtd: spi-nor: add rockchip serial flash controller driver
From: Shawn Lin <shawn@rock-chips.com>
Add Rockchip SFC(serial flash controller) driver.
Signed-off-by: Shawn Lin <shawn@rock-chips.com>
Signed-off-by: Andy Yan <andy@rock-chips.com>
Acked-by: Marek Vasut <marek.va...@gmail.com>
---
Changes in v8:
- remove unused macro SFC_CMD_TRAN_BYTES_MASK
- set max transfer length to 15.5KB
- remove unnecessary buffer align check
- remove the duplicate logic what spi-nor.c already does for spi_nor_write
- add spi_nor_erase, as the SFC should get the erase address.
Changes in v7:
- correct the fifo status check in pio read/write mode.
- copy data from user buffer to dma buffer
Changes in v6:
- fold in Andy's improvement for checking fifo level
before pio read
- rename the controller to rv1108 since offically it's
renamed and acked by Rob.
- use dma_coerce_mask_and_coherent suggested by Andy.
Changes in v5:
- check if the buf is aligned to 32bit
- check if the buf for dma comes from vmalloc
- fix to use 1-1-n according to the current framework
- avoid bytes cnt overflow
Changes in v4:
- use uppercase DMA for description
- simplify the code of get_if_type
- use dma_dir to simplify the code
- simplify the rockchip_sfc_do_rd_wr
- some minor improvements
- add reset controller when doing resume
Changes in v3:
- use io{read32,write32}_rep to simplify the corner cases
- remove more unnecessary bit definitions
- some minor comment fixes and improvement
- fix wrong unregister function
- unify more code
- use nor to avoid constantly replicating the whole
sfc->flash[sfc->num_chip].nor
- add email for MODULE_AUTHOR
- remove #if 1 --- #endif
- extract DMA code to imporve the code structure
- reset all when failing to do dma
- pass sfc to get_if_type
- rename sfc-no-dma to sfc-no-DMA
Changes in v2:
- fix typos
- add some comment for buffer and others operations
- rename SFC_MAX_CHIP_NUM to MAX_CHIPSELECT_NUM
- use u8 for cs
- return -EINVAL for default case of get_if_type
- use readl_poll_*() to check timeout cases
- simplify and clarify some condition checks
- rework the bitshifts to simplify the code
- define SFC_CMD_DUMMY(x)
- fix ummap for dma read path and finish all the
cache maintenance.
- rename to rockchip_sfc_chip_priv and embed struct spi_nor
in it.
- add MODULE_AUTHOR
- add runtime PM and general PM support.
- Thanks for Marek's comments. Link:
http://lists.infradead.org/pipermail/linux-mtd/2016-November/070321.html
MAINTAINERS| 9 +
drivers/mtd/spi-nor/Kconfig| 7 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/rockchip-sfc.c | 942 +
4 files changed, 959 insertions(+)
create mode 100644 drivers/mtd/spi-nor/rockchip-sfc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index aa71ab52f..0718bc0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11704,6 +11704,15 @@ F: drivers/gpio/gpio-bd9571mwv.c
F: include/linux/mfd/bd9571mwv.h
F: Documentation/devicetree/bindings/mfd/bd9571mwv.txt
+ROCKCHIP SERIAL FLASH CONTROLLER DRIVER
+M: Shawn Lin <shawn....@rock-chips.com>
+M: Andy Yan <andy@rock-chips.com>
+L: linux-...@lists.infradead.org
+L: linux-rockc...@lists.infradead.org
+S: Maintained
+F: Documentation/devicetree/bindings/mtd/rockchip-sfc.txt
+F: drivers/mtd/spi-nor/rockchip-sfc.c
+
ROSE NETWORK LAYER
M: Ralf Baechle <r...@linux-mips.org>
L: linux-h...@vger.kernel.org
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 89da88e..f2898ea 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -129,4 +129,11 @@ config SPI_STM32_QUADSPI
This enables support for the STM32 Quad SPI controller.
We only connect the NOR to this controller.
+config SPI_ROCKCHIP_SFC
+ tristate "Rockchip Serial Flash Controller(SFC)"
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
+ depends on HAS_IOMEM && HAS_DMA
+ help
+ This enables support for rockchip serial flash controller.
+
endif # MTD_SPI_NOR
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index f4c61d2..c294156 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
obj-$(CONFIG_SPI_INTEL_SPI_PCI)+= intel-spi-pci.o
obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o
obj-$(CONFIG_SPI_STM32_QUADSPI)+= stm32-quadspi.o
+obj-$(CONFIG_SPI_ROCKCHIP_SFC) += rockchip-sfc.o
diff --git a/drivers/mtd/spi-nor/rockchip-sfc.c
b/drivers/mtd/spi-nor/rockchip-sfc.c
new file mode 100644
index 000..6037101
--- /dev/null
+++ b/drivers/mtd/spi-nor/rockchip-sfc.c
@@ -0,0 +1,942 @@
+/*
+ * Rockchip Serial Flash Controller Driver
+ *
+ * Copyright (c) 2017, Rockchip Inc.
+ * Author: Shawn Lin <shawn@rock-chips.com>
+ *
+ * This program is free software; you can redistribute i
[PATCH v8 2/3] mtd: spi-nor: add rockchip serial flash controller driver
From: Shawn Lin
Add Rockchip SFC(serial flash controller) driver.
Signed-off-by: Shawn Lin
Signed-off-by: Andy Yan
Acked-by: Marek Vasut
---
Changes in v8:
- remove unused macro SFC_CMD_TRAN_BYTES_MASK
- set max transfer length to 15.5KB
- remove unnecessary buffer align check
- remove the duplicate logic what spi-nor.c already does for spi_nor_write
- add spi_nor_erase, as the SFC should get the erase address.
Changes in v7:
- correct the fifo status check in pio read/write mode.
- copy data from user buffer to dma buffer
Changes in v6:
- fold in Andy's improvement for checking fifo level
before pio read
- rename the controller to rv1108 since offically it's
renamed and acked by Rob.
- use dma_coerce_mask_and_coherent suggested by Andy.
Changes in v5:
- check if the buf is aligned to 32bit
- check if the buf for dma comes from vmalloc
- fix to use 1-1-n according to the current framework
- avoid bytes cnt overflow
Changes in v4:
- use uppercase DMA for description
- simplify the code of get_if_type
- use dma_dir to simplify the code
- simplify the rockchip_sfc_do_rd_wr
- some minor improvements
- add reset controller when doing resume
Changes in v3:
- use io{read32,write32}_rep to simplify the corner cases
- remove more unnecessary bit definitions
- some minor comment fixes and improvement
- fix wrong unregister function
- unify more code
- use nor to avoid constantly replicating the whole
sfc->flash[sfc->num_chip].nor
- add email for MODULE_AUTHOR
- remove #if 1 --- #endif
- extract DMA code to imporve the code structure
- reset all when failing to do dma
- pass sfc to get_if_type
- rename sfc-no-dma to sfc-no-DMA
Changes in v2:
- fix typos
- add some comment for buffer and others operations
- rename SFC_MAX_CHIP_NUM to MAX_CHIPSELECT_NUM
- use u8 for cs
- return -EINVAL for default case of get_if_type
- use readl_poll_*() to check timeout cases
- simplify and clarify some condition checks
- rework the bitshifts to simplify the code
- define SFC_CMD_DUMMY(x)
- fix ummap for dma read path and finish all the
cache maintenance.
- rename to rockchip_sfc_chip_priv and embed struct spi_nor
in it.
- add MODULE_AUTHOR
- add runtime PM and general PM support.
- Thanks for Marek's comments. Link:
http://lists.infradead.org/pipermail/linux-mtd/2016-November/070321.html
MAINTAINERS| 9 +
drivers/mtd/spi-nor/Kconfig| 7 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/rockchip-sfc.c | 942 +
4 files changed, 959 insertions(+)
create mode 100644 drivers/mtd/spi-nor/rockchip-sfc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index aa71ab52f..0718bc0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11704,6 +11704,15 @@ F: drivers/gpio/gpio-bd9571mwv.c
F: include/linux/mfd/bd9571mwv.h
F: Documentation/devicetree/bindings/mfd/bd9571mwv.txt
+ROCKCHIP SERIAL FLASH CONTROLLER DRIVER
+M: Shawn Lin
+M: Andy Yan
+L: linux-...@lists.infradead.org
+L: linux-rockc...@lists.infradead.org
+S: Maintained
+F: Documentation/devicetree/bindings/mtd/rockchip-sfc.txt
+F: drivers/mtd/spi-nor/rockchip-sfc.c
+
ROSE NETWORK LAYER
M: Ralf Baechle
L: linux-h...@vger.kernel.org
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 89da88e..f2898ea 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -129,4 +129,11 @@ config SPI_STM32_QUADSPI
This enables support for the STM32 Quad SPI controller.
We only connect the NOR to this controller.
+config SPI_ROCKCHIP_SFC
+ tristate "Rockchip Serial Flash Controller(SFC)"
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
+ depends on HAS_IOMEM && HAS_DMA
+ help
+ This enables support for rockchip serial flash controller.
+
endif # MTD_SPI_NOR
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index f4c61d2..c294156 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
obj-$(CONFIG_SPI_INTEL_SPI_PCI)+= intel-spi-pci.o
obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o
obj-$(CONFIG_SPI_STM32_QUADSPI)+= stm32-quadspi.o
+obj-$(CONFIG_SPI_ROCKCHIP_SFC) += rockchip-sfc.o
diff --git a/drivers/mtd/spi-nor/rockchip-sfc.c
b/drivers/mtd/spi-nor/rockchip-sfc.c
new file mode 100644
index 000..6037101
--- /dev/null
+++ b/drivers/mtd/spi-nor/rockchip-sfc.c
@@ -0,0 +1,942 @@
+/*
+ * Rockchip Serial Flash Controller Driver
+ *
+ * Copyright (c) 2017, Rockchip Inc.
+ * Author: Shawn Lin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hop
[PATCH v8 0/3] Add Rockchip SFC(serial flash controller) support
This is try to support SFC found on Rockchip RV1108 platform.
Thanks for Cyrille's review, this version trys to address all
his concern in V7 [0].
Feature:
(1) Support x1, x2, x4 data bits mode
(2) Support up to 4 chip select
(3) Support two independent clock domain: AHB clock and SPI clock
(4) Support DMA master up to 16KB - 1 transfer
Test environment:
This patchset was tested on RK1108 evb boards with Winboud w25q256,
Gigadevice GD25Q256, working fine with squashfs and jffs2.
[0] http://patchwork.ozlabs.org/patch/793292/
Changes in v8:
- remove unused macro SFC_CMD_TRAN_BYTES_MASK
- set max transfer length to 15.5KB
- remove unnecessary buffer align check
- remove the duplicate logic what spi-nor.c already does for spi_nor_write
- add spi_nor_erase, as the SFC should get the erase address.
Changes in v7:
- correct the fifo status check in pio read/write mode.
- copy data from user buffer to dma buffer
Changes in v6:
- fold in Andy's improvement for checking fifo level
before pio read
- rename the controller to rv1108 since offically it's
renamed and acked by Rob.
- use dma_coerce_mask_and_coherent suggested by Andy.
Changes in v5:
- check if the buf is aligned to 32bit
- check if the buf for dma comes from vmalloc
- fix to use 1-1-n according to the current framework
- avoid bytes cnt overflow
Changes in v4:
- use uppercase DMA for description
- simplify the code of get_if_type
- use dma_dir to simplify the code
- simplify the rockchip_sfc_do_rd_wr
- some minor improvements
- add reset controller when doing resume
Changes in v3:
- use io{read32,write32}_rep to simplify the corner cases
- remove more unnecessary bit definitions
- some minor comment fixes and improvement
- fix wrong unregister function
- unify more code
- use nor to avoid constantly replicating the whole
sfc->flash[sfc->num_chip].nor
- add email for MODULE_AUTHOR
- remove #if 1 --- #endif
- extract DMA code to imporve the code structure
- reset all when failing to do dma
- pass sfc to get_if_type
- rename sfc-no-dma to sfc-no-DMA
Changes in v2:
- fix typos
- add some comment for buffer and others operations
- rename SFC_MAX_CHIP_NUM to MAX_CHIPSELECT_NUM
- use u8 for cs
- return -EINVAL for default case of get_if_type
- use readl_poll_*() to check timeout cases
- simplify and clarify some condition checks
- rework the bitshifts to simplify the code
- define SFC_CMD_DUMMY(x)
- fix ummap for dma read path and finish all the
cache maintenance.
- rename to rockchip_sfc_chip_priv and embed struct spi_nor
in it.
- add MODULE_AUTHOR
- add runtime PM and general PM support.
- Thanks for Marek's comments. Link:
http://lists.infradead.org/pipermail/linux-mtd/2016-November/070321.html
Andy Yan (1):
ARM: dts: rockchip: enable sfc for rv1108 evb
Shawn Lin (2):
mtd: spi-nor: Bindings for Rockchip serial flash controller
mtd: spi-nor: add rockchip serial flash controller driver
.../devicetree/bindings/mtd/rockchip-sfc.txt | 31 +
MAINTAINERS| 9 +
arch/arm/boot/dts/rv1108-evb.dts | 10 +
arch/arm/boot/dts/rv1108.dtsi | 13 +
drivers/mtd/spi-nor/Kconfig| 7 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/rockchip-sfc.c | 942 +
7 files changed, 1013 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/rockchip-sfc.txt
create mode 100644 drivers/mtd/spi-nor/rockchip-sfc.c
--
2.7.4
[PATCH v8 0/3] Add Rockchip SFC(serial flash controller) support
This is try to support SFC found on Rockchip RV1108 platform.
Thanks for Cyrille's review, this version trys to address all
his concern in V7 [0].
Feature:
(1) Support x1, x2, x4 data bits mode
(2) Support up to 4 chip select
(3) Support two independent clock domain: AHB clock and SPI clock
(4) Support DMA master up to 16KB - 1 transfer
Test environment:
This patchset was tested on RK1108 evb boards with Winboud w25q256,
Gigadevice GD25Q256, working fine with squashfs and jffs2.
[0] http://patchwork.ozlabs.org/patch/793292/
Changes in v8:
- remove unused macro SFC_CMD_TRAN_BYTES_MASK
- set max transfer length to 15.5KB
- remove unnecessary buffer align check
- remove the duplicate logic what spi-nor.c already does for spi_nor_write
- add spi_nor_erase, as the SFC should get the erase address.
Changes in v7:
- correct the fifo status check in pio read/write mode.
- copy data from user buffer to dma buffer
Changes in v6:
- fold in Andy's improvement for checking fifo level
before pio read
- rename the controller to rv1108 since offically it's
renamed and acked by Rob.
- use dma_coerce_mask_and_coherent suggested by Andy.
Changes in v5:
- check if the buf is aligned to 32bit
- check if the buf for dma comes from vmalloc
- fix to use 1-1-n according to the current framework
- avoid bytes cnt overflow
Changes in v4:
- use uppercase DMA for description
- simplify the code of get_if_type
- use dma_dir to simplify the code
- simplify the rockchip_sfc_do_rd_wr
- some minor improvements
- add reset controller when doing resume
Changes in v3:
- use io{read32,write32}_rep to simplify the corner cases
- remove more unnecessary bit definitions
- some minor comment fixes and improvement
- fix wrong unregister function
- unify more code
- use nor to avoid constantly replicating the whole
sfc->flash[sfc->num_chip].nor
- add email for MODULE_AUTHOR
- remove #if 1 --- #endif
- extract DMA code to imporve the code structure
- reset all when failing to do dma
- pass sfc to get_if_type
- rename sfc-no-dma to sfc-no-DMA
Changes in v2:
- fix typos
- add some comment for buffer and others operations
- rename SFC_MAX_CHIP_NUM to MAX_CHIPSELECT_NUM
- use u8 for cs
- return -EINVAL for default case of get_if_type
- use readl_poll_*() to check timeout cases
- simplify and clarify some condition checks
- rework the bitshifts to simplify the code
- define SFC_CMD_DUMMY(x)
- fix ummap for dma read path and finish all the
cache maintenance.
- rename to rockchip_sfc_chip_priv and embed struct spi_nor
in it.
- add MODULE_AUTHOR
- add runtime PM and general PM support.
- Thanks for Marek's comments. Link:
http://lists.infradead.org/pipermail/linux-mtd/2016-November/070321.html
Andy Yan (1):
ARM: dts: rockchip: enable sfc for rv1108 evb
Shawn Lin (2):
mtd: spi-nor: Bindings for Rockchip serial flash controller
mtd: spi-nor: add rockchip serial flash controller driver
.../devicetree/bindings/mtd/rockchip-sfc.txt | 31 +
MAINTAINERS| 9 +
arch/arm/boot/dts/rv1108-evb.dts | 10 +
arch/arm/boot/dts/rv1108.dtsi | 13 +
drivers/mtd/spi-nor/Kconfig| 7 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/rockchip-sfc.c | 942 +
7 files changed, 1013 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/rockchip-sfc.txt
create mode 100644 drivers/mtd/spi-nor/rockchip-sfc.c
--
2.7.4
Re: [PATCH 2/2] cpufreq: dt: add support for rockchip rv1108
Hi Viresh:
On 2017年09月14日 03:18, Viresh Kumar wrote:
On 21-08-17, 17:10, Andy Yan wrote:
Add the compatible string to support the generic device tree
cpufreq-dt driver on rockchip rv1108 soc.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
index 1c26292..2d71c09 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -69,6 +69,7 @@ static const struct of_device_id machines[] __initconst = {
{ .compatible = "renesas,r8a7794", },
{ .compatible = "renesas,sh73a0", },
+ { .compatible = "rockchip,rv1108", },
{ .compatible = "rockchip,rk2928", },
{ .compatible = "rockchip,rk3036", },
{ .compatible = "rockchip,rk3066a", },
You use operating-points-v2 or the V1 bindings for this SoC? The SoCs using
operating-points-v2 don't need such changes anymore.
Yes, I use operating-points-v2.
Re: [PATCH 2/2] cpufreq: dt: add support for rockchip rv1108
Hi Viresh:
On 2017年09月14日 03:18, Viresh Kumar wrote:
On 21-08-17, 17:10, Andy Yan wrote:
Add the compatible string to support the generic device tree
cpufreq-dt driver on rockchip rv1108 soc.
Signed-off-by: Andy Yan
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
index 1c26292..2d71c09 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -69,6 +69,7 @@ static const struct of_device_id machines[] __initconst = {
{ .compatible = "renesas,r8a7794", },
{ .compatible = "renesas,sh73a0", },
+ { .compatible = "rockchip,rv1108", },
{ .compatible = "rockchip,rk2928", },
{ .compatible = "rockchip,rk3036", },
{ .compatible = "rockchip,rk3066a", },
You use operating-points-v2 or the V1 bindings for this SoC? The SoCs using
operating-points-v2 don't need such changes anymore.
Yes, I use operating-points-v2.
[PATCH v7 2/2] mtd: spi-nor: add support for GD25Q256
Add support for GD25Q256, a 32MiB SPI Nor flash
from GigaDevice.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/mtd/spi-nor/spi-nor.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 3b94308..dc89ef2 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -872,6 +872,8 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t
ofs, uint64_t len)
return ret;
}
+static int macronix_quad_enable(struct spi_nor *nor);
+
/* Used when the "_ext_id" is two bytes at most */
#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
.id = { \
@@ -999,6 +1001,12 @@ static const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ .quad_enable = macronix_quad_enable,
+ },
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
--
2.7.4
[PATCH v7 2/2] mtd: spi-nor: add support for GD25Q256
Add support for GD25Q256, a 32MiB SPI Nor flash
from GigaDevice.
Signed-off-by: Andy Yan
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/mtd/spi-nor/spi-nor.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 3b94308..dc89ef2 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -872,6 +872,8 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t
ofs, uint64_t len)
return ret;
}
+static int macronix_quad_enable(struct spi_nor *nor);
+
/* Used when the "_ext_id" is two bytes at most */
#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
.id = { \
@@ -999,6 +1001,12 @@ static const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ .quad_enable = macronix_quad_enable,
+ },
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
--
2.7.4
[PATCH v7 1/2] mtd: spi-nor: add a quad_enable callback in struct flash_info
Some manufacturers may use different bit to set QE on different
memories.
The GD25Q256 from GigaDevice is an example, which uses S6(bit 6
of the Status Register-1) to set QE, which is different with
other supported memories from GigaDevice that use S9(bit 1 of
the Status Register-2). This makes it is impossible to select
the quad enable method by distinguishing the MFR. This patch
introduce a quad_enable function which can be set per memory
in the flash_info list table.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v7:
- fix some typos.
Changes in v6:
- split the quad_enable callback to a single patch
- adjust the columns per line of the commit message.
Changes in v5:
- set quad_enable in flash_info list, thanks the guidance by Cyrille.
Changes in v4:
- add SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
Changes in v3:
- rebase on top of spi-nor tree
- add SPI_NOR_4B_OPCODES flag
Changes in v2:
- drop one line unnecessary modification
drivers/mtd/spi-nor/spi-nor.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index cf1d4a1..3b94308 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -89,6 +89,8 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+
+ int (*quad_enable)(struct spi_nor *nor);
};
#define JEDEC_MFR(info)((info)->id[0])
@@ -2388,6 +2390,15 @@ static int spi_nor_init_params(struct spi_nor *nor,
params->quad_enable = spansion_quad_enable;
break;
}
+
+ /*
+* Some manufacturer like GigaDevice may use different
+* bit to set QE on different memories, so the MFR can't
+* indicate the quad_enable method for this case, we need
+* set it in flash info list.
+*/
+ if (info->quad_enable)
+ params->quad_enable = info->quad_enable;
}
/* Override the parameters with data read from SFDP tables. */
--
2.7.4
[PATCH v7 1/2] mtd: spi-nor: add a quad_enable callback in struct flash_info
Some manufacturers may use different bit to set QE on different
memories.
The GD25Q256 from GigaDevice is an example, which uses S6(bit 6
of the Status Register-1) to set QE, which is different with
other supported memories from GigaDevice that use S9(bit 1 of
the Status Register-2). This makes it is impossible to select
the quad enable method by distinguishing the MFR. This patch
introduce a quad_enable function which can be set per memory
in the flash_info list table.
Signed-off-by: Andy Yan
---
Changes in v7:
- fix some typos.
Changes in v6:
- split the quad_enable callback to a single patch
- adjust the columns per line of the commit message.
Changes in v5:
- set quad_enable in flash_info list, thanks the guidance by Cyrille.
Changes in v4:
- add SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
Changes in v3:
- rebase on top of spi-nor tree
- add SPI_NOR_4B_OPCODES flag
Changes in v2:
- drop one line unnecessary modification
drivers/mtd/spi-nor/spi-nor.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index cf1d4a1..3b94308 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -89,6 +89,8 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+
+ int (*quad_enable)(struct spi_nor *nor);
};
#define JEDEC_MFR(info)((info)->id[0])
@@ -2388,6 +2390,15 @@ static int spi_nor_init_params(struct spi_nor *nor,
params->quad_enable = spansion_quad_enable;
break;
}
+
+ /*
+* Some manufacturer like GigaDevice may use different
+* bit to set QE on different memories, so the MFR can't
+* indicate the quad_enable method for this case, we need
+* set it in flash info list.
+*/
+ if (info->quad_enable)
+ params->quad_enable = info->quad_enable;
}
/* Override the parameters with data read from SFDP tables. */
--
2.7.4
[PATCH v6 2/2] mtd: spi-nor: add support for GD25Q256
Add support for GD25Q256, a 32MiB SPI Nor flash
from GigaDevice.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/mtd/spi-nor/spi-nor.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 3b94308..dc89ef2 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -872,6 +872,8 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t
ofs, uint64_t len)
return ret;
}
+static int macronix_quad_enable(struct spi_nor *nor);
+
/* Used when the "_ext_id" is two bytes at most */
#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
.id = { \
@@ -999,6 +1001,12 @@ static const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ .quad_enable = macronix_quad_enable,
+ },
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
--
2.7.4
[PATCH v6 2/2] mtd: spi-nor: add support for GD25Q256
Add support for GD25Q256, a 32MiB SPI Nor flash
from GigaDevice.
Signed-off-by: Andy Yan
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/mtd/spi-nor/spi-nor.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 3b94308..dc89ef2 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -872,6 +872,8 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t
ofs, uint64_t len)
return ret;
}
+static int macronix_quad_enable(struct spi_nor *nor);
+
/* Used when the "_ext_id" is two bytes at most */
#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
.id = { \
@@ -999,6 +1001,12 @@ static const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ .quad_enable = macronix_quad_enable,
+ },
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
--
2.7.4
[PATCH v6 1/2] mtd: spi-nor: add a quad_enable callback in struct flash_info
Some manufacturers may use different bit to set QE on
different memories.
The GD25Q256 from GigaDevice is a example, which uses S6(bit 6
of the Status Register-1) to set QE, which is different with
other supported memories from GigaDevice that use S9(bit 1 of
the Status Register-2). This makes it is impossible to select
the quald enable methd by distinguish the MFR，So this patch
introduce a quad_enable function which can be set per memory
in the flash_info list table.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v6:
- split the quad_enable callback to a single patch
- adjust the columns per line of the commit message.
Changes in v5:
- set quad_enable in flash_info list, thanks the guidance by Cyrille.
Changes in v4:
- add SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
Changes in v3:
- rebase on top of spi-nor tree
- add SPI_NOR_4B_OPCODES flag
Changes in v2:
- drop one line unnecessary modification
drivers/mtd/spi-nor/spi-nor.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index cf1d4a1..3b94308 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -89,6 +89,8 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+
+ int (*quad_enable)(struct spi_nor *nor);
};
#define JEDEC_MFR(info)((info)->id[0])
@@ -2388,6 +2390,15 @@ static int spi_nor_init_params(struct spi_nor *nor,
params->quad_enable = spansion_quad_enable;
break;
}
+
+ /*
+* Some manufacturer like GigaDevice may use different
+* bit to set QE on different memories, so the MFR can't
+* indicate the quad_enable method for this case, we need
+* set it in flash info list.
+*/
+ if (info->quad_enable)
+ params->quad_enable = info->quad_enable;
}
/* Override the parameters with data read from SFDP tables. */
--
2.7.4
[PATCH v6 1/2] mtd: spi-nor: add a quad_enable callback in struct flash_info
Some manufacturers may use different bit to set QE on
different memories.
The GD25Q256 from GigaDevice is a example, which uses S6(bit 6
of the Status Register-1) to set QE, which is different with
other supported memories from GigaDevice that use S9(bit 1 of
the Status Register-2). This makes it is impossible to select
the quald enable methd by distinguish the MFR，So this patch
introduce a quad_enable function which can be set per memory
in the flash_info list table.
Signed-off-by: Andy Yan
---
Changes in v6:
- split the quad_enable callback to a single patch
- adjust the columns per line of the commit message.
Changes in v5:
- set quad_enable in flash_info list, thanks the guidance by Cyrille.
Changes in v4:
- add SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
Changes in v3:
- rebase on top of spi-nor tree
- add SPI_NOR_4B_OPCODES flag
Changes in v2:
- drop one line unnecessary modification
drivers/mtd/spi-nor/spi-nor.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index cf1d4a1..3b94308 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -89,6 +89,8 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+
+ int (*quad_enable)(struct spi_nor *nor);
};
#define JEDEC_MFR(info)((info)->id[0])
@@ -2388,6 +2390,15 @@ static int spi_nor_init_params(struct spi_nor *nor,
params->quad_enable = spansion_quad_enable;
break;
}
+
+ /*
+* Some manufacturer like GigaDevice may use different
+* bit to set QE on different memories, so the MFR can't
+* indicate the quad_enable method for this case, we need
+* set it in flash info list.
+*/
+ if (info->quad_enable)
+ params->quad_enable = info->quad_enable;
}
/* Override the parameters with data read from SFDP tables. */
--
2.7.4
[PATCH v5] mtd: spi-nor: add support for GD25Q256
Add support for GD25Q256, a 32MiB SPI Nor
flash from GigaDevice.
The GD25Q256 uses S6 to set QE, which is
different with other supported memories
from GigaDevice that use S9. So we introduce
a quad_enable function which can be set per
memory in the flash_info list.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v5:
- set quad_enable in flash_info list, thanks the guidance by Cyrille.
Changes in v4:
- add SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
Changes in v3:
- rebase on top of spi-nor tree
- add SPI_NOR_4B_OPCODES flag
Changes in v2:
- drop one line unnecessary modification
drivers/mtd/spi-nor/spi-nor.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index cf1d4a1..dc89ef2 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -89,6 +89,8 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+
+ int (*quad_enable)(struct spi_nor *nor);
};
#define JEDEC_MFR(info)((info)->id[0])
@@ -870,6 +872,8 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t
ofs, uint64_t len)
return ret;
}
+static int macronix_quad_enable(struct spi_nor *nor);
+
/* Used when the "_ext_id" is two bytes at most */
#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
.id = { \
@@ -997,6 +1001,12 @@ static const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ .quad_enable = macronix_quad_enable,
+ },
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
@@ -2388,6 +2398,15 @@ static int spi_nor_init_params(struct spi_nor *nor,
params->quad_enable = spansion_quad_enable;
break;
}
+
+ /*
+* Some manufacturer like GigaDevice may use different
+* bit to set QE on different memories, so the MFR can't
+* indicate the quad_enable method for this case, we need
+* set it in flash info list.
+*/
+ if (info->quad_enable)
+ params->quad_enable = info->quad_enable;
}
/* Override the parameters with data read from SFDP tables. */
--
2.7.4
[PATCH v5] mtd: spi-nor: add support for GD25Q256
Add support for GD25Q256, a 32MiB SPI Nor
flash from GigaDevice.
The GD25Q256 uses S6 to set QE, which is
different with other supported memories
from GigaDevice that use S9. So we introduce
a quad_enable function which can be set per
memory in the flash_info list.
Signed-off-by: Andy Yan
---
Changes in v5:
- set quad_enable in flash_info list, thanks the guidance by Cyrille.
Changes in v4:
- add SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
Changes in v3:
- rebase on top of spi-nor tree
- add SPI_NOR_4B_OPCODES flag
Changes in v2:
- drop one line unnecessary modification
drivers/mtd/spi-nor/spi-nor.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index cf1d4a1..dc89ef2 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -89,6 +89,8 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+
+ int (*quad_enable)(struct spi_nor *nor);
};
#define JEDEC_MFR(info)((info)->id[0])
@@ -870,6 +872,8 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t
ofs, uint64_t len)
return ret;
}
+static int macronix_quad_enable(struct spi_nor *nor);
+
/* Used when the "_ext_id" is two bytes at most */
#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
.id = { \
@@ -997,6 +1001,12 @@ static const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ .quad_enable = macronix_quad_enable,
+ },
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
@@ -2388,6 +2398,15 @@ static int spi_nor_init_params(struct spi_nor *nor,
params->quad_enable = spansion_quad_enable;
break;
}
+
+ /*
+* Some manufacturer like GigaDevice may use different
+* bit to set QE on different memories, so the MFR can't
+* indicate the quad_enable method for this case, we need
+* set it in flash info list.
+*/
+ if (info->quad_enable)
+ params->quad_enable = info->quad_enable;
}
/* Override the parameters with data read from SFDP tables. */
--
2.7.4
Re: [PATCH v4] mtd: spi-nor: add support for GD25Q256
Hi Cyrille:
On 2017年08月23日 15:46, Cyrille Pitchen wrote:
Hi Andy,
Le 16/08/2017 à 05:40, Andy Yan a écrit :
Hi Cyrille:
On 2017年08月16日 00:04, Cyrille Pitchen wrote:
Hi Andy,
Le 25/07/2017 à 12:12, Andy Yan a écrit :
Add support for GD25Q256, a 32MiB SPI Nor
flash from Gigadevice.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v4:
- add SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
Between v3 and v4, I see that you've also changed the procedure to the
the Quad Enable bit on all Gigadevice memories with QSPI capabilities.
This is not a detail and should have been reported here.
Sorry, I will keep this in mind.
Changes in v3:
- rebase on top of spi-nor tree
- add SPI_NOR_4B_OPCODES flag
Changes in v2:
- drop one line unnecessary modification
drivers/mtd/spi-nor/spi-nor.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c
b/drivers/mtd/spi-nor/spi-nor.c
index 196b52f..e4145cd 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -986,6 +986,11 @@ static const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+{
+"gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+},
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
@@ -2365,6 +2370,7 @@ static int spi_nor_init_params(struct spi_nor
*nor,
SNOR_HWCAPS_PP_QUAD)) {
switch (JEDEC_MFR(info)) {
case SNOR_MFR_MACRONIX:
+case SNOR_MFR_GIGADEVICE:
params->quad_enable = macronix_quad_enable;
Here, you've have changed the Quad Enable requirement for *all*
Gigadevice memories with Quad SPI capabilities.
However, I'm reading the GD25Q128 datasheet and it claims that the QE
bit is BIT(1) of the Status Register 2. Hence some
spansion*_quad_enable() should be used, as before your patch.
Then, still according to the datasheet, the GD25Q128 memory is compliant
with the JESD216 specification (minor 0) but neither with rev A (minor
5) nor rev B (minor 6).
So its Basic Flash Parameter Table is limited to 9 DWORDs instead of 16
DWORDs, hence doesn't provide the Quad Enable requirements. It means
that the SFDP tables would not help to select the right _quad_enable()
function by overriding the choice made by the switch() statement above.
tl;dr
This chunk would introduce a regression with some already supported
Gigadevice memories. So I reject this patch, sorry.
After check some other Gigadevice memories, I found it's true as you
mentioned.
Some memories use S9 as the QE bit, but some use S6.
Do you have some ideas for this case? Add a check for the full
jedec_id or encode
the QE bit in the flash_info?
I am a new bee in the flash failed, very appreciate for your advice.
Historically spi-nor.c assumed that the procedure to set the QE bit
could be chosen based on the manufacturer ID only, hence without needing
to check the whole JEDEC ID. Obviouly this is no longer true for
Gigadevice SPI NOR memories...
So you need a solution which is backward compatible with the existing
code so you patch would not introduce any regression for other SPI NOR
memories.
Then, I suggest you add a .quad_enable member in 'struct flash_info'.
#define USE_CLSR BIT(14) /* use CLSR command */
+
+ int (*quad_enable)(struct spi_nor *nor);
};
#define JEDEC_MFR(info) ((info)->id[0]
Also in spi_nor_init_params():
/* Select the procedure to set the Quad Enable bit. */
if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
SNOR_HWCAPS_PP_QUAD)) {
switch (JEDEC_MFR(info)) {
case SNOR_MFR_MACRONIX:
params->quad_enable = macronix_quad_enable;
break;
case SNOR_MFR_MICRON:
break;
default:
/* Kept only for backward compatibility purpose. */
params->quad_enable = spansion_quad_enable;
break;
}
}
+
+ if (info->quad_enable)
+ params->quad_enable = info->quad_enable;
/* Override the parameters with data read from SFDP tables. */
nor->addr_width = 0;
nor->mtd.erasesize = 0;
if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
!(info->flags & SPI_NOR_SKIP_SFDP)) {
struct spi_nor_flash_parameter sfdp_params;
memcpy(_params, params, sizeof(sfdp_params));
if (spi_nor_parse_sfdp(nor, _params)) {
Re: [PATCH v4] mtd: spi-nor: add support for GD25Q256
Hi Cyrille:
On 2017年08月23日 15:46, Cyrille Pitchen wrote:
Hi Andy,
Le 16/08/2017 à 05:40, Andy Yan a écrit :
Hi Cyrille:
On 2017年08月16日 00:04, Cyrille Pitchen wrote:
Hi Andy,
Le 25/07/2017 à 12:12, Andy Yan a écrit :
Add support for GD25Q256, a 32MiB SPI Nor
flash from Gigadevice.
Signed-off-by: Andy Yan
---
Changes in v4:
- add SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
Between v3 and v4, I see that you've also changed the procedure to the
the Quad Enable bit on all Gigadevice memories with QSPI capabilities.
This is not a detail and should have been reported here.
Sorry, I will keep this in mind.
Changes in v3:
- rebase on top of spi-nor tree
- add SPI_NOR_4B_OPCODES flag
Changes in v2:
- drop one line unnecessary modification
drivers/mtd/spi-nor/spi-nor.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c
b/drivers/mtd/spi-nor/spi-nor.c
index 196b52f..e4145cd 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -986,6 +986,11 @@ static const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+{
+"gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+},
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
@@ -2365,6 +2370,7 @@ static int spi_nor_init_params(struct spi_nor
*nor,
SNOR_HWCAPS_PP_QUAD)) {
switch (JEDEC_MFR(info)) {
case SNOR_MFR_MACRONIX:
+case SNOR_MFR_GIGADEVICE:
params->quad_enable = macronix_quad_enable;
Here, you've have changed the Quad Enable requirement for *all*
Gigadevice memories with Quad SPI capabilities.
However, I'm reading the GD25Q128 datasheet and it claims that the QE
bit is BIT(1) of the Status Register 2. Hence some
spansion*_quad_enable() should be used, as before your patch.
Then, still according to the datasheet, the GD25Q128 memory is compliant
with the JESD216 specification (minor 0) but neither with rev A (minor
5) nor rev B (minor 6).
So its Basic Flash Parameter Table is limited to 9 DWORDs instead of 16
DWORDs, hence doesn't provide the Quad Enable requirements. It means
that the SFDP tables would not help to select the right _quad_enable()
function by overriding the choice made by the switch() statement above.
tl;dr
This chunk would introduce a regression with some already supported
Gigadevice memories. So I reject this patch, sorry.
After check some other Gigadevice memories, I found it's true as you
mentioned.
Some memories use S9 as the QE bit, but some use S6.
Do you have some ideas for this case? Add a check for the full
jedec_id or encode
the QE bit in the flash_info?
I am a new bee in the flash failed, very appreciate for your advice.
Historically spi-nor.c assumed that the procedure to set the QE bit
could be chosen based on the manufacturer ID only, hence without needing
to check the whole JEDEC ID. Obviouly this is no longer true for
Gigadevice SPI NOR memories...
So you need a solution which is backward compatible with the existing
code so you patch would not introduce any regression for other SPI NOR
memories.
Then, I suggest you add a .quad_enable member in 'struct flash_info'.
#define USE_CLSR BIT(14) /* use CLSR command */
+
+ int (*quad_enable)(struct spi_nor *nor);
};
#define JEDEC_MFR(info) ((info)->id[0]
Also in spi_nor_init_params():
/* Select the procedure to set the Quad Enable bit. */
if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
SNOR_HWCAPS_PP_QUAD)) {
switch (JEDEC_MFR(info)) {
case SNOR_MFR_MACRONIX:
params->quad_enable = macronix_quad_enable;
break;
case SNOR_MFR_MICRON:
break;
default:
/* Kept only for backward compatibility purpose. */
params->quad_enable = spansion_quad_enable;
break;
}
}
+
+ if (info->quad_enable)
+ params->quad_enable = info->quad_enable;
/* Override the parameters with data read from SFDP tables. */
nor->addr_width = 0;
nor->mtd.erasesize = 0;
if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
!(info->flags & SPI_NOR_SKIP_SFDP)) {
struct spi_nor_flash_parameter sfdp_params;
memcpy(_params, params, sizeof(sfdp_params));
if (spi_nor_parse_sfdp(nor, _params)) {
nor->addr_wi
Re: [PATCH v2 3/3] cpufreq: dt: add support for rockchip rv1108
Hi Rafael: On 2017年08月22日 21:44, Rafael J. Wysocki wrote: On Tuesday, August 22, 2017 3:15:22 PM CEST Andy Yan wrote: Add the compatible string to support the generic device tree cpufreq-dt driver on rockchip rv1108 soc. Signed-off-by: Andy Yan <andy@rock-chips.com> This is a [3/3] in a series, so presumably it depends on something, so I guess it should be applied along with the thing it depends on. Right? The other two are dts parts [1] [2], they have been taken to arm-soc by Heiko. And Heiko also gave a Reviewed-by for this patch in v1[3]. [1] https://patchwork.kernel.org/patch/9915139/ [2] https://patchwork.kernel.org/patch/9915145/ [3] https://patchwork.kernel.org/patch/9911907/ Thanks, Rafael
Re: [PATCH v2 3/3] cpufreq: dt: add support for rockchip rv1108
Hi Rafael: On 2017年08月22日 21:44, Rafael J. Wysocki wrote: On Tuesday, August 22, 2017 3:15:22 PM CEST Andy Yan wrote: Add the compatible string to support the generic device tree cpufreq-dt driver on rockchip rv1108 soc. Signed-off-by: Andy Yan This is a [3/3] in a series, so presumably it depends on something, so I guess it should be applied along with the thing it depends on. Right? The other two are dts parts [1] [2], they have been taken to arm-soc by Heiko. And Heiko also gave a Reviewed-by for this patch in v1[3]. [1] https://patchwork.kernel.org/patch/9915139/ [2] https://patchwork.kernel.org/patch/9915145/ [3] https://patchwork.kernel.org/patch/9911907/ Thanks, Rafael
[PATCH v2 3/3] cpufreq: dt: add support for rockchip rv1108
Add the compatible string to support the generic device tree
cpufreq-dt driver on rockchip rv1108 soc.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v2: None
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
index 1c26292..2d71c09 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -69,6 +69,7 @@ static const struct of_device_id machines[] __initconst = {
{ .compatible = "renesas,r8a7794", },
{ .compatible = "renesas,sh73a0", },
+ { .compatible = "rockchip,rv1108", },
{ .compatible = "rockchip,rk2928", },
{ .compatible = "rockchip,rk3036", },
{ .compatible = "rockchip,rk3066a", },
--
2.7.4
[PATCH v2 3/3] cpufreq: dt: add support for rockchip rv1108
Add the compatible string to support the generic device tree
cpufreq-dt driver on rockchip rv1108 soc.
Signed-off-by: Andy Yan
---
Changes in v2: None
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
index 1c26292..2d71c09 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -69,6 +69,7 @@ static const struct of_device_id machines[] __initconst = {
{ .compatible = "renesas,r8a7794", },
{ .compatible = "renesas,sh73a0", },
+ { .compatible = "rockchip,rv1108", },
{ .compatible = "rockchip,rk2928", },
{ .compatible = "rockchip,rk3036", },
{ .compatible = "rockchip,rk3066a", },
--
2.7.4
[PATCH v2 2/3] ARM: dts: rockchip: add cpu power supply for rv1108 evb
The cpu is powered by regulator vdd_core on RV1108 evalution
board. Add it to the cpu dt node.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 32fb09a..e517aa3 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -104,6 +104,10 @@
};
};
+ {
+ cpu-supply = <_core>;
+};
+
{
status = "okay";
i2c-scl-rising-time-ns = <275>;
--
2.7.4
[PATCH v2 2/3] ARM: dts: rockchip: add cpu power supply for rv1108 evb
The cpu is powered by regulator vdd_core on RV1108 evalution
board. Add it to the cpu dt node.
Signed-off-by: Andy Yan
---
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 32fb09a..e517aa3 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -104,6 +104,10 @@
};
};
+ {
+ cpu-supply = <_core>;
+};
+
{
status = "okay";
i2c-scl-rising-time-ns = <275>;
--
2.7.4
[PATCH v2 1/3] ARM: dts: rockchip: add cpu opp table for rv1108
Add cpu opp table for rv1108 to support frequency
from 408MHZ to 1008MHZ.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v2:
- switch to operating-points-v2
- split cpu-supply to a separate patch
arch/arm/boot/dts/rv1108.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 064cec3..1b854e1 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -69,6 +69,33 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
+ operating-points-v2 = <_opp_table>;
+ clocks = < ARMCLK>;
+ };
+ };
+
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+
+ opp-40800 {
+ opp-hz = /bits/ 64 <40800>;
+ opp-microvolt = <975000>;
+ clock-latency-ns = <4>;
+ };
+ opp-6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <975000>;
+ clock-latency-ns = <4>;
+ };
+ opp-81600 {
+ opp-hz = /bits/ 64 <81600>;
+ opp-microvolt = <1025000>;
+ clock-latency-ns = <4>;
+ };
+ opp-100800 {
+ opp-hz = /bits/ 64 <100800>;
+ opp-microvolt = <115>;
+ clock-latency-ns = <4>;
};
};
--
2.7.4
[PATCH v2 1/3] ARM: dts: rockchip: add cpu opp table for rv1108
Add cpu opp table for rv1108 to support frequency
from 408MHZ to 1008MHZ.
Signed-off-by: Andy Yan
---
Changes in v2:
- switch to operating-points-v2
- split cpu-supply to a separate patch
arch/arm/boot/dts/rv1108.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 064cec3..1b854e1 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -69,6 +69,33 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
+ operating-points-v2 = <_opp_table>;
+ clocks = < ARMCLK>;
+ };
+ };
+
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+
+ opp-40800 {
+ opp-hz = /bits/ 64 <40800>;
+ opp-microvolt = <975000>;
+ clock-latency-ns = <4>;
+ };
+ opp-6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <975000>;
+ clock-latency-ns = <4>;
+ };
+ opp-81600 {
+ opp-hz = /bits/ 64 <81600>;
+ opp-microvolt = <1025000>;
+ clock-latency-ns = <4>;
+ };
+ opp-100800 {
+ opp-hz = /bits/ 64 <100800>;
+ opp-microvolt = <115>;
+ clock-latency-ns = <4>;
};
};
--
2.7.4
[PATCH 2/2] cpufreq: dt: add support for rockchip rv1108
Add the compatible string to support the generic device tree
cpufreq-dt driver on rockchip rv1108 soc.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
index 1c26292..2d71c09 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -69,6 +69,7 @@ static const struct of_device_id machines[] __initconst = {
{ .compatible = "renesas,r8a7794", },
{ .compatible = "renesas,sh73a0", },
+ { .compatible = "rockchip,rv1108", },
{ .compatible = "rockchip,rk2928", },
{ .compatible = "rockchip,rk3036", },
{ .compatible = "rockchip,rk3066a", },
--
2.7.4
[PATCH 2/2] cpufreq: dt: add support for rockchip rv1108
Add the compatible string to support the generic device tree
cpufreq-dt driver on rockchip rv1108 soc.
Signed-off-by: Andy Yan
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
b/drivers/cpufreq/cpufreq-dt-platdev.c
index 1c26292..2d71c09 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -69,6 +69,7 @@ static const struct of_device_id machines[] __initconst = {
{ .compatible = "renesas,r8a7794", },
{ .compatible = "renesas,sh73a0", },
+ { .compatible = "rockchip,rv1108", },
{ .compatible = "rockchip,rk2928", },
{ .compatible = "rockchip,rk3036", },
{ .compatible = "rockchip,rk3066a", },
--
2.7.4
[PATCH 1/2] ARM: dts: rockchip: add cpu opp table for rv1108
Add cpu opp table for rv1108 to support frequency
from 408MHZ to 1008MHZ.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
arch/arm/boot/dts/rv1108-evb.dts | 4
arch/arm/boot/dts/rv1108.dtsi| 9 +
2 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 32fb09a..e517aa3 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -104,6 +104,10 @@
};
};
+ {
+ cpu-supply = <_core>;
+};
+
{
status = "okay";
i2c-scl-rising-time-ns = <275>;
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 064cec3..6ebf07c 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -69,6 +69,15 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
+ operating-points = <
+ /* KHzuV */
+ 408000 975000
+ 60 975000
+ 816000 1025000
+ 1008000 115
+ >;
+ clock-latency = <4>;
+ clocks = < ARMCLK>;
};
};
--
2.7.4
[PATCH 1/2] ARM: dts: rockchip: add cpu opp table for rv1108
Add cpu opp table for rv1108 to support frequency
from 408MHZ to 1008MHZ.
Signed-off-by: Andy Yan
---
arch/arm/boot/dts/rv1108-evb.dts | 4
arch/arm/boot/dts/rv1108.dtsi| 9 +
2 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 32fb09a..e517aa3 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -104,6 +104,10 @@
};
};
+ {
+ cpu-supply = <_core>;
+};
+
{
status = "okay";
i2c-scl-rising-time-ns = <275>;
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 064cec3..6ebf07c 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -69,6 +69,15 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
+ operating-points = <
+ /* KHzuV */
+ 408000 975000
+ 60 975000
+ 816000 1025000
+ 1008000 115
+ >;
+ clock-latency = <4>;
+ clocks = < ARMCLK>;
};
};
--
2.7.4
Re: [PATCH v4] mtd: spi-nor: add support for GD25Q256
Hi Cyrille:
On 2017年08月16日 00:04, Cyrille Pitchen wrote:
Hi Andy,
Le 25/07/2017 à 12:12, Andy Yan a écrit :
Add support for GD25Q256, a 32MiB SPI Nor
flash from Gigadevice.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v4:
- add SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
Between v3 and v4, I see that you've also changed the procedure to the
the Quad Enable bit on all Gigadevice memories with QSPI capabilities.
This is not a detail and should have been reported here.
Sorry, I will keep this in mind.
Changes in v3:
- rebase on top of spi-nor tree
- add SPI_NOR_4B_OPCODES flag
Changes in v2:
- drop one line unnecessary modification
drivers/mtd/spi-nor/spi-nor.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 196b52f..e4145cd 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -986,6 +986,11 @@ static const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
@@ -2365,6 +2370,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
SNOR_HWCAPS_PP_QUAD)) {
switch (JEDEC_MFR(info)) {
case SNOR_MFR_MACRONIX:
+ case SNOR_MFR_GIGADEVICE:
params->quad_enable = macronix_quad_enable;
Here, you've have changed the Quad Enable requirement for *all*
Gigadevice memories with Quad SPI capabilities.
However, I'm reading the GD25Q128 datasheet and it claims that the QE
bit is BIT(1) of the Status Register 2. Hence some
spansion*_quad_enable() should be used, as before your patch.
Then, still according to the datasheet, the GD25Q128 memory is compliant
with the JESD216 specification (minor 0) but neither with rev A (minor
5) nor rev B (minor 6).
So its Basic Flash Parameter Table is limited to 9 DWORDs instead of 16
DWORDs, hence doesn't provide the Quad Enable requirements. It means
that the SFDP tables would not help to select the right _quad_enable()
function by overriding the choice made by the switch() statement above.
tl;dr
This chunk would introduce a regression with some already supported
Gigadevice memories. So I reject this patch, sorry.
After check some other Gigadevice memories, I found it's true as
you mentioned.
Some memories use S9 as the QE bit, but some use S6.
Do you have some ideas for this case? Add a check for the full
jedec_id or encode
the QE bit in the flash_info?
I am a new bee in the flash failed, very appreciate for your advice.
Best regards,
Cyrille
break;
Re: [PATCH v4] mtd: spi-nor: add support for GD25Q256
Hi Cyrille:
On 2017年08月16日 00:04, Cyrille Pitchen wrote:
Hi Andy,
Le 25/07/2017 à 12:12, Andy Yan a écrit :
Add support for GD25Q256, a 32MiB SPI Nor
flash from Gigadevice.
Signed-off-by: Andy Yan
---
Changes in v4:
- add SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB
Between v3 and v4, I see that you've also changed the procedure to the
the Quad Enable bit on all Gigadevice memories with QSPI capabilities.
This is not a detail and should have been reported here.
Sorry, I will keep this in mind.
Changes in v3:
- rebase on top of spi-nor tree
- add SPI_NOR_4B_OPCODES flag
Changes in v2:
- drop one line unnecessary modification
drivers/mtd/spi-nor/spi-nor.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 196b52f..e4145cd 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -986,6 +986,11 @@ static const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
@@ -2365,6 +2370,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
SNOR_HWCAPS_PP_QUAD)) {
switch (JEDEC_MFR(info)) {
case SNOR_MFR_MACRONIX:
+ case SNOR_MFR_GIGADEVICE:
params->quad_enable = macronix_quad_enable;
Here, you've have changed the Quad Enable requirement for *all*
Gigadevice memories with Quad SPI capabilities.
However, I'm reading the GD25Q128 datasheet and it claims that the QE
bit is BIT(1) of the Status Register 2. Hence some
spansion*_quad_enable() should be used, as before your patch.
Then, still according to the datasheet, the GD25Q128 memory is compliant
with the JESD216 specification (minor 0) but neither with rev A (minor
5) nor rev B (minor 6).
So its Basic Flash Parameter Table is limited to 9 DWORDs instead of 16
DWORDs, hence doesn't provide the Quad Enable requirements. It means
that the SFDP tables would not help to select the right _quad_enable()
function by overriding the choice made by the switch() statement above.
tl;dr
This chunk would introduce a regression with some already supported
Gigadevice memories. So I reject this patch, sorry.
After check some other Gigadevice memories, I found it's true as
you mentioned.
Some memories use S9 as the QE bit, but some use S6.
Do you have some ideas for this case? Add a check for the full
jedec_id or encode
the QE bit in the flash_info?
I am a new bee in the flash failed, very appreciate for your advice.
Best regards,
Cyrille
break;
[PATCH v4 7/8] ARM: dts: rockchip: add pmic rk805 dt node for rv1108 evb
RK805 is used as the voltage regulator on rv1108 evaluation
board. Add device tree node for it.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 108 +++
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 77ce707..a1bd95e 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -94,6 +94,114 @@
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
};
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-boot-on;
+ };
+};
+
+ {
+ status = "okay";
+ i2c-scl-rising-time-ns = <275>;
+ i2c-scl-falling-time-ns = <16>;
+ clock-frequency = <40>;
+
+ rk805: pmic@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <>;
+ interrupts = ;
+ rockchip,system-power-controller;
+
+ vcc1-supply = <_sys>;
+ vcc2-supply = <_sys>;
+ vcc3-supply = <_sys>;
+ vcc4-supply = <_sys>;
+ vcc5-supply = <_sys>;
+ vcc6-supply = <_sys>;
+
+ regulators {
+ vdd_core: DCDC_REG1 {
+ regulator-name= "vdd_core";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <150>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ regulator-state-uv = <90>;
+ };
+ };
+
+ vdd_cam: DCDC_REG2 {
+ regulator-name= "vdd_cam";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <200>;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name= "vcc_ddr";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name= "vcc_io";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ regulator-state-uv = <330>;
+ };
+ };
+
+ vdd_10: LDO_REG1 {
+ regulator-name= "vdd_10";
+ regulator-min-microvolt = <100>;
+ regulator-max-microvolt = <100>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vcc_18: LDO_REG2 {
+ regulator-name= "vcc_18";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vdd10_pmu: LDO_REG3 {
+ r
[PATCH v4 7/8] ARM: dts: rockchip: add pmic rk805 dt node for rv1108 evb
RK805 is used as the voltage regulator on rv1108 evaluation
board. Add device tree node for it.
Signed-off-by: Andy Yan
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 108 +++
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 77ce707..a1bd95e 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -94,6 +94,114 @@
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
};
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-boot-on;
+ };
+};
+
+ {
+ status = "okay";
+ i2c-scl-rising-time-ns = <275>;
+ i2c-scl-falling-time-ns = <16>;
+ clock-frequency = <40>;
+
+ rk805: pmic@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <>;
+ interrupts = ;
+ rockchip,system-power-controller;
+
+ vcc1-supply = <_sys>;
+ vcc2-supply = <_sys>;
+ vcc3-supply = <_sys>;
+ vcc4-supply = <_sys>;
+ vcc5-supply = <_sys>;
+ vcc6-supply = <_sys>;
+
+ regulators {
+ vdd_core: DCDC_REG1 {
+ regulator-name= "vdd_core";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <150>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ regulator-state-uv = <90>;
+ };
+ };
+
+ vdd_cam: DCDC_REG2 {
+ regulator-name= "vdd_cam";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <200>;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name= "vcc_ddr";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name= "vcc_io";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ regulator-state-uv = <330>;
+ };
+ };
+
+ vdd_10: LDO_REG1 {
+ regulator-name= "vdd_10";
+ regulator-min-microvolt = <100>;
+ regulator-max-microvolt = <100>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vcc_18: LDO_REG2 {
+ regulator-name= "vcc_18";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vdd10_pmu: LDO_REG3 {
+ regulat
[PATCH v4 8/8] ARM: dts: rockchip: add accelerometer bma250e dt node for rv1108 evb
Add dt node of bosch accelerometer bma250e on rv1108 evb.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v4:
- order it by i2c address.
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index a1bd95e..32fb09a 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -202,6 +202,13 @@
};
};
};
+
+ bma250: accelerometer@19 {
+ compatible = "bosch,bma250e";
+ reg = <0x19>;
+ interrupt-parent = <>;
+ interrupts = ;
+ };
};
{
--
2.7.4
[PATCH v4 8/8] ARM: dts: rockchip: add accelerometer bma250e dt node for rv1108 evb
Add dt node of bosch accelerometer bma250e on rv1108 evb.
Signed-off-by: Andy Yan
---
Changes in v4:
- order it by i2c address.
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index a1bd95e..32fb09a 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -202,6 +202,13 @@
};
};
};
+
+ bma250: accelerometer@19 {
+ compatible = "bosch,bma250e";
+ reg = <0x19>;
+ interrupt-parent = <>;
+ interrupts = ;
+ };
};
{
--
2.7.4
[PATCH v4 6/8] ARM: dts: rockchip: add pwm backlight for rv1108 evb
RV1108 EVB uses pwm0 modulate the backlight, add dt
node to enable it.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 43
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 44feea7..77ce707 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -55,6 +55,49 @@
stdout-path = "serial2:150n8";
bootargs = "root=/dev/mtdblock2
mtdparts=spi-nor:256k@0(u-boot)ro,6m(kernel)ro,9m(rootfs),-(freedisk)";
};
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = < 0 25000 0>;
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+16 17 18 19 20 21 22 23
+24 25 26 27 28 29 30 31
+32 33 34 35 36 37 38 39
+40 41 42 43 44 45 46 47
+48 49 50 51 52 53 54 55
+56 57 58 59 60 61 62 63
+64 65 66 67 68 69 70 71
+72 73 74 75 76 77 78 79
+80 81 82 83 84 85 86 87
+88 89 90 91 92 93 94 95
+96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255>;
+ default-brightness-level = <200>;
+ };
+};
+
+ {
+ status = "okay";
};
{
--
2.7.4
[PATCH v4 6/8] ARM: dts: rockchip: add pwm backlight for rv1108 evb
RV1108 EVB uses pwm0 modulate the backlight, add dt
node to enable it.
Signed-off-by: Andy Yan
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 43
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 44feea7..77ce707 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -55,6 +55,49 @@
stdout-path = "serial2:150n8";
bootargs = "root=/dev/mtdblock2
mtdparts=spi-nor:256k@0(u-boot)ro,6m(kernel)ro,9m(rootfs),-(freedisk)";
};
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = < 0 25000 0>;
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+16 17 18 19 20 21 22 23
+24 25 26 27 28 29 30 31
+32 33 34 35 36 37 38 39
+40 41 42 43 44 45 46 47
+48 49 50 51 52 53 54 55
+56 57 58 59 60 61 62 63
+64 65 66 67 68 69 70 71
+72 73 74 75 76 77 78 79
+80 81 82 83 84 85 86 87
+88 89 90 91 92 93 94 95
+96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255>;
+ default-brightness-level = <200>;
+ };
+};
+
+ {
+ status = "okay";
};
{
--
2.7.4
[PATCH v4 5/8] ARM: dts: rockchip: add saradc support for rv1108
Add saradc device tree node for rv1108 soc
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v4:
- remove unnecessary property io-channel-ranges
Changes in v3: None
Changes in v2:
- add compatible string "rockchip,rv1108-saradc"
arch/arm/boot/dts/rv1108.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 75a0b1e..064cec3 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -275,6 +275,17 @@
status = "disabled";
};
+ adc: adc@1038c000 {
+ compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
+ reg = <0x1038c000 0x100>;
+ interrupts = ;
+ #io-channel-cells = <1>;
+ clock-frequency = <100>;
+ clocks = < SCLK_SARADC>, < PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ status = "disabled";
+ };
+
i2c0: i2c@2000 {
compatible = "rockchip,rv1108-i2c";
reg = <0x2000 0x1000>;
--
2.7.4
[PATCH v4 5/8] ARM: dts: rockchip: add saradc support for rv1108
Add saradc device tree node for rv1108 soc
Signed-off-by: Andy Yan
---
Changes in v4:
- remove unnecessary property io-channel-ranges
Changes in v3: None
Changes in v2:
- add compatible string "rockchip,rv1108-saradc"
arch/arm/boot/dts/rv1108.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 75a0b1e..064cec3 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -275,6 +275,17 @@
status = "disabled";
};
+ adc: adc@1038c000 {
+ compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
+ reg = <0x1038c000 0x100>;
+ interrupts = ;
+ #io-channel-cells = <1>;
+ clock-frequency = <100>;
+ clocks = < SCLK_SARADC>, < PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ status = "disabled";
+ };
+
i2c0: i2c@2000 {
compatible = "rockchip,rv1108-i2c";
reg = <0x2000 0x1000>;
--
2.7.4
[PATCH v4 4/8] ARM: dts: rockchip: add pwm dt node for rv1108
Add pwm device tree node for rv1108 soc
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- add compatible string "rockchip,rv1108-pwm"
arch/arm/boot/dts/rv1108.dtsi | 143 ++
1 file changed, 143 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 4470679..75a0b1e 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -213,6 +213,54 @@
status = "disabled";
};
+ pwm4: pwm@1028 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x1028 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm5: pwm@10280010 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280010 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm6: pwm@10280020 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280020 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm7: pwm@10280030 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280030 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
grf: syscon@1030 {
compatible = "rockchip,rv1108-grf", "syscon";
reg = <0x1030 0x1000>;
@@ -241,6 +289,53 @@
status = "disabled";
};
+ pwm0: pwm@2004 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x2004 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm1: pwm@20040010 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040010 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm2: pwm@20040020 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040020 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm3: pwm@20040030 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040030 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+
[PATCH v4 4/8] ARM: dts: rockchip: add pwm dt node for rv1108
Add pwm device tree node for rv1108 soc
Signed-off-by: Andy Yan
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- add compatible string "rockchip,rv1108-pwm"
arch/arm/boot/dts/rv1108.dtsi | 143 ++
1 file changed, 143 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 4470679..75a0b1e 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -213,6 +213,54 @@
status = "disabled";
};
+ pwm4: pwm@1028 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x1028 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm5: pwm@10280010 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280010 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm6: pwm@10280020 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280020 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm7: pwm@10280030 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280030 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
grf: syscon@1030 {
compatible = "rockchip,rv1108-grf", "syscon";
reg = <0x1030 0x1000>;
@@ -241,6 +289,53 @@
status = "disabled";
};
+ pwm0: pwm@2004 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x2004 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm1: pwm@20040010 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040010 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm2: pwm@20040020 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040020 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm3: pwm@20040030 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040030 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+
[PATCH v4 3/8] dt-bindings: pwm: add description for rv1108 pwm
Add device tree bindings document for pwm on rockchip rv1108 soc. Signed-off-by: Andy Yan <andy@rock-chips.com> --- Changes in v4: None Changes in v3: - make the compatible string be: "rockchip,rv1108-pwm", "rockchip,rk3288-pwm" for rv1108 Changes in v2: None Documentation/devicetree/bindings/pwm/pwm-rockchip.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt index 2350ef9..2c5e52a 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt @@ -3,7 +3,8 @@ Rockchip PWM controller Required properties: - compatible: should be "rockchip,-pwm" "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs - "rockchip,rk3288-pwm": found on RK3288 SoC + "rockchip,rk3288-pwm": found on RK3288 SOC + "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC - reg: physical base address and length of the controller's registers - clocks: See ../clock/clock-bindings.txt -- 2.7.4
[PATCH v4 3/8] dt-bindings: pwm: add description for rv1108 pwm
Add device tree bindings document for pwm on rockchip rv1108 soc. Signed-off-by: Andy Yan --- Changes in v4: None Changes in v3: - make the compatible string be: "rockchip,rv1108-pwm", "rockchip,rk3288-pwm" for rv1108 Changes in v2: None Documentation/devicetree/bindings/pwm/pwm-rockchip.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt index 2350ef9..2c5e52a 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt @@ -3,7 +3,8 @@ Rockchip PWM controller Required properties: - compatible: should be "rockchip,-pwm" "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs - "rockchip,rk3288-pwm": found on RK3288 SoC + "rockchip,rk3288-pwm": found on RK3288 SOC + "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC - reg: physical base address and length of the controller's registers - clocks: See ../clock/clock-bindings.txt -- 2.7.4
[PATCH v4 2/8] ARM: dts: rockchip: add spi dt node for rv1108
Add SPI device tree node for rv1108.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 86aa52a..4470679 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -200,6 +200,19 @@
status = "disabled";
};
+ spi: spi@1027 {
+ compatible = "rockchip,rv1108-spi";
+ reg = <0x1027 0x1000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_SPI>, < PCLK_SPI>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = < 8>, < 9>;
+ #dma-cells = <2>;
+ status = "disabled";
+ };
+
grf: syscon@1030 {
compatible = "rockchip,rv1108-grf", "syscon";
reg = <0x1030 0x1000>;
--
2.7.4
[PATCH v4 2/8] ARM: dts: rockchip: add spi dt node for rv1108
Add SPI device tree node for rv1108.
Signed-off-by: Andy Yan
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 86aa52a..4470679 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -200,6 +200,19 @@
status = "disabled";
};
+ spi: spi@1027 {
+ compatible = "rockchip,rv1108-spi";
+ reg = <0x1027 0x1000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_SPI>, < PCLK_SPI>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = < 8>, < 9>;
+ #dma-cells = <2>;
+ status = "disabled";
+ };
+
grf: syscon@1030 {
compatible = "rockchip,rv1108-grf", "syscon";
reg = <0x1030 0x1000>;
--
2.7.4
[PATCH v4 1/8] spi: rockchip: add compatible string for rv1108 spi
The spi on rv1108 is the same as other rockchip based
socs, add compatible string for it.
Signed-off-by: Andy Yan <andy@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
Documentation/devicetree/bindings/spi/spi-rockchip.txt | 1 +
drivers/spi/spi-rockchip.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
index 83da493..6e3ffac 100644
--- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
@@ -6,6 +6,7 @@ and display controllers using the SPI communication interface.
Required Properties:
- compatible: should be one of the following.
+"rockchip,rv1108-spi" for rv1108 SoCs.
"rockchip,rk3036-spi" for rk3036 SoCS.
"rockchip,rk3066-spi" for rk3066 SoCs.
"rockchip,rk3188-spi" for rk3188 SoCs.
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 0b4a52b..27b4db2 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -919,6 +919,7 @@ static const struct dev_pm_ops rockchip_spi_pm = {
};
static const struct of_device_id rockchip_spi_dt_match[] = {
+ { .compatible = "rockchip,rv1108-spi", },
{ .compatible = "rockchip,rk3036-spi", },
{ .compatible = "rockchip,rk3066-spi", },
{ .compatible = "rockchip,rk3188-spi", },
--
2.7.4
[PATCH v4 1/8] spi: rockchip: add compatible string for rv1108 spi
The spi on rv1108 is the same as other rockchip based
socs, add compatible string for it.
Signed-off-by: Andy Yan
Acked-by: Rob Herring
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
Documentation/devicetree/bindings/spi/spi-rockchip.txt | 1 +
drivers/spi/spi-rockchip.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
index 83da493..6e3ffac 100644
--- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
@@ -6,6 +6,7 @@ and display controllers using the SPI communication interface.
Required Properties:
- compatible: should be one of the following.
+"rockchip,rv1108-spi" for rv1108 SoCs.
"rockchip,rk3036-spi" for rk3036 SoCS.
"rockchip,rk3066-spi" for rk3066 SoCs.
"rockchip,rk3188-spi" for rk3188 SoCs.
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 0b4a52b..27b4db2 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -919,6 +919,7 @@ static const struct dev_pm_ops rockchip_spi_pm = {
};
static const struct of_device_id rockchip_spi_dt_match[] = {
+ { .compatible = "rockchip,rv1108-spi", },
{ .compatible = "rockchip,rk3036-spi", },
{ .compatible = "rockchip,rk3066-spi", },
{ .compatible = "rockchip,rk3188-spi", },
--
2.7.4
[PATCH v4 0/8] Support more devices on rockchip rv1108
This series try to support i2c/spi/pwm/saradc/pmic/watchdog on rockchip rv1108 soc. The clk tree, pinctrl, i2c, watchdog and saradc dt-bindings has been applied. So there are not included in this version. Changes in v4: - remove unnecessary property io-channel-ranges of saradc - order i2c devices by i2c address. Changes in v3: - make the compatible string be: "rockchip,rv1108-pwm", "rockchip,rk3288-pwm" for rv1108 Changes in v2: - add compatible string "rockchip,rv1108-pwm" - add compatible string "rockchip,rv1108-saradc" Andy Yan (8): spi: rockchip: add compatible string for rv1108 spi ARM: dts: rockchip: add spi dt node for rv1108 dt-bindings: pwm: add description for rv1108 pwm ARM: dts: rockchip: add pwm dt node for rv1108 ARM: dts: rockchip: add saradc support for rv1108 ARM: dts: rockchip: add pwm backlight for rv1108 evb ARM: dts: rockchip: add pmic rk805 dt node for rv1108 evb ARM: dts: rockchip: add accelerometer bma250e dt node for rv1108 evb .../devicetree/bindings/pwm/pwm-rockchip.txt | 3 +- .../devicetree/bindings/spi/spi-rockchip.txt | 1 + arch/arm/boot/dts/rv1108-evb.dts | 158 +++ arch/arm/boot/dts/rv1108.dtsi | 167 + drivers/spi/spi-rockchip.c | 1 + 5 files changed, 329 insertions(+), 1 deletion(-) -- 2.7.4
[PATCH v4 0/8] Support more devices on rockchip rv1108
This series try to support i2c/spi/pwm/saradc/pmic/watchdog on rockchip rv1108 soc. The clk tree, pinctrl, i2c, watchdog and saradc dt-bindings has been applied. So there are not included in this version. Changes in v4: - remove unnecessary property io-channel-ranges of saradc - order i2c devices by i2c address. Changes in v3: - make the compatible string be: "rockchip,rv1108-pwm", "rockchip,rk3288-pwm" for rv1108 Changes in v2: - add compatible string "rockchip,rv1108-pwm" - add compatible string "rockchip,rv1108-saradc" Andy Yan (8): spi: rockchip: add compatible string for rv1108 spi ARM: dts: rockchip: add spi dt node for rv1108 dt-bindings: pwm: add description for rv1108 pwm ARM: dts: rockchip: add pwm dt node for rv1108 ARM: dts: rockchip: add saradc support for rv1108 ARM: dts: rockchip: add pwm backlight for rv1108 evb ARM: dts: rockchip: add pmic rk805 dt node for rv1108 evb ARM: dts: rockchip: add accelerometer bma250e dt node for rv1108 evb .../devicetree/bindings/pwm/pwm-rockchip.txt | 3 +- .../devicetree/bindings/spi/spi-rockchip.txt | 1 + arch/arm/boot/dts/rv1108-evb.dts | 158 +++ arch/arm/boot/dts/rv1108.dtsi | 167 + drivers/spi/spi-rockchip.c | 1 + 5 files changed, 329 insertions(+), 1 deletion(-) -- 2.7.4
Re: [PATCH v3 10/13] ARM: dts: rockchip: add saradc support for rv1108
Hi Heiko:
On 2017年08月13日 20:13, Heiko Stuebner wrote:
Hi Andy,
Am Freitag, 11. August 2017, 11:46:51 CEST schrieb Andy Yan:
Add saradc device tree node for rv1108 soc
Signed-off-by: Andy Yan <andy@rock-chips.com>
+ adc: adc@1038c000 {
+ compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
+ reg = <0x1038c000 0x100>;
+ interrupts = ;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
What do you need the io-channel-ranges for?
I.e. according to the documenation it is meant for when the adc is also
a "bus node" and has children that should inherit channels from it.
In all saradc uses so far we only have separate nodes referencing the
adc controller (like adc-keys etc), so this does not look like it is needed?
Sorry, I just copied it from the downstream dts. After checked with
David, he suggested that we could remove it.
Heiko
Re: [PATCH v3 10/13] ARM: dts: rockchip: add saradc support for rv1108
Hi Heiko:
On 2017年08月13日 20:13, Heiko Stuebner wrote:
Hi Andy,
Am Freitag, 11. August 2017, 11:46:51 CEST schrieb Andy Yan:
Add saradc device tree node for rv1108 soc
Signed-off-by: Andy Yan
+ adc: adc@1038c000 {
+ compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
+ reg = <0x1038c000 0x100>;
+ interrupts = ;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
What do you need the io-channel-ranges for?
I.e. according to the documenation it is meant for when the adc is also
a "bus node" and has children that should inherit channels from it.
In all saradc uses so far we only have separate nodes referencing the
adc controller (like adc-keys etc), so this does not look like it is needed?
Sorry, I just copied it from the downstream dts. After checked with
David, he suggested that we could remove it.
Heiko
[PATCH v3 13/13] ARM: dts: rockchip: add accelerometer bma250e dt node for rv1108 evb
Add dt node of bosch accelerometer bma250e on rv1108 evb.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index a1bd95e..6690083 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -110,6 +110,13 @@
i2c-scl-falling-time-ns = <16>;
clock-frequency = <40>;
+ bma250: accelerometer@19 {
+ compatible = "bosch,bma250e";
+ reg = <0x19>;
+ interrupt-parent = <>;
+ interrupts = ;
+ };
+
rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
--
2.7.4
[PATCH v3 13/13] ARM: dts: rockchip: add accelerometer bma250e dt node for rv1108 evb
Add dt node of bosch accelerometer bma250e on rv1108 evb.
Signed-off-by: Andy Yan
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index a1bd95e..6690083 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -110,6 +110,13 @@
i2c-scl-falling-time-ns = <16>;
clock-frequency = <40>;
+ bma250: accelerometer@19 {
+ compatible = "bosch,bma250e";
+ reg = <0x19>;
+ interrupt-parent = <>;
+ interrupts = ;
+ };
+
rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
--
2.7.4
[PATCH v3 12/13] ARM: dts: rockchip: add pmic rk805 dt node for rv1108 evb
RK805 is used as the voltage regulator on rv1108 evaluation
board. Add device tree node for it.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 108 +++
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 77ce707..a1bd95e 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -94,6 +94,114 @@
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
};
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-boot-on;
+ };
+};
+
+ {
+ status = "okay";
+ i2c-scl-rising-time-ns = <275>;
+ i2c-scl-falling-time-ns = <16>;
+ clock-frequency = <40>;
+
+ rk805: pmic@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <>;
+ interrupts = ;
+ rockchip,system-power-controller;
+
+ vcc1-supply = <_sys>;
+ vcc2-supply = <_sys>;
+ vcc3-supply = <_sys>;
+ vcc4-supply = <_sys>;
+ vcc5-supply = <_sys>;
+ vcc6-supply = <_sys>;
+
+ regulators {
+ vdd_core: DCDC_REG1 {
+ regulator-name= "vdd_core";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <150>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ regulator-state-uv = <90>;
+ };
+ };
+
+ vdd_cam: DCDC_REG2 {
+ regulator-name= "vdd_cam";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <200>;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name= "vcc_ddr";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name= "vcc_io";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ regulator-state-uv = <330>;
+ };
+ };
+
+ vdd_10: LDO_REG1 {
+ regulator-name= "vdd_10";
+ regulator-min-microvolt = <100>;
+ regulator-max-microvolt = <100>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vcc_18: LDO_REG2 {
+ regulator-name= "vcc_18";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vdd10_pmu: LDO_REG3 {
+ r
[PATCH v3 12/13] ARM: dts: rockchip: add pmic rk805 dt node for rv1108 evb
RK805 is used as the voltage regulator on rv1108 evaluation
board. Add device tree node for it.
Signed-off-by: Andy Yan
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 108 +++
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 77ce707..a1bd95e 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -94,6 +94,114 @@
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
};
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-boot-on;
+ };
+};
+
+ {
+ status = "okay";
+ i2c-scl-rising-time-ns = <275>;
+ i2c-scl-falling-time-ns = <16>;
+ clock-frequency = <40>;
+
+ rk805: pmic@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ interrupt-parent = <>;
+ interrupts = ;
+ rockchip,system-power-controller;
+
+ vcc1-supply = <_sys>;
+ vcc2-supply = <_sys>;
+ vcc3-supply = <_sys>;
+ vcc4-supply = <_sys>;
+ vcc5-supply = <_sys>;
+ vcc6-supply = <_sys>;
+
+ regulators {
+ vdd_core: DCDC_REG1 {
+ regulator-name= "vdd_core";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <150>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ regulator-state-uv = <90>;
+ };
+ };
+
+ vdd_cam: DCDC_REG2 {
+ regulator-name= "vdd_cam";
+ regulator-min-microvolt = <70>;
+ regulator-max-microvolt = <200>;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name= "vcc_ddr";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name= "vcc_io";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-enabled;
+ regulator-state-uv = <330>;
+ };
+ };
+
+ vdd_10: LDO_REG1 {
+ regulator-name= "vdd_10";
+ regulator-min-microvolt = <100>;
+ regulator-max-microvolt = <100>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vcc_18: LDO_REG2 {
+ regulator-name= "vcc_18";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-state-disabled;
+ };
+ };
+
+ vdd10_pmu: LDO_REG3 {
+ regulator-name= "vdd10_pmu";
+
[PATCH v3 11/13] ARM: dts: rockchip: add pwm backlight for rv1108 evb
RV1108 EVB uses pwm0 modulate the backlight, add dt
node to enable it.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 43
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 44feea7..77ce707 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -55,6 +55,49 @@
stdout-path = "serial2:150n8";
bootargs = "root=/dev/mtdblock2
mtdparts=spi-nor:256k@0(u-boot)ro,6m(kernel)ro,9m(rootfs),-(freedisk)";
};
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = < 0 25000 0>;
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+16 17 18 19 20 21 22 23
+24 25 26 27 28 29 30 31
+32 33 34 35 36 37 38 39
+40 41 42 43 44 45 46 47
+48 49 50 51 52 53 54 55
+56 57 58 59 60 61 62 63
+64 65 66 67 68 69 70 71
+72 73 74 75 76 77 78 79
+80 81 82 83 84 85 86 87
+88 89 90 91 92 93 94 95
+96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255>;
+ default-brightness-level = <200>;
+ };
+};
+
+ {
+ status = "okay";
};
{
--
2.7.4
[PATCH v3 11/13] ARM: dts: rockchip: add pwm backlight for rv1108 evb
RV1108 EVB uses pwm0 modulate the backlight, add dt
node to enable it.
Signed-off-by: Andy Yan
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 43
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 44feea7..77ce707 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -55,6 +55,49 @@
stdout-path = "serial2:150n8";
bootargs = "root=/dev/mtdblock2
mtdparts=spi-nor:256k@0(u-boot)ro,6m(kernel)ro,9m(rootfs),-(freedisk)";
};
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = < 0 25000 0>;
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+16 17 18 19 20 21 22 23
+24 25 26 27 28 29 30 31
+32 33 34 35 36 37 38 39
+40 41 42 43 44 45 46 47
+48 49 50 51 52 53 54 55
+56 57 58 59 60 61 62 63
+64 65 66 67 68 69 70 71
+72 73 74 75 76 77 78 79
+80 81 82 83 84 85 86 87
+88 89 90 91 92 93 94 95
+96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255>;
+ default-brightness-level = <200>;
+ };
+};
+
+ {
+ status = "okay";
};
{
--
2.7.4
[PATCH v3 10/13] ARM: dts: rockchip: add saradc support for rv1108
Add saradc device tree node for rv1108 soc
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v3: None
Changes in v2:
- add compatible string "rockchip,rv1108-saradc"
arch/arm/boot/dts/rv1108.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 75a0b1e..92b6005 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -275,6 +275,18 @@
status = "disabled";
};
+ adc: adc@1038c000 {
+ compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
+ reg = <0x1038c000 0x100>;
+ interrupts = ;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ clock-frequency = <100>;
+ clocks = < SCLK_SARADC>, < PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ status = "disabled";
+ };
+
i2c0: i2c@2000 {
compatible = "rockchip,rv1108-i2c";
reg = <0x2000 0x1000>;
--
2.7.4
[PATCH v3 10/13] ARM: dts: rockchip: add saradc support for rv1108
Add saradc device tree node for rv1108 soc
Signed-off-by: Andy Yan
---
Changes in v3: None
Changes in v2:
- add compatible string "rockchip,rv1108-saradc"
arch/arm/boot/dts/rv1108.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 75a0b1e..92b6005 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -275,6 +275,18 @@
status = "disabled";
};
+ adc: adc@1038c000 {
+ compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
+ reg = <0x1038c000 0x100>;
+ interrupts = ;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ clock-frequency = <100>;
+ clocks = < SCLK_SARADC>, < PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ status = "disabled";
+ };
+
i2c0: i2c@2000 {
compatible = "rockchip,rv1108-i2c";
reg = <0x2000 0x1000>;
--
2.7.4
[PATCH v3 09/13] dt-bindings: adc: add description for rv1108 saradc
Add device tree bindings document for saradc on rockchip rv1108 soc. Signed-off-by: Andy Yan <andy@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt index e0a9b9d..c2c50b5 100644 --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt @@ -6,6 +6,7 @@ Required properties: - "rockchip,rk3066-tsadc": for rk3036 - "rockchip,rk3328-saradc", "rockchip,rk3399-saradc": for rk3328 - "rockchip,rk3399-saradc": for rk3399 + - "rockchip,rv1108-saradc", "rockchip,rk3399-saradc": for rv1108 - reg: physical base address of the controller and length of memory mapped region. -- 2.7.4
[PATCH v3 09/13] dt-bindings: adc: add description for rv1108 saradc
Add device tree bindings document for saradc on rockchip rv1108 soc. Signed-off-by: Andy Yan Acked-by: Rob Herring --- Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt index e0a9b9d..c2c50b5 100644 --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt @@ -6,6 +6,7 @@ Required properties: - "rockchip,rk3066-tsadc": for rk3036 - "rockchip,rk3328-saradc", "rockchip,rk3399-saradc": for rk3328 - "rockchip,rk3399-saradc": for rk3399 + - "rockchip,rv1108-saradc", "rockchip,rk3399-saradc": for rv1108 - reg: physical base address of the controller and length of memory mapped region. -- 2.7.4
[PATCH v3 08/13] ARM: dts: rockchip: add watchdog dt node for rv1108
Add watchdog device tree node for rv1108
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 76a325a..75a0b1e 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -266,6 +266,15 @@
reg = <0x1030 0x1000>;
};
+ watchdog: wdt@1036 {
+ compatible = "snps,dw-wdt";
+ reg = <0x1036 0x100>;
+ clocks = < PCLK_WDT>;
+ clock-names = "pclk_wdt";
+ interrupts = ;
+ status = "disabled";
+ };
+
i2c0: i2c@2000 {
compatible = "rockchip,rv1108-i2c";
reg = <0x2000 0x1000>;
--
2.7.4
[PATCH v3 08/13] ARM: dts: rockchip: add watchdog dt node for rv1108
Add watchdog device tree node for rv1108
Signed-off-by: Andy Yan
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 76a325a..75a0b1e 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -266,6 +266,15 @@
reg = <0x1030 0x1000>;
};
+ watchdog: wdt@1036 {
+ compatible = "snps,dw-wdt";
+ reg = <0x1036 0x100>;
+ clocks = < PCLK_WDT>;
+ clock-names = "pclk_wdt";
+ interrupts = ;
+ status = "disabled";
+ };
+
i2c0: i2c@2000 {
compatible = "rockchip,rv1108-i2c";
reg = <0x2000 0x1000>;
--
2.7.4
[PATCH v3 07/13] ARM: dts: rockchip: add pwm dt node for rv1108
Add pwm device tree node for rv1108 soc
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v3: None
Changes in v2:
- add compatible string "rockchip,rv1108-pwm"
arch/arm/boot/dts/rv1108.dtsi | 143 ++
1 file changed, 143 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index b688f4a..76a325a 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -213,6 +213,54 @@
status = "disabled";
};
+ pwm4: pwm@1028 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x1028 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm5: pwm@10280010 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280010 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm6: pwm@10280020 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280020 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm7: pwm@10280030 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280030 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
grf: syscon@1030 {
compatible = "rockchip,rv1108-grf", "syscon";
reg = <0x1030 0x1000>;
@@ -232,6 +280,53 @@
status = "disabled";
};
+ pwm0: pwm@2004 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x2004 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm1: pwm@20040010 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040010 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm2: pwm@20040020 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040020 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm3: pwm@20040030 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040030 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+
[PATCH v3 07/13] ARM: dts: rockchip: add pwm dt node for rv1108
Add pwm device tree node for rv1108 soc
Signed-off-by: Andy Yan
---
Changes in v3: None
Changes in v2:
- add compatible string "rockchip,rv1108-pwm"
arch/arm/boot/dts/rv1108.dtsi | 143 ++
1 file changed, 143 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index b688f4a..76a325a 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -213,6 +213,54 @@
status = "disabled";
};
+ pwm4: pwm@1028 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x1028 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm5: pwm@10280010 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280010 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm6: pwm@10280020 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280020 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm7: pwm@10280030 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x10280030 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM>, < PCLK_PWM>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
grf: syscon@1030 {
compatible = "rockchip,rv1108-grf", "syscon";
reg = <0x1030 0x1000>;
@@ -232,6 +280,53 @@
status = "disabled";
};
+ pwm0: pwm@2004 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x2004 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm1: pwm@20040010 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040010 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm2: pwm@20040020 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040020 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm3: pwm@20040030 {
+ compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
+ reg = <0x20040030 0x10>;
+ interrupts = ;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin>;
+ clocks = < SCLK_PWM0_PMU>, < PCLK_PWM0_PMU>;
+ clock-names = "pwm", "pclk";
+ status = "disab
[PATCH v3 06/13] dt-bindings: pwm: add description for rv1108 pwm
Add device tree bindings document for pwm on rockchip rv1108 soc. Signed-off-by: Andy Yan <andy@rock-chips.com> --- Changes in v3: - make the compatible string be: "rockchip,rv1108-pwm", "rockchip,rk3288-pwm" for rv1108 Changes in v2: None Documentation/devicetree/bindings/pwm/pwm-rockchip.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt index 2350ef9..2c5e52a 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt @@ -3,7 +3,8 @@ Rockchip PWM controller Required properties: - compatible: should be "rockchip,-pwm" "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs - "rockchip,rk3288-pwm": found on RK3288 SoC + "rockchip,rk3288-pwm": found on RK3288 SOC + "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC - reg: physical base address and length of the controller's registers - clocks: See ../clock/clock-bindings.txt -- 2.7.4
[PATCH v3 06/13] dt-bindings: pwm: add description for rv1108 pwm
Add device tree bindings document for pwm on rockchip rv1108 soc. Signed-off-by: Andy Yan --- Changes in v3: - make the compatible string be: "rockchip,rv1108-pwm", "rockchip,rk3288-pwm" for rv1108 Changes in v2: None Documentation/devicetree/bindings/pwm/pwm-rockchip.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt index 2350ef9..2c5e52a 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt @@ -3,7 +3,8 @@ Rockchip PWM controller Required properties: - compatible: should be "rockchip,-pwm" "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs - "rockchip,rk3288-pwm": found on RK3288 SoC + "rockchip,rk3288-pwm": found on RK3288 SOC + "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC - reg: physical base address and length of the controller's registers - clocks: See ../clock/clock-bindings.txt -- 2.7.4
[PATCH v3 05/13] ARM: dts: rockchip: add spi dt node for rv1108
Add SPI device tree node for rv1108.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 663f2f2..b688f4a 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -200,6 +200,19 @@
status = "disabled";
};
+ spi: spi@1027 {
+ compatible = "rockchip,rv1108-spi";
+ reg = <0x1027 0x1000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_SPI>, < PCLK_SPI>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = < 8>, < 9>;
+ #dma-cells = <2>;
+ status = "disabled";
+ };
+
grf: syscon@1030 {
compatible = "rockchip,rv1108-grf", "syscon";
reg = <0x1030 0x1000>;
--
2.7.4
[PATCH v3 05/13] ARM: dts: rockchip: add spi dt node for rv1108
Add SPI device tree node for rv1108.
Signed-off-by: Andy Yan
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 663f2f2..b688f4a 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -200,6 +200,19 @@
status = "disabled";
};
+ spi: spi@1027 {
+ compatible = "rockchip,rv1108-spi";
+ reg = <0x1027 0x1000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_SPI>, < PCLK_SPI>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = < 8>, < 9>;
+ #dma-cells = <2>;
+ status = "disabled";
+ };
+
grf: syscon@1030 {
compatible = "rockchip,rv1108-grf", "syscon";
reg = <0x1030 0x1000>;
--
2.7.4
[PATCH v3 05/13] ARM: dts: rockchip: add spi dt node for rv1108
Add SPI device tree node for rv1108.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 663f2f2..b688f4a 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -200,6 +200,19 @@
status = "disabled";
};
+ spi: spi@1027 {
+ compatible = "rockchip,rv1108-spi";
+ reg = <0x1027 0x1000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_SPI>, < PCLK_SPI>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = < 8>, < 9>;
+ #dma-cells = <2>;
+ status = "disabled";
+ };
+
grf: syscon@1030 {
compatible = "rockchip,rv1108-grf", "syscon";
reg = <0x1030 0x1000>;
--
2.7.4
[PATCH v3 05/13] ARM: dts: rockchip: add spi dt node for rv1108
Add SPI device tree node for rv1108.
Signed-off-by: Andy Yan
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 663f2f2..b688f4a 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -200,6 +200,19 @@
status = "disabled";
};
+ spi: spi@1027 {
+ compatible = "rockchip,rv1108-spi";
+ reg = <0x1027 0x1000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_SPI>, < PCLK_SPI>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = < 8>, < 9>;
+ #dma-cells = <2>;
+ status = "disabled";
+ };
+
grf: syscon@1030 {
compatible = "rockchip,rv1108-grf", "syscon";
reg = <0x1030 0x1000>;
--
2.7.4
[PATCH v3 04/13] spi: rockchip: add compatible string for rv1108 spi
The spi on rv1108 is the same as other rockchip based
socs, add compatible string for it.
Signed-off-by: Andy Yan <andy@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v3: None
Changes in v2: None
Documentation/devicetree/bindings/spi/spi-rockchip.txt | 1 +
drivers/spi/spi-rockchip.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
index 83da493..6e3ffac 100644
--- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
@@ -6,6 +6,7 @@ and display controllers using the SPI communication interface.
Required Properties:
- compatible: should be one of the following.
+"rockchip,rv1108-spi" for rv1108 SoCs.
"rockchip,rk3036-spi" for rk3036 SoCS.
"rockchip,rk3066-spi" for rk3066 SoCs.
"rockchip,rk3188-spi" for rk3188 SoCs.
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 0b4a52b..27b4db2 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -919,6 +919,7 @@ static const struct dev_pm_ops rockchip_spi_pm = {
};
static const struct of_device_id rockchip_spi_dt_match[] = {
+ { .compatible = "rockchip,rv1108-spi", },
{ .compatible = "rockchip,rk3036-spi", },
{ .compatible = "rockchip,rk3066-spi", },
{ .compatible = "rockchip,rk3188-spi", },
--
2.7.4
[PATCH v3 04/13] spi: rockchip: add compatible string for rv1108 spi
The spi on rv1108 is the same as other rockchip based
socs, add compatible string for it.
Signed-off-by: Andy Yan
Acked-by: Rob Herring
---
Changes in v3: None
Changes in v2: None
Documentation/devicetree/bindings/spi/spi-rockchip.txt | 1 +
drivers/spi/spi-rockchip.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
index 83da493..6e3ffac 100644
--- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
@@ -6,6 +6,7 @@ and display controllers using the SPI communication interface.
Required Properties:
- compatible: should be one of the following.
+"rockchip,rv1108-spi" for rv1108 SoCs.
"rockchip,rk3036-spi" for rk3036 SoCS.
"rockchip,rk3066-spi" for rk3066 SoCs.
"rockchip,rk3188-spi" for rk3188 SoCs.
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 0b4a52b..27b4db2 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -919,6 +919,7 @@ static const struct dev_pm_ops rockchip_spi_pm = {
};
static const struct of_device_id rockchip_spi_dt_match[] = {
+ { .compatible = "rockchip,rv1108-spi", },
{ .compatible = "rockchip,rk3036-spi", },
{ .compatible = "rockchip,rk3066-spi", },
{ .compatible = "rockchip,rk3188-spi", },
--
2.7.4
[PATCH v3 03/13] ARM: dts: rockchip: add i2c dt node for rv1108
There are four i2c controllers on rv1108, add
device tree node for them.
Signed-off-by: Andy Yan <andy@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108.dtsi | 72 +++
1 file changed, 72 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 8377eb9..663f2f2 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -52,6 +52,10 @@
interrupt-parent = <>;
aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
serial0 =
serial1 =
serial2 =
@@ -154,11 +158,67 @@
status = "disabled";
};
+ i2c1: i2c@1024 {
+ compatible = "rockchip,rv1108-i2c";
+ reg = <0x1024 0x1000>;
+ interrupts = ;
+ rockchip,grf = <>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_I2C1>, < PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <_xfer>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@1025 {
+ compatible = "rockchip,rv1108-i2c";
+ reg = <0x1025 0x1000>;
+ interrupts = ;
+ rockchip,grf = <>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_I2C2>, < PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <_xfer>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@1026 {
+ compatible = "rockchip,rv1108-i2c";
+ reg = <0x1026 0x1000>;
+ interrupts = ;
+ rockchip,grf = <>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_I2C3>, < PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <_xfer>;
+ status = "disabled";
+ };
+
grf: syscon@1030 {
compatible = "rockchip,rv1108-grf", "syscon";
reg = <0x1030 0x1000>;
};
+ i2c0: i2c@2000 {
+ compatible = "rockchip,rv1108-i2c";
+ reg = <0x2000 0x1000>;
+ interrupts = ;
+ rockchip,grf = <>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_I2C0_PMU>, < PCLK_I2C0_PMU>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <_xfer>;
+ status = "disabled";
+ };
+
pmugrf: syscon@2006 {
compatible = "rockchip,rv1108-pmugrf", "syscon";
reg = <0x2006 0x1000>;
@@ -343,6 +403,18 @@
input-enable;
};
+ pcfg_pull_none_smt: pcfg-pull-none-smt {
+ bias-disable;
+ input-schmitt-enable;
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_1
_pull_none_smt>,
+ <0 RK_PB2 RK_FUNC_1
_pull_none_smt>;
+ };
+ };
+
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <2 RK_PD3 RK_FUNC_1
_pull_up>,
--
2.7.4
[PATCH v3 03/13] ARM: dts: rockchip: add i2c dt node for rv1108
There are four i2c controllers on rv1108, add
device tree node for them.
Signed-off-by: Andy Yan
---
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108.dtsi | 72 +++
1 file changed, 72 insertions(+)
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 8377eb9..663f2f2 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -52,6 +52,10 @@
interrupt-parent = <>;
aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
serial0 =
serial1 =
serial2 =
@@ -154,11 +158,67 @@
status = "disabled";
};
+ i2c1: i2c@1024 {
+ compatible = "rockchip,rv1108-i2c";
+ reg = <0x1024 0x1000>;
+ interrupts = ;
+ rockchip,grf = <>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_I2C1>, < PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <_xfer>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@1025 {
+ compatible = "rockchip,rv1108-i2c";
+ reg = <0x1025 0x1000>;
+ interrupts = ;
+ rockchip,grf = <>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_I2C2>, < PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <_xfer>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@1026 {
+ compatible = "rockchip,rv1108-i2c";
+ reg = <0x1026 0x1000>;
+ interrupts = ;
+ rockchip,grf = <>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_I2C3>, < PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <_xfer>;
+ status = "disabled";
+ };
+
grf: syscon@1030 {
compatible = "rockchip,rv1108-grf", "syscon";
reg = <0x1030 0x1000>;
};
+ i2c0: i2c@2000 {
+ compatible = "rockchip,rv1108-i2c";
+ reg = <0x2000 0x1000>;
+ interrupts = ;
+ rockchip,grf = <>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < SCLK_I2C0_PMU>, < PCLK_I2C0_PMU>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <_xfer>;
+ status = "disabled";
+ };
+
pmugrf: syscon@2006 {
compatible = "rockchip,rv1108-pmugrf", "syscon";
reg = <0x2006 0x1000>;
@@ -343,6 +403,18 @@
input-enable;
};
+ pcfg_pull_none_smt: pcfg-pull-none-smt {
+ bias-disable;
+ input-schmitt-enable;
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_1
_pull_none_smt>,
+ <0 RK_PB2 RK_FUNC_1
_pull_none_smt>;
+ };
+ };
+
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <2 RK_PD3 RK_FUNC_1
_pull_up>,
--
2.7.4
[PATCH v3 02/13] i2c: rk3x: add support for rv1108
Support for the i2c controller on rv1108 soc.
Signed-off-by: Andy Yan <andy@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v3: None
Changes in v2: None
drivers/i2c/busses/i2c-rk3x.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index df22066..fe23457 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -1131,6 +1131,11 @@ static const struct i2c_algorithm rk3x_i2c_algorithm = {
.functionality = rk3x_i2c_func,
};
+static const struct rk3x_i2c_soc_data rv1108_soc_data = {
+ .grf_offset = -1,
+ .calc_timings = rk3x_i2c_v1_calc_timings,
+};
+
static const struct rk3x_i2c_soc_data rk3066_soc_data = {
.grf_offset = 0x154,
.calc_timings = rk3x_i2c_v0_calc_timings,
@@ -1158,6 +1163,10 @@ static const struct rk3x_i2c_soc_data rk3399_soc_data = {
static const struct of_device_id rk3x_i2c_match[] = {
{
+ .compatible = "rockchip,rv1108-i2c",
+ .data = (void *)_soc_data
+ },
+ {
.compatible = "rockchip,rk3066-i2c",
.data = (void *)_soc_data
},
--
2.7.4
[PATCH v3 02/13] i2c: rk3x: add support for rv1108
Support for the i2c controller on rv1108 soc.
Signed-off-by: Andy Yan
Reviewed-by: Heiko Stuebner
---
Changes in v3: None
Changes in v2: None
drivers/i2c/busses/i2c-rk3x.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index df22066..fe23457 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -1131,6 +1131,11 @@ static const struct i2c_algorithm rk3x_i2c_algorithm = {
.functionality = rk3x_i2c_func,
};
+static const struct rk3x_i2c_soc_data rv1108_soc_data = {
+ .grf_offset = -1,
+ .calc_timings = rk3x_i2c_v1_calc_timings,
+};
+
static const struct rk3x_i2c_soc_data rk3066_soc_data = {
.grf_offset = 0x154,
.calc_timings = rk3x_i2c_v0_calc_timings,
@@ -1158,6 +1163,10 @@ static const struct rk3x_i2c_soc_data rk3399_soc_data = {
static const struct of_device_id rk3x_i2c_match[] = {
{
+ .compatible = "rockchip,rv1108-i2c",
+ .data = (void *)_soc_data
+ },
+ {
.compatible = "rockchip,rk3066-i2c",
.data = (void *)_soc_data
},
--
2.7.4
[PATCH v3 01/13] dt-bindings: i2c: rk3x: add support for rv1108
Add dt Document for i2c controller on rv1108 Signed-off-by: Andy Yan <andy@rock-chips.com> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/i2c/i2c-rk3x.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt b/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt index e18445d..22f2eeb 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt @@ -7,6 +7,7 @@ Required properties : - reg : Offset and length of the register set for the device - compatible: should be one of the following: + - "rockchip,rv1108-i2c": for rv1108 - "rockchip,rk3066-i2c": for rk3066 - "rockchip,rk3188-i2c": for rk3188 - "rockchip,rk3228-i2c": for rk3228 -- 2.7.4
[PATCH v3 01/13] dt-bindings: i2c: rk3x: add support for rv1108
Add dt Document for i2c controller on rv1108 Signed-off-by: Andy Yan Acked-by: Rob Herring --- Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/i2c/i2c-rk3x.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt b/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt index e18445d..22f2eeb 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt @@ -7,6 +7,7 @@ Required properties : - reg : Offset and length of the register set for the device - compatible: should be one of the following: + - "rockchip,rv1108-i2c": for rv1108 - "rockchip,rk3066-i2c": for rk3066 - "rockchip,rk3188-i2c": for rk3188 - "rockchip,rk3228-i2c": for rk3228 -- 2.7.4
[PATCH v3 00/13] Support more devices on rockchip rv1108
This series try to support i2c/spi/pwm/saradc/pmic/watchdog on rockchip rv1108 soc. As the clk tree part has been taken from Elaine's series, so this part will be not included in my series from this version. This version has no more changes, except the pwm dt-bindings followed by Rob's suggestion, and the Acked-by from Rob of other dt-bindings. Changes in v3: - remove the clk tree part - make the compatible string be: "rockchip,rv1108-pwm", "rockchip,rk3288-pwm" for rv1108 pwm Changes in v2: - add compatible string "rockchip,rv1108-pwm" - add compatible string "rockchip,rv1108-saradc" Andy Yan (13): dt-bindings: i2c: rk3x: add support for rv1108 i2c: rk3x: add support for rv1108 ARM: dts: rockchip: add i2c dt node for rv1108 spi: rockchip: add compatible string for rv1108 spi ARM: dts: rockchip: add spi dt node for rv1108 dt-bindings: pwm: add description for rv1108 pwm ARM: dts: rockchip: add pwm dt node for rv1108 ARM: dts: rockchip: add watchdog dt node for rv1108 dt-bindings: adc: add description for rv1108 saradc ARM: dts: rockchip: add saradc support for rv1108 ARM: dts: rockchip: add pwm backlight for rv1108 evb ARM: dts: rockchip: add pmic rk805 dt node for rv1108 evb ARM: dts: rockchip: add accelerometer bma250e dt node for rv1108 evb Documentation/devicetree/bindings/i2c/i2c-rk3x.txt | 1 + .../bindings/iio/adc/rockchip-saradc.txt | 1 + .../devicetree/bindings/pwm/pwm-rockchip.txt | 3 +- .../devicetree/bindings/spi/spi-rockchip.txt | 1 + arch/arm/boot/dts/rv1108-evb.dts | 158 + arch/arm/boot/dts/rv1108.dtsi | 249 + drivers/i2c/busses/i2c-rk3x.c | 9 + drivers/spi/spi-rockchip.c | 1 + 8 files changed, 422 insertions(+), 1 deletion(-) -- 2.7.4
