[PATCH 2/3] clocksource: imx-sysctr: Add of_clk skip option
From: Anson Huang
On some i.MX8M platforms, clock driver uses platform driver
model and it is NOT ready during timer initialization phase,
the clock operations will fail and system counter driver will
fail too. As all the i.MX8M platforms' system counter clock
are from OSC which is always enabled, so it is no need to enable
clock for system counter driver, the ONLY thing is to pass
clock frequence to driver.
This patch adds an option of skipping of_clk operation for
system counter driver, an optional property "clock-frequency"
is introduced to pass the frequency value to system counter
driver and indicate driver to skip of_clk operations.
Signed-off-by: Anson Huang
---
drivers/clocksource/timer-imx-sysctr.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clocksource/timer-imx-sysctr.c
b/drivers/clocksource/timer-imx-sysctr.c
index fd7d680..8ff3d7e 100644
--- a/drivers/clocksource/timer-imx-sysctr.c
+++ b/drivers/clocksource/timer-imx-sysctr.c
@@ -129,6 +129,14 @@ static void __init sysctr_clockevent_init(void)
static int __init sysctr_timer_init(struct device_node *np)
{
int ret = 0;
+ u32 rate;
+
+ if (!of_property_read_u32(np, "clock-frequency",
+ )) {
+ to_sysctr.of_clk.rate = rate;
+ to_sysctr.of_clk.period = DIV_ROUND_UP(rate, HZ);
+ to_sysctr.flags &= ~TIMER_OF_CLOCK;
+ }
ret = timer_of_init(np, _sysctr);
if (ret)
--
2.7.4
[PATCH 1/3] clocksource/drivers/sysctr: Add an optional property
From: Anson Huang
This patch adds an optional property "clock-frequency" to pass
the system counter frequency value to kernel system counter
driver and indicate the driver to skip of_clk operations, this
is to support those platforms using platform driver model for
clock driver.
Signed-off-by: Anson Huang
---
Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
index d576599..c9907a0 100644
--- a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
+++ b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
@@ -14,6 +14,11 @@ Required properties:
- clocks : Specifies the counter clock.
- clock-names: Specifies the clock's name of this module
+Optional properties:
+
+- clock-frequency : Specifies system counter clock frequency and indicates
system
+ counter driver to skip clock operations.
+
Example:
system_counter: timer@306a {
@@ -22,4 +27,5 @@ Example:
clocks = <_8m>;
clock-names = "per";
interrupts = ;
+ clock-frequency = <833>;
};
--
2.7.4
[PATCH 2/4] dt-bindings: clock: imx8mm: Add system counter clock
From: Anson Huang Add i.MX8MM system counter clock macro definition. Signed-off-by: Anson Huang --- include/dt-bindings/clock/imx8mm-clock.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index 07e6c68..a8c2124 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -248,6 +248,8 @@ #define IMX8MM_CLK_SNVS_ROOT 228 #define IMX8MM_CLK_GIC 229 -#define IMX8MM_CLK_END 230 +#define IMX8MM_CLK_SYS_CTR 230 + +#define IMX8MM_CLK_END 231 #endif -- 2.7.4
[PATCH 3/4] clk: imx8mm: Add system counter to clock tree
From: Anson Huang
i.MX8MM timer-imx-sysctr driver needs system counter clock
for proper function, add it into clock tree.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx8mm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 43fa9c3..56d53dd 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -645,6 +645,8 @@ static int __init imx8mm_clocks_init(struct device_node
*ccm_node)
clks[IMX8MM_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root",
"dram_alt", 1, 4);
clks[IMX8MM_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base +
0x9800, 24, 1, imx8mm_dram_core_sels, ARRAY_SIZE(imx8mm_dram_core_sels),
CLK_IS_CRITICAL);
+ clks[IMX8MM_CLK_SYS_CTR] = imx_clk_fixed_factor("sys_ctr", "osc_24m",
1, 3);
+
clks[IMX8MM_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div",
clks[IMX8MM_CLK_A53_DIV],
clks[IMX8MM_CLK_A53_SRC],
--
2.7.4
[PATCH 1/4] arm64: Enable TIMER_IMX_SYS_CTR for ARCH_MXC platforms
From: Anson Huang ARCH_MXC platforms needs system counter as broadcast timer to support cpuidle, enable it by default. Signed-off-by: Anson Huang --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 4778c77..f5e623f 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -173,6 +173,7 @@ config ARCH_MXC select PM select PM_GENERIC_DOMAINS select SOC_BUS + select TIMER_IMX_SYS_CTR help This enables support for the ARMv8 based SoCs in the NXP i.MX family. -- 2.7.4
[PATCH 4/4] arm64: dts: imx8mm: Add system counter node
From: Anson Huang
Add i.MX8MM system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 232a741..f606efa 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -510,6 +510,15 @@
#pwm-cells = <2>;
status = "disabled";
};
+
+ system_counter: timer@306a {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x306a 0x3>;
+ interrupts = ,
+;
+ clocks = < IMX8MM_CLK_SYS_CTR>;
+ clock-names = "per";
+ };
};
aips3: bus@3080 {
--
2.7.4
[PATCH] arm64: defconfig: Enable CONFIG_KEYBOARD_SNVS_PWRKEY as module
From: Anson Huang Enable CONFIG_KEYBOARD_SNVS_PWRKEY as module to support i.MX8M series SoCs' power key. Signed-off-by: Anson Huang --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 29f7768..3c17f6e 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -291,6 +291,7 @@ CONFIG_WLCORE_SDIO=m CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_ADC=m CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_SNVS_PWRKEY=m CONFIG_KEYBOARD_CROS_EC=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=m -- 2.7.4
[PATCH 1/2] clk: imx: Remove __init for imx_register_uart_clocks() API
From: Anson Huang
Some of i.MX SoCs' clock driver use platform driver model,
and they need to call imx_register_uart_clocks() API, so
imx_register_uart_clocks() API should NOT be in .init section.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index f241189..76457b2 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -123,8 +123,8 @@ void imx_cscmr1_fixup(u32 *val)
return;
}
-static int imx_keep_uart_clocks __initdata;
-static struct clk ** const *imx_uart_clocks __initdata;
+static int imx_keep_uart_clocks;
+static struct clk ** const *imx_uart_clocks;
static int __init imx_keep_uart_clocks_param(char *str)
{
@@ -137,7 +137,7 @@ __setup_param("earlycon", imx_keep_uart_earlycon,
__setup_param("earlyprintk", imx_keep_uart_earlyprintk,
imx_keep_uart_clocks_param, 0);
-void __init imx_register_uart_clocks(struct clk ** const clks[])
+void imx_register_uart_clocks(struct clk ** const clks[])
{
if (imx_keep_uart_clocks) {
int i;
--
2.7.4
[PATCH 2/2] clk: imx8mq: Keep uart clocks on during system boot
From: Anson Huang
Call imx_register_uart_clocks() API to keep uart clocks enabled
when earlyprintk or earlycon is active.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx8mq.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 5fbc2a7..d407a07 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -272,6 +272,14 @@ static const char * const imx8mq_clko2_sels[] =
{"osc_25m", "sys2_pll_200m", "sy
static struct clk_onecell_data clk_data;
+static struct clk ** const uart_clks[] = {
+ [IMX8MQ_CLK_UART1_ROOT],
+ [IMX8MQ_CLK_UART2_ROOT],
+ [IMX8MQ_CLK_UART3_ROOT],
+ [IMX8MQ_CLK_UART4_ROOT],
+ NULL
+};
+
static int imx8mq_clocks_probe(struct platform_device *pdev)
{
struct device *dev = >dev;
@@ -555,6 +563,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
err = of_clk_add_provider(np, of_clk_src_onecell_get, _data);
WARN_ON(err);
+ imx_register_uart_clocks(uart_clks);
+
return err;
}
--
2.7.4
[PATCH V5 3/5] clk: imx: Add API for clk unregister when driver probe fail
From: Anson Huang
For i.MX clock drivers probe fail case, clks should be unregistered
in the return path, this patch adds a common API for i.MX clock
drivers to unregister clocks when fail.
Signed-off-by: Anson Huang
---
New patch.
---
drivers/clk/imx/clk.c | 8
drivers/clk/imx/clk.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index f241189..8616967 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -13,6 +13,14 @@
DEFINE_SPINLOCK(imx_ccm_lock);
+void imx_unregister_clocks(struct clk *clks[], unsigned int count)
+{
+ unsigned int i;
+
+ for (i = 0; i < count; i++)
+ clk_unregister(clks[i]);
+}
+
void __init imx_mmdc_mask_handshake(void __iomem *ccm_base,
unsigned int chn)
{
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 19d7b8b..bb4ec1b 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -12,6 +12,7 @@ void imx_check_clk_hws(struct clk_hw *clks[], unsigned int
count);
void imx_register_uart_clocks(struct clk ** const clks[]);
void imx_register_uart_clocks_hws(struct clk_hw ** const hws[]);
void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
+void imx_unregister_clocks(struct clk *clks[], unsigned int count);
extern void imx_cscmr1_fixup(u32 *val);
--
2.7.4
[PATCH V5 4/5] clk: imx: Add support for i.MX8MN clock driver
From: Anson Huang
This patch adds i.MX8MN clock driver support.
Signed-off-by: Anson Huang
---
Changes since V4:
- use dev_err instead of pr_err;
- unregister clocks when probe failed.
---
drivers/clk/imx/Kconfig | 6 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx8mn.c | 636 +++
3 files changed, 643 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mn.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 0eaf418..1ac0c79 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -14,6 +14,12 @@ config CLK_IMX8MM
help
Build the driver for i.MX8MM CCM Clock Driver
+config CLK_IMX8MN
+ bool "IMX8MN CCM Clock Driver"
+ depends on ARCH_MXC && ARM64
+ help
+ Build the driver for i.MX8MN CCM Clock Driver
+
config CLK_IMX8MQ
bool "IMX8MQ CCM Clock Driver"
depends on ARCH_MXC && ARM64
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 05641c6..77a3d71 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_MXC_CLK_SCU) += \
clk-lpcg-scu.o
obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
+obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
new file mode 100644
index 000..07481a5
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -0,0 +1,636 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018-2019 NXP.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static u32 share_count_sai2;
+static u32 share_count_sai3;
+static u32 share_count_sai5;
+static u32 share_count_sai6;
+static u32 share_count_sai7;
+static u32 share_count_disp;
+static u32 share_count_pdm;
+static u32 share_count_nand;
+
+enum {
+ ARM_PLL,
+ GPU_PLL,
+ VPU_PLL,
+ SYS_PLL1,
+ SYS_PLL2,
+ SYS_PLL3,
+ DRAM_PLL,
+ AUDIO_PLL1,
+ AUDIO_PLL2,
+ VIDEO_PLL2,
+ NR_PLLS,
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
+ PLL_1443X_RATE(786432000U, 655, 5, 2, 23593),
+ PLL_1443X_RATE(722534400U, 301, 5, 1, 3670),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(59400U, 198, 2, 2, 0),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+};
+
+static struct imx_pll14xx_clk imx8mn_audio_pll = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_audiopll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_video_pll = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_videopll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_dram_pll = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_drampll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_arm_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_gpu_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_vpu_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_sys_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy",
"dummy", };
+static const char * const audio_pll1_bypass_sels[] = {"audio_pll1",
"audio_pll1_ref_sel", };
+static const char * const audio_pll2_bypass_sels[] = {"audio_pll2",
"audio_pll2_ref_sel", };
+static const char * const video_pll1_bypass_sels[] = {"video_pll1",
"video_pll1_ref_sel", };
+static const char * const dram_pll_bypass_sels[] = {"dram_pll",
"dram_pll_ref_sel", };
+static const char * const gpu_pll_bypass_sels[] = {"gpu_pll",
"gpu_pll_ref_sel", };
+static const char * const vpu_pll_bypass_sels[] = {"vpu_pll&quo
[PATCH V5 1/5] dt-bindings: imx: Add clock binding doc for i.MX8MN
From: Anson Huang
Add the clock binding doc for i.MX8MN.
Signed-off-by: Anson Huang
Reviewed-by: Maxime Ripard
---
No changes.
---
.../devicetree/bindings/clock/imx8mn-clock.yaml| 112 +++
include/dt-bindings/clock/imx8mn-clock.h | 215 +
2 files changed, 327 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
create mode 100644 include/dt-bindings/clock/imx8mn-clock.h
diff --git a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
new file mode 100644
index 000..454c5b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8M Nano Clock Control Module Binding
+
+maintainers:
+ - Anson Huang
+
+description: |
+ NXP i.MX8M Nano clock control module is an integrated clock controller, which
+ generates and supplies to all modules.
+
+properties:
+ compatible:
+const: fsl,imx8mn-ccm
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: 32k osc
+ - description: 24m osc
+ - description: ext1 clock input
+ - description: ext2 clock input
+ - description: ext3 clock input
+ - description: ext4 clock input
+
+ clock-names:
+items:
+ - const: osc_32k
+ - const: osc_24m
+ - const: clk_ext1
+ - const: clk_ext2
+ - const: clk_ext3
+ - const: clk_ext4
+
+ '#clock-cells':
+const: 1
+description: |
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See
include/dt-bindings/clock/imx8mn-clock.h
+ for the full list of i.MX8M Nano clock IDs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+examples:
+ # Clock Control Module node:
+ - |
+clk: clock-controller@3038 {
+compatible = "fsl,imx8mn-ccm";
+reg = <0x0 0x3038 0x0 0x1>;
+#clock-cells = <1>;
+clocks = <_32k>, <_24m>, <_ext1>,
+ <_ext2>, <_ext3>, <_ext4>;
+clock-names = "osc_32k", "osc_24m", "clk_ext1",
+ "clk_ext2", "clk_ext3", "clk_ext4";
+};
+
+ # Required external clocks for Clock Control Module node:
+ - |
+osc_32k: clock-osc-32k {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+};
+
+osc_24m: clock-osc-24m {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <2400>;
+clock-output-names = "osc_24m";
+};
+
+clk_ext1: clock-ext1 {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <13300>;
+clock-output-names = "clk_ext1";
+};
+
+clk_ext2: clock-ext2 {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <13300>;
+clock-output-names = "clk_ext2";
+};
+
+clk_ext3: clock-ext3 {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <13300>;
+clock-output-names = "clk_ext3";
+};
+
+clk_ext4: clock-ext4 {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency= <13300>;
+clock-output-names = "clk_ext4";
+};
+
+...
diff --git a/include/dt-bindings/clock/imx8mn-clock.h
b/include/dt-bindings/clock/imx8mn-clock.h
new file mode 100644
index 000..5255b1c
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
+#define __DT_BINDINGS_CLOCK_IMX8MN_H
+
+#define IMX8MN_CLK_DUMMY 0
+#define IMX8MN_CLK_32K 1
+#define IMX8MN_CLK_24M 2
+#define IMX8MN_OSC_HDMI_CLK3
+#define IMX8MN_CLK_EXT14
+#define IMX8MN_CLK_EXT25
+#define IMX8MN_CLK_EXT36
+#define IMX8MN_CLK_EXT47
+#define IMX8MN_AUDIO_PLL1_REF_SEL 8
+#define IMX8MN_AUDIO_PLL2_REF_SEL 9
+#define IMX8MN_VIDEO_PLL1_REF_SEL 10
+#define IMX8MN_DRAM_PLL_REF_SEL11
+#define IMX8MN_GPU_PLL_REF_SEL
[PATCH V5 5/5] arm64: defconfig: Select CONFIG_CLK_IMX8MN by default
From: Anson Huang Enable CONFIG_CLK_IMX8MN to support i.MX8MN clock driver. Signed-off-by: Anson Huang --- No changes. --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7a21159..29f7768 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -659,6 +659,7 @@ CONFIG_COMMON_CLK_S2MPS11=y CONFIG_CLK_QORIQ=y CONFIG_COMMON_CLK_PWM=y CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y CONFIG_CLK_IMX8MQ=y CONFIG_CLK_IMX8QXP=y CONFIG_TI_SCI_CLK=y -- 2.7.4
[PATCH V5 2/5] clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage
From: Anson Huang
1416X/1443X PLL are used on i.MX8MM and i.MX8MN and maybe
other i.MX8M series SoC later, the macro definitions of
these PLLs' initialization should be common for usage.
Signed-off-by: Anson Huang
---
No changes.
---
drivers/clk/imx/clk-imx8mm.c | 17 -
drivers/clk/imx/clk.h| 17 +
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 6b8e75d..43fa9c3 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -26,23 +26,6 @@ static u32 share_count_dcss;
static u32 share_count_pdm;
static u32 share_count_nand;
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- .kdiv = (_k), \
- }
-
static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
PLL_1416X_RATE(18U, 225, 3, 0),
PLL_1416X_RATE(16U, 200, 3, 0),
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index d94d9cb..19d7b8b 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -153,6 +153,23 @@ enum imx_pllv3_type {
struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent_name, void __iomem *base, u32 div_mask);
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
void __iomem *base);
--
2.7.4
[PATCH V4 4/4] dt-bindings: arm: imx: Add the soc binding for i.MX8MQ
From: Anson Huang This patch adds the soc & board binding for i.MX8MQ. Signed-off-by: Anson Huang Reviewed-by: Rob Herring --- No changes. --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b35abb1..f944df8 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -183,6 +183,12 @@ properties: - fsl,imx8mn-ddr4-evk# i.MX8MN DDR4 EVK Board - const: fsl,imx8mn + - description: i.MX8MQ based Boards +items: + - enum: + - fsl,imx8mq-evk# i.MX8MQ EVK Board + - const: fsl,imx8mq + - description: i.MX8QXP based Boards items: - enum: -- 2.7.4
[PATCH V4 2/4] arm64: dts: freescale: Add i.MX8MN dtsi support
From: Anson Huang
The i.MX8M Nano Media Applications Processor is a new SoC of the i.MX8M
family, it is a 14nm FinFET product of the growing mScale family targeting
the consumer market. It is built in Samsung 14LPP to achieve both high
performance and low power consumption and relies on a powerful fully
coherent core complex based on a quad core ARM Cortex-A53 cluster,
Cortex-M7 low-power coprocessor and graphics accelerator.
This patch adds the basic dtsi support for i.MX8MN.
Signed-off-by: Anson Huang
---
Changes since V3:
- add "fsl,imx8mm-anatop" as anatop's fallback compatible to support
SoC driver.
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 712 ++
1 file changed, 712 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
new file mode 100644
index 000..f5eff35
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -0,0 +1,712 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+#include "imx8mn-pinfunc.h"
+
+/ {
+ compatible = "fsl,imx8mn";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 =
+ gpio0 =
+ gpio1 =
+ gpio2 =
+ gpio3 =
+ gpio4 =
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ spi0 =
+ spi1 =
+ spi2 =
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x0 0x4000 0 0x8000>;
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "osc_24m";
+ };
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13300>;
+ clock-output-names = "clk_ext1";
+ };
+
+ clk_ext2: clock-ext2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13300>;
+
[PATCH V4 3/4] arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support
From: Anson Huang
This patch adds basic i.MM8MN DDR4 EVK board support.
Signed-off-by: Anson Huang
---
No change.
---
arch/arm64/boot/dts/freescale/Makefile| 1 +
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 221 ++
2 files changed, 222 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile
b/arch/arm64/boot/dts/freescale/Makefile
index 0bd122f..2c9070f 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
new file mode 100644
index 000..9b2c172
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+
+/ {
+ model = "NXP i.MX8MNano DDR4 EVK board";
+ compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
+
+ chosen {
+ stdout-path =
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO220x19
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MN_IOMUXC_G
[PATCH V4 1/4] dt-bindings: arm: imx: Add the soc binding for i.MX8MN
From: Anson Huang This patch adds the soc & board binding for i.MX8MN. Signed-off-by: Anson Huang Reviewed-by: Rob Herring --- No change. --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 407138e..b35abb1 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -177,6 +177,12 @@ properties: - fsl,imx8mm-evk# i.MX8MM EVK Board - const: fsl,imx8mm + - description: i.MX8MN based Boards +items: + - enum: + - fsl,imx8mn-ddr4-evk# i.MX8MN DDR4 EVK Board + - const: fsl,imx8mn + - description: i.MX8QXP based Boards items: - enum: -- 2.7.4
RE: [PATCH] soc: imx: Add i.MX8MN SoC driver support
Hi, Shawn
> -Original Message-
> From: Shawn Guo
> Sent: Tuesday, June 18, 2019 8:59 PM
> To: Anson Huang
> Cc: s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> Leonard Crestez ; viresh.ku...@linaro.org;
> Abel Vesa ; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; dl-linux-imx
> Subject: Re: [PATCH] soc: imx: Add i.MX8MN SoC driver support
>
> On Tue, Jun 18, 2019 at 08:24:59AM +, Anson Huang wrote:
> > Hi, Shawn
> >
> > > -Original Message-
> > > From: Shawn Guo
> > > Sent: Tuesday, June 18, 2019 3:04 PM
> > > To: Anson Huang
> > > Cc: s.ha...@pengutronix.de; ker...@pengutronix.de;
> > > feste...@gmail.com; Leonard Crestez ;
> > > viresh.ku...@linaro.org; Abel Vesa ;
> > > linux-arm-ker...@lists.infradead.org;
> > > linux-kernel@vger.kernel.org; dl-linux-imx
> > > Subject: Re: [PATCH] soc: imx: Add i.MX8MN SoC driver support
> > >
> > > On Tue, Jun 11, 2019 at 09:31:25AM +0800, anson.hu...@nxp.com
> wrote:
> > > > From: Anson Huang
> > > >
> > > > This patch adds i.MX8MN SoC driver support:
> > > >
> > > > root@imx8mnevk:~# cat /sys/devices/soc0/family Freescale i.MX
> > > >
> > > > root@imx8mnevk:~# cat /sys/devices/soc0/machine NXP i.MX8MNano
> > > DDR4
> > > > EVK board
> > > >
> > > > root@imx8mnevk:~# cat /sys/devices/soc0/soc_id i.MX8MN
> > > >
> > > > root@imx8mnevk:~# cat /sys/devices/soc0/revision
> > > > 1.0
> > > >
> > > > Signed-off-by: Anson Huang
> > > > ---
> > > > drivers/soc/imx/soc-imx8.c | 13 -
> > > > 1 file changed, 12 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/soc/imx/soc-imx8.c
> > > > b/drivers/soc/imx/soc-imx8.c index 3842d09..02309a2 100644
> > > > --- a/drivers/soc/imx/soc-imx8.c
> > > > +++ b/drivers/soc/imx/soc-imx8.c
> > > > @@ -55,7 +55,12 @@ static u32 __init imx8mm_soc_revision(void)
> > > > void __iomem *anatop_base;
> > > > u32 rev;
> > > >
> > > > - np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
> > > > + if (of_machine_is_compatible("fsl,imx8mm"))
> > > > + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-
> > > anatop");
> > > > + else if (of_machine_is_compatible("fsl,imx8mn"))
> > > > + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-
> > > anatop");
> > >
> > > Can we have this anatop compatible in imx8_soc_data, so that we may
> > > save the call to of_machine_is_compatible()?
> >
> > Do you mean adding a variable like " const char *anatop_compat " in
> > imx8_soc_date structure, then initialize it according to SoC type, and
> > in imx8mm_soc_revision(), get to soc_data's anatio_compat to find the
> > anatop node? If yes, we have to add some code to get the soc_data in this
> function, or maybe we can pass anatop compatible name as .soc_revision's
> parameter?
> >
> > static const struct imx8_soc_data imx8mn_soc_data = {
> > .name = "i.MX8MN",
> > .soc_revision = imx8mm_soc_revision,
> > .anatop_compat = "fsl,imx8mn-anatop", };
>
> Okay, just realized that we only want to handle imx8mn with imx8mm
> function. It makes less sense to add anatop compatible into imx8_soc_data
> just for that.
>
> So it looks like that imx8mn is highly compatible with imx8mm, including
> anatop block? If that's the case, maybe we can have compatible of imx8mn
> anatop like below, so that we can save above changes?
>
> compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
Make sense, I just sent out V2 with this approach, and will add the
"fsl,imx8mm-anatop"
as i.MX8MN ANATOP fallback compatible when I need to resend the i.MX8MN DT
patch series.
Thanks,
Anson
>
> Shawn
[PATCH V2] soc: imx: Add i.MX8MN SoC driver support
From: Anson Huang
This patch adds i.MX8MN SoC driver support:
root@imx8mnevk:~# cat /sys/devices/soc0/family
Freescale i.MX
root@imx8mnevk:~# cat /sys/devices/soc0/machine
NXP i.MX8MNano DDR4 EVK board
root@imx8mnevk:~# cat /sys/devices/soc0/soc_id
i.MX8MN
root@imx8mnevk:~# cat /sys/devices/soc0/revision
1.0
Signed-off-by: Anson Huang
---
Changes since V1:
- i.MX8MN's anatop is fully compatible with i.MX8MM, so just use
"fsl,imx8mm-anatop" as fallback
compatible in i.MX8MN DT can avoid the machine check.
---
drivers/soc/imx/soc-imx8.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/soc/imx/soc-imx8.c b/drivers/soc/imx/soc-imx8.c
index 315311f..f924ae8 100644
--- a/drivers/soc/imx/soc-imx8.c
+++ b/drivers/soc/imx/soc-imx8.c
@@ -79,9 +79,15 @@ static const struct imx8_soc_data imx8mm_soc_data = {
.soc_revision = imx8mm_soc_revision,
};
+static const struct imx8_soc_data imx8mn_soc_data = {
+ .name = "i.MX8MN",
+ .soc_revision = imx8mm_soc_revision,
+};
+
static const struct of_device_id imx8_soc_match[] = {
{ .compatible = "fsl,imx8mq", .data = _soc_data, },
{ .compatible = "fsl,imx8mm", .data = _soc_data, },
+ { .compatible = "fsl,imx8mn", .data = _soc_data, },
{ }
};
--
2.7.4
RE: [PATCH V2 2/2] soc: imx8: Use existing of_root directly
Hi, Shawn
> -Original Message-
> From: Shawn Guo
> Sent: Tuesday, June 18, 2019 5:15 PM
> To: Anson Huang
> Cc: s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> Leonard Crestez ; viresh.ku...@linaro.org;
> Abel Vesa ; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; dl-linux-imx
> Subject: Re: [PATCH V2 2/2] soc: imx8: Use existing of_root directly
>
> On Fri, Jun 14, 2019 at 04:07:48PM +0800, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > There is common of_root for reference, no need to find it from DT
> > again, use of_root directly to make driver simple.
> >
> > Signed-off-by: Anson Huang
> > Reviewed-by: Dong Aisheng
>
> It cannot be applied. Please resend by basing on my imx/drivers branch.
OK, just resent, there is a soc driver patch in linux-next, previously I did it
based on it.
Now I change it to your git repo, you could meet conflict during merge.
Thanks,
Anson
>
> Shawn
>
> > ---
> > No changes.
> > ---
> > drivers/soc/imx/soc-imx8.c | 9 ++---
> > 1 file changed, 2 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/soc/imx/soc-imx8.c b/drivers/soc/imx/soc-imx8.c
> > index 5c7f330..b459bf2 100644
> > --- a/drivers/soc/imx/soc-imx8.c
> > +++ b/drivers/soc/imx/soc-imx8.c
> > @@ -105,7 +105,6 @@ static int __init imx8_soc_init(void) {
> > struct soc_device_attribute *soc_dev_attr;
> > struct soc_device *soc_dev;
> > - struct device_node *root;
> > const struct of_device_id *id;
> > u32 soc_rev = 0;
> > const struct imx8_soc_data *data;
> > @@ -117,12 +116,11 @@ static int __init imx8_soc_init(void)
> >
> > soc_dev_attr->family = "Freescale i.MX";
> >
> > - root = of_find_node_by_path("/");
> > - ret = of_property_read_string(root, "model", _dev_attr-
> >machine);
> > + ret = of_property_read_string(of_root, "model",
> > +_dev_attr->machine);
> > if (ret)
> > goto free_soc;
> >
> > - id = of_match_node(imx8_soc_match, root);
> > + id = of_match_node(imx8_soc_match, of_root);
> > if (!id) {
> > ret = -ENODEV;
> > goto free_soc;
> > @@ -147,8 +145,6 @@ static int __init imx8_soc_init(void)
> > goto free_rev;
> > }
> >
> > - of_node_put(root);
> > -
> > if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
> > platform_device_register_simple("imx-cpufreq-dt", -1, NULL,
> 0);
> >
> > @@ -159,7 +155,6 @@ static int __init imx8_soc_init(void)
> > kfree(soc_dev_attr->revision);
> > free_soc:
> > kfree(soc_dev_attr);
> > - of_node_put(root);
> > return ret;
> > }
> > device_initcall(imx8_soc_init);
> > --
> > 2.7.4
> >
[PATCH RESEND V2] soc: imx8: Use existing of_root directly
From: Anson Huang
There is common of_root for reference, no need to find it
from DT again, use of_root directly to make driver simple.
Signed-off-by: Anson Huang
---
drivers/soc/imx/soc-imx8.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/imx/soc-imx8.c b/drivers/soc/imx/soc-imx8.c
index ef2406f..34ab993 100644
--- a/drivers/soc/imx/soc-imx8.c
+++ b/drivers/soc/imx/soc-imx8.c
@@ -94,7 +94,6 @@ static int __init imx8_soc_init(void)
{
struct soc_device_attribute *soc_dev_attr;
struct soc_device *soc_dev;
- struct device_node *root;
const struct of_device_id *id;
u32 soc_rev = 0;
const struct imx8_soc_data *data;
@@ -106,12 +105,11 @@ static int __init imx8_soc_init(void)
soc_dev_attr->family = "Freescale i.MX";
- root = of_find_node_by_path("/");
- ret = of_property_read_string(root, "model", _dev_attr->machine);
+ ret = of_property_read_string(of_root, "model", _dev_attr->machine);
if (ret)
goto free_soc;
- id = of_match_node(imx8_soc_match, root);
+ id = of_match_node(imx8_soc_match, of_root);
if (!id) {
ret = -ENODEV;
goto free_soc;
@@ -136,8 +134,6 @@ static int __init imx8_soc_init(void)
goto free_rev;
}
- of_node_put(root);
-
return 0;
free_rev:
@@ -145,7 +141,6 @@ static int __init imx8_soc_init(void)
kfree(soc_dev_attr->revision);
free_soc:
kfree(soc_dev_attr);
- of_node_put(root);
return ret;
}
device_initcall(imx8_soc_init);
--
2.7.4
RE: [PATCH] soc: imx: Add i.MX8MN SoC driver support
Hi, Shawn
> -Original Message-
> From: Shawn Guo
> Sent: Tuesday, June 18, 2019 3:04 PM
> To: Anson Huang
> Cc: s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> Leonard Crestez ; viresh.ku...@linaro.org;
> Abel Vesa ; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; dl-linux-imx
> Subject: Re: [PATCH] soc: imx: Add i.MX8MN SoC driver support
>
> On Tue, Jun 11, 2019 at 09:31:25AM +0800, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > This patch adds i.MX8MN SoC driver support:
> >
> > root@imx8mnevk:~# cat /sys/devices/soc0/family Freescale i.MX
> >
> > root@imx8mnevk:~# cat /sys/devices/soc0/machine NXP i.MX8MNano
> DDR4
> > EVK board
> >
> > root@imx8mnevk:~# cat /sys/devices/soc0/soc_id i.MX8MN
> >
> > root@imx8mnevk:~# cat /sys/devices/soc0/revision
> > 1.0
> >
> > Signed-off-by: Anson Huang
> > ---
> > drivers/soc/imx/soc-imx8.c | 13 -
> > 1 file changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/soc/imx/soc-imx8.c b/drivers/soc/imx/soc-imx8.c
> > index 3842d09..02309a2 100644
> > --- a/drivers/soc/imx/soc-imx8.c
> > +++ b/drivers/soc/imx/soc-imx8.c
> > @@ -55,7 +55,12 @@ static u32 __init imx8mm_soc_revision(void)
> > void __iomem *anatop_base;
> > u32 rev;
> >
> > - np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
> > + if (of_machine_is_compatible("fsl,imx8mm"))
> > + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-
> anatop");
> > + else if (of_machine_is_compatible("fsl,imx8mn"))
> > + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-
> anatop");
>
> Can we have this anatop compatible in imx8_soc_data, so that we may save
> the call to of_machine_is_compatible()?
Do you mean adding a variable like " const char *anatop_compat " in
imx8_soc_date structure,
then initialize it according to SoC type, and in imx8mm_soc_revision(), get to
soc_data's anatio_compat to
find the anatop node? If yes, we have to add some code to get the soc_data in
this function, or maybe
we can pass anatop compatible name as .soc_revision's parameter?
static const struct imx8_soc_data imx8mn_soc_data = {
.name = "i.MX8MN",
.soc_revision = imx8mm_soc_revision,
.anatop_compat = "fsl,imx8mn-anatop",
};
Anson.
>
> Shawn
>
> > + else
> > + np = NULL;
> > if (!np)
> > return 0;
> >
> > @@ -79,9 +84,15 @@ static const struct imx8_soc_data imx8mm_soc_data
> = {
> > .soc_revision = imx8mm_soc_revision, };
> >
> > +static const struct imx8_soc_data imx8mn_soc_data = {
> > + .name = "i.MX8MN",
> > + .soc_revision = imx8mm_soc_revision, };
> > +
> > static const struct of_device_id imx8_soc_match[] = {
> > { .compatible = "fsl,imx8mq", .data = _soc_data, },
> > { .compatible = "fsl,imx8mm", .data = _soc_data, },
> > + { .compatible = "fsl,imx8mn", .data = _soc_data, },
> > { }
> > };
> >
> > --
> > 2.7.4
> >
[PATCH V15 3/5] thermal: imx_sc: add i.MX system controller thermal support
From: Anson Huang
i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller
inside, the system controller is in charge of controlling power,
clock and thermal sensors etc..
This patch adds i.MX system controller thermal driver support,
Linux kernel has to communicate with system controller via MU
(message unit) IPC to get each thermal sensor's temperature,
it supports multiple sensors which are passed from device tree,
please see the binding doc for details.
Signed-off-by: Anson Huang
---
No change.
---
drivers/thermal/Kconfig | 11 +++
drivers/thermal/Makefile | 1 +
drivers/thermal/imx_sc_thermal.c | 142 +++
3 files changed, 154 insertions(+)
create mode 100644 drivers/thermal/imx_sc_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 9966364..454cbe5 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -233,6 +233,17 @@ config IMX_THERMAL
cpufreq is used as the cooling device to throttle CPUs when the
passive trip is crossed.
+config IMX_SC_THERMAL
+ tristate "Temperature sensor driver for NXP i.MX SoCs with System
Controller"
+ depends on ARCH_MXC && IMX_SCU
+ depends on OF
+ help
+ Support for Temperature Monitor (TEMPMON) found on NXP i.MX SoCs with
+ system controller inside, Linux kernel has to communicate with system
+ controller via MU (message unit) IPC to get temperature from thermal
+ sensor. It supports one critical trip point and one
+ passive trip point for each thermal sensor.
+
config MAX77620_THERMAL
tristate "Temperature sensor driver for Maxim MAX77620 PMIC"
depends on MFD_MAX77620
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 74a37c7..717a1ba 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
obj-$(CONFIG_TANGO_THERMAL)+= tango_thermal.o
obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_IMX_SC_THERMAL) += imx_sc_thermal.o
obj-$(CONFIG_MAX77620_THERMAL) += max77620_thermal.o
obj-$(CONFIG_QORIQ_THERMAL)+= qoriq_thermal.o
obj-$(CONFIG_DA9062_THERMAL) += da9062-thermal.o
diff --git a/drivers/thermal/imx_sc_thermal.c b/drivers/thermal/imx_sc_thermal.c
new file mode 100644
index 000..d406ecb
--- /dev/null
+++ b/drivers/thermal/imx_sc_thermal.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "thermal_core.h"
+
+#define IMX_SC_MISC_FUNC_GET_TEMP 13
+
+static struct imx_sc_ipc *thermal_ipc_handle;
+
+struct imx_sc_sensor {
+ struct thermal_zone_device *tzd;
+ u32 resource_id;
+};
+
+struct req_get_temp {
+ u16 resource_id;
+ u8 type;
+} __packed;
+
+struct resp_get_temp {
+ u16 celsius;
+ u8 tenths;
+} __packed;
+
+struct imx_sc_msg_misc_get_temp {
+ struct imx_sc_rpc_msg hdr;
+ union {
+ struct req_get_temp req;
+ struct resp_get_temp resp;
+ } data;
+};
+
+static int imx_sc_thermal_get_temp(void *data, int *temp)
+{
+ struct imx_sc_msg_misc_get_temp msg;
+ struct imx_sc_rpc_msg *hdr =
+ struct imx_sc_sensor *sensor = data;
+ int ret;
+
+ msg.data.req.resource_id = sensor->resource_id;
+ msg.data.req.type = IMX_SC_C_TEMP;
+
+ hdr->ver = IMX_SC_RPC_VERSION;
+ hdr->svc = IMX_SC_RPC_SVC_MISC;
+ hdr->func = IMX_SC_MISC_FUNC_GET_TEMP;
+ hdr->size = 2;
+
+ ret = imx_scu_call_rpc(thermal_ipc_handle, , true);
+ if (ret) {
+ dev_err(>tzd->device, "read temp sensor %d failed, ret
%d\n",
+ sensor->resource_id, ret);
+ return ret;
+ }
+
+ *temp = msg.data.resp.celsius * 1000 + msg.data.resp.tenths * 100;
+
+ return 0;
+}
+
+static const struct thermal_zone_of_device_ops imx_sc_thermal_ops = {
+ .get_temp = imx_sc_thermal_get_temp,
+};
+
+static int imx_sc_thermal_probe(struct platform_device *pdev)
+{
+ struct device_node *np, *child, *sensor_np;
+ struct imx_sc_sensor *sensor;
+ int ret;
+
+ ret = imx_scu_get_handle(_ipc_handle);
+ if (ret)
+ return ret;
+
+ np = of_find_node_by_name(NULL, "thermal-zones");
+ if (!np)
+ return -ENODEV;
+
+ sensor_np = of_node_get(pdev->dev.of_node);
+
+ for_each_available_child_of_node(np, child) {
+ sensor = devm_kzalloc(>dev, sizeof(*sensor), GFP_KERNEL);
+ if (!sensor) {
+ of_node_put(sensor_np);
+ retur
[PATCH V5 5/5] arm64: defconfig: Select CONFIG_CLK_IMX8MN by default
From: Anson Huang Enable CONFIG_CLK_IMX8MN to support i.MX8MN clock driver. Signed-off-by: Anson Huang --- No changes. --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3dfbd6a..b2de9d0 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -658,6 +658,7 @@ CONFIG_COMMON_CLK_S2MPS11=y CONFIG_CLK_QORIQ=y CONFIG_COMMON_CLK_PWM=y CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y CONFIG_CLK_IMX8MQ=y CONFIG_CLK_IMX8QXP=y CONFIG_TI_SCI_CLK=y -- 2.7.4
[PATCH V5 1/5] dt-bindings: imx: Add clock binding doc for i.MX8MN
From: Anson Huang
Add the clock binding doc for i.MX8MN.
Signed-off-by: Anson Huang
Reviewed-by: Maxime Ripard
---
Changes since V4:
- remove unnecessary reference statement for common clock binding;
- move the description about clock cell to clock-cells node.
---
.../devicetree/bindings/clock/imx8mn-clock.yaml| 112 +++
include/dt-bindings/clock/imx8mn-clock.h | 215 +
2 files changed, 327 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
create mode 100644 include/dt-bindings/clock/imx8mn-clock.h
diff --git a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
new file mode 100644
index 000..454c5b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8M Nano Clock Control Module Binding
+
+maintainers:
+ - Anson Huang
+
+description: |
+ NXP i.MX8M Nano clock control module is an integrated clock controller, which
+ generates and supplies to all modules.
+
+properties:
+ compatible:
+const: fsl,imx8mn-ccm
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: 32k osc
+ - description: 24m osc
+ - description: ext1 clock input
+ - description: ext2 clock input
+ - description: ext3 clock input
+ - description: ext4 clock input
+
+ clock-names:
+items:
+ - const: osc_32k
+ - const: osc_24m
+ - const: clk_ext1
+ - const: clk_ext2
+ - const: clk_ext3
+ - const: clk_ext4
+
+ '#clock-cells':
+const: 1
+description: |
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See
include/dt-bindings/clock/imx8mn-clock.h
+ for the full list of i.MX8M Nano clock IDs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+examples:
+ # Clock Control Module node:
+ - |
+clk: clock-controller@3038 {
+compatible = "fsl,imx8mn-ccm";
+reg = <0x0 0x3038 0x0 0x1>;
+#clock-cells = <1>;
+clocks = <_32k>, <_24m>, <_ext1>,
+ <_ext2>, <_ext3>, <_ext4>;
+clock-names = "osc_32k", "osc_24m", "clk_ext1",
+ "clk_ext2", "clk_ext3", "clk_ext4";
+};
+
+ # Required external clocks for Clock Control Module node:
+ - |
+osc_32k: clock-osc-32k {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+};
+
+osc_24m: clock-osc-24m {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <2400>;
+clock-output-names = "osc_24m";
+};
+
+clk_ext1: clock-ext1 {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <13300>;
+clock-output-names = "clk_ext1";
+};
+
+clk_ext2: clock-ext2 {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <13300>;
+clock-output-names = "clk_ext2";
+};
+
+clk_ext3: clock-ext3 {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <13300>;
+clock-output-names = "clk_ext3";
+};
+
+clk_ext4: clock-ext4 {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency= <13300>;
+clock-output-names = "clk_ext4";
+};
+
+...
diff --git a/include/dt-bindings/clock/imx8mn-clock.h
b/include/dt-bindings/clock/imx8mn-clock.h
new file mode 100644
index 000..5255b1c
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
+#define __DT_BINDINGS_CLOCK_IMX8MN_H
+
+#define IMX8MN_CLK_DUMMY 0
+#define IMX8MN_CLK_32K 1
+#define IMX8MN_CLK_24M 2
+#define IMX8MN_OSC_HDMI_CLK3
+#define IMX8MN_CLK_EXT14
+#define IMX8MN_CLK_EXT25
+#define IMX8MN_CLK_EXT36
+#define IMX8MN_CLK_EXT47
+#define IMX8MN_AUDIO_PLL1_REF_SEL 8
+#define IMX8MN_AUDIO_PLL2_REF_SEL 9
+#define I
[PATCH V5 2/5] clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage
From: Anson Huang
1416X/1443X PLL are used on i.MX8MM and i.MX8MN and maybe
other i.MX8M series SoC later, the macro definitions of
these PLLs' initialization should be common for usage.
Signed-off-by: Anson Huang
---
No changes.
---
drivers/clk/imx/clk-imx8mm.c | 17 -
drivers/clk/imx/clk.h| 17 +
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 6b8e75d..43fa9c3 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -26,23 +26,6 @@ static u32 share_count_dcss;
static u32 share_count_pdm;
static u32 share_count_nand;
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- .kdiv = (_k), \
- }
-
static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
PLL_1416X_RATE(18U, 225, 3, 0),
PLL_1416X_RATE(16U, 200, 3, 0),
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index d94d9cb..19d7b8b 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -153,6 +153,23 @@ enum imx_pllv3_type {
struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent_name, void __iomem *base, u32 div_mask);
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
void __iomem *base);
--
2.7.4
[PATCH V5 4/5] clk: imx: Add support for i.MX8MN clock driver
From: Anson Huang
This patch adds i.MX8MN clock driver support.
Signed-off-by: Anson Huang
---
Changes since V4:
- add clock unregister operations when probe failed.
---
drivers/clk/imx/Kconfig | 6 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx8mn.c | 636 +++
3 files changed, 643 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mn.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 0eaf418..1ac0c79 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -14,6 +14,12 @@ config CLK_IMX8MM
help
Build the driver for i.MX8MM CCM Clock Driver
+config CLK_IMX8MN
+ bool "IMX8MN CCM Clock Driver"
+ depends on ARCH_MXC && ARM64
+ help
+ Build the driver for i.MX8MN CCM Clock Driver
+
config CLK_IMX8MQ
bool "IMX8MQ CCM Clock Driver"
depends on ARCH_MXC && ARM64
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 05641c6..77a3d71 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_MXC_CLK_SCU) += \
clk-lpcg-scu.o
obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
+obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
new file mode 100644
index 000..c6ffa3c
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -0,0 +1,636 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018-2019 NXP.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static u32 share_count_sai2;
+static u32 share_count_sai3;
+static u32 share_count_sai5;
+static u32 share_count_sai6;
+static u32 share_count_sai7;
+static u32 share_count_disp;
+static u32 share_count_pdm;
+static u32 share_count_nand;
+
+enum {
+ ARM_PLL,
+ GPU_PLL,
+ VPU_PLL,
+ SYS_PLL1,
+ SYS_PLL2,
+ SYS_PLL3,
+ DRAM_PLL,
+ AUDIO_PLL1,
+ AUDIO_PLL2,
+ VIDEO_PLL2,
+ NR_PLLS,
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
+ PLL_1443X_RATE(786432000U, 655, 5, 2, 23593),
+ PLL_1443X_RATE(722534400U, 301, 5, 1, 3670),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(59400U, 198, 2, 2, 0),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+};
+
+static struct imx_pll14xx_clk imx8mn_audio_pll = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_audiopll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_video_pll = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_videopll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_dram_pll = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_drampll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_arm_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_gpu_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_vpu_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_sys_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy",
"dummy", };
+static const char * const audio_pll1_bypass_sels[] = {"audio_pll1",
"audio_pll1_ref_sel", };
+static const char * const audio_pll2_bypass_sels[] = {"audio_pll2",
"audio_pll2_ref_sel", };
+static const char * const video_pll1_bypass_sels[] = {"video_pll1",
"video_pll1_ref_sel", };
+static const char * const dram_pll_bypass_sels[] = {"dram_pll",
"dram_pll_ref_sel", };
+static const char * const gpu_pll_bypass_sels[] = {"gpu_pll",
"gpu_pll_ref_sel", };
+static const char * const vpu_pll_bypass_sels[] = {"vpu_pll",
"vpu_pll_ref_sel"
[PATCH V5 3/5] clk: imx: Add API for clk unregister when driver probe fail
From: Anson Huang
For i.MX clock drivers probe fail case, clks should be unregistered
in the return path, this patch adds a common API for i.MX clock
drivers to unregister clocks when fail.
Signed-off-by: Anson Huang
---
New patch.
---
drivers/clk/imx/clk.c | 8
drivers/clk/imx/clk.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index f241189..14a6161 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -13,6 +13,14 @@
DEFINE_SPINLOCK(imx_ccm_lock);
+void imx_unregister_clocks(struct clk *clks[], unsigned int count)
+{
+ unsigned int i;
+
+ for (i = 0; i < count; i++)
+ clk_unregister(clks[i]);
+}
+
void __init imx_mmdc_mask_handshake(void __iomem *ccm_base,
unsigned int chn)
{
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 19d7b8b..bb4ec1b 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -12,6 +12,7 @@ void imx_check_clk_hws(struct clk_hw *clks[], unsigned int
count);
void imx_register_uart_clocks(struct clk ** const clks[]);
void imx_register_uart_clocks_hws(struct clk_hw ** const hws[]);
void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
+void imx_unregister_clocks(struct clk *clks[], unsigned int count);
extern void imx_cscmr1_fixup(u32 *val);
--
2.7.4
[PATCH V2 1/2] soc: imx8: Fix potential kernel dump in error path
From: Anson Huang
When SoC's revision value is 0, SoC driver will print out
"unknown" in sysfs's revision node, this "unknown" is a
static string which can NOT be freed, this will caused below
kernel dump in later error path which calls kfree:
kernel BUG at mm/slub.c:3942!
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
Modules linked in:
CPU: 2 PID: 1 Comm: swapper/0 Not tainted
5.2.0-rc4-next-20190611-00023-g705146c-dirty #2197
Hardware name: NXP i.MX8MQ EVK (DT)
pstate: 6005 (nZCv daif -PAN -UAO)
pc : kfree+0x170/0x1b0
lr : imx8_soc_init+0xc0/0xe4
sp : 1003bd10
x29: 1003bd10 x28: 1121e0a0
x27: 11482000 x26: 1117068c
x25: 1121e100 x24: 11482000
x23: 10fe2b58 x22: 111b9ab0
x21: 8000bd9dfba0 x20: 111b9b70
x19: 7e43f880 x18: 1000
x17: 10d05fa0 x16: 122e
x15: 0140 x14: 3036
x13: 8000b94b5bb0 x12: 0038
x11: x10:
x9 : 0003 x8 : 8000b9488147
x7 : 1003bc00 x6 :
x5 : 0003 x4 : 0003
x3 : 0003 x2 : b8793acd604edf00
x1 : 7e43f880 x0 : 7e43f888
Call trace:
kfree+0x170/0x1b0
imx8_soc_init+0xc0/0xe4
do_one_initcall+0x58/0x1b8
kernel_init_freeable+0x1cc/0x288
kernel_init+0x10/0x100
ret_from_fork+0x10/0x18
This patch fixes this potential kernel dump when a chip's
revision is "unknown", it is done by checking whether the
revision space can be freed.
Fixes: a7e26f356ca1 ("soc: imx: Add generic i.MX8 SoC driver")
Signed-off-by: Anson Huang
---
Changes since V1:
- still need the "unknown" info for revision to avoid confusion, so fix
this issue
by checking whether the revision space can be freed before freeing it.
---
drivers/soc/imx/soc-imx8.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/imx/soc-imx8.c b/drivers/soc/imx/soc-imx8.c
index 02309a2..5c7f330 100644
--- a/drivers/soc/imx/soc-imx8.c
+++ b/drivers/soc/imx/soc-imx8.c
@@ -155,7 +155,8 @@ static int __init imx8_soc_init(void)
return 0;
free_rev:
- kfree(soc_dev_attr->revision);
+ if (strcmp(soc_dev_attr->revision, "unknown"))
+ kfree(soc_dev_attr->revision);
free_soc:
kfree(soc_dev_attr);
of_node_put(root);
--
2.7.4
[PATCH V2 2/2] soc: imx8: Use existing of_root directly
From: Anson Huang
There is common of_root for reference, no need to find it
from DT again, use of_root directly to make driver simple.
Signed-off-by: Anson Huang
Reviewed-by: Dong Aisheng
---
No changes.
---
drivers/soc/imx/soc-imx8.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/imx/soc-imx8.c b/drivers/soc/imx/soc-imx8.c
index 5c7f330..b459bf2 100644
--- a/drivers/soc/imx/soc-imx8.c
+++ b/drivers/soc/imx/soc-imx8.c
@@ -105,7 +105,6 @@ static int __init imx8_soc_init(void)
{
struct soc_device_attribute *soc_dev_attr;
struct soc_device *soc_dev;
- struct device_node *root;
const struct of_device_id *id;
u32 soc_rev = 0;
const struct imx8_soc_data *data;
@@ -117,12 +116,11 @@ static int __init imx8_soc_init(void)
soc_dev_attr->family = "Freescale i.MX";
- root = of_find_node_by_path("/");
- ret = of_property_read_string(root, "model", _dev_attr->machine);
+ ret = of_property_read_string(of_root, "model", _dev_attr->machine);
if (ret)
goto free_soc;
- id = of_match_node(imx8_soc_match, root);
+ id = of_match_node(imx8_soc_match, of_root);
if (!id) {
ret = -ENODEV;
goto free_soc;
@@ -147,8 +145,6 @@ static int __init imx8_soc_init(void)
goto free_rev;
}
- of_node_put(root);
-
if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
@@ -159,7 +155,6 @@ static int __init imx8_soc_init(void)
kfree(soc_dev_attr->revision);
free_soc:
kfree(soc_dev_attr);
- of_node_put(root);
return ret;
}
device_initcall(imx8_soc_init);
--
2.7.4
[PATCH] arm64: dts: imx8mq-evk: Enable SNVS power key
From: Anson Huang
Enable SNVS power key for i.MX8MQ EVK board.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index b2038be..e3df9b8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -242,6 +242,10 @@
power-supply = <_reg>;
};
+_pwrkey {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_uart1>;
--
2.7.4
[PATCH] arm64: dts: imx8mm: Enable SNVS power key according to board design
From: Anson Huang
The SNVS power key depends on board design, by default it should
be disabled in SoC DT and ONLY be enabled on board DT if it is
wired up.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 4
arch/arm64/boot/dts/freescale/imx8mm.dtsi| 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index f8ff0a4..594f158 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -65,6 +65,10 @@
};
};
+_pwrkey {
+ status = "okay";
+};
+
{ /* console */
pinctrl-names = "default";
pinctrl-0 = <_uart2>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 67ed1c5..232a741 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -439,6 +439,7 @@
interrupts = ;
linux,keycode = ;
wakeup-source;
+ status = "disabled";
};
};
--
2.7.4
[PATCH 2/6] ARM: dts: imx6sx: Enable SNVS power key according to board design
From: Anson Huang
The SNVS power key depends on board design, by default it should
be disabled in SoC DT and ONLY be enabled on board DT if it is
wired up.
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx6sx-sdb-reva.dts | 4
arch/arm/boot/dts/imx6sx-sdb.dts | 4
arch/arm/boot/dts/imx6sx.dtsi | 1 +
3 files changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts
b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
index 5b3d6c10..f1830ed 100644
--- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -166,3 +166,7 @@
_vdd2p5 {
vin-supply = <_reg>;
};
+
+_pwrkey {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 10f6da8..a8ee708 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -153,3 +153,7 @@
/* Transceiver EN/STBY is active low on RevB board */
gpio = < 27 GPIO_ACTIVE_LOW>;
};
+
+_pwrkey {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index bbdfdd8..bb25add 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -738,6 +738,7 @@
interrupts = ;
linux,keycode = ;
wakeup-source;
+ status = "disabled";
};
};
--
2.7.4
[PATCH 4/6] ARM: dts: imx6sll: Enable SNVS power key according to board design
From: Anson Huang
The SNVS power key depends on board design, by default it should
be disabled in SoC DT and ONLY be enabled on board DT if it is
wired up.
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx6sll-evk.dts | 4
arch/arm/boot/dts/imx6sll.dtsi| 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sll-evk.dts
b/arch/arm/boot/dts/imx6sll-evk.dts
index 78809ea..61aa074 100644
--- a/arch/arm/boot/dts/imx6sll-evk.dts
+++ b/arch/arm/boot/dts/imx6sll-evk.dts
@@ -269,6 +269,10 @@
vin-supply = <_reg>;
};
+_pwrkey {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_uart1>;
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index 1b4899f..4384023 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -576,6 +576,7 @@
interrupts = ;
linux,keycode = ;
wakeup-source;
+ status = "disabled";
};
};
--
2.7.4
[PATCH 5/6] ARM: dts: imx7s: Enable SNVS power key according to board design
From: Anson Huang
The SNVS power key depends on board design, by default it should
be disabled in SoC DT and ONLY be enabled on board DT if it is
wired up.
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx7d-sdb.dts | 4
arch/arm/boot/dts/imx7s.dtsi| 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index a5365b8..869efbc 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -387,6 +387,10 @@
vin-supply = <_reg>;
};
+_pwrkey {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_uart1>;
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index d8b4eb6..479be1f 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -609,6 +609,7 @@
interrupts = ;
linux,keycode = ;
wakeup-source;
+ status = "disabled";
};
};
--
2.7.4
[PATCH 1/6] ARM: dts: imx6qdl: Enable SNVS power key according to board design
From: Anson Huang
The SNVS power key depends on board design, by default it should
be disabled in SoC DT and ONLY be enabled on board DT if it is
wired up.
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 4
arch/arm/boot/dts/imx6qdl.dtsi | 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 11103a4..71ca76a 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -761,6 +761,10 @@
status = "okay";
};
+_pwrkey {
+ status = "okay";
+};
+
{
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 929fc7d..4b80193 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -841,6 +841,7 @@
interrupts = ;
linux,keycode = ;
wakeup-source;
+ status = "disabled";
};
snvs_lpgpr: snvs-lpgpr {
--
2.7.4
[PATCH 6/6] ARM: dts: imx6sll: Enable SNVS poweroff according to board design
From: Anson Huang
The SNVS poweroff depends on board design, by default it should
be disabled in SoC DT and ONLY be enabled on board DT if it is
wired up to external PMIC.
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx6sll-evk.dts | 4
arch/arm/boot/dts/imx6sll.dtsi| 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sll-evk.dts
b/arch/arm/boot/dts/imx6sll-evk.dts
index 61aa074..3e1d32f 100644
--- a/arch/arm/boot/dts/imx6sll-evk.dts
+++ b/arch/arm/boot/dts/imx6sll-evk.dts
@@ -269,6 +269,10 @@
vin-supply = <_reg>;
};
+_poweroff {
+ status = "okay";
+};
+
_pwrkey {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index 4384023..b0a77ff 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -568,6 +568,7 @@
regmap = <>;
offset = <0x38>;
mask = <0x61>;
+ status = "disabled";
};
snvs_pwrkey: snvs-powerkey {
--
2.7.4
[PATCH 3/6] ARM: dts: imx6ul: Enable SNVS power key according to board design
From: Anson Huang
The SNVS power key depends on board design, by default it should
be disabled in SoC DT and ONLY be enabled on board DT if it is
wired up.
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 4
arch/arm/boot/dts/imx6ul.dtsi | 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
index 9207d5d..cbe61b6 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
@@ -238,6 +238,10 @@
status = "okay";
};
+_pwrkey {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_tsc>;
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index fc388b8..0c51439 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -650,6 +650,7 @@
interrupts = ;
linux,keycode = ;
wakeup-source;
+ status = "disabled";
};
snvs_lpgpr: snvs-lpgpr {
--
2.7.4
[PATCH V3 2/4] arm64: dts: freescale: Add i.MX8MN dtsi support
From: Anson Huang
The i.MX8M Nano Media Applications Processor is a new SoC of the i.MX8M
family, it is a 14nm FinFET product of the growing mScale family targeting
the consumer market. It is built in Samsung 14LPP to achieve both high
performance and low power consumption and relies on a powerful fully
coherent core complex based on a quad core ARM Cortex-A53 cluster,
Cortex-M7 low-power coprocessor and graphics accelerator.
This patch adds the basic dtsi support for i.MX8MN.
Signed-off-by: Anson Huang
---
Changes since V2:
- make SNVS powerkey disabled by default as it depends on board design.
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 711 ++
1 file changed, 711 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
new file mode 100644
index 000..1449ee1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -0,0 +1,711 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+#include "imx8mn-pinfunc.h"
+
+/ {
+ compatible = "fsl,imx8mn";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 =
+ gpio0 =
+ gpio1 =
+ gpio2 =
+ gpio3 =
+ gpio4 =
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ spi0 =
+ spi1 =
+ spi2 =
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x0 0x4000 0 0x8000>;
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "osc_24m";
+ };
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13300>;
+ clock-output-names = "clk_ext1";
+ };
+
+ clk_ext2: clock-ext2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13300>;
+ clock-outp
[PATCH V3 3/4] arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support
From: Anson Huang
This patch adds basic i.MM8MN DDR4 EVK board support.
Signed-off-by: Anson Huang
---
Changes since V2:
- Enable SNVS powerkey.
---
arch/arm64/boot/dts/freescale/Makefile| 1 +
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 221 ++
2 files changed, 222 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile
b/arch/arm64/boot/dts/freescale/Makefile
index 0bd122f..2c9070f 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
new file mode 100644
index 000..9b2c172
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+
+/ {
+ model = "NXP i.MX8MNano DDR4 EVK board";
+ compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
+
+ chosen {
+ stdout-path =
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO220x19
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MN_IOMUXC_G
[PATCH V3 1/4] dt-bindings: arm: imx: Add the soc binding for i.MX8MN
From: Anson Huang This patch adds the soc & board binding for i.MX8MN. Signed-off-by: Anson Huang Reviewed-by: Rob Herring --- Changes since V2: - sort it with alphabet order, no content change. --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 407138e..b35abb1 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -177,6 +177,12 @@ properties: - fsl,imx8mm-evk# i.MX8MM EVK Board - const: fsl,imx8mm + - description: i.MX8MN based Boards +items: + - enum: + - fsl,imx8mn-ddr4-evk# i.MX8MN DDR4 EVK Board + - const: fsl,imx8mn + - description: i.MX8QXP based Boards items: - enum: -- 2.7.4
[PATCH V3 4/4] dt-bindings: arm: imx: Add the soc binding for i.MX8MQ
From: Anson Huang This patch adds the soc & board binding for i.MX8MQ. Signed-off-by: Anson Huang --- New patch, as I just found i.MX8MQ SoC & board binding is missed, so add this patch based on i.MX8MN binding, so put it in same series to avoid dependency issue. --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b35abb1..f944df8 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -183,6 +183,12 @@ properties: - fsl,imx8mn-ddr4-evk# i.MX8MN DDR4 EVK Board - const: fsl,imx8mn + - description: i.MX8MQ based Boards +items: + - enum: + - fsl,imx8mq-evk# i.MX8MQ EVK Board + - const: fsl,imx8mq + - description: i.MX8QXP based Boards items: - enum: -- 2.7.4
[PATCH 2/2] soc: imx8: Use existing of_root directly
From: Anson Huang
There is common of_root for reference, no need to find it
from DT again, use of_root directly to make driver simple.
Signed-off-by: Anson Huang
---
drivers/soc/imx/soc-imx8.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/imx/soc-imx8.c b/drivers/soc/imx/soc-imx8.c
index 86b925a..a632083 100644
--- a/drivers/soc/imx/soc-imx8.c
+++ b/drivers/soc/imx/soc-imx8.c
@@ -100,7 +100,6 @@ static int __init imx8_soc_init(void)
{
struct soc_device_attribute *soc_dev_attr;
struct soc_device *soc_dev;
- struct device_node *root;
const struct of_device_id *id;
u32 soc_rev = 0;
const struct imx8_soc_data *data;
@@ -112,12 +111,11 @@ static int __init imx8_soc_init(void)
soc_dev_attr->family = "Freescale i.MX";
- root = of_find_node_by_path("/");
- ret = of_property_read_string(root, "model", _dev_attr->machine);
+ ret = of_property_read_string(of_root, "model", _dev_attr->machine);
if (ret)
goto free_soc;
- id = of_match_node(imx8_soc_match, root);
+ id = of_match_node(imx8_soc_match, of_root);
if (!id) {
ret = -ENODEV;
goto free_soc;
@@ -145,8 +143,6 @@ static int __init imx8_soc_init(void)
goto free_rev;
}
- of_node_put(root);
-
if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
@@ -156,7 +152,6 @@ static int __init imx8_soc_init(void)
kfree(soc_dev_attr->revision);
free_soc:
kfree(soc_dev_attr);
- of_node_put(root);
return ret;
}
device_initcall(imx8_soc_init);
--
2.7.4
[PATCH 1/2] soc: imx8: Fix potential kernel dump in error path
From: Anson Huang
When SoC's revision value is 0, SoC driver will print out
"unknown" in sysfs's revision node, this "unknown" is a
static string which can NOT be freed, this will caused below
kernel dump in later error path which calls kfree:
kernel BUG at mm/slub.c:3942!
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
Modules linked in:
CPU: 2 PID: 1 Comm: swapper/0 Not tainted
5.2.0-rc4-next-20190611-00023-g705146c-dirty #2197
Hardware name: NXP i.MX8MQ EVK (DT)
pstate: 6005 (nZCv daif -PAN -UAO)
pc : kfree+0x170/0x1b0
lr : imx8_soc_init+0xc0/0xe4
sp : 1003bd10
x29: 1003bd10 x28: 1121e0a0
x27: 11482000 x26: 1117068c
x25: 1121e100 x24: 11482000
x23: 10fe2b58 x22: 111b9ab0
x21: 8000bd9dfba0 x20: 111b9b70
x19: 7e43f880 x18: 1000
x17: 10d05fa0 x16: 122e
x15: 0140 x14: 3036
x13: 8000b94b5bb0 x12: 0038
x11: x10:
x9 : 0003 x8 : 8000b9488147
x7 : 1003bc00 x6 :
x5 : 0003 x4 : 0003
x3 : 0003 x2 : b8793acd604edf00
x1 : 7e43f880 x0 : 7e43f888
Call trace:
kfree+0x170/0x1b0
imx8_soc_init+0xc0/0xe4
do_one_initcall+0x58/0x1b8
kernel_init_freeable+0x1cc/0x288
kernel_init+0x10/0x100
ret_from_fork+0x10/0x18
This patch fixes this potential kernel dump when a chip's
revision is "unknown", it is done by always printing out
the revision value.
Fixes: a7e26f356ca1 ("soc: imx: Add generic i.MX8 SoC driver")
Signed-off-by: Anson Huang
---
drivers/soc/imx/soc-imx8.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/imx/soc-imx8.c b/drivers/soc/imx/soc-imx8.c
index 02309a2..86b925a 100644
--- a/drivers/soc/imx/soc-imx8.c
+++ b/drivers/soc/imx/soc-imx8.c
@@ -96,11 +96,6 @@ static const struct of_device_id imx8_soc_match[] = {
{ }
};
-#define imx8_revision(soc_rev) \
- soc_rev ? \
- kasprintf(GFP_KERNEL, "%d.%d", (soc_rev >> 4) & 0xf, soc_rev & 0xf) : \
- "unknown"
-
static int __init imx8_soc_init(void)
{
struct soc_device_attribute *soc_dev_attr;
@@ -135,7 +130,10 @@ static int __init imx8_soc_init(void)
soc_rev = data->soc_revision();
}
- soc_dev_attr->revision = imx8_revision(soc_rev);
+ soc_dev_attr->revision = kasprintf(GFP_KERNEL,
+ "%d.%d",
+ (soc_rev >> 4) & 0xf,
+ soc_rev & 0xf);
if (!soc_dev_attr->revision) {
ret = -ENOMEM;
goto free_soc;
--
2.7.4
RE: [PATCH 2/3] rtc: imx-sc: Make compatible string more generic
Hi, Fabio/Trent
> -Original Message-
> From: Trent Piepho
> Sent: Wednesday, June 12, 2019 4:46 AM
> To: feste...@gmail.com; Anson Huang
> Cc: Aisheng Dong ; alexandre.bell...@bootlin.com;
> robh...@kernel.org; dl-linux-imx ; linux-
> ker...@vger.kernel.org; devicet...@vger.kernel.org;
> a.zu...@towertech.it; mark.rutl...@arm.com; Peng Fan
> ; shawn...@kernel.org; linux-arm-
> ker...@lists.infradead.org; Daniel Baluta ;
> ulf.hans...@linaro.org; ker...@pengutronix.de; linux-...@vger.kernel.org;
> s.ha...@pengutronix.de
> Subject: Re: [PATCH 2/3] rtc: imx-sc: Make compatible string more generic
>
> On Tue, 2019-06-11 at 17:32 -0300, Fabio Estevam wrote:
> > Hi Anson,
> >
> > On Tue, Jun 11, 2019 at 3:31 AM wrote:
> > >
> > > From: Anson Huang
> > >
> > > i.MX system controller RTC driver can support all i.MX SoCs with
> > > system controller inside, this patch makes the compatible string
> > > more generic to support other i.MX SoCs with system controller
> > > inside, such as i.MX8QM etc..
> > >
> > > Signed-off-by: Anson Huang
> > > ---
> > > drivers/rtc/rtc-imx-sc.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/rtc/rtc-imx-sc.c b/drivers/rtc/rtc-imx-sc.c
> > > index c933045..38ef3ca 100644
> > > --- a/drivers/rtc/rtc-imx-sc.c
> > > +++ b/drivers/rtc/rtc-imx-sc.c
> > > @@ -178,7 +178,7 @@ static int imx_sc_rtc_probe(struct
> > > platform_device *pdev) }
> > >
> > > static const struct of_device_id imx_sc_dt_ids[] = {
> > > - { .compatible = "fsl,imx8qxp-sc-rtc", },
> > > + { .compatible = "fsl,imx-sc-rtc", },
> >
> > What is wrong with the current compatible string?
Nothing wrong, just want to make it aligned with other SCU drivers, like
SCU watchdog, SCU thermal etc., the driver ONLY contains "fsl,imx-sc-xxx"
compatible string, then for new SoC, we can just add it as compatible or
fallback compatible string, no need to do any change for driver.
> >
> > If you want to support i.MX8QM just add in its dtsi:
> >
> > compatible = "fsl,imx8qm-sc-rtc", "fsl,imx8qxp-sc-rtc"
> >
> > and add a dt-bindings entry for "fsl,imx8qm-sc-rtc"
I am OK if we can just use " fsl,imx8qxp-sc-rtc" as fallback compatible string
for later SoCs.
>
> Yes, I thought this is (was?) the recommended practice for IP blocks in SoCs
> that don't have their own version (vs something like a Synopsis block used
> many places):
>
> * Use the first SoC to have the block as the base compatible for the block.
> * Always add the current SoC, in additional to the base, in the SoC's dts's
> list
> of compatibles. Even if unneeded at the present.
> * The driver will list the base compatible in the match table, and will add
> new
> ones for specific socs if/when there is a need for it.
Make sense, I was recommended to make the fallback compatible string aligned
for all SCU drivers, for me, I am OK with either way, so if you think it is NOT
necessary
to do it, we can drop this series.
Thanks,
Anson
[PATCH V2 3/3] arm64: defconfig: Select CONFIG_PINCTRL_IMX8MN by default
From: Anson Huang Enable CONFIG_PINCTRL_IMX8MN by default to support i.MX8MN pinctrl driver. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng --- Changes since V1: - sort the change in alphabet order. --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 9e6e07e..a47b0d6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -374,6 +374,7 @@ CONFIG_SPMI=y CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_IMX8MM=y +CONFIG_PINCTRL_IMX8MN=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IPQ8074=y -- 2.7.4
[PATCH V2 2/3] pinctrl: freescale: Add i.MX8MN pinctrl driver support
From: Anson Huang
Add the pinctrl driver support for i.MX8MN.
Signed-off-by: Anson Huang
Acked-by: Dong Aisheng
---
Changes since V1:
- Fix some nitpicks like sorting the change in alphabet order
and improve the headfile included.
---
drivers/pinctrl/freescale/Kconfig | 7 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx8mn.c | 348 +
3 files changed, 356 insertions(+)
create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8mn.c
diff --git a/drivers/pinctrl/freescale/Kconfig
b/drivers/pinctrl/freescale/Kconfig
index aeab0d9..5f40580 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -130,6 +130,13 @@ config PINCTRL_IMX8MM
help
Say Y here to enable the imx8mm pinctrl driver
+config PINCTRL_IMX8MN
+ bool "IMX8MN pinctrl driver"
+ depends on ARCH_MXC && ARM64
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx8mn pinctrl driver
+
config PINCTRL_IMX8MQ
bool "IMX8MQ pinctrl driver"
depends on ARCH_MXC && ARM64
diff --git a/drivers/pinctrl/freescale/Makefile
b/drivers/pinctrl/freescale/Makefile
index 02020a7..78e9140 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D)+= pinctrl-imx7d.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
obj-$(CONFIG_PINCTRL_IMX8MM) += pinctrl-imx8mm.o
+obj-$(CONFIG_PINCTRL_IMX8MN) += pinctrl-imx8mn.o
obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mn.c
b/drivers/pinctrl/freescale/pinctrl-imx8mn.c
new file mode 100644
index 000..100ed8c
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx8mn.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-imx.h"
+
+enum imx8mn_pads {
+ MX8MN_PAD_RESERVE0 = 0,
+ MX8MN_PAD_RESERVE1 = 1,
+ MX8MN_PAD_RESERVE2 = 2,
+ MX8MN_PAD_RESERVE3 = 3,
+ MX8MN_PAD_RESERVE4 = 4,
+ MX8MN_PAD_RESERVE5 = 5,
+ MX8MN_PAD_RESERVE6 = 6,
+ MX8MN_PAD_RESERVE7 = 7,
+ MX8MN_IOMUXC_BOOT_MODE2 = 8,
+ MX8MN_IOMUXC_BOOT_MODE3 = 9,
+ MX8MN_IOMUXC_GPIO1_IO00 = 10,
+ MX8MN_IOMUXC_GPIO1_IO01 = 11,
+ MX8MN_IOMUXC_GPIO1_IO02 = 12,
+ MX8MN_IOMUXC_GPIO1_IO03 = 13,
+ MX8MN_IOMUXC_GPIO1_IO04 = 14,
+ MX8MN_IOMUXC_GPIO1_IO05 = 15,
+ MX8MN_IOMUXC_GPIO1_IO06 = 16,
+ MX8MN_IOMUXC_GPIO1_IO07 = 17,
+ MX8MN_IOMUXC_GPIO1_IO08 = 18,
+ MX8MN_IOMUXC_GPIO1_IO09 = 19,
+ MX8MN_IOMUXC_GPIO1_IO10 = 20,
+ MX8MN_IOMUXC_GPIO1_IO11 = 21,
+ MX8MN_IOMUXC_GPIO1_IO12 = 22,
+ MX8MN_IOMUXC_GPIO1_IO13 = 23,
+ MX8MN_IOMUXC_GPIO1_IO14 = 24,
+ MX8MN_IOMUXC_GPIO1_IO15 = 25,
+ MX8MN_IOMUXC_ENET_MDC = 26,
+ MX8MN_IOMUXC_ENET_MDIO = 27,
+ MX8MN_IOMUXC_ENET_TD3 = 28,
+ MX8MN_IOMUXC_ENET_TD2 = 29,
+ MX8MN_IOMUXC_ENET_TD1 = 30,
+ MX8MN_IOMUXC_ENET_TD0 = 31,
+ MX8MN_IOMUXC_ENET_TX_CTL = 32,
+ MX8MN_IOMUXC_ENET_TXC = 33,
+ MX8MN_IOMUXC_ENET_RX_CTL = 34,
+ MX8MN_IOMUXC_ENET_RXC = 35,
+ MX8MN_IOMUXC_ENET_RD0 = 36,
+ MX8MN_IOMUXC_ENET_RD1 = 37,
+ MX8MN_IOMUXC_ENET_RD2 = 38,
+ MX8MN_IOMUXC_ENET_RD3 = 39,
+ MX8MN_IOMUXC_SD1_CLK = 40,
+ MX8MN_IOMUXC_SD1_CMD = 41,
+ MX8MN_IOMUXC_SD1_DATA0 = 42,
+ MX8MN_IOMUXC_SD1_DATA1 = 43,
+ MX8MN_IOMUXC_SD1_DATA2 = 44,
+ MX8MN_IOMUXC_SD1_DATA3 = 45,
+ MX8MN_IOMUXC_SD1_DATA4 = 46,
+ MX8MN_IOMUXC_SD1_DATA5 = 47,
+ MX8MN_IOMUXC_SD1_DATA6 = 48,
+ MX8MN_IOMUXC_SD1_DATA7 = 49,
+ MX8MN_IOMUXC_SD1_RESET_B = 50,
+ MX8MN_IOMUXC_SD1_STROBE = 51,
+ MX8MN_IOMUXC_SD2_CD_B = 52,
+ MX8MN_IOMUXC_SD2_CLK = 53,
+ MX8MN_IOMUXC_SD2_CMD = 54,
+ MX8MN_IOMUXC_SD2_DATA0 = 55,
+ MX8MN_IOMUXC_SD2_DATA1 = 56,
+ MX8MN_IOMUXC_SD2_DATA2 = 57,
+ MX8MN_IOMUXC_SD2_DATA3 = 58,
+ MX8MN_IOMUXC_SD2_RESET_B = 59,
+ MX8MN_IOMUXC_SD2_WP = 60,
+ MX8MN_IOMUXC_NAND_ALE = 61,
+ MX8MN_IOMUXC_NAND_CE0 = 62,
+ MX8MN_IOMUXC_NAND_CE1 = 63,
+ MX8MN_IOMUXC_NAND_CE2 = 64,
+ MX8MN_IOMUXC_NAND_CE3 = 65,
+ MX8MN_IOMUXC_NAND_CLE = 66,
+ MX8MN_IOMUXC_NAND_DATA00 = 67,
+ MX8MN_IOMUXC_NAND_DATA01 = 68,
+ MX8MN_IOMUXC_NAND_DATA02 = 69,
+ MX8MN_IOMUXC_NAND_DATA03 = 70,
+ MX8MN_IOMUXC_NAND_DATA04 = 71,
+ MX8MN_IOMUXC_NAND_DATA05 = 72,
+ MX8MN_IOMUXC_NAND_DATA06 = 73,
+ MX8MN_IOMUXC_NAND_DATA07 = 74,
+ MX8MN_IOMUXC
[PATCH V2 1/3] dt-bindings: imx: Add pinctrl binding doc for i.MX8MN
From: Anson Huang
Add binding doc for i.MX8MN pinctrl driver.
Signed-off-by: Anson Huang
Acked-by: Dong Aisheng
---
No change.
---
.../bindings/pinctrl/fsl,imx8mn-pinctrl.txt| 39 ++
arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h | 646 +
2 files changed, 685 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt
new file mode 100644
index 000..330716c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt
@@ -0,0 +1,39 @@
+* Freescale IMX8MN IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
+for common binding part and usage.
+
+Required properties:
+- compatible: "fsl,imx8mn-iomuxc"
+- reg: should contain the base physical address and size of the iomuxc
+ registers.
+
+Required properties in sub-nodes:
+- fsl,pins: each entry consists of 6 integers and represents the mux and config
+ setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in
+ . The last integer CONFIG is
+ the pad setting value like pull-up on this pin. Please refer to i.MX8M Nano
+ Reference Manual for detailed CONFIG settings.
+
+Examples:
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_uart1>;
+};
+
+iomuxc: pinctrl@3033 {
+compatible = "fsl,imx8mn-iomuxc";
+reg = <0x0 0x3033 0x0 0x1>;
+
+pinctrl_uart1: uart1grp {
+fsl,pins = <
+ MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
+ MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
+ MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO60x19
+>;
+};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h
b/arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h
new file mode 100644
index 000..faf1e69
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h
@@ -0,0 +1,646 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __DTS_IMX8MN_PINFUNC_H
+#define __DTS_IMX8MN_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ *
+ */
+
+#define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2
0x020 0x25C 0x000 0x0 0x0
+#define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL
0x020 0x25C 0x55C 0x1 0x3
+#define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3
0x024 0x260 0x000 0x0 0x0
+#define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA
0x024 0x260 0x56C 0x1 0x3
+#define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0
0x028 0x290 0x000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT
0x028 0x290 0x000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
0x028 0x290 0x000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1
0x028 0x290 0x000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1
0x02C 0x294 0x000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT
0x02C 0x294 0x000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M
0x02C 0x294 0x000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2
0x02C 0x294 0x000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2
0x030 0x298 0x000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B
0x030 0x298 0x000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY
0x030 0x298 0x000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3
0x034 0x29C 0x000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT
0x034 0x29C 0x000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0
0x034 0x29C 0x000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK
0x034 0x29C 0x000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4
0x038 0x2A0 0x000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
0x038 0x2A0 0x000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1
0x038 0x2A0 0x000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV
[PATCH 3/3] arm64: dts: imx8qxp: Add fallback compatible string for RTC node
From: Anson Huang
The i.MX system controller RTC driver uses generic compatible
string to support all i.MX SoCs with system controller inside,
this patch adds the generic system controller RTC compatible
string as fallback compatible string accordingly.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 12044be..40811a2 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -162,7 +162,7 @@
};
rtc: rtc {
- compatible = "fsl,imx8qxp-sc-rtc";
+ compatible = "fsl,imx8qxp-sc-rtc", "fsl,imx-sc-rtc";
};
watchdog {
--
2.7.4
[PATCH 2/3] rtc: imx-sc: Make compatible string more generic
From: Anson Huang
i.MX system controller RTC driver can support all i.MX SoCs
with system controller inside, this patch makes the compatible
string more generic to support other i.MX SoCs with system
controller inside, such as i.MX8QM etc..
Signed-off-by: Anson Huang
---
drivers/rtc/rtc-imx-sc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-imx-sc.c b/drivers/rtc/rtc-imx-sc.c
index c933045..38ef3ca 100644
--- a/drivers/rtc/rtc-imx-sc.c
+++ b/drivers/rtc/rtc-imx-sc.c
@@ -178,7 +178,7 @@ static int imx_sc_rtc_probe(struct platform_device *pdev)
}
static const struct of_device_id imx_sc_dt_ids[] = {
- { .compatible = "fsl,imx8qxp-sc-rtc", },
+ { .compatible = "fsl,imx-sc-rtc", },
{}
};
MODULE_DEVICE_TABLE(of, imx_sc_dt_ids);
--
2.7.4
[PATCH 1/3] dt-bindings: fsl: scu: Update RTC compatible string
From: Anson Huang
Update RTC compatible string to make system controller RTC
driver more generic for all i.MX SoCs with system controller
inside.
Signed-off-by: Anson Huang
---
This patch should be based on below patch which is already picked by
watchdog maintainer:
https://patchwork.kernel.org/patch/10962183/
---
Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
index fc3844e..7ca20a1 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
@@ -131,7 +131,9 @@ RTC bindings based on SCU Message Protocol
Required properties:
-- compatible: should be "fsl,imx8qxp-sc-rtc";
+- compatible: should be:
+ "fsl,imx8qxp-sc-rtc"
+ followed by "fsl,imx-sc-rtc";
OCOTP bindings based on SCU Message Protocol
@@ -226,7 +228,7 @@ firmware {
};
rtc: rtc {
- compatible = "fsl,imx8qxp-sc-rtc";
+ compatible = "fsl,imx8qxp-sc-rtc", "fsl,imx-sc-rtc";
};
watchdog {
--
2.7.4
RE: [PATCH V3 3/4] clk: imx: Add support for i.MX8MN clock driver
Hi, Stephen
> -Original Message-
> From: Stephen Boyd
> Sent: Monday, June 10, 2019 11:14 PM
> To: bjorn.anders...@linaro.org; catalin.mari...@arm.com;
> devicet...@vger.kernel.org; dingu...@kernel.org;
> enric.balle...@collabora.com; feste...@gmail.com;
> horms+rene...@verge.net.au; ja...@amarulasolutions.com;
> ker...@pengutronix.de; l.st...@pengutronix.de; linux-arm-
> ker...@lists.infradead.org; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; mark.rutl...@arm.com;
> maxime.rip...@bootlin.com; mturque...@baylibre.com; o...@lixom.net;
> robh...@kernel.org; s.hauer@pengutronix .de ;
> shawn...@kernel.org; will.dea...@arm.com; Abel Vesa
> ; Aisheng Dong ; Anson
> Huang ; Jacky Bai ; Leonard
> Crestez
> Cc: dl-linux-imx
> Subject: RE: [PATCH V3 3/4] clk: imx: Add support for i.MX8MN clock driver
>
> Quoting Anson Huang (2019-06-08 02:58:18)
> > Hi, Stephen
> >
> > > -Original Message-
> > > From: Stephen Boyd
> > > Sent: Saturday, June 8, 2019 2:01 AM
> > > To: bjorn.anders...@linaro.org; catalin.mari...@arm.com;
> > > devicet...@vger.kernel.org; dingu...@kernel.org;
> > > enric.balle...@collabora.com; feste...@gmail.com;
> > > horms+rene...@verge.net.au; ja...@amarulasolutions.com;
> > > ker...@pengutronix.de; l.st...@pengutronix.de; linux-arm-
> > > ker...@lists.infradead.org; linux-...@vger.kernel.org; linux-
> > > ker...@vger.kernel.org; mark.rutl...@arm.com;
> > > maxime.rip...@bootlin.com; mturque...@baylibre.com; o...@lixom.net;
> > > robh...@kernel.org; s.hauer@pengutronix .de
> > > robh+;
> > > shawn...@kernel.org; will.dea...@arm.com; Abel Vesa
> > > ; Aisheng Dong ; Anson
> > > Huang ; Jacky Bai ;
> Leonard
> > > Crestez
> > > Cc: dl-linux-imx
> > > Subject: RE: [PATCH V3 3/4] clk: imx: Add support for i.MX8MN clock
> > > driver
> > >
> > > Quoting Anson Huang (2019-06-06 17:50:28)
> > > >
> > > > I will use devm_platform_ioremap_resource() instead of ioremap(),
> > > > and can you be more specific about devmified clk registration?
> > > >
> > >
> > > I mean using things like devm_clk_hw_register().
> >
> > Sorry, I am still a little confused, all the clock
> > register(clk_register()) are via each different clock types like
> > imx_clk_gate4/imx_clk_pll14xx, if using clk_hw_register, means we need
> > to re-write the clock driver using different clk register method, that
> > will make the driver completely different from i.mx8mq/i.mx8mm, they
> > are actually same series of SoC as i.mx8mn, it will introduce many
> confusion, is my understanding correct? And is it OK to just keep what it is
> and make them all aligned?
> >
>
> Ok, the problem I'm trying to point out is that clk registrations need to be
> undone, i.e. clk_unregister() needs to be called, when the driver fails to
> probe. devm_*() is one way to do this, but if you have other ways of
> removing all the registered clks then that works too. Makes sense?
Yes, it makes sense. Do you think it is OK to add an imx_unregister_clocks()
API, then
call it in every place of returning failure in .probe function? If yes, I will
add it and also
fix it in i.MX8MQ driver which uses platform driver model but does NOT handle
this case.
base = devm_platform_ioremap_resource(pdev, 0);
- if (WARN_ON(IS_ERR(base)))
- return PTR_ERR(base);
+ if (WARN_ON(IS_ERR(base))) {
+ ret = PTR_ERR(base);
+ goto unregister_clks;
+ }
pr_err("failed to register clks for i.MX8MN\n");
- return -EINVAL;
+ goto unregister_clks;
}
return 0;
+
+unregister_clks:
+ imx_unregister_clocks(clks, ARRAY_SIZE(clks));
+
+ return ret;
+void imx_unregister_clocks(struct clk *clks[], unsigned int count)
+{
+ unsigned i;
+
+ for (i = 0; i < count; i++)
+ clk_unregister(clks[i]);
+}
+
Thanks,
Anson.
[PATCH] soc: imx: Add i.MX8MN SoC driver support
From: Anson Huang
This patch adds i.MX8MN SoC driver support:
root@imx8mnevk:~# cat /sys/devices/soc0/family
Freescale i.MX
root@imx8mnevk:~# cat /sys/devices/soc0/machine
NXP i.MX8MNano DDR4 EVK board
root@imx8mnevk:~# cat /sys/devices/soc0/soc_id
i.MX8MN
root@imx8mnevk:~# cat /sys/devices/soc0/revision
1.0
Signed-off-by: Anson Huang
---
drivers/soc/imx/soc-imx8.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/imx/soc-imx8.c b/drivers/soc/imx/soc-imx8.c
index 3842d09..02309a2 100644
--- a/drivers/soc/imx/soc-imx8.c
+++ b/drivers/soc/imx/soc-imx8.c
@@ -55,7 +55,12 @@ static u32 __init imx8mm_soc_revision(void)
void __iomem *anatop_base;
u32 rev;
- np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
+ if (of_machine_is_compatible("fsl,imx8mm"))
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
+ else if (of_machine_is_compatible("fsl,imx8mn"))
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
+ else
+ np = NULL;
if (!np)
return 0;
@@ -79,9 +84,15 @@ static const struct imx8_soc_data imx8mm_soc_data = {
.soc_revision = imx8mm_soc_revision,
};
+static const struct imx8_soc_data imx8mn_soc_data = {
+ .name = "i.MX8MN",
+ .soc_revision = imx8mm_soc_revision,
+};
+
static const struct of_device_id imx8_soc_match[] = {
{ .compatible = "fsl,imx8mq", .data = _soc_data, },
{ .compatible = "fsl,imx8mm", .data = _soc_data, },
+ { .compatible = "fsl,imx8mn", .data = _soc_data, },
{ }
};
--
2.7.4
RE: [RESEND] input: keyboard: imx: make sure keyboard can always wake up system
Hi, Dmitry Any feedback for this patch? Thanks, Anson > -Original Message- > From: Anson Huang > Sent: Tuesday, May 21, 2019 2:36 PM > To: dmitry.torok...@gmail.com > Cc: shawn...@kernel.org; s.ha...@pengutronix.de; > ker...@pengutronix.de; feste...@gmail.com; linux-in...@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org; dl-linux- > imx > Subject: RE: [RESEND] input: keyboard: imx: make sure keyboard can always > wake up system > > Hi, Dmitry > > > -Original Message- > > From: dmitry.torok...@gmail.com [mailto:dmitry.torok...@gmail.com] > > Sent: Tuesday, May 21, 2019 1:31 PM > > To: Anson Huang > > Cc: shawn...@kernel.org; s.ha...@pengutronix.de; > > ker...@pengutronix.de; feste...@gmail.com; > > linux-in...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > > linux-kernel@vger.kernel.org; dl-linux- imx > > Subject: Re: [RESEND] input: keyboard: imx: make sure keyboard can > > always wake up system > > > > Hi Anson, > > On Thu, Apr 04, 2019 at 01:40:16AM +, Anson Huang wrote: > > > There are several scenarios that keyboard can NOT wake up system > > > from suspend, e.g., if a keyboard is depressed between system device > > > suspend phase and device noirq suspend phase, the keyboard ISR will > > > be called and both keyboard depress and release interrupts will be > > > disabled, then keyboard will no longer be able to wake up system. > > > Another scenario would be, if a keyboard is kept depressed, and then > > > system goes into suspend, the expected behavior would be when > > > keyboard is released, system will be waked up, but current > > > implementation can NOT achieve that, because both depress and > > > release interrupts are disabled in ISR, and the event check is still in > progress. > > > > > > To fix these issues, need to make sure keyboard's depress or release > > > interrupt is enabled after noirq device suspend phase, this patch > > > moves the suspend/resume callback to noirq suspend/resume phase, > and > > > enable the corresponding interrupt according to current keyboard status. > > > > I believe it is possible for IRQ to be disabled and still being > > enabled as wakeup source. What happens if you call disable_irq() > > before disabling the clock? > > Doing below does NOT fix the scenario/issue 100%, if the keypad's IRQ > arrived during suspend phase but before disabling its IRQ in its suspend > callback, then issue is still there, as the issue is that when system suspend, > keypad's irq arrived during suspend and noirq suspend phase, then keypad's > hardware interrupt detection will be disabled in the ISR handler, and the > timer event setup by ISR handler is NOT fired, > imx_keypad_check_for_events() is NOT executed and hardware keypad's > depress/release interrupt is NOT re-enabled yet, so it can NOT wake up > system anymore... > > So I think the solid fix is to make sure keypad can generate IRQ (either > depress or release) at any time during system suspend flow. > > +++ b/drivers/input/keyboard/imx_keypad.c > @@ -533,6 +533,8 @@ static int __maybe_unused imx_kbd_suspend(struct > device *dev) > /* imx kbd can wake up system even clock is disabled */ > mutex_lock(_dev->mutex); > > + disable_irq(kbd->irq); > + > if (input_dev->users) > clk_disable_unprepare(kbd->clk); > > > @@ -562,6 +569,8 @@ static int __maybe_unused imx_kbd_resume(struct > device *dev) > goto err_clk; > } > > + enable_irq(kbd->irq); > + > err_clk: > > Anson. > > > > > Thanks. > > > > -- > > Dmitry
[PATCH] clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap()
From: Anson Huang
i.MX8MQ clock driver uses platform driver model, better to use
devm_platform_ioremap_resource() instead of of_iomap() to get
IO base.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx8mq.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 1292241..7da1edb 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -361,9 +361,9 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
clks[IMX8MQ_SYS2_PLL_1000M] = imx_clk_fixed_factor("sys2_pll_1000m",
"sys2_pll_out", 1, 1);
np = dev->of_node;
- base = of_iomap(np, 0);
- if (WARN_ON(!base))
- return -ENOMEM;
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (WARN_ON(IS_ERR(base)))
+ return PTR_ERR(base);
/* CORE */
clks[IMX8MQ_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000,
24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
--
2.7.4
[PATCH 1/2] clk: imx: Remove __init for imx_check_clocks() API
From: Anson Huang
Some of i.MX SoCs' clock driver use platform driver model,
and they need to call imx_check_clocks() API, so
imx_check_clocks() API should NOT be in .init section.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index 9cd7097..b1416b2 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -23,7 +23,7 @@ void __init imx_mmdc_mask_handshake(void __iomem *ccm_base,
writel_relaxed(reg, ccm_base + CCM_CCDR);
}
-void __init imx_check_clocks(struct clk *clks[], unsigned int count)
+void imx_check_clocks(struct clk *clks[], unsigned int count)
{
unsigned i;
--
2.7.4
[PATCH 2/2] clk: imx8mq: Use imx_check_clocks() API directly
From: Anson Huang
Use imx_check_clocks() API to check clocks directly.
Signed-off-by: Anson Huang
---
drivers/clk/imx/clk-imx8mq.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 7da1edb..5fbc2a7 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -278,7 +278,6 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
struct device_node *np = dev->of_node;
void __iomem *base;
int err;
- int i;
clks[IMX8MQ_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
clks[IMX8MQ_CLK_32K] = of_clk_get_by_name(np, "ckil");
@@ -548,10 +547,7 @@ static int imx8mq_clocks_probe(struct platform_device
*pdev)
clks[IMX8MQ_ARM_PLL_OUT],
clks[IMX8MQ_SYS1_PLL_800M]);
- for (i = 0; i < IMX8MQ_CLK_END; i++)
- if (IS_ERR(clks[i]))
- pr_err("i.MX8mq clk %u register failed with %ld\n",
- i, PTR_ERR(clks[i]));
+ imx_check_clocks(clks, ARRAY_SIZE(clks));
clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks);
--
2.7.4
RE: [PATCH RESEND V13 2/5] thermal: of-thermal: add API for getting sensor ID from DT
Hi, Eduardo > -Original Message- > From: Anson Huang > Sent: Wednesday, May 29, 2019 11:37 AM > To: Eduardo Valentin > Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; > s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com; > catalin.mari...@arm.com; will.dea...@arm.com; rui.zh...@intel.com; > daniel.lezc...@linaro.org; Aisheng Dong ; > ulf.hans...@linaro.org; Peng Fan ; Daniel Baluta > ; maxime.rip...@bootlin.com; o...@lixom.net; > ja...@amarulasolutions.com; horms+rene...@verge.net.au; Leonard > Crestez ; bjorn.anders...@linaro.org; > dingu...@kernel.org; enric.balle...@collabora.com; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux...@vger.kernel.org; dl-linux-imx i...@nxp.com> > Subject: RE: [PATCH RESEND V13 2/5] thermal: of-thermal: add API for getting > sensor ID from DT > > Hi, Eduardo > > > -Original Message- > > From: Eduardo Valentin > > Sent: Wednesday, May 29, 2019 11:02 AM > > To: Anson Huang > > Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; > > s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com; > > catalin.mari...@arm.com; will.dea...@arm.com; rui.zh...@intel.com; > > daniel.lezc...@linaro.org; Aisheng Dong ; > > ulf.hans...@linaro.org; Peng Fan ; Daniel Baluta > > ; maxime.rip...@bootlin.com; o...@lixom.net; > > ja...@amarulasolutions.com; horms+rene...@verge.net.au; Leonard > > Crestez ; bjorn.anders...@linaro.org; > > dingu...@kernel.org; enric.balle...@collabora.com; > > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- > > ker...@lists.infradead.org; linux...@vger.kernel.org; dl-linux-imx > > > > Subject: Re: [PATCH RESEND V13 2/5] thermal: of-thermal: add API for > > getting sensor ID from DT > > > > On Tue, May 28, 2019 at 02:06:18PM +0800, anson.hu...@nxp.com wrote: > > > From: Anson Huang > > > > > > On some platforms like i.MX8QXP, the thermal driver needs a real HW > > > sensor ID from DT thermal zone, the HW sensor ID is used to get > > > temperature from SCU firmware, and the virtual sensor ID starting > > > from > > > 0 to N is NOT used at all, this patch adds new API > > > thermal_zone_of_get_sensor_id() to provide the feature of getting > > > sensor ID from DT thermal zone's node. > > > > > > Signed-off-by: Anson Huang > > > --- > > > Changes since V12: > > > - adjust the second parameter of thermal_zone_of_get_sensor_id() > > > API, > > then caller no need > > > to pass the of_phandle_args structure and put the sensor_specs.np > > manually, also putting > > > the sensor node device check inside this API to make it easy for > > > usage; > > > > What happened to using nxp,resource-id property in your driver? > > Why do we need this as an API in of-thermal? What other drivers may > > benefit of this? > > > > Regardless, this patch needs to document the new API under > > Documentation/ > > As Rob has different opinion about this property, he thought it is > unnecessary, see below discussion mail, that is why I need to add API to get > the resource ID from phandle argument. > I am totally confused now, which approach should we adopt? > > https://patchwork.kernel.org/patch/10831397/ I will add the new API document in V14, I remembered that there is also other vendors have similar sensor HW ID as i.MX8QXP, instead of adding private properties for each vendor, adding an API to read out the sensor ID can benefit us a lot I think. Thanks, Anson > > Thanks, > Anson > > > > > > --- > > > drivers/thermal/of-thermal.c | 66 > > > +--- > > > > > include/linux/thermal.h | 10 +++ > > > 2 files changed, 60 insertions(+), 16 deletions(-) > > > > > > diff --git a/drivers/thermal/of-thermal.c > > > b/drivers/thermal/of-thermal.c index dc5093b..a53792b 100644 > > > --- a/drivers/thermal/of-thermal.c > > > +++ b/drivers/thermal/of-thermal.c > > > @@ -449,6 +449,54 @@ thermal_zone_of_add_sensor(struct > device_node > > > *zone, } > > > > > > /** > > > + * thermal_zone_of_get_sensor_id - get sensor ID from a DT thermal > > > + zone > > > + * @tz_np: a valid thermal zone device node. > > > + * @sensor_np: a sensor node of a valid sensor device. > > > + * @id: a sensor ID pointer will be passed back. > > > + * > > > + *
RE: [PATCH V3 3/4] clk: imx: Add support for i.MX8MN clock driver
Hi, Stephen > -Original Message- > From: Stephen Boyd > Sent: Saturday, June 8, 2019 2:01 AM > To: bjorn.anders...@linaro.org; catalin.mari...@arm.com; > devicet...@vger.kernel.org; dingu...@kernel.org; > enric.balle...@collabora.com; feste...@gmail.com; > horms+rene...@verge.net.au; ja...@amarulasolutions.com; > ker...@pengutronix.de; l.st...@pengutronix.de; linux-arm- > ker...@lists.infradead.org; linux-...@vger.kernel.org; linux- > ker...@vger.kernel.org; mark.rutl...@arm.com; > maxime.rip...@bootlin.com; mturque...@baylibre.com; o...@lixom.net; > robh...@kernel.org; s.hauer@pengutronix .de ; > shawn...@kernel.org; will.dea...@arm.com; Abel Vesa > ; Aisheng Dong ; Anson > Huang ; Jacky Bai ; Leonard > Crestez > Cc: dl-linux-imx > Subject: RE: [PATCH V3 3/4] clk: imx: Add support for i.MX8MN clock driver > > Quoting Anson Huang (2019-06-06 17:50:28) > > > > I will use devm_platform_ioremap_resource() instead of ioremap(), and > > can you be more specific about devmified clk registration? > > > > I mean using things like devm_clk_hw_register(). Sorry, I am still a little confused, all the clock register(clk_register()) are via each different clock types like imx_clk_gate4/imx_clk_pll14xx, if using clk_hw_register, means we need to re-write the clock driver using different clk register method, that will make the driver completely different from i.mx8mq/i.mx8mm, they are actually same series of SoC as i.mx8mn, it will introduce many confusion, is my understanding correct? And is it OK to just keep what it is and make them all aligned? Thanks, Anson.
RE: [PATCH RESEND V4 3/3] watchdog: imx_sc: Add pretimeout support
Hi, Guenter > -Original Message- > From: Guenter Roeck On Behalf Of Guenter Roeck > Sent: Saturday, June 8, 2019 1:41 AM > To: Anson Huang > Cc: robh...@kernel.org; mark.rutl...@arm.com; w...@linux-watchdog.org; > shawn...@kernel.org; s.ha...@pengutronix.de; ker...@pengutronix.de; > feste...@gmail.com; Aisheng Dong ; > ulf.hans...@linaro.org; Daniel Baluta ; Peng Fan > ; devicet...@vger.kernel.org; linux- > ker...@vger.kernel.org; linux-watch...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; dl-linux-imx > Subject: Re: [PATCH RESEND V4 3/3] watchdog: imx_sc: Add pretimeout > support > > On Wed, Jun 05, 2019 at 06:24:33AM +, Anson Huang wrote: > > Hi, Guenter > > > > > -Original Message- > > > From: Guenter Roeck On Behalf Of Guenter Roeck > > > Sent: Sunday, May 12, 2019 9:28 PM > > > To: Anson Huang ; robh...@kernel.org; > > > mark.rutl...@arm.com; w...@linux-watchdog.org; > shawn...@kernel.org; > > > s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com; > > > Aisheng Dong ; ulf.hans...@linaro.org; Daniel > > > Baluta ; Peng Fan ; > > > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux- > > > watch...@vger.kernel.org; linux-arm-ker...@lists.infradead.org > > > Cc: dl-linux-imx > > > Subject: Re: [PATCH RESEND V4 3/3] watchdog: imx_sc: Add pretimeout > > > support > > > > > > On 5/12/19 3:10 AM, Anson Huang wrote: > > > > i.MX system controller watchdog can support pretimeout IRQ via > > > > general SCU MU IRQ, it depends on IMX_SCU and driver MUST be > > > > probed after SCU IPC ready, then enable corresponding SCU IRQ > > > > group and register SCU IRQ notifier, when watchdog pretimeout IRQ > > > > fires, SCU MU IRQ will be handled and watchdog pretimeout notifier > > > > will be called to handle the event. > > > > > > > > Signed-off-by: Anson Huang > > > > > > Revviewed-by: Guenter Roeck > > > > > > Other patches waiting for DT review. IMX API feedback below. > > > > Shaw just picked up the DT patch. Would you please pick up this driver > > and dt-binding patch to you git repo? > > > I'll pick up patch 3/3, but I can not pick up patches into arch/arm64/boot/; > that is the responsibility of arm64 maintainers. I can only do that if I get > an > explicit Ack and permission to do so from an arm64 maintainer, and I don't > recall getting that. Will you also pick up 1/3, the DT binding patch, as DT binding normally go with driver, if NOT, please advise who should pick up this patch. Thanks, Anson. > > Guenter > > > Thanks, > > Anson > > > > > > > > Side note: This patch depends on 'firmware: imx: enable imx scu > > > general irq function' which is not yet in mainline. > > > > > > > --- > > > > No change, just resend patch with correct encoding. > > > > --- > > > > drivers/watchdog/Kconfig | 1 + > > > > drivers/watchdog/imx_sc_wdt.c | 116 > > > +++--- > > > > 2 files changed, 98 insertions(+), 19 deletions(-) > > > > > > > > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > > > > index 7ea6037..e08238c 100644 > > > > --- a/drivers/watchdog/Kconfig > > > > +++ b/drivers/watchdog/Kconfig > > > > @@ -716,6 +716,7 @@ config IMX2_WDT > > > > config IMX_SC_WDT > > > > tristate "IMX SC Watchdog" > > > > depends on HAVE_ARM_SMCCC > > > > + depends on IMX_SCU > > > > select WATCHDOG_CORE > > > > help > > > > This is the driver for the system controller watchdog diff > > > > --git a/drivers/watchdog/imx_sc_wdt.c > > > > b/drivers/watchdog/imx_sc_wdt.c index 49848b6..6ecc03f 100644 > > > > --- a/drivers/watchdog/imx_sc_wdt.c > > > > +++ b/drivers/watchdog/imx_sc_wdt.c > > > > @@ -4,6 +4,7 @@ > > > >*/ > > > > > > > > #include > > > > +#include > > > > #include > > > > #include > > > > #include > > > > @@ -33,11 +34,19 @@ > > > > > > > > #define SC_TIMER_WDOG_ACTION_PARTITION0 > > > > > > > > +#define SC_IRQ_WDOG1 > > > > +#define SC_IRQ_GROUP_WDOG 1 > > > > + > > > >
RE: [PATCH V3 3/4] clk: imx: Add support for i.MX8MN clock driver
Hi, Stephen > -Original Message- > From: Stephen Boyd > Sent: Friday, June 7, 2019 12:26 AM > To: Anson Huang ; Abel Vesa > ; Aisheng Dong ; > bjorn.anders...@linaro.org; catalin.mari...@arm.com; > devicet...@vger.kernel.org; dingu...@kernel.org; > enric.balle...@collabora.com; feste...@gmail.com; > horms+rene...@verge.net.au; ja...@amarulasolutions.com; > ker...@pengutronix.de; l.st...@pengutronix.de; Leonard Crestez > ; linux-arm-ker...@lists.infradead.org; linux- > c...@vger.kernel.org; linux-kernel@vger.kernel.org; mark.rutl...@arm.com; > maxime.rip...@bootlin.com; mturque...@baylibre.com; o...@lixom.net; > Jacky Bai ; robh...@kernel.org; > s.ha...@pengutronix.de; shawn...@kernel.org; will.dea...@arm.com > Cc: dl-linux-imx > Subject: Re: [PATCH V3 3/4] clk: imx: Add support for i.MX8MN clock driver > > Quoting anson.hu...@nxp.com (2019-06-03 18:59:27) > > From: Anson Huang > > > > This patch adds i.MX8MN clock driver support. > > > > Signed-off-by: Anson Huang > > --- > > Changes since V2: > > - use platform driver model for this clock driver; > > Can you also use platform device APIs like platform_*(), > devm_ioremap_resource() and devmified clk registration? I will use devm_platform_ioremap_resource() instead of ioremap(), and can you be more specific about devmified clk registration? Thanks, Anson
RE: [PATCH V4 1/4] dt-bindings: imx: Add clock binding doc for i.MX8MN
Hi, Maxime
> -Original Message-
> From: Maxime Ripard
> Sent: Thursday, June 6, 2019 3:41 PM
> To: Anson Huang
> Cc: mturque...@baylibre.com; sb...@kernel.org; robh...@kernel.org;
> mark.rutl...@arm.com; shawn...@kernel.org; s.ha...@pengutronix.de;
> ker...@pengutronix.de; feste...@gmail.com; catalin.mari...@arm.com;
> will.dea...@arm.com; o...@lixom.net; ja...@amarulasolutions.com;
> horms+rene...@verge.net.au; bjorn.anders...@linaro.org; Leonard Crestez
> ; dingu...@kernel.org;
> enric.balle...@collabora.com; Aisheng Dong ;
> Abel Vesa ; Jacky Bai ;
> l.st...@pengutronix.de; Peng Fan ; linux-
> c...@vger.kernel.org; devicet...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; dl-linux-imx
>
> Subject: Re: [PATCH V4 1/4] dt-bindings: imx: Add clock binding doc for
> i.MX8MN
>
> Hi,
>
> On Thu, Jun 06, 2019 at 09:33:20AM +0800, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > Add the clock binding doc for i.MX8MN.
> >
> > Signed-off-by: Anson Huang
> > ---
> > Changes since V3:
> > - switch binding doc from .txt to .yaml.
> > ---
> > .../devicetree/bindings/clock/imx8mn-clock.yaml| 115 +++
> > include/dt-bindings/clock/imx8mn-clock.h | 215
> +
> > 2 files changed, 330 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
> > create mode 100644 include/dt-bindings/clock/imx8mn-clock.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
> > b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
> > new file mode 100644
> > index 000..8cb8fcf
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
> > @@ -0,0 +1,115 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NXP i.MX8M Nano Clock Control Module Binding
> > +
> > +maintainers:
> > + - Anson Huang
> > +
> > +description: |
> > + NXP i.MX8M Nano clock control module is an integrated clock
> > +controller, which
> > + generates and supplies to all modules.
> > +
> > + This binding uses common clock bindings [1]
> > + Documentation/devicetree/bindings/clock/clock-bindings.txt
>
> Which part exactly are you using?
>
> I'm not sure it's worth referring to. Any provider property should be listed
> here, and the consumer properties are already checked.
Agreed, I will remove this reference statement in next version.
>
> > +properties:
> > + compatible:
> > +const: fsl,imx8mn-ccm
> > +
> > + reg:
> > +maxItems: 1
> > +
> > + clocks:
> > +items:
> > + - description: 32k osc
> > + - description: 24m osc
> > + - description: ext1 clock input
> > + - description: ext2 clock input
> > + - description: ext3 clock input
> > + - description: ext4 clock input
> > +
> > + clock-names:
> > +items:
> > + - const: osc_32k
> > + - const: osc_24m
> > + - const: clk_ext1
> > + - const: clk_ext2
> > + - const: clk_ext3
> > + - const: clk_ext4
> > +
> > + '#clock-cells':
> > +const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - '#clock-cells'
> > +
> > +examples:
> > + # Clock Control Module node:
> > + - |
> > +clk: clock-controller@3038 {
> > +compatible = "fsl,imx8mn-ccm";
> > +reg = <0x0 0x3038 0x0 0x1>;
> > +#clock-cells = <1>;
> > +clocks = <_32k>, <_24m>, <_ext1>,
> > + <_ext2>, <_ext3>, <_ext4>;
> > +clock-names = "osc_32k", "osc_24m", "clk_ext1",
> > + "clk_ext2", "clk_ext3", "clk_ext4";
> > +};
> > +
> > + # Required external clocks for Clock Control Module node:
> > + - |
> > +osc_32k: clock-osc-32k {
> > +compatible = "fixed-clock";
> > +#clock-cells = <0>;
> > +clock-frequency = <32768>;
> > + clock-output-names = "osc_32k";
> > +};
> > +
> > +osc_24m: clock-osc-24m {
> >
RE: [PATCH] arm64: dts: imx8mm: Move gic node into soc node
Hi, Shawn
> -Original Message-
> From: Shawn Guo
> Sent: Thursday, June 6, 2019 10:18 AM
> To: Anson Huang
> Cc: robh...@kernel.org; mark.rutl...@arm.com; s.ha...@pengutronix.de;
> ker...@pengutronix.de; feste...@gmail.com; Leonard Crestez
> ; Aisheng Dong ;
> viresh.ku...@linaro.org; Jacky Bai ;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; dl-linux-imx
> Subject: Re: [PATCH] arm64: dts: imx8mm: Move gic node into soc node
>
> On Mon, Jun 03, 2019 at 09:50:20AM +0800, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > GIC is inside of SoC from architecture perspective, it should be
> > located inside of soc node in DT.
> >
> > Signed-off-by: Anson Huang
>
> It doesn't apply to my imx/dt64 branch. Please generate it against that
> branch for my for-next.
OK, just resent the patch based on the correct branch.
Thanks,
Anson.
>
> Shawn
>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 18 +-
> > 1 file changed, 9 insertions(+), 9 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > index dc99f45..429312e 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > @@ -169,15 +169,6 @@
> > clock-output-names = "clk_ext4";
> > };
> >
> > - gic: interrupt-controller@3880 {
> > - compatible = "arm,gic-v3";
> > - reg = <0x0 0x3880 0 0x1>, /* GIC Dist */
> > - <0x0 0x3888 0 0xC>; /* GICR (RD_base +
> SGI_base) */
> > - #interrupt-cells = <3>;
> > - interrupt-controller;
> > - interrupts = ;
> > - };
> > -
> > psci {
> > compatible = "arm,psci-1.0";
> > method = "smc";
> > @@ -739,6 +730,15 @@
> > dma-names = "rx-tx";
> > status = "disabled";
> > };
> > +
> > + gic: interrupt-controller@3880 {
> > + compatible = "arm,gic-v3";
> > + reg = <0x3880 0x1>, /* GIC Dist */
> > + <0x3888 0xc>; /* GICR (RD_base +
> SGI_base) */
> > + #interrupt-cells = <3>;
> > + interrupt-controller;
> > + interrupts = ;
> > + };
> > };
> >
> > usbphynop1: usbphynop1 {
> > --
> > 2.7.4
> >
[PATCH RESEND] arm64: dts: imx8mm: Move gic node into soc node
From: Anson Huang
GIC is inside of SoC from architecture perspective, it should
be located inside of soc node in DT.
Signed-off-by: Anson Huang
---
Resend the patch based on Shawn's imx/dt64 branch.
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 2128644..dcae59d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -169,15 +169,6 @@
clock-output-names = "clk_ext4";
};
- gic: interrupt-controller@3880 {
- compatible = "arm,gic-v3";
- reg = <0x0 0x3880 0 0x1>, /* GIC Dist */
- <0x0 0x3888 0 0xC>; /* GICR (RD_base + SGI_base)
*/
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupts = ;
- };
-
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -810,5 +801,14 @@
dma-names = "rx-tx";
status = "disabled";
};
+
+ gic: interrupt-controller@3880 {
+ compatible = "arm,gic-v3";
+ reg = <0x3880 0x1>, /* GIC Dist */
+ <0x3888 0xc>; /* GICR (RD_base +
SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = ;
+ };
};
};
--
2.7.4
[PATCH V4 4/4] arm64: defconfig: Select CONFIG_CLK_IMX8MN by default
From: Anson Huang Enable CONFIG_CLK_IMX8MN to support i.MX8MN clock driver. Signed-off-by: Anson Huang --- No changes. --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8d4f25c..ae17f45 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -655,6 +655,7 @@ CONFIG_COMMON_CLK_S2MPS11=y CONFIG_CLK_QORIQ=y CONFIG_COMMON_CLK_PWM=y CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y CONFIG_CLK_IMX8MQ=y CONFIG_CLK_IMX8QXP=y CONFIG_TI_SCI_CLK=y -- 2.7.4
[PATCH V4 1/4] dt-bindings: imx: Add clock binding doc for i.MX8MN
From: Anson Huang
Add the clock binding doc for i.MX8MN.
Signed-off-by: Anson Huang
---
Changes since V3:
- switch binding doc from .txt to .yaml.
---
.../devicetree/bindings/clock/imx8mn-clock.yaml| 115 +++
include/dt-bindings/clock/imx8mn-clock.h | 215 +
2 files changed, 330 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
create mode 100644 include/dt-bindings/clock/imx8mn-clock.h
diff --git a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
new file mode 100644
index 000..8cb8fcf
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8M Nano Clock Control Module Binding
+
+maintainers:
+ - Anson Huang
+
+description: |
+ NXP i.MX8M Nano clock control module is an integrated clock controller, which
+ generates and supplies to all modules.
+
+ This binding uses common clock bindings
+ [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+properties:
+ compatible:
+const: fsl,imx8mn-ccm
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: 32k osc
+ - description: 24m osc
+ - description: ext1 clock input
+ - description: ext2 clock input
+ - description: ext3 clock input
+ - description: ext4 clock input
+
+ clock-names:
+items:
+ - const: osc_32k
+ - const: osc_24m
+ - const: clk_ext1
+ - const: clk_ext2
+ - const: clk_ext3
+ - const: clk_ext4
+
+ '#clock-cells':
+const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+examples:
+ # Clock Control Module node:
+ - |
+clk: clock-controller@3038 {
+compatible = "fsl,imx8mn-ccm";
+reg = <0x0 0x3038 0x0 0x1>;
+#clock-cells = <1>;
+clocks = <_32k>, <_24m>, <_ext1>,
+ <_ext2>, <_ext3>, <_ext4>;
+clock-names = "osc_32k", "osc_24m", "clk_ext1",
+ "clk_ext2", "clk_ext3", "clk_ext4";
+};
+
+ # Required external clocks for Clock Control Module node:
+ - |
+osc_32k: clock-osc-32k {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+};
+
+osc_24m: clock-osc-24m {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <2400>;
+clock-output-names = "osc_24m";
+};
+
+clk_ext1: clock-ext1 {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <13300>;
+clock-output-names = "clk_ext1";
+};
+
+clk_ext2: clock-ext2 {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <13300>;
+clock-output-names = "clk_ext2";
+};
+
+clk_ext3: clock-ext3 {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency = <13300>;
+clock-output-names = "clk_ext3";
+};
+
+clk_ext4: clock-ext4 {
+compatible = "fixed-clock";
+#clock-cells = <0>;
+clock-frequency= <13300>;
+clock-output-names = "clk_ext4";
+};
+
+ # The clock consumer should specify the desired clock by having the clock
+ # ID in its "clocks" phandle cell. See
include/dt-bindings/clock/imx8mn-clock.h
+ # for the full list of i.MX8M Nano clock IDs.
+
+...
diff --git a/include/dt-bindings/clock/imx8mn-clock.h
b/include/dt-bindings/clock/imx8mn-clock.h
new file mode 100644
index 000..5255b1c
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
+#define __DT_BINDINGS_CLOCK_IMX8MN_H
+
+#define IMX8MN_CLK_DUMMY 0
+#define IMX8MN_CLK_32K 1
+#define IMX8MN_CLK_24M 2
+#define IMX8MN_OSC_HDMI_CLK3
+#define IMX8MN_CLK_EXT14
+#define IMX8MN_CLK_EXT25
+#define IMX8MN_CLK_EXT36
+#define IMX8MN_CLK_EXT47
+#define IMX8MN_AUDIO_PLL1_REF_SEL 8
+#define IMX8MN_AUDIO_PLL2_REF_SEL 9
+#define IMX8MN_VIDEO_PLL1_REF_SEL
[PATCH V4 2/4] clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage
From: Anson Huang
1416X/1443X PLL are used on i.MX8MM and i.MX8MN and maybe
other i.MX8M series SoC later, the macro definitions of
these PLLs' initialization should be common for usage.
Signed-off-by: Anson Huang
---
No changes.
---
drivers/clk/imx/clk-imx8mm.c | 17 -
drivers/clk/imx/clk.h| 17 +
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index eb9fcf0..fecb3b2 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -26,23 +26,6 @@ static u32 share_count_dcss;
static u32 share_count_pdm;
static u32 share_count_nand;
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- .kdiv = (_k), \
- }
-
static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
PLL_1416X_RATE(18U, 225, 3, 0),
PLL_1416X_RATE(16U, 200, 3, 0),
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 6dcdc91..ac8c4ae 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -81,6 +81,23 @@ enum imx_pllv3_type {
IMX_PLLV3_AV_IMX7,
};
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent_name, void __iomem *base, u32 div_mask);
--
2.7.4
[PATCH V4 3/4] clk: imx: Add support for i.MX8MN clock driver
From: Anson Huang
This patch adds i.MX8MN clock driver support.
Signed-off-by: Anson Huang
---
No changes.
---
drivers/clk/imx/Kconfig | 6 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx8mn.c | 630 +++
3 files changed, 637 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mn.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 0eaf418..1ac0c79 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -14,6 +14,12 @@ config CLK_IMX8MM
help
Build the driver for i.MX8MM CCM Clock Driver
+config CLK_IMX8MN
+ bool "IMX8MN CCM Clock Driver"
+ depends on ARCH_MXC && ARM64
+ help
+ Build the driver for i.MX8MN CCM Clock Driver
+
config CLK_IMX8MQ
bool "IMX8MQ CCM Clock Driver"
depends on ARCH_MXC && ARM64
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 05641c6..77a3d71 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_MXC_CLK_SCU) += \
clk-lpcg-scu.o
obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
+obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
new file mode 100644
index 000..3f09974
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -0,0 +1,630 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018-2019 NXP.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static u32 share_count_sai2;
+static u32 share_count_sai3;
+static u32 share_count_sai5;
+static u32 share_count_sai6;
+static u32 share_count_sai7;
+static u32 share_count_disp;
+static u32 share_count_pdm;
+static u32 share_count_nand;
+
+enum {
+ ARM_PLL,
+ GPU_PLL,
+ VPU_PLL,
+ SYS_PLL1,
+ SYS_PLL2,
+ SYS_PLL3,
+ DRAM_PLL,
+ AUDIO_PLL1,
+ AUDIO_PLL2,
+ VIDEO_PLL2,
+ NR_PLLS,
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
+ PLL_1443X_RATE(786432000U, 655, 5, 2, 23593),
+ PLL_1443X_RATE(722534400U, 301, 5, 1, 3670),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(59400U, 198, 2, 2, 0),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+};
+
+static struct imx_pll14xx_clk imx8mn_audio_pll = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_audiopll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_video_pll = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_videopll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_dram_pll = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_drampll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_arm_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_gpu_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_vpu_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_sys_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy",
"dummy", };
+static const char * const audio_pll1_bypass_sels[] = {"audio_pll1",
"audio_pll1_ref_sel", };
+static const char * const audio_pll2_bypass_sels[] = {"audio_pll2",
"audio_pll2_ref_sel", };
+static const char * const video_pll1_bypass_sels[] = {"video_pll1",
"video_pll1_ref_sel", };
+static const char * const dram_pll_bypass_sels[] = {"dram_pll",
"dram_pll_ref_sel", };
+static const char * const gpu_pll_bypass_sels[] = {"gpu_pll",
"gpu_pll_ref_sel", };
+static const char * const vpu_pll_bypass_sels[] = {"vpu_pll",
"vpu_pll_ref_sel", };
+static const char * const arm_pll_bypass_sels[] = {
RE: [PATCH V3 1/4] dt-bindings: imx: Add clock binding doc for i.MX8MN
Hi, Stephen > -Original Message- > From: Stephen Boyd > Sent: Thursday, June 6, 2019 7:33 AM > To: Anson Huang ; Abel Vesa > ; Aisheng Dong ; > bjorn.anders...@linaro.org; catalin.mari...@arm.com; > devicet...@vger.kernel.org; dingu...@kernel.org; > enric.balle...@collabora.com; feste...@gmail.com; > horms+rene...@verge.net.au; ja...@amarulasolutions.com; > ker...@pengutronix.de; l.st...@pengutronix.de; Leonard Crestez > ; linux-arm-ker...@lists.infradead.org; linux- > c...@vger.kernel.org; linux-kernel@vger.kernel.org; mark.rutl...@arm.com; > maxime.rip...@bootlin.com; mturque...@baylibre.com; o...@lixom.net; > Jacky Bai ; robh...@kernel.org; > s.ha...@pengutronix.de; shawn...@kernel.org; will.dea...@arm.com > Cc: dl-linux-imx > Subject: Re: [PATCH V3 1/4] dt-bindings: imx: Add clock binding doc for > i.MX8MN > > Quoting anson.hu...@nxp.com (2019-06-03 18:59:25) > > From: Anson Huang > > > > Add the clock binding doc for i.MX8MN. > > > > Signed-off-by: Anson Huang > > --- > > No changes. > > --- > > .../devicetree/bindings/clock/imx8mn-clock.txt | 29 +++ > > Can this be yaml? OK, I will try to use yaml in V4. Thanks, Anson. > > > include/dt-bindings/clock/imx8mn-clock.h | 215 > + > > 2 files changed, 244 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/imx8mn- > clock.txt > > create mode 100644 include/dt-bindings/clock/imx8mn-clock.h > >
RE: [PATCH RESEND V4 3/3] watchdog: imx_sc: Add pretimeout support
Hi, Guenter
> -Original Message-
> From: Guenter Roeck On Behalf Of Guenter Roeck
> Sent: Sunday, May 12, 2019 9:28 PM
> To: Anson Huang ; robh...@kernel.org;
> mark.rutl...@arm.com; w...@linux-watchdog.org; shawn...@kernel.org;
> s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> Aisheng Dong ; ulf.hans...@linaro.org; Daniel
> Baluta ; Peng Fan ;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> watch...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
> Cc: dl-linux-imx
> Subject: Re: [PATCH RESEND V4 3/3] watchdog: imx_sc: Add pretimeout
> support
>
> On 5/12/19 3:10 AM, Anson Huang wrote:
> > i.MX system controller watchdog can support pretimeout IRQ via general
> > SCU MU IRQ, it depends on IMX_SCU and driver MUST be probed after SCU
> > IPC ready, then enable corresponding SCU IRQ group and register SCU
> > IRQ notifier, when watchdog pretimeout IRQ fires, SCU MU IRQ will be
> > handled and watchdog pretimeout notifier will be called to handle the
> > event.
> >
> > Signed-off-by: Anson Huang
>
> Revviewed-by: Guenter Roeck
>
> Other patches waiting for DT review. IMX API feedback below.
Shaw just picked up the DT patch. Would you please pick up this driver and
dt-binding patch
to you git repo?
Thanks,
Anson
>
> Side note: This patch depends on 'firmware: imx: enable imx scu general irq
> function' which is not yet in mainline.
>
> > ---
> > No change, just resend patch with correct encoding.
> > ---
> > drivers/watchdog/Kconfig | 1 +
> > drivers/watchdog/imx_sc_wdt.c | 116
> +++---
> > 2 files changed, 98 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index
> > 7ea6037..e08238c 100644
> > --- a/drivers/watchdog/Kconfig
> > +++ b/drivers/watchdog/Kconfig
> > @@ -716,6 +716,7 @@ config IMX2_WDT
> > config IMX_SC_WDT
> > tristate "IMX SC Watchdog"
> > depends on HAVE_ARM_SMCCC
> > + depends on IMX_SCU
> > select WATCHDOG_CORE
> > help
> > This is the driver for the system controller watchdog diff --git
> > a/drivers/watchdog/imx_sc_wdt.c b/drivers/watchdog/imx_sc_wdt.c index
> > 49848b6..6ecc03f 100644
> > --- a/drivers/watchdog/imx_sc_wdt.c
> > +++ b/drivers/watchdog/imx_sc_wdt.c
> > @@ -4,6 +4,7 @@
> >*/
> >
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -33,11 +34,19 @@
> >
> > #define SC_TIMER_WDOG_ACTION_PARTITION0
> >
> > +#define SC_IRQ_WDOG1
> > +#define SC_IRQ_GROUP_WDOG 1
> > +
> > static bool nowayout = WATCHDOG_NOWAYOUT;
> > module_param(nowayout, bool, );
> > MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once
> started (default="
> > __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
> >
> > +struct imx_sc_wdt_device {
> > + struct watchdog_device wdd;
> > + struct notifier_block wdt_notifier;
> > +};
> > +
> > static int imx_sc_wdt_ping(struct watchdog_device *wdog)
> > {
> > struct arm_smccc_res res;
> > @@ -85,24 +94,66 @@ static int imx_sc_wdt_set_timeout(struct
> watchdog_device *wdog,
> > return res.a0 ? -EACCES : 0;
> > }
> >
> > +static int imx_sc_wdt_set_pretimeout(struct watchdog_device *wdog,
> > +unsigned int pretimeout)
> > +{
> > + struct arm_smccc_res res;
> > +
> > + arm_smccc_smc(IMX_SIP_TIMER,
> IMX_SIP_TIMER_SET_PRETIME_WDOG,
> > + pretimeout * 1000, 0, 0, 0, 0, 0, );
> > + if (res.a0)
> > + return -EACCES;
> > +
> > + wdog->pretimeout = pretimeout;
> > +
> > + return 0;
> > +}
> > +
> > +static int imx_sc_wdt_notify(struct notifier_block *nb,
> > +unsigned long event, void *group) {
> > + struct imx_sc_wdt_device *imx_sc_wdd =
> > +container_of(nb,
> > + struct imx_sc_wdt_device,
> > + wdt_notifier);
> > +
> > + if (event & SC_IRQ_WDOG &&
> > + *(u8 *)group == SC_IRQ_GROUP_WDOG)
> > + watchdog_notify_pretimeout(_sc_wdd->wdd);
>
> This should really not be necessary. Event mask and target group (if needed
> with a wildcard for the group) should be parameters of
> imx_scu_irq_register_n
RE: [PATCH RESEND V4 2/3] arm64: dts: imx8qxp: Move watchdog node into scu node
Hi, Shawn
> -Original Message-
> From: Shawn Guo
> Sent: Wednesday, June 5, 2019 2:00 PM
> To: Anson Huang
> Cc: robh...@kernel.org; mark.rutl...@arm.com; w...@linux-watchdog.org;
> li...@roeck-us.net; s.ha...@pengutronix.de; ker...@pengutronix.de;
> feste...@gmail.com; Aisheng Dong ;
> ulf.hans...@linaro.org; Daniel Baluta ; Peng Fan
> ; devicet...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-watch...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; dl-linux-imx
> Subject: Re: [PATCH RESEND V4 2/3] arm64: dts: imx8qxp: Move watchdog
> node into scu node
>
> On Tue, Jun 04, 2019 at 09:06:28AM +, Anson Huang wrote:
> > Hi, Shawn
> > The driver and binding doc are already reviewed and waiting for DT
> patch, will you help review this DT patch?
>
> I'm fine with it. Should I just pick this patch up, or is there any
> dependency
> we need to handle?
No dependency, it just makes more sense to move the node into SCU node as it is
NOW depending on SCU
driver. Once you pick up this patch (and maybe the dt-binding patch as well?),
I will notify the watchdog
maintainer to pick up the watchdog patch in this series.
Thanks,
Anson
>
> Shawn
>
> >
> > Thanks,
> > Anson
> >
> > > -Original Message-
> > > From: Anson Huang
> > > Sent: Sunday, May 12, 2019 6:11 PM
> > > To: robh...@kernel.org; mark.rutl...@arm.com;
> > > w...@linux-watchdog.org; li...@roeck-us.net; shawn...@kernel.org;
> > > s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> > > Aisheng Dong ; ulf.hans...@linaro.org; Daniel
> > > Baluta ; Peng Fan ;
> > > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> > > watch...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
> > > Cc: dl-linux-imx
> > > Subject: [PATCH RESEND V4 2/3] arm64: dts: imx8qxp: Move watchdog
> > > node into scu node
> > >
> > > i.MX system controller watchdog has pretimeout function which
> > > depends on i.MX SCU driver, so it should be a subnode of SCU.
> > >
> > > Signed-off-by: Anson Huang
> > > ---
> > > No change, just resend patch with correct encoding.
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 10 +-
> > > 1 file changed, 5 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > index 0683ee2..b17c22e 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > @@ -149,6 +149,11 @@
> > > rtc: rtc {
> > > compatible = "fsl,imx8qxp-sc-rtc";
> > > };
> > > +
> > > + watchdog {
> > > + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
> > > + timeout-sec = <60>;
> > > + };
> > > };
> > >
> > > timer {
> > > @@ -517,9 +522,4 @@
> > > power-domains = < IMX_SC_R_GPIO_7>;
> > > };
> > > };
> > > -
> > > - watchdog {
> > > - compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
> > > - timeout-sec = <60>;
> > > - };
> > > };
> > > --
> > > 2.7.4
> >
RE: [PATCH RESEND V4 2/3] arm64: dts: imx8qxp: Move watchdog node into scu node
Hi, Shawn
The driver and binding doc are already reviewed and waiting for DT
patch, will you help review this DT patch?
Thanks,
Anson
> -Original Message-
> From: Anson Huang
> Sent: Sunday, May 12, 2019 6:11 PM
> To: robh...@kernel.org; mark.rutl...@arm.com; w...@linux-watchdog.org;
> li...@roeck-us.net; shawn...@kernel.org; s.ha...@pengutronix.de;
> ker...@pengutronix.de; feste...@gmail.com; Aisheng Dong
> ; ulf.hans...@linaro.org; Daniel Baluta
> ; Peng Fan ;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> watch...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
> Cc: dl-linux-imx
> Subject: [PATCH RESEND V4 2/3] arm64: dts: imx8qxp: Move watchdog node
> into scu node
>
> i.MX system controller watchdog has pretimeout function which depends on
> i.MX SCU driver, so it should be a subnode of SCU.
>
> Signed-off-by: Anson Huang
> ---
> No change, just resend patch with correct encoding.
> ---
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 0683ee2..b17c22e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -149,6 +149,11 @@
> rtc: rtc {
> compatible = "fsl,imx8qxp-sc-rtc";
> };
> +
> + watchdog {
> + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
> + timeout-sec = <60>;
> + };
> };
>
> timer {
> @@ -517,9 +522,4 @@
> power-domains = < IMX_SC_R_GPIO_7>;
> };
> };
> -
> - watchdog {
> - compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
> - timeout-sec = <60>;
> - };
> };
> --
> 2.7.4
RE: [RFC PATCH 0/3] Add support of busfreq
Hi, Alexandre > -Original Message- > From: Leonard Crestez > Sent: Wednesday, May 15, 2019 3:34 AM > To: Alexandre Bailon ; Jacky Bai > Cc: Michael Turquette ; Linux PM list p...@vger.kernel.org>; Georgi Djakov ; Patrick > Titiano ; Linux Kernel Mailing List ker...@vger.kernel.org>; Stephen Boyd ; Emilio > Lopez ; Hans de Goede ; > linux-clk ; linux-arm-kernel ker...@lists.infradead.org>; Zening Wang ; > Aisheng Dong ; Kevin Hilman > ; Carlo Caione ; dl-linux- > imx ; Anson Huang ; Viresh > Kumar > Subject: Re: [RFC PATCH 0/3] Add support of busfreq > > On 15.03.2019 18:55, Alexandre Bailon wrote: > >> On Wed, Mar 13, 2019 at 12:33 PM Alexandre Bailon > wrote: > > >>> As exemple, this series implements busfreq for i.MX8MM whose > >>> upstreaming is in progress. Because this relies on ATF to do the > >>> frequency scaling, it won't be hard make it work. I have similar question as previous reviewer, is there any branch that we can test this series? And, from the patch, it has multiple levels description of fabric arch, while we ONLY intend to scale "bus" frequency per devices' request, here "bus" includes DRAM, NOC and AHB, AXI, should we make it more flatter, such as just a virtual fabric as a single provider, and then all other devices as nodes under this provider? Anson > >> > >> It's not clear to me whether this series actual scales the dram > >> frequency based on what you said above. Is it just theoretical or do > >> you have it working with a pile of out-of-tree patches? Would be good > >> to include that pile of patches in your integration branch that I > >> suggested above. > > > The current series only introduce busfreq generic driver, and the > > busfreq driver for the imx8mm. > > As is, the imx8mm driver will just be loaded, but do nothing because > > none of the drivers have been updated to request bandwidth using the > > interconnect framework. > > > > My intent was to sent a first draft o busfreq, to get some feedback, > > before to send a more complete, and fully functional series. > > It's been a while since this was first posted and imx8mm now boots fine in > linux-next. Is there a more up-to-date WIP branch somewhere? > Otherwise I can try to hack this series into a bootable form. > > > In addition, the current clock driver of imx8mm doesn't allow dram > > frequency scaling, so if busfreq driver tries, it will fail (should be > > harmless > because any other clocks should restored to their previous > rate). > > I'm confused about this. In NXP tree the actual DRAM switch is done inside > ATF via SIP calls and involves corralling all CPUs. Do you want an "dram" clk > which wraps the SIP calls required to changing dram frequency and root > switching etc? > > I've been looking at the busfreq implementation in the NXP tree and > refactoring just the "dram freq switch" behind a clk might work nicely. > > This would be similar to the imx_cpu clk used for cpufreq-dt and it might > even be possible to upstream this separately from the rest of busfreq logic > dealing with device requests. > > > I haven't done a very careful review but I noticed you're not using the OPP > framework and instead redefined everything? It's not clear why. > > -- > Regards, > Leonard
[PATCH V3 3/4] clk: imx: Add support for i.MX8MN clock driver
From: Anson Huang
This patch adds i.MX8MN clock driver support.
Signed-off-by: Anson Huang
---
Changes since V2:
- use platform driver model for this clock driver;
- add "const" to clock mux arrays.
---
drivers/clk/imx/Kconfig | 6 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx8mn.c | 630 +++
3 files changed, 637 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mn.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 0eaf418..1ac0c79 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -14,6 +14,12 @@ config CLK_IMX8MM
help
Build the driver for i.MX8MM CCM Clock Driver
+config CLK_IMX8MN
+ bool "IMX8MN CCM Clock Driver"
+ depends on ARCH_MXC && ARM64
+ help
+ Build the driver for i.MX8MN CCM Clock Driver
+
config CLK_IMX8MQ
bool "IMX8MQ CCM Clock Driver"
depends on ARCH_MXC && ARM64
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 05641c6..77a3d71 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_MXC_CLK_SCU) += \
clk-lpcg-scu.o
obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
+obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
new file mode 100644
index 000..3f09974
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -0,0 +1,630 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018-2019 NXP.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static u32 share_count_sai2;
+static u32 share_count_sai3;
+static u32 share_count_sai5;
+static u32 share_count_sai6;
+static u32 share_count_sai7;
+static u32 share_count_disp;
+static u32 share_count_pdm;
+static u32 share_count_nand;
+
+enum {
+ ARM_PLL,
+ GPU_PLL,
+ VPU_PLL,
+ SYS_PLL1,
+ SYS_PLL2,
+ SYS_PLL3,
+ DRAM_PLL,
+ AUDIO_PLL1,
+ AUDIO_PLL2,
+ VIDEO_PLL2,
+ NR_PLLS,
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
+ PLL_1443X_RATE(786432000U, 655, 5, 2, 23593),
+ PLL_1443X_RATE(722534400U, 301, 5, 1, 3670),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(59400U, 198, 2, 2, 0),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+};
+
+static struct imx_pll14xx_clk imx8mn_audio_pll = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_audiopll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_video_pll = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_videopll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_dram_pll = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_drampll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_arm_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_gpu_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_vpu_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_sys_pll = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy",
"dummy", };
+static const char * const audio_pll1_bypass_sels[] = {"audio_pll1",
"audio_pll1_ref_sel", };
+static const char * const audio_pll2_bypass_sels[] = {"audio_pll2",
"audio_pll2_ref_sel", };
+static const char * const video_pll1_bypass_sels[] = {"video_pll1",
"video_pll1_ref_sel", };
+static const char * const dram_pll_bypass_sels[] = {"dram_pll",
"dram_pll_ref_sel", };
+static const char * const gpu_pll_bypass_sels[] = {"gpu_pll",
"gpu_pll_ref_sel", };
+static const char * const vpu_pll_byp
[PATCH V3 1/4] dt-bindings: imx: Add clock binding doc for i.MX8MN
From: Anson Huang
Add the clock binding doc for i.MX8MN.
Signed-off-by: Anson Huang
---
No changes.
---
.../devicetree/bindings/clock/imx8mn-clock.txt | 29 +++
include/dt-bindings/clock/imx8mn-clock.h | 215 +
2 files changed, 244 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx8mn-clock.txt
create mode 100644 include/dt-bindings/clock/imx8mn-clock.h
diff --git a/Documentation/devicetree/bindings/clock/imx8mn-clock.txt
b/Documentation/devicetree/bindings/clock/imx8mn-clock.txt
new file mode 100644
index 000..d83db5c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8mn-clock.txt
@@ -0,0 +1,29 @@
+* Clock bindings for NXP i.MX8M Nano
+
+Required properties:
+- compatible: Should be "fsl,imx8mn-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+- clocks: list of clock specifiers, must contain an entry for each required
+ entry in clock-names
+- clock-names: should include the following entries:
+- "osc_32k"
+- "osc_24m"
+- "clk_ext1"
+- "clk_ext2"
+- "clk_ext3"
+- "clk_ext4"
+
+clk: clock-controller@3038 {
+ compatible = "fsl,imx8mn-ccm";
+ reg = <0x0 0x3038 0x0 0x1>;
+ #clock-cells = <1>;
+ clocks = <_32k>, <_24m>, <_ext1>, <_ext2>,
+<_ext3>, <_ext4>;
+ clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4";
+};
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
+for the full list of i.MX8M Nano clock IDs.
diff --git a/include/dt-bindings/clock/imx8mn-clock.h
b/include/dt-bindings/clock/imx8mn-clock.h
new file mode 100644
index 000..5255b1c
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
+#define __DT_BINDINGS_CLOCK_IMX8MN_H
+
+#define IMX8MN_CLK_DUMMY 0
+#define IMX8MN_CLK_32K 1
+#define IMX8MN_CLK_24M 2
+#define IMX8MN_OSC_HDMI_CLK3
+#define IMX8MN_CLK_EXT14
+#define IMX8MN_CLK_EXT25
+#define IMX8MN_CLK_EXT36
+#define IMX8MN_CLK_EXT47
+#define IMX8MN_AUDIO_PLL1_REF_SEL 8
+#define IMX8MN_AUDIO_PLL2_REF_SEL 9
+#define IMX8MN_VIDEO_PLL1_REF_SEL 10
+#define IMX8MN_DRAM_PLL_REF_SEL11
+#define IMX8MN_GPU_PLL_REF_SEL 12
+#define IMX8MN_VPU_PLL_REF_SEL 13
+#define IMX8MN_ARM_PLL_REF_SEL 14
+#define IMX8MN_SYS_PLL1_REF_SEL15
+#define IMX8MN_SYS_PLL2_REF_SEL16
+#define IMX8MN_SYS_PLL3_REF_SEL17
+#define IMX8MN_AUDIO_PLL1 18
+#define IMX8MN_AUDIO_PLL2 19
+#define IMX8MN_VIDEO_PLL1 20
+#define IMX8MN_DRAM_PLL21
+#define IMX8MN_GPU_PLL 22
+#define IMX8MN_VPU_PLL 23
+#define IMX8MN_ARM_PLL 24
+#define IMX8MN_SYS_PLL125
+#define IMX8MN_SYS_PLL226
+#define IMX8MN_SYS_PLL327
+#define IMX8MN_AUDIO_PLL1_BYPASS 28
+#define IMX8MN_AUDIO_PLL2_BYPASS 29
+#define IMX8MN_VIDEO_PLL1_BYPASS 30
+#define IMX8MN_DRAM_PLL_BYPASS 31
+#define IMX8MN_GPU_PLL_BYPASS 32
+#define IMX8MN_VPU_PLL_BYPASS 33
+#define IMX8MN_ARM_PLL_BYPASS 34
+#define IMX8MN_SYS_PLL1_BYPASS 35
+#define IMX8MN_SYS_PLL2_BYPASS 36
+#define IMX8MN_SYS_PLL3_BYPASS 37
+#define IMX8MN_AUDIO_PLL1_OUT 38
+#define IMX8MN_AUDIO_PLL2_OUT 39
+#define IMX8MN_VIDEO_PLL1_OUT 40
+#define IMX8MN_DRAM_PLL_OUT41
+#define IMX8MN_GPU_PLL_OUT 42
+#define IMX8MN_VPU_PLL_OUT 43
+#define IMX8MN_ARM_PLL_OUT 44
+#define IMX8MN_SYS_PLL1_OUT45
+#define IMX8MN_SYS_PLL2_OUT46
+#define IMX8MN_SYS_PLL3_OUT47
+#define IMX8MN_SYS_PLL1_40M48
+#define IMX8MN_SYS_PLL1_80M49
+#define IMX8MN_SYS_PLL1_100M 50
+#define IMX8MN_SYS_PLL1_133M
[PATCH V3 2/4] clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage
From: Anson Huang
1416X/1443X PLL are used on i.MX8MM and i.MX8MN and maybe
other i.MX8M series SoC later, the macro definitions of
these PLLs' initialization should be common for usage.
Signed-off-by: Anson Huang
---
New patch.
---
drivers/clk/imx/clk-imx8mm.c | 17 -
drivers/clk/imx/clk.h| 17 +
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index eb9fcf0..fecb3b2 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -26,23 +26,6 @@ static u32 share_count_dcss;
static u32 share_count_pdm;
static u32 share_count_nand;
-#define PLL_1416X_RATE(_rate, _m, _p, _s) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- }
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
- { \
- .rate = (_rate),\
- .mdiv = (_m), \
- .pdiv = (_p), \
- .sdiv = (_s), \
- .kdiv = (_k), \
- }
-
static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
PLL_1416X_RATE(18U, 225, 3, 0),
PLL_1416X_RATE(16U, 200, 3, 0),
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 6dcdc91..ac8c4ae 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -81,6 +81,23 @@ enum imx_pllv3_type {
IMX_PLLV3_AV_IMX7,
};
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
const char *parent_name, void __iomem *base, u32 div_mask);
--
2.7.4
[PATCH V3 4/4] arm64: defconfig: Select CONFIG_CLK_IMX8MN by default
From: Anson Huang Enable CONFIG_CLK_IMX8MN to support i.MX8MN clock driver. Signed-off-by: Anson Huang --- Changes since V2: - follow alphabet sequence. --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8d4f25c..ae17f45 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -655,6 +655,7 @@ CONFIG_COMMON_CLK_S2MPS11=y CONFIG_CLK_QORIQ=y CONFIG_COMMON_CLK_PWM=y CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y CONFIG_CLK_IMX8MQ=y CONFIG_CLK_IMX8QXP=y CONFIG_TI_SCI_CLK=y -- 2.7.4
RE: [PATCH V2 2/3] clk: imx: Add support for i.MX8MN clock driver
> -Original Message-
> From: Leonard Crestez
> Sent: Monday, June 3, 2019 4:45 PM
> To: Anson Huang ; mturque...@baylibre.com;
> sb...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; s.ha...@pengutronix.de; ker...@pengutronix.de;
> feste...@gmail.com; catalin.mari...@arm.com; will.dea...@arm.com;
> maxime.rip...@bootlin.com; o...@lixom.net; horms+rene...@verge.net.au;
> ja...@amarulasolutions.com; bjorn.anders...@linaro.org;
> dingu...@kernel.org; enric.balle...@collabora.com; Aisheng Dong
> ; Jacky Bai ; Abel Vesa
> ; l.st...@pengutronix.de; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org
> Cc: dl-linux-imx
> Subject: Re: [PATCH V2 2/3] clk: imx: Add support for i.MX8MN clock driver
>
> On 6/3/2019 4:33 AM, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > This patch adds i.MX8MN clock driver support.
>
> > +#include "clk.h"
> > +
> > +#define PLL_1416X_RATE(_rate, _m, _p, _s) \
> > + { \
> > + .rate = (_rate),\
> > + .mdiv = (_m), \
> > + .pdiv = (_p), \
> > + .sdiv = (_s), \
> > + }
> > +
> > +#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
> > + { \
> > + .rate = (_rate),\
> > + .mdiv = (_m), \
> > + .pdiv = (_p), \
> > + .sdiv = (_s), \
> > + .kdiv = (_k), \
> > + }
>
> These macros are shared with clk-imx8mm (and perhaps some future chips)
> so they should be moved to driver/clk/imx/clk.h
OK, will move them into clk.h in V3.
Anson.
RE: [PATCH V2 2/3] clk: imx: Add support for i.MX8MN clock driver
Hi, Abel
> -Original Message-
> From: Abel Vesa
> Sent: Monday, June 3, 2019 3:30 PM
> To: Anson Huang
> Cc: mturque...@baylibre.com; sb...@kernel.org; robh...@kernel.org;
> mark.rutl...@arm.com; shawn...@kernel.org; s.ha...@pengutronix.de;
> ker...@pengutronix.de; feste...@gmail.com; catalin.mari...@arm.com;
> will.dea...@arm.com; maxime.rip...@bootlin.com; o...@lixom.net;
> horms+rene...@verge.net.au; ja...@amarulasolutions.com;
> bjorn.anders...@linaro.org; Leonard Crestez ;
> dingu...@kernel.org; enric.balle...@collabora.com; Aisheng Dong
> ; Jacky Bai ;
> l.st...@pengutronix.de; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; dl-linux-imx
> Subject: Re: [PATCH V2 2/3] clk: imx: Add support for i.MX8MN clock driver
>
> On 19-06-03 09:35:02, anson.hu...@nxp.com wrote:
> > From: Anson Huang
> >
> > This patch adds i.MX8MN clock driver support.
> >
> > Signed-off-by: Anson Huang
> > ---
> > Changes since V1:
> > - add GPIOx clocks.
>
> ...
>
> > +static struct imx_pll14xx_clk imx8mn_sys_pll __initdata = {
> > + .type = PLL_1416X,
> > + .rate_table = imx8mn_pll1416x_tbl,
> > +};
> > +
> > +static const char *pll_ref_sels[] = { "osc_24m", "dummy", "dummy",
> > +"dummy", };
>
> All of these should be "static const char * const ".
OK.
>
> > +static const char *audio_pll1_bypass_sels[] = {"audio_pll1",
> > +"audio_pll1_ref_sel", }; static const char *audio_pll2_bypass_sels[]
> > += {"audio_pll2", "audio_pll2_ref_sel", };
>
> ...
>
> > + clk_data.clks = clks;
> > + clk_data.clk_num = ARRAY_SIZE(clks);
> > + ret = of_clk_add_provider(np, of_clk_src_onecell_get, _data);
> > + if (ret < 0) {
> > + pr_err("failed to register clks for i.MX8MN\n");
> > + return -EINVAL;
> > + }
> > +
> > + imx_register_uart_clocks(uart_clks);
> > +
> > + return 0;
> > +}
> > +CLK_OF_DECLARE_DRIVER(imx8mn, "fsl,imx8mn-ccm",
> imx8mn_clocks_init);
>
> Any reason why this cannot be a platform driver ?
It should can be, I just did NOT take care of it, 8MQ uses platform driver
model, while
8MM does NOT, I will modify both of them to use platform driver model.
Thanks,
Anson.
>
> > --
> > 2.7.4
> >
RE: [PATCH] arm64: dts: imx8mm: Fix build warnings
Hi, Fabio > -Original Message- > From: Fabio Estevam > Sent: Monday, June 3, 2019 10:49 AM > To: Anson Huang > Cc: Rob Herring ; Mark Rutland > ; Shawn Guo ; Sascha > Hauer ; Sascha Hauer ; > Leonard Crestez ; Aisheng Dong > ; viresh kumar ; Jacky > Bai ; open list:OPEN FIRMWARE AND FLATTENED > DEVICE TREE BINDINGS ; moderated > list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE ker...@lists.infradead.org>; linux-kernel ; dl- > linux-imx > Subject: Re: [PATCH] arm64: dts: imx8mm: Fix build warnings > > Hi Anson, > > On Sun, Jun 2, 2019 at 9:46 PM wrote: > > > > From: Anson Huang > > > > This patch fixes below build warning with "W=1": > > I have already sent patches to fix these warnings. OK, thanks, then please ignore this patch. Anson.
[PATCH] arm64: dts: imx8mm: Move gic node into soc node
From: Anson Huang
GIC is inside of SoC from architecture perspective, it should
be located inside of soc node in DT.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index dc99f45..429312e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -169,15 +169,6 @@
clock-output-names = "clk_ext4";
};
- gic: interrupt-controller@3880 {
- compatible = "arm,gic-v3";
- reg = <0x0 0x3880 0 0x1>, /* GIC Dist */
- <0x0 0x3888 0 0xC>; /* GICR (RD_base + SGI_base)
*/
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupts = ;
- };
-
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -739,6 +730,15 @@
dma-names = "rx-tx";
status = "disabled";
};
+
+ gic: interrupt-controller@3880 {
+ compatible = "arm,gic-v3";
+ reg = <0x3880 0x1>, /* GIC Dist */
+ <0x3888 0xc>; /* GICR (RD_base +
SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = ;
+ };
};
usbphynop1: usbphynop1 {
--
2.7.4
[PATCH V2 3/3] arm64: defconfig: Select CONFIG_CLK_IMX8MN by default
From: Anson Huang Enable CONFIG_CLK_IMX8MN to support i.MX8MN clock driver. Signed-off-by: Anson Huang --- No changes. --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8d4f25c..aef797c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -654,6 +654,7 @@ CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_S2MPS11=y CONFIG_CLK_QORIQ=y CONFIG_COMMON_CLK_PWM=y +CONFIG_CLK_IMX8MN=y CONFIG_CLK_IMX8MM=y CONFIG_CLK_IMX8MQ=y CONFIG_CLK_IMX8QXP=y -- 2.7.4
[PATCH V2 1/3] dt-bindings: imx: Add clock binding doc for i.MX8MN
From: Anson Huang
Add the clock binding doc for i.MX8MN.
Signed-off-by: Anson Huang
---
No changes.
---
.../devicetree/bindings/clock/imx8mn-clock.txt | 29 +++
include/dt-bindings/clock/imx8mn-clock.h | 215 +
2 files changed, 244 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx8mn-clock.txt
create mode 100644 include/dt-bindings/clock/imx8mn-clock.h
diff --git a/Documentation/devicetree/bindings/clock/imx8mn-clock.txt
b/Documentation/devicetree/bindings/clock/imx8mn-clock.txt
new file mode 100644
index 000..d83db5c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8mn-clock.txt
@@ -0,0 +1,29 @@
+* Clock bindings for NXP i.MX8M Nano
+
+Required properties:
+- compatible: Should be "fsl,imx8mn-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+- clocks: list of clock specifiers, must contain an entry for each required
+ entry in clock-names
+- clock-names: should include the following entries:
+- "osc_32k"
+- "osc_24m"
+- "clk_ext1"
+- "clk_ext2"
+- "clk_ext3"
+- "clk_ext4"
+
+clk: clock-controller@3038 {
+ compatible = "fsl,imx8mn-ccm";
+ reg = <0x0 0x3038 0x0 0x1>;
+ #clock-cells = <1>;
+ clocks = <_32k>, <_24m>, <_ext1>, <_ext2>,
+<_ext3>, <_ext4>;
+ clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4";
+};
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
+for the full list of i.MX8M Nano clock IDs.
diff --git a/include/dt-bindings/clock/imx8mn-clock.h
b/include/dt-bindings/clock/imx8mn-clock.h
new file mode 100644
index 000..5255b1c
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
+#define __DT_BINDINGS_CLOCK_IMX8MN_H
+
+#define IMX8MN_CLK_DUMMY 0
+#define IMX8MN_CLK_32K 1
+#define IMX8MN_CLK_24M 2
+#define IMX8MN_OSC_HDMI_CLK3
+#define IMX8MN_CLK_EXT14
+#define IMX8MN_CLK_EXT25
+#define IMX8MN_CLK_EXT36
+#define IMX8MN_CLK_EXT47
+#define IMX8MN_AUDIO_PLL1_REF_SEL 8
+#define IMX8MN_AUDIO_PLL2_REF_SEL 9
+#define IMX8MN_VIDEO_PLL1_REF_SEL 10
+#define IMX8MN_DRAM_PLL_REF_SEL11
+#define IMX8MN_GPU_PLL_REF_SEL 12
+#define IMX8MN_VPU_PLL_REF_SEL 13
+#define IMX8MN_ARM_PLL_REF_SEL 14
+#define IMX8MN_SYS_PLL1_REF_SEL15
+#define IMX8MN_SYS_PLL2_REF_SEL16
+#define IMX8MN_SYS_PLL3_REF_SEL17
+#define IMX8MN_AUDIO_PLL1 18
+#define IMX8MN_AUDIO_PLL2 19
+#define IMX8MN_VIDEO_PLL1 20
+#define IMX8MN_DRAM_PLL21
+#define IMX8MN_GPU_PLL 22
+#define IMX8MN_VPU_PLL 23
+#define IMX8MN_ARM_PLL 24
+#define IMX8MN_SYS_PLL125
+#define IMX8MN_SYS_PLL226
+#define IMX8MN_SYS_PLL327
+#define IMX8MN_AUDIO_PLL1_BYPASS 28
+#define IMX8MN_AUDIO_PLL2_BYPASS 29
+#define IMX8MN_VIDEO_PLL1_BYPASS 30
+#define IMX8MN_DRAM_PLL_BYPASS 31
+#define IMX8MN_GPU_PLL_BYPASS 32
+#define IMX8MN_VPU_PLL_BYPASS 33
+#define IMX8MN_ARM_PLL_BYPASS 34
+#define IMX8MN_SYS_PLL1_BYPASS 35
+#define IMX8MN_SYS_PLL2_BYPASS 36
+#define IMX8MN_SYS_PLL3_BYPASS 37
+#define IMX8MN_AUDIO_PLL1_OUT 38
+#define IMX8MN_AUDIO_PLL2_OUT 39
+#define IMX8MN_VIDEO_PLL1_OUT 40
+#define IMX8MN_DRAM_PLL_OUT41
+#define IMX8MN_GPU_PLL_OUT 42
+#define IMX8MN_VPU_PLL_OUT 43
+#define IMX8MN_ARM_PLL_OUT 44
+#define IMX8MN_SYS_PLL1_OUT45
+#define IMX8MN_SYS_PLL2_OUT46
+#define IMX8MN_SYS_PLL3_OUT47
+#define IMX8MN_SYS_PLL1_40M48
+#define IMX8MN_SYS_PLL1_80M49
+#define IMX8MN_SYS_PLL1_100M 50
+#define IMX8MN_SYS_PLL1_133M
[PATCH V2 2/3] clk: imx: Add support for i.MX8MN clock driver
From: Anson Huang
This patch adds i.MX8MN clock driver support.
Signed-off-by: Anson Huang
---
Changes since V1:
- add GPIOx clocks.
---
drivers/clk/imx/Kconfig | 6 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx8mn.c | 614 +++
3 files changed, 621 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mn.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 0eaf418..1ac0c79 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -14,6 +14,12 @@ config CLK_IMX8MM
help
Build the driver for i.MX8MM CCM Clock Driver
+config CLK_IMX8MN
+ bool "IMX8MN CCM Clock Driver"
+ depends on ARCH_MXC && ARM64
+ help
+ Build the driver for i.MX8MN CCM Clock Driver
+
config CLK_IMX8MQ
bool "IMX8MQ CCM Clock Driver"
depends on ARCH_MXC && ARM64
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 05641c6..70a55cd 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_MXC_CLK_SCU) += \
clk-scu.o \
clk-lpcg-scu.o
+obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
new file mode 100644
index 000..7a92c75a
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -0,0 +1,614 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018-2019 NXP.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static u32 share_count_sai2;
+static u32 share_count_sai3;
+static u32 share_count_sai5;
+static u32 share_count_sai6;
+static u32 share_count_sai7;
+static u32 share_count_disp;
+static u32 share_count_pdm;
+static u32 share_count_nand;
+
+enum {
+ ARM_PLL,
+ GPU_PLL,
+ VPU_PLL,
+ SYS_PLL1,
+ SYS_PLL2,
+ SYS_PLL3,
+ DRAM_PLL,
+ AUDIO_PLL1,
+ AUDIO_PLL2,
+ VIDEO_PLL2,
+ NR_PLLS,
+};
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
+ PLL_1443X_RATE(786432000U, 655, 5, 2, 23593),
+ PLL_1443X_RATE(722534400U, 301, 5, 1, 3670),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(59400U, 198, 2, 2, 0),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+};
+
+static struct imx_pll14xx_clk imx8mn_audio_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_audiopll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_video_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_videopll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_dram_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_drampll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_arm_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_gpu_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_vpu_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_sys_pll __initdata = {
+ .type = PLL_1416X,
+
[PATCH V2 2/3] arm64: dts: freescale: Add i.MX8MN dtsi support
From: Anson Huang
The i.MX8M Nano Media Applications Processor is a new SoC of the i.MX8M
family, it is a 14nm FinFET product of the growing mScale family targeting
the consumer market. It is built in Samsung 14LPP to achieve both high
performance and low power consumption and relies on a powerful fully
coherent core complex based on a quad core ARM Cortex-A53 cluster,
Cortex-M7 low-power coprocessor and graphics accelerator.
This patch adds the basic dtsi support for i.MX8MN.
Signed-off-by: Anson Huang
---
Changes since V1:
- fix build warnings of soc/aips bus unit name and reg properties;
- move gic into soc node;
- move usbphynop1/usbphynop2 node outside the soc node.
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 710 ++
1 file changed, 710 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
new file mode 100644
index 000..1fb9148
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -0,0 +1,710 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+#include "imx8mn-pinfunc.h"
+
+/ {
+ compatible = "fsl,imx8mn";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 =
+ gpio0 =
+ gpio1 =
+ gpio2 =
+ gpio3 =
+ gpio4 =
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ spi0 =
+ spi1 =
+ spi2 =
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x0 0x4000 0 0x8000>;
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "osc_24m";
+ };
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13300>;
+ clock-output-names = "clk_ext1";
+ };
+
+ clk_ext2: clock-ext2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>
[PATCH V2 3/3] arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support
From: Anson Huang
This patch adds basic i.MM8MN DDR4 EVK board support.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/Makefile| 1 +
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 217 ++
2 files changed, 218 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile
b/arch/arm64/boot/dts/freescale/Makefile
index 0bd122f..2cdd4cc 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -20,6 +20,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
new file mode 100644
index 000..da552c2
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+
+/ {
+ model = "NXP i.MX8MNano DDR4 EVK board";
+ compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
+
+ chosen {
+ stdout-path =
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO220x19
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MN_IOMUXC_G
[PATCH V2 1/3] dt-bindings: arm: imx: Add the soc binding for i.MX8MN
From: Anson Huang This patch adds the soc & board binding for i.MX8MN. Signed-off-by: Anson Huang --- No changes. --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 407138e..b1a5231 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -171,6 +171,12 @@ properties: - const: compulab,cl-som-imx7 - const: fsl,imx7d + - description: i.MX8MN based Boards +items: + - enum: + - fsl,imx8mn-ddr4-evk# i.MX8MN DDR4 EVK Board + - const: fsl,imx8mn + - description: i.MX8MM based Boards items: - enum: -- 2.7.4
RE: [PATCH 2/3] arm64: dts: freescale: Add i.MX8MN dtsi support
Hi, Andrey
> -Original Message-
> From: Andrey Smirnov
> Sent: Saturday, June 1, 2019 3:04 AM
> To: Anson Huang
> Cc: Rob Herring ; Mark Rutland
> ; Shawn Guo ; Sascha
> Hauer ; Sascha Hauer ;
> Fabio Estevam ; manivannan.sadhasi...@linaro.org;
> bruno.thom...@gmail.com; Aisheng Dong ; Jacky
> Bai ; Leo Li ; Lucas Stach
> ; Pankaj Bansal ;
> Bhaskar Upadhaya ; Pramod Kumar
> ; Vabhav Sharma ;
> Leonard Crestez ; open list:OPEN FIRMWARE
> AND FLATTENED DEVICE TREE BINDINGS ;
> linux-kernel ; linux-arm-kernel ker...@lists.infradead.org>; dl-linux-imx
> Subject: Re: [PATCH 2/3] arm64: dts: freescale: Add i.MX8MN dtsi support
>
> On Thu, May 30, 2019 at 2:45 AM wrote:
> >
> > From: Anson Huang
> >
> > The i.MX8M Nano Media Applications Processor is a new SoC of the
> > i.MX8M family, it is a 14nm FinFET product of the growing mScale
> > family targeting the consumer market. It is built in Samsung 14LPP to
> > achieve both high performance and low power consumption and relies on
> > a powerful fully coherent core complex based on a quad core ARM
> > Cortex-A53 cluster,
> > Cortex-M7 low-power coprocessor and graphics accelerator.
> >
> > This patch adds the basic dtsi support for i.MX8MN.
> >
> > Signed-off-by: Anson Huang
> > ---
> > This patch should be based on below patches for clock and pinctrl head
> files:
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
> >
> hwork.kernel.org%2Fpatch%2F10968059%2Fdata=02%7C01%7CAnson
> .Huang%
> >
> 40nxp.com%7C8d77b87aa30b4c7067ca08d6e5fac8c3%7C686ea1d3bc2b4c6fa
> 92cd99
> >
> c5c301635%7C0%7C0%7C636949262607301101sdata=tA55rOer30Vbq
> FZ%2Badm
> > XC3K42Y%2BG7niE6BbAB4WD2%2Fk%3Dreserved=0
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
> >
> hwork.kernel.org%2Fpatch%2F10968267%2Fdata=02%7C01%7CAnson
> .Huang%
> >
> 40nxp.com%7C8d77b87aa30b4c7067ca08d6e5fac8c3%7C686ea1d3bc2b4c6fa
> 92cd99
> >
> c5c301635%7C0%7C0%7C636949262607301101sdata=wMIK9tYicC3Km
> xJ4zLDuw
> > 9Wg65vOUdCkZwX8hg3EUz4%3Dreserved=0
> > ---
> > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 701
> > ++
> > 1 file changed, 701 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/freescale/imx8mn.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > new file mode 100644
> > index 000..c318ee6
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > @@ -0,0 +1,701 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright 2019 NXP
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include "imx8mn-pinfunc.h"
> > +
> > +/ {
> > + compatible = "fsl,imx8mn";
> > + interrupt-parent = <>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + aliases {
> > + ethernet0 =
> > + gpio0 =
> > + gpio1 =
> > + gpio2 =
> > + gpio3 =
> > + gpio4 =
> > + i2c0 =
> > + i2c1 =
> > + i2c2 =
> > + i2c3 =
> > + mmc0 =
> > + mmc1 =
> > + mmc2 =
> > + serial0 =
> > + serial1 =
> > + serial2 =
> > + serial3 =
> > + spi0 =
> > + spi1 =
> > + spi2 =
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + A53_0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x0>;
> > + clock-latency = <61036>;
> > + clocks = < IMX8MN_CLK_ARM>;
> > + enable-method = "psci";
> > + next-level-cache = <_L2>;
> > + };
> > +
> > + A53_1: cpu@1 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > +
[PATCH] arm64: dts: imx8mm: Fix build warnings
From: Anson Huang
This patch fixes below build warning with "W=1":
arch/arm64/boot/dts/freescale/imx8mm.dtsi:203.6-754.4:
Warning (unit_address_vs_reg): /soc: node has a reg or
ranges property, but no unit name
arch/arm64/boot/dts/freescale/imx8mm.dtsi:209.23-388.5:
Warning (unit_address_vs_reg): /soc/bus@3000: node
has a unit name, but no reg property
arch/arm64/boot/dts/freescale/imx8mm.dtsi:390.23-439.5:
Warning (unit_address_vs_reg): /soc/bus@3040: node
has a unit name, but no reg property
arch/arm64/boot/dts/freescale/imx8mm.dtsi:441.23-658.5:
Warning (unit_address_vs_reg): /soc/bus@3080: node
has a unit name, but no reg property
arch/arm64/boot/dts/freescale/imx8mm.dtsi:660.23-724.5:
Warning (unit_address_vs_reg): /soc/bus@32c0: node
has a unit name, but no reg property
arch/arm64/boot/dts/freescale/imx8mm.dtsi:681.27-687.6:
Warning (simple_bus_reg): /soc/bus@32c0/usbphynop1:
missing or empty reg/ranges property
arch/arm64/boot/dts/freescale/imx8mm.dtsi:710.27-716.6:
Warning (simple_bus_reg): /soc/bus@32c0/usbphynop2:
missing or empty reg/ranges property
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 38 +--
1 file changed, 21 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 708d3c4..dc99f45 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -200,7 +200,7 @@
arm,no-tick-in-suspend;
};
- soc {
+ soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -208,6 +208,7 @@
aips1: bus@3000 {
compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x3000 0x40>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -389,6 +390,7 @@
aips2: bus@3040 {
compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x3040 0x40>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -440,6 +442,7 @@
aips3: bus@3080 {
compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x3080 0x40>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -659,6 +662,7 @@
aips4: bus@32c0 {
compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x32c0 0x40>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -678,14 +682,6 @@
status = "disabled";
};
- usbphynop1: usbphynop1 {
- compatible = "usb-nop-xceiv";
- clocks = < IMX8MM_CLK_USB_PHY_REF>;
- assigned-clocks = < IMX8MM_CLK_USB_PHY_REF>;
- assigned-clock-parents = <
IMX8MM_SYS_PLL1_100M>;
- clock-names = "main_clk";
- };
-
usbmisc1: usbmisc@32e40200 {
compatible = "fsl,imx8mm-usbmisc",
"fsl,imx7d-usbmisc";
#index-cells = <1>;
@@ -707,14 +703,6 @@
status = "disabled";
};
- usbphynop2: usbphynop2 {
- compatible = "usb-nop-xceiv";
- clocks = < IMX8MM_CLK_USB_PHY_REF>;
- assigned-clocks = < IMX8MM_CLK_USB_PHY_REF>;
- assigned-clock-parents = <
IMX8MM_SYS_PLL1_100M>;
- clock-names = "main_clk";
- };
-
usbmisc2: usbmisc@32e50200 {
compatible = "fsl,imx8mm-usbmisc",
"fsl,imx7d-usbmisc";
#index-cells = <1>;
@@ -752,4 +740,20 @@
status = "disabled";
};
};
+
+ usbphynop1: usbphynop1 {
+ compatible = "usb-nop-xceiv";
+ clocks = < IMX8MM_CLK_USB_PHY_REF>;
+
RE: [PATCH 2/3] arm64: dts: freescale: Add i.MX8MN dtsi support
Hi, Fabio
> -Original Message-
> From: Fabio Estevam
> Sent: Friday, May 31, 2019 7:40 PM
> To: Anson Huang
> Cc: Rob Herring ; Mark Rutland
> ; Shawn Guo ; Sascha
> Hauer ; Sascha Hauer ;
> Andrey Smirnov ; Manivannan Sadhasivam
> ; Bruno Thomsen
> ; Aisheng Dong ;
> Jacky Bai ; Leo Li ; Lucas Stach
> ; Pankaj Bansal ;
> Bhaskar Upadhaya ; Pramod Kumar
> ; Vabhav Sharma ;
> Leonard Crestez ; open list:OPEN FIRMWARE
> AND FLATTENED DEVICE TREE BINDINGS ;
> linux-kernel ; moderated list:ARM/FREESCALE
> IMX / MXC ARM ARCHITECTURE ; dl-
> linux-imx
> Subject: Re: [PATCH 2/3] arm64: dts: freescale: Add i.MX8MN dtsi support
>
> On Thu, May 30, 2019 at 6:45 AM wrote:
>
> > + gpio1: gpio@3020 {
> > + compatible = "fsl,imx8mn-gpio",
> > "fsl,imx35-gpio";
> > + reg = <0x3020 0x1>;
> > + interrupts = > IRQ_TYPE_LEVEL_HIGH>,
> > + > + IRQ_TYPE_LEVEL_HIGH>;
>
> No GPIO clocks entries?
Just noticed this, the internal bring-up branch's clock driver does NOT have it,
I will add them in V2, thanks for pointing out this.
>
> > + usbphynop1: usbphynop1 {
> > + compatible = "usb-nop-xceiv";
> > + clocks = < IMX8MN_CLK_USB_PHY_REF>;
> > + assigned-clocks = <
> > IMX8MN_CLK_USB_PHY_REF>;
> > + assigned-clock-parents = <
> IMX8MN_SYS_PLL1_100M>;
> > + clock-names = "main_clk";
> > + };
>
> usbphynop1 does not have any registers associated, so it should be placed
> outside the soc.
>
> Building with W=1 should warn you about that.
>
OK, I will move them to outside of soc.
> > + usbphynop2: usbphynop2 {
> > + compatible = "usb-nop-xceiv";
> > + clocks = < IMX8MN_CLK_USB_PHY_REF>;
> > + assigned-clocks = <
> > IMX8MN_CLK_USB_PHY_REF>;
> > + assigned-clock-parents = <
> IMX8MN_SYS_PLL1_100M>;
> > + clock-names = "main_clk";
> > + };
> > +
>
> Ditto
OK, I will move them to outside of soc.
Thanks,
Anson.
[PATCH 3/3] arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support
From: Anson Huang
This patch adds basic i.MM8MN DDR4 EVK board support.
Signed-off-by: Anson Huang
---
arch/arm64/boot/dts/freescale/Makefile| 1 +
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 217 ++
2 files changed, 218 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile
b/arch/arm64/boot/dts/freescale/Makefile
index 0bd122f..2cdd4cc 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -20,6 +20,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
new file mode 100644
index 000..da552c2
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+
+/ {
+ model = "NXP i.MX8MNano DDR4 EVK board";
+ compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
+
+ chosen {
+ stdout-path =
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO220x19
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MN_IOMUXC_G
[PATCH 2/3] arm64: dts: freescale: Add i.MX8MN dtsi support
From: Anson Huang
The i.MX8M Nano Media Applications Processor is a new SoC of the i.MX8M
family, it is a 14nm FinFET product of the growing mScale family targeting
the consumer market. It is built in Samsung 14LPP to achieve both high
performance and low power consumption and relies on a powerful fully
coherent core complex based on a quad core ARM Cortex-A53 cluster,
Cortex-M7 low-power coprocessor and graphics accelerator.
This patch adds the basic dtsi support for i.MX8MN.
Signed-off-by: Anson Huang
---
This patch should be based on below patches for clock and pinctrl head files:
https://patchwork.kernel.org/patch/10968059/
https://patchwork.kernel.org/patch/10968267/
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 701 ++
1 file changed, 701 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
new file mode 100644
index 000..c318ee6
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -0,0 +1,701 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+#include "imx8mn-pinfunc.h"
+
+/ {
+ compatible = "fsl,imx8mn";
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 =
+ gpio0 =
+ gpio1 =
+ gpio2 =
+ gpio3 =
+ gpio4 =
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ spi0 =
+ spi1 =
+ spi2 =
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A53_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ clock-latency = <61036>;
+ clocks = < IMX8MN_CLK_ARM>;
+ enable-method = "psci";
+ next-level-cache = <_L2>;
+ };
+
+ A53_L2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x0 0x4000 0 0x8000>;
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "osc_24m";
+ };
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13300>;
+ clock-output-names = "clk_ext1";
+ };
+
+ clk_ext2: clock-ext2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-
[PATCH 1/3] dt-bindings: arm: imx: Add the soc binding for i.MX8MN
From: Anson Huang This patch adds the soc & board binding for i.MX8MN. Signed-off-by: Anson Huang --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 407138e..b1a5231 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -171,6 +171,12 @@ properties: - const: compulab,cl-som-imx7 - const: fsl,imx7d + - description: i.MX8MN based Boards +items: + - enum: + - fsl,imx8mn-ddr4-evk# i.MX8MN DDR4 EVK Board + - const: fsl,imx8mn + - description: i.MX8MM based Boards items: - enum: -- 2.7.4
[PATCH 3/3] arm64: defconfig: Select CONFIG_CLK_IMX8MN by default
From: Anson Huang Enable CONFIG_CLK_IMX8MN to support i.MX8MN clock driver. Signed-off-by: Anson Huang --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8d4f25c..aef797c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -654,6 +654,7 @@ CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_S2MPS11=y CONFIG_CLK_QORIQ=y CONFIG_COMMON_CLK_PWM=y +CONFIG_CLK_IMX8MN=y CONFIG_CLK_IMX8MM=y CONFIG_CLK_IMX8MQ=y CONFIG_CLK_IMX8QXP=y -- 2.7.4
[PATCH 1/3] dt-bindings: imx: Add clock binding doc for i.MX8MN
From: Anson Huang
Add the clock binding doc for i.MX8MN.
Signed-off-by: Anson Huang
---
.../devicetree/bindings/clock/imx8mn-clock.txt | 29 +++
include/dt-bindings/clock/imx8mn-clock.h | 215 +
2 files changed, 244 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx8mn-clock.txt
create mode 100644 include/dt-bindings/clock/imx8mn-clock.h
diff --git a/Documentation/devicetree/bindings/clock/imx8mn-clock.txt
b/Documentation/devicetree/bindings/clock/imx8mn-clock.txt
new file mode 100644
index 000..d83db5c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx8mn-clock.txt
@@ -0,0 +1,29 @@
+* Clock bindings for NXP i.MX8M Nano
+
+Required properties:
+- compatible: Should be "fsl,imx8mn-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+- clocks: list of clock specifiers, must contain an entry for each required
+ entry in clock-names
+- clock-names: should include the following entries:
+- "osc_32k"
+- "osc_24m"
+- "clk_ext1"
+- "clk_ext2"
+- "clk_ext3"
+- "clk_ext4"
+
+clk: clock-controller@3038 {
+ compatible = "fsl,imx8mn-ccm";
+ reg = <0x0 0x3038 0x0 0x1>;
+ #clock-cells = <1>;
+ clocks = <_32k>, <_24m>, <_ext1>, <_ext2>,
+<_ext3>, <_ext4>;
+ clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
+ "clk_ext3", "clk_ext4";
+};
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
+for the full list of i.MX8M Nano clock IDs.
diff --git a/include/dt-bindings/clock/imx8mn-clock.h
b/include/dt-bindings/clock/imx8mn-clock.h
new file mode 100644
index 000..5255b1c
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
+#define __DT_BINDINGS_CLOCK_IMX8MN_H
+
+#define IMX8MN_CLK_DUMMY 0
+#define IMX8MN_CLK_32K 1
+#define IMX8MN_CLK_24M 2
+#define IMX8MN_OSC_HDMI_CLK3
+#define IMX8MN_CLK_EXT14
+#define IMX8MN_CLK_EXT25
+#define IMX8MN_CLK_EXT36
+#define IMX8MN_CLK_EXT47
+#define IMX8MN_AUDIO_PLL1_REF_SEL 8
+#define IMX8MN_AUDIO_PLL2_REF_SEL 9
+#define IMX8MN_VIDEO_PLL1_REF_SEL 10
+#define IMX8MN_DRAM_PLL_REF_SEL11
+#define IMX8MN_GPU_PLL_REF_SEL 12
+#define IMX8MN_VPU_PLL_REF_SEL 13
+#define IMX8MN_ARM_PLL_REF_SEL 14
+#define IMX8MN_SYS_PLL1_REF_SEL15
+#define IMX8MN_SYS_PLL2_REF_SEL16
+#define IMX8MN_SYS_PLL3_REF_SEL17
+#define IMX8MN_AUDIO_PLL1 18
+#define IMX8MN_AUDIO_PLL2 19
+#define IMX8MN_VIDEO_PLL1 20
+#define IMX8MN_DRAM_PLL21
+#define IMX8MN_GPU_PLL 22
+#define IMX8MN_VPU_PLL 23
+#define IMX8MN_ARM_PLL 24
+#define IMX8MN_SYS_PLL125
+#define IMX8MN_SYS_PLL226
+#define IMX8MN_SYS_PLL327
+#define IMX8MN_AUDIO_PLL1_BYPASS 28
+#define IMX8MN_AUDIO_PLL2_BYPASS 29
+#define IMX8MN_VIDEO_PLL1_BYPASS 30
+#define IMX8MN_DRAM_PLL_BYPASS 31
+#define IMX8MN_GPU_PLL_BYPASS 32
+#define IMX8MN_VPU_PLL_BYPASS 33
+#define IMX8MN_ARM_PLL_BYPASS 34
+#define IMX8MN_SYS_PLL1_BYPASS 35
+#define IMX8MN_SYS_PLL2_BYPASS 36
+#define IMX8MN_SYS_PLL3_BYPASS 37
+#define IMX8MN_AUDIO_PLL1_OUT 38
+#define IMX8MN_AUDIO_PLL2_OUT 39
+#define IMX8MN_VIDEO_PLL1_OUT 40
+#define IMX8MN_DRAM_PLL_OUT41
+#define IMX8MN_GPU_PLL_OUT 42
+#define IMX8MN_VPU_PLL_OUT 43
+#define IMX8MN_ARM_PLL_OUT 44
+#define IMX8MN_SYS_PLL1_OUT45
+#define IMX8MN_SYS_PLL2_OUT46
+#define IMX8MN_SYS_PLL3_OUT47
+#define IMX8MN_SYS_PLL1_40M48
+#define IMX8MN_SYS_PLL1_80M49
+#define IMX8MN_SYS_PLL1_100M 50
+#define IMX8MN_SYS_PLL1_133M 51
[PATCH 2/3] clk: imx: Add support for i.MX8MN clock driver
From: Anson Huang
This patch adds i.MX8MN clock driver support.
Signed-off-by: Anson Huang
---
drivers/clk/imx/Kconfig | 6 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx8mn.c | 609 +++
3 files changed, 616 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mn.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 0eaf418..1ac0c79 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -14,6 +14,12 @@ config CLK_IMX8MM
help
Build the driver for i.MX8MM CCM Clock Driver
+config CLK_IMX8MN
+ bool "IMX8MN CCM Clock Driver"
+ depends on ARCH_MXC && ARM64
+ help
+ Build the driver for i.MX8MN CCM Clock Driver
+
config CLK_IMX8MQ
bool "IMX8MQ CCM Clock Driver"
depends on ARCH_MXC && ARM64
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 05641c6..70a55cd 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_MXC_CLK_SCU) += \
clk-scu.o \
clk-lpcg-scu.o
+obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
new file mode 100644
index 000..c38dcd3
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -0,0 +1,609 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018-2019 NXP.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+static u32 share_count_sai2;
+static u32 share_count_sai3;
+static u32 share_count_sai5;
+static u32 share_count_sai6;
+static u32 share_count_sai7;
+static u32 share_count_disp;
+static u32 share_count_pdm;
+static u32 share_count_nand;
+
+enum {
+ ARM_PLL,
+ GPU_PLL,
+ VPU_PLL,
+ SYS_PLL1,
+ SYS_PLL2,
+ SYS_PLL3,
+ DRAM_PLL,
+ AUDIO_PLL1,
+ AUDIO_PLL2,
+ VIDEO_PLL2,
+ NR_PLLS,
+};
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate),\
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
+ PLL_1416X_RATE(18U, 225, 3, 0),
+ PLL_1416X_RATE(16U, 200, 3, 0),
+ PLL_1416X_RATE(12U, 300, 3, 1),
+ PLL_1416X_RATE(10U, 250, 3, 1),
+ PLL_1416X_RATE(8U, 200, 3, 1),
+ PLL_1416X_RATE(75000U, 250, 2, 2),
+ PLL_1416X_RATE(7U, 350, 3, 2),
+ PLL_1416X_RATE(6U, 300, 3, 2),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
+ PLL_1443X_RATE(786432000U, 655, 5, 2, 23593),
+ PLL_1443X_RATE(722534400U, 301, 5, 1, 3670),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+ PLL_1443X_RATE(59400U, 198, 2, 2, 0),
+};
+
+static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
+ PLL_1443X_RATE(65000U, 325, 3, 2, 0),
+};
+
+static struct imx_pll14xx_clk imx8mn_audio_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_audiopll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_video_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_videopll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_dram_pll __initdata = {
+ .type = PLL_1443X,
+ .rate_table = imx8mn_drampll_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_arm_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_gpu_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_vpu_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll1416x_tbl,
+};
+
+static struct imx_pll14xx_clk imx8mn_sys_pll __initdata = {
+ .type = PLL_1416X,
+ .rate_table = imx8mn_pll141
[PATCH] dt-bindings: imx: Correct pinfunc head file path for i.MX8MM
From: Anson Huang The i.MX8MM pinfunc head file is located in DT folder, correct it. Signed-off-by: Anson Huang --- Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt index 524a16f..e4e01c0 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt @@ -12,7 +12,7 @@ Required properties in sub-nodes: - fsl,pins: each entry consists of 6 integers and represents the mux and config setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in - . The last integer CONFIG is + . The last integer CONFIG is the pad setting value like pull-up on this pin. Please refer to i.MX8M Mini Reference Manual for detailed CONFIG settings. -- 2.7.4
[PATCH 1/3] dt-bindings: imx: Add pinctrl binding doc for i.MX8MN
From: Anson Huang
Add binding doc for i.MX8MN pinctrl driver.
Signed-off-by: Anson Huang
---
.../bindings/pinctrl/fsl,imx8mn-pinctrl.txt| 39 ++
arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h | 646 +
2 files changed, 685 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt
create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt
new file mode 100644
index 000..330716c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt
@@ -0,0 +1,39 @@
+* Freescale IMX8MN IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
+for common binding part and usage.
+
+Required properties:
+- compatible: "fsl,imx8mn-iomuxc"
+- reg: should contain the base physical address and size of the iomuxc
+ registers.
+
+Required properties in sub-nodes:
+- fsl,pins: each entry consists of 6 integers and represents the mux and config
+ setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in
+ . The last integer CONFIG is
+ the pad setting value like pull-up on this pin. Please refer to i.MX8M Nano
+ Reference Manual for detailed CONFIG settings.
+
+Examples:
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_uart1>;
+};
+
+iomuxc: pinctrl@3033 {
+compatible = "fsl,imx8mn-iomuxc";
+reg = <0x0 0x3033 0x0 0x1>;
+
+pinctrl_uart1: uart1grp {
+fsl,pins = <
+ MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
+ MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
+ MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO60x19
+>;
+};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h
b/arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h
new file mode 100644
index 000..faf1e69
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h
@@ -0,0 +1,646 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __DTS_IMX8MN_PINFUNC_H
+#define __DTS_IMX8MN_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ *
+ */
+
+#define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2
0x020 0x25C 0x000 0x0 0x0
+#define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL
0x020 0x25C 0x55C 0x1 0x3
+#define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3
0x024 0x260 0x000 0x0 0x0
+#define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA
0x024 0x260 0x56C 0x1 0x3
+#define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0
0x028 0x290 0x000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT
0x028 0x290 0x000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
0x028 0x290 0x000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1
0x028 0x290 0x000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1
0x02C 0x294 0x000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT
0x02C 0x294 0x000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M
0x02C 0x294 0x000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2
0x02C 0x294 0x000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2
0x030 0x298 0x000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B
0x030 0x298 0x000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY
0x030 0x298 0x000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3
0x034 0x29C 0x000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT
0x034 0x29C 0x000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0
0x034 0x29C 0x000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK
0x034 0x29C 0x000 0x6 0x0
+#define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4
0x038 0x2A0 0x000 0x0 0x0
+#define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
0x038 0x2A0 0x000 0x1 0x0
+#define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1
0x038 0x2A0 0x000 0x5 0x0
+#define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV
[PATCH 2/3] pinctrl: freescale: Add i.MX8MN pinctrl driver support
From: Anson Huang
Add the pinctrl driver support for i.MX8MN.
Signed-off-by: Anson Huang
---
drivers/pinctrl/freescale/Kconfig | 7 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx8mn.c | 348 +
3 files changed, 356 insertions(+)
create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8mn.c
diff --git a/drivers/pinctrl/freescale/Kconfig
b/drivers/pinctrl/freescale/Kconfig
index aeab0d9..4ff52fa 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -123,6 +123,13 @@ config PINCTRL_IMX7ULP
help
Say Y here to enable the imx7ulp pinctrl driver
+config PINCTRL_IMX8MN
+ bool "IMX8MN pinctrl driver"
+ depends on ARCH_MXC && ARM64
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx8mn pinctrl driver
+
config PINCTRL_IMX8MM
bool "IMX8MM pinctrl driver"
depends on ARCH_MXC && ARM64
diff --git a/drivers/pinctrl/freescale/Makefile
b/drivers/pinctrl/freescale/Makefile
index 02020a7..18225da 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D)+= pinctrl-imx7d.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
+obj-$(CONFIG_PINCTRL_IMX8MN) += pinctrl-imx8mn.o
obj-$(CONFIG_PINCTRL_IMX8MM) += pinctrl-imx8mm.o
obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mn.c
b/drivers/pinctrl/freescale/pinctrl-imx8mn.c
new file mode 100644
index 000..67161df
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx8mn.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-imx.h"
+
+enum imx8mn_pads {
+ MX8MN_PAD_RESERVE0 = 0,
+ MX8MN_PAD_RESERVE1 = 1,
+ MX8MN_PAD_RESERVE2 = 2,
+ MX8MN_PAD_RESERVE3 = 3,
+ MX8MN_PAD_RESERVE4 = 4,
+ MX8MN_PAD_RESERVE5 = 5,
+ MX8MN_PAD_RESERVE6 = 6,
+ MX8MN_PAD_RESERVE7 = 7,
+ MX8MN_IOMUXC_BOOT_MODE2 = 8,
+ MX8MN_IOMUXC_BOOT_MODE3 = 9,
+ MX8MN_IOMUXC_GPIO1_IO00 = 10,
+ MX8MN_IOMUXC_GPIO1_IO01 = 11,
+ MX8MN_IOMUXC_GPIO1_IO02 = 12,
+ MX8MN_IOMUXC_GPIO1_IO03 = 13,
+ MX8MN_IOMUXC_GPIO1_IO04 = 14,
+ MX8MN_IOMUXC_GPIO1_IO05 = 15,
+ MX8MN_IOMUXC_GPIO1_IO06 = 16,
+ MX8MN_IOMUXC_GPIO1_IO07 = 17,
+ MX8MN_IOMUXC_GPIO1_IO08 = 18,
+ MX8MN_IOMUXC_GPIO1_IO09 = 19,
+ MX8MN_IOMUXC_GPIO1_IO10 = 20,
+ MX8MN_IOMUXC_GPIO1_IO11 = 21,
+ MX8MN_IOMUXC_GPIO1_IO12 = 22,
+ MX8MN_IOMUXC_GPIO1_IO13 = 23,
+ MX8MN_IOMUXC_GPIO1_IO14 = 24,
+ MX8MN_IOMUXC_GPIO1_IO15 = 25,
+ MX8MN_IOMUXC_ENET_MDC = 26,
+ MX8MN_IOMUXC_ENET_MDIO = 27,
+ MX8MN_IOMUXC_ENET_TD3 = 28,
+ MX8MN_IOMUXC_ENET_TD2 = 29,
+ MX8MN_IOMUXC_ENET_TD1 = 30,
+ MX8MN_IOMUXC_ENET_TD0 = 31,
+ MX8MN_IOMUXC_ENET_TX_CTL = 32,
+ MX8MN_IOMUXC_ENET_TXC = 33,
+ MX8MN_IOMUXC_ENET_RX_CTL = 34,
+ MX8MN_IOMUXC_ENET_RXC = 35,
+ MX8MN_IOMUXC_ENET_RD0 = 36,
+ MX8MN_IOMUXC_ENET_RD1 = 37,
+ MX8MN_IOMUXC_ENET_RD2 = 38,
+ MX8MN_IOMUXC_ENET_RD3 = 39,
+ MX8MN_IOMUXC_SD1_CLK = 40,
+ MX8MN_IOMUXC_SD1_CMD = 41,
+ MX8MN_IOMUXC_SD1_DATA0 = 42,
+ MX8MN_IOMUXC_SD1_DATA1 = 43,
+ MX8MN_IOMUXC_SD1_DATA2 = 44,
+ MX8MN_IOMUXC_SD1_DATA3 = 45,
+ MX8MN_IOMUXC_SD1_DATA4 = 46,
+ MX8MN_IOMUXC_SD1_DATA5 = 47,
+ MX8MN_IOMUXC_SD1_DATA6 = 48,
+ MX8MN_IOMUXC_SD1_DATA7 = 49,
+ MX8MN_IOMUXC_SD1_RESET_B = 50,
+ MX8MN_IOMUXC_SD1_STROBE = 51,
+ MX8MN_IOMUXC_SD2_CD_B = 52,
+ MX8MN_IOMUXC_SD2_CLK = 53,
+ MX8MN_IOMUXC_SD2_CMD = 54,
+ MX8MN_IOMUXC_SD2_DATA0 = 55,
+ MX8MN_IOMUXC_SD2_DATA1 = 56,
+ MX8MN_IOMUXC_SD2_DATA2 = 57,
+ MX8MN_IOMUXC_SD2_DATA3 = 58,
+ MX8MN_IOMUXC_SD2_RESET_B = 59,
+ MX8MN_IOMUXC_SD2_WP = 60,
+ MX8MN_IOMUXC_NAND_ALE = 61,
+ MX8MN_IOMUXC_NAND_CE0 = 62,
+ MX8MN_IOMUXC_NAND_CE1 = 63,
+ MX8MN_IOMUXC_NAND_CE2 = 64,
+ MX8MN_IOMUXC_NAND_CE3 = 65,
+ MX8MN_IOMUXC_NAND_CLE = 66,
+ MX8MN_IOMUXC_NAND_DATA00 = 67,
+ MX8MN_IOMUXC_NAND_DATA01 = 68,
+ MX8MN_IOMUXC_NAND_DATA02 = 69,
+ MX8MN_IOMUXC_NAND_DATA03 = 70,
+ MX8MN_IOMUXC_NAND_DATA04 = 71,
+ MX8MN_IOMUXC_NAND_DATA05 = 72,
+ MX8MN_IOMUXC_NAND_DATA06 = 73,
+ MX8MN_IOMUXC_NAND_DATA07 = 74,
+ MX8MN_IOMUXC_NAND_DQS = 75,
+ MX8MN_IOMUXC_NAND_RE_B = 76,
+ MX8MN_IOMUXC_NAND_READY_B = 77,
+ MX8MN_IOMUXC_NAND_WE_B = 78,
+ MX8MN_IOMUXC_NAND_
