[PATCH v1] [media] uvcvideo: mark buffer error where overflow
Some cameras post inaccurate frame where next frame data overlap
it. this results in screen flicker, and it need to be prevented.
So this patch marks the buffer error to discard the frame where
buffer overflow.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
drivers/media/usb/uvc/uvc_video.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/media/usb/uvc/uvc_video.c
b/drivers/media/usb/uvc/uvc_video.c
index fb86d6a..81a3530 100644
--- a/drivers/media/usb/uvc/uvc_video.c
+++ b/drivers/media/usb/uvc/uvc_video.c
@@ -1077,6 +1077,7 @@ static void uvc_video_decode_data(struct uvc_streaming
*stream,
/* Complete the current frame if the buffer size was exceeded. */
if (len > maxlen) {
uvc_trace(UVC_TRACE_FRAME, "Frame complete (overflow).\n");
+ buf->error = 1;
buf->state = UVC_BUF_STATE_READY;
}
}
--
2.7.4
[PATCH v1] [media] uvcvideo: mark buffer error where overflow
Some cameras post inaccurate frame where next frame data overlap
it. this results in screen flicker, and it need to be prevented.
So this patch marks the buffer error to discard the frame where
buffer overflow.
Signed-off-by: Baoyou Xie
---
drivers/media/usb/uvc/uvc_video.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/media/usb/uvc/uvc_video.c
b/drivers/media/usb/uvc/uvc_video.c
index fb86d6a..81a3530 100644
--- a/drivers/media/usb/uvc/uvc_video.c
+++ b/drivers/media/usb/uvc/uvc_video.c
@@ -1077,6 +1077,7 @@ static void uvc_video_decode_data(struct uvc_streaming
*stream,
/* Complete the current frame if the buffer size was exceeded. */
if (len > maxlen) {
uvc_trace(UVC_TRACE_FRAME, "Frame complete (overflow).\n");
+ buf->error = 1;
buf->state = UVC_BUF_STATE_READY;
}
}
--
2.7.4
[PATCH v1] [media] uvcvideo: mark buffer error where overflow
Some cameras post inaccurate frame where next frame data overlap
it. this results in screen flicker, and it need to be prevented.
So this patch marks the buffer error to discard the frame where
buffer overflow.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
drivers/media/usb/uvc/uvc_video.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/media/usb/uvc/uvc_video.c
b/drivers/media/usb/uvc/uvc_video.c
index fb86d6a..81a3530 100644
--- a/drivers/media/usb/uvc/uvc_video.c
+++ b/drivers/media/usb/uvc/uvc_video.c
@@ -1077,6 +1077,7 @@ static void uvc_video_decode_data(struct uvc_streaming
*stream,
/* Complete the current frame if the buffer size was exceeded. */
if (len > maxlen) {
uvc_trace(UVC_TRACE_FRAME, "Frame complete (overflow).\n");
+ buf->error = 1;
buf->state = UVC_BUF_STATE_READY;
}
}
--
2.7.4
[PATCH v1] [media] uvcvideo: mark buffer error where overflow
Some cameras post inaccurate frame where next frame data overlap
it. this results in screen flicker, and it need to be prevented.
So this patch marks the buffer error to discard the frame where
buffer overflow.
Signed-off-by: Baoyou Xie
---
drivers/media/usb/uvc/uvc_video.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/media/usb/uvc/uvc_video.c
b/drivers/media/usb/uvc/uvc_video.c
index fb86d6a..81a3530 100644
--- a/drivers/media/usb/uvc/uvc_video.c
+++ b/drivers/media/usb/uvc/uvc_video.c
@@ -1077,6 +1077,7 @@ static void uvc_video_decode_data(struct uvc_streaming
*stream,
/* Complete the current frame if the buffer size was exceeded. */
if (len > maxlen) {
uvc_trace(UVC_TRACE_FRAME, "Frame complete (overflow).\n");
+ buf->error = 1;
buf->state = UVC_BUF_STATE_READY;
}
}
--
2.7.4
[PATCH v8 3/3] i2c: zx2967: add i2c controller driver for ZTE's zx2967 family
This patch adds i2c controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Reviewed-by: Shawn Guo <shawn...@kernel.org>
Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com>
Reviewed-by: Jun Nie <jun@linaro.org>
---
drivers/i2c/busses/Kconfig | 9 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-zx2967.c | 646
3 files changed, 656 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-zx2967.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e4a603e..d983e36 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1246,4 +1246,13 @@ config I2C_OPAL
This driver can also be built as a module. If so, the module will be
called as i2c-opal.
+config I2C_ZX2967
+ tristate "ZTE zx2967 I2C support"
+ depends on ARCH_ZX
+ default y
+ help
+ Selecting this option will add ZX2967 I2C driver.
+ This driver can also be built as a module. If so, the module will be
+ called i2c-zx2967.
+
endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index beb4809..16b2901 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_XILINX)+= i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
+obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
diff --git a/drivers/i2c/busses/i2c-zx2967.c b/drivers/i2c/busses/i2c-zx2967.c
new file mode 100644
index 000..fe20ef8
--- /dev/null
+++ b/drivers/i2c/busses/i2c-zx2967.c
@@ -0,0 +1,646 @@
+/*
+ * ZTE's zx2967 family i2c bus controller driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie <baoyou@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_CMD0x04
+#define REG_DEVADDR_H 0x0C
+#define REG_DEVADDR_L 0x10
+#define REG_CLK_DIV_FS 0x14
+#define REG_CLK_DIV_HS 0x18
+#define REG_WRCONF 0x1C
+#define REG_RDCONF 0x20
+#define REG_DATA 0x24
+#define REG_STAT 0x28
+
+#define I2C_STOP 0
+#define I2C_MASTER BIT(0)
+#define I2C_ADDR_MODE_TEN BIT(1)
+#define I2C_IRQ_MSK_ENABLE BIT(3)
+#define I2C_RW_READBIT(4)
+#define I2C_CMB_RW_EN BIT(5)
+#define I2C_START BIT(6)
+
+#define I2C_ADDR_LOW_MASK GENMASK(6, 0)
+#define I2C_ADDR_LOW_SHIFT 0
+#define I2C_ADDR_HI_MASK GENMASK(2, 0)
+#define I2C_ADDR_HI_SHIFT 7
+
+#define I2C_WFIFO_RESETBIT(7)
+#define I2C_RFIFO_RESETBIT(7)
+
+#define I2C_IRQ_ACK_CLEAR BIT(7)
+#define I2C_INT_MASK GENMASK(6, 0)
+
+#define I2C_TRANS_DONE BIT(0)
+#define I2C_ERROR_DEVICE BIT(1)
+#define I2C_ERROR_DATA BIT(2)
+#define I2C_ERROR_MASK GENMASK(2, 1)
+
+#define I2C_SR_BUSYBIT(6)
+
+#define I2C_SR_EDEVICE BIT(1)
+#define I2C_SR_EDATA BIT(2)
+
+#define I2C_FIFO_MAX 16
+
+#define I2C_TIMEOUTmsecs_to_jiffies(1000)
+
+#define DEV(i2c) (>adap.dev)
+
+struct zx2967_i2c_info {
+ struct i2c_adapter adap;
+ struct clk *clk;
+ struct completion complete;
+ u32 clk_freq;
+ void __iomem*reg_base;
+ size_t residue;
+ int irq;
+ int msg_rd;
+ u8 *cur_trans;
+ u8 access_cnt;
+ boolis_suspended;
+};
+
+static void zx2967_i2c_writel(struct zx2967_i2c_info *zx_i2c,
+ u32 val, unsigned long reg)
+{
+ writel_relaxed(val, zx_i2c->reg_base + reg);
+}
+
+static u32 zx2967_i2c_readl(struct zx2967_i2c_info *zx_i2c, unsigned long reg)
+{
+ return readl_relaxed(zx_i2c->reg_base + reg);
+}
+
+static void zx2967_i2c_writesb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ writesb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_readsb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ readsb(z
[PATCH v8 3/3] i2c: zx2967: add i2c controller driver for ZTE's zx2967 family
This patch adds i2c controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie
Reviewed-by: Shawn Guo
Reviewed-by: Andy Shevchenko
Reviewed-by: Jun Nie
---
drivers/i2c/busses/Kconfig | 9 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-zx2967.c | 646
3 files changed, 656 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-zx2967.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e4a603e..d983e36 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1246,4 +1246,13 @@ config I2C_OPAL
This driver can also be built as a module. If so, the module will be
called as i2c-opal.
+config I2C_ZX2967
+ tristate "ZTE zx2967 I2C support"
+ depends on ARCH_ZX
+ default y
+ help
+ Selecting this option will add ZX2967 I2C driver.
+ This driver can also be built as a module. If so, the module will be
+ called i2c-zx2967.
+
endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index beb4809..16b2901 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_XILINX)+= i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
+obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
diff --git a/drivers/i2c/busses/i2c-zx2967.c b/drivers/i2c/busses/i2c-zx2967.c
new file mode 100644
index 000..fe20ef8
--- /dev/null
+++ b/drivers/i2c/busses/i2c-zx2967.c
@@ -0,0 +1,646 @@
+/*
+ * ZTE's zx2967 family i2c bus controller driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_CMD0x04
+#define REG_DEVADDR_H 0x0C
+#define REG_DEVADDR_L 0x10
+#define REG_CLK_DIV_FS 0x14
+#define REG_CLK_DIV_HS 0x18
+#define REG_WRCONF 0x1C
+#define REG_RDCONF 0x20
+#define REG_DATA 0x24
+#define REG_STAT 0x28
+
+#define I2C_STOP 0
+#define I2C_MASTER BIT(0)
+#define I2C_ADDR_MODE_TEN BIT(1)
+#define I2C_IRQ_MSK_ENABLE BIT(3)
+#define I2C_RW_READBIT(4)
+#define I2C_CMB_RW_EN BIT(5)
+#define I2C_START BIT(6)
+
+#define I2C_ADDR_LOW_MASK GENMASK(6, 0)
+#define I2C_ADDR_LOW_SHIFT 0
+#define I2C_ADDR_HI_MASK GENMASK(2, 0)
+#define I2C_ADDR_HI_SHIFT 7
+
+#define I2C_WFIFO_RESETBIT(7)
+#define I2C_RFIFO_RESETBIT(7)
+
+#define I2C_IRQ_ACK_CLEAR BIT(7)
+#define I2C_INT_MASK GENMASK(6, 0)
+
+#define I2C_TRANS_DONE BIT(0)
+#define I2C_ERROR_DEVICE BIT(1)
+#define I2C_ERROR_DATA BIT(2)
+#define I2C_ERROR_MASK GENMASK(2, 1)
+
+#define I2C_SR_BUSYBIT(6)
+
+#define I2C_SR_EDEVICE BIT(1)
+#define I2C_SR_EDATA BIT(2)
+
+#define I2C_FIFO_MAX 16
+
+#define I2C_TIMEOUTmsecs_to_jiffies(1000)
+
+#define DEV(i2c) (>adap.dev)
+
+struct zx2967_i2c_info {
+ struct i2c_adapter adap;
+ struct clk *clk;
+ struct completion complete;
+ u32 clk_freq;
+ void __iomem*reg_base;
+ size_t residue;
+ int irq;
+ int msg_rd;
+ u8 *cur_trans;
+ u8 access_cnt;
+ boolis_suspended;
+};
+
+static void zx2967_i2c_writel(struct zx2967_i2c_info *zx_i2c,
+ u32 val, unsigned long reg)
+{
+ writel_relaxed(val, zx_i2c->reg_base + reg);
+}
+
+static u32 zx2967_i2c_readl(struct zx2967_i2c_info *zx_i2c, unsigned long reg)
+{
+ return readl_relaxed(zx_i2c->reg_base + reg);
+}
+
+static void zx2967_i2c_writesb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ writesb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_readsb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ readsb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_start_ctrl(struct zx2967_i2c_info *zx_i2c)
+{
+ u32 status;
+ u32 ctl;
+
+
[PATCH v8 2/3] MAINTAINERS: add zx2967 i2c controller driver to ARM ZTE architecture
Add the zx2967 i2c controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..313fab5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1987,9 +1987,11 @@ L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-zx/ F: drivers/clk/zte/ +F: drivers/i2c/busses/i2c-zx2967.c F: drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt +F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt F: Documentation/devicetree/bindings/soc/zte/ F: include/dt-bindings/soc/zx*.h -- 2.7.4
[PATCH v8 1/3] dt: bindings: add documentation for zx2967 family i2c controller
This patch adds dt-binding documentation for zx2967 family
i2c controller.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Acked-by: Rob Herring <r...@kernel.org>
---
.../devicetree/bindings/i2c/i2c-zx2967.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
new file mode 100644
index 000..a528374
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
@@ -0,0 +1,24 @@
+ZTE zx2967 I2C controller
+
+Required properties:
+ - compatible: must be "zte,zx296718-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+ - clock-frequency: the desired I2C bus clock frequency.
+
+Examples:
+
+ i2c@112000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x00112000 0x1000>;
+ interrupts = ;
+ clocks = <>;
+ #address-cells = <1>
+ #size-cells = <0>;
+ clock-frequency = <160>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ };
--
2.7.4
[PATCH v8 1/3] dt: bindings: add documentation for zx2967 family i2c controller
This patch adds dt-binding documentation for zx2967 family
i2c controller.
Signed-off-by: Baoyou Xie
Acked-by: Rob Herring
---
.../devicetree/bindings/i2c/i2c-zx2967.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
new file mode 100644
index 000..a528374
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
@@ -0,0 +1,24 @@
+ZTE zx2967 I2C controller
+
+Required properties:
+ - compatible: must be "zte,zx296718-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+ - clock-frequency: the desired I2C bus clock frequency.
+
+Examples:
+
+ i2c@112000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x00112000 0x1000>;
+ interrupts = ;
+ clocks = <>;
+ #address-cells = <1>
+ #size-cells = <0>;
+ clock-frequency = <160>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ };
--
2.7.4
[PATCH v8 2/3] MAINTAINERS: add zx2967 i2c controller driver to ARM ZTE architecture
Add the zx2967 i2c controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..313fab5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1987,9 +1987,11 @@ L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-zx/ F: drivers/clk/zte/ +F: drivers/i2c/busses/i2c-zx2967.c F: drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt +F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt F: Documentation/devicetree/bindings/soc/zte/ F: include/dt-bindings/soc/zx*.h -- 2.7.4
[PATCH v2 3/3] ASoC: zx-tdm: add zte's tdm controller driver
This patch adds tdm controller driver for zte's SoC family.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
sound/soc/zte/Kconfig | 8 +
sound/soc/zte/Makefile | 1 +
sound/soc/zte/zx-tdm.c | 461 +
3 files changed, 470 insertions(+)
create mode 100644 sound/soc/zte/zx-tdm.c
diff --git a/sound/soc/zte/Kconfig b/sound/soc/zte/Kconfig
index 6d8a90d..75f67a5 100644
--- a/sound/soc/zte/Kconfig
+++ b/sound/soc/zte/Kconfig
@@ -15,3 +15,11 @@ config ZX_I2S
help
Say Y or M if you want to add support for codecs attached to the
ZTE ZX I2S interface
+
+config ZX_TDM
+tristate "ZTE ZX TDM Driver Support"
+depends on COMMON_CLK
+select SND_SOC_GENERIC_DMAENGINE_PCM
+help
+ Say Y or M if you want to add support for codecs attached to the
+ ZTE ZX TDM interface
diff --git a/sound/soc/zte/Makefile b/sound/soc/zte/Makefile
index 77768f5..1fc841a 100644
--- a/sound/soc/zte/Makefile
+++ b/sound/soc/zte/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_ZX_SPDIF) += zx-spdif.o
obj-$(CONFIG_ZX_I2S) += zx-i2s.o
+obj-$(CONFIG_ZX_TDM) += zx-tdm.o
diff --git a/sound/soc/zte/zx-tdm.c b/sound/soc/zte/zx-tdm.c
new file mode 100644
index 000..bd632cc
--- /dev/null
+++ b/sound/soc/zte/zx-tdm.c
@@ -0,0 +1,461 @@
+/*
+ * ZTE's TDM driver
+ *
+ * Copyright (C) 2017 ZTE Ltd
+ *
+ * Author: Baoyou Xie <baoyou@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#defineREG_TIMING_CTRL 0x04
+#defineREG_TX_FIFO_CTRL0x0C
+#defineREG_RX_FIFO_CTRL0x10
+#define REG_INT_EN 0x1C
+#define REG_INT_STATUS 0x20
+#define REG_DATABUF0x24
+#define REG_TS_MASK0 0x44
+#define REG_PROCESS_CTRL 0x54
+
+#define FIFO_CTRL_TX_RST BIT(0)
+#define FIFO_CTRL_RX_RST BIT(0)
+#define DEAGULT_FIFO_THRES GENMASK(4, 2)
+
+#define FIFO_CTRL_TX_DMA_ENBIT(1)
+#define FIFO_CTRL_RX_DMA_ENBIT(1)
+
+#define TX_FIFO_RST_MASK BIT(0)
+#define RX_FIFO_RST_MASK BIT(0)
+
+#define FIFOCTRL_TX_FIFO_RST BIT(0)
+#define FIFOCTRL_RX_FIFO_RST BIT(0)
+
+#define TXTH_MASK GENMASK(5, 2)
+#define RXTH_MASK GENMASK(5, 2)
+
+#define FIFOCTRL_THRESHOLD(x) ((x) << 2)
+
+#define TIMING_MS_MASK BIT(1)
+/*
+ * 00: 8 clk cycles every timeslot
+ * 01: 16 clk cycles every timeslot
+ * 10: 32 clk cycles every timeslot
+ */
+#define TIMING_SYNC_WIDTH_MASK GENMASK(6, 5)
+#define TIMING_WIDTH_SHIFT 5
+#define TIMING_DEFAULT_WIDTH0
+#define TIMING_TS_WIDTH(x) ((x) << TIMING_WIDTH_SHIFT)
+#define TIMING_WIDTH_FACTOR 8
+
+#define TIMING_MASTER_MODE BIT(21)
+#define TIMING_LSB_FIRST BIT(20)
+#define TIMING_TS_NUM(x) (((x) - 1) << 7)
+#define TIMING_CLK_SEL_MASKGENMASK(2, 0)
+#define TIMING_CLK_SEL_DEF BIT(2)
+
+#define PROCESS_TX_EN BIT(0)
+#define PROCESS_RX_EN BIT(1)
+#define PROCESS_TDM_EN BIT(2)
+#define PROCESS_DISABLE_ALL0
+
+#define INT_DISABLE_ALL0
+#define INT_STATUS_MASKGENMASK(6, 0)
+
+struct zx_tdm_info {
+ struct snd_dmaengine_dai_dma_data dma_playback;
+ struct snd_dmaengine_dai_dma_data dma_capture;
+ resource_size_t phy_addr;
+ void __iomem*regbase;
+ struct clk *dai_wclk;
+ struct clk *dai_pclk;
+ int master;
+ struct device *dev;
+};
+
+static inline u32 zx_tdm_readl(struct zx_tdm_info *tdm, u16 reg)
+{
+ return readl_relaxed(tdm->regbase + reg);
+}
+
+static inline void zx_tdm_writel(struct zx_tdm_info *tdm, u16 reg, u32 val)
+{
+ writel_relaxed(val, tdm->regbase + reg);
+}
+
+static void zx_tdm_tx_en(struct zx_tdm_info *tdm, bool on)
+{
+ unsigned long val;
+
+ val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
+ if (on)
+ val |= PROCESS_TX_EN | PROCESS_TDM_EN;
+ else
+ val &= ~(PROCESS_TX_EN | PROCESS_TDM_EN);
+ zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
+}
+
+static void zx_tdm_rx_en(struct zx_tdm_info *tdm, bool on)
+{
+ unsigned long val;
+
+ val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
+ if (on)
+ val |= PROCESS_RX_EN | PROCESS_TDM_EN;
+ else
+ val &= ~(PROCESS_RX_EN | PROCESS_TDM_EN);
+ zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
+}
+
+static void zx_tdm_tx_dma_en(struct zx_tdm_info *tdm, bool on)
+{
+ unsigned long val;
+
+ val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);
+ val |= FIFO_CTRL_TX_RST | DEAGULT_FIFO_THRES;
+ if (on)
+
[PATCH v2 2/3] MAINTAINERS: add zte tdm controller driver to ARM ZTE architecture
Add the zte tdm controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..1269eb6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1991,7 +1991,9 @@ F:drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/soc/zte/ +F: Documentation/devicetree/bindings/sound/zte,zx-tdm.txt F: include/dt-bindings/soc/zx*.h +F: sound/soc/zte/zx-tdm.c ARM/ZYNQ ARCHITECTURE M: Michal Simek <michal.si...@xilinx.com> -- 2.7.4
[PATCH v2 3/3] ASoC: zx-tdm: add zte's tdm controller driver
This patch adds tdm controller driver for zte's SoC family.
Signed-off-by: Baoyou Xie
---
sound/soc/zte/Kconfig | 8 +
sound/soc/zte/Makefile | 1 +
sound/soc/zte/zx-tdm.c | 461 +
3 files changed, 470 insertions(+)
create mode 100644 sound/soc/zte/zx-tdm.c
diff --git a/sound/soc/zte/Kconfig b/sound/soc/zte/Kconfig
index 6d8a90d..75f67a5 100644
--- a/sound/soc/zte/Kconfig
+++ b/sound/soc/zte/Kconfig
@@ -15,3 +15,11 @@ config ZX_I2S
help
Say Y or M if you want to add support for codecs attached to the
ZTE ZX I2S interface
+
+config ZX_TDM
+tristate "ZTE ZX TDM Driver Support"
+depends on COMMON_CLK
+select SND_SOC_GENERIC_DMAENGINE_PCM
+help
+ Say Y or M if you want to add support for codecs attached to the
+ ZTE ZX TDM interface
diff --git a/sound/soc/zte/Makefile b/sound/soc/zte/Makefile
index 77768f5..1fc841a 100644
--- a/sound/soc/zte/Makefile
+++ b/sound/soc/zte/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_ZX_SPDIF) += zx-spdif.o
obj-$(CONFIG_ZX_I2S) += zx-i2s.o
+obj-$(CONFIG_ZX_TDM) += zx-tdm.o
diff --git a/sound/soc/zte/zx-tdm.c b/sound/soc/zte/zx-tdm.c
new file mode 100644
index 000..bd632cc
--- /dev/null
+++ b/sound/soc/zte/zx-tdm.c
@@ -0,0 +1,461 @@
+/*
+ * ZTE's TDM driver
+ *
+ * Copyright (C) 2017 ZTE Ltd
+ *
+ * Author: Baoyou Xie
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#defineREG_TIMING_CTRL 0x04
+#defineREG_TX_FIFO_CTRL0x0C
+#defineREG_RX_FIFO_CTRL0x10
+#define REG_INT_EN 0x1C
+#define REG_INT_STATUS 0x20
+#define REG_DATABUF0x24
+#define REG_TS_MASK0 0x44
+#define REG_PROCESS_CTRL 0x54
+
+#define FIFO_CTRL_TX_RST BIT(0)
+#define FIFO_CTRL_RX_RST BIT(0)
+#define DEAGULT_FIFO_THRES GENMASK(4, 2)
+
+#define FIFO_CTRL_TX_DMA_ENBIT(1)
+#define FIFO_CTRL_RX_DMA_ENBIT(1)
+
+#define TX_FIFO_RST_MASK BIT(0)
+#define RX_FIFO_RST_MASK BIT(0)
+
+#define FIFOCTRL_TX_FIFO_RST BIT(0)
+#define FIFOCTRL_RX_FIFO_RST BIT(0)
+
+#define TXTH_MASK GENMASK(5, 2)
+#define RXTH_MASK GENMASK(5, 2)
+
+#define FIFOCTRL_THRESHOLD(x) ((x) << 2)
+
+#define TIMING_MS_MASK BIT(1)
+/*
+ * 00: 8 clk cycles every timeslot
+ * 01: 16 clk cycles every timeslot
+ * 10: 32 clk cycles every timeslot
+ */
+#define TIMING_SYNC_WIDTH_MASK GENMASK(6, 5)
+#define TIMING_WIDTH_SHIFT 5
+#define TIMING_DEFAULT_WIDTH0
+#define TIMING_TS_WIDTH(x) ((x) << TIMING_WIDTH_SHIFT)
+#define TIMING_WIDTH_FACTOR 8
+
+#define TIMING_MASTER_MODE BIT(21)
+#define TIMING_LSB_FIRST BIT(20)
+#define TIMING_TS_NUM(x) (((x) - 1) << 7)
+#define TIMING_CLK_SEL_MASKGENMASK(2, 0)
+#define TIMING_CLK_SEL_DEF BIT(2)
+
+#define PROCESS_TX_EN BIT(0)
+#define PROCESS_RX_EN BIT(1)
+#define PROCESS_TDM_EN BIT(2)
+#define PROCESS_DISABLE_ALL0
+
+#define INT_DISABLE_ALL0
+#define INT_STATUS_MASKGENMASK(6, 0)
+
+struct zx_tdm_info {
+ struct snd_dmaengine_dai_dma_data dma_playback;
+ struct snd_dmaengine_dai_dma_data dma_capture;
+ resource_size_t phy_addr;
+ void __iomem*regbase;
+ struct clk *dai_wclk;
+ struct clk *dai_pclk;
+ int master;
+ struct device *dev;
+};
+
+static inline u32 zx_tdm_readl(struct zx_tdm_info *tdm, u16 reg)
+{
+ return readl_relaxed(tdm->regbase + reg);
+}
+
+static inline void zx_tdm_writel(struct zx_tdm_info *tdm, u16 reg, u32 val)
+{
+ writel_relaxed(val, tdm->regbase + reg);
+}
+
+static void zx_tdm_tx_en(struct zx_tdm_info *tdm, bool on)
+{
+ unsigned long val;
+
+ val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
+ if (on)
+ val |= PROCESS_TX_EN | PROCESS_TDM_EN;
+ else
+ val &= ~(PROCESS_TX_EN | PROCESS_TDM_EN);
+ zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
+}
+
+static void zx_tdm_rx_en(struct zx_tdm_info *tdm, bool on)
+{
+ unsigned long val;
+
+ val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
+ if (on)
+ val |= PROCESS_RX_EN | PROCESS_TDM_EN;
+ else
+ val &= ~(PROCESS_RX_EN | PROCESS_TDM_EN);
+ zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
+}
+
+static void zx_tdm_tx_dma_en(struct zx_tdm_info *tdm, bool on)
+{
+ unsigned long val;
+
+ val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);
+ val |= FIFO_CTRL_TX_RST | DEAGULT_FIFO_THRES;
+ if (on)
+ val |= FIFO_CTRL_TX_DMA_EN;
+ else
+
[PATCH v2 2/3] MAINTAINERS: add zte tdm controller driver to ARM ZTE architecture
Add the zte tdm controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..1269eb6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1991,7 +1991,9 @@ F:drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/soc/zte/ +F: Documentation/devicetree/bindings/sound/zte,zx-tdm.txt F: include/dt-bindings/soc/zx*.h +F: sound/soc/zte/zx-tdm.c ARM/ZYNQ ARCHITECTURE M: Michal Simek -- 2.7.4
[PATCH v2 1/3] ASoC: zx-tdm: add bindings doc for zte's tdm controller
This patch adds dt-binding documentation for zte's tdm controller.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
.../devicetree/bindings/sound/zte,tdm.txt | 30 ++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/zte,tdm.txt
diff --git a/Documentation/devicetree/bindings/sound/zte,tdm.txt
b/Documentation/devicetree/bindings/sound/zte,tdm.txt
new file mode 100644
index 000..8ffc39e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/zte,tdm.txt
@@ -0,0 +1,30 @@
+ZTE TDM DAI driver
+
+Required properties:
+
+- compatible : should be one of the following.
+ * zte,zx296718-tdm
+- reg : physical base address of the controller and length of memory mapped
+region.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- clock-names: "wclk" for the wclk.
+ "pclk" for the pclk.
+-#clock-cells: should be 1.
+- zte,tdm-dma-sysctrl : Reference to the sysctrl controller controlling
+the dma. includes:
+ phandle of sysctrl.
+ register offset in sysctrl for control dma.
+ mask of the register that be written to sysctrl.
+
+Example:
+
+ tdm: tdm@1487000 {
+ compatible = "zte,zx296718-tdm";
+ reg = <0x01487000 0x1000>;
+ clocks = < AUDIO_TDM_WCLK>, < AUDIO_TDM_PCLK>;
+ clock-names = "wclk", "pclk";
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ zte,tdm-dma-sysctrl = < 0x10c 4>;
+ };
--
2.7.4
[PATCH v2 1/3] ASoC: zx-tdm: add bindings doc for zte's tdm controller
This patch adds dt-binding documentation for zte's tdm controller.
Signed-off-by: Baoyou Xie
---
.../devicetree/bindings/sound/zte,tdm.txt | 30 ++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/zte,tdm.txt
diff --git a/Documentation/devicetree/bindings/sound/zte,tdm.txt
b/Documentation/devicetree/bindings/sound/zte,tdm.txt
new file mode 100644
index 000..8ffc39e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/zte,tdm.txt
@@ -0,0 +1,30 @@
+ZTE TDM DAI driver
+
+Required properties:
+
+- compatible : should be one of the following.
+ * zte,zx296718-tdm
+- reg : physical base address of the controller and length of memory mapped
+region.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- clock-names: "wclk" for the wclk.
+ "pclk" for the pclk.
+-#clock-cells: should be 1.
+- zte,tdm-dma-sysctrl : Reference to the sysctrl controller controlling
+the dma. includes:
+ phandle of sysctrl.
+ register offset in sysctrl for control dma.
+ mask of the register that be written to sysctrl.
+
+Example:
+
+ tdm: tdm@1487000 {
+ compatible = "zte,zx296718-tdm";
+ reg = <0x01487000 0x1000>;
+ clocks = < AUDIO_TDM_WCLK>, < AUDIO_TDM_PCLK>;
+ clock-names = "wclk", "pclk";
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ zte,tdm-dma-sysctrl = < 0x10c 4>;
+ };
--
2.7.4
[PATCH v7 3/3] i2c: zx2967: add i2c controller driver for ZTE's zx2967 family
This patch adds i2c controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Reviewed-by: Shawn Guo <shawn...@kernel.org>
Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com>
---
drivers/i2c/busses/Kconfig | 9 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-zx2967.c | 667
3 files changed, 677 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-zx2967.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e4a603e..d983e36 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1246,4 +1246,13 @@ config I2C_OPAL
This driver can also be built as a module. If so, the module will be
called as i2c-opal.
+config I2C_ZX2967
+ tristate "ZTE zx2967 I2C support"
+ depends on ARCH_ZX
+ default y
+ help
+ Selecting this option will add ZX2967 I2C driver.
+ This driver can also be built as a module. If so, the module will be
+ called i2c-zx2967.
+
endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index beb4809..16b2901 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_XILINX)+= i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
+obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
diff --git a/drivers/i2c/busses/i2c-zx2967.c b/drivers/i2c/busses/i2c-zx2967.c
new file mode 100644
index 000..f136aee
--- /dev/null
+++ b/drivers/i2c/busses/i2c-zx2967.c
@@ -0,0 +1,667 @@
+/*
+ * ZTE's zx2967 family i2c bus controller driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie <baoyou@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_CMD0x04
+#define REG_DEVADDR_H 0x0C
+#define REG_DEVADDR_L 0x10
+#define REG_CLK_DIV_FS 0x14
+#define REG_CLK_DIV_HS 0x18
+#define REG_WRCONF 0x1C
+#define REG_RDCONF 0x20
+#define REG_DATA 0x24
+#define REG_STAT 0x28
+
+#define I2C_STOP 0
+#define I2C_MASTER BIT(0)
+#define I2C_ADDR_MODE_TEN BIT(1)
+#define I2C_IRQ_MSK_ENABLE BIT(3)
+#define I2C_RW_READBIT(4)
+#define I2C_CMB_RW_EN BIT(5)
+#define I2C_START BIT(6)
+
+#define I2C_ADDR_LOW_MASK GENMASK(6, 0)
+#define I2C_ADDR_LOW_SHIFT 0
+#define I2C_ADDR_HI_MASK GENMASK(2, 0)
+#define I2C_ADDR_HI_SHIFT 7
+
+#define I2C_WFIFO_RESETBIT(7)
+#define I2C_RFIFO_RESETBIT(7)
+
+#define I2C_IRQ_ACK_CLEAR BIT(7)
+#define I2C_INT_MASK GENMASK(6, 0)
+
+#define I2C_TRANS_DONE BIT(0)
+#define I2C_ERROR_DEVICE BIT(1)
+#define I2C_ERROR_DATA BIT(2)
+#define I2C_ERROR_MASK GENMASK(2, 1)
+
+#define I2C_SR_BUSYBIT(6)
+
+#define I2C_SR_EDEVICE BIT(1)
+#define I2C_SR_EDATA BIT(2)
+
+#define I2C_FIFO_MAX 16
+
+#define I2C_TIMEOUTmsecs_to_jiffies(1000)
+
+#define DEV(i2c) (>adap.dev)
+
+struct zx2967_i2c_info {
+ struct i2c_adapter adap;
+ struct clk *clk;
+ struct completion complete;
+ u32 clk_freq;
+ void __iomem*reg_base;
+ size_t residue;
+ int irq;
+ int msg_rd;
+ u8 *cur_trans;
+ u8 access_cnt;
+ boolis_suspended;
+};
+
+static void zx2967_i2c_writel(struct zx2967_i2c_info *zx_i2c,
+ u32 val, unsigned long reg)
+{
+ writel_relaxed(val, zx_i2c->reg_base + reg);
+}
+
+static u32 zx2967_i2c_readl(struct zx2967_i2c_info *zx_i2c, unsigned long reg)
+{
+ return readl_relaxed(zx_i2c->reg_base + reg);
+}
+
+static void zx2967_i2c_writesb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ writesb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_readsb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ readsb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2
[PATCH v7 3/3] i2c: zx2967: add i2c controller driver for ZTE's zx2967 family
This patch adds i2c controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie
Reviewed-by: Shawn Guo
Reviewed-by: Andy Shevchenko
---
drivers/i2c/busses/Kconfig | 9 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-zx2967.c | 667
3 files changed, 677 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-zx2967.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e4a603e..d983e36 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1246,4 +1246,13 @@ config I2C_OPAL
This driver can also be built as a module. If so, the module will be
called as i2c-opal.
+config I2C_ZX2967
+ tristate "ZTE zx2967 I2C support"
+ depends on ARCH_ZX
+ default y
+ help
+ Selecting this option will add ZX2967 I2C driver.
+ This driver can also be built as a module. If so, the module will be
+ called i2c-zx2967.
+
endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index beb4809..16b2901 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_XILINX)+= i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
+obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
diff --git a/drivers/i2c/busses/i2c-zx2967.c b/drivers/i2c/busses/i2c-zx2967.c
new file mode 100644
index 000..f136aee
--- /dev/null
+++ b/drivers/i2c/busses/i2c-zx2967.c
@@ -0,0 +1,667 @@
+/*
+ * ZTE's zx2967 family i2c bus controller driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_CMD0x04
+#define REG_DEVADDR_H 0x0C
+#define REG_DEVADDR_L 0x10
+#define REG_CLK_DIV_FS 0x14
+#define REG_CLK_DIV_HS 0x18
+#define REG_WRCONF 0x1C
+#define REG_RDCONF 0x20
+#define REG_DATA 0x24
+#define REG_STAT 0x28
+
+#define I2C_STOP 0
+#define I2C_MASTER BIT(0)
+#define I2C_ADDR_MODE_TEN BIT(1)
+#define I2C_IRQ_MSK_ENABLE BIT(3)
+#define I2C_RW_READBIT(4)
+#define I2C_CMB_RW_EN BIT(5)
+#define I2C_START BIT(6)
+
+#define I2C_ADDR_LOW_MASK GENMASK(6, 0)
+#define I2C_ADDR_LOW_SHIFT 0
+#define I2C_ADDR_HI_MASK GENMASK(2, 0)
+#define I2C_ADDR_HI_SHIFT 7
+
+#define I2C_WFIFO_RESETBIT(7)
+#define I2C_RFIFO_RESETBIT(7)
+
+#define I2C_IRQ_ACK_CLEAR BIT(7)
+#define I2C_INT_MASK GENMASK(6, 0)
+
+#define I2C_TRANS_DONE BIT(0)
+#define I2C_ERROR_DEVICE BIT(1)
+#define I2C_ERROR_DATA BIT(2)
+#define I2C_ERROR_MASK GENMASK(2, 1)
+
+#define I2C_SR_BUSYBIT(6)
+
+#define I2C_SR_EDEVICE BIT(1)
+#define I2C_SR_EDATA BIT(2)
+
+#define I2C_FIFO_MAX 16
+
+#define I2C_TIMEOUTmsecs_to_jiffies(1000)
+
+#define DEV(i2c) (>adap.dev)
+
+struct zx2967_i2c_info {
+ struct i2c_adapter adap;
+ struct clk *clk;
+ struct completion complete;
+ u32 clk_freq;
+ void __iomem*reg_base;
+ size_t residue;
+ int irq;
+ int msg_rd;
+ u8 *cur_trans;
+ u8 access_cnt;
+ boolis_suspended;
+};
+
+static void zx2967_i2c_writel(struct zx2967_i2c_info *zx_i2c,
+ u32 val, unsigned long reg)
+{
+ writel_relaxed(val, zx_i2c->reg_base + reg);
+}
+
+static u32 zx2967_i2c_readl(struct zx2967_i2c_info *zx_i2c, unsigned long reg)
+{
+ return readl_relaxed(zx_i2c->reg_base + reg);
+}
+
+static void zx2967_i2c_writesb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ writesb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_readsb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ readsb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_start_ctrl(struct zx2967_i2c_info *zx_i2c)
+{
+ u32 status;
+ u32 ctl;
+
+ status = zx2967_i
[PATCH v7 2/3] MAINTAINERS: add zx2967 i2c controller driver to ARM ZTE architecture
Add the zx2967 i2c controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..313fab5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1987,9 +1987,11 @@ L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-zx/ F: drivers/clk/zte/ +F: drivers/i2c/busses/i2c-zx2967.c F: drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt +F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt F: Documentation/devicetree/bindings/soc/zte/ F: include/dt-bindings/soc/zx*.h -- 2.7.4
[PATCH v7 2/3] MAINTAINERS: add zx2967 i2c controller driver to ARM ZTE architecture
Add the zx2967 i2c controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..313fab5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1987,9 +1987,11 @@ L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-zx/ F: drivers/clk/zte/ +F: drivers/i2c/busses/i2c-zx2967.c F: drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt +F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt F: Documentation/devicetree/bindings/soc/zte/ F: include/dt-bindings/soc/zx*.h -- 2.7.4
[PATCH v7 1/3] dt: bindings: add documentation for zx2967 family i2c controller
This patch adds dt-binding documentation for zx2967 family
i2c controller.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Acked-by: Rob Herring <r...@kernel.org>
---
.../devicetree/bindings/i2c/i2c-zx2967.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
new file mode 100644
index 000..a528374
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
@@ -0,0 +1,24 @@
+ZTE zx2967 I2C controller
+
+Required properties:
+ - compatible: must be "zte,zx296718-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+ - clock-frequency: the desired I2C bus clock frequency.
+
+Examples:
+
+ i2c@112000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x00112000 0x1000>;
+ interrupts = ;
+ clocks = <>;
+ #address-cells = <1>
+ #size-cells = <0>;
+ clock-frequency = <160>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ };
--
2.7.4
[PATCH v7 1/3] dt: bindings: add documentation for zx2967 family i2c controller
This patch adds dt-binding documentation for zx2967 family
i2c controller.
Signed-off-by: Baoyou Xie
Acked-by: Rob Herring
---
.../devicetree/bindings/i2c/i2c-zx2967.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
new file mode 100644
index 000..a528374
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
@@ -0,0 +1,24 @@
+ZTE zx2967 I2C controller
+
+Required properties:
+ - compatible: must be "zte,zx296718-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+ - clock-frequency: the desired I2C bus clock frequency.
+
+Examples:
+
+ i2c@112000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x00112000 0x1000>;
+ interrupts = ;
+ clocks = <>;
+ #address-cells = <1>
+ #size-cells = <0>;
+ clock-frequency = <160>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ };
--
2.7.4
[PATCH v1 3/3] ASoC: zx-96p22: add zte's aud96p22 controller driver
This patch adds aud96p22 controller driver for zte's SoC family.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
sound/soc/codecs/Kconfig | 4 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/zx_aud96p22.c | 588 +
3 files changed, 594 insertions(+)
create mode 100644 sound/soc/codecs/zx_aud96p22.c
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index cfc108e..120af32 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -1116,4 +1116,8 @@ config SND_SOC_TPA6130A2
tristate "Texas Instruments TPA6130A2 headphone amplifier"
depends on I2C
+config SND_SOC_ZX96P22
+ tristate "ZTE Inner AUD96P22 CODEC"
+ depends on I2C
+
endmenu
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 2624c73..dbc3818 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -219,6 +219,7 @@ snd-soc-wm9705-objs := wm9705.o
snd-soc-wm9712-objs := wm9712.o
snd-soc-wm9713-objs := wm9713.o
snd-soc-wm-hubs-objs := wm_hubs.o
+snd-soc-zx96p22-objs := zx_aud96p22.o
# Amp
snd-soc-max9877-objs := max9877.o
snd-soc-max98504-objs := max98504.o
@@ -444,6 +445,7 @@ obj-$(CONFIG_SND_SOC_WM9712)+= snd-soc-wm9712.o
obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o
obj-$(CONFIG_SND_SOC_WM_ADSP) += snd-soc-wm-adsp.o
obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o
+obj-$(CONFIG_SND_SOC_ZX96P22) += snd-soc-zx96p22.o
# Amp
obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o
diff --git a/sound/soc/codecs/zx_aud96p22.c b/sound/soc/codecs/zx_aud96p22.c
new file mode 100644
index 000..f2979df
--- /dev/null
+++ b/sound/soc/codecs/zx_aud96p22.c
@@ -0,0 +1,588 @@
+/*
+ * ZTE's audio 96p22 driver
+ *
+ * Copyright (C) 2017 ZTE Ltd
+ *
+ * Author: Baoyou Xie <baoyou@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define BGPIO64(64)
+#define snd_kcontrol_dev(kcontrol) \
+ ((struct device *)((kcontrol)->private_value))
+
+struct i2c_reg {
+ unsigned char addr;
+ unsigned char high_data;
+ unsigned char low_data;
+};
+
+struct zx_aud96p22_info {
+ struct device *dev;
+ int gpio;
+ bool capture;
+};
+
+static struct i2c_reg i2c_dac_master_volume_table[] = {
+ { 0x34, 0xe7, 0xe7 },
+};
+
+static struct i2c_reg i2c_adc_master_volume_table[] = {
+ { 0x24, 0xbf, 0xbf },
+};
+
+static struct i2c_reg i2c_dac_headset_volume_table[] = {
+ { 0x38, 0x0d, 0x0d },
+};
+
+static struct i2c_reg i2c_dac_sleep_table[] = {
+ { 0x18, 0x00, 0x00 }, //play power down
+};
+
+static struct i2c_reg i2c_dac_wakeup_table[] = {
+ { 0x18, 0x00, 0xff }, //play power up
+};
+
+static struct i2c_reg i2c_adc_sleep_table[] = {
+ { 0x16, 0x00, 0x00 }, //record power down
+};
+
+static struct i2c_reg i2c_adc_wakeup_table[] = {
+ { 0x16, 0x00, 0x0f }, //record power up
+};
+
+static struct i2c_reg i2c_codec_start_table[] = {
+ { 0x15, 0x00, 0x00 }, //power down control
+ { 0x47, 0x00, 0x00 }, //record path slect
+ { 0x24, 0xbf, 0xbf }, //record volume control
+ { 0x26, 0x30, 0x30 }, //record pga volume control
+ { 0xc8, 0x00, 0x00 }, //ALC control
+ { 0xce, 0x00, 0xf5 }, //record noise gate
+ { 0xf3, 0x00, 0xc0 }, //dac noise dithe
+ { 0xcd, 0x00, 0x20 }, //max record volume
+ { 0x15, 0x00, 0x01 }, //power down control
+ { 0x18, 0x00, 0xff }, //play power control
+ { 0x16, 0x00, 0x0f }, //record power up
+ { 0x19, 0x00, 0x04 }, //power down control
+ { 0x02, 0x00, 0x05 }, //ext clock slect
+ { 0x01, 0x00, 0x05 }, //ext clock slect
+ { 0x00, 0x00, 0x00 }, //adc dpz reset
+ { 0x00, 0x00, 0x03 }, //dac dpz reset
+ { 0x04, 0x00, 0x40 }, //clk div
+ { 0x05, 0x00, 0x04 }, //clk div0x4
+ { 0x06, 0x00, 0x40 }, //clk div
+ { 0x07, 0x00, 0x04 }, //clk div 0x4
+ { 0x03, 0x00, 0x01 }, //slave 16bit i2s
+ { 0x00, 0x00, 0x00 }, //adc dpz reset
+ { 0x00, 0x00, 0x03 }, //dac dpz reset
+};
+
+static int zx_aud96p22_i2c_write(struct i2c_client *i2c_client,
+const void *data, size_t count)
+{
+ int xfer;
+
+ xfer = i2c_master_send(i2c_client, data, count);
+ if (xfer == count)
+ return 0;
+ else if (xfer < 0)
+ return xfer;
+ else
+ return -EIO;
+}
+
+static int zx_aud96p22_i2c_read(struct i2c_client *i2c_client,
+ unsigned char addr)
+{
+ int xfer;
+
+ xfer = i2c_smbus_read_word_data(i2c_client, addr);
+ if (xfer < 0)
+ dev_warn(_client->dev, "transfer error %d\n", xfer);
+
+ return xfer;
+}
+
+static in
[PATCH v1 3/3] ASoC: zx-96p22: add zte's aud96p22 controller driver
This patch adds aud96p22 controller driver for zte's SoC family.
Signed-off-by: Baoyou Xie
---
sound/soc/codecs/Kconfig | 4 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/zx_aud96p22.c | 588 +
3 files changed, 594 insertions(+)
create mode 100644 sound/soc/codecs/zx_aud96p22.c
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index cfc108e..120af32 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -1116,4 +1116,8 @@ config SND_SOC_TPA6130A2
tristate "Texas Instruments TPA6130A2 headphone amplifier"
depends on I2C
+config SND_SOC_ZX96P22
+ tristate "ZTE Inner AUD96P22 CODEC"
+ depends on I2C
+
endmenu
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 2624c73..dbc3818 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -219,6 +219,7 @@ snd-soc-wm9705-objs := wm9705.o
snd-soc-wm9712-objs := wm9712.o
snd-soc-wm9713-objs := wm9713.o
snd-soc-wm-hubs-objs := wm_hubs.o
+snd-soc-zx96p22-objs := zx_aud96p22.o
# Amp
snd-soc-max9877-objs := max9877.o
snd-soc-max98504-objs := max98504.o
@@ -444,6 +445,7 @@ obj-$(CONFIG_SND_SOC_WM9712)+= snd-soc-wm9712.o
obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o
obj-$(CONFIG_SND_SOC_WM_ADSP) += snd-soc-wm-adsp.o
obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o
+obj-$(CONFIG_SND_SOC_ZX96P22) += snd-soc-zx96p22.o
# Amp
obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o
diff --git a/sound/soc/codecs/zx_aud96p22.c b/sound/soc/codecs/zx_aud96p22.c
new file mode 100644
index 000..f2979df
--- /dev/null
+++ b/sound/soc/codecs/zx_aud96p22.c
@@ -0,0 +1,588 @@
+/*
+ * ZTE's audio 96p22 driver
+ *
+ * Copyright (C) 2017 ZTE Ltd
+ *
+ * Author: Baoyou Xie
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define BGPIO64(64)
+#define snd_kcontrol_dev(kcontrol) \
+ ((struct device *)((kcontrol)->private_value))
+
+struct i2c_reg {
+ unsigned char addr;
+ unsigned char high_data;
+ unsigned char low_data;
+};
+
+struct zx_aud96p22_info {
+ struct device *dev;
+ int gpio;
+ bool capture;
+};
+
+static struct i2c_reg i2c_dac_master_volume_table[] = {
+ { 0x34, 0xe7, 0xe7 },
+};
+
+static struct i2c_reg i2c_adc_master_volume_table[] = {
+ { 0x24, 0xbf, 0xbf },
+};
+
+static struct i2c_reg i2c_dac_headset_volume_table[] = {
+ { 0x38, 0x0d, 0x0d },
+};
+
+static struct i2c_reg i2c_dac_sleep_table[] = {
+ { 0x18, 0x00, 0x00 }, //play power down
+};
+
+static struct i2c_reg i2c_dac_wakeup_table[] = {
+ { 0x18, 0x00, 0xff }, //play power up
+};
+
+static struct i2c_reg i2c_adc_sleep_table[] = {
+ { 0x16, 0x00, 0x00 }, //record power down
+};
+
+static struct i2c_reg i2c_adc_wakeup_table[] = {
+ { 0x16, 0x00, 0x0f }, //record power up
+};
+
+static struct i2c_reg i2c_codec_start_table[] = {
+ { 0x15, 0x00, 0x00 }, //power down control
+ { 0x47, 0x00, 0x00 }, //record path slect
+ { 0x24, 0xbf, 0xbf }, //record volume control
+ { 0x26, 0x30, 0x30 }, //record pga volume control
+ { 0xc8, 0x00, 0x00 }, //ALC control
+ { 0xce, 0x00, 0xf5 }, //record noise gate
+ { 0xf3, 0x00, 0xc0 }, //dac noise dithe
+ { 0xcd, 0x00, 0x20 }, //max record volume
+ { 0x15, 0x00, 0x01 }, //power down control
+ { 0x18, 0x00, 0xff }, //play power control
+ { 0x16, 0x00, 0x0f }, //record power up
+ { 0x19, 0x00, 0x04 }, //power down control
+ { 0x02, 0x00, 0x05 }, //ext clock slect
+ { 0x01, 0x00, 0x05 }, //ext clock slect
+ { 0x00, 0x00, 0x00 }, //adc dpz reset
+ { 0x00, 0x00, 0x03 }, //dac dpz reset
+ { 0x04, 0x00, 0x40 }, //clk div
+ { 0x05, 0x00, 0x04 }, //clk div0x4
+ { 0x06, 0x00, 0x40 }, //clk div
+ { 0x07, 0x00, 0x04 }, //clk div 0x4
+ { 0x03, 0x00, 0x01 }, //slave 16bit i2s
+ { 0x00, 0x00, 0x00 }, //adc dpz reset
+ { 0x00, 0x00, 0x03 }, //dac dpz reset
+};
+
+static int zx_aud96p22_i2c_write(struct i2c_client *i2c_client,
+const void *data, size_t count)
+{
+ int xfer;
+
+ xfer = i2c_master_send(i2c_client, data, count);
+ if (xfer == count)
+ return 0;
+ else if (xfer < 0)
+ return xfer;
+ else
+ return -EIO;
+}
+
+static int zx_aud96p22_i2c_read(struct i2c_client *i2c_client,
+ unsigned char addr)
+{
+ int xfer;
+
+ xfer = i2c_smbus_read_word_data(i2c_client, addr);
+ if (xfer < 0)
+ dev_warn(_client->dev, "transfer error %d\n", xfer);
+
+ return xfer;
+}
+
+static int zx_aud96p22_i2c_update(struct i2c_client *i2c_client,
+
[PATCH v1 2/3] MAINTAINERS: add zte 96p22 controller driver to ARM ZTE architecture
Add the zte 96p22 controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..8146377 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1991,7 +1991,9 @@ F:drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/soc/zte/ +F: Documentation/devicetree/bindings/sound/zte,zx-96p22.txt F: include/dt-bindings/soc/zx*.h +F: sound/soc/codecs/zx_aud96p22.c ARM/ZYNQ ARCHITECTURE M: Michal Simek <michal.si...@xilinx.com> -- 2.7.4
[PATCH v1 2/3] MAINTAINERS: add zte 96p22 controller driver to ARM ZTE architecture
Add the zte 96p22 controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..8146377 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1991,7 +1991,9 @@ F:drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/soc/zte/ +F: Documentation/devicetree/bindings/sound/zte,zx-96p22.txt F: include/dt-bindings/soc/zx*.h +F: sound/soc/codecs/zx_aud96p22.c ARM/ZYNQ ARCHITECTURE M: Michal Simek -- 2.7.4
[PATCH v1 1/3] ASoC: zx-96p22: add documentation for zte's aud96p22 controller
This patch adds dt-binding documentation for zte's aud96p22 controller.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
.../devicetree/bindings/sound/zte,zx-96p22.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/zte,zx-96p22.txt
diff --git a/Documentation/devicetree/bindings/sound/zte,zx-96p22.txt
b/Documentation/devicetree/bindings/sound/zte,zx-96p22.txt
new file mode 100644
index 000..4184566
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/zte,zx-96p22.txt
@@ -0,0 +1,24 @@
+ZTE zx96p22 controller
+
+Required properties:
+ - compatible : Must be "zte,zx-aud96p22"
+ - #sound-dai-cells: Should be 0
+ - reg : Offset of I2C register for zx96p22
+
+Example:
+
+ audio_i2c0: audio_i2c0@1486000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x01486000 0x1000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < AUDIO_I2C0_WCLK>;
+ clock-frequency = <160>;
+ status = "ok";
+ inner_codec: aud96p22@22 {
+ compatible = "zte,zx-aud96p22";
+ #sound-dai-cells = <0>;
+ reg = <0x22>;
+ };
+ };
--
2.7.4
[PATCH v1 1/3] ASoC: zx-96p22: add documentation for zte's aud96p22 controller
This patch adds dt-binding documentation for zte's aud96p22 controller.
Signed-off-by: Baoyou Xie
---
.../devicetree/bindings/sound/zte,zx-96p22.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/zte,zx-96p22.txt
diff --git a/Documentation/devicetree/bindings/sound/zte,zx-96p22.txt
b/Documentation/devicetree/bindings/sound/zte,zx-96p22.txt
new file mode 100644
index 000..4184566
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/zte,zx-96p22.txt
@@ -0,0 +1,24 @@
+ZTE zx96p22 controller
+
+Required properties:
+ - compatible : Must be "zte,zx-aud96p22"
+ - #sound-dai-cells: Should be 0
+ - reg : Offset of I2C register for zx96p22
+
+Example:
+
+ audio_i2c0: audio_i2c0@1486000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x01486000 0x1000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = < AUDIO_I2C0_WCLK>;
+ clock-frequency = <160>;
+ status = "ok";
+ inner_codec: aud96p22@22 {
+ compatible = "zte,zx-aud96p22";
+ #sound-dai-cells = <0>;
+ reg = <0x22>;
+ };
+ };
--
2.7.4
[PATCH v1 2/3] MAINTAINERS: add zte tdm controller driver to ARM ZTE architecture
Add the zte tdm controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..1269eb6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1991,7 +1991,9 @@ F:drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/soc/zte/ +F: Documentation/devicetree/bindings/sound/zte,zx-tdm.txt F: include/dt-bindings/soc/zx*.h +F: sound/soc/zte/zx-tdm.c ARM/ZYNQ ARCHITECTURE M: Michal Simek <michal.si...@xilinx.com> -- 2.7.4
[PATCH v1 3/3] ASoC: zx-tdm: add zte's tdm controller driver
This patch adds tdm controller driver for zte's SoC family.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
sound/soc/zte/Kconfig | 8 +
sound/soc/zte/Makefile | 1 +
sound/soc/zte/zx-tdm.c | 466 +
3 files changed, 475 insertions(+)
create mode 100644 sound/soc/zte/zx-tdm.c
diff --git a/sound/soc/zte/Kconfig b/sound/soc/zte/Kconfig
index 6d8a90d..75f67a5 100644
--- a/sound/soc/zte/Kconfig
+++ b/sound/soc/zte/Kconfig
@@ -15,3 +15,11 @@ config ZX_I2S
help
Say Y or M if you want to add support for codecs attached to the
ZTE ZX I2S interface
+
+config ZX_TDM
+tristate "ZTE ZX TDM Driver Support"
+depends on COMMON_CLK
+select SND_SOC_GENERIC_DMAENGINE_PCM
+help
+ Say Y or M if you want to add support for codecs attached to the
+ ZTE ZX TDM interface
diff --git a/sound/soc/zte/Makefile b/sound/soc/zte/Makefile
index 77768f5..1fc841a 100644
--- a/sound/soc/zte/Makefile
+++ b/sound/soc/zte/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_ZX_SPDIF) += zx-spdif.o
obj-$(CONFIG_ZX_I2S) += zx-i2s.o
+obj-$(CONFIG_ZX_TDM) += zx-tdm.o
diff --git a/sound/soc/zte/zx-tdm.c b/sound/soc/zte/zx-tdm.c
new file mode 100644
index 000..72e5136
--- /dev/null
+++ b/sound/soc/zte/zx-tdm.c
@@ -0,0 +1,466 @@
+/*
+ * ZTE's TDM driver
+ *
+ * Copyright (C) 2017 ZTE Ltd
+ *
+ * Author: Baoyou Xie <baoyou@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_TIMING_CTRL0x04
+#defineREG_TX_FIFO_CTRL0x0C
+#defineREG_RX_FIFO_CTRL0x10
+#define REG_INT_EN 0x1C
+#define REG_INT_STATUS 0x20
+#define REG_DATABUF0x24
+#define REG_TS_MASK0 0x44
+#define REG_PROCESS_CTRL 0x54
+
+#define FIFO_CTRL_TX_RST BIT(0)
+#define FIFO_CTRL_RX_RST BIT(0)
+#define DEAGULT_FIFO_THRES GENMASK(4, 2)
+
+#define FIFO_CTRL_TX_DMA_ENBIT(1)
+#define FIFO_CTRL_RX_DMA_ENBIT(1)
+
+#define TX_FIFO_RST_MASK BIT(0)
+#define RX_FIFO_RST_MASK BIT(0)
+
+#define FIFOCTRL_TX_FIFO_RST BIT(0)
+#define FIFOCTRL_RX_FIFO_RST BIT(0)
+
+#define TXTH_MASK GENMASK(5, 2)
+#define RXTH_MASK GENMASK(5, 2)
+
+#define FIFOCTRL_THRESHOLD(x) (x << 2)
+
+#define TIMING_MS_MASK BIT(1)
+/*
+ * 00: 8 clk cycles every timeslot
+ * 01: 16 clk cycles every timeslot
+ * 10: 32 clk cycles every timeslot
+ */
+#define TIMING_SYNC_WIDTH_MASK GENMASK(6, 5)
+#define TIMING_WIDTH_SHIFT 5
+#define TIMING_DEFAULT_WIDTH0
+#define TIMING_TS_WIDTH(x) ((x) << TIMING_WIDTH_SHIFT)
+#define TIMING_WIDTH_FACTOR 8
+
+#define TIMING_MASTER_MODE BIT(21)
+#define TIMING_LSB_FIRST BIT(20)
+#define TIMING_TS_NUM(x) ((x - 1) << 7)
+#define TIMING_CLK_SEL_MASKGENMASK(2, 0)
+#define TIMING_CLK_SEL_DEF BIT(2)
+
+#define PROCESS_TX_EN BIT(0)
+#define PROCESS_RX_EN BIT(1)
+#define PROCESS_TDM_EN BIT(2)
+#define PROCESS_DISABLE_ALL0
+
+#define INT_DISABLE_ALL0
+#define INT_STATUS_MASKGENMASK(6, 0)
+
+struct zx_tdm_info {
+ struct snd_dmaengine_dai_dma_data dma_playback;
+ struct snd_dmaengine_dai_dma_data dma_capture;
+ resource_size_t phy_addr;
+ void __iomem*regmap;
+ struct clk *dai_wclk;
+ struct clk *dai_pclk;
+ int master;
+ struct device *dev;
+};
+
+static inline u32 zx_tdm_readl(struct zx_tdm_info *tdm, u16 reg)
+{
+ return readl_relaxed(tdm->regmap + reg);
+}
+
+static inline void zx_tdm_writel(struct zx_tdm_info *tdm, u16 reg, u32 val)
+{
+ writel_relaxed(val, tdm->regmap + reg);
+}
+
+static void zx_tdm_tx_en(struct zx_tdm_info *tdm, bool on)
+{
+ unsigned long val;
+
+ val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
+ if (on)
+ val |= PROCESS_TX_EN | PROCESS_TDM_EN;
+ else
+ val &= ~(PROCESS_TX_EN | PROCESS_TDM_EN);
+ zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
+}
+
+static void zx_tdm_rx_en(struct zx_tdm_info *tdm, bool on)
+{
+ unsigned long val;
+
+ val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
+ if (on)
+ val |= PROCESS_RX_EN | PROCESS_TDM_EN;
+ else
+ val &= ~(PROCESS_RX_EN | PROCESS_TDM_EN);
+ zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
+}
+
+static void zx_tdm_tx_dma_en(struct zx_tdm_info *tdm, bool on)
+{
+ unsigned long val;
+
+ val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);
+ val |= FIFO_CTRL_TX_RST | DEAGULT_FIFO_THRES;
+ if (on)
+
[PATCH v1 3/3] ASoC: zx-tdm: add zte's tdm controller driver
This patch adds tdm controller driver for zte's SoC family.
Signed-off-by: Baoyou Xie
---
sound/soc/zte/Kconfig | 8 +
sound/soc/zte/Makefile | 1 +
sound/soc/zte/zx-tdm.c | 466 +
3 files changed, 475 insertions(+)
create mode 100644 sound/soc/zte/zx-tdm.c
diff --git a/sound/soc/zte/Kconfig b/sound/soc/zte/Kconfig
index 6d8a90d..75f67a5 100644
--- a/sound/soc/zte/Kconfig
+++ b/sound/soc/zte/Kconfig
@@ -15,3 +15,11 @@ config ZX_I2S
help
Say Y or M if you want to add support for codecs attached to the
ZTE ZX I2S interface
+
+config ZX_TDM
+tristate "ZTE ZX TDM Driver Support"
+depends on COMMON_CLK
+select SND_SOC_GENERIC_DMAENGINE_PCM
+help
+ Say Y or M if you want to add support for codecs attached to the
+ ZTE ZX TDM interface
diff --git a/sound/soc/zte/Makefile b/sound/soc/zte/Makefile
index 77768f5..1fc841a 100644
--- a/sound/soc/zte/Makefile
+++ b/sound/soc/zte/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_ZX_SPDIF) += zx-spdif.o
obj-$(CONFIG_ZX_I2S) += zx-i2s.o
+obj-$(CONFIG_ZX_TDM) += zx-tdm.o
diff --git a/sound/soc/zte/zx-tdm.c b/sound/soc/zte/zx-tdm.c
new file mode 100644
index 000..72e5136
--- /dev/null
+++ b/sound/soc/zte/zx-tdm.c
@@ -0,0 +1,466 @@
+/*
+ * ZTE's TDM driver
+ *
+ * Copyright (C) 2017 ZTE Ltd
+ *
+ * Author: Baoyou Xie
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_TIMING_CTRL0x04
+#defineREG_TX_FIFO_CTRL0x0C
+#defineREG_RX_FIFO_CTRL0x10
+#define REG_INT_EN 0x1C
+#define REG_INT_STATUS 0x20
+#define REG_DATABUF0x24
+#define REG_TS_MASK0 0x44
+#define REG_PROCESS_CTRL 0x54
+
+#define FIFO_CTRL_TX_RST BIT(0)
+#define FIFO_CTRL_RX_RST BIT(0)
+#define DEAGULT_FIFO_THRES GENMASK(4, 2)
+
+#define FIFO_CTRL_TX_DMA_ENBIT(1)
+#define FIFO_CTRL_RX_DMA_ENBIT(1)
+
+#define TX_FIFO_RST_MASK BIT(0)
+#define RX_FIFO_RST_MASK BIT(0)
+
+#define FIFOCTRL_TX_FIFO_RST BIT(0)
+#define FIFOCTRL_RX_FIFO_RST BIT(0)
+
+#define TXTH_MASK GENMASK(5, 2)
+#define RXTH_MASK GENMASK(5, 2)
+
+#define FIFOCTRL_THRESHOLD(x) (x << 2)
+
+#define TIMING_MS_MASK BIT(1)
+/*
+ * 00: 8 clk cycles every timeslot
+ * 01: 16 clk cycles every timeslot
+ * 10: 32 clk cycles every timeslot
+ */
+#define TIMING_SYNC_WIDTH_MASK GENMASK(6, 5)
+#define TIMING_WIDTH_SHIFT 5
+#define TIMING_DEFAULT_WIDTH0
+#define TIMING_TS_WIDTH(x) ((x) << TIMING_WIDTH_SHIFT)
+#define TIMING_WIDTH_FACTOR 8
+
+#define TIMING_MASTER_MODE BIT(21)
+#define TIMING_LSB_FIRST BIT(20)
+#define TIMING_TS_NUM(x) ((x - 1) << 7)
+#define TIMING_CLK_SEL_MASKGENMASK(2, 0)
+#define TIMING_CLK_SEL_DEF BIT(2)
+
+#define PROCESS_TX_EN BIT(0)
+#define PROCESS_RX_EN BIT(1)
+#define PROCESS_TDM_EN BIT(2)
+#define PROCESS_DISABLE_ALL0
+
+#define INT_DISABLE_ALL0
+#define INT_STATUS_MASKGENMASK(6, 0)
+
+struct zx_tdm_info {
+ struct snd_dmaengine_dai_dma_data dma_playback;
+ struct snd_dmaengine_dai_dma_data dma_capture;
+ resource_size_t phy_addr;
+ void __iomem*regmap;
+ struct clk *dai_wclk;
+ struct clk *dai_pclk;
+ int master;
+ struct device *dev;
+};
+
+static inline u32 zx_tdm_readl(struct zx_tdm_info *tdm, u16 reg)
+{
+ return readl_relaxed(tdm->regmap + reg);
+}
+
+static inline void zx_tdm_writel(struct zx_tdm_info *tdm, u16 reg, u32 val)
+{
+ writel_relaxed(val, tdm->regmap + reg);
+}
+
+static void zx_tdm_tx_en(struct zx_tdm_info *tdm, bool on)
+{
+ unsigned long val;
+
+ val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
+ if (on)
+ val |= PROCESS_TX_EN | PROCESS_TDM_EN;
+ else
+ val &= ~(PROCESS_TX_EN | PROCESS_TDM_EN);
+ zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
+}
+
+static void zx_tdm_rx_en(struct zx_tdm_info *tdm, bool on)
+{
+ unsigned long val;
+
+ val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
+ if (on)
+ val |= PROCESS_RX_EN | PROCESS_TDM_EN;
+ else
+ val &= ~(PROCESS_RX_EN | PROCESS_TDM_EN);
+ zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
+}
+
+static void zx_tdm_tx_dma_en(struct zx_tdm_info *tdm, bool on)
+{
+ unsigned long val;
+
+ val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);
+ val |= FIFO_CTRL_TX_RST | DEAGULT_FIFO_THRES;
+ if (on)
+ val |= FIFO_CTRL_TX_DMA_EN;
+ else
+
[PATCH v1 2/3] MAINTAINERS: add zte tdm controller driver to ARM ZTE architecture
Add the zte tdm controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..1269eb6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1991,7 +1991,9 @@ F:drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/soc/zte/ +F: Documentation/devicetree/bindings/sound/zte,zx-tdm.txt F: include/dt-bindings/soc/zx*.h +F: sound/soc/zte/zx-tdm.c ARM/ZYNQ ARCHITECTURE M: Michal Simek -- 2.7.4
[PATCH v1 1/3] ASoC: zx-tdm: add documentation for zte's tdm controller
This patch adds dt-binding documentation for zte's tdm controller.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
.../devicetree/bindings/sound/zte,tdm.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/zte,tdm.txt
diff --git a/Documentation/devicetree/bindings/sound/zte,tdm.txt
b/Documentation/devicetree/bindings/sound/zte,tdm.txt
new file mode 100644
index 000..f6e4f7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/zte,tdm.txt
@@ -0,0 +1,32 @@
+ZTE TDM DAI driver
+
+Required properties:
+
+- compatible : should be one of the following.
+ * zte,zx-tdm
+- reg : physical base address of the controller and length of memory mapped
+region.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- clock-names: "tdm_wclk" for the wclk.
+ "tdm_pclk" for the pclk.
+-#clock-cells: should be 1.
+- zte,tdm-dma-sysctrl : Reference to the sysctrl controller controlling
+the dma. includes:
+ phandle of sysctrl.
+ register offset in sysctrl for control dma.
+ mask of the register that be written to dma.
+ value of the register that be written to dma.
+
+Example:
+
+ tdm: tdm@1487000 {
+ compatible = "zte,zx-tdm";
+ reg = <0x01487000 0x1000>;
+ clocks = < AUDIO_TDM_WCLK>, < AUDIO_TDM_PCLK>;
+ clock-names = "tdm_wclk", "tdm_pclk";
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ zte,tdm-dma-sysctrl = < 0x10c 0xf 0xf>;
+ status = "ok";
+ };
--
2.7.4
[PATCH v1 1/3] ASoC: zx-tdm: add documentation for zte's tdm controller
This patch adds dt-binding documentation for zte's tdm controller.
Signed-off-by: Baoyou Xie
---
.../devicetree/bindings/sound/zte,tdm.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/zte,tdm.txt
diff --git a/Documentation/devicetree/bindings/sound/zte,tdm.txt
b/Documentation/devicetree/bindings/sound/zte,tdm.txt
new file mode 100644
index 000..f6e4f7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/zte,tdm.txt
@@ -0,0 +1,32 @@
+ZTE TDM DAI driver
+
+Required properties:
+
+- compatible : should be one of the following.
+ * zte,zx-tdm
+- reg : physical base address of the controller and length of memory mapped
+region.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- clock-names: "tdm_wclk" for the wclk.
+ "tdm_pclk" for the pclk.
+-#clock-cells: should be 1.
+- zte,tdm-dma-sysctrl : Reference to the sysctrl controller controlling
+the dma. includes:
+ phandle of sysctrl.
+ register offset in sysctrl for control dma.
+ mask of the register that be written to dma.
+ value of the register that be written to dma.
+
+Example:
+
+ tdm: tdm@1487000 {
+ compatible = "zte,zx-tdm";
+ reg = <0x01487000 0x1000>;
+ clocks = < AUDIO_TDM_WCLK>, < AUDIO_TDM_PCLK>;
+ clock-names = "tdm_wclk", "tdm_pclk";
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ zte,tdm-dma-sysctrl = < 0x10c 0xf 0xf>;
+ status = "ok";
+ };
--
2.7.4
[PATCH v6 2/3] MAINTAINERS: add zx2967 i2c controller driver to ARM ZTE architecture
Add the zx2967 i2c controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..313fab5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1987,9 +1987,11 @@ L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-zx/ F: drivers/clk/zte/ +F: drivers/i2c/busses/i2c-zx2967.c F: drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt +F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt F: Documentation/devicetree/bindings/soc/zte/ F: include/dt-bindings/soc/zx*.h -- 2.7.4
[PATCH v6 2/3] MAINTAINERS: add zx2967 i2c controller driver to ARM ZTE architecture
Add the zx2967 i2c controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..313fab5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1987,9 +1987,11 @@ L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-zx/ F: drivers/clk/zte/ +F: drivers/i2c/busses/i2c-zx2967.c F: drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt +F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt F: Documentation/devicetree/bindings/soc/zte/ F: include/dt-bindings/soc/zx*.h -- 2.7.4
[PATCH v6 1/3] dt: bindings: add documentation for zx2967 family i2c controller
This patch adds dt-binding documentation for zx2967 family
i2c controller.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Acked-by: Rob Herring <r...@kernel.org>
---
.../devicetree/bindings/i2c/i2c-zx2967.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
new file mode 100644
index 000..a528374
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
@@ -0,0 +1,24 @@
+ZTE zx2967 I2C controller
+
+Required properties:
+ - compatible: must be "zte,zx296718-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+ - clock-frequency: the desired I2C bus clock frequency.
+
+Examples:
+
+ i2c@112000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x00112000 0x1000>;
+ interrupts = ;
+ clocks = <>;
+ #address-cells = <1>
+ #size-cells = <0>;
+ clock-frequency = <160>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ };
--
2.7.4
[PATCH v6 1/3] dt: bindings: add documentation for zx2967 family i2c controller
This patch adds dt-binding documentation for zx2967 family
i2c controller.
Signed-off-by: Baoyou Xie
Acked-by: Rob Herring
---
.../devicetree/bindings/i2c/i2c-zx2967.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
new file mode 100644
index 000..a528374
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
@@ -0,0 +1,24 @@
+ZTE zx2967 I2C controller
+
+Required properties:
+ - compatible: must be "zte,zx296718-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+ - clock-frequency: the desired I2C bus clock frequency.
+
+Examples:
+
+ i2c@112000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x00112000 0x1000>;
+ interrupts = ;
+ clocks = <>;
+ #address-cells = <1>
+ #size-cells = <0>;
+ clock-frequency = <160>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ };
--
2.7.4
[PATCH v6 3/3] i2c: zx2967: add i2c controller driver for ZTE's zx2967 family
This patch adds i2c controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Reviewed-by: Shawn Guo <shawn...@kernel.org>
---
drivers/i2c/busses/Kconfig | 9 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-zx2967.c | 676
3 files changed, 686 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-zx2967.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e4a603e..d983e36 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1246,4 +1246,13 @@ config I2C_OPAL
This driver can also be built as a module. If so, the module will be
called as i2c-opal.
+config I2C_ZX2967
+ tristate "ZTE zx2967 I2C support"
+ depends on ARCH_ZX
+ default y
+ help
+ Selecting this option will add ZX2967 I2C driver.
+ This driver can also be built as a module. If so, the module will be
+ called i2c-zx2967.
+
endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index beb4809..16b2901 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_XILINX)+= i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
+obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
diff --git a/drivers/i2c/busses/i2c-zx2967.c b/drivers/i2c/busses/i2c-zx2967.c
new file mode 100644
index 000..3a36b84
--- /dev/null
+++ b/drivers/i2c/busses/i2c-zx2967.c
@@ -0,0 +1,676 @@
+/*
+ * ZTE's zx2967 family i2c bus controller driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie <baoyou@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_CMD0x04
+#define REG_DEVADDR_H 0x0C
+#define REG_DEVADDR_L 0x10
+#define REG_CLK_DIV_FS 0x14
+#define REG_CLK_DIV_HS 0x18
+#define REG_WRCONF 0x1C
+#define REG_RDCONF 0x20
+#define REG_DATA 0x24
+#define REG_STAT 0x28
+
+#define I2C_STOP 0
+#define I2C_MASTER BIT(0)
+#define I2C_ADDR_MODE_TEN BIT(1)
+#define I2C_IRQ_MSK_ENABLE BIT(3)
+#define I2C_RW_READBIT(4)
+#define I2C_CMB_RW_EN BIT(5)
+#define I2C_START BIT(6)
+
+#define I2C_ADDR_LOW_MASK GENMASK(6, 0)
+#define I2C_ADDR_LOW_SHIFT 0
+#define I2C_ADDR_HI_MASK GENMASK(2, 0)
+#define I2C_ADDR_HI_SHIFT 7
+
+#define I2C_WFIFO_RESETBIT(7)
+#define I2C_RFIFO_RESETBIT(7)
+
+#define I2C_IRQ_ACK_CLEAR BIT(7)
+#define I2C_INT_MASK GENMASK(6, 0)
+
+#define I2C_TRANS_DONE BIT(0)
+#define I2C_ERROR_DEVICE BIT(1)
+#define I2C_ERROR_DATA BIT(2)
+#define I2C_ERROR_MASK GENMASK(2, 1)
+
+#define I2C_SR_BUSYBIT(6)
+
+#define I2C_SR_EDEVICE BIT(1)
+#define I2C_SR_EDATA BIT(2)
+
+#define I2C_FIFO_MAX 16
+
+#define I2C_TIMEOUTmsecs_to_jiffies(1000)
+
+#define DEV(i2c) (>adap.dev)
+
+struct zx2967_i2c_info {
+ spinlock_t lock;
+ struct i2c_adapter adap;
+ struct clk *clk;
+ struct completion complete;
+ u32 clk_freq;
+ void __iomem*reg_base;
+ size_t residue;
+ int irq;
+ int msg_rd;
+ u8 *cur_trans;
+ u8 access_cnt;
+ boolis_suspended;
+};
+
+static void zx2967_i2c_writel(struct zx2967_i2c_info *zx_i2c,
+ u32 val, unsigned long reg)
+{
+ writel_relaxed(val, zx_i2c->reg_base + reg);
+}
+
+static u32 zx2967_i2c_readl(struct zx2967_i2c_info *zx_i2c, unsigned long reg)
+{
+ return readl_relaxed(zx_i2c->reg_base + reg);
+}
+
+static void zx2967_i2c_writesb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ writesb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_readsb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ readsb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_start_ctrl(struct zx2
[PATCH v6 3/3] i2c: zx2967: add i2c controller driver for ZTE's zx2967 family
This patch adds i2c controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie
Reviewed-by: Shawn Guo
---
drivers/i2c/busses/Kconfig | 9 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-zx2967.c | 676
3 files changed, 686 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-zx2967.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e4a603e..d983e36 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1246,4 +1246,13 @@ config I2C_OPAL
This driver can also be built as a module. If so, the module will be
called as i2c-opal.
+config I2C_ZX2967
+ tristate "ZTE zx2967 I2C support"
+ depends on ARCH_ZX
+ default y
+ help
+ Selecting this option will add ZX2967 I2C driver.
+ This driver can also be built as a module. If so, the module will be
+ called i2c-zx2967.
+
endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index beb4809..16b2901 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_XILINX)+= i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
+obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
diff --git a/drivers/i2c/busses/i2c-zx2967.c b/drivers/i2c/busses/i2c-zx2967.c
new file mode 100644
index 000..3a36b84
--- /dev/null
+++ b/drivers/i2c/busses/i2c-zx2967.c
@@ -0,0 +1,676 @@
+/*
+ * ZTE's zx2967 family i2c bus controller driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_CMD0x04
+#define REG_DEVADDR_H 0x0C
+#define REG_DEVADDR_L 0x10
+#define REG_CLK_DIV_FS 0x14
+#define REG_CLK_DIV_HS 0x18
+#define REG_WRCONF 0x1C
+#define REG_RDCONF 0x20
+#define REG_DATA 0x24
+#define REG_STAT 0x28
+
+#define I2C_STOP 0
+#define I2C_MASTER BIT(0)
+#define I2C_ADDR_MODE_TEN BIT(1)
+#define I2C_IRQ_MSK_ENABLE BIT(3)
+#define I2C_RW_READBIT(4)
+#define I2C_CMB_RW_EN BIT(5)
+#define I2C_START BIT(6)
+
+#define I2C_ADDR_LOW_MASK GENMASK(6, 0)
+#define I2C_ADDR_LOW_SHIFT 0
+#define I2C_ADDR_HI_MASK GENMASK(2, 0)
+#define I2C_ADDR_HI_SHIFT 7
+
+#define I2C_WFIFO_RESETBIT(7)
+#define I2C_RFIFO_RESETBIT(7)
+
+#define I2C_IRQ_ACK_CLEAR BIT(7)
+#define I2C_INT_MASK GENMASK(6, 0)
+
+#define I2C_TRANS_DONE BIT(0)
+#define I2C_ERROR_DEVICE BIT(1)
+#define I2C_ERROR_DATA BIT(2)
+#define I2C_ERROR_MASK GENMASK(2, 1)
+
+#define I2C_SR_BUSYBIT(6)
+
+#define I2C_SR_EDEVICE BIT(1)
+#define I2C_SR_EDATA BIT(2)
+
+#define I2C_FIFO_MAX 16
+
+#define I2C_TIMEOUTmsecs_to_jiffies(1000)
+
+#define DEV(i2c) (>adap.dev)
+
+struct zx2967_i2c_info {
+ spinlock_t lock;
+ struct i2c_adapter adap;
+ struct clk *clk;
+ struct completion complete;
+ u32 clk_freq;
+ void __iomem*reg_base;
+ size_t residue;
+ int irq;
+ int msg_rd;
+ u8 *cur_trans;
+ u8 access_cnt;
+ boolis_suspended;
+};
+
+static void zx2967_i2c_writel(struct zx2967_i2c_info *zx_i2c,
+ u32 val, unsigned long reg)
+{
+ writel_relaxed(val, zx_i2c->reg_base + reg);
+}
+
+static u32 zx2967_i2c_readl(struct zx2967_i2c_info *zx_i2c, unsigned long reg)
+{
+ return readl_relaxed(zx_i2c->reg_base + reg);
+}
+
+static void zx2967_i2c_writesb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ writesb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_readsb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ readsb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_start_ctrl(struct zx2967_i2c_info *zx_i2c)
+{
+ u32 status;
+ u32 ctl;
+
+ status = zx2967_i
[PATCH v4 1/3] clk: zte: add i2s clocks for zx296718
The i2s related clock support is missing from the existing zx296718
clock driver. This patch adds it, so that the upstream ZX I2S driver
can work out.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
drivers/clk/zte/clk-zx296718.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index ad5d1df..2f7c668 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -936,6 +936,10 @@ static struct zx_clk_gate audio_gate_clk[] = {
GATE(AUDIO_I2S1_WCLK, "i2s1_wclk", "i2s1_wclk_div", AUDIO_I2S1_CLK, 9,
CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_I2S2_WCLK, "i2s2_wclk", "i2s2_wclk_div", AUDIO_I2S2_CLK, 9,
CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_I2S3_WCLK, "i2s3_wclk", "i2s3_wclk_div", AUDIO_I2S3_CLK, 9,
CLK_SET_RATE_PARENT, 0),
+ GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0),
GATE(AUDIO_I2C0_WCLK, "i2c0_wclk", "i2c0_wclk_mux", AUDIO_I2C0_CLK, 9,
CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_SPDIF0_WCLK, "spdif0_wclk", "spdif0_wclk_div",
AUDIO_SPDIF0_CLK, 9, CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div",
AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
--
2.7.4
[PATCH v4 1/3] clk: zte: add i2s clocks for zx296718
The i2s related clock support is missing from the existing zx296718
clock driver. This patch adds it, so that the upstream ZX I2S driver
can work out.
Signed-off-by: Baoyou Xie
---
drivers/clk/zte/clk-zx296718.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index ad5d1df..2f7c668 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -936,6 +936,10 @@ static struct zx_clk_gate audio_gate_clk[] = {
GATE(AUDIO_I2S1_WCLK, "i2s1_wclk", "i2s1_wclk_div", AUDIO_I2S1_CLK, 9,
CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_I2S2_WCLK, "i2s2_wclk", "i2s2_wclk_div", AUDIO_I2S2_CLK, 9,
CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_I2S3_WCLK, "i2s3_wclk", "i2s3_wclk_div", AUDIO_I2S3_CLK, 9,
CLK_SET_RATE_PARENT, 0),
+ GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0),
GATE(AUDIO_I2C0_WCLK, "i2c0_wclk", "i2c0_wclk_mux", AUDIO_I2C0_CLK, 9,
CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_SPDIF0_WCLK, "spdif0_wclk", "spdif0_wclk_div",
AUDIO_SPDIF0_CLK, 9, CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div",
AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
--
2.7.4
[PATCH v4 2/3] ASoC: zx-i2s: Add the info of pclk to the binding document for zx2967 family
ZTE's zx2967 I2S controller driver introduces pclk, this
patch documents this fact.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
Documentation/devicetree/bindings/sound/zte,zx-i2s.txt | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
index 7e5aa6f..292ad50 100644
--- a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
@@ -1,10 +1,12 @@
ZTE ZX296702 I2S controller
Required properties:
- - compatible : Must be "zte,zx296702-i2s"
+ - compatible : Must be one of:
+ "zte,zx296718-i2s", "zte,zx296702-i2s"
+ "zte,zx296702-i2s"
- reg : Must contain I2S core's registers location and length
- clocks : Pairs of phandle and specifier referencing the controller's clocks.
- - clock-names: "tx" for the clock to the I2S interface.
+ - clock-names: "wclk" for the wclk, "pclk" for the pclk to the I2S interface.
- dmas: Pairs of phandle and specifier for the DMA channel that is used by
the core. The core expects two dma channels for transmit.
- dma-names : Must be "tx" and "rx"
@@ -16,12 +18,12 @@ please check:
* dma/dma.txt
Example:
- i2s0: i2s0@0b005000 {
+ i2s0: i2s@b005000 {
#sound-dai-cells = <0>;
- compatible = "zte,zx296702-i2s";
+ compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
reg = <0x0b005000 0x1000>;
- clocks = < ZX296702_I2S0_DIV>;
- clock-names = "tx";
+ clocks = < AUDIO_I2S0_WCLK>, <
AUDIO_I2S0_PCLK>;
+ clock-names = "wclk", "pclk";
interrupts = ;
dmas = < 5>, < 6>;
dma-names = "tx", "rx";
--
2.7.4
[PATCH v4 3/3] ASoC: zx-i2s: introduce pclk for zx2967 family
The pclk is necessary for zx2967 I2S controller. the driver
currently doesn't handle it. This is something we need to fix.
In turn, the driver supports zx296718's I2S controller.
By the way, this patch also change the clock name from tx to wclk
to make it clear.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
sound/soc/zte/zx-i2s.c | 38 +-
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/sound/soc/zte/zx-i2s.c b/sound/soc/zte/zx-i2s.c
index ed7a56d..a865f37 100644
--- a/sound/soc/zte/zx-i2s.c
+++ b/sound/soc/zte/zx-i2s.c
@@ -95,7 +95,8 @@
struct zx_i2s_info {
struct snd_dmaengine_dai_dma_data dma_playback;
struct snd_dmaengine_dai_dma_data dma_capture;
- struct clk *dai_clk;
+ struct clk *dai_wclk;
+ struct clk *dai_pclk;
void __iomem*reg_base;
int master;
resource_size_t mapbase;
@@ -275,8 +276,9 @@ static int zx_i2s_hw_params(struct snd_pcm_substream
*substream,
writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
if (i2s->master)
- ret = clk_set_rate(i2s->dai_clk,
- params_rate(params) * ch_num * CLK_RAT);
+ ret = clk_set_rate(i2s->dai_wclk,
+ params_rate(params) * ch_num * CLK_RAT);
+
return ret;
}
@@ -328,8 +330,19 @@ static int zx_i2s_startup(struct snd_pcm_substream
*substream,
struct snd_soc_dai *dai)
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
+ int ret;
+
+ ret = clk_prepare_enable(zx_i2s->dai_wclk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(zx_i2s->dai_pclk);
+ if (ret) {
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ return ret;
+ }
- return clk_prepare_enable(zx_i2s->dai_clk);
+ return ret;
}
static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
@@ -337,7 +350,8 @@ static void zx_i2s_shutdown(struct snd_pcm_substream
*substream,
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
- clk_disable_unprepare(zx_i2s->dai_clk);
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ clk_disable_unprepare(zx_i2s->dai_pclk);
}
static struct snd_soc_dai_ops zx_i2s_dai_ops = {
@@ -381,10 +395,16 @@ static int zx_i2s_probe(struct platform_device *pdev)
if (!zx_i2s)
return -ENOMEM;
- zx_i2s->dai_clk = devm_clk_get(>dev, "tx");
- if (IS_ERR(zx_i2s->dai_clk)) {
- dev_err(>dev, "Fail to get clk\n");
- return PTR_ERR(zx_i2s->dai_clk);
+ zx_i2s->dai_wclk = devm_clk_get(>dev, "wclk");
+ if (IS_ERR(zx_i2s->dai_wclk)) {
+ dev_err(>dev, "Fail to get wclk\n");
+ return PTR_ERR(zx_i2s->dai_wclk);
+ }
+
+ zx_i2s->dai_pclk = devm_clk_get(>dev, "pclk");
+ if (IS_ERR(zx_i2s->dai_pclk)) {
+ dev_err(>dev, "Fail to get pclk\n");
+ return PTR_ERR(zx_i2s->dai_pclk);
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--
2.7.4
[PATCH v4 2/3] ASoC: zx-i2s: Add the info of pclk to the binding document for zx2967 family
ZTE's zx2967 I2S controller driver introduces pclk, this
patch documents this fact.
Signed-off-by: Baoyou Xie
---
Documentation/devicetree/bindings/sound/zte,zx-i2s.txt | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
index 7e5aa6f..292ad50 100644
--- a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
@@ -1,10 +1,12 @@
ZTE ZX296702 I2S controller
Required properties:
- - compatible : Must be "zte,zx296702-i2s"
+ - compatible : Must be one of:
+ "zte,zx296718-i2s", "zte,zx296702-i2s"
+ "zte,zx296702-i2s"
- reg : Must contain I2S core's registers location and length
- clocks : Pairs of phandle and specifier referencing the controller's clocks.
- - clock-names: "tx" for the clock to the I2S interface.
+ - clock-names: "wclk" for the wclk, "pclk" for the pclk to the I2S interface.
- dmas: Pairs of phandle and specifier for the DMA channel that is used by
the core. The core expects two dma channels for transmit.
- dma-names : Must be "tx" and "rx"
@@ -16,12 +18,12 @@ please check:
* dma/dma.txt
Example:
- i2s0: i2s0@0b005000 {
+ i2s0: i2s@b005000 {
#sound-dai-cells = <0>;
- compatible = "zte,zx296702-i2s";
+ compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
reg = <0x0b005000 0x1000>;
- clocks = < ZX296702_I2S0_DIV>;
- clock-names = "tx";
+ clocks = < AUDIO_I2S0_WCLK>, <
AUDIO_I2S0_PCLK>;
+ clock-names = "wclk", "pclk";
interrupts = ;
dmas = < 5>, < 6>;
dma-names = "tx", "rx";
--
2.7.4
[PATCH v4 3/3] ASoC: zx-i2s: introduce pclk for zx2967 family
The pclk is necessary for zx2967 I2S controller. the driver
currently doesn't handle it. This is something we need to fix.
In turn, the driver supports zx296718's I2S controller.
By the way, this patch also change the clock name from tx to wclk
to make it clear.
Signed-off-by: Baoyou Xie
---
sound/soc/zte/zx-i2s.c | 38 +-
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/sound/soc/zte/zx-i2s.c b/sound/soc/zte/zx-i2s.c
index ed7a56d..a865f37 100644
--- a/sound/soc/zte/zx-i2s.c
+++ b/sound/soc/zte/zx-i2s.c
@@ -95,7 +95,8 @@
struct zx_i2s_info {
struct snd_dmaengine_dai_dma_data dma_playback;
struct snd_dmaengine_dai_dma_data dma_capture;
- struct clk *dai_clk;
+ struct clk *dai_wclk;
+ struct clk *dai_pclk;
void __iomem*reg_base;
int master;
resource_size_t mapbase;
@@ -275,8 +276,9 @@ static int zx_i2s_hw_params(struct snd_pcm_substream
*substream,
writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
if (i2s->master)
- ret = clk_set_rate(i2s->dai_clk,
- params_rate(params) * ch_num * CLK_RAT);
+ ret = clk_set_rate(i2s->dai_wclk,
+ params_rate(params) * ch_num * CLK_RAT);
+
return ret;
}
@@ -328,8 +330,19 @@ static int zx_i2s_startup(struct snd_pcm_substream
*substream,
struct snd_soc_dai *dai)
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
+ int ret;
+
+ ret = clk_prepare_enable(zx_i2s->dai_wclk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(zx_i2s->dai_pclk);
+ if (ret) {
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ return ret;
+ }
- return clk_prepare_enable(zx_i2s->dai_clk);
+ return ret;
}
static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
@@ -337,7 +350,8 @@ static void zx_i2s_shutdown(struct snd_pcm_substream
*substream,
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
- clk_disable_unprepare(zx_i2s->dai_clk);
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ clk_disable_unprepare(zx_i2s->dai_pclk);
}
static struct snd_soc_dai_ops zx_i2s_dai_ops = {
@@ -381,10 +395,16 @@ static int zx_i2s_probe(struct platform_device *pdev)
if (!zx_i2s)
return -ENOMEM;
- zx_i2s->dai_clk = devm_clk_get(>dev, "tx");
- if (IS_ERR(zx_i2s->dai_clk)) {
- dev_err(>dev, "Fail to get clk\n");
- return PTR_ERR(zx_i2s->dai_clk);
+ zx_i2s->dai_wclk = devm_clk_get(>dev, "wclk");
+ if (IS_ERR(zx_i2s->dai_wclk)) {
+ dev_err(>dev, "Fail to get wclk\n");
+ return PTR_ERR(zx_i2s->dai_wclk);
+ }
+
+ zx_i2s->dai_pclk = devm_clk_get(>dev, "pclk");
+ if (IS_ERR(zx_i2s->dai_pclk)) {
+ dev_err(>dev, "Fail to get pclk\n");
+ return PTR_ERR(zx_i2s->dai_pclk);
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--
2.7.4
[PATCH v5 2/3] MAINTAINERS: add zx2967 i2c controller driver to ARM ZTE architecture
Add the zx2967 i2c controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..313fab5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1987,9 +1987,11 @@ L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-zx/ F: drivers/clk/zte/ +F: drivers/i2c/busses/i2c-zx2967.c F: drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt +F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt F: Documentation/devicetree/bindings/soc/zte/ F: include/dt-bindings/soc/zx*.h -- 2.7.4
[PATCH v5 2/3] MAINTAINERS: add zx2967 i2c controller driver to ARM ZTE architecture
Add the zx2967 i2c controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e63063b..313fab5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1987,9 +1987,11 @@ L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-zx/ F: drivers/clk/zte/ +F: drivers/i2c/busses/i2c-zx2967.c F: drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt +F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt F: Documentation/devicetree/bindings/soc/zte/ F: include/dt-bindings/soc/zx*.h -- 2.7.4
[PATCH v5 3/3] i2c: zx2967: add i2c controller driver for ZTE's zx2967 family
This patch adds i2c controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Reviewed-by: Shawn Guo <shawn...@kernel.org>
---
drivers/i2c/busses/Kconfig | 9 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-zx2967.c | 676
3 files changed, 686 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-zx2967.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e4a603e..d983e36 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1246,4 +1246,13 @@ config I2C_OPAL
This driver can also be built as a module. If so, the module will be
called as i2c-opal.
+config I2C_ZX2967
+ tristate "ZTE zx2967 I2C support"
+ depends on ARCH_ZX
+ default y
+ help
+ Selecting this option will add ZX2967 I2C driver.
+ This driver can also be built as a module. If so, the module will be
+ called i2c-zx2967.
+
endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index beb4809..16b2901 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_XILINX)+= i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
+obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
diff --git a/drivers/i2c/busses/i2c-zx2967.c b/drivers/i2c/busses/i2c-zx2967.c
new file mode 100644
index 000..0cf04b7
--- /dev/null
+++ b/drivers/i2c/busses/i2c-zx2967.c
@@ -0,0 +1,676 @@
+/*
+ * ZTE's zx2967 family i2c bus controller driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie <baoyou@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_CMD0x04
+#define REG_DEVADDR_H 0x0C
+#define REG_DEVADDR_L 0x10
+#define REG_CLK_DIV_FS 0x14
+#define REG_CLK_DIV_HS 0x18
+#define REG_WRCONF 0x1C
+#define REG_RDCONF 0x20
+#define REG_DATA 0x24
+#define REG_STAT 0x28
+
+#define I2C_STOP 0
+#define I2C_MASTER BIT(0)
+#define I2C_ADDR_MODE_TEN BIT(1)
+#define I2C_IRQ_MSK_ENABLE BIT(3)
+#define I2C_RW_READBIT(4)
+#define I2C_CMB_RW_EN BIT(5)
+#define I2C_START BIT(6)
+
+#define I2C_TENBIT_SHIFT 7
+#define I2C_TENBIT_MASKGENMASK(2, 0)
+
+#define I2C_WFIFO_RESETBIT(7)
+#define I2C_RFIFO_RESETBIT(7)
+
+#define I2C_IRQ_ACK_CLEAR BIT(7)
+#define I2C_INT_MASK GENMASK(6, 0)
+
+#define I2C_TRANS_DONE BIT(0)
+#define I2C_ERROR_DEVICE BIT(1)
+#define I2C_ERROR_DATA BIT(2)
+#define I2C_ERROR_MASK GENMASK(2, 1)
+
+#define I2C_SR_BUSYBIT(6)
+
+#define I2C_SR_EDEVICE BIT(1)
+#define I2C_SR_EDATA BIT(2)
+
+#define I2C_FIFO_MAX 16
+
+#define I2C_TIMEOUTmsecs_to_jiffies(1000)
+
+#define DEV(i2c) (>adap.dev)
+
+struct zx2967_i2c_info {
+ spinlock_t lock;
+ struct i2c_adapter adap;
+ struct clk *clk;
+ struct completion complete;
+ u32 clk_freq;
+ void __iomem*reg_base;
+ size_t residue;
+ int irq;
+ int msg_rd;
+ u8 *buf;
+ u8 access_cnt;
+ boolis_suspended;
+};
+
+static void zx2967_i2c_writel(struct zx2967_i2c_info *zx_i2c,
+ u32 val, unsigned long reg)
+{
+ writel_relaxed(val, zx_i2c->reg_base + reg);
+}
+
+static u32 zx2967_i2c_readl(struct zx2967_i2c_info *zx_i2c, unsigned long reg)
+{
+ return readl_relaxed(zx_i2c->reg_base + reg);
+}
+
+static void zx2967_i2c_writesb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ writesb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_readsb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ readsb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_start_ctrl(struct zx2967_i2c_info *zx_i2c)
+{
+ u32 status;
+ u32 ctl;
+
+ status = zx2967_
[PATCH v5 3/3] i2c: zx2967: add i2c controller driver for ZTE's zx2967 family
This patch adds i2c controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie
Reviewed-by: Shawn Guo
---
drivers/i2c/busses/Kconfig | 9 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-zx2967.c | 676
3 files changed, 686 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-zx2967.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e4a603e..d983e36 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1246,4 +1246,13 @@ config I2C_OPAL
This driver can also be built as a module. If so, the module will be
called as i2c-opal.
+config I2C_ZX2967
+ tristate "ZTE zx2967 I2C support"
+ depends on ARCH_ZX
+ default y
+ help
+ Selecting this option will add ZX2967 I2C driver.
+ This driver can also be built as a module. If so, the module will be
+ called i2c-zx2967.
+
endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index beb4809..16b2901 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_XILINX)+= i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
+obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
diff --git a/drivers/i2c/busses/i2c-zx2967.c b/drivers/i2c/busses/i2c-zx2967.c
new file mode 100644
index 000..0cf04b7
--- /dev/null
+++ b/drivers/i2c/busses/i2c-zx2967.c
@@ -0,0 +1,676 @@
+/*
+ * ZTE's zx2967 family i2c bus controller driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_CMD0x04
+#define REG_DEVADDR_H 0x0C
+#define REG_DEVADDR_L 0x10
+#define REG_CLK_DIV_FS 0x14
+#define REG_CLK_DIV_HS 0x18
+#define REG_WRCONF 0x1C
+#define REG_RDCONF 0x20
+#define REG_DATA 0x24
+#define REG_STAT 0x28
+
+#define I2C_STOP 0
+#define I2C_MASTER BIT(0)
+#define I2C_ADDR_MODE_TEN BIT(1)
+#define I2C_IRQ_MSK_ENABLE BIT(3)
+#define I2C_RW_READBIT(4)
+#define I2C_CMB_RW_EN BIT(5)
+#define I2C_START BIT(6)
+
+#define I2C_TENBIT_SHIFT 7
+#define I2C_TENBIT_MASKGENMASK(2, 0)
+
+#define I2C_WFIFO_RESETBIT(7)
+#define I2C_RFIFO_RESETBIT(7)
+
+#define I2C_IRQ_ACK_CLEAR BIT(7)
+#define I2C_INT_MASK GENMASK(6, 0)
+
+#define I2C_TRANS_DONE BIT(0)
+#define I2C_ERROR_DEVICE BIT(1)
+#define I2C_ERROR_DATA BIT(2)
+#define I2C_ERROR_MASK GENMASK(2, 1)
+
+#define I2C_SR_BUSYBIT(6)
+
+#define I2C_SR_EDEVICE BIT(1)
+#define I2C_SR_EDATA BIT(2)
+
+#define I2C_FIFO_MAX 16
+
+#define I2C_TIMEOUTmsecs_to_jiffies(1000)
+
+#define DEV(i2c) (>adap.dev)
+
+struct zx2967_i2c_info {
+ spinlock_t lock;
+ struct i2c_adapter adap;
+ struct clk *clk;
+ struct completion complete;
+ u32 clk_freq;
+ void __iomem*reg_base;
+ size_t residue;
+ int irq;
+ int msg_rd;
+ u8 *buf;
+ u8 access_cnt;
+ boolis_suspended;
+};
+
+static void zx2967_i2c_writel(struct zx2967_i2c_info *zx_i2c,
+ u32 val, unsigned long reg)
+{
+ writel_relaxed(val, zx_i2c->reg_base + reg);
+}
+
+static u32 zx2967_i2c_readl(struct zx2967_i2c_info *zx_i2c, unsigned long reg)
+{
+ return readl_relaxed(zx_i2c->reg_base + reg);
+}
+
+static void zx2967_i2c_writesb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ writesb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_readsb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ readsb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_start_ctrl(struct zx2967_i2c_info *zx_i2c)
+{
+ u32 status;
+ u32 ctl;
+
+ status = zx2967_i2c_readl(zx_i2c, REG_STAT);
+ status |= I2C_IRQ_ACK_CLEAR;
+ zx2967_i2c_writel
[PATCH v5 1/3] dt: bindings: add documentation for zx2967 family i2c controller
This patch adds dt-binding documentation for zx2967 family
i2c controller.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Acked-by: Rob Herring <r...@kernel.org>
---
.../devicetree/bindings/i2c/i2c-zx2967.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
new file mode 100644
index 000..a528374
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
@@ -0,0 +1,24 @@
+ZTE zx2967 I2C controller
+
+Required properties:
+ - compatible: must be "zte,zx296718-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+ - clock-frequency: the desired I2C bus clock frequency.
+
+Examples:
+
+ i2c@112000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x00112000 0x1000>;
+ interrupts = ;
+ clocks = <>;
+ #address-cells = <1>
+ #size-cells = <0>;
+ clock-frequency = <160>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ };
--
2.7.4
[PATCH v5 1/3] dt: bindings: add documentation for zx2967 family i2c controller
This patch adds dt-binding documentation for zx2967 family
i2c controller.
Signed-off-by: Baoyou Xie
Acked-by: Rob Herring
---
.../devicetree/bindings/i2c/i2c-zx2967.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
new file mode 100644
index 000..a528374
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
@@ -0,0 +1,24 @@
+ZTE zx2967 I2C controller
+
+Required properties:
+ - compatible: must be "zte,zx296718-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+ - clock-frequency: the desired I2C bus clock frequency.
+
+Examples:
+
+ i2c@112000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x00112000 0x1000>;
+ interrupts = ;
+ clocks = <>;
+ #address-cells = <1>
+ #size-cells = <0>;
+ clock-frequency = <160>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ };
--
2.7.4
[PATCH v3 2/3] ASoC: zx-i2s: introduce pclk for zx2967 family
ZTE's zx2967 I2S controller driver introduces pclk, this
patch documents this fact.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
Documentation/devicetree/bindings/sound/zte,zx-i2s.txt | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
index 7e5aa6f..77390c0 100644
--- a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
@@ -4,7 +4,7 @@ Required properties:
- compatible : Must be "zte,zx296702-i2s"
- reg : Must contain I2S core's registers location and length
- clocks : Pairs of phandle and specifier referencing the controller's clocks.
- - clock-names: "tx" for the clock to the I2S interface.
+ - clock-names: "wclk" for the wclk, "pclk" for the pclk to the I2S interface.
- dmas: Pairs of phandle and specifier for the DMA channel that is used by
the core. The core expects two dma channels for transmit.
- dma-names : Must be "tx" and "rx"
@@ -15,13 +15,17 @@ please check:
* clock/clock-bindings.txt
* dma/dma.txt
+Please note that ZTE ZX296702 I2S controller driver is compatible for zx296702
+and zx296718, so compatible string might be set as follow:
+ "zte,zx296718-i2s", "zte,zx296702-i2s"
+
Example:
i2s0: i2s0@0b005000 {
#sound-dai-cells = <0>;
- compatible = "zte,zx296702-i2s";
+ compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
reg = <0x0b005000 0x1000>;
- clocks = < ZX296702_I2S0_DIV>;
- clock-names = "tx";
+ clocks = < AUDIO_I2S0_WCLK>, <
AUDIO_I2S0_PCLK>;
+ clock-names = "wclk", "pclk";
interrupts = ;
dmas = < 5>, < 6>;
dma-names = "tx", "rx";
--
2.7.4
[PATCH v3 2/3] ASoC: zx-i2s: introduce pclk for zx2967 family
ZTE's zx2967 I2S controller driver introduces pclk, this
patch documents this fact.
Signed-off-by: Baoyou Xie
---
Documentation/devicetree/bindings/sound/zte,zx-i2s.txt | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
index 7e5aa6f..77390c0 100644
--- a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt
@@ -4,7 +4,7 @@ Required properties:
- compatible : Must be "zte,zx296702-i2s"
- reg : Must contain I2S core's registers location and length
- clocks : Pairs of phandle and specifier referencing the controller's clocks.
- - clock-names: "tx" for the clock to the I2S interface.
+ - clock-names: "wclk" for the wclk, "pclk" for the pclk to the I2S interface.
- dmas: Pairs of phandle and specifier for the DMA channel that is used by
the core. The core expects two dma channels for transmit.
- dma-names : Must be "tx" and "rx"
@@ -15,13 +15,17 @@ please check:
* clock/clock-bindings.txt
* dma/dma.txt
+Please note that ZTE ZX296702 I2S controller driver is compatible for zx296702
+and zx296718, so compatible string might be set as follow:
+ "zte,zx296718-i2s", "zte,zx296702-i2s"
+
Example:
i2s0: i2s0@0b005000 {
#sound-dai-cells = <0>;
- compatible = "zte,zx296702-i2s";
+ compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
reg = <0x0b005000 0x1000>;
- clocks = < ZX296702_I2S0_DIV>;
- clock-names = "tx";
+ clocks = < AUDIO_I2S0_WCLK>, <
AUDIO_I2S0_PCLK>;
+ clock-names = "wclk", "pclk";
interrupts = ;
dmas = < 5>, < 6>;
dma-names = "tx", "rx";
--
2.7.4
[PATCH v3 3/3] ASoC: zx-i2s: introduce pclk for zx2967 family
The pclk is necessary for zx2967 I2S controller. the driver
currently doesn't handle it. This is something we need to fix.
In turn, the driver supports zx296718's I2S controller.
By the way, this patch also change the clock name from tx to wclk
to make it clear.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
sound/soc/zte/zx-i2s.c | 37 -
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/sound/soc/zte/zx-i2s.c b/sound/soc/zte/zx-i2s.c
index ed7a56d..2d486ea 100644
--- a/sound/soc/zte/zx-i2s.c
+++ b/sound/soc/zte/zx-i2s.c
@@ -95,7 +95,7 @@
struct zx_i2s_info {
struct snd_dmaengine_dai_dma_data dma_playback;
struct snd_dmaengine_dai_dma_data dma_capture;
- struct clk *dai_clk;
+ struct clk *dai_wclk, *dai_pclk;
void __iomem*reg_base;
int master;
resource_size_t mapbase;
@@ -275,8 +275,9 @@ static int zx_i2s_hw_params(struct snd_pcm_substream
*substream,
writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
if (i2s->master)
- ret = clk_set_rate(i2s->dai_clk,
- params_rate(params) * ch_num * CLK_RAT);
+ ret = clk_set_rate(i2s->dai_wclk,
+ params_rate(params) * ch_num * CLK_RAT);
+
return ret;
}
@@ -328,8 +329,19 @@ static int zx_i2s_startup(struct snd_pcm_substream
*substream,
struct snd_soc_dai *dai)
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
+ int ret;
+
+ ret = clk_prepare_enable(zx_i2s->dai_wclk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(zx_i2s->dai_pclk);
+ if (ret) {
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ return ret;
+ }
- return clk_prepare_enable(zx_i2s->dai_clk);
+ return ret;
}
static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
@@ -337,7 +349,8 @@ static void zx_i2s_shutdown(struct snd_pcm_substream
*substream,
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
- clk_disable_unprepare(zx_i2s->dai_clk);
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ clk_disable_unprepare(zx_i2s->dai_pclk);
}
static struct snd_soc_dai_ops zx_i2s_dai_ops = {
@@ -381,10 +394,16 @@ static int zx_i2s_probe(struct platform_device *pdev)
if (!zx_i2s)
return -ENOMEM;
- zx_i2s->dai_clk = devm_clk_get(>dev, "tx");
- if (IS_ERR(zx_i2s->dai_clk)) {
- dev_err(>dev, "Fail to get clk\n");
- return PTR_ERR(zx_i2s->dai_clk);
+ zx_i2s->dai_wclk = devm_clk_get(>dev, "wclk");
+ if (IS_ERR(zx_i2s->dai_wclk)) {
+ dev_err(>dev, "Fail to get wclk\n");
+ return PTR_ERR(zx_i2s->dai_wclk);
+ }
+
+ zx_i2s->dai_pclk = devm_clk_get(>dev, "pclk");
+ if (IS_ERR(zx_i2s->dai_pclk)) {
+ dev_info(>dev, "have no pclk\n");
+ zx_i2s->dai_pclk = NULL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--
2.7.4
[PATCH v3 3/3] ASoC: zx-i2s: introduce pclk for zx2967 family
The pclk is necessary for zx2967 I2S controller. the driver
currently doesn't handle it. This is something we need to fix.
In turn, the driver supports zx296718's I2S controller.
By the way, this patch also change the clock name from tx to wclk
to make it clear.
Signed-off-by: Baoyou Xie
---
sound/soc/zte/zx-i2s.c | 37 -
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/sound/soc/zte/zx-i2s.c b/sound/soc/zte/zx-i2s.c
index ed7a56d..2d486ea 100644
--- a/sound/soc/zte/zx-i2s.c
+++ b/sound/soc/zte/zx-i2s.c
@@ -95,7 +95,7 @@
struct zx_i2s_info {
struct snd_dmaengine_dai_dma_data dma_playback;
struct snd_dmaengine_dai_dma_data dma_capture;
- struct clk *dai_clk;
+ struct clk *dai_wclk, *dai_pclk;
void __iomem*reg_base;
int master;
resource_size_t mapbase;
@@ -275,8 +275,9 @@ static int zx_i2s_hw_params(struct snd_pcm_substream
*substream,
writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
if (i2s->master)
- ret = clk_set_rate(i2s->dai_clk,
- params_rate(params) * ch_num * CLK_RAT);
+ ret = clk_set_rate(i2s->dai_wclk,
+ params_rate(params) * ch_num * CLK_RAT);
+
return ret;
}
@@ -328,8 +329,19 @@ static int zx_i2s_startup(struct snd_pcm_substream
*substream,
struct snd_soc_dai *dai)
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
+ int ret;
+
+ ret = clk_prepare_enable(zx_i2s->dai_wclk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(zx_i2s->dai_pclk);
+ if (ret) {
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ return ret;
+ }
- return clk_prepare_enable(zx_i2s->dai_clk);
+ return ret;
}
static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
@@ -337,7 +349,8 @@ static void zx_i2s_shutdown(struct snd_pcm_substream
*substream,
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
- clk_disable_unprepare(zx_i2s->dai_clk);
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ clk_disable_unprepare(zx_i2s->dai_pclk);
}
static struct snd_soc_dai_ops zx_i2s_dai_ops = {
@@ -381,10 +394,16 @@ static int zx_i2s_probe(struct platform_device *pdev)
if (!zx_i2s)
return -ENOMEM;
- zx_i2s->dai_clk = devm_clk_get(>dev, "tx");
- if (IS_ERR(zx_i2s->dai_clk)) {
- dev_err(>dev, "Fail to get clk\n");
- return PTR_ERR(zx_i2s->dai_clk);
+ zx_i2s->dai_wclk = devm_clk_get(>dev, "wclk");
+ if (IS_ERR(zx_i2s->dai_wclk)) {
+ dev_err(>dev, "Fail to get wclk\n");
+ return PTR_ERR(zx_i2s->dai_wclk);
+ }
+
+ zx_i2s->dai_pclk = devm_clk_get(>dev, "pclk");
+ if (IS_ERR(zx_i2s->dai_pclk)) {
+ dev_info(>dev, "have no pclk\n");
+ zx_i2s->dai_pclk = NULL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--
2.7.4
[PATCH v3 1/3] clk: zte: add i2s clocks for zx296718
The i2s related clock support is missing from the existing zx296718
clock driver. This patch adds it, so that the upstream ZX I2S driver
can work out.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
drivers/clk/zte/clk-zx296718.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index ad5d1df..f106d40 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -941,6 +941,10 @@ static struct zx_clk_gate audio_gate_clk[] = {
GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div",
AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_TDM_WCLK, "tdm_wclk", "tdm_wclk_div", AUDIO_TDM_CLK, 17,
CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_TS_PCLK, "tempsensor_pclk", "clk49m5", AUDIO_TS_CLK, 1, 0,
0),
+ GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0),
};
static struct clk_hw_onecell_data audio_hw_onecell_data = {
--
2.7.4
[PATCH v3 1/3] clk: zte: add i2s clocks for zx296718
The i2s related clock support is missing from the existing zx296718
clock driver. This patch adds it, so that the upstream ZX I2S driver
can work out.
Signed-off-by: Baoyou Xie
---
drivers/clk/zte/clk-zx296718.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index ad5d1df..f106d40 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -941,6 +941,10 @@ static struct zx_clk_gate audio_gate_clk[] = {
GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div",
AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_TDM_WCLK, "tdm_wclk", "tdm_wclk_div", AUDIO_TDM_CLK, 17,
CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_TS_PCLK, "tempsensor_pclk", "clk49m5", AUDIO_TS_CLK, 1, 0,
0),
+ GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0),
};
static struct clk_hw_onecell_data audio_hw_onecell_data = {
--
2.7.4
[PATCH v2 3/3] ASoC: zx-i2s: support zx296718 SoC for ZTE's i2s controller driver
This patch adds zx296718 SoC support for ZTE's i2s controller driver.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
sound/soc/zte/zx-i2s.c | 45 +++--
1 file changed, 35 insertions(+), 10 deletions(-)
diff --git a/sound/soc/zte/zx-i2s.c b/sound/soc/zte/zx-i2s.c
index ed7a56d..2afac69 100644
--- a/sound/soc/zte/zx-i2s.c
+++ b/sound/soc/zte/zx-i2s.c
@@ -95,12 +95,13 @@
struct zx_i2s_info {
struct snd_dmaengine_dai_dma_data dma_playback;
struct snd_dmaengine_dai_dma_data dma_capture;
- struct clk *dai_clk;
+ struct clk *dai_wclk, *dai_pclk;
void __iomem*reg_base;
int master;
resource_size_t mapbase;
};
+
static void zx_i2s_tx_en(void __iomem *base, bool on)
{
unsigned long val;
@@ -274,9 +275,14 @@ static int zx_i2s_hw_params(struct snd_pcm_substream
*substream,
val |= ZX_I2S_TIMING_CHN(ch_num);
writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
- if (i2s->master)
- ret = clk_set_rate(i2s->dai_clk,
- params_rate(params) * ch_num * CLK_RAT);
+ if (i2s->master) {
+ unsigned long rate = params_rate(params) * ch_num * CLK_RAT;
+
+ ret = clk_set_rate(i2s->dai_wclk, rate);
+ if (!ret && i2s->dai_pclk)
+ ret = clk_set_rate(i2s->dai_pclk, rate);
+ }
+
return ret;
}
@@ -328,8 +334,19 @@ static int zx_i2s_startup(struct snd_pcm_substream
*substream,
struct snd_soc_dai *dai)
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
+ int ret;
+
+ ret = clk_prepare_enable(zx_i2s->dai_wclk);
+ if (ret)
+ return ret;
- return clk_prepare_enable(zx_i2s->dai_clk);
+ ret = clk_prepare_enable(zx_i2s->dai_pclk);
+ if (ret) {
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ return ret;
+ }
+
+ return ret;
}
static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
@@ -337,7 +354,8 @@ static void zx_i2s_shutdown(struct snd_pcm_substream
*substream,
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
- clk_disable_unprepare(zx_i2s->dai_clk);
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ clk_disable_unprepare(zx_i2s->dai_pclk);
}
static struct snd_soc_dai_ops zx_i2s_dai_ops = {
@@ -381,10 +399,16 @@ static int zx_i2s_probe(struct platform_device *pdev)
if (!zx_i2s)
return -ENOMEM;
- zx_i2s->dai_clk = devm_clk_get(>dev, "tx");
- if (IS_ERR(zx_i2s->dai_clk)) {
- dev_err(>dev, "Fail to get clk\n");
- return PTR_ERR(zx_i2s->dai_clk);
+ zx_i2s->dai_wclk = devm_clk_get(>dev, "tx");
+ if (IS_ERR(zx_i2s->dai_wclk)) {
+ dev_err(>dev, "Fail to get wclk\n");
+ return PTR_ERR(zx_i2s->dai_wclk);
+ }
+
+ zx_i2s->dai_pclk = devm_clk_get(>dev, "pclk");
+ if (IS_ERR(zx_i2s->dai_pclk)) {
+ dev_info(>dev, "have no pclk\n");
+ zx_i2s->dai_pclk = NULL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -414,6 +438,7 @@ static int zx_i2s_probe(struct platform_device *pdev)
static const struct of_device_id zx_i2s_dt_ids[] = {
{ .compatible = "zte,zx296702-i2s", },
+ { .compatible = "zte,zx296718-i2s", },
{}
};
MODULE_DEVICE_TABLE(of, zx_i2s_dt_ids);
--
2.7.4
[PATCH v2 3/3] ASoC: zx-i2s: support zx296718 SoC for ZTE's i2s controller driver
This patch adds zx296718 SoC support for ZTE's i2s controller driver.
Signed-off-by: Baoyou Xie
---
sound/soc/zte/zx-i2s.c | 45 +++--
1 file changed, 35 insertions(+), 10 deletions(-)
diff --git a/sound/soc/zte/zx-i2s.c b/sound/soc/zte/zx-i2s.c
index ed7a56d..2afac69 100644
--- a/sound/soc/zte/zx-i2s.c
+++ b/sound/soc/zte/zx-i2s.c
@@ -95,12 +95,13 @@
struct zx_i2s_info {
struct snd_dmaengine_dai_dma_data dma_playback;
struct snd_dmaengine_dai_dma_data dma_capture;
- struct clk *dai_clk;
+ struct clk *dai_wclk, *dai_pclk;
void __iomem*reg_base;
int master;
resource_size_t mapbase;
};
+
static void zx_i2s_tx_en(void __iomem *base, bool on)
{
unsigned long val;
@@ -274,9 +275,14 @@ static int zx_i2s_hw_params(struct snd_pcm_substream
*substream,
val |= ZX_I2S_TIMING_CHN(ch_num);
writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
- if (i2s->master)
- ret = clk_set_rate(i2s->dai_clk,
- params_rate(params) * ch_num * CLK_RAT);
+ if (i2s->master) {
+ unsigned long rate = params_rate(params) * ch_num * CLK_RAT;
+
+ ret = clk_set_rate(i2s->dai_wclk, rate);
+ if (!ret && i2s->dai_pclk)
+ ret = clk_set_rate(i2s->dai_pclk, rate);
+ }
+
return ret;
}
@@ -328,8 +334,19 @@ static int zx_i2s_startup(struct snd_pcm_substream
*substream,
struct snd_soc_dai *dai)
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
+ int ret;
+
+ ret = clk_prepare_enable(zx_i2s->dai_wclk);
+ if (ret)
+ return ret;
- return clk_prepare_enable(zx_i2s->dai_clk);
+ ret = clk_prepare_enable(zx_i2s->dai_pclk);
+ if (ret) {
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ return ret;
+ }
+
+ return ret;
}
static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
@@ -337,7 +354,8 @@ static void zx_i2s_shutdown(struct snd_pcm_substream
*substream,
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
- clk_disable_unprepare(zx_i2s->dai_clk);
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ clk_disable_unprepare(zx_i2s->dai_pclk);
}
static struct snd_soc_dai_ops zx_i2s_dai_ops = {
@@ -381,10 +399,16 @@ static int zx_i2s_probe(struct platform_device *pdev)
if (!zx_i2s)
return -ENOMEM;
- zx_i2s->dai_clk = devm_clk_get(>dev, "tx");
- if (IS_ERR(zx_i2s->dai_clk)) {
- dev_err(>dev, "Fail to get clk\n");
- return PTR_ERR(zx_i2s->dai_clk);
+ zx_i2s->dai_wclk = devm_clk_get(>dev, "tx");
+ if (IS_ERR(zx_i2s->dai_wclk)) {
+ dev_err(>dev, "Fail to get wclk\n");
+ return PTR_ERR(zx_i2s->dai_wclk);
+ }
+
+ zx_i2s->dai_pclk = devm_clk_get(>dev, "pclk");
+ if (IS_ERR(zx_i2s->dai_pclk)) {
+ dev_info(>dev, "have no pclk\n");
+ zx_i2s->dai_pclk = NULL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -414,6 +438,7 @@ static int zx_i2s_probe(struct platform_device *pdev)
static const struct of_device_id zx_i2s_dt_ids[] = {
{ .compatible = "zte,zx296702-i2s", },
+ { .compatible = "zte,zx296718-i2s", },
{}
};
MODULE_DEVICE_TABLE(of, zx_i2s_dt_ids);
--
2.7.4
[PATCH v2 2/3] dt: ASoC: zx-i2s: Document for the ZTE zx296718 I2S controller
This patch documents the devicetree for the ZTE's zx296718 I2S audio controller. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- Documentation/devicetree/bindings/sound/zte,zx-i2s.txt | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt index 7e5aa6f..c405561 100644 --- a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt +++ b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt @@ -1,10 +1,12 @@ ZTE ZX296702 I2S controller Required properties: - - compatible : Must be "zte,zx296702-i2s" + - compatible : Should include one of the following strings: + "zte,zx296702-i2s","zte,zx296718-i2s". - reg : Must contain I2S core's registers location and length - clocks : Pairs of phandle and specifier referencing the controller's clocks. - - clock-names: "tx" for the clock to the I2S interface. + - clock-names: "tx" for the wclk, "pclk" for the pclk to the I2S interface. + must contain pclk for zx296718 SoC. - dmas: Pairs of phandle and specifier for the DMA channel that is used by the core. The core expects two dma channels for transmit. - dma-names : Must be "tx" and "rx" -- 2.7.4
[PATCH v2 2/3] dt: ASoC: zx-i2s: Document for the ZTE zx296718 I2S controller
This patch documents the devicetree for the ZTE's zx296718 I2S audio controller. Signed-off-by: Baoyou Xie --- Documentation/devicetree/bindings/sound/zte,zx-i2s.txt | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt index 7e5aa6f..c405561 100644 --- a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt +++ b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt @@ -1,10 +1,12 @@ ZTE ZX296702 I2S controller Required properties: - - compatible : Must be "zte,zx296702-i2s" + - compatible : Should include one of the following strings: + "zte,zx296702-i2s","zte,zx296718-i2s". - reg : Must contain I2S core's registers location and length - clocks : Pairs of phandle and specifier referencing the controller's clocks. - - clock-names: "tx" for the clock to the I2S interface. + - clock-names: "tx" for the wclk, "pclk" for the pclk to the I2S interface. + must contain pclk for zx296718 SoC. - dmas: Pairs of phandle and specifier for the DMA channel that is used by the core. The core expects two dma channels for transmit. - dma-names : Must be "tx" and "rx" -- 2.7.4
[PATCH v2 1/3] clk: zte: add i2s clocks for zx296718
The i2s related clock support is missing from the existing zx296718
clock driver. This patch adds it, so that the upstream ZX I2S driver
can work out.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
drivers/clk/zte/clk-zx296718.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index ad5d1df..f106d40 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -941,6 +941,10 @@ static struct zx_clk_gate audio_gate_clk[] = {
GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div",
AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_TDM_WCLK, "tdm_wclk", "tdm_wclk_div", AUDIO_TDM_CLK, 17,
CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_TS_PCLK, "tempsensor_pclk", "clk49m5", AUDIO_TS_CLK, 1, 0,
0),
+ GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0),
};
static struct clk_hw_onecell_data audio_hw_onecell_data = {
--
2.7.4
[PATCH v2 1/3] clk: zte: add i2s clocks for zx296718
The i2s related clock support is missing from the existing zx296718
clock driver. This patch adds it, so that the upstream ZX I2S driver
can work out.
Signed-off-by: Baoyou Xie
---
drivers/clk/zte/clk-zx296718.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index ad5d1df..f106d40 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -941,6 +941,10 @@ static struct zx_clk_gate audio_gate_clk[] = {
GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div",
AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_TDM_WCLK, "tdm_wclk", "tdm_wclk_div", AUDIO_TDM_CLK, 17,
CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_TS_PCLK, "tempsensor_pclk", "clk49m5", AUDIO_TS_CLK, 1, 0,
0),
+ GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0),
};
static struct clk_hw_onecell_data audio_hw_onecell_data = {
--
2.7.4
[PATCH v9 3/3] thermal: zx2967: add thermal driver for ZTE's zx2967 family
This patch adds thermal driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
drivers/thermal/Kconfig | 8 ++
drivers/thermal/Makefile | 1 +
drivers/thermal/zx2967_thermal.c | 258 +++
3 files changed, 267 insertions(+)
create mode 100644 drivers/thermal/zx2967_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 18f2de6..f64bd50 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -444,4 +444,12 @@ config BCM2835_THERMAL
help
Support for thermal sensors on Broadcom bcm2835 SoCs.
+config ZX2967_THERMAL
+ tristate "Thermal sensors on zx2967 SoC"
+ depends on ARCH_ZX || COMPILE_TEST
+ help
+ Enable the zx2967 thermal sensors driver, which supports
+ the primitive temperature sensor embedded in zx2967 SoCs.
+ This sensor generates the real time die temperature.
+
endif
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 677c6d9..c00c05e 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o
obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o
obj-$(CONFIG_BCM2835_THERMAL) += bcm2835_thermal.o
+obj-$(CONFIG_ZX2967_THERMAL) += zx2967_thermal.o
diff --git a/drivers/thermal/zx2967_thermal.c b/drivers/thermal/zx2967_thermal.c
new file mode 100644
index 000..a5670ad
--- /dev/null
+++ b/drivers/thermal/zx2967_thermal.c
@@ -0,0 +1,258 @@
+/*
+ * ZTE's zx2967 family thermal sensor driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie <baoyou@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Power Mode: 0->low 1->high */
+#define ZX2967_THERMAL_POWER_MODE 0
+#define ZX2967_POWER_MODE_LOW 0
+#define ZX2967_POWER_MODE_HIGH 1
+
+/* DCF Control Register */
+#define ZX2967_THERMAL_DCF 0x4
+#define ZX2967_DCF_EN BIT(1)
+#define ZX2967_DCF_FREEZE BIT(0)
+
+/* Selection Register */
+#define ZX2967_THERMAL_SEL 0x8
+
+/* Control Register */
+#define ZX2967_THERMAL_CTRL0x10
+
+#define ZX2967_THERMAL_READY BIT(12)
+#define ZX2967_THERMAL_TEMP_MASK GENMASK(11, 0)
+#define ZX2967_THERMAL_ID_MASK 0x18
+#define ZX2967_THERMAL_ID 0x10
+
+#define ZX2967_GET_TEMP_TIMEOUT_US (100 * 1024)
+
+/**
+ * struct zx2967_thermal_priv - zx2967 thermal sensor private structure
+ * @tzd: struct thermal_zone_device where the sensor is registered
+ * @lock: prevents read sensor in parallel
+ * @clk_topcrm: topcrm clk structure
+ * @clk_apb: apb clk structure
+ * @regs: pointer to base address of the thermal sensor
+ */
+
+struct zx2967_thermal_priv {
+ struct thermal_zone_device *tzd;
+ struct mutexlock;
+ struct clk *clk_topcrm;
+ struct clk *clk_apb;
+ void __iomem*regs;
+ struct device *dev;
+};
+
+static int zx2967_thermal_get_temp(void *data, int *temp)
+{
+ void __iomem *regs;
+ struct zx2967_thermal_priv *priv = data;
+ u32 val;
+ int ret;
+
+ if (!priv->tzd)
+ return -EAGAIN;
+
+ regs = priv->regs;
+ mutex_lock(>lock);
+ writel_relaxed(ZX2967_POWER_MODE_LOW,
+ regs + ZX2967_THERMAL_POWER_MODE);
+ writel_relaxed(ZX2967_DCF_EN, regs + ZX2967_THERMAL_DCF);
+
+ val = readl_relaxed(regs + ZX2967_THERMAL_SEL);
+ val &= ~ZX2967_THERMAL_ID_MASK;
+ val |= ZX2967_THERMAL_ID;
+ writel_relaxed(val, regs + ZX2967_THERMAL_SEL);
+
+ /*
+* Must wait for a while, surely it's a bit odd.
+* otherwise temperature value we got has a few deviation, even if
+* the THERMAL_READY bit is set.
+*/
+ usleep_range(100, 300);
+ ret = readx_poll_timeout(readl, regs + ZX2967_THERMAL_CTRL,
+val, val & ZX2967_THERMAL_READY, 300,
+ZX2967_GET_TEMP_TIMEOUT_US);
+ if (ret) {
+ dev_err(priv->dev, "Thermal sensor data timeout\n");
+ goto unlock;
+ }
+
+ writel_relaxed(ZX2967_DCF_FREEZE | ZX2967_DCF_EN,
+ regs + ZX2967_THERMAL_DCF);
+ val = readl_relaxed(regs + ZX2967_THERMAL_CTRL)
+& ZX2967_THERMAL_TEMP_MASK;
+ writel_relaxed(ZX2967_POWER_MODE_HIGH,
+ regs + ZX2967_THERMAL_POWER_MODE);
+
+ /*
+* Calculate temperature
+* In dts, slope is multiplied by 1000.
+*/
+ *temp
[PATCH v9 2/3] MAINTAINERS: add zx2967 thermal drivers to ARM ZTE architecture
Add the zx2967 thermal drivers as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4e81e2b..2a84440 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1990,11 +1990,13 @@ F: drivers/clk/zte/ F: drivers/i2c/busses/i2c-zx2967.c F: drivers/reset/reset-zx2967.c F: drivers/soc/zte/ +F: drivers/thermal/zx* F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt F: Documentation/devicetree/bindings/soc/zte/ +F: Documentation/devicetree/bindings/thermal/zx* F: include/dt-bindings/soc/zx*.h ARM/ZYNQ ARCHITECTURE -- 2.7.4
[PATCH v9 3/3] thermal: zx2967: add thermal driver for ZTE's zx2967 family
This patch adds thermal driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie
---
drivers/thermal/Kconfig | 8 ++
drivers/thermal/Makefile | 1 +
drivers/thermal/zx2967_thermal.c | 258 +++
3 files changed, 267 insertions(+)
create mode 100644 drivers/thermal/zx2967_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 18f2de6..f64bd50 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -444,4 +444,12 @@ config BCM2835_THERMAL
help
Support for thermal sensors on Broadcom bcm2835 SoCs.
+config ZX2967_THERMAL
+ tristate "Thermal sensors on zx2967 SoC"
+ depends on ARCH_ZX || COMPILE_TEST
+ help
+ Enable the zx2967 thermal sensors driver, which supports
+ the primitive temperature sensor embedded in zx2967 SoCs.
+ This sensor generates the real time die temperature.
+
endif
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 677c6d9..c00c05e 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o
obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o
obj-$(CONFIG_BCM2835_THERMAL) += bcm2835_thermal.o
+obj-$(CONFIG_ZX2967_THERMAL) += zx2967_thermal.o
diff --git a/drivers/thermal/zx2967_thermal.c b/drivers/thermal/zx2967_thermal.c
new file mode 100644
index 000..a5670ad
--- /dev/null
+++ b/drivers/thermal/zx2967_thermal.c
@@ -0,0 +1,258 @@
+/*
+ * ZTE's zx2967 family thermal sensor driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Power Mode: 0->low 1->high */
+#define ZX2967_THERMAL_POWER_MODE 0
+#define ZX2967_POWER_MODE_LOW 0
+#define ZX2967_POWER_MODE_HIGH 1
+
+/* DCF Control Register */
+#define ZX2967_THERMAL_DCF 0x4
+#define ZX2967_DCF_EN BIT(1)
+#define ZX2967_DCF_FREEZE BIT(0)
+
+/* Selection Register */
+#define ZX2967_THERMAL_SEL 0x8
+
+/* Control Register */
+#define ZX2967_THERMAL_CTRL0x10
+
+#define ZX2967_THERMAL_READY BIT(12)
+#define ZX2967_THERMAL_TEMP_MASK GENMASK(11, 0)
+#define ZX2967_THERMAL_ID_MASK 0x18
+#define ZX2967_THERMAL_ID 0x10
+
+#define ZX2967_GET_TEMP_TIMEOUT_US (100 * 1024)
+
+/**
+ * struct zx2967_thermal_priv - zx2967 thermal sensor private structure
+ * @tzd: struct thermal_zone_device where the sensor is registered
+ * @lock: prevents read sensor in parallel
+ * @clk_topcrm: topcrm clk structure
+ * @clk_apb: apb clk structure
+ * @regs: pointer to base address of the thermal sensor
+ */
+
+struct zx2967_thermal_priv {
+ struct thermal_zone_device *tzd;
+ struct mutexlock;
+ struct clk *clk_topcrm;
+ struct clk *clk_apb;
+ void __iomem*regs;
+ struct device *dev;
+};
+
+static int zx2967_thermal_get_temp(void *data, int *temp)
+{
+ void __iomem *regs;
+ struct zx2967_thermal_priv *priv = data;
+ u32 val;
+ int ret;
+
+ if (!priv->tzd)
+ return -EAGAIN;
+
+ regs = priv->regs;
+ mutex_lock(>lock);
+ writel_relaxed(ZX2967_POWER_MODE_LOW,
+ regs + ZX2967_THERMAL_POWER_MODE);
+ writel_relaxed(ZX2967_DCF_EN, regs + ZX2967_THERMAL_DCF);
+
+ val = readl_relaxed(regs + ZX2967_THERMAL_SEL);
+ val &= ~ZX2967_THERMAL_ID_MASK;
+ val |= ZX2967_THERMAL_ID;
+ writel_relaxed(val, regs + ZX2967_THERMAL_SEL);
+
+ /*
+* Must wait for a while, surely it's a bit odd.
+* otherwise temperature value we got has a few deviation, even if
+* the THERMAL_READY bit is set.
+*/
+ usleep_range(100, 300);
+ ret = readx_poll_timeout(readl, regs + ZX2967_THERMAL_CTRL,
+val, val & ZX2967_THERMAL_READY, 300,
+ZX2967_GET_TEMP_TIMEOUT_US);
+ if (ret) {
+ dev_err(priv->dev, "Thermal sensor data timeout\n");
+ goto unlock;
+ }
+
+ writel_relaxed(ZX2967_DCF_FREEZE | ZX2967_DCF_EN,
+ regs + ZX2967_THERMAL_DCF);
+ val = readl_relaxed(regs + ZX2967_THERMAL_CTRL)
+& ZX2967_THERMAL_TEMP_MASK;
+ writel_relaxed(ZX2967_POWER_MODE_HIGH,
+ regs + ZX2967_THERMAL_POWER_MODE);
+
+ /*
+* Calculate temperature
+* In dts, slope is multiplied by 1000.
+*/
+ *temp = DIV_ROUND_CLOSEST(((s32)val + priv->tzd->tzp->offset) * 10
[PATCH v9 2/3] MAINTAINERS: add zx2967 thermal drivers to ARM ZTE architecture
Add the zx2967 thermal drivers as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4e81e2b..2a84440 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1990,11 +1990,13 @@ F: drivers/clk/zte/ F: drivers/i2c/busses/i2c-zx2967.c F: drivers/reset/reset-zx2967.c F: drivers/soc/zte/ +F: drivers/thermal/zx* F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt F: Documentation/devicetree/bindings/soc/zte/ +F: Documentation/devicetree/bindings/thermal/zx* F: include/dt-bindings/soc/zx*.h ARM/ZYNQ ARCHITECTURE -- 2.7.4
[PATCH v9 1/3] dt: bindings: add documentation for zx2967 family thermal sensor
This patch adds dt-binding documentation for zx2967 family thermal sensor.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Acked-by: Rob Herring <r...@kernel.org>
Reviewed-by: Shawn Guo <shawn...@kernel.org>
---
.../devicetree/bindings/thermal/zx2967-thermal.txt | 116 +
1 file changed, 116 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
diff --git a/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
new file mode 100644
index 000..0810644
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
@@ -0,0 +1,116 @@
+* ZTE zx2967 family Thermal
+
+Required Properties:
+- compatible: should be one of the following.
+* zte,zx296718-thermal
+- reg: physical base address of the controller and length of memory mapped
+region.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- clock-names: "topcrm" for the topcrm clock.
+ "apb" for the apb clock.
+- #thermal-sensor-cells: must be 0.
+
+Please note: slope coefficient defined in thermal-zones section need to be
+multiplied by 1000.
+
+Example for tempsensor:
+
+ tempsensor: tempsensor@148a000 {
+ compatible = "zte,zx296718-thermal";
+ reg = <0x0148a000 0x20>;
+ clocks = < TEMPSENSOR_GATE>, < AUDIO_TS_PCLK>;
+ clock-names = "topcrm", "apb";
+ #thermal-sensor-cells = <0>;
+ };
+
+Example for cooling device:
+
+ cooling_dev: cooling_dev {
+ cluster0_cooling_dev: cluster0-cooling-dev {
+ #cooling-cells = <2>;
+ cpumask = <0xf>;
+ capacitance = <1500>;
+ };
+
+ cluster1_cooling_dev: cluster1-cooling-dev {
+ #cooling-cells = <2>;
+ cpumask = <0x30>;
+ capacitance = <2000>;
+ };
+ };
+
+Example for thermal zones:
+
+ thermal-zones {
+ zx296718_thermal: zx296718_thermal {
+ polling-delay-passive = <500>;
+ polling-delay = <1000>;
+ sustainable-power = <6500>;
+
+ thermal-sensors = < 0>;
+ /*
+* slope need to be multiplied by 1000.
+*/
+ coefficients = <1951 (-922)>;
+
+ trips {
+ trip0: switch_on_temperature {
+ temperature = <9>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip1: desired_temperature {
+ temperature = <10>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit: critical_temperature {
+ temperature = <11>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <>;
+ cooling-device = < 2 5>;
+ };
+
+ map1 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map2 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map3 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map4 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ contribution = <9000>;
+ };
+
+ map5 {
+ trip = <>;
+ cooling
[PATCH v9 1/3] dt: bindings: add documentation for zx2967 family thermal sensor
This patch adds dt-binding documentation for zx2967 family thermal sensor.
Signed-off-by: Baoyou Xie
Acked-by: Rob Herring
Reviewed-by: Shawn Guo
---
.../devicetree/bindings/thermal/zx2967-thermal.txt | 116 +
1 file changed, 116 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
diff --git a/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
new file mode 100644
index 000..0810644
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
@@ -0,0 +1,116 @@
+* ZTE zx2967 family Thermal
+
+Required Properties:
+- compatible: should be one of the following.
+* zte,zx296718-thermal
+- reg: physical base address of the controller and length of memory mapped
+region.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- clock-names: "topcrm" for the topcrm clock.
+ "apb" for the apb clock.
+- #thermal-sensor-cells: must be 0.
+
+Please note: slope coefficient defined in thermal-zones section need to be
+multiplied by 1000.
+
+Example for tempsensor:
+
+ tempsensor: tempsensor@148a000 {
+ compatible = "zte,zx296718-thermal";
+ reg = <0x0148a000 0x20>;
+ clocks = < TEMPSENSOR_GATE>, < AUDIO_TS_PCLK>;
+ clock-names = "topcrm", "apb";
+ #thermal-sensor-cells = <0>;
+ };
+
+Example for cooling device:
+
+ cooling_dev: cooling_dev {
+ cluster0_cooling_dev: cluster0-cooling-dev {
+ #cooling-cells = <2>;
+ cpumask = <0xf>;
+ capacitance = <1500>;
+ };
+
+ cluster1_cooling_dev: cluster1-cooling-dev {
+ #cooling-cells = <2>;
+ cpumask = <0x30>;
+ capacitance = <2000>;
+ };
+ };
+
+Example for thermal zones:
+
+ thermal-zones {
+ zx296718_thermal: zx296718_thermal {
+ polling-delay-passive = <500>;
+ polling-delay = <1000>;
+ sustainable-power = <6500>;
+
+ thermal-sensors = < 0>;
+ /*
+* slope need to be multiplied by 1000.
+*/
+ coefficients = <1951 (-922)>;
+
+ trips {
+ trip0: switch_on_temperature {
+ temperature = <9>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip1: desired_temperature {
+ temperature = <10>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit: critical_temperature {
+ temperature = <11>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <>;
+ cooling-device = < 2 5>;
+ };
+
+ map1 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map2 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map3 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map4 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ contribution = <9000>;
+ };
+
+ map5 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ cont
[PATCH v1 3/3] ASoC: zx-i2s: support zx296718 SoC for ZTE's i2s controller driver
This patch adds zx296718 SoC support for ZTE's i2s controller driver.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
sound/soc/zte/zx-i2s.c | 49 -
1 file changed, 40 insertions(+), 9 deletions(-)
diff --git a/sound/soc/zte/zx-i2s.c b/sound/soc/zte/zx-i2s.c
index ed7a56d..68d590be 100644
--- a/sound/soc/zte/zx-i2s.c
+++ b/sound/soc/zte/zx-i2s.c
@@ -95,12 +95,13 @@
struct zx_i2s_info {
struct snd_dmaengine_dai_dma_data dma_playback;
struct snd_dmaengine_dai_dma_data dma_capture;
- struct clk *dai_clk;
+ struct clk *dai_wclk, *dai_pclk;
void __iomem*reg_base;
int master;
resource_size_t mapbase;
};
+
static void zx_i2s_tx_en(void __iomem *base, bool on)
{
unsigned long val;
@@ -218,6 +219,17 @@ static int zx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
return 0;
}
+static void zx_i2s_set_clk(struct zx_i2s_info *i2s,
+ unsigned int ch_num, unsigned int sample_rate)
+{
+ unsigned long val = sample_rate * ch_num * CLK_RAT;
+
+ clk_set_rate(i2s->dai_wclk, val);
+
+ if (i2s->dai_pclk)
+ clk_set_rate(i2s->dai_pclk, val);
+}
+
static int zx_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *socdai)
@@ -275,8 +287,8 @@ static int zx_i2s_hw_params(struct snd_pcm_substream
*substream,
writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
if (i2s->master)
- ret = clk_set_rate(i2s->dai_clk,
- params_rate(params) * ch_num * CLK_RAT);
+ zx_i2s_set_clk(i2s, ch_num, params_rate(params));
+
return ret;
}
@@ -328,8 +340,19 @@ static int zx_i2s_startup(struct snd_pcm_substream
*substream,
struct snd_soc_dai *dai)
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
+ int ret;
+
+ ret = clk_prepare_enable(zx_i2s->dai_wclk);
+ if (ret)
+ return ret;
- return clk_prepare_enable(zx_i2s->dai_clk);
+ ret = clk_prepare_enable(zx_i2s->dai_pclk);
+ if (ret) {
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ return ret;
+ }
+
+ return ret;
}
static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
@@ -337,7 +360,8 @@ static void zx_i2s_shutdown(struct snd_pcm_substream
*substream,
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
- clk_disable_unprepare(zx_i2s->dai_clk);
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ clk_disable_unprepare(zx_i2s->dai_pclk);
}
static struct snd_soc_dai_ops zx_i2s_dai_ops = {
@@ -381,10 +405,16 @@ static int zx_i2s_probe(struct platform_device *pdev)
if (!zx_i2s)
return -ENOMEM;
- zx_i2s->dai_clk = devm_clk_get(>dev, "tx");
- if (IS_ERR(zx_i2s->dai_clk)) {
- dev_err(>dev, "Fail to get clk\n");
- return PTR_ERR(zx_i2s->dai_clk);
+ zx_i2s->dai_wclk = devm_clk_get(>dev, "tx");
+ if (IS_ERR(zx_i2s->dai_wclk)) {
+ dev_err(>dev, "Fail to get wclk\n");
+ return PTR_ERR(zx_i2s->dai_wclk);
+ }
+
+ zx_i2s->dai_pclk = devm_clk_get(>dev, "pclk");
+ if (IS_ERR(zx_i2s->dai_pclk)) {
+ dev_info(>dev, "have no pclk\n");
+ zx_i2s->dai_pclk = NULL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -414,6 +444,7 @@ static int zx_i2s_probe(struct platform_device *pdev)
static const struct of_device_id zx_i2s_dt_ids[] = {
{ .compatible = "zte,zx296702-i2s", },
+ { .compatible = "zte,zx296718-i2s", },
{}
};
MODULE_DEVICE_TABLE(of, zx_i2s_dt_ids);
--
2.7.4
[PATCH v1 3/3] ASoC: zx-i2s: support zx296718 SoC for ZTE's i2s controller driver
This patch adds zx296718 SoC support for ZTE's i2s controller driver.
Signed-off-by: Baoyou Xie
---
sound/soc/zte/zx-i2s.c | 49 -
1 file changed, 40 insertions(+), 9 deletions(-)
diff --git a/sound/soc/zte/zx-i2s.c b/sound/soc/zte/zx-i2s.c
index ed7a56d..68d590be 100644
--- a/sound/soc/zte/zx-i2s.c
+++ b/sound/soc/zte/zx-i2s.c
@@ -95,12 +95,13 @@
struct zx_i2s_info {
struct snd_dmaengine_dai_dma_data dma_playback;
struct snd_dmaengine_dai_dma_data dma_capture;
- struct clk *dai_clk;
+ struct clk *dai_wclk, *dai_pclk;
void __iomem*reg_base;
int master;
resource_size_t mapbase;
};
+
static void zx_i2s_tx_en(void __iomem *base, bool on)
{
unsigned long val;
@@ -218,6 +219,17 @@ static int zx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
return 0;
}
+static void zx_i2s_set_clk(struct zx_i2s_info *i2s,
+ unsigned int ch_num, unsigned int sample_rate)
+{
+ unsigned long val = sample_rate * ch_num * CLK_RAT;
+
+ clk_set_rate(i2s->dai_wclk, val);
+
+ if (i2s->dai_pclk)
+ clk_set_rate(i2s->dai_pclk, val);
+}
+
static int zx_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *socdai)
@@ -275,8 +287,8 @@ static int zx_i2s_hw_params(struct snd_pcm_substream
*substream,
writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
if (i2s->master)
- ret = clk_set_rate(i2s->dai_clk,
- params_rate(params) * ch_num * CLK_RAT);
+ zx_i2s_set_clk(i2s, ch_num, params_rate(params));
+
return ret;
}
@@ -328,8 +340,19 @@ static int zx_i2s_startup(struct snd_pcm_substream
*substream,
struct snd_soc_dai *dai)
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
+ int ret;
+
+ ret = clk_prepare_enable(zx_i2s->dai_wclk);
+ if (ret)
+ return ret;
- return clk_prepare_enable(zx_i2s->dai_clk);
+ ret = clk_prepare_enable(zx_i2s->dai_pclk);
+ if (ret) {
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ return ret;
+ }
+
+ return ret;
}
static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
@@ -337,7 +360,8 @@ static void zx_i2s_shutdown(struct snd_pcm_substream
*substream,
{
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
- clk_disable_unprepare(zx_i2s->dai_clk);
+ clk_disable_unprepare(zx_i2s->dai_wclk);
+ clk_disable_unprepare(zx_i2s->dai_pclk);
}
static struct snd_soc_dai_ops zx_i2s_dai_ops = {
@@ -381,10 +405,16 @@ static int zx_i2s_probe(struct platform_device *pdev)
if (!zx_i2s)
return -ENOMEM;
- zx_i2s->dai_clk = devm_clk_get(>dev, "tx");
- if (IS_ERR(zx_i2s->dai_clk)) {
- dev_err(>dev, "Fail to get clk\n");
- return PTR_ERR(zx_i2s->dai_clk);
+ zx_i2s->dai_wclk = devm_clk_get(>dev, "tx");
+ if (IS_ERR(zx_i2s->dai_wclk)) {
+ dev_err(>dev, "Fail to get wclk\n");
+ return PTR_ERR(zx_i2s->dai_wclk);
+ }
+
+ zx_i2s->dai_pclk = devm_clk_get(>dev, "pclk");
+ if (IS_ERR(zx_i2s->dai_pclk)) {
+ dev_info(>dev, "have no pclk\n");
+ zx_i2s->dai_pclk = NULL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -414,6 +444,7 @@ static int zx_i2s_probe(struct platform_device *pdev)
static const struct of_device_id zx_i2s_dt_ids[] = {
{ .compatible = "zte,zx296702-i2s", },
+ { .compatible = "zte,zx296718-i2s", },
{}
};
MODULE_DEVICE_TABLE(of, zx_i2s_dt_ids);
--
2.7.4
[PATCH v1 2/3] dt: Document for the ZTE zx296718 I2S controller
This patch documents the devicetree for the ZTE's zx296718 I2S audio controller. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- Documentation/devicetree/bindings/sound/zte,zx-i2s.txt | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt index 7e5aa6f..c405561 100644 --- a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt +++ b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt @@ -1,10 +1,12 @@ ZTE ZX296702 I2S controller Required properties: - - compatible : Must be "zte,zx296702-i2s" + - compatible : Should include one of the following strings: + "zte,zx296702-i2s","zte,zx296718-i2s". - reg : Must contain I2S core's registers location and length - clocks : Pairs of phandle and specifier referencing the controller's clocks. - - clock-names: "tx" for the clock to the I2S interface. + - clock-names: "tx" for the wclk, "pclk" for the pclk to the I2S interface. + must contain pclk for zx296718 SoC. - dmas: Pairs of phandle and specifier for the DMA channel that is used by the core. The core expects two dma channels for transmit. - dma-names : Must be "tx" and "rx" -- 2.7.4
[PATCH v1 2/3] dt: Document for the ZTE zx296718 I2S controller
This patch documents the devicetree for the ZTE's zx296718 I2S audio controller. Signed-off-by: Baoyou Xie --- Documentation/devicetree/bindings/sound/zte,zx-i2s.txt | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt index 7e5aa6f..c405561 100644 --- a/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt +++ b/Documentation/devicetree/bindings/sound/zte,zx-i2s.txt @@ -1,10 +1,12 @@ ZTE ZX296702 I2S controller Required properties: - - compatible : Must be "zte,zx296702-i2s" + - compatible : Should include one of the following strings: + "zte,zx296702-i2s","zte,zx296718-i2s". - reg : Must contain I2S core's registers location and length - clocks : Pairs of phandle and specifier referencing the controller's clocks. - - clock-names: "tx" for the clock to the I2S interface. + - clock-names: "tx" for the wclk, "pclk" for the pclk to the I2S interface. + must contain pclk for zx296718 SoC. - dmas: Pairs of phandle and specifier for the DMA channel that is used by the core. The core expects two dma channels for transmit. - dma-names : Must be "tx" and "rx" -- 2.7.4
[PATCH v1 1/3] clk: zte: add i2s clocks for zx296718
The i2s related clock support is missing from the existing zx296718
clock driver. This patch adds it, so that the upstream ZX I2S driver
can work out.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
drivers/clk/zte/clk-zx296718.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index ad5d1df..f106d40 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -941,6 +941,10 @@ static struct zx_clk_gate audio_gate_clk[] = {
GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div",
AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_TDM_WCLK, "tdm_wclk", "tdm_wclk_div", AUDIO_TDM_CLK, 17,
CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_TS_PCLK, "tempsensor_pclk", "clk49m5", AUDIO_TS_CLK, 1, 0,
0),
+ GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0),
};
static struct clk_hw_onecell_data audio_hw_onecell_data = {
--
2.7.4
[PATCH v1 1/3] clk: zte: add i2s clocks for zx296718
The i2s related clock support is missing from the existing zx296718
clock driver. This patch adds it, so that the upstream ZX I2S driver
can work out.
Signed-off-by: Baoyou Xie
---
drivers/clk/zte/clk-zx296718.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index ad5d1df..f106d40 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -941,6 +941,10 @@ static struct zx_clk_gate audio_gate_clk[] = {
GATE(AUDIO_SPDIF1_WCLK, "spdif1_wclk", "spdif1_wclk_div",
AUDIO_SPDIF1_CLK, 9, CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_TDM_WCLK, "tdm_wclk", "tdm_wclk_div", AUDIO_TDM_CLK, 17,
CLK_SET_RATE_PARENT, 0),
GATE(AUDIO_TS_PCLK, "tempsensor_pclk", "clk49m5", AUDIO_TS_CLK, 1, 0,
0),
+ GATE(AUDIO_I2S0_PCLK, "i2s0_pclk", "clk49m5", AUDIO_I2S0_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S1_PCLK, "i2s1_pclk", "clk49m5", AUDIO_I2S1_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S2_PCLK, "i2s2_pclk", "clk49m5", AUDIO_I2S2_CLK, 8, 0, 0),
+ GATE(AUDIO_I2S3_PCLK, "i2s3_pclk", "clk49m5", AUDIO_I2S3_CLK, 8, 0, 0),
};
static struct clk_hw_onecell_data audio_hw_onecell_data = {
--
2.7.4
[PATCH v4 3/3] i2c: zx2967: add i2c controller driver for ZTE's zx2967 family
This patch adds i2c controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
drivers/i2c/busses/Kconfig | 9 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-zx2967.c | 688
3 files changed, 698 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-zx2967.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e4a603e..d983e36 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1246,4 +1246,13 @@ config I2C_OPAL
This driver can also be built as a module. If so, the module will be
called as i2c-opal.
+config I2C_ZX2967
+ tristate "ZTE zx2967 I2C support"
+ depends on ARCH_ZX
+ default y
+ help
+ Selecting this option will add ZX2967 I2C driver.
+ This driver can also be built as a module. If so, the module will be
+ called i2c-zx2967.
+
endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index beb4809..16b2901 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_XILINX)+= i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
+obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
diff --git a/drivers/i2c/busses/i2c-zx2967.c b/drivers/i2c/busses/i2c-zx2967.c
new file mode 100644
index 000..7b3471a
--- /dev/null
+++ b/drivers/i2c/busses/i2c-zx2967.c
@@ -0,0 +1,688 @@
+/*
+ * ZTE's zx2967 family i2c bus controller driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie <baoyou@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_CMD0x04
+#define REG_DEVADDR_H 0x0C
+#define REG_DEVADDR_L 0x10
+#define REG_CLK_DIV_FS 0x14
+#define REG_CLK_DIV_HS 0x18
+#define REG_WRCONF 0x1C
+#define REG_RDCONF 0x20
+#define REG_DATA 0x24
+#define REG_STAT 0x28
+
+#define I2C_STOP 0
+#define I2C_MASTER BIT(0)
+#define I2C_ADDR_MODE_TEN BIT(1)
+#define I2C_IRQ_MSK_ENABLE BIT(3)
+#define I2C_RW_READBIT(4)
+#define I2C_CMB_RW_EN BIT(5)
+#define I2C_START BIT(6)
+#define I2C_ADDR_MODE_TEN BIT(1)
+
+#define I2C_WFIFO_RESETBIT(7)
+#define I2C_RFIFO_RESETBIT(7)
+
+#define I2C_IRQ_ACK_CLEAR BIT(7)
+#define I2C_INT_MASK GENMASK(6, 0)
+
+#define I2C_TRANS_DONE BIT(0)
+#define I2C_ERROR_DEVICE BIT(1)
+#define I2C_ERROR_DATA BIT(2)
+#define I2C_ERROR_MASK GENMASK(2, 1)
+
+#define I2C_SR_BUSYBIT(6)
+
+#define I2C_SR_EDEVICE BIT(1)
+#define I2C_SR_EDATA BIT(2)
+
+#define I2C_FIFO_MAX 16
+
+#define I2C_TIMEOUTmsecs_to_jiffies(1000)
+
+struct zx2967_i2c_info {
+ spinlock_t lock;
+ struct device *dev;
+ struct i2c_adapter adap;
+ struct clk *clk;
+ struct completion complete;
+ u32 clk_freq;
+ void __iomem*reg_base;
+ size_t residue;
+ int irq;
+ int msg_rd;
+ u8 *buf;
+ u8 access_cnt;
+ boolis_suspended;
+};
+
+static void zx2967_i2c_writel(struct zx2967_i2c_info *zx_i2c,
+ u32 val, unsigned long reg)
+{
+ writel_relaxed(val, zx_i2c->reg_base + reg);
+}
+
+static u32 zx2967_i2c_readl(struct zx2967_i2c_info *zx_i2c, unsigned long reg)
+{
+ return readl_relaxed(zx_i2c->reg_base + reg);
+}
+
+static void zx2967_i2c_writesb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ writesb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_readsb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ readsb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_start_ctrl(struct zx2967_i2c_info *zx_i2c)
+{
+ u32 status;
+ u32 ctl;
+
+ status = zx2967_i2c_readl(zx_i2c, REG_STAT);
+ status |= I2C_IRQ_ACK_CLEAR;
+ zx2967_i2c_writel(zx_i2c, status, REG_STAT);
+
+
[PATCH v4 3/3] i2c: zx2967: add i2c controller driver for ZTE's zx2967 family
This patch adds i2c controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie
---
drivers/i2c/busses/Kconfig | 9 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-zx2967.c | 688
3 files changed, 698 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-zx2967.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e4a603e..d983e36 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1246,4 +1246,13 @@ config I2C_OPAL
This driver can also be built as a module. If so, the module will be
called as i2c-opal.
+config I2C_ZX2967
+ tristate "ZTE zx2967 I2C support"
+ depends on ARCH_ZX
+ default y
+ help
+ Selecting this option will add ZX2967 I2C driver.
+ This driver can also be built as a module. If so, the module will be
+ called i2c-zx2967.
+
endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index beb4809..16b2901 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_XILINX)+= i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
+obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o
diff --git a/drivers/i2c/busses/i2c-zx2967.c b/drivers/i2c/busses/i2c-zx2967.c
new file mode 100644
index 000..7b3471a
--- /dev/null
+++ b/drivers/i2c/busses/i2c-zx2967.c
@@ -0,0 +1,688 @@
+/*
+ * ZTE's zx2967 family i2c bus controller driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_CMD0x04
+#define REG_DEVADDR_H 0x0C
+#define REG_DEVADDR_L 0x10
+#define REG_CLK_DIV_FS 0x14
+#define REG_CLK_DIV_HS 0x18
+#define REG_WRCONF 0x1C
+#define REG_RDCONF 0x20
+#define REG_DATA 0x24
+#define REG_STAT 0x28
+
+#define I2C_STOP 0
+#define I2C_MASTER BIT(0)
+#define I2C_ADDR_MODE_TEN BIT(1)
+#define I2C_IRQ_MSK_ENABLE BIT(3)
+#define I2C_RW_READBIT(4)
+#define I2C_CMB_RW_EN BIT(5)
+#define I2C_START BIT(6)
+#define I2C_ADDR_MODE_TEN BIT(1)
+
+#define I2C_WFIFO_RESETBIT(7)
+#define I2C_RFIFO_RESETBIT(7)
+
+#define I2C_IRQ_ACK_CLEAR BIT(7)
+#define I2C_INT_MASK GENMASK(6, 0)
+
+#define I2C_TRANS_DONE BIT(0)
+#define I2C_ERROR_DEVICE BIT(1)
+#define I2C_ERROR_DATA BIT(2)
+#define I2C_ERROR_MASK GENMASK(2, 1)
+
+#define I2C_SR_BUSYBIT(6)
+
+#define I2C_SR_EDEVICE BIT(1)
+#define I2C_SR_EDATA BIT(2)
+
+#define I2C_FIFO_MAX 16
+
+#define I2C_TIMEOUTmsecs_to_jiffies(1000)
+
+struct zx2967_i2c_info {
+ spinlock_t lock;
+ struct device *dev;
+ struct i2c_adapter adap;
+ struct clk *clk;
+ struct completion complete;
+ u32 clk_freq;
+ void __iomem*reg_base;
+ size_t residue;
+ int irq;
+ int msg_rd;
+ u8 *buf;
+ u8 access_cnt;
+ boolis_suspended;
+};
+
+static void zx2967_i2c_writel(struct zx2967_i2c_info *zx_i2c,
+ u32 val, unsigned long reg)
+{
+ writel_relaxed(val, zx_i2c->reg_base + reg);
+}
+
+static u32 zx2967_i2c_readl(struct zx2967_i2c_info *zx_i2c, unsigned long reg)
+{
+ return readl_relaxed(zx_i2c->reg_base + reg);
+}
+
+static void zx2967_i2c_writesb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ writesb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_readsb(struct zx2967_i2c_info *zx_i2c,
+ void *data, unsigned long reg, int len)
+{
+ readsb(zx_i2c->reg_base + reg, data, len);
+}
+
+static void zx2967_i2c_start_ctrl(struct zx2967_i2c_info *zx_i2c)
+{
+ u32 status;
+ u32 ctl;
+
+ status = zx2967_i2c_readl(zx_i2c, REG_STAT);
+ status |= I2C_IRQ_ACK_CLEAR;
+ zx2967_i2c_writel(zx_i2c, status, REG_STAT);
+
+ ctl = zx2967_i2c_readl(zx_i2c, REG_CMD);
+
[PATCH v4 1/3] dt: bindings: add documentation for zx2967 family i2c controller
This patch adds dt-binding documentation for zx2967 family
i2c controller.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Acked-by: Rob Herring <r...@kernel.org>
---
.../devicetree/bindings/i2c/i2c-zx2967.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
new file mode 100644
index 000..a528374
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
@@ -0,0 +1,24 @@
+ZTE zx2967 I2C controller
+
+Required properties:
+ - compatible: must be "zte,zx296718-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+ - clock-frequency: the desired I2C bus clock frequency.
+
+Examples:
+
+ i2c@112000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x00112000 0x1000>;
+ interrupts = ;
+ clocks = <>;
+ #address-cells = <1>
+ #size-cells = <0>;
+ clock-frequency = <160>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ };
--
2.7.4
[PATCH v4 2/3] MAINTAINERS: add zx2967 i2c controller driver to ARM ZTE architecture
Add the zx2967 i2c controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5fb9b62..4e81e2b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1987,10 +1987,12 @@ L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-zx/ F: drivers/clk/zte/ +F: drivers/i2c/busses/i2c-zx2967.c F: drivers/reset/reset-zx2967.c F: drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt +F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt F: Documentation/devicetree/bindings/soc/zte/ F: include/dt-bindings/soc/zx*.h -- 2.7.4
[PATCH v4 1/3] dt: bindings: add documentation for zx2967 family i2c controller
This patch adds dt-binding documentation for zx2967 family
i2c controller.
Signed-off-by: Baoyou Xie
Acked-by: Rob Herring
---
.../devicetree/bindings/i2c/i2c-zx2967.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
new file mode 100644
index 000..a528374
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
@@ -0,0 +1,24 @@
+ZTE zx2967 I2C controller
+
+Required properties:
+ - compatible: must be "zte,zx296718-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+ - clock-frequency: the desired I2C bus clock frequency.
+
+Examples:
+
+ i2c@112000 {
+ compatible = "zte,zx296718-i2c";
+ reg = <0x00112000 0x1000>;
+ interrupts = ;
+ clocks = <>;
+ #address-cells = <1>
+ #size-cells = <0>;
+ clock-frequency = <160>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_global_pin>;
+ };
--
2.7.4
[PATCH v4 2/3] MAINTAINERS: add zx2967 i2c controller driver to ARM ZTE architecture
Add the zx2967 i2c controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5fb9b62..4e81e2b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1987,10 +1987,12 @@ L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-zx/ F: drivers/clk/zte/ +F: drivers/i2c/busses/i2c-zx2967.c F: drivers/reset/reset-zx2967.c F: drivers/soc/zte/ F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt +F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt F: Documentation/devicetree/bindings/soc/zte/ F: include/dt-bindings/soc/zx*.h -- 2.7.4
[PATCH v8 3/3] thermal: zx2967: add thermal driver for ZTE's zx2967 family
This patch adds thermal driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
drivers/thermal/Kconfig | 8 ++
drivers/thermal/Makefile | 1 +
drivers/thermal/zx2967_thermal.c | 255 +++
3 files changed, 264 insertions(+)
create mode 100644 drivers/thermal/zx2967_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 18f2de6..f64bd50 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -444,4 +444,12 @@ config BCM2835_THERMAL
help
Support for thermal sensors on Broadcom bcm2835 SoCs.
+config ZX2967_THERMAL
+ tristate "Thermal sensors on zx2967 SoC"
+ depends on ARCH_ZX || COMPILE_TEST
+ help
+ Enable the zx2967 thermal sensors driver, which supports
+ the primitive temperature sensor embedded in zx2967 SoCs.
+ This sensor generates the real time die temperature.
+
endif
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 677c6d9..c00c05e 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o
obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o
obj-$(CONFIG_BCM2835_THERMAL) += bcm2835_thermal.o
+obj-$(CONFIG_ZX2967_THERMAL) += zx2967_thermal.o
diff --git a/drivers/thermal/zx2967_thermal.c b/drivers/thermal/zx2967_thermal.c
new file mode 100644
index 000..d177238
--- /dev/null
+++ b/drivers/thermal/zx2967_thermal.c
@@ -0,0 +1,255 @@
+/*
+ * ZTE's zx2967 family thermal sensor driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie <baoyou@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Power Mode: 0->low 1->high */
+#define ZX2967_THERMAL_POWER_MODE 0
+#define ZX2967_POWER_MODE_LOW 0
+#define ZX2967_POWER_MODE_HIGH 1
+
+/* DCF Control Register */
+#define ZX2967_THERMAL_DCF 0x4
+#define ZX2967_DCF_EN BIT(1)
+#define ZX2967_DCF_FREEZE BIT(0)
+
+/* Selection Register */
+#define ZX2967_THERMAL_SEL 0x8
+
+/* Control Register */
+#define ZX2967_THERMAL_CTRL0x10
+
+#define ZX2967_THERMAL_READY BIT(12)
+#define ZX2967_THERMAL_TEMP_MASK GENMASK(11, 0)
+#define ZX2967_THERMAL_ID_MASK 0x18
+#define ZX2967_THERMAL_ID 0x10
+
+#define ZX2967_GET_TEMP_TIMEOUT_US (100 * 1024)
+
+/* zx2967 Thermal Sensor Private Structure */
+struct zx2967_thermal_priv {
+ /* struct thermal_zone_device where the sensor is registered */
+ struct thermal_zone_device *tzd;
+ /* prevents reads sensor in parallel */
+ struct mutexlock;
+ /* topcrm clk structure */
+ struct clk *clk_topcrm;
+ /* apb clk structure */
+ struct clk *clk_apb;
+ /* pointer to base address of the thermal sensor */
+ void __iomem*regs;
+ struct device *dev;
+};
+
+static int zx2967_thermal_get_temp(void *data, int *temp)
+{
+ void __iomem *regs;
+ struct zx2967_thermal_priv *priv = data;
+ u32 val;
+ int ret;
+
+ if (!priv->tzd)
+ return -EAGAIN;
+
+ regs = priv->regs;
+ mutex_lock(>lock);
+ writel_relaxed(ZX2967_POWER_MODE_LOW,
+ regs + ZX2967_THERMAL_POWER_MODE);
+ writel_relaxed(ZX2967_DCF_EN, regs + ZX2967_THERMAL_DCF);
+
+ val = readl_relaxed(regs + ZX2967_THERMAL_SEL);
+ val &= ~ZX2967_THERMAL_ID_MASK;
+ val |= ZX2967_THERMAL_ID;
+ writel_relaxed(val, regs + ZX2967_THERMAL_SEL);
+
+ /*
+* Must wait for a while, surely it's a bit odd.
+* otherwise temperature value we got has a few deviation, even if
+* the THERMAL_READY bit is set.
+*/
+ usleep_range(100, 300);
+ ret = readx_poll_timeout(readl, regs + ZX2967_THERMAL_CTRL,
+val, val & ZX2967_THERMAL_READY, 300,
+ZX2967_GET_TEMP_TIMEOUT_US);
+ if (ret) {
+ dev_err(priv->dev, "Thermal sensor data timeout\n");
+ goto unlock;
+ }
+
+ writel_relaxed(ZX2967_DCF_FREEZE | ZX2967_DCF_EN,
+ regs + ZX2967_THERMAL_DCF);
+ val = readl_relaxed(regs + ZX2967_THERMAL_CTRL)
+& ZX2967_THERMAL_TEMP_MASK;
+ writel_relaxed(ZX2967_POWER_MODE_HIGH,
+ regs + ZX2967_THERMAL_POWER_MODE);
+
+ /*
+* Calculate temperature
+* In dts, slope is multiplied by 1000.
+*/
+ *temp = DIV_ROUND_CLOSEST(((s32)val + priv->
[PATCH v8 3/3] thermal: zx2967: add thermal driver for ZTE's zx2967 family
This patch adds thermal driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie
---
drivers/thermal/Kconfig | 8 ++
drivers/thermal/Makefile | 1 +
drivers/thermal/zx2967_thermal.c | 255 +++
3 files changed, 264 insertions(+)
create mode 100644 drivers/thermal/zx2967_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 18f2de6..f64bd50 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -444,4 +444,12 @@ config BCM2835_THERMAL
help
Support for thermal sensors on Broadcom bcm2835 SoCs.
+config ZX2967_THERMAL
+ tristate "Thermal sensors on zx2967 SoC"
+ depends on ARCH_ZX || COMPILE_TEST
+ help
+ Enable the zx2967 thermal sensors driver, which supports
+ the primitive temperature sensor embedded in zx2967 SoCs.
+ This sensor generates the real time die temperature.
+
endif
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 677c6d9..c00c05e 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o
obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o
obj-$(CONFIG_BCM2835_THERMAL) += bcm2835_thermal.o
+obj-$(CONFIG_ZX2967_THERMAL) += zx2967_thermal.o
diff --git a/drivers/thermal/zx2967_thermal.c b/drivers/thermal/zx2967_thermal.c
new file mode 100644
index 000..d177238
--- /dev/null
+++ b/drivers/thermal/zx2967_thermal.c
@@ -0,0 +1,255 @@
+/*
+ * ZTE's zx2967 family thermal sensor driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Power Mode: 0->low 1->high */
+#define ZX2967_THERMAL_POWER_MODE 0
+#define ZX2967_POWER_MODE_LOW 0
+#define ZX2967_POWER_MODE_HIGH 1
+
+/* DCF Control Register */
+#define ZX2967_THERMAL_DCF 0x4
+#define ZX2967_DCF_EN BIT(1)
+#define ZX2967_DCF_FREEZE BIT(0)
+
+/* Selection Register */
+#define ZX2967_THERMAL_SEL 0x8
+
+/* Control Register */
+#define ZX2967_THERMAL_CTRL0x10
+
+#define ZX2967_THERMAL_READY BIT(12)
+#define ZX2967_THERMAL_TEMP_MASK GENMASK(11, 0)
+#define ZX2967_THERMAL_ID_MASK 0x18
+#define ZX2967_THERMAL_ID 0x10
+
+#define ZX2967_GET_TEMP_TIMEOUT_US (100 * 1024)
+
+/* zx2967 Thermal Sensor Private Structure */
+struct zx2967_thermal_priv {
+ /* struct thermal_zone_device where the sensor is registered */
+ struct thermal_zone_device *tzd;
+ /* prevents reads sensor in parallel */
+ struct mutexlock;
+ /* topcrm clk structure */
+ struct clk *clk_topcrm;
+ /* apb clk structure */
+ struct clk *clk_apb;
+ /* pointer to base address of the thermal sensor */
+ void __iomem*regs;
+ struct device *dev;
+};
+
+static int zx2967_thermal_get_temp(void *data, int *temp)
+{
+ void __iomem *regs;
+ struct zx2967_thermal_priv *priv = data;
+ u32 val;
+ int ret;
+
+ if (!priv->tzd)
+ return -EAGAIN;
+
+ regs = priv->regs;
+ mutex_lock(>lock);
+ writel_relaxed(ZX2967_POWER_MODE_LOW,
+ regs + ZX2967_THERMAL_POWER_MODE);
+ writel_relaxed(ZX2967_DCF_EN, regs + ZX2967_THERMAL_DCF);
+
+ val = readl_relaxed(regs + ZX2967_THERMAL_SEL);
+ val &= ~ZX2967_THERMAL_ID_MASK;
+ val |= ZX2967_THERMAL_ID;
+ writel_relaxed(val, regs + ZX2967_THERMAL_SEL);
+
+ /*
+* Must wait for a while, surely it's a bit odd.
+* otherwise temperature value we got has a few deviation, even if
+* the THERMAL_READY bit is set.
+*/
+ usleep_range(100, 300);
+ ret = readx_poll_timeout(readl, regs + ZX2967_THERMAL_CTRL,
+val, val & ZX2967_THERMAL_READY, 300,
+ZX2967_GET_TEMP_TIMEOUT_US);
+ if (ret) {
+ dev_err(priv->dev, "Thermal sensor data timeout\n");
+ goto unlock;
+ }
+
+ writel_relaxed(ZX2967_DCF_FREEZE | ZX2967_DCF_EN,
+ regs + ZX2967_THERMAL_DCF);
+ val = readl_relaxed(regs + ZX2967_THERMAL_CTRL)
+& ZX2967_THERMAL_TEMP_MASK;
+ writel_relaxed(ZX2967_POWER_MODE_HIGH,
+ regs + ZX2967_THERMAL_POWER_MODE);
+
+ /*
+* Calculate temperature
+* In dts, slope is multiplied by 1000.
+*/
+ *temp = DIV_ROUND_CLOSEST(((s32)val + priv->tzd->tzp->offset) * 1000,
+
[PATCH v8 1/3] dt: bindings: add documentation for zx2967 family thermal sensor
This patch adds dt-binding documentation for zx2967 family thermal sensor.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Acked-by: Rob Herring <r...@kernel.org>
Reviewed-by: Shawn Guo <shawn...@kernel.org>
---
.../devicetree/bindings/thermal/zx2967-thermal.txt | 116 +
1 file changed, 116 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
diff --git a/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
new file mode 100644
index 000..0810644
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
@@ -0,0 +1,116 @@
+* ZTE zx2967 family Thermal
+
+Required Properties:
+- compatible: should be one of the following.
+* zte,zx296718-thermal
+- reg: physical base address of the controller and length of memory mapped
+region.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- clock-names: "topcrm" for the topcrm clock.
+ "apb" for the apb clock.
+- #thermal-sensor-cells: must be 0.
+
+Please note: coefficients defined in thermal-zones section need to be
+multiplied by 1000.
+
+Example for tempsensor:
+
+ tempsensor: tempsensor@148a000 {
+ compatible = "zte,zx296718-thermal";
+ reg = <0x0148a000 0x20>;
+ clocks = < TEMPSENSOR_GATE>, < AUDIO_TS_PCLK>;
+ clock-names = "topcrm", "apb";
+ #thermal-sensor-cells = <0>;
+ };
+
+Example for cooling device:
+
+ cooling_dev: cooling_dev {
+ cluster0_cooling_dev: cluster0-cooling-dev {
+ #cooling-cells = <2>;
+ cpumask = <0xf>;
+ capacitance = <1500>;
+ };
+
+ cluster1_cooling_dev: cluster1-cooling-dev {
+ #cooling-cells = <2>;
+ cpumask = <0x30>;
+ capacitance = <2000>;
+ };
+ };
+
+Example for thermal zones:
+
+ thermal-zones {
+ zx296718_thermal: zx296718_thermal {
+ polling-delay-passive = <500>;
+ polling-delay = <1000>;
+ sustainable-power = <6500>;
+
+ thermal-sensors = < 0>;
+ /*
+* slope need to be multiplied by 1000.
+*/
+ coefficients = <1951 (-922)>;
+
+ trips {
+ trip0: switch_on_temperature {
+ temperature = <9>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip1: desired_temperature {
+ temperature = <10>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit: critical_temperature {
+ temperature = <11>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <>;
+ cooling-device = < 2 5>;
+ };
+
+ map1 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map2 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map3 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map4 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ contribution = <9000>;
+ };
+
+ map5 {
+ trip = <>;
+ cooling
[PATCH v8 2/3] MAINTAINERS: add zx2967 thermal drivers to ARM ZTE architecture
Add the zx2967 thermal drivers as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5fb9b62..edfdea3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1989,10 +1989,12 @@ F: arch/arm/mach-zx/ F: drivers/clk/zte/ F: drivers/reset/reset-zx2967.c F: drivers/soc/zte/ +F: drivers/thermal/zx* F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt F: Documentation/devicetree/bindings/soc/zte/ +F: Documentation/devicetree/bindings/thermal/zx* F: include/dt-bindings/soc/zx*.h ARM/ZYNQ ARCHITECTURE -- 2.7.4
[PATCH v8 1/3] dt: bindings: add documentation for zx2967 family thermal sensor
This patch adds dt-binding documentation for zx2967 family thermal sensor.
Signed-off-by: Baoyou Xie
Acked-by: Rob Herring
Reviewed-by: Shawn Guo
---
.../devicetree/bindings/thermal/zx2967-thermal.txt | 116 +
1 file changed, 116 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
diff --git a/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
new file mode 100644
index 000..0810644
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
@@ -0,0 +1,116 @@
+* ZTE zx2967 family Thermal
+
+Required Properties:
+- compatible: should be one of the following.
+* zte,zx296718-thermal
+- reg: physical base address of the controller and length of memory mapped
+region.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- clock-names: "topcrm" for the topcrm clock.
+ "apb" for the apb clock.
+- #thermal-sensor-cells: must be 0.
+
+Please note: coefficients defined in thermal-zones section need to be
+multiplied by 1000.
+
+Example for tempsensor:
+
+ tempsensor: tempsensor@148a000 {
+ compatible = "zte,zx296718-thermal";
+ reg = <0x0148a000 0x20>;
+ clocks = < TEMPSENSOR_GATE>, < AUDIO_TS_PCLK>;
+ clock-names = "topcrm", "apb";
+ #thermal-sensor-cells = <0>;
+ };
+
+Example for cooling device:
+
+ cooling_dev: cooling_dev {
+ cluster0_cooling_dev: cluster0-cooling-dev {
+ #cooling-cells = <2>;
+ cpumask = <0xf>;
+ capacitance = <1500>;
+ };
+
+ cluster1_cooling_dev: cluster1-cooling-dev {
+ #cooling-cells = <2>;
+ cpumask = <0x30>;
+ capacitance = <2000>;
+ };
+ };
+
+Example for thermal zones:
+
+ thermal-zones {
+ zx296718_thermal: zx296718_thermal {
+ polling-delay-passive = <500>;
+ polling-delay = <1000>;
+ sustainable-power = <6500>;
+
+ thermal-sensors = < 0>;
+ /*
+* slope need to be multiplied by 1000.
+*/
+ coefficients = <1951 (-922)>;
+
+ trips {
+ trip0: switch_on_temperature {
+ temperature = <9>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip1: desired_temperature {
+ temperature = <10>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit: critical_temperature {
+ temperature = <11>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <>;
+ cooling-device = < 2 5>;
+ };
+
+ map1 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map2 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map3 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map4 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ contribution = <9000>;
+ };
+
+ map5 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ cont
[PATCH v8 2/3] MAINTAINERS: add zx2967 thermal drivers to ARM ZTE architecture
Add the zx2967 thermal drivers as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5fb9b62..edfdea3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1989,10 +1989,12 @@ F: arch/arm/mach-zx/ F: drivers/clk/zte/ F: drivers/reset/reset-zx2967.c F: drivers/soc/zte/ +F: drivers/thermal/zx* F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt F: Documentation/devicetree/bindings/soc/zte/ +F: Documentation/devicetree/bindings/thermal/zx* F: include/dt-bindings/soc/zx*.h ARM/ZYNQ ARCHITECTURE -- 2.7.4
[PATCH v9 3/3] watchdog: zx2967: add watchdog controller driver for ZTE's zx2967 family
This patch adds watchdog controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
drivers/watchdog/Kconfig | 10 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/zx2967_wdt.c | 291 ++
3 files changed, 302 insertions(+)
create mode 100644 drivers/watchdog/zx2967_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index acb00b5..05093a2 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -714,6 +714,16 @@ config ASPEED_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called aspeed_wdt.
+config ZX2967_WATCHDOG
+ tristate "ZTE zx2967 SoCs watchdog support"
+ depends on ARCH_ZX
+ select WATCHDOG_CORE
+ help
+ Say Y here to include support for the watchdog timer
+ in ZTE zx2967 SoCs.
+ To compile this driver as a module, choose M here: the
+ module will be called zx2967_wdt.
+
# AVR32 Architecture
config AT32AP700X_WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 0c3d35e..bf2d296 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -82,6 +82,7 @@ obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o
obj-$(CONFIG_ATLAS7_WATCHDOG) += atlas7_wdt.o
obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
+obj-$(CONFIG_ZX2967_WATCHDOG) += zx2967_wdt.o
# AVR32 Architecture
obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
diff --git a/drivers/watchdog/zx2967_wdt.c b/drivers/watchdog/zx2967_wdt.c
new file mode 100644
index 000..e290d5a
--- /dev/null
+++ b/drivers/watchdog/zx2967_wdt.c
@@ -0,0 +1,291 @@
+/*
+ * watchdog driver for ZTE's zx2967 family
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie <baoyou@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define ZX2967_WDT_CFG_REG 0x4
+#define ZX2967_WDT_LOAD_REG0x8
+#define ZX2967_WDT_REFRESH_REG 0x18
+#define ZX2967_WDT_START_REG 0x1c
+
+#define ZX2967_WDT_REFRESH_MASKGENMASK(5, 0)
+
+#define ZX2967_WDT_CFG_DIV(n) n) & 0xff) - 1) << 8)
+#define ZX2967_WDT_START_EN0x1
+
+/*
+ * Hardware magic number.
+ * When watchdog reg is written, the lowest 16 bits are valid, but
+ * the highest 16 bits should be always this number.
+ */
+#define ZX2967_WDT_WRITEKEY(0x1234 << 16)
+#define ZX2967_WDT_VAL_MASKGENMASK(15, 0)
+
+#define ZX2967_WDT_DIV_DEFAULT 16
+#define ZX2967_WDT_DEFAULT_TIMEOUT 32
+#define ZX2967_WDT_MIN_TIMEOUT 1
+#define ZX2967_WDT_MAX_TIMEOUT 524
+#define ZX2967_WDT_MAX_COUNT 0x
+
+#define ZX2967_WDT_CLK_FREQ0x8000
+
+#define ZX2967_WDT_FLAG_REBOOT_MON BIT(0)
+
+struct zx2967_wdt {
+ struct watchdog_device wdt_device;
+ void __iomem*reg_base;
+ struct clk *clock;
+};
+
+static inline u32 zx2967_wdt_readl(struct zx2967_wdt *wdt, u16 reg)
+{
+ return readl_relaxed(wdt->reg_base + reg);
+}
+
+static inline void zx2967_wdt_writel(struct zx2967_wdt *wdt, u16 reg, u32 val)
+{
+ writel_relaxed(val | ZX2967_WDT_WRITEKEY, wdt->reg_base + reg);
+}
+
+static void zx2967_wdt_refresh(struct zx2967_wdt *wdt)
+{
+ u32 val;
+
+ val = zx2967_wdt_readl(wdt, ZX2967_WDT_REFRESH_REG);
+ /*
+* Bit 4-5, 1 and 2: refresh config info
+* Bit 2-3, 1 and 2: refresh counter
+* Bit 0-1, 1 and 2: refresh int-value
+* we shift each group value between 1 and 2 to refresh all data.
+*/
+ val ^= ZX2967_WDT_REFRESH_MASK;
+ zx2967_wdt_writel(wdt, ZX2967_WDT_REFRESH_REG,
+ val & ZX2967_WDT_VAL_MASK);
+}
+
+static int
+zx2967_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout)
+{
+ struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
+ unsigned int divisor = ZX2967_WDT_DIV_DEFAULT;
+ u32 count;
+
+ count = timeout * ZX2967_WDT_CLK_FREQ;
+ if (count > divisor * ZX2967_WDT_MAX_COUNT)
+ divisor = DIV_ROUND_UP(count, ZX2967_WDT_MAX_COUNT);
+ count = DIV_ROUND_UP(count, divisor);
+ zx2967_wdt_writel(wdt, ZX2967_WDT_CFG_REG,
+ ZX2967_WDT_CFG_DIV(divisor) & ZX2967_WDT_VAL_MASK);
+ zx2967_wdt_writel(wdt, ZX2967_WDT_LOAD_REG,
+ count & ZX2967_WDT_VAL_MASK);
+ zx2967_wdt_refresh(wdt);
+ wdd->timeout = (count * divisor) / ZX2967_WDT_CLK_FREQ;
+
+ return 0;
+}
+
+static void __zx2967_wdt_s
[PATCH v9 3/3] watchdog: zx2967: add watchdog controller driver for ZTE's zx2967 family
This patch adds watchdog controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie
---
drivers/watchdog/Kconfig | 10 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/zx2967_wdt.c | 291 ++
3 files changed, 302 insertions(+)
create mode 100644 drivers/watchdog/zx2967_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index acb00b5..05093a2 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -714,6 +714,16 @@ config ASPEED_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called aspeed_wdt.
+config ZX2967_WATCHDOG
+ tristate "ZTE zx2967 SoCs watchdog support"
+ depends on ARCH_ZX
+ select WATCHDOG_CORE
+ help
+ Say Y here to include support for the watchdog timer
+ in ZTE zx2967 SoCs.
+ To compile this driver as a module, choose M here: the
+ module will be called zx2967_wdt.
+
# AVR32 Architecture
config AT32AP700X_WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 0c3d35e..bf2d296 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -82,6 +82,7 @@ obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o
obj-$(CONFIG_ATLAS7_WATCHDOG) += atlas7_wdt.o
obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
+obj-$(CONFIG_ZX2967_WATCHDOG) += zx2967_wdt.o
# AVR32 Architecture
obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
diff --git a/drivers/watchdog/zx2967_wdt.c b/drivers/watchdog/zx2967_wdt.c
new file mode 100644
index 000..e290d5a
--- /dev/null
+++ b/drivers/watchdog/zx2967_wdt.c
@@ -0,0 +1,291 @@
+/*
+ * watchdog driver for ZTE's zx2967 family
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define ZX2967_WDT_CFG_REG 0x4
+#define ZX2967_WDT_LOAD_REG0x8
+#define ZX2967_WDT_REFRESH_REG 0x18
+#define ZX2967_WDT_START_REG 0x1c
+
+#define ZX2967_WDT_REFRESH_MASKGENMASK(5, 0)
+
+#define ZX2967_WDT_CFG_DIV(n) n) & 0xff) - 1) << 8)
+#define ZX2967_WDT_START_EN0x1
+
+/*
+ * Hardware magic number.
+ * When watchdog reg is written, the lowest 16 bits are valid, but
+ * the highest 16 bits should be always this number.
+ */
+#define ZX2967_WDT_WRITEKEY(0x1234 << 16)
+#define ZX2967_WDT_VAL_MASKGENMASK(15, 0)
+
+#define ZX2967_WDT_DIV_DEFAULT 16
+#define ZX2967_WDT_DEFAULT_TIMEOUT 32
+#define ZX2967_WDT_MIN_TIMEOUT 1
+#define ZX2967_WDT_MAX_TIMEOUT 524
+#define ZX2967_WDT_MAX_COUNT 0x
+
+#define ZX2967_WDT_CLK_FREQ0x8000
+
+#define ZX2967_WDT_FLAG_REBOOT_MON BIT(0)
+
+struct zx2967_wdt {
+ struct watchdog_device wdt_device;
+ void __iomem*reg_base;
+ struct clk *clock;
+};
+
+static inline u32 zx2967_wdt_readl(struct zx2967_wdt *wdt, u16 reg)
+{
+ return readl_relaxed(wdt->reg_base + reg);
+}
+
+static inline void zx2967_wdt_writel(struct zx2967_wdt *wdt, u16 reg, u32 val)
+{
+ writel_relaxed(val | ZX2967_WDT_WRITEKEY, wdt->reg_base + reg);
+}
+
+static void zx2967_wdt_refresh(struct zx2967_wdt *wdt)
+{
+ u32 val;
+
+ val = zx2967_wdt_readl(wdt, ZX2967_WDT_REFRESH_REG);
+ /*
+* Bit 4-5, 1 and 2: refresh config info
+* Bit 2-3, 1 and 2: refresh counter
+* Bit 0-1, 1 and 2: refresh int-value
+* we shift each group value between 1 and 2 to refresh all data.
+*/
+ val ^= ZX2967_WDT_REFRESH_MASK;
+ zx2967_wdt_writel(wdt, ZX2967_WDT_REFRESH_REG,
+ val & ZX2967_WDT_VAL_MASK);
+}
+
+static int
+zx2967_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout)
+{
+ struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
+ unsigned int divisor = ZX2967_WDT_DIV_DEFAULT;
+ u32 count;
+
+ count = timeout * ZX2967_WDT_CLK_FREQ;
+ if (count > divisor * ZX2967_WDT_MAX_COUNT)
+ divisor = DIV_ROUND_UP(count, ZX2967_WDT_MAX_COUNT);
+ count = DIV_ROUND_UP(count, divisor);
+ zx2967_wdt_writel(wdt, ZX2967_WDT_CFG_REG,
+ ZX2967_WDT_CFG_DIV(divisor) & ZX2967_WDT_VAL_MASK);
+ zx2967_wdt_writel(wdt, ZX2967_WDT_LOAD_REG,
+ count & ZX2967_WDT_VAL_MASK);
+ zx2967_wdt_refresh(wdt);
+ wdd->timeout = (count * divisor) / ZX2967_WDT_CLK_FREQ;
+
+ return 0;
+}
+
+static void __zx2967_wdt_start(struct zx2967_wdt *wdt)
+{
+ u32 val;
+
+ val = zx2967
[PATCH v9 1/3] dt: bindings: add documentation for zx2967 family watchdog controller
This patch adds dt-binding documentation for zx2967 family
watchdog controller.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Acked-by: Rob Herring <r...@kernel.org>
---
.../bindings/watchdog/zte,zx2967-wdt.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
b/Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
new file mode 100644
index 000..06ce677
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
@@ -0,0 +1,32 @@
+ZTE zx2967 Watchdog timer
+
+Required properties:
+
+- compatible : should be one of the following.
+ * zte,zx296718-wdt
+- reg : Specifies base physical address and size of the registers.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- resets : Reference to the reset controller controlling the watchdog
+ controller.
+
+Optional properties:
+
+- timeout-sec : Contains the watchdog timeout in seconds.
+- zte,wdt-reset-sysctrl : Directs how to reset system by the watchdog.
+ if we don't want to restart system when watchdog been triggered,
+ it's not required, vice versa.
+ It should include following fields.
+ * phandle of aon-sysctrl.
+ * offset of register that be written, should be 0xb0.
+ * configure value that be written to aon-sysctrl.
+ * bit mask, corresponding bits will be affected.
+
+Example:
+
+wdt: watchdog@1465000 {
+ compatible = "zte,zx296718-wdt";
+ reg = <0x1465000 0x1000>;
+ clocks = < WDT_WCLK>;
+ resets = < 35>;
+ zte,wdt-reset-sysctrl = <_sysctrl 0xb0 1 0x115>;
+};
--
2.7.4
[PATCH v9 2/3] MAINTAINERS: add zx2967 watchdog controller driver to ARM ZTE architecture
Add the zx2967 watchdog controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index edfdea3..275c434 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1990,11 +1990,13 @@ F: drivers/clk/zte/ F: drivers/reset/reset-zx2967.c F: drivers/soc/zte/ F: drivers/thermal/zx* +F: drivers/watchdog/zx2967_wdt.c F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt F: Documentation/devicetree/bindings/soc/zte/ F: Documentation/devicetree/bindings/thermal/zx* +F: Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt F: include/dt-bindings/soc/zx*.h ARM/ZYNQ ARCHITECTURE -- 2.7.4
[PATCH v9 1/3] dt: bindings: add documentation for zx2967 family watchdog controller
This patch adds dt-binding documentation for zx2967 family
watchdog controller.
Signed-off-by: Baoyou Xie
Acked-by: Rob Herring
---
.../bindings/watchdog/zte,zx2967-wdt.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
b/Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
new file mode 100644
index 000..06ce677
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
@@ -0,0 +1,32 @@
+ZTE zx2967 Watchdog timer
+
+Required properties:
+
+- compatible : should be one of the following.
+ * zte,zx296718-wdt
+- reg : Specifies base physical address and size of the registers.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- resets : Reference to the reset controller controlling the watchdog
+ controller.
+
+Optional properties:
+
+- timeout-sec : Contains the watchdog timeout in seconds.
+- zte,wdt-reset-sysctrl : Directs how to reset system by the watchdog.
+ if we don't want to restart system when watchdog been triggered,
+ it's not required, vice versa.
+ It should include following fields.
+ * phandle of aon-sysctrl.
+ * offset of register that be written, should be 0xb0.
+ * configure value that be written to aon-sysctrl.
+ * bit mask, corresponding bits will be affected.
+
+Example:
+
+wdt: watchdog@1465000 {
+ compatible = "zte,zx296718-wdt";
+ reg = <0x1465000 0x1000>;
+ clocks = < WDT_WCLK>;
+ resets = < 35>;
+ zte,wdt-reset-sysctrl = <_sysctrl 0xb0 1 0x115>;
+};
--
2.7.4
[PATCH v9 2/3] MAINTAINERS: add zx2967 watchdog controller driver to ARM ZTE architecture
Add the zx2967 watchdog controller driver as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index edfdea3..275c434 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1990,11 +1990,13 @@ F: drivers/clk/zte/ F: drivers/reset/reset-zx2967.c F: drivers/soc/zte/ F: drivers/thermal/zx* +F: drivers/watchdog/zx2967_wdt.c F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt F: Documentation/devicetree/bindings/soc/zte/ F: Documentation/devicetree/bindings/thermal/zx* +F: Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt F: include/dt-bindings/soc/zx*.h ARM/ZYNQ ARCHITECTURE -- 2.7.4
[PATCH v7 3/3] thermal: zx2967: add thermal driver for ZTE's zx2967 family
This patch adds thermal driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
---
drivers/thermal/Kconfig | 8 ++
drivers/thermal/Makefile | 1 +
drivers/thermal/zx2967_thermal.c | 281 +++
3 files changed, 290 insertions(+)
create mode 100644 drivers/thermal/zx2967_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 18f2de6..f64bd50 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -444,4 +444,12 @@ config BCM2835_THERMAL
help
Support for thermal sensors on Broadcom bcm2835 SoCs.
+config ZX2967_THERMAL
+ tristate "Thermal sensors on zx2967 SoC"
+ depends on ARCH_ZX || COMPILE_TEST
+ help
+ Enable the zx2967 thermal sensors driver, which supports
+ the primitive temperature sensor embedded in zx2967 SoCs.
+ This sensor generates the real time die temperature.
+
endif
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 677c6d9..c00c05e 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o
obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o
obj-$(CONFIG_BCM2835_THERMAL) += bcm2835_thermal.o
+obj-$(CONFIG_ZX2967_THERMAL) += zx2967_thermal.o
diff --git a/drivers/thermal/zx2967_thermal.c b/drivers/thermal/zx2967_thermal.c
new file mode 100644
index 000..fba55b1c
--- /dev/null
+++ b/drivers/thermal/zx2967_thermal.c
@@ -0,0 +1,281 @@
+/*
+ * ZTE's zx2967 family thermal sensor driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie <baoyou@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Power Mode: 0->low 1->high */
+#define ZX2967_THERMAL_POWER_MODE 0
+#define ZX2967_POWER_MODE_LOW 0
+#define ZX2967_POWER_MODE_HIGH 1
+
+/* DCF Control Register */
+#define ZX2967_THERMAL_DCF 0x4
+#define ZX2967_DCF_EN BIT(1)
+#define ZX2967_DCF_FREEZE BIT(0)
+
+/* Selection Register */
+#define ZX2967_THERMAL_SEL 0x8
+
+/* Control Register */
+#define ZX2967_THERMAL_CTRL0x10
+
+#define ZX2967_THERMAL_READY BIT(12)
+#define ZX2967_THERMAL_TEMP_MASK 0xfff
+#define ZX2967_THERMAL_ID_MASK 0x18
+#define ZX2967_THERMAL_ID0 0x10
+#define ZX2967_THERMAL_ID1 0x8
+
+#define ZX2967_GET_TEMP_TIMEOUT_US (100 * 1024)
+
+struct zx2967_thermal_sensor {
+ struct zx2967_thermal_priv *priv;
+ struct thermal_zone_device *tzd;
+ int id;
+};
+
+/*
+ * Now, one sensor remains in system, but in fact, we intend to support
+ * two sensors.
+ */
+#define NUM_SENSORS1
+
+struct zx2967_thermal_priv {
+ struct zx2967_thermal_sensorsensors[NUM_SENSORS];
+ /* Prevents reads sensor in parallel */
+ struct mutexlock;
+ struct clk *clk_gate;
+ struct clk *pclk;
+ void __iomem*regs;
+ struct device *dev;
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int zx2967_thermal_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct zx2967_thermal_priv *priv = platform_get_drvdata(pdev);
+
+ if (priv && priv->pclk)
+ clk_disable_unprepare(priv->pclk);
+
+ if (priv && priv->clk_gate)
+ clk_disable_unprepare(priv->clk_gate);
+
+ return 0;
+}
+
+static int zx2967_thermal_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct zx2967_thermal_priv *priv = platform_get_drvdata(pdev);
+ int error;
+
+ error = clk_prepare_enable(priv->clk_gate);
+ if (error)
+ return error;
+
+ error = clk_prepare_enable(priv->pclk);
+ if (error) {
+ clk_disable_unprepare(priv->clk_gate);
+ return error;
+ }
+
+ return 0;
+}
+static SIMPLE_DEV_PM_OPS(zx2967_thermal_pm_ops,
+zx2967_thermal_suspend, zx2967_thermal_resume);
+#endif
+
+static int zx2967_thermal_get_temp(void *data, int *temp)
+{
+ void __iomem *regs;
+ struct zx2967_thermal_sensor *sensor = data;
+ struct zx2967_thermal_priv *priv = sensor->priv;
+ u32 val, sel_id;
+ int ret;
+
+ if (!sensor->tzd)
+ return -EAGAIN;
+
+ regs = priv->regs;
+ mutex_lock(>lock);
+ writel_relaxed(ZX2967_POWER_MODE_LOW,
+ regs + ZX2967_THERMAL_POWER_MODE);
+ writel_relaxed(ZX2967_DCF_EN, regs + ZX2967_THERMA
[PATCH v7 3/3] thermal: zx2967: add thermal driver for ZTE's zx2967 family
This patch adds thermal driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie
---
drivers/thermal/Kconfig | 8 ++
drivers/thermal/Makefile | 1 +
drivers/thermal/zx2967_thermal.c | 281 +++
3 files changed, 290 insertions(+)
create mode 100644 drivers/thermal/zx2967_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 18f2de6..f64bd50 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -444,4 +444,12 @@ config BCM2835_THERMAL
help
Support for thermal sensors on Broadcom bcm2835 SoCs.
+config ZX2967_THERMAL
+ tristate "Thermal sensors on zx2967 SoC"
+ depends on ARCH_ZX || COMPILE_TEST
+ help
+ Enable the zx2967 thermal sensors driver, which supports
+ the primitive temperature sensor embedded in zx2967 SoCs.
+ This sensor generates the real time die temperature.
+
endif
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 677c6d9..c00c05e 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o
obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o
obj-$(CONFIG_BCM2835_THERMAL) += bcm2835_thermal.o
+obj-$(CONFIG_ZX2967_THERMAL) += zx2967_thermal.o
diff --git a/drivers/thermal/zx2967_thermal.c b/drivers/thermal/zx2967_thermal.c
new file mode 100644
index 000..fba55b1c
--- /dev/null
+++ b/drivers/thermal/zx2967_thermal.c
@@ -0,0 +1,281 @@
+/*
+ * ZTE's zx2967 family thermal sensor driver
+ *
+ * Copyright (C) 2017 ZTE Ltd.
+ *
+ * Author: Baoyou Xie
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Power Mode: 0->low 1->high */
+#define ZX2967_THERMAL_POWER_MODE 0
+#define ZX2967_POWER_MODE_LOW 0
+#define ZX2967_POWER_MODE_HIGH 1
+
+/* DCF Control Register */
+#define ZX2967_THERMAL_DCF 0x4
+#define ZX2967_DCF_EN BIT(1)
+#define ZX2967_DCF_FREEZE BIT(0)
+
+/* Selection Register */
+#define ZX2967_THERMAL_SEL 0x8
+
+/* Control Register */
+#define ZX2967_THERMAL_CTRL0x10
+
+#define ZX2967_THERMAL_READY BIT(12)
+#define ZX2967_THERMAL_TEMP_MASK 0xfff
+#define ZX2967_THERMAL_ID_MASK 0x18
+#define ZX2967_THERMAL_ID0 0x10
+#define ZX2967_THERMAL_ID1 0x8
+
+#define ZX2967_GET_TEMP_TIMEOUT_US (100 * 1024)
+
+struct zx2967_thermal_sensor {
+ struct zx2967_thermal_priv *priv;
+ struct thermal_zone_device *tzd;
+ int id;
+};
+
+/*
+ * Now, one sensor remains in system, but in fact, we intend to support
+ * two sensors.
+ */
+#define NUM_SENSORS1
+
+struct zx2967_thermal_priv {
+ struct zx2967_thermal_sensorsensors[NUM_SENSORS];
+ /* Prevents reads sensor in parallel */
+ struct mutexlock;
+ struct clk *clk_gate;
+ struct clk *pclk;
+ void __iomem*regs;
+ struct device *dev;
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int zx2967_thermal_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct zx2967_thermal_priv *priv = platform_get_drvdata(pdev);
+
+ if (priv && priv->pclk)
+ clk_disable_unprepare(priv->pclk);
+
+ if (priv && priv->clk_gate)
+ clk_disable_unprepare(priv->clk_gate);
+
+ return 0;
+}
+
+static int zx2967_thermal_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct zx2967_thermal_priv *priv = platform_get_drvdata(pdev);
+ int error;
+
+ error = clk_prepare_enable(priv->clk_gate);
+ if (error)
+ return error;
+
+ error = clk_prepare_enable(priv->pclk);
+ if (error) {
+ clk_disable_unprepare(priv->clk_gate);
+ return error;
+ }
+
+ return 0;
+}
+static SIMPLE_DEV_PM_OPS(zx2967_thermal_pm_ops,
+zx2967_thermal_suspend, zx2967_thermal_resume);
+#endif
+
+static int zx2967_thermal_get_temp(void *data, int *temp)
+{
+ void __iomem *regs;
+ struct zx2967_thermal_sensor *sensor = data;
+ struct zx2967_thermal_priv *priv = sensor->priv;
+ u32 val, sel_id;
+ int ret;
+
+ if (!sensor->tzd)
+ return -EAGAIN;
+
+ regs = priv->regs;
+ mutex_lock(>lock);
+ writel_relaxed(ZX2967_POWER_MODE_LOW,
+ regs + ZX2967_THERMAL_POWER_MODE);
+ writel_relaxed(ZX2967_DCF_EN, regs + ZX2967_THERMAL_DCF);
+
+ val = readl_relaxed(regs + ZX2967_THERMAL_SEL);
+
[PATCH v7 1/3] dt: bindings: add documentation for zx2967 family thermal sensor
This patch adds dt-binding documentation for zx2967 family thermal sensor.
Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Acked-by: Rob Herring <r...@kernel.org>
Reviewed-by: Shawn Guo <shawn...@kernel.org>
---
.../devicetree/bindings/thermal/zx2967-thermal.txt | 116 +
1 file changed, 116 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
diff --git a/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
new file mode 100644
index 000..169a699
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
@@ -0,0 +1,116 @@
+* ZTE zx2967 family Thermal
+
+Required Properties:
+- compatible: should be one of the following.
+* zte,zx296718-thermal
+- reg: physical base address of the controller and length of memory mapped
+region.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- clock-names: "gate" for the topcrm clock.
+ "pclk" for the apb clock.
+- #thermal-sensor-cells: must be 0.
+
+Please note: coefficients defined in thermal-zones section need to be
+multiplied by 1000.
+
+Example for tempsensor:
+
+ tempsensor: tempsensor@148a000 {
+ compatible = "zte,zx296718-thermal";
+ reg = <0x0148a000 0x20>;
+ clocks = < TEMPSENSOR_GATE>, < AUDIO_TS_PCLK>;
+ clock-names = "gate", "pclk";
+ #thermal-sensor-cells = <0>;
+ };
+
+Example for cooling device:
+
+ cooling_dev: cooling_dev {
+ cluster0_cooling_dev: cluster0-cooling-dev {
+ #cooling-cells = <2>;
+ cpumask = <0xf>;
+ capacitance = <1500>;
+ };
+
+ cluster1_cooling_dev: cluster1-cooling-dev {
+ #cooling-cells = <2>;
+ cpumask = <0x30>;
+ capacitance = <2000>;
+ };
+ };
+
+Example for thermal zones:
+
+ thermal-zones {
+ zx296718_thermal: zx296718_thermal {
+ polling-delay-passive = <500>;
+ polling-delay = <1000>;
+ sustainable-power = <6500>;
+
+ thermal-sensors = < 0>;
+ /*
+* both slope and offset need to be multiplied by 1000.
+*/
+ coefficients = <1951 (-922)>;
+
+ trips {
+ trip0: switch_on_temperature {
+ temperature = <9>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip1: desired_temperature {
+ temperature = <10>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit: critical_temperature {
+ temperature = <11>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <>;
+ cooling-device = < 2 5>;
+ };
+
+ map1 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map2 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map3 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map4 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ contribution = <9000>;
+ };
+
+ map5 {
+ trip = <>;
+ cooling
[PATCH v7 1/3] dt: bindings: add documentation for zx2967 family thermal sensor
This patch adds dt-binding documentation for zx2967 family thermal sensor.
Signed-off-by: Baoyou Xie
Acked-by: Rob Herring
Reviewed-by: Shawn Guo
---
.../devicetree/bindings/thermal/zx2967-thermal.txt | 116 +
1 file changed, 116 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
diff --git a/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
new file mode 100644
index 000..169a699
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
@@ -0,0 +1,116 @@
+* ZTE zx2967 family Thermal
+
+Required Properties:
+- compatible: should be one of the following.
+* zte,zx296718-thermal
+- reg: physical base address of the controller and length of memory mapped
+region.
+- clocks : Pairs of phandle and specifier referencing the controller's clocks.
+- clock-names: "gate" for the topcrm clock.
+ "pclk" for the apb clock.
+- #thermal-sensor-cells: must be 0.
+
+Please note: coefficients defined in thermal-zones section need to be
+multiplied by 1000.
+
+Example for tempsensor:
+
+ tempsensor: tempsensor@148a000 {
+ compatible = "zte,zx296718-thermal";
+ reg = <0x0148a000 0x20>;
+ clocks = < TEMPSENSOR_GATE>, < AUDIO_TS_PCLK>;
+ clock-names = "gate", "pclk";
+ #thermal-sensor-cells = <0>;
+ };
+
+Example for cooling device:
+
+ cooling_dev: cooling_dev {
+ cluster0_cooling_dev: cluster0-cooling-dev {
+ #cooling-cells = <2>;
+ cpumask = <0xf>;
+ capacitance = <1500>;
+ };
+
+ cluster1_cooling_dev: cluster1-cooling-dev {
+ #cooling-cells = <2>;
+ cpumask = <0x30>;
+ capacitance = <2000>;
+ };
+ };
+
+Example for thermal zones:
+
+ thermal-zones {
+ zx296718_thermal: zx296718_thermal {
+ polling-delay-passive = <500>;
+ polling-delay = <1000>;
+ sustainable-power = <6500>;
+
+ thermal-sensors = < 0>;
+ /*
+* both slope and offset need to be multiplied by 1000.
+*/
+ coefficients = <1951 (-922)>;
+
+ trips {
+ trip0: switch_on_temperature {
+ temperature = <9>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip1: desired_temperature {
+ temperature = <10>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ crit: critical_temperature {
+ temperature = <11>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <>;
+ cooling-device = < 2 5>;
+ };
+
+ map1 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map2 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map3 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ };
+
+ map4 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ contribution = <9000>;
+ };
+
+ map5 {
+ trip = <>;
+ cooling-device = <_cooling_dev
1 2>;
+ cont
[PATCH v7 2/3] MAINTAINERS: add zx2967 thermal drivers to ARM ZTE architecture
Add the zx2967 thermal drivers as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie <baoyou@linaro.org> --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5fb9b62..edfdea3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1989,10 +1989,12 @@ F: arch/arm/mach-zx/ F: drivers/clk/zte/ F: drivers/reset/reset-zx2967.c F: drivers/soc/zte/ +F: drivers/thermal/zx* F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt F: Documentation/devicetree/bindings/soc/zte/ +F: Documentation/devicetree/bindings/thermal/zx* F: include/dt-bindings/soc/zx*.h ARM/ZYNQ ARCHITECTURE -- 2.7.4
[PATCH v7 2/3] MAINTAINERS: add zx2967 thermal drivers to ARM ZTE architecture
Add the zx2967 thermal drivers as maintained by ARM ZTE architecture maintainers, as they're parts of the core IP. Signed-off-by: Baoyou Xie --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5fb9b62..edfdea3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1989,10 +1989,12 @@ F: arch/arm/mach-zx/ F: drivers/clk/zte/ F: drivers/reset/reset-zx2967.c F: drivers/soc/zte/ +F: drivers/thermal/zx* F: Documentation/devicetree/bindings/arm/zte.txt F: Documentation/devicetree/bindings/clock/zx296702-clk.txt F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt F: Documentation/devicetree/bindings/soc/zte/ +F: Documentation/devicetree/bindings/thermal/zx* F: include/dt-bindings/soc/zx*.h ARM/ZYNQ ARCHITECTURE -- 2.7.4
