Re: [PATCH v1, 3/3] drm/mediatek: gamma set with cmdq
Hi, Yongqiang:
On Mon, 2021-04-12 at 16:45 +0800, Yongqiang Niu wrote:
> On Mon, 2021-04-12 at 16:28 +0800, CK Hu wrote:
> > Hi, Yongqiang:
> >
> > On Mon, 2021-04-12 at 14:35 +0800, Yongqiang Niu wrote:
> > > gamma lut set in vsync active will caused display flash issue
> > > set gamma lut with cmdq
> >
> > In MT8173, it's ok to set gammma out of vblank period. Why do you
> > setting gamma in vblank in this patch?
> >
> > Regards,
> > CK
> >
>
> mtk drm driver code has changed many since mt8173, there is no one test
> this in the newest version for mt8173.
>
> and this issue is random.
> https://partnerissuetracker.corp.google.com/u/1/issues/153842418
>
> and not all platform will set gamma lut.
> some project platform will not set gamma lut from chrome os
> (crhome os set gamma lut may be with some special panel, like AUO
> B116XTN02.3 in
> https://partnerissuetracker.corp.google.com/u/1/issues/153842418
> )
>
I could not see the page in partnelissuetracker, If this patch fix some
bug, describe the bug in commit message. It's better that information
include how to reproduce this bug and what kind of error happen. More
information would help us to understand why setting in vblank would fix
this bug.
Regards,
CK
> > >
> > > Signed-off-by: Yongqiang Niu
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_disp_aal.c | 4 ++--
> > > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 ---
> > > drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 11 ++-
> > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++---
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 8 +---
> > > 5 files changed, 28 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> > > b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> > > index 64b4528..c8e178e 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> > > @@ -59,12 +59,12 @@ void mtk_aal_config(struct device *dev, unsigned int
> > > w,
> > > mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, aal->regs,
> > > DISP_AAL_SIZE);
> > > }
> > >
> > > -void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
> > > +void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state,
> > > struct cmdq_pkt *cmdq_pkt)
> > > {
> > > struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> > >
> > > if (aal->data && aal->data->has_gamma)
> > > - mtk_gamma_set_common(aal->regs, state);
> > > + mtk_gamma_set_common(aal->regs, >cmdq_reg, state,
> > > cmdq_pkt);
> > > }
> > >
> > > void mtk_aal_start(struct device *dev)
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > index 86c3068..c2e7dcb 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > @@ -14,7 +14,7 @@
> > > void mtk_aal_config(struct device *dev, unsigned int w,
> > > unsigned int h, unsigned int vrefresh,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > > -void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state);
> > > +void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state,
> > > struct cmdq_pkt *cmdq_pkt);
> > > void mtk_aal_start(struct device *dev);
> > > void mtk_aal_stop(struct device *dev);
> > >
> > > @@ -50,8 +50,9 @@ void mtk_dither_set_common(void __iomem *regs, struct
> > > cmdq_client_reg *cmdq_reg,
> > > void mtk_gamma_config(struct device *dev, unsigned int w,
> > > unsigned int h, unsigned int vrefresh,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > > -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state);
> > > -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state
> > > *state);
> > > +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state,
> > > struct cmdq_pkt *cmdq_pkt);
> > > +void mtk_gamma_set_common(void __iomem *regs, struct cmdq_client_reg
> > > *cmdq_reg,
> > > + struct drm_crtc_state *state, struct cmdq_pkt
> > > *cmdq_pkt);
> > > void mtk_gamma_start(struct device *dev);
> > >
Re: [PATCH v1] drm/mediatek: adjust rdma fifo threshold calculate formula
Hi, Yongqiang: On Mon, 2021-04-12 at 15:25 +0800, Yongqiang Niu wrote: > the orginal formula will caused rdma fifo threshold config overflow > > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index 728aaad..8c9371b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -167,7 +167,7 @@ void mtk_rdma_config(struct device *dev, unsigned int > width, >* output threshold to 6 microseconds with 7/6 overhead to >* account for blanking, and with a pixel depth of 4 bytes: >*/ > - threshold = width * height * vrefresh * 4 * 7 / 100; > + threshold = rdma_fifo_size * 7 / 10; It's better to set threshold by width and height, but it seems that no one could come out a solution for all SoC. I could just accept this solution, but I need some addition comment for this solution. How do you decide 7/10? In the future, another may need to modify this value and he need to know why you use 7/10. If you just choose it at random, just tell us that you just randomly choose it. Regards, CK > reg = RDMA_FIFO_UNDERFLOW_EN | > RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
Re: [PATCH v1, 3/3] drm/mediatek: gamma set with cmdq
Hi, Yongqiang:
On Mon, 2021-04-12 at 14:35 +0800, Yongqiang Niu wrote:
> gamma lut set in vsync active will caused display flash issue
> set gamma lut with cmdq
In MT8173, it's ok to set gammma out of vblank period. Why do you
setting gamma in vblank in this patch?
Regards,
CK
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_aal.c | 4 ++--
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 ---
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 11 ++-
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 8 +---
> 5 files changed, 28 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> index 64b4528..c8e178e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> @@ -59,12 +59,12 @@ void mtk_aal_config(struct device *dev, unsigned int w,
> mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, aal->regs,
> DISP_AAL_SIZE);
> }
>
> -void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
> +void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state,
> struct cmdq_pkt *cmdq_pkt)
> {
> struct mtk_disp_aal *aal = dev_get_drvdata(dev);
>
> if (aal->data && aal->data->has_gamma)
> - mtk_gamma_set_common(aal->regs, state);
> + mtk_gamma_set_common(aal->regs, >cmdq_reg, state,
> cmdq_pkt);
> }
>
> void mtk_aal_start(struct device *dev)
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 86c3068..c2e7dcb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -14,7 +14,7 @@
> void mtk_aal_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> -void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state);
> +void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state,
> struct cmdq_pkt *cmdq_pkt);
> void mtk_aal_start(struct device *dev);
> void mtk_aal_stop(struct device *dev);
>
> @@ -50,8 +50,9 @@ void mtk_dither_set_common(void __iomem *regs, struct
> cmdq_client_reg *cmdq_reg,
> void mtk_gamma_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state);
> -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
> +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state, struct
> cmdq_pkt *cmdq_pkt);
> +void mtk_gamma_set_common(void __iomem *regs, struct cmdq_client_reg
> *cmdq_reg,
> + struct drm_crtc_state *state, struct cmdq_pkt
> *cmdq_pkt);
> void mtk_gamma_start(struct device *dev);
> void mtk_gamma_stop(struct device *dev);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> index 3ebf91e..99a4ff3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> @@ -55,7 +55,8 @@ void mtk_gamma_clk_disable(struct device *dev)
> clk_disable_unprepare(gamma->clk);
> }
>
> -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state)
> +void mtk_gamma_set_common(void __iomem *regs, struct cmdq_client_reg
> *cmdq_reg,
> + struct drm_crtc_state *state, struct cmdq_pkt
> *cmdq_pkt)
> {
> unsigned int i, reg;
> struct drm_color_lut *lut;
> @@ -65,23 +66,23 @@ void mtk_gamma_set_common(void __iomem *regs, struct
> drm_crtc_state *state)
> if (state->gamma_lut) {
> reg = readl(regs + DISP_GAMMA_CFG);
> reg = reg | GAMMA_LUT_EN;
> - writel(reg, regs + DISP_GAMMA_CFG);
> + mtk_ddp_write(cmdq_pkt, reg, cmdq_reg, regs, DISP_GAMMA_CFG);
> lut_base = regs + DISP_GAMMA_LUT;
> lut = (struct drm_color_lut *)state->gamma_lut->data;
> for (i = 0; i < MTK_LUT_SIZE; i++) {
> word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
> (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
> ((lut[i].blue >> 6) & LUT_10BIT_MASK);
> - writel(word, (lut_base + i * 4));
> + mtk_ddp_write(cmdq_pkt, word, cmdq_reg, regs, (lut_base
> + i * 4));
> }
> }
> }
>
> -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state)
> +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state, struct
> cmdq_pkt *cmdq_pkt)
> {
> struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
>
> -
Re: [PATCH v1, 1/3] drm/mediatek: Separate aal module
Hi, Yongqiang:
On Mon, 2021-04-12 at 14:35 +0800, Yongqiang Niu wrote:
> mt8183 aal has no gamma function
Separate this patch to two patch: one is add has_gamma config in aal.
another one is add mt8183 aal support.
Regards,
CK
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_aal.c | 167
>
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 39 +--
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 6 files changed, 187 insertions(+), 40 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_aal.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index dc54a7a..29098d7 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -mediatek-drm-y := mtk_disp_ccorr.o \
> +mediatek-drm-y := mtk_disp_aal.o \
> + mtk_disp_ccorr.o \
> mtk_disp_color.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> new file mode 100644
> index 000..64b4528
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> @@ -0,0 +1,167 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_AAL_EN 0x
> +#define AAL_EN BIT(0)
> +#define DISP_AAL_SIZE0x0030
> +
> +
> +struct mtk_disp_aal_data {
> + bool has_gamma;
> +};
> +
> +/**
> + * struct mtk_disp_aal - DISP_AAL driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_aal {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> + const struct mtk_disp_aal_data *data;
> +};
> +
> +int mtk_aal_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(aal->clk);
> +}
> +
> +void mtk_aal_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(aal->clk);
> +}
> +
> +void mtk_aal_config(struct device *dev, unsigned int w,
> +unsigned int h, unsigned int vrefresh,
> +unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, aal->regs,
> DISP_AAL_SIZE);
> +}
> +
> +void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
> +{
> + struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> +
> + if (aal->data && aal->data->has_gamma)
> + mtk_gamma_set_common(aal->regs, state);
> +}
> +
> +void mtk_aal_start(struct device *dev)
> +{
> + struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> +
> + writel(AAL_EN, aal->regs + DISP_AAL_EN);
> +}
> +
> +void mtk_aal_stop(struct device *dev)
> +{
> + struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, aal->regs + DISP_AAL_EN);
> +}
> +
> +static int mtk_disp_aal_bind(struct device *dev, struct device *master,
> +void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_disp_aal_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_aal_component_ops = {
> + .bind = mtk_disp_aal_bind,
> + .unbind = mtk_disp_aal_unbind,
> +};
> +
> +static int mtk_disp_aal_probe(struct platform_device *pdev)
> +{
> + struct device *dev = >dev;
> + struct mtk_disp_aal *priv;
> + struct resource *res;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(priv->clk)) {
> + dev_err(dev, "failed to get aal clk\n");
> + return PTR_ERR(priv->clk);
> + }
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->regs = devm_ioremap_resource(dev, res);
> + if (IS_ERR(priv->regs)) {
> + dev_err(dev, "failed to ioremap aal\n");
> + return PTR_ERR(priv->regs);
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, >cmdq_reg, 0);
> + if (ret)
> +
Re: [PATCH 3/3] drm/mediatek: dpi: add bus format negociation
Hi, Jitao:
On Tue, 2021-03-30 at 23:53 +0800, Jitao Shi wrote:
> Add the atomic_get_output_bus_fmts, atomic_get_input_bus_fmts to negociate
> the possible output and input formats for the current mode and monitor,
> and use the negotiated formats in a basic atomic_check callback.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 96
> --
> 1 file changed, 91 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 87bb27649c4c..4e45d1b01b0c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -81,6 +81,8 @@ struct mtk_dpi {
> struct pinctrl *pinctrl;
> struct pinctrl_state *pins_gpio;
> struct pinctrl_state *pins_dpi;
> + unsigned int in_bus_format;
> + unsigned int out_bus_format;
Why do you keep these two value? You does not use them.
> bool ddr_edge_sel;
> int refcount;
> };
> @@ -534,6 +536,92 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> return 0;
> }
>
> +#define MAX_OUTPUT_SEL_FORMATS 2
> +
> +static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge
> *bridge,
> + struct drm_bridge_state *bridge_state,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state,
> + unsigned int *num_output_fmts)
> +{
> + struct drm_display_mode *mode = _state->mode;
> + u32 *output_fmts;
> + struct mtk_dpi *dpi = bridge_to_dpi(bridge);
> +
> + *num_output_fmts = 0;
> +
> + output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
> + GFP_KERNEL);
> + if (!output_fmts)
> + return NULL;
> +
> + /* Default 8bit RGB fallback */
> + if (dpi->conf->dual_edge) {
> + output_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE;
> + output_fmts[1] = MEDIA_BUS_FMT_RGB888_2X12_BE;
So mt8183 does not support MEDIA_BUS_FMT_RGB888_1X24?
> + *num_output_fmts = 2;
> + } else {
> + output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
> + *num_output_fmts = 1;
> + }
> +
> + return output_fmts;
> +}
> +
> +#define MAX_INPUT_SEL_FORMATS1
> +
> +static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge
> *bridge,
> + struct drm_bridge_state *bridge_state,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state,
> + u32 output_fmt,
> + unsigned int *num_input_fmts)
> +{
> + u32 *input_fmts;
> +
> + *num_input_fmts = 0;
> +
> + input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
> + GFP_KERNEL);
> + if (!input_fmts)
> + return NULL;
> +
> + *num_input_fmts = 1;
> + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
> +
> + return input_fmts;
> +}
> +
> +static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge,
> +struct drm_bridge_state *bridge_state,
> +struct drm_crtc_state *crtc_state,
> +struct drm_connector_state *conn_state)
> +{
> + struct mtk_dpi *dpi = bridge->driver_private;
> +
> + dpi->out_bus_format = bridge_state->output_bus_cfg.format;
> +
> + dpi->in_bus_format = bridge_state->input_bus_cfg.format;
> +
> + dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n",
> + bridge_state->input_bus_cfg.format,
> + bridge_state->output_bus_cfg.format);
> +
> + if (dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_LE ||
> + dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_BE) {
I think you could remove this 'if' checking.
Regards,
CK.
> + dpi->ddr_edge_sel =
> + (dpi->out_bus_format == MEDIA_BUS_FMT_RGB888_2X12_LE) ?
> + true : false;
> + }
> +
> + dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
> + dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
> + dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
> + dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
> +
> + return 0;
> +}
> +
> static int mtk_dpi_bridge_attach(struct drm_bridge *bridge,
>enum drm_bridge_attach_flags flags)
> {
> @@ -572,6 +660,9 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs
> = {
> .mode_set = mtk_dpi_bridge_mode_set,
> .disable = mtk_dpi_bridge_disable,
> .enable = mtk_dpi_bridge_enable,
> + .atomic_check = mtk_dpi_bridge_atomic_check,
> + .atomic_get_output_bus_fmts =
Re: [PATCH v6 8/8] drm/mediatek: add support for mediatek SOC MT8192
Hi, Hsin-Yi:
On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> add support for mediatek SOC MT8192
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6
> drivers/gpu/drm/mediatek/mtk_drm_drv.c| 42 +++
> 4 files changed, 74 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> index 141cb36b9c07b..3a53ebc4e1724 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -205,9 +205,15 @@ static const struct mtk_disp_ccorr_data
> mt8183_ccorr_driver_data = {
> .matrix_bits = 10,
> };
>
> +static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = {
> + .matrix_bits = 11,
> +};
> +
> static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
> { .compatible = "mediatek,mt8183-disp-ccorr",
> .data = _ccorr_driver_data},
> + { .compatible = "mediatek,mt8192-disp-ccorr",
> + .data = _ccorr_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 961f87f8d4d15..e266baae586c4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -455,6 +455,22 @@ static const struct mtk_disp_ovl_data
> mt8183_ovl_2l_driver_data = {
> .fmt_rgb565_is_0 = true,
> };
>
> +static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 4,
> + .fmt_rgb565_is_0 = true,
> + .smi_id_en = true,
> +};
> +
> +static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 2,
> + .fmt_rgb565_is_0 = true,
> + .smi_id_en = true,
> +};
> +
> static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-ovl",
> .data = _ovl_driver_data},
> @@ -464,6 +480,10 @@ static const struct of_device_id
> mtk_disp_ovl_driver_dt_match[] = {
> .data = _ovl_driver_data},
> { .compatible = "mediatek,mt8183-disp-ovl-2l",
> .data = _ovl_2l_driver_data},
> + { .compatible = "mediatek,mt8192-disp-ovl",
> + .data = _ovl_driver_data},
> + { .compatible = "mediatek,mt8192-disp-ovl-2l",
> + .data = _ovl_2l_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 728aaadfea8cf..f123fc00a3935 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data
> mt8183_rdma_driver_data = {
> .fifo_size = 5 * SZ_1K,
> };
>
> +static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
> + .fifo_size = 5 * SZ_1K,
> +};
> +
> static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = _rdma_driver_data},
> @@ -362,6 +366,8 @@ static const struct of_device_id
> mtk_disp_rdma_driver_dt_match[] = {
> .data = _rdma_driver_data},
> { .compatible = "mediatek,mt8183-disp-rdma",
> .data = _rdma_driver_data},
> + { .compatible = "mediatek,mt8192-disp-rdma",
> + .data = _rdma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b013d56d27773..6df551055630c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -147,6 +147,25 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] =
> {
> DDP_COMPONENT_DPI0,
> };
>
> +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_OVL_2L0,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_POSTMASK0,
>
Re: [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr
Hi, Hsin-Yi:
On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add matrix_bits and coeffs_precision to ccorr private data:
> - matrix bits of mt8183 is 10
> - matrix bits of mt8192 is 11
>
Reviewed-by: CK Hu
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++-
> 1 file changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> index 6c86673a835c3..141cb36b9c07b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -30,7 +30,7 @@
> #define DISP_CCORR_COEF_40x0090
>
> struct mtk_disp_ccorr_data {
> - u32 reserved;
> + u32 matrix_bits;
> };
>
> /**
> @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev)
> writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
> }
>
> -/* Converts a DRM S31.32 value to the HW S1.10 format. */
> -static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> +/* Converts a DRM S31.32 value to the HW S1.n format. */
> +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
> {
> u16 r;
>
> /* Sign bit. */
> - r = in & BIT_ULL(63) ? BIT(11) : 0;
> + r = in & BIT_ULL(63) ? BIT(n + 1) : 0;
>
> if ((in & GENMASK_ULL(62, 33)) > 0) {
> - /* identity value 0x1 -> 0x400, */
> + /* identity value 0x1 -> 0x400(mt8183), */
> + /* identity value 0x1 -> 0x800(mt8192), */
> /* if bigger this, set it to max 0x7ff. */
> - r |= GENMASK(10, 0);
> + r |= GENMASK(n, 0);
> } else {
> - /* take the 11 most important bits. */
> - r |= (in >> 22) & GENMASK(10, 0);
> + /* take the n+1 most important bits. */
> + r |= (in >> (32 - n)) & GENMASK(n, 0);
> }
>
> return r;
> @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct
> drm_crtc_state *state)
> uint16_t coeffs[9] = { 0 };
> int i;
> struct cmdq_pkt *cmdq_pkt = NULL;
> + u32 matrix_bits = ccorr->data->matrix_bits;
>
> if (!blob)
> return;
> @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct
> drm_crtc_state *state)
> input = ctm->matrix;
>
> for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits);
>
> mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> >cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);
> @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device
> *pdev)
> return 0;
> }
>
> +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
> + .matrix_bits = 10,
> +};
> +
> static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
> - { .compatible = "mediatek,mt8183-disp-ccorr"},
> + { .compatible = "mediatek,mt8183-disp-ccorr",
> + .data = _ccorr_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK
Hi, Hsin-Yi:
On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add component POSTMASK.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> 2 files changed, 73 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index b6c4e73031ca6..0a84ae53eb72a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -64,6 +64,12 @@
>
> #define AAL_EN BIT(0)
>
> +#define DISP_POSTMASK_EN 0x
> +#define POSTMASK_EN BIT(0)
> +#define DISP_POSTMASK_CFG0x0020
> +#define POSTMASK_RELAY_MODE BIT(0)
> +#define DISP_POSTMASK_SIZE 0x0030
> +
> #define DISP_DITHERING BIT(2)
> #define DITHER_LSB_ERR_SHIFT_R(x)(((x) & 0x7) << 28)
> #define DITHER_OVFLW_BIT_R(x)(((x) & 0x7) << 24)
> @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev)
> writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> }
>
> +void mtk_postmask_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, priv->regs,
> + DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, >cmdq_reg,
> + priv->regs, DISP_POSTMASK_CFG);
> +}
> +
> +void mtk_postmask_start(struct device *dev)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> +void mtk_postmask_stop(struct device *dev)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> static void mtk_aal_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
> .bgclr_in_off = mtk_ovl_bgclr_in_off,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_postmask = {
> + .clk_enable = mtk_ddp_clk_enable,
> + .clk_disable = mtk_ddp_clk_disable,
> + .config = mtk_postmask_config,
> + .start = mtk_postmask_start,
> + .stop = mtk_postmask_stop,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_rdma = {
> .clk_enable = mtk_rdma_clk_enable,
> .clk_disable = mtk_rdma_clk_disable,
> @@ -448,6 +488,7 @@ static const char * const
> mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> [MTK_DISP_BLS] = "bls",
> + [MTK_DISP_POSTMASK] = "postmask",
> };
>
> struct mtk_ddp_comp_match {
> @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match {
> };
>
> static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX]
> = {
> - [DDP_COMPONENT_AAL0]= { MTK_DISP_AAL, 0, _aal },
> - [DDP_COMPONENT_AAL1]= { MTK_DISP_AAL, 1, _aal },
> - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, _ccorr },
> - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, _color },
> - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, _color },
> - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER,0, _dither },
> - [DDP_COMPONENT_DPI0]= { MTK_DPI,0, _dpi },
> - [DDP_COMPONENT_DPI1]= { MTK_DPI,1, _dpi },
> - [DDP_COMPONENT_DSI0]= { MTK_DSI,0, _dsi },
> - [DDP_COMPONENT_DSI1]= { MTK_DSI,1, _dsi },
> - [DDP_COMPONENT_DSI2]= { MTK_DSI,2, _dsi },
> - [DDP_COMPONENT_DSI3]= { MTK_DSI,3, _dsi },
> - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, _gamma },
> - [DDP_COMPONENT_OD0] = { MTK_DISP_OD,0, _od },
> - [DDP_COMPONENT_OD1] = { MTK_DISP_OD,1, _od },
> - [DDP_COMPONENT_OVL0]= { MTK_DISP_OVL,
Re: [PATCH v5 6/8] drm/mediatek: add matrix_bits private data for ccorr
Hi, Hsin-Yi:
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add matrix_bits and coeffs_precision to ccorr private data:
> - matrix bits of mt8183 is 10
> - matrix bits of mt8192 is 11
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 34 ---
> 1 file changed, 24 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> index 6c86673a835c3..fb86f3a8b3a18 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -29,8 +29,10 @@
> #define DISP_CCORR_COEF_30x008C
> #define DISP_CCORR_COEF_40x0090
>
> +#define CCORR_MATRIX_BITS10
> +
> struct mtk_disp_ccorr_data {
> - u32 reserved;
> + u32 matrix_bits;
> };
>
> /**
> @@ -85,21 +87,22 @@ void mtk_ccorr_stop(struct device *dev)
> writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
> }
>
> -/* Converts a DRM S31.32 value to the HW S1.10 format. */
> -static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> +/* Converts a DRM S31.32 value to the HW S1.n format. */
> +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
> {
> u16 r;
>
> /* Sign bit. */
> - r = in & BIT_ULL(63) ? BIT(11) : 0;
> + r = in & BIT_ULL(63) ? BIT(n + 1) : 0;
>
> if ((in & GENMASK_ULL(62, 33)) > 0) {
> - /* identity value 0x1 -> 0x400, */
> + /* identity value 0x1 -> 0x400(mt8183), */
> + /* identity value 0x1 -> 0x800(mt8192), */
> /* if bigger this, set it to max 0x7ff. */
> - r |= GENMASK(10, 0);
> + r |= GENMASK(n, 0);
> } else {
> - /* take the 11 most important bits. */
> - r |= (in >> 22) & GENMASK(10, 0);
> + /* take the n+1 most important bits. */
> + r |= (in >> (32 - n)) & GENMASK(n, 0);
> }
>
> return r;
> @@ -114,6 +117,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct
> drm_crtc_state *state)
> uint16_t coeffs[9] = { 0 };
> int i;
> struct cmdq_pkt *cmdq_pkt = NULL;
> + u32 matrix_bits;
>
> if (!blob)
> return;
> @@ -121,8 +125,13 @@ void mtk_ccorr_ctm_set(struct device *dev, struct
> drm_crtc_state *state)
> ctm = (struct drm_color_ctm *)blob->data;
> input = ctm->matrix;
>
> + if (ccorr->data)
ccorr->data is always true, isn't it?
> + matrix_bits = ccorr->data->matrix_bits;
> + else
> + matrix_bits = CCORR_MATRIX_BITS;
> +
> for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits);
>
> mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> >cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);
> @@ -199,8 +208,13 @@ static int mtk_disp_ccorr_remove(struct platform_device
> *pdev)
> return 0;
> }
>
> +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
> + .matrix_bits = CCORR_MATRIX_BITS,
Drop CCORR_MATRIX_BITS and use 10 here.
> +};
> +
> static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
> - { .compatible = "mediatek,mt8183-disp-ccorr"},
> + { .compatible = "mediatek,mt8183-disp-ccorr",
> + .data = _ccorr_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
Re: [PATCH v5 5/8] drm/mediatek: Fix ccorr size config
Hi, Hsin-Yi:
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Fix setting to follow hardware datasheet. The original error setting
> affects mt8192 display.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> index 6ee2431e6b843..6c86673a835c3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -65,7 +65,7 @@ void mtk_ccorr_config(struct device *dev, unsigned int w,
> {
> struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
>
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, ccorr->regs,
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, ccorr->regs,
> DISP_CCORR_SIZE);
> mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, >cmdq_reg, ccorr->regs,
> DISP_CCORR_CFG);
Re: [PATCH v5 4/8] drm/mediatek: separate ccorr module
Hi, Hsin-Yi:
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> ccorr ctm matrix bits will be different in mt8192
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 6 files changed, 236 insertions(+), 96 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index 13a0eafabf9c0..f119bef6d6e66 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -mediatek-drm-y := mtk_disp_color.o \
> +mediatek-drm-y := mtk_disp_ccorr.o \
> + mtk_disp_color.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> mtk_disp_postmask.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> new file mode 100644
> index 0..6ee2431e6b843
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -0,0 +1,216 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_CCORR_EN0x
> +#define CCORR_EN BIT(0)
> +#define DISP_CCORR_CFG 0x0020
> +#define CCORR_RELAY_MODE BIT(0)
> +#define CCORR_ENGINE_EN BIT(1)
> +#define CCORR_GAMMA_OFF BIT(2)
> +#define CCORR_WGAMUT_SRC_CLIPBIT(3)
> +#define DISP_CCORR_SIZE 0x0030
> +#define DISP_CCORR_COEF_00x0080
> +#define DISP_CCORR_COEF_10x0084
> +#define DISP_CCORR_COEF_20x0088
> +#define DISP_CCORR_COEF_30x008C
> +#define DISP_CCORR_COEF_40x0090
> +
> +struct mtk_disp_ccorr_data {
> + u32 reserved;
> +};
> +
> +/**
> + * struct mtk_disp_ccorr - DISP_CCORR driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_ccorr {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> + const struct mtk_disp_ccorr_data*data;
> +};
> +
> +int mtk_ccorr_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(ccorr->clk);
> +}
> +
> +void mtk_ccorr_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(ccorr->clk);
> +}
> +
> +void mtk_ccorr_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, ccorr->regs,
> + DISP_CCORR_SIZE);
> + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, >cmdq_reg, ccorr->regs,
> + DISP_CCORR_CFG);
> +}
> +
> +void mtk_ccorr_start(struct device *dev)
> +{
> + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
> +
> + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN);
> +}
> +
> +void mtk_ccorr_stop(struct device *dev)
> +{
> + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
> +}
> +
> +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> +{
> + u16 r;
> +
> + /* Sign bit. */
> + r = in & BIT_ULL(63) ? BIT(11) : 0;
> +
> + if ((in & GENMASK_ULL(62, 33)) > 0) {
> + /* identity value 0x10
Re: [PATCH v5 2/8] drm/mediatek: add component POSTMASK
Hi, Hsin-Yi:
It looks like that postmask driver could be placed in mtk_drm_ddp_comp.c
and this patch would much smaller.
Regards,
CK
On Mon, 2021-02-01 at 18:37 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add component POSTMASK.
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/Makefile| 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 149 +++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 71 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 7 files changed, 204 insertions(+), 31 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index b64674b944860..13a0eafabf9c0 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -3,6 +3,7 @@
> mediatek-drm-y := mtk_disp_color.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> + mtk_disp_postmask.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp_comp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index cdb0383f99061..06d4d4e1c0d05 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -37,6 +37,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct
> drm_crtc_state *state);
> void mtk_gamma_start(struct device *dev);
> void mtk_gamma_stop(struct device *dev);
>
> +int mtk_postmask_clk_enable(struct device *dev);
> +void mtk_postmask_clk_disable(struct device *dev);
> +void mtk_postmask_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_postmask_start(struct device *dev);
> +void mtk_postmask_stop(struct device *dev);
> +
> void mtk_ovl_bgclr_in_on(struct device *dev);
> void mtk_ovl_bgclr_in_off(struct device *dev);
> void mtk_ovl_bypass_shadow(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> new file mode 100644
> index 0..5a109fee6b238
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> @@ -0,0 +1,149 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_POSTMASK_EN 0x
> +#define POSTMASK_EN BIT(0)
> +#define DISP_POSTMASK_CFG0x0020
> +#define POSTMASK_RELAY_MODE BIT(0)
> +#define DISP_POSTMASK_SIZE 0x0030
> +
> +/**
> + * struct mtk_disp_postmask - DISP_postmask driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_postmask {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> +};
> +
> +int mtk_postmask_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(postmask->clk);
> +}
> +
> +void mtk_postmask_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(postmask->clk);
> +}
> +
> +void mtk_postmask_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg,
> postmask->regs,
> + DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, >cmdq_reg,
> + postmask->regs, DISP_POSTMASK_CFG);
> +}
> +
> +void mtk_postmask_start(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + writel(POSTMASK_EN, postmask->regs + DISP_POSTMASK_EN);
> +}
> +
> +void mtk_postmask_stop(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, postmask->regs + DISP_POSTMASK_EN);
> +}
> +
> +static int mtk_disp_postmask_bind(struct device *dev, struct device *master,
> void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_disp_postmask_unbind(struct device *dev, struct
Re: [PATCH v4 4/8] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch,
> ovl will hang up when more than 1 layer enabled.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index da7e38a28759b..961f87f8d4d15 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -24,6 +24,7 @@
> #define DISP_REG_OVL_RST 0x0014
> #define DISP_REG_OVL_ROI_SIZE0x0020
> #define DISP_REG_OVL_DATAPATH_CON0x0024
> +#define OVL_LAYER_SMI_ID_EN BIT(0)
> #define OVL_BGCLR_SEL_IN BIT(2)
> #define DISP_REG_OVL_ROI_BGCLR 0x0028
> #define DISP_REG_OVL_SRC_CON 0x002c
> @@ -62,6 +63,7 @@ struct mtk_disp_ovl_data {
> unsigned int gmc_bits;
> unsigned int layer_nr;
> bool fmt_rgb565_is_0;
> + bool smi_id_en;
> };
>
> /**
> @@ -134,6 +136,13 @@ void mtk_ovl_start(struct device *dev)
> {
> struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
>
> + if (ovl->data->smi_id_en) {
> + unsigned int reg;
> +
> + reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg | OVL_LAYER_SMI_ID_EN;
> + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> + }
> writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
> }
>
> @@ -142,6 +151,14 @@ void mtk_ovl_stop(struct device *dev)
> struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
>
> writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
> + if (ovl->data->smi_id_en) {
> + unsigned int reg;
> +
> + reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg & ~OVL_LAYER_SMI_ID_EN;
> + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> + }
> +
> }
>
> void mtk_ovl_config(struct device *dev, unsigned int w,
Re: [PATCH v4 7/8] soc: mediatek: add mtk mutex support for MT8192
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8192 SoC.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mtk-mutex.c | 35
> 1 file changed, 35 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index 718a41beb6afb..dfd9806d5a001 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -39,6 +39,18 @@
> #define MT8167_MUTEX_MOD_DISP_DITHER 15
> #define MT8167_MUTEX_MOD_DISP_UFOE 16
>
> +#define MT8192_MUTEX_MOD_DISP_OVL0 0
> +#define MT8192_MUTEX_MOD_DISP_OVL0_2L1
> +#define MT8192_MUTEX_MOD_DISP_RDMA0 2
> +#define MT8192_MUTEX_MOD_DISP_COLOR0 4
> +#define MT8192_MUTEX_MOD_DISP_CCORR0 5
> +#define MT8192_MUTEX_MOD_DISP_AAL0 6
> +#define MT8192_MUTEX_MOD_DISP_GAMMA0 7
> +#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
> +#define MT8192_MUTEX_MOD_DISP_DITHER09
> +#define MT8192_MUTEX_MOD_DISP_OVL2_2L16
> +#define MT8192_MUTEX_MOD_DISP_RDMA4 17
> +
> #define MT8183_MUTEX_MOD_DISP_RDMA0 0
> #define MT8183_MUTEX_MOD_DISP_RDMA1 1
> #define MT8183_MUTEX_MOD_DISP_OVL0 9
> @@ -214,6 +226,20 @@ static const unsigned int
> mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> };
>
> +static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
> + [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
> + [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
> +};
> +
> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> @@ -275,6 +301,13 @@ static const struct mtk_mutex_data
> mt8183_mutex_driver_data = {
> .no_clk = true,
> };
>
> +static const struct mtk_mutex_data mt8192_mutex_driver_data = {
> + .mutex_mod = mt8192_mutex_mod,
> + .mutex_sof = mt8183_mutex_sof,
> + .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -507,6 +540,8 @@ static const struct of_device_id mutex_driver_dt_match[]
> = {
> .data = _mutex_driver_data},
> { .compatible = "mediatek,mt8183-disp-mutex",
> .data = _mutex_driver_data},
> + { .compatible = "mediatek,mt8192-disp-mutex",
> + .data = _mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
Re: [PATCH v4 2/8] drm/mediatek: add component POSTMASK
Hi, Hsin-Yi:
On Fri, 2021-01-29 at 15:34 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> This patch add component POSTMASK,
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/Makefile| 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 161 +++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 7 files changed, 186 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index b64674b944860..13a0eafabf9c0 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -3,6 +3,7 @@
> mediatek-drm-y := mtk_disp_color.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> + mtk_disp_postmask.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp_comp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 02191010699f8..d74e85db3fcdf 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -37,6 +37,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct
> drm_crtc_state *state);
> void mtk_gamma_start(struct device *dev);
> void mtk_gamma_stop(struct device *dev);
>
> +int mtk_postmask_clk_enable(struct device *dev);
> +void mtk_postmask_clk_disable(struct device *dev);
> +void mtk_postmask_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_postmask_start(struct device *dev);
> +void mtk_postmask_stop(struct device *dev);
> +
> void mtk_ovl_bgclr_in_on(struct device *dev);
> void mtk_ovl_bgclr_in_off(struct device *dev);
> void mtk_ovl_bypass_shadow(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> new file mode 100644
> index 0..d640cef9c15a4
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> @@ -0,0 +1,161 @@
> +/*
> + * SPDX-License-Identifier:
> + *
> + * Copyright (c) 2020 MediaTek Inc.
2021
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_POSTMASK_EN 0x
> +#define POSTMASK_EN BIT(0)
> +#define DISP_POSTMASK_CFG0x0020
> +#define POSTMASK_RELAY_MODE BIT(0)
> +#define DISP_POSTMASK_SIZE 0x0030
> +
> +struct mtk_disp_postmask_data {
> + u32 reserved;
> +};
Useless, so remove.
> +
> +/**
> + * struct mtk_disp_postmask - DISP_postmask driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_postmask {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> + const struct mtk_disp_postmask_data *data;
> +};
> +
> +int mtk_postmask_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(postmask->clk);
> +}
> +
> +void mtk_postmask_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(postmask->clk);
> +}
> +
> +void mtk_postmask_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg,
> postmask->regs,
> + DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, >cmdq_reg,
> + postmask->regs, DISP_POSTMASK_CFG);
> +}
> +
> +void mtk_postmask_start(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + writel(POSTMASK_EN, postmask->regs + DISP_POSTMASK_EN);
> +}
> +
> +void mtk_postmask_stop(struct device *dev)
> +{
> + struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, postmask->regs + DISP_POSTMASK_EN);
> +}
> +
> +static int mtk_disp_postmask_bind(struct device *dev, struct device *master,
> void *data)
> +{
> + return 0;
> +}
> +
> +static void
Re: [PATCH v12 6/8] drm/mediatek: enable dither function
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> for 5 or 6 bpc panel, we need enable dither function
> to improve the display quality
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index ac2cb25620357..6c8f246380a74 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -53,6 +53,7 @@
> #define DITHER_ENBIT(0)
> #define DISP_DITHER_CFG 0x0020
> #define DITHER_RELAY_MODEBIT(0)
> +#define DITHER_ENGINE_EN BIT(1)
> #define DISP_DITHER_SIZE 0x0030
>
> #define LUT_10BIT_MASK 0x03ff
> @@ -314,9 +315,19 @@ static void mtk_dither_config(struct device *dev,
> unsigned int w,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> + bool enable = (bpc == 5 || bpc == 6);
I strongly believe that dither function in dither is identical to the
one in gamma and od, and in mtk_dither_set_common(), 'bpc >=
MTK_MIN_BPC' is valid, so I believe we need not to limit bpc to 5 or 6.
But we should consider the case that bpc is invalid in
mtk_dither_set_common(). Invalid case in gamma and od use different way
to process. For gamma, dither is default relay mode, so invalid bpc
would do nothing in mtk_dither_set_common() and result in relay mode.
For od, it set to relay mode first, them invalid bpc would do nothing in
mtk_dither_set_common() and result in relay mode. I would like dither,
gamma and od to process invalid bpc in the same way. One solution is to
set relay mode in mtk_dither_set_common() for invalid bpc.
Regards,
CK
>
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, priv->regs,
> DISP_DITHER_SIZE);
> - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg, priv->regs,
> DISP_DITHER_CFG);
> + if (enable) {
> + mtk_dither_set_common(priv->regs, >cmdq_reg, bpc,
> + DISP_DITHER_CFG, DITHER_ENGINE_EN,
> + cmdq_pkt);
> + } else {
> + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg,
> + priv->regs, DISP_DITHER_CFG);
> + }
> +
> + mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, priv->regs,
> + DISP_DITHER_SIZE);
> }
>
> static void mtk_dither_start(struct device *dev)
Re: [PATCH v12 7/8] soc: mediatek: add mtk mutex support for MT8183
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8183 SoC.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50
> 1 file changed, 50 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index f531b119da7a9..718a41beb6afb 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -14,6 +14,8 @@
>
> #define MT2701_MUTEX0_MOD0 0x2c
> #define MT2701_MUTEX0_SOF0 0x30
> +#define MT8183_MUTEX0_MOD0 0x30
> +#define MT8183_MUTEX0_SOF0 0x2c
>
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n)(0x24 + 0x20 * (n))
> @@ -37,6 +39,18 @@
> #define MT8167_MUTEX_MOD_DISP_DITHER 15
> #define MT8167_MUTEX_MOD_DISP_UFOE 16
>
> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0
> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1
> +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L10
> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L11
> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12
> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> +#define MT8183_MUTEX_MOD_DISP_DITHER017
> +
> #define MT8173_MUTEX_MOD_DISP_OVL0 11
> #define MT8173_MUTEX_MOD_DISP_OVL1 12
> #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> @@ -87,6 +101,11 @@
> #define MT2712_MUTEX_SOF_DSI36
> #define MT8167_MUTEX_SOF_DPI02
> #define MT8167_MUTEX_SOF_DPI13
> +#define MT8183_MUTEX_SOF_DSI01
> +#define MT8183_MUTEX_SOF_DPI02
> +
> +#define MT8183_MUTEX_EOF_DSI0(MT8183_MUTEX_SOF_DSI0
> << 6)
> +#define MT8183_MUTEX_EOF_DPI0(MT8183_MUTEX_SOF_DPI0
> << 6)
>
> struct mtk_mutex {
> int id;
> @@ -181,6 +200,20 @@ static const unsigned int
> mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> };
>
> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> +};
> +
> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> @@ -198,6 +231,13 @@ static const unsigned int
> mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> };
>
> +/* Add EOF setting so overlay hardware can receive frame done irq */
> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data
> mt8173_mutex_driver_data = {
> .mutex_sof_reg = MT2701_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> + .mutex_mod = mt8183_mutex_mod,
> + .mutex_sof = mt8183_mutex_sof,
> + .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> + .no_clk = true,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[]
> = {
> .data = _mutex_driver_data},
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = _mutex_driver_data},
> + { .compatible = "mediatek,mt8183-disp-mutex",
> + .data = _mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
Re: [PATCH v11 7/9] drm/mediatek: enable dither function
On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote:
> On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu
> wrote:
> >
> > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
> > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
> > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
> > > > > Hi, Hsin-Yi:
> > > > >
> > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> > > > > > From: Yongqiang Niu
> > > > > >
> > > > > > for 5 or 6 bpc panel, we need enable dither function
> > > > > > to improve the display quality
> > > > > >
> > > > > > Signed-off-by: Yongqiang Niu
> > > > > > Signed-off-by: Hsin-Yi Wang
> > > > > > ---
> > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44
> > > > > > -
> > > > > > 1 file changed, 43 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > index 8173f709272be..e85625704d611 100644
> > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > @@ -53,7 +53,9 @@
> > > > > > #define DITHER_EN BIT(0)
> > > > > > #define DISP_DITHER_CFG0x0020
> > > > > > #define DITHER_RELAY_MODE BIT(0)
> > > > > > +#define DITHER_ENGINE_EN BIT(1)
> > > > > > #define DISP_DITHER_SIZE 0x0030
> > > > > > +#define DITHER_REG(idx)(0x100 +
> > > > > > (idx) * 4)
> > > > > >
> > > > > > #define LUT_10BIT_MASK 0x03ff
> > > > > >
> > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device
> > > > > > *dev, unsigned int w,
> > > > > > {
> > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > > > > >
> > > > > > + bool enable = false;
> > > > > > +
> > > > > > + /* default value for dither reg 5 to 14 */
> > > > > > + const u32 dither_setting[] = {
> > > > > > + 0x, /* 5 */
> > > > > > + 0x3002, /* 6 */
> > > > > > + 0x, /* 7 */
> > > > > > + 0x, /* 8 */
> > > > > > + 0x, /* 9 */
> > > > > > + 0x, /* 10 */
> > > > > > + 0x, /* 11 */
> > > > > > + 0x0011, /* 12 */
> > > > > > + 0x, /* 13 */
> > > > > > + 0x, /* 14 */
> > > > >
> > > > > Could you explain what is this?
> > > >
> > > > this is dither 5 to dither 14 setting
> > > > this will be useless, we just need set dither 5 and dither 7 like
> > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
> > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
> > > > other value is same with hardware default value.
> > > >
> > > >
> > > > >
> > > > > > + };
> > > > > > +
> > > > > > + if (bpc == 5 || bpc == 6) {
> > > > > > + enable = true;
> > > > > > + mtk_ddp_write(cmdq_pkt,
> > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC -
> > > > > > bpc) |
> > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC -
> > > > > > bpc) |
> > > > > > + DITHER_NEW_BIT_MODE,
> > > > > > + >cmdq_reg, priv->regs,
> > > > > > DITHER_REG(15));
> > > > > > + mtk_ddp_write(cmdq_pkt,
> > > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC -
> > > > > > bpc) |
> > > > > >
Re: [PATCH v11 7/9] drm/mediatek: enable dither function
On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
> On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
> > Hi, Hsin-Yi:
> >
> > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> > > From: Yongqiang Niu
> > >
> > > for 5 or 6 bpc panel, we need enable dither function
> > > to improve the display quality
> > >
> > > Signed-off-by: Yongqiang Niu
> > > Signed-off-by: Hsin-Yi Wang
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 -
> > > 1 file changed, 43 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > index 8173f709272be..e85625704d611 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > @@ -53,7 +53,9 @@
> > > #define DITHER_ENBIT(0)
> > > #define DISP_DITHER_CFG 0x0020
> > > #define DITHER_RELAY_MODEBIT(0)
> > > +#define DITHER_ENGINE_EN BIT(1)
> > > #define DISP_DITHER_SIZE 0x0030
> > > +#define DITHER_REG(idx) (0x100 + (idx) * 4)
> > >
> > > #define LUT_10BIT_MASK 0x03ff
> > >
> > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev,
> > > unsigned int w,
> > > {
> > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > >
> > > + bool enable = false;
> > > +
> > > + /* default value for dither reg 5 to 14 */
> > > + const u32 dither_setting[] = {
> > > + 0x, /* 5 */
> > > + 0x3002, /* 6 */
> > > + 0x, /* 7 */
> > > + 0x, /* 8 */
> > > + 0x, /* 9 */
> > > + 0x, /* 10 */
> > > + 0x, /* 11 */
> > > + 0x0011, /* 12 */
> > > + 0x, /* 13 */
> > > + 0x, /* 14 */
> >
> > Could you explain what is this?
>
> this is dither 5 to dither 14 setting
> this will be useless, we just need set dither 5 and dither 7 like
> mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
> mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
> other value is same with hardware default value.
>
>
> >
> > > + };
> > > +
> > > + if (bpc == 5 || bpc == 6) {
> > > + enable = true;
> > > + mtk_ddp_write(cmdq_pkt,
> > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> > > + DITHER_NEW_BIT_MODE,
> > > + >cmdq_reg, priv->regs, DITHER_REG(15));
> > > + mtk_ddp_write(cmdq_pkt,
> > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> >
> > This result in 0x50505050, but previous version is 0x50504040, so this
> > version is correct and previous version is incorrect?
>
> the new version set r g b 3 channel same, seams more reasonable
>
>
So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15,
DISP_DITHER_16 is identical to mtk_dither_set(), so call
mtk_dither_set() instead of duplication here.
Regards,
CK
> >
> > Regards,
> > CK
> >
> > > + >cmdq_reg, priv->regs, DITHER_REG(16));
> > > + }
> > > +
> > > +
> > > + if (enable) {
> > > + u32 idx;
> > > +
> > > + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)
> > > + mtk_ddp_write(cmdq_pkt, dither_setting[idx],
> > > >cmdq_reg, priv->regs,
> > > + DITHER_REG(idx + 5));
> > > + }
> > > +
> > > mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, priv->regs,
> > > DISP_DITHER_SIZE);
> > > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg, priv->regs,
> > > DISP_DITHER_CFG);
> > > +mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN :
> > > DITHER_RELAY_MODE, >cmdq_reg, priv->regs, DISP_DITHER_CFG);
> > > }
> > >
> > > static void mtk_dither_start(struct device *dev)
> >
> >
>
>
Re: [PATCH v11 3/9] drm/mediatek: add RDMA fifo size error handle
Hi, Hsin-Yi: On Thu, 2021-01-28 at 15:27 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu > > This patch add RDMA fifo size error handle > rdma fifo size will not always bigger than the calculated threshold > if that case happened, we need set fifo size as the threshold > > Signed-off-by: Yongqiang Niu > Signed-off-by: Hsin-Yi Wang > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index b84004394970f..04b9542010b00 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -168,6 +168,10 @@ void mtk_rdma_config(struct device *dev, unsigned int > width, >* account for blanking, and with a pixel depth of 4 bytes: >*/ > threshold = width * height * vrefresh * 4 * 7 / 100; > + > + if (threshold > rdma_fifo_size) > + threshold = rdma_fifo_size; > + Please see the discussion in [1]. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/1607591262-21736-6-git-send-email-yongqiang@mediatek.com/ Regards, CK > reg = RDMA_FIFO_UNDERFLOW_EN | > RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
Re: [PATCH v11 8/9] soc: mediatek: add mtk mutex support for MT8183
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8183 SoC.
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50
> 1 file changed, 50 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index f531b119da7a9..b348f962f82a4 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -14,6 +14,8 @@
>
> #define MT2701_MUTEX0_MOD0 0x2c
> #define MT2701_MUTEX0_SOF0 0x30
> +#define MT8183_DISP_MUTEX0_MOD0 0x30
> +#define MT8183_DISP_MUTEX0_SOF0 0x2c
Modify 'DISP_MUTEX' to 'MUTEX'
Regards,
CK
>
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n)(0x24 + 0x20 * (n))
> @@ -37,6 +39,18 @@
> #define MT8167_MUTEX_MOD_DISP_DITHER 15
> #define MT8167_MUTEX_MOD_DISP_UFOE 16
>
> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0
> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1
> +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L10
> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L11
> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12
> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> +#define MT8183_MUTEX_MOD_DISP_DITHER017
> +
> #define MT8173_MUTEX_MOD_DISP_OVL0 11
> #define MT8173_MUTEX_MOD_DISP_OVL1 12
> #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> @@ -87,6 +101,11 @@
> #define MT2712_MUTEX_SOF_DSI36
> #define MT8167_MUTEX_SOF_DPI02
> #define MT8167_MUTEX_SOF_DPI13
> +#define MT8183_MUTEX_SOF_DSI01
> +#define MT8183_MUTEX_SOF_DPI02
> +
> +#define MT8183_MUTEX_EOF_DSI0(MT8183_MUTEX_SOF_DSI0
> << 6)
> +#define MT8183_MUTEX_EOF_DPI0(MT8183_MUTEX_SOF_DPI0
> << 6)
>
> struct mtk_mutex {
> int id;
> @@ -181,6 +200,20 @@ static const unsigned int
> mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> };
>
> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> +};
> +
> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> @@ -198,6 +231,13 @@ static const unsigned int
> mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> };
>
> +/* Add EOF setting so overlay hardware can receive frame done irq */
> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data
> mt8173_mutex_driver_data = {
> .mutex_sof_reg = MT2701_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> + .mutex_mod = mt8183_mutex_mod,
> + .mutex_sof = mt8183_mutex_sof,
> + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
> + .no_clk = true,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[]
> = {
> .data = _mutex_driver_data},
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = _mutex_driver_data},
> + { .compatible = "mediatek,mt8183-disp-mutex",
> + .data = _mutex_driver_data},
> {},
> };
>
Re: [PATCH v11 7/9] drm/mediatek: enable dither function
Hi, Hsin-Yi:
On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> for 5 or 6 bpc panel, we need enable dither function
> to improve the display quality
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 -
> 1 file changed, 43 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 8173f709272be..e85625704d611 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -53,7 +53,9 @@
> #define DITHER_ENBIT(0)
> #define DISP_DITHER_CFG 0x0020
> #define DITHER_RELAY_MODEBIT(0)
> +#define DITHER_ENGINE_EN BIT(1)
> #define DISP_DITHER_SIZE 0x0030
> +#define DITHER_REG(idx) (0x100 + (idx) * 4)
>
> #define LUT_10BIT_MASK 0x03ff
>
> @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev,
> unsigned int w,
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> + bool enable = false;
> +
> + /* default value for dither reg 5 to 14 */
> + const u32 dither_setting[] = {
> + 0x, /* 5 */
> + 0x3002, /* 6 */
> + 0x, /* 7 */
> + 0x, /* 8 */
> + 0x, /* 9 */
> + 0x, /* 10 */
> + 0x, /* 11 */
> + 0x0011, /* 12 */
> + 0x, /* 13 */
> + 0x, /* 14 */
Could you explain what is this?
> + };
> +
> + if (bpc == 5 || bpc == 6) {
> + enable = true;
> + mtk_ddp_write(cmdq_pkt,
> + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> + DITHER_NEW_BIT_MODE,
> + >cmdq_reg, priv->regs, DITHER_REG(15));
> + mtk_ddp_write(cmdq_pkt,
> + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
This result in 0x50505050, but previous version is 0x50504040, so this
version is correct and previous version is incorrect?
Regards,
CK
> + >cmdq_reg, priv->regs, DITHER_REG(16));
> + }
> +
> +
> + if (enable) {
> + u32 idx;
> +
> + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)
> + mtk_ddp_write(cmdq_pkt, dither_setting[idx],
> >cmdq_reg, priv->regs,
> + DITHER_REG(idx + 5));
> + }
> +
> mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, priv->regs,
> DISP_DITHER_SIZE);
> - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg, priv->regs,
> DISP_DITHER_CFG);
> +mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN :
> DITHER_RELAY_MODE, >cmdq_reg, priv->regs, DISP_DITHER_CFG);
> }
>
> static void mtk_dither_start(struct device *dev)
Re: [PATCH v11 4/9] drm/mediatek: add mtk_dither_set_common() function
On Thu, 2021-01-28 at 15:27 +0800, Hsin-Yi Wang wrote:
> Current implementation of mtk_dither_set() cast dev data to
> struct mtk_ddp_comp_dev. But other devices with different dev data
> would also call this function.
>
> Separate necessary parameters out so other device components (dither,
> gamma) can call this function.
Reviewed-by: CK Hu
>
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 25 +
> 2 files changed, 20 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 46d199b7b4a29..c50d5fc9fd349 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -17,6 +17,10 @@ void mtk_color_config(struct device *dev, unsigned int w,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> void mtk_color_start(struct device *dev);
>
> +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg
> *cmdq_reg,
> +unsigned int bpc, unsigned int CFG,
> +struct cmdq_pkt *cmdq_pkt);
> +
> void mtk_dpi_start(struct device *dev);
> void mtk_dpi_stop(struct device *dev);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 7b5293429426d..53d25823a37cc 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -151,33 +151,40 @@ static void mtk_ddp_clk_disable(struct device *dev)
> clk_disable_unprepare(priv->clk);
> }
>
> -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> - unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> -{
> - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg
> *cmdq_reg,
> +unsigned int bpc, unsigned int CFG, struct cmdq_pkt
> *cmdq_pkt)
> +{
> /* If bpc equal to 0, the dithering function didn't be enabled */
> if (bpc == 0)
> return;
>
> if (bpc >= MTK_MIN_BPC) {
> - mtk_ddp_write(cmdq_pkt, 0, >cmdq_reg, priv->regs,
> DISP_DITHER_5);
> - mtk_ddp_write(cmdq_pkt, 0, >cmdq_reg, priv->regs,
> DISP_DITHER_7);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_NEW_BIT_MODE,
> - >cmdq_reg, priv->regs, DISP_DITHER_15);
> + cmdq_reg, regs, DISP_DITHER_15);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> - >cmdq_reg, priv->regs, DISP_DITHER_16);
> - mtk_ddp_write(cmdq_pkt, DISP_DITHERING, >cmdq_reg,
> priv->regs, CFG);
> + cmdq_reg, regs, DISP_DITHER_16);
> + mtk_ddp_write(cmdq_pkt, DISP_DITHERING, cmdq_reg, regs, CFG);
> }
> }
>
> +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> + unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_dither_set_common(priv->regs, >cmdq_reg, bpc, CFG, cmdq_pkt);
> +}
> +
> static void mtk_od_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183
On Thu, 2021-01-28 at 14:15 +0800, Hsin-Yi Wang wrote:
> On Thu, Jan 28, 2021 at 2:13 PM CK Hu wrote:
> >
> > Hi, Hsin-Yi:
> >
> > Modify the title's prefix to 'soc: mediatek:'
> >
> > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > > From: Yongqiang Niu
> > >
> > > Add DDP support for MT8183 SoC.
> > >
> > > Signed-off-by: Yongqiang Niu
> > > Signed-off-by: Hsin-Yi Wang
> > > ---
> > > drivers/soc/mediatek/mtk-mutex.c | 50
> > > 1 file changed, 50 insertions(+)
> > >
> > > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > > b/drivers/soc/mediatek/mtk-mutex.c
> > > index f531b119da7a9..f64e9c33e85ad 100644
> > > --- a/drivers/soc/mediatek/mtk-mutex.c
> > > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > > @@ -14,6 +14,8 @@
> > >
> > > #define MT2701_MUTEX0_MOD0 0x2c
> > > #define MT2701_MUTEX0_SOF0 0x30
> > > +#define MT8183_DISP_MUTEX0_MOD0 0x30
> > > +#define MT8183_DISP_MUTEX0_SOF0 0x2c
> >
> > Modify 'DISP_MUTEX' to 'MUTEX'
> >
> > >
> > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> > > #define DISP_REG_MUTEX(n)(0x24 + 0x20 * (n))
> > > @@ -37,6 +39,18 @@
> > > #define MT8167_MUTEX_MOD_DISP_DITHER 15
> > > #define MT8167_MUTEX_MOD_DISP_UFOE 16
> > >
> > > +#define MT8183_MUTEX_MOD_DISP_RDMA0 0
> > > +#define MT8183_MUTEX_MOD_DISP_RDMA1 1
> > > +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> > > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L10
> > > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L11
> > > +#define MT8183_MUTEX_MOD_DISP_WDMA0 12
> > > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> > > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> > > +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> > > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> > > +#define MT8183_MUTEX_MOD_DISP_DITHER017
> > > +
> > > #define MT8173_MUTEX_MOD_DISP_OVL0 11
> > > #define MT8173_MUTEX_MOD_DISP_OVL1 12
> > > #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> > > @@ -87,6 +101,12 @@
> > > #define MT2712_MUTEX_SOF_DSI36
> > > #define MT8167_MUTEX_SOF_DPI02
> > > #define MT8167_MUTEX_SOF_DPI13
> > > +#define MT8183_MUTEX_SOF_DSI01
> > > +#define MT8183_MUTEX_SOF_DPI02
> > > +
> > > +/* Add EOF setting so overlay hardware can receive frame done irq */
> > > +#define MT8183_MUTEX_EOF_DSI0
> > > (MT8183_MUTEX_SOF_DSI0 << 6)
> > > +#define MT8183_MUTEX_EOF_DPI0
> > > (MT8183_MUTEX_SOF_DPI0 << 6)
> > >
>
> Hi CK, comment is added here. I can move to mt8183_mutex_sof if preferred.
I prefer to move comment to mt8183_mutex_sof.
>
> > > struct mtk_mutex {
> > > int id;
> > > @@ -181,6 +201,20 @@ static const unsigned int
> > > mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> > > };
> > >
> > > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> > > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> > > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> > > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> > > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> > > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> > > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> > > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> > > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> > > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> > > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> > > +};
> > > +
> > > static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> > > @@ -198,6 +232,12 @@ static const unsigne
Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183
On Thu, 2021-01-28 at 14:13 +0800, CK Hu wrote:
> Hi, Hsin-Yi:
>
> Modify the title's prefix to 'soc: mediatek:'
Modify more, the title should be 'soc: mediatek: add mtk mutex support
for MT8183'
>
> On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > From: Yongqiang Niu
> >
> > Add DDP support for MT8183 SoC.
> >
> > Signed-off-by: Yongqiang Niu
> > Signed-off-by: Hsin-Yi Wang
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 50
> > 1 file changed, 50 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index f531b119da7a9..f64e9c33e85ad 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -14,6 +14,8 @@
> >
> > #define MT2701_MUTEX0_MOD0 0x2c
> > #define MT2701_MUTEX0_SOF0 0x30
> > +#define MT8183_DISP_MUTEX0_MOD00x30
> > +#define MT8183_DISP_MUTEX0_SOF00x2c
>
> Modify 'DISP_MUTEX' to 'MUTEX'
>
> >
> > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> > @@ -37,6 +39,18 @@
> > #define MT8167_MUTEX_MOD_DISP_DITHER 15
> > #define MT8167_MUTEX_MOD_DISP_UFOE 16
> >
> > +#define MT8183_MUTEX_MOD_DISP_RDMA00
> > +#define MT8183_MUTEX_MOD_DISP_RDMA11
> > +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
> > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
> > +#define MT8183_MUTEX_MOD_DISP_WDMA012
> > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> > +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> > +#define MT8183_MUTEX_MOD_DISP_DITHER0 17
> > +
> > #define MT8173_MUTEX_MOD_DISP_OVL0 11
> > #define MT8173_MUTEX_MOD_DISP_OVL1 12
> > #define MT8173_MUTEX_MOD_DISP_RDMA013
> > @@ -87,6 +101,12 @@
> > #define MT2712_MUTEX_SOF_DSI3 6
> > #define MT8167_MUTEX_SOF_DPI0 2
> > #define MT8167_MUTEX_SOF_DPI1 3
> > +#define MT8183_MUTEX_SOF_DSI0 1
> > +#define MT8183_MUTEX_SOF_DPI0 2
> > +
> > +/* Add EOF setting so overlay hardware can receive frame done irq */
> > +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0
> > << 6)
> > +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0
> > << 6)
> >
> > struct mtk_mutex {
> > int id;
> > @@ -181,6 +201,20 @@ static const unsigned int
> > mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> > };
> >
> > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> > +};
> > +
> > static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> > @@ -198,6 +232,12 @@ static const unsigned int
> > mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> > };
> >
> > +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> > + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
>
> According to discussion in [1], add comment for the odd EOF setting.
>
> [1]
> https://patchwork.k
Re: [PATCH v10 9/9] drm/mediatek: add support for mediatek SOC MT8183
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> 1. add ovl private data
> 2. add rdma private data
> 3. add gamma privte data
> 4. add main and external path module for crtc create
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +++
> drivers/gpu/drm/mediatek/mtk_drm_drv.c| 45 +++
> 4 files changed, 70 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> index c98fe284265d0..93ad76a2dda5e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> @@ -179,6 +179,7 @@ static const struct mtk_disp_gamma_data
> mt8173_gamma_driver_data = {
> static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = {
> { .compatible = "mediatek,mt8173-disp-gamma",
> .data = _gamma_driver_data},
> + { .compatible = "mediatek,mt8183-disp-gamma"},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 1c295c58a5e82..da7e38a28759b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -424,11 +424,29 @@ static const struct mtk_disp_ovl_data
> mt8173_ovl_driver_data = {
> .fmt_rgb565_is_0 = true,
> };
>
> +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 4,
> + .fmt_rgb565_is_0 = true,
> +};
> +
> +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 2,
> + .fmt_rgb565_is_0 = true,
> +};
> +
> static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-ovl",
> .data = _ovl_driver_data},
> { .compatible = "mediatek,mt8173-disp-ovl",
> .data = _ovl_driver_data},
> + { .compatible = "mediatek,mt8183-disp-ovl",
> + .data = _ovl_driver_data},
> + { .compatible = "mediatek,mt8183-disp-ovl-2l",
> + .data = _ovl_2l_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 04b9542010b00..29fa5f3a05c30 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -355,11 +355,17 @@ static const struct mtk_disp_rdma_data
> mt8173_rdma_driver_data = {
> .fifo_size = SZ_8K,
> };
>
> +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
> + .fifo_size = 5 * SZ_1K,
> +};
> +
> static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = _rdma_driver_data},
> { .compatible = "mediatek,mt8173-disp-rdma",
> .data = _rdma_driver_data},
> + { .compatible = "mediatek,mt8183-disp-rdma",
> + .data = _rdma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 279d3e6f11563..486e73e675ad5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -129,6 +129,24 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] =
> {
> DDP_COMPONENT_DPI0,
> };
>
> +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_OVL_2L0,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DSI0,
> +};
> +
> +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
> + DDP_COMPONENT_OVL_2L1,
> + DDP_COMPONENT_RDMA1,
> + DDP_COMPONENT_DPI0,
> +};
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .main_path = mt2701_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -161,6 +179,13 @@ static const struct mtk_mmsys_driver_data
> mt8173
Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183
Hi, Hsin-Yi:
Modify the title's prefix to 'soc: mediatek:'
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add DDP support for MT8183 SoC.
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50
> 1 file changed, 50 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index f531b119da7a9..f64e9c33e85ad 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -14,6 +14,8 @@
>
> #define MT2701_MUTEX0_MOD0 0x2c
> #define MT2701_MUTEX0_SOF0 0x30
> +#define MT8183_DISP_MUTEX0_MOD0 0x30
> +#define MT8183_DISP_MUTEX0_SOF0 0x2c
Modify 'DISP_MUTEX' to 'MUTEX'
>
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n)(0x24 + 0x20 * (n))
> @@ -37,6 +39,18 @@
> #define MT8167_MUTEX_MOD_DISP_DITHER 15
> #define MT8167_MUTEX_MOD_DISP_UFOE 16
>
> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0
> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1
> +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L10
> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L11
> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12
> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> +#define MT8183_MUTEX_MOD_DISP_DITHER017
> +
> #define MT8173_MUTEX_MOD_DISP_OVL0 11
> #define MT8173_MUTEX_MOD_DISP_OVL1 12
> #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> @@ -87,6 +101,12 @@
> #define MT2712_MUTEX_SOF_DSI36
> #define MT8167_MUTEX_SOF_DPI02
> #define MT8167_MUTEX_SOF_DPI13
> +#define MT8183_MUTEX_SOF_DSI01
> +#define MT8183_MUTEX_SOF_DPI02
> +
> +/* Add EOF setting so overlay hardware can receive frame done irq */
> +#define MT8183_MUTEX_EOF_DSI0(MT8183_MUTEX_SOF_DSI0
> << 6)
> +#define MT8183_MUTEX_EOF_DPI0(MT8183_MUTEX_SOF_DPI0
> << 6)
>
> struct mtk_mutex {
> int id;
> @@ -181,6 +201,20 @@ static const unsigned int
> mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> };
>
> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> +};
> +
> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> @@ -198,6 +232,12 @@ static const unsigned int
> mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> };
>
> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
According to discussion in [1], add comment for the odd EOF setting.
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/1595469798-3824-8-git-send-email-yongqiang@mediatek.com/
Regards,
CK.
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data
> mt8173_mutex_driver_data = {
> .mutex_sof_reg = MT2701_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> + .mutex_mod = mt8183_mutex_mod,
> + .mutex_sof = mt8183_mutex_sof,
> + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
> + .no_clk = true,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[]
> = {
>
Re: [PATCH v10 7/9] drm/mediatek: enable dither function
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> for 5 or 6 bpc panel, we need enable dither function
> to improve the display quality
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 37 -
> 1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 8173f709272be..ee54505412dcd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -53,7 +53,9 @@
> #define DITHER_ENBIT(0)
> #define DISP_DITHER_CFG 0x0020
> #define DITHER_RELAY_MODEBIT(0)
> +#define DITHER_ENGINE_EN BIT(1)
> #define DISP_DITHER_SIZE 0x0030
> +#define DITHER_REG(idx) (0x100 + (idx) * 4)
>
> #define LUT_10BIT_MASK 0x03ff
>
> @@ -313,8 +315,41 @@ static void mtk_dither_config(struct device *dev,
> unsigned int w,
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> + bool enable = true;
> +
> + const u32 dither_setting[] = {
> + 0x, /* 5 */
> + 0x3002, /* 6 */
> + 0x, /* 7 */
> + 0x, /* 8 */
> + 0x, /* 9 */
> + 0x, /* 10 */
> + 0x, /* 11 */
> + 0x0011, /* 12 */
> + 0x, /* 13 */
> + 0x, /* 14 */
Could you explain what is this?
> + };
> +
> + if (bpc == 6) {
> + mtk_ddp_write(cmdq_pkt, 0x4041, >cmdq_reg,
> priv->regs, DITHER_REG(15));
> + mtk_ddp_write(cmdq_pkt, 0x40404040, >cmdq_reg,
> priv->regs, DITHER_REG(16));
> + } else if (bpc == 5) {
> + mtk_ddp_write(cmdq_pkt, 0x5051, >cmdq_reg,
> priv->regs, DITHER_REG(15));
> + mtk_ddp_write(cmdq_pkt, 0x50504040, >cmdq_reg,
> priv->regs, DITHER_REG(16));
This looks very similar to the code in mtk_dither_set(), could you
symbolize this magic number like mtk_dither_set()?
Regards,
CK
> + } else {
> + enable = false;
> + }
> +
> + if (enable) {
> + u32 idx;
> +
> + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)
> + mtk_ddp_write(cmdq_pkt, dither_setting[idx],
> >cmdq_reg, priv->regs,
> + DITHER_REG(idx + 5));
> + }
> +
> mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, priv->regs,
> DISP_DITHER_SIZE);
> - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg, priv->regs,
> DISP_DITHER_CFG);
> +mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN :
> DITHER_RELAY_MODE, >cmdq_reg, priv->regs, DISP_DITHER_CFG);
> }
>
> static void mtk_dither_start(struct device *dev)
Re: [PATCH v10 5/9] drm/mediatek: separate gamma module
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> mt8183 gamma module will different with mt8173
> separate gamma for add private data
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 10 ++
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 188
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 71 ++--
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 6 files changed, 214 insertions(+), 61 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_gamma.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile
> b/drivers/gpu/drm/mediatek/Makefile
> index 01d06332f7679..b64674b944860 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
>
> mediatek-drm-y := mtk_disp_color.o \
> + mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index c50d5fc9fd349..c1e658b490b6c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -27,6 +27,16 @@ void mtk_dpi_stop(struct device *dev);
> void mtk_dsi_ddp_start(struct device *dev);
> void mtk_dsi_ddp_stop(struct device *dev);
>
> +int mtk_gamma_clk_enable(struct device *dev);
> +void mtk_gamma_clk_disable(struct device *dev);
> +void mtk_gamma_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state);
> +void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
> +void mtk_gamma_start(struct device *dev);
> +void mtk_gamma_stop(struct device *dev);
> +
> void mtk_ovl_bgclr_in_on(struct device *dev);
> void mtk_ovl_bgclr_in_off(struct device *dev);
> void mtk_ovl_bypass_shadow(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> new file mode 100644
> index 0..b5a499d7e472c
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> @@ -0,0 +1,188 @@
> +/*
> + * SPDX-License-Identifier:
> + *
> + * Copyright (c) 2020 MediaTek Inc.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_GAMMA_EN0x
> +#define GAMMA_EN BIT(0)
> +#define DISP_GAMMA_CFG 0x0020
> +#define GAMMA_LUT_EN BIT(1)
> +#define DISP_GAMMA_SIZE 0x0030
> +#define DISP_GAMMA_LUT 0x0700
> +
> +#define LUT_10BIT_MASK 0x03ff
> +
> +struct mtk_disp_gamma_data {
> + u32 reserved;
> +};
> +
> +/**
> + * struct mtk_disp_gamma - DISP_GAMMA driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_gamma {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> + const struct mtk_disp_gamma_data *data;
> +};
> +
> +int mtk_gamma_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(gamma->clk);
> +}
> +
> +void mtk_gamma_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(gamma->clk);
> +}
> +
> +void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state)
> +{
> + unsigned int i, reg;
> + struct drm_color_lut *lut;
> + void __iomem *lut_base;
> + u32 word;
> +
> + if (state->gamma_lut) {
> + reg = readl(regs + DISP_GAMMA_CFG);
> + reg = reg | GAMMA_LUT_EN;
> + writel(reg, regs + DISP_GAMMA_CFG);
> + lut_base = regs + DISP_GAMMA_LUT;
> + lut = (struct drm_color_lut *)state->gamma_lut->dat
Re: [PATCH v10 6/9] drm/mediatek: add has_dither private data for gamma
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Not all SoC has dither function in gamma module.
> Add private data to control this function setting.
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 12 +---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> index b5a499d7e472c..c98fe284265d0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> @@ -25,7 +25,7 @@
> #define LUT_10BIT_MASK 0x03ff
>
> struct mtk_disp_gamma_data {
> - u32 reserved;
> + bool has_dither;
> };
>
> /**
> @@ -91,7 +91,8 @@ void mtk_gamma_config(struct device *dev, unsigned int w,
>
> mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, gamma->regs,
> DISP_GAMMA_SIZE);
> - mtk_dither_set_common(gamma->regs, >cmdq_reg, bpc,
> DISP_GAMMA_CFG, cmdq_pkt);
> + if (gamma->data && gamma->data->has_dither)
> + mtk_dither_set_common(gamma->regs, >cmdq_reg, bpc,
> DISP_GAMMA_CFG, cmdq_pkt);
> }
>
> void mtk_gamma_start(struct device *dev)
> @@ -171,8 +172,13 @@ static int mtk_disp_gamma_remove(struct platform_device
> *pdev)
> return 0;
> }
>
> +static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = {
> + .has_dither = true,
> +};
> +
> static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = {
> - { .compatible = "mediatek,mt8173-disp-gamma"},
> + { .compatible = "mediatek,mt8173-disp-gamma",
> + .data = _gamma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match);
Re: [PATCH v10 4/9] drm/mediatek: generalize mtk_dither_set() function
On Thu, 2021-01-28 at 13:09 +0800, Hsin-Yi Wang wrote:
> On Thu, Jan 28, 2021 at 12:39 PM CK Hu wrote:
> >
> > Hi, Hsin-Yi:
> >
> > On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > > There may be data structure other than mtk_ddp_comp_dev that would call
> > > mtk_dither_set(), so use regs as parameter instead of device.
> >
> > You does not change the interface of mtk_dither_set(). You move the
> > common part in mtk_dither_set() to a new function which could be called
> > by another caller.
> >
> > Regards,
> > CK.
> >
> Current mtk_dither_set() cast dev data to struct mtk_ddp_comp_dev. But
> mtk_disp_gamma in next patch would also call this function. But it's
> dev data is struct mtk_disp_gamma, which is different, so we can't
> cast to mtk_ddp_comp_dev. I separate the necessary parameters (regs,
> cmdq_reg) out, so both component dither and gamma can both call this
> separated function.
I know this. This patch looks good to me but the description would
confuse me.From the description, it seems that you modify the interface
of mtk_dither_set(). So please modify the description to be more clear.
Regards,
CK
>
> This is similar to the mtk_gamma_set_common() in the next patch, which
> gamma and aal both used.
>
> > >
> > > Signed-off-by: Hsin-Yi Wang
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4
> > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 25 +
> > > 2 files changed, 20 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > index 46d199b7b4a29..c50d5fc9fd349 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > > @@ -17,6 +17,10 @@ void mtk_color_config(struct device *dev, unsigned int
> > > w,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > > void mtk_color_start(struct device *dev);
> > >
> > > +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg
> > > *cmdq_reg,
> > > +unsigned int bpc, unsigned int CFG,
> > > +struct cmdq_pkt *cmdq_pkt);
> > > +
> > > void mtk_dpi_start(struct device *dev);
> > > void mtk_dpi_stop(struct device *dev);
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > index 7b5293429426d..53d25823a37cc 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > @@ -151,33 +151,40 @@ static void mtk_ddp_clk_disable(struct device *dev)
> > > clk_disable_unprepare(priv->clk);
> > > }
> > >
> > > -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > > - unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> > > -{
> > > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > >
> > > +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg
> > > *cmdq_reg,
> > > +unsigned int bpc, unsigned int CFG, struct
> > > cmdq_pkt *cmdq_pkt)
> > > +{
> > > /* If bpc equal to 0, the dithering function didn't be enabled */
> > > if (bpc == 0)
> > > return;
> > >
> > > if (bpc >= MTK_MIN_BPC) {
> > > - mtk_ddp_write(cmdq_pkt, 0, >cmdq_reg, priv->regs,
> > > DISP_DITHER_5);
> > > - mtk_ddp_write(cmdq_pkt, 0, >cmdq_reg, priv->regs,
> > > DISP_DITHER_7);
> > > + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> > > + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
> > > mtk_ddp_write(cmdq_pkt,
> > > DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> > > DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> > > DITHER_NEW_BIT_MODE,
> > > - >cmdq_reg, priv->regs, DISP_DITHER_15);
> > > + cmdq_reg, regs, DISP_DITHER_15);
> > > mtk_ddp_write(cmdq_pkt,
> > > DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> > > DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc)
Re: [PATCH v10 4/9] drm/mediatek: generalize mtk_dither_set() function
Hi, Hsin-Yi:
On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> There may be data structure other than mtk_ddp_comp_dev that would call
> mtk_dither_set(), so use regs as parameter instead of device.
You does not change the interface of mtk_dither_set(). You move the
common part in mtk_dither_set() to a new function which could be called
by another caller.
Regards,
CK.
>
> Signed-off-by: Hsin-Yi Wang
> ---
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 25 +
> 2 files changed, 20 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 46d199b7b4a29..c50d5fc9fd349 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -17,6 +17,10 @@ void mtk_color_config(struct device *dev, unsigned int w,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> void mtk_color_start(struct device *dev);
>
> +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg
> *cmdq_reg,
> +unsigned int bpc, unsigned int CFG,
> +struct cmdq_pkt *cmdq_pkt);
> +
> void mtk_dpi_start(struct device *dev);
> void mtk_dpi_stop(struct device *dev);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 7b5293429426d..53d25823a37cc 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -151,33 +151,40 @@ static void mtk_ddp_clk_disable(struct device *dev)
> clk_disable_unprepare(priv->clk);
> }
>
> -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> - unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> -{
> - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg
> *cmdq_reg,
> +unsigned int bpc, unsigned int CFG, struct cmdq_pkt
> *cmdq_pkt)
> +{
> /* If bpc equal to 0, the dithering function didn't be enabled */
> if (bpc == 0)
> return;
>
> if (bpc >= MTK_MIN_BPC) {
> - mtk_ddp_write(cmdq_pkt, 0, >cmdq_reg, priv->regs,
> DISP_DITHER_5);
> - mtk_ddp_write(cmdq_pkt, 0, >cmdq_reg, priv->regs,
> DISP_DITHER_7);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_NEW_BIT_MODE,
> - >cmdq_reg, priv->regs, DISP_DITHER_15);
> + cmdq_reg, regs, DISP_DITHER_15);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> - >cmdq_reg, priv->regs, DISP_DITHER_16);
> - mtk_ddp_write(cmdq_pkt, DISP_DITHERING, >cmdq_reg,
> priv->regs, CFG);
> + cmdq_reg, regs, DISP_DITHER_16);
> + mtk_ddp_write(cmdq_pkt, DISP_DITHERING, cmdq_reg, regs, CFG);
> }
> }
>
> +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> + unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_dither_set_common(priv->regs, >cmdq_reg, bpc, CFG, cmdq_pkt);
> +}
> +
> static void mtk_od_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
Re: [PATCH v10 3/9] drm/mediatek: add RDMA fifo size error handle
Hi, Hsin-Yi: On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu > > This patch add RDMA fifo size error handle > rdma fifo size will not always bigger than the calculated threshold > if that case happened, we need set fifo size as the threshold > > Signed-off-by: Yongqiang Niu > Signed-off-by: Hsin-Yi Wang > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index b84004394970f..04b9542010b00 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -168,6 +168,10 @@ void mtk_rdma_config(struct device *dev, unsigned int > width, >* account for blanking, and with a pixel depth of 4 bytes: >*/ > threshold = width * height * vrefresh * 4 * 7 / 100; > + > + if (threshold > rdma_fifo_size) > + threshold = rdma_fifo_size; Please see the discussion in [1]. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/1607591262-21736-6-git-send-email-yongqiang@mediatek.com/ Regards, CK > + > reg = RDMA_FIFO_UNDERFLOW_EN | > RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
Re: [PATCH 3/3] arm64: dts: mt8183: Add display nodes for MT8183
Hi, Enric:
On Fri, 2020-11-27 at 11:49 +0100, Enric Balletbo i Serra wrote:
> Add display subsystem device nodes to allow video output.
>
> Signed-off-by: Enric Balletbo i Serra
> ---
>
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 114 +++
> 1 file changed, 114 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index ba9ff192cda3..34d83f517b07 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -6,6 +6,7 @@
> */
>
> #include
> +#include
This should be
#include
Regards,
CK
> #include
> #include
> #include
> @@ -33,6 +34,11 @@ aliases {
> i2c9 =
> i2c10 =
> i2c11 =
> + ovl0 =
> + ovl-2l0 = _2l0;
> + ovl-2l1 = _2l1;
> + rdma0 =
> + rdma1 =
> };
>
> cpus {
> @@ -964,6 +970,107 @@ mmsys: syscon@1400 {
> #clock-cells = <1>;
> };
>
> + ovl0: ovl@14008000 {
> + compatible = "mediatek,mt8183-disp-ovl";
> + reg = <0 0x14008000 0 0x1000>;
> + interrupts = ;
> + power-domains = < MT8183_POWER_DOMAIN_DISP>;
> + clocks = < CLK_MM_DISP_OVL0>;
> + iommus = < M4U_PORT_DISP_OVL0>;
> + mediatek,larb = <>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0x8000
> 0x1000>;
> + };
> +
> + ovl_2l0: ovl@14009000 {
> + compatible = "mediatek,mt8183-disp-ovl-2l";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = ;
> + power-domains = < MT8183_POWER_DOMAIN_DISP>;
> + clocks = < CLK_MM_DISP_OVL0_2L>;
> + iommus = < M4U_PORT_DISP_2L_OVL0_LARB0>;
> + mediatek,larb = <>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0x9000
> 0x1000>;
> + };
> +
> + ovl_2l1: ovl@1400a000 {
> + compatible = "mediatek,mt8183-disp-ovl-2l";
> + reg = <0 0x1400a000 0 0x1000>;
> + interrupts = ;
> + power-domains = < MT8183_POWER_DOMAIN_DISP>;
> + clocks = < CLK_MM_DISP_OVL1_2L>;
> + iommus = < M4U_PORT_DISP_2L_OVL1_LARB0>;
> + mediatek,larb = <>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0xa000
> 0x1000>;
> + };
> +
> + rdma0: rdma@1400b000 {
> + compatible = "mediatek,mt8183-disp-rdma";
> + reg = <0 0x1400b000 0 0x1000>;
> + interrupts = ;
> + power-domains = < MT8183_POWER_DOMAIN_DISP>;
> + clocks = < CLK_MM_DISP_RDMA0>;
> + iommus = < M4U_PORT_DISP_RDMA0>;
> + mediatek,larb = <>;
> + mediatek,rdma_fifo_size = <5120>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0xb000
> 0x1000>;
> + };
> +
> + rdma1: rdma@1400c000 {
> + compatible = "mediatek,mt8183-disp-rdma";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = ;
> + power-domains = < MT8183_POWER_DOMAIN_DISP>;
> + clocks = < CLK_MM_DISP_RDMA1>;
> + iommus = < M4U_PORT_DISP_RDMA1>;
> + mediatek,larb = <>;
> + mediatek,rdma_fifo_size = <2048>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0xc000
> 0x1000>;
> + };
> +
> + color0: color@1400e000 {
> + compatible = "mediatek,mt8183-disp-color",
> + "mediatek,mt8173-disp-color";
> + reg = <0 0x1400e000 0 0x1000>;
> + interrupts = ;
> + power-domains = < MT8183_POWER_DOMAIN_DISP>;
> + clocks = < CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0xe000
> 0x1000>;
> + };
> +
> + ccorr0: ccorr@1400f000 {
> + compatible = "mediatek,mt8183-disp-ccorr";
> + reg = <0 0x1400f000 0 0x1000>;
> + interrupts = ;
> + power-domains = < MT8183_POWER_DOMAIN_DISP>;
> + clocks = < CLK_MM_DISP_CCORR0>;
> + };
> +
> + aal0: aal@1401 {
> + compatible = "mediatek,mt8183-disp-aal",
> + "mediatek,mt8173-disp-aal";
> + reg = <0 0x1401 0 0x1000>;
> + interrupts = ;
> +
Re: [PATCH v2 4/8] dt-bindings: phy: convert HDMI PHY binding to YAML schema
Hi, Chunfeng:
On Tue, 2020-10-13 at 16:52 +0800, Chunfeng Yun wrote:
> Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml
>
> Signed-off-by: Chunfeng Yun
> ---
> v2: fix binding check warning of reg in example
> ---
> .../display/mediatek/mediatek,hdmi.txt| 17 +---
> .../bindings/phy/mediatek,hdmi-phy.yaml | 90 +++
> 2 files changed, 91 insertions(+), 16 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> index 7b124242b0c5..edac18951a75 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> @@ -50,22 +50,7 @@ Required properties:
>
> HDMI PHY
>
> -
> -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
> -output and drives the HDMI pads.
> -
> -Required properties:
> -- compatible: "mediatek,-hdmi-phy"
> -- reg: Physical base address and length of the module's registers
> -- clocks: PLL reference clock
> -- clock-names: must contain "pll_ref"
> -- clock-output-names: must be "hdmitx_dig_cts" on mt8173
> -- #phy-cells: must be <0>
> -- #clock-cells: must be <0>
> -
> -Optional properties:
> -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
> -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
> +See phy/mediatek,hdmi-phy.yaml
>
> Example:
>
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> new file mode 100644
> index ..77df50204606
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
> +
> +maintainers:
> + - CK Hu
I think you should remove "CK Hu " and add latest
mediatek drm maintainer:
DRM DRIVERS FOR MEDIATEK
M: Chun-Kuang Hu
M: Philipp Zabel
L: dri-de...@lists.freedesktop.org
S: Supported
F: Documentation/devicetree/bindings/display/mediatek/
F: drivers/gpu/drm/mediatek/
Regards,
CK
> + - Chunfeng Yun
> +
> +description: |
> + The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
> + output and drives the HDMI pads.
> +
> +properties:
> + $nodename:
> +pattern: "^hdmi-phy@[0-9a-f]+$"
> +
> + compatible:
> +enum:
> + - mediatek,mt2701-hdmi-phy
> + - mediatek,mt8173-hdmi-phy
> +
> + reg:
> +maxItems: 1
> +
> + clocks:
> +items:
> + - description: PLL reference clock
> +
> + clock-names:
> +items:
> + - const: pll_ref
> +
> + clock-output-names:
> +items:
> + - const: hdmitx_dig_cts
> +
> + "#phy-cells":
> +const: 0
> +
> + "#clock-cells":
> +const: 0
> +
> + mediatek,ibias:
> +description:
> + TX DRV bias current for < 1.65Gbps
> +$ref: /schemas/types.yaml#/definitions/uint32
> +minimum: 0
> +maximum: 63
> +default: 0xa
> +
> + mediatek,ibias_up:
> +description:
> + TX DRV bias current for >= 1.65Gbps
> +$ref: /schemas/types.yaml#/definitions/uint32
> +minimum: 0
> +maximum: 63
> +default: 0x1c
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - clock-output-names
> + - "#phy-cells"
> + - "#clock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +#include
> +hdmi_phy: hdmi-phy@10209100 {
> +compatible = "mediatek,mt8173-hdmi-phy";
> +reg = <0x10209100 0x24>;
> +clocks = < CLK_APMIXED_HDMI_REF>;
> +clock-names = "pll_ref";
> +clock-output-names = "hdmitx_dig_cts";
> +mediatek,ibias = <0xa>;
> +mediatek,ibias_up = <0x1c>;
> +#clock-cells = <0>;
> +#phy-cells = <0>;
> +};
> +
> +...
Re: [RFC PATCH 3/4] usb: xhci-mtk: add support runtime pm
Hi, Chunfeng:
On Thu, 2020-09-03 at 11:34 +0800, Chunfeng Yun wrote:
> From: CK Hu
>
> add support runtime pm feature
>
> Signed-off-by: Zhanyong Wang
> Signed-off-by: Chunfeng Yun
> ---
> drivers/usb/host/xhci-mtk.c | 446
> +++-
> drivers/usb/host/xhci-mtk.h | 14 ++
> 2 files changed, 455 insertions(+), 5 deletions(-)
> mode change 100644 => 100755 drivers/usb/host/xhci-mtk.h
>
[snip]
> @@ -562,6 +794,31 @@ static int xhci_mtk_probe(struct platform_device *pdev)
> if (ret)
> goto dealloc_usb2_hcd;
>
> + INIT_DELAYED_WORK(>seal, xhci_mtk_seal_work);
> + snprintf(mtk->seal_descr, sizeof(mtk->seal_descr), "seal%s:usb%d",
> + hcd->driver->description, hcd->self.busnum);
> + ret = devm_request_irq(mtk->seal_irq, _mtk_seal_irq,
> + IRQF_TRIGGER_FALLING, mtk->seal_descr, mtk);
In interrupt.h [1], devm_request_irq() need 6 parameters:
static inline int __must_check
devm_request_irq(struct device *dev, unsigned int irq, irq_handler_t
handler,
unsigned long irqflags, const char *devname, void *dev_id)
{
return devm_request_threaded_irq(dev, irq, handler, NULL, irqflags,
devname, dev_id);
}
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/interrupt.h?h=v5.9-rc1
Regards,
CK
> + if (ret != 0) {
> + dev_err(dev, "seal request interrupt %d failed\n",
> + mtk->seal_irq);
> + goto dealloc_usb2_hcd;
> + }
> + xhci_mtk_seal_wakeup_enable(mtk, false);
> +
> + device_enable_async_suspend(dev);
> + xhci_mtk_runtime_ready = 1;
> +
> + ret = add_power_attributes(dev);
> + if (ret)
> + goto dealloc_usb2_hcd;
> +
> + pm_runtime_mark_last_busy(dev);
> + pm_runtime_put_autosuspend(dev);
> +
> + dev_dbg(dev, "%s: xhci_mtk_runtime_ready %i",
> + __func__, xhci_mtk_runtime_ready);
> +
> return 0;
>
> dealloc_usb2_hcd:
> @@ -584,7 +841,7 @@ static int xhci_mtk_probe(struct platform_device *pdev)
> xhci_mtk_ldos_disable(mtk);
>
> disable_pm:
> - pm_runtime_put_sync(dev);
> + pm_runtime_put_sync_autosuspend(dev);
> pm_runtime_disable(dev);
> return ret;
> }
Re: [PATCH v4 0/3] Mediatek pinctrl patch on mt8192
Hi, Linus: On Thu, 2020-08-27 at 10:52 +0200, Linus Walleij wrote: > On Mon, Aug 17, 2020 at 2:18 AM Zhiyong Tao wrote: > > > This series includes 3 patches: > > 1.add pinctrl file on mt8192. > > 2.add pinctrl binding document on mt8192. > > 3.add pinctrl driver on MT8192. > > Patches applied for v5.10! I does not see these patches in your tree [1], have you applied them? I would like to pick these patches from your tree. [1] https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/ Regards, CK > Thanks! > Linus Walleij > > ___ > Linux-mediatek mailing list > linux-media...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
Re: [PATCH v2] nvmem: mtk-efuse: Remove EFUSE register write support
Hi, Chih-En:
On Wed, 2020-08-26 at 14:21 +0800, Chih-En Hsu wrote:
> This patch is to remove function "mtk_reg_write" since
> Mediatek EFUSE hardware only supports read functionality
> for NVMEM consumers.
>
Reviewed-by: CK Hu
> Fixes: 4c7e4fe37766 ("nvmem: mediatek: Add Mediatek EFUSE driver")
> Signed-off-by: Chih-En Hsu
> ---
> drivers/nvmem/mtk-efuse.c | 14 --
> 1 file changed, 14 deletions(-)
>
> diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c
> index 856d9c3fc38e..6a537d959f14 100644
> --- a/drivers/nvmem/mtk-efuse.c
> +++ b/drivers/nvmem/mtk-efuse.c
> @@ -28,19 +28,6 @@ static int mtk_reg_read(void *context,
> return 0;
> }
>
> -static int mtk_reg_write(void *context,
> - unsigned int reg, void *_val, size_t bytes)
> -{
> - struct mtk_efuse_priv *priv = context;
> - u32 *val = _val;
> - int i = 0, words = bytes / 4;
> -
> - while (words--)
> - writel(*val++, priv->base + reg + (i++ * 4));
> -
> - return 0;
> -}
> -
> static int mtk_efuse_probe(struct platform_device *pdev)
> {
> struct device *dev = >dev;
> @@ -61,7 +48,6 @@ static int mtk_efuse_probe(struct platform_device *pdev)
> econfig.stride = 4;
> econfig.word_size = 4;
> econfig.reg_read = mtk_reg_read;
> - econfig.reg_write = mtk_reg_write;
> econfig.size = resource_size(res);
> econfig.priv = priv;
> econfig.dev = dev;
Re: [PATCH] nvmem: mtk-efuse: Remove EFUSE register write support
Hi, Chih-En:
On Wed, 2020-08-26 at 13:01 +0800, Chih-En Hsu wrote:
> This patch is to remove function "mtk_reg_write" since
> Mediatek EFUSE hardware only supports read functionality
> for NVMEM consumers.
>
This is a bug-fix patch, so need a 'Fixes' tag. You could refer to [1].
[1]
https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-changes
Regards,
CK.
> Signed-off-by: Chih-En Hsu
> ---
> drivers/nvmem/mtk-efuse.c | 14 --
> 1 file changed, 14 deletions(-)
>
> diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c
> index 856d9c3fc38e..6a537d959f14 100644
> --- a/drivers/nvmem/mtk-efuse.c
> +++ b/drivers/nvmem/mtk-efuse.c
> @@ -28,19 +28,6 @@ static int mtk_reg_read(void *context,
> return 0;
> }
>
> -static int mtk_reg_write(void *context,
> - unsigned int reg, void *_val, size_t bytes)
> -{
> - struct mtk_efuse_priv *priv = context;
> - u32 *val = _val;
> - int i = 0, words = bytes / 4;
> -
> - while (words--)
> - writel(*val++, priv->base + reg + (i++ * 4));
> -
> - return 0;
> -}
> -
> static int mtk_efuse_probe(struct platform_device *pdev)
> {
> struct device *dev = >dev;
> @@ -61,7 +48,6 @@ static int mtk_efuse_probe(struct platform_device *pdev)
> econfig.stride = 4;
> econfig.word_size = 4;
> econfig.reg_read = mtk_reg_read;
> - econfig.reg_write = mtk_reg_write;
> econfig.size = resource_size(res);
> econfig.priv = priv;
> econfig.dev = dev;
Re: [PATCH v3 1/3] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile
Hi, Seiya:
On Wed, 2020-07-29 at 16:02 +0800, CK Hu wrote:
> Hi, Seiya:
>
> On Wed, 2020-07-29 at 09:30 +0800, Seiya Wang wrote:
> > Add basic chip support for Mediatek MT8192
> >
> > Signed-off-by: Seiya Wang
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 29 ++
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi| 671
> >
> > 3 files changed, 701 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt8192.dtsi
> >
>
> [snip]
>
> > +
> > + watchdog: watchdog@10007000 {
> > + compatible = "mediatek,mt6589-wdt";
>
> According to [1] and [2], compatible string for mt8192 watch dog should
> be "mediatek,mt6873-wdt","mediatek,mt8192-wdt".
>
>
> [1]
> https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2287090/12
> [2]
> https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2131598/18
>
> > + reg = <0 0x10007000 0 0x100>;
> > + #reset-cells = <1>;
> > + };
> > +
>
> [snip]
>
> > +
> > + mmsys: mmsys@1400 {
> > + compatible = "mediatek,mt8192-mmsys", "syscon";
>
> You should define "mediatek,mt8192-mmsys" first, then you could use it
> in this patch
Sorry, this series depend on [1], but mmsys is a syscon, so this should
be
mmsys: syscon@1400 {
[1]
http://lists.infradead.org/pipermail/linux-mediatek/2020-July/014451.html
Regards,
CK
> .
>
> Regards,
> CK
>
> > + reg = <0 0x1400 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
>
Re: [PATCH v3 1/3] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile
Hi, Seiya:
On Wed, 2020-07-29 at 09:30 +0800, Seiya Wang wrote:
> Add basic chip support for Mediatek MT8192
>
> Signed-off-by: Seiya Wang
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 29 ++
> arch/arm64/boot/dts/mediatek/mt8192.dtsi| 671
>
> 3 files changed, 701 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8192.dtsi
>
[snip]
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt6589-wdt";
According to [1] and [2], compatible string for mt8192 watch dog should
be "mediatek,mt6873-wdt","mediatek,mt8192-wdt".
[1]
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2287090/12
[2]
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2131598/18
> + reg = <0 0x10007000 0 0x100>;
> + #reset-cells = <1>;
> + };
> +
[snip]
> +
> + mmsys: mmsys@1400 {
> + compatible = "mediatek,mt8192-mmsys", "syscon";
You should define "mediatek,mt8192-mmsys" first, then you could use it
in this patch.
Regards,
CK
> + reg = <0 0x1400 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
Re: [PATCH v4 09/17] media: mtk-vcodec: Get rid of mtk_smi_larb_get/put
+ Tiffany & Maoguang.
On Sat, 2020-05-30 at 16:10 +0800, Yong Wu wrote:
> MediaTek IOMMU has already added the device_link between the consumer
> and smi-larb device. If the vcodec device call the pm_runtime_get_sync,
> the smi-larb's pm_runtime_get_sync also be called automatically.
>
> CC: Tiffany Lin
> Signed-off-by: Yong Wu
> Reviewed-by: Evan Green
> ---
> .../media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c | 19 ---
> drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h | 3 ---
> drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c | 1 -
> .../media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c | 27
> --
> 4 files changed, 50 deletions(-)
>
> diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
> b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
> index 36dfe3f..1d7d14d 100644
> --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
> +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
> @@ -8,14 +8,12 @@
> #include
> #include
> #include
> -#include
>
> #include "mtk_vcodec_dec_pm.h"
> #include "mtk_vcodec_util.h"
>
> int mtk_vcodec_init_dec_pm(struct mtk_vcodec_dev *mtkdev)
> {
> - struct device_node *node;
> struct platform_device *pdev;
> struct mtk_vcodec_pm *pm;
> struct mtk_vcodec_clk *dec_clk;
> @@ -26,18 +24,7 @@ int mtk_vcodec_init_dec_pm(struct mtk_vcodec_dev *mtkdev)
> pm = >pm;
> pm->mtkdev = mtkdev;
> dec_clk = >vdec_clk;
> - node = of_parse_phandle(pdev->dev.of_node, "mediatek,larb", 0);
> - if (!node) {
> - mtk_v4l2_err("of_parse_phandle mediatek,larb fail!");
> - return -1;
> - }
>
> - pdev = of_find_device_by_node(node);
> - of_node_put(node);
> - if (WARN_ON(!pdev)) {
> - return -1;
> - }
> - pm->larbvdec = >dev;
> pdev = mtkdev->plat_dev;
> pm->dev = >dev;
>
> @@ -113,11 +100,6 @@ void mtk_vcodec_dec_clock_on(struct mtk_vcodec_pm *pm)
> }
> }
>
> - ret = mtk_smi_larb_get(pm->larbvdec);
> - if (ret) {
> - mtk_v4l2_err("mtk_smi_larb_get larbvdec fail %d", ret);
> - goto error;
> - }
> return;
>
> error:
> @@ -130,7 +112,6 @@ void mtk_vcodec_dec_clock_off(struct mtk_vcodec_pm *pm)
> struct mtk_vcodec_clk *dec_clk = >vdec_clk;
> int i = 0;
>
> - mtk_smi_larb_put(pm->larbvdec);
> for (i = dec_clk->clk_num - 1; i >= 0; i--)
> clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk);
> }
> diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
> b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
> index 52d1ce1..7d3966a 100644
> --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
> +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
> @@ -190,10 +190,7 @@ struct mtk_vcodec_clk {
> */
> struct mtk_vcodec_pm {
> struct mtk_vcodec_clk vdec_clk;
> - struct device *larbvdec;
> -
> struct mtk_vcodec_clk venc_clk;
> - struct device *larbvenc;
> struct device *dev;
> struct mtk_vcodec_dev *mtkdev;
> };
> diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
> b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
> index 5301dca..18025f7 100644
> --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
> +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
> @@ -8,7 +8,6 @@
> #include
> #include
> #include
> -#include
> #include
>
> #include "mtk_vcodec_drv.h"
> diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c
> b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c
> index 01c6a55..047919e 100644
> --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c
> +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c
> @@ -8,44 +8,25 @@
> #include
> #include
> #include
> -#include
>
> #include "mtk_vcodec_enc_pm.h"
> #include "mtk_vcodec_util.h"
>
> int mtk_vcodec_init_enc_pm(struct mtk_vcodec_dev *mtkdev)
> {
> - struct device_node *node;
> struct platform_device *pdev;
> struct mtk_vcodec_pm *pm;
> struct mtk_vcodec_clk *enc_clk;
> struct mtk_vcodec_clk_info *clk_info;
> int ret = 0, i = 0;
> - struct device *dev;
>
> pdev = mtkdev->plat_dev;
> pm = >pm;
> memset(pm, 0, sizeof(struct mtk_vcodec_pm));
> pm->mtkdev = mtkdev;
> pm->dev = >dev;
> - dev = >dev;
> enc_clk = >venc_clk;
>
> - node = of_parse_phandle(dev->of_node, "mediatek,larb", 0);
> - if (!node) {
> - mtk_v4l2_err("no mediatek,larb found");
> - return -ENODEV;
> - }
> - pdev = of_find_device_by_node(node);
> - of_node_put(node);
> - if (!pdev) {
> - mtk_v4l2_err("no mediatek,larb device found");
> - return -ENODEV;
> - }
> - pm->larbvenc = >dev;
> - pdev = mtkdev->plat_dev;
> - pm->dev = >dev;
> -
> enc_clk->clk_num =
Re: [PATCH v4 08/17] media: mtk-vcodec: separate mtk-vcodec-enc node.
+ Tiffany & Maoguang.
On Sat, 2020-05-30 at 16:10 +0800, Yong Wu wrote:
> From: Maoguang Meng
>
> MTK H264 Encoder(VENC_SYS) and VP8 Encoder(VENC_LT_SYS) are two
> independent hardware instance. They have their owner interrupt,
> register mapping, and special clocks.
>
> This patch seperates the two instance. This is a preparing patch for
> adding device_link between the larbs and venc-device. It's mainly for
> fixing the problem:
> https://lkml.org/lkml/2019/9/3/316
>
> User Call "VIDIOC_QUERYCAP":
> H264 Encoder return driver name "mtk-vcodec-enc";
> VP8 Encoder return driver name "mtk-venc-vp8.
>
> Signed-off-by: Maoguang Meng
> Signed-off-by: Hsin-Yi Wang
> Signed-off-by: Irui Wang
> ---
> drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h | 10 +-
> drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c | 23 +++-
> .../media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c | 127
> +
> .../media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c | 31 +
> .../media/platform/mtk-vcodec/mtk_vcodec_enc_pm.h | 1 -
> .../media/platform/mtk-vcodec/venc/venc_vp8_if.c | 4 +-
> 6 files changed, 80 insertions(+), 116 deletions(-)
>
> diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
> b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
> index a2716117..52d1ce1 100644
> --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
> +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_drv.h
> @@ -19,6 +19,7 @@
> #define MTK_VCODEC_DRV_NAME "mtk_vcodec_drv"
> #define MTK_VCODEC_DEC_NAME "mtk-vcodec-dec"
> #define MTK_VCODEC_ENC_NAME "mtk-vcodec-enc"
> +#define MTK_VENC_VP8_NAME"mtk-venc-vp8"
> #define MTK_PLATFORM_STR "platform:mt8173"
>
> #define MTK_VCODEC_MAX_PLANES3
> @@ -193,7 +194,6 @@ struct mtk_vcodec_pm {
>
> struct mtk_vcodec_clk venc_clk;
> struct device *larbvenc;
> - struct device *larbvenclt;
> struct device *dev;
> struct mtk_vcodec_dev *mtkdev;
> };
> @@ -311,25 +311,27 @@ enum mtk_chip {
> * @chip: chip this encoder is compatible with
> *
> * @uses_ext: whether the encoder uses the extended firmware messaging format
> - * @has_lt_irq: whether the encoder uses the LT irq
> + * @name: whether the encoder core is vp8
> * @min_birate: minimum supported encoding bitrate
> * @max_bitrate: maximum supported encoding bitrate
> * @capture_formats: array of supported capture formats
> * @num_capture_formats: number of entries in capture_formats
> * @output_formats: array of supported output formats
> * @num_output_formats: number of entries in output_formats
> + * @core_id: stand for h264 or vp8 encode index
> */
> struct mtk_vcodec_enc_pdata {
> enum mtk_chip chip;
>
> bool uses_ext;
> - bool has_lt_irq;
> + const char *name;
> unsigned long min_bitrate;
> unsigned long max_bitrate;
> const struct mtk_video_fmt *capture_formats;
> size_t num_capture_formats;
> const struct mtk_video_fmt *output_formats;
> size_t num_output_formats;
> + int core_id;
> };
>
> /**
> @@ -359,7 +361,6 @@ struct mtk_vcodec_enc_pdata {
> *
> * @dec_irq: decoder irq resource
> * @enc_irq: h264 encoder irq resource
> - * @enc_lt_irq: vp8 encoder irq resource
> *
> * @dec_mutex: decoder hardware lock
> * @enc_mutex: encoder hardware lock.
> @@ -395,7 +396,6 @@ struct mtk_vcodec_dev {
>
> int dec_irq;
> int enc_irq;
> - int enc_lt_irq;
>
> struct mutex dec_mutex;
> struct mutex enc_mutex;
> diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
> b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
> index f0af78f..5301dca 100644
> --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
> +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c
> @@ -9,6 +9,7 @@
> #include
> #include
> #include
> +#include
>
> #include "mtk_vcodec_drv.h"
> #include "mtk_vcodec_enc.h"
> @@ -174,7 +175,10 @@ static int vidioc_enum_fmt_vid_out(struct file *file,
> void *priv,
> static int vidioc_venc_querycap(struct file *file, void *priv,
> struct v4l2_capability *cap)
> {
> - strscpy(cap->driver, MTK_VCODEC_ENC_NAME, sizeof(cap->driver));
> + const struct mtk_vcodec_enc_pdata *pdata =
> + fh_to_ctx(priv)->dev->venc_pdata;
> +
> + strscpy(cap->driver, pdata->name, sizeof(cap->driver));
> strscpy(cap->bus_info, MTK_PLATFORM_STR, sizeof(cap->bus_info));
> strscpy(cap->card, MTK_PLATFORM_STR, sizeof(cap->card));
>
> @@ -788,7 +792,7 @@ static int vb2ops_venc_start_streaming(struct vb2_queue
> *q, unsigned int count)
> */
> if ((ctx->state == MTK_STATE_ABORT) || (ctx->state == MTK_STATE_FREE)) {
> ret = -EIO;
> - goto err_set_param;
> + goto err_start_stream;
> }
>
> /* Do the initialization when both start_streaming have been called */
> @@ -800,6 +804,12 @@ static
Re: [PATCH v5, 24/32] drm/mediatek: add clock property check before get it
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add clock property check before get it
>
I've rewrite this patch and applied to mediatek-drm-next-5.5 [1] with
the title "drm/mediatek: add no_clk into ddp private data", thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5
Regards,
CK
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index a5a6689..effc24a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -657,10 +657,12 @@ static int mtk_ddp_probe(struct platform_device *pdev)
> for (i = 0; i < 10; i++)
> ddp->mutex[i].id = i;
>
> - ddp->clk = devm_clk_get(dev, NULL);
> - if (IS_ERR(ddp->clk)) {
> - dev_err(dev, "Failed to get clock\n");
> - return PTR_ERR(ddp->clk);
> + if (of_find_property(dev->of_node, "clocks", )) {
> + ddp->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(ddp->clk)) {
> + dev_err(dev, "Failed to get clock\n");
> + return PTR_ERR(ddp->clk);
> + }
> }
>
> regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Re: [PATCH v5, 15/32] drm/mediatek: add commponent OVL_2L0
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add commponent OVL_2L0
>
Applied to mediatek-drm-next-5.5 [1], thanks.
[1]
https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5
Regards,
CK
> Signed-off-by: Yongqiang Niu
> Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index b18bd66..4200f89 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -219,6 +219,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
>
> static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_OVL] = "ovl",
> + [MTK_DISP_OVL_2L] = "ovl_2l",
> [MTK_DISP_RDMA] = "rdma",
> [MTK_DISP_WDMA] = "wdma",
> [MTK_DISP_COLOR] = "color",
> @@ -258,6 +259,7 @@ struct mtk_ddp_comp_match {
> [DDP_COMPONENT_OD1] = { MTK_DISP_OD,1, _od },
> [DDP_COMPONENT_OVL0]= { MTK_DISP_OVL, 0, NULL },
> [DDP_COMPONENT_OVL1]= { MTK_DISP_OVL, 1, NULL },
> + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,0, NULL },
> [DDP_COMPONENT_PWM0]= { MTK_DISP_PWM, 0, NULL },
> [DDP_COMPONENT_PWM1]= { MTK_DISP_PWM, 1, NULL },
> [DDP_COMPONENT_PWM2]= { MTK_DISP_PWM, 2, NULL },
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 8d220224..9caec2d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -17,6 +17,7 @@
>
> enum mtk_ddp_comp_type {
> MTK_DISP_OVL,
> + MTK_DISP_OVL_2L,
> MTK_DISP_RDMA,
> MTK_DISP_WDMA,
> MTK_DISP_COLOR,
> @@ -50,6 +51,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_OD0,
> DDP_COMPONENT_OD1,
> DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_OVL_2L0,
> DDP_COMPONENT_OVL1,
> DDP_COMPONENT_PWM0,
> DDP_COMPONENT_PWM1,
Re: [PATCH v15 1/4] soc: mediatek: cmdq: define the instruction struct
Hi, Bibby:
On Fri, 2019-09-27 at 19:42 +0800, Bibby Hsieh wrote:
> Define an instruction structure for gce driver to append command.
> This structure can make the client's code more readability.
>
> Signed-off-by: Bibby Hsieh
> Reviewed-by: CK Hu
You've modified this patch in this version, so you should drop this
'Reviewed-by' tag.
> Reviewed-by: Houlong Wei
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 106 +--
> include/linux/mailbox/mtk-cmdq-mailbox.h | 10 +++
> 2 files changed, 90 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 7aa0517ff2f3..7af327b98d25 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -9,12 +9,24 @@
> #include
> #include
>
> -#define CMDQ_ARG_A_WRITE_MASK0x
> #define CMDQ_WRITE_ENABLE_MASK BIT(0)
> #define CMDQ_EOC_IRQ_EN BIT(0)
> #define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \
> << 32 | CMDQ_EOC_IRQ_EN)
>
> +struct cmdq_instruction {
> + union {
> + u32 value;
> + u32 mask;
> + };
> + union {
> + u16 offset;
> + u16 event;
> + };
> + u8 subsys;
> + u8 op;
> +};
> +
> static void cmdq_client_timeout(struct timer_list *t)
> {
> struct cmdq_client *client = from_timer(client, t, timer);
> @@ -110,10 +122,10 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt)
> }
> EXPORT_SYMBOL(cmdq_pkt_destroy);
>
> -static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
> -u32 arg_a, u32 arg_b)
> +static int cmdq_pkt_append_command(struct cmdq_pkt *pkt,
> +struct cmdq_instruction *inst)
> {
> - u64 *cmd_ptr;
> + struct cmdq_instruction *cmd_ptr;
>
> if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) {
> /*
> @@ -129,8 +141,9 @@ static int cmdq_pkt_append_command(struct cmdq_pkt *pkt,
> enum cmdq_code code,
> __func__, (u32)pkt->buf_size);
> return -ENOMEM;
> }
> +
> cmd_ptr = pkt->va_base + pkt->cmd_buf_size;
> - (*cmd_ptr) = (u64)((code << CMDQ_OP_CODE_SHIFT) | arg_a) << 32 | arg_b;
> + *cmd_ptr = *inst;
> pkt->cmd_buf_size += CMDQ_INST_SIZE;
>
> return 0;
> @@ -138,24 +151,42 @@ static int cmdq_pkt_append_command(struct cmdq_pkt
> *pkt, enum cmdq_code code,
>
> int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
> {
> - u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) |
> - (subsys << CMDQ_SUBSYS_SHIFT);
> + struct cmdq_instruction *inst = kzalloc(sizeof(*inst), GFP_KERNEL);
Frequently allocate/free increase CPU loading. The simpler way is
struct cmdq_instruction inst = { 0 };
cmdq_pkt_append_command(pkt, );
> + int err = 0;
No need to assign initial value.
> +
> + if (!inst)
> + return -ENOMEM;
> +
> + inst->op = CMDQ_CODE_WRITE;
> + inst->value = value;
> + inst->offset = offset;
> + inst->subsys = subsys;
>
> - return cmdq_pkt_append_command(pkt, CMDQ_CODE_WRITE, arg_a, value);
> + err = cmdq_pkt_append_command(pkt, inst);
> + kfree(inst);
> +
> + return err;
> }
> EXPORT_SYMBOL(cmdq_pkt_write);
>
[snip]
>
> static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
> {
> - int err;
> + struct cmdq_instruction *inst = kzalloc(sizeof(*inst), GFP_KERNEL);
> + int err = 0;
> +
> + if (!inst)
> + return -ENOMEM;
>
> /* insert EOC and generate IRQ for each command iteration */
> - err = cmdq_pkt_append_command(pkt, CMDQ_CODE_EOC, 0, CMDQ_EOC_IRQ_EN);
> + inst->op = CMDQ_CODE_EOC;
> + inst->value = CMDQ_EOC_IRQ_EN;
> + err = cmdq_pkt_append_command(pkt, inst);
>
> /* JUMP to end */
> - err |= cmdq_pkt_append_command(pkt, CMDQ_CODE_JUMP, 0, CMDQ_JUMP_PASS);
> + inst->op = CMDQ_CODE_JUMP;
> + inst->value = CMDQ_JUMP_PASS;
> + err |= cmdq_pkt_append_command(pkt, inst);
OR the err value looks strange. If you OR err 0x1 and err 0x10, you
would get the new err 0x11. How do you know that err 0x11 is the
combination of 0x1 and 0x10?
This bug seems exist in previous patch, so I would like you to fix this
bug first and then apply this patch.
Regards,
CK
> + kfree(inst);
>
> return err;
> }
> diff --git a/include/linux
Re: [PATCH v6 0/7] Support dsi for mt8183
Hi, Jitao: For this series, applied to mediatek-drm-next-5.5 [1], and I break "[v6,2/7] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701" into two patches, thanks. [1] https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5 Regards, CK On Sun, 2019-08-11 at 18:40 +0800, Jitao Shi wrote: > Change since v5: > - fine tune dphy timing. > > Change since v4: > - move mipi_dsi_host_unregiter() to .remove() > - fine tune add frame size control coding style > - change the data type of data_rate as u32, and add DIV_ROUND_UP_ULL > - use div_u64 when 80ULL / dsi->data_rate. > > Changes since v3 > - add one more 'tab' for bitwise define. > - add Tested-by: Ryan Case > and Reviewed-by: CK Hu . > - remove compare da_hs_zero to da_hs_prepare. > > Changes since v2: > - change the video timing calc method > - fine the dsi and mipitx init sequence > - fine tune commit msg > > Changes since v1: > - separate frame size and reg commit control independent patches. > - fix some return values in probe > - remove DSI_CMDW0 in "CMDQ reg address of mt8173 is different with mt2701" > > Jitao Shi (7): > drm/mediatek: move mipi_dsi_host_register to probe > drm/mediatek: fixes CMDQ reg address of mt8173 is different with > mt2701 > drm/mediatek: add dsi reg commit disable control > drm/mediatek: add frame size control > drm/mediatek: add mt8183 dsi driver support > drm/mediatek: change the dsi phytiming calculate method > drm: mediatek: adjust dsi and mipi_tx probe sequence > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +- > drivers/gpu/drm/mediatek/mtk_dsi.c | 224 ++--- > 2 files changed, 161 insertions(+), 65 deletions(-) >
Re: [PATCH v6 0/3] Support mipitx for mt8183
Hi, Jitao: For this series, applied to mediatek-drm-next-5.5 [1], thanks. [1] https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5 Regards, CK On Wed, 2019-08-07 at 16:46 +0800, Jitao Shi wrote: > Change since v5: > - remove mipi_tx->ref_clk > - remove mt8183 pll prepare unprepare > > Change since v4: > - fine tune the mipi_tx->ref_clk and mipi_tx->pll sequence >1. Prepare mipi_tx->ref_clk >2. Prepare mipi_tx->pll >3. Enable mipi_tx->ref_clk >4. Enable mipi_tx->pll > > Changes since v3: > - turn off PLL before setting PLL parameters. > > Changes since v2: > - update Acked-by: Rob Herring > - update mt8183 max bit rate support > > Changes since v1: > - update dt-bindings document for mt8183 mipitx. > - remove mtk_mipitx_clk_get_ops and assign clk_ops in probe. > - fix the lincence > - remove txdiv1 from mtk_mipi_tx_pll_prepare > > Jitao Shi (3): > dt-bindings: display: mediatek: update dsi supported chips > drm/mediatek: separate mipi_tx to different file > drm/mediatek: add mipi_tx driver for mt8183 > > .../display/mediatek/mediatek,dsi.txt | 4 +- > drivers/gpu/drm/mediatek/Makefile | 2 + > drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 338 ++ > drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 49 +++ > drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 289 +++ > drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 150 > 6 files changed, 515 insertions(+), 317 deletions(-) > create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h > create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c > create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c >
Re: [PATCH 1/2] drm/mediatek: Only block updates to CRTCs that have a pending update
Hi, Bibby:
On Fri, 2019-08-30 at 15:38 +0800, Bibby Hsieh wrote:
> Currently we use a single mutex to allow only a single atomic
> update at a time. In truth, though, we really only want to
> ensure that only a single atomic update is allowed per CRTC.
>
> In other words, for each atomic update, we only block if there
> is a pending update for the CRTCs involved, and don't block if
> there are only pending updates for other CRTCs.
I don't know why this patch is so complicated. The original problem is
that one mutex for whole drm would block different crtc. So I think each
crtc has its own mutex would solve this problem and we need not the
event waiting. Do I miss something?
Regards,
CK
>
> Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
>
> Signed-off-by: Daniel Kurtz
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 14 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 182 +---
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 12 +-
> 3 files changed, 184 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index b55970a2869d..7697b40baac0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -5,6 +5,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -45,6 +46,8 @@ struct mtk_drm_crtc {
> struct mtk_disp_mutex *mutex;
> unsigned intddp_comp_nr;
> struct mtk_ddp_comp **ddp_comp;
> +
> + struct drm_crtc_state *old_crtc_state;
> };
>
> struct mtk_crtc_state {
> @@ -343,6 +346,7 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc
> *mtk_crtc)
> static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
> {
> struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> + struct drm_atomic_state *atomic_state = mtk_crtc->old_crtc_state->state;
> struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
> struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
> unsigned int i;
> @@ -382,6 +386,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
> }
> }
> mtk_crtc->pending_planes = false;
> + mtk_atomic_state_put_queue(atomic_state);
> }
> }
>
> @@ -451,6 +456,7 @@ static void mtk_drm_crtc_atomic_begin(struct drm_crtc
> *crtc,
> static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> struct drm_crtc_state *old_crtc_state)
> {
> + struct drm_atomic_state *old_atomic_state = old_crtc_state->state;
> struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> struct mtk_drm_private *priv = crtc->dev->dev_private;
> unsigned int pending_planes = 0;
> @@ -469,8 +475,13 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc
> *crtc,
> pending_planes |= BIT(i);
> }
> }
> - if (pending_planes)
> +
> + if (pending_planes) {
> mtk_crtc->pending_planes = true;
> + drm_atomic_state_get(old_atomic_state);
> + mtk_crtc->old_crtc_state = old_crtc_state;
> + }
> +
> if (crtc->state->color_mgmt_changed)
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> @@ -526,6 +537,7 @@ static int mtk_drm_crtc_init(struct drm_device *drm,
>
> void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp)
> {
> +
> struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> struct mtk_drm_private *priv = crtc->dev->dev_private;
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index c0928b69dc43..b0308a3a7483 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -31,11 +31,120 @@
> #define DRIVER_MAJOR 1
> #define DRIVER_MINOR 0
>
> -static void mtk_atomic_schedule(struct mtk_drm_private *private,
> +struct mtk_atomic_state {
> + struct drm_atomic_state base;
> + struct list_head list;
> + struct work_struct work;
> +};
> +
> +static inline struct mtk_atomic_state *to_mtk_state(struct drm_atomic_state
> *s)
> +{
> + return container_of(s, struct mtk_atomic_state, base);
> +}
> +
> +void mtk_atomic_state_put_queue(struct drm_atomic_state *state)
> +{
> + struct drm_device *drm = state->dev;
> + struct mtk_drm_private *mtk_drm = drm->dev_private;
> + struct mtk_atomic_state *mtk_state = to_mtk_state(state);
> + unsigned long flags;
> +
> + spin_lock_irqsave(_drm->unreference.lock, flags);
> + list_add_tail(_state->list, _drm->unreference.list);
> + spin_unlock_irqrestore(_drm->unreference.lock, flags);
> +
> + schedule_work(_drm->unreference.work);
> +}
> +
> +static uint32_t
Re: [PATCH v5, 30/32] drm/mediatek: add connection from DITHER0 to DSI0
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from DITHER0 to DSI0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 237824f..fd38658 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -35,10 +35,12 @@
>
> #define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04
> #define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08
> +#define MT8183_DISP_DITHER0_MOUT_EN 0xf0c
> #define MT8183_DISP_PATH0_SEL_IN 0xf24
>
> #define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
> #define OVL1_2L_MOUT_EN_RDMA1BIT(4)
> +#define DITHER0_MOUT_IN_DSI0 BIT(0)
> #define DISP_PATH0_SEL_IN_OVL0_2L0x1
>
> #define MT2701_DISP_MUTEX0_MOD0 0x2c
> @@ -323,6 +325,9 @@ static unsigned int mtk_ddp_mout_en(const struct
> mtk_mmsys_reg_data *data,
> next == DDP_COMPONENT_RDMA1) {
> *addr = MT8183_DISP_OVL1_2L_MOUT_EN;
> value = OVL1_2L_MOUT_EN_RDMA1;
> + } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> + *addr = MT8183_DISP_DITHER0_MOUT_EN;
> + value = DITHER0_MOUT_IN_DSI0;
> } else {
> value = 0;
> }
Re: [PATCH v5, 26/32] drm/mediatek: add connection from RDMA0 to COLOR0
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from RDMA0 to COLOR0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 42a130a..03a46ec 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -171,6 +171,8 @@ struct mtk_ddp {
>
> struct mtk_mmsys_reg_data {
> u32 ovl0_mout_en;
> + u32 rdma0_sout_sel_in;
> + u32 rdma0_sout_color0;
> u32 rdma1_sout_sel_in;
> u32 rdma1_sout_dpi0;
> u32 dpi0_sel_in;
> @@ -428,6 +430,9 @@ static unsigned int mtk_ddp_sout_sel(const struct
> mtk_mmsys_reg_data *data,
> } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> value = RDMA2_SOUT_DSI3;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
> + *addr = data->rdma0_sout_sel_in;
> + value = data->rdma0_sout_color0;
> } else {
> value = 0;
> }
Re: [PATCH v5, 12/32] drm/mediatek: add mmsys private data for ddp path config
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add mmsys private data for ddp path config
> all these register offset and value will be different in future SOC
> add these define into mmsys private data
> u32 ovl0_mout_en;
> u32 rdma1_sout_sel_in;
> u32 rdma1_sout_dsi0;
> u32 dpi0_sel_in;
> u32 dpi0_sel_in_rdma1;
> u32 dsi0_sel_in;
> u32 dsi0_sel_in_rdma1;
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 ++
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 86
> +++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 5 ++
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 ++
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 3 ++
> 5 files changed, 76 insertions(+), 25 deletions(-)
>
[snip]
>
> void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> + const struct mtk_mmsys_reg_data *reg_data,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> {
> unsigned int addr, value, reg;
>
> - value = mtk_ddp_mout_en(cur, next, );
> + value = mtk_ddp_mout_en(reg_data, cur, next, );
> if (value) {
> reg = readl_relaxed(config_regs + addr) | value;
> writel_relaxed(reg, config_regs + addr);
> }
>
> - mtk_ddp_sout_sel(config_regs, cur, next);
> + value = mtk_ddp_sout_sel(reg_data, cur, next, );
> + if (value)
> + writel_relaxed(value, config_regs + addr);
I think the register could be written inside mtk_ddp_sout_sel(), why do
you move out of that function?
Regards,
CK
>
> - value = mtk_ddp_sel_in(cur, next, );
> + value = mtk_ddp_sel_in(reg_data, cur, next, );
> if (value) {
> reg = readl_relaxed(config_regs + addr) | value;
> writel_relaxed(reg, config_regs + addr);
> @@ -420,18 +455,19 @@ void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> }
>
>
>
Re: [PATCH v6 14/14] arm64: dts: Add power controller device node of MT8183
Hi, Matthias:
On Thu, 2019-08-29 at 09:19 +0200, Matthias Brugger wrote:
>
> On 01/07/2019 10:57, CK Hu wrote:
> > Hi, Weiyi:
> >
> > On Thu, 2019-06-20 at 10:38 +0800, Weiyi Lu wrote:
> >> Add power controller node and smi-common node for MT8183
> >> In scpsys node, it contains clocks and regmapping of
> >> infracfg and smi-common for bus protection.
> >>
> >> Signed-off-by: Weiyi Lu
> >> ---
> >> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62
> >>
> >> 1 file changed, 62 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> index 08274bf..75c4881 100644
> >> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> @@ -8,6 +8,7 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >>
> >> / {
> >>compatible = "mediatek,mt8183";
> >> @@ -196,6 +197,62 @@
> >>#clock-cells = <1>;
> >>};
> >>
> >> + scpsys: syscon@10006000 {
> >> + compatible = "mediatek,mt8183-scpsys", "syscon";
> >> + #power-domain-cells = <1>;
> >> + reg = <0 0x10006000 0 0x1000>;
> >> + clocks = < CLK_TOP_MUX_AUD_INTBUS>,
> >> + < CLK_INFRA_AUDIO>,
> >> + < CLK_INFRA_AUDIO_26M_BCLK>,
> >> + < CLK_TOP_MUX_MFG>,
> >> + < CLK_TOP_MUX_MM>,
> >> + < CLK_TOP_MUX_CAM>,
> >> + < CLK_TOP_MUX_IMG>,
> >> + < CLK_TOP_MUX_IPU_IF>,
> >> + < CLK_TOP_MUX_DSP>,
> >> + < CLK_TOP_MUX_DSP1>,
> >> + < CLK_TOP_MUX_DSP2>,
> >> + < CLK_MM_SMI_COMMON>,
> >> + < CLK_MM_SMI_LARB0>,
> >> + < CLK_MM_SMI_LARB1>,
> >> + < CLK_MM_GALS_COMM0>,
> >> + < CLK_MM_GALS_COMM1>,
> >> + < CLK_MM_GALS_CCU2MM>,
> >> + < CLK_MM_GALS_IPU12MM>,
> >> + < CLK_MM_GALS_IMG2MM>,
> >> + < CLK_MM_GALS_CAM2MM>,
> >> + < CLK_MM_GALS_IPU2MM>,
> >
> > Up to now, MT8183 mmsys has the same resource with another device node:
> >
> > mmsys: syscon@1400 {
> > compatible = "mediatek,mt8183-mmsys", "syscon";
> > reg = <0 0x1400 0 0x1000>;
> > #clock-cells = <1>;
> > };
> >
> > display_components: dispsys@1400 {
> > compatible = "mediatek,mt8183-display";
> > reg = <0 0x1400 0 0x1000>;
> > power-domains = < MT8183_POWER_DOMAIN_DISP>;
> > };
> >
> > I think this two node should be merge into one node, so I've try to
> > merge them:
> >
> > mmsys: syscon@1400 {
> > compatible = "mediatek,mt8183-mmsys", "syscon";
> > reg = <0 0x1400 0 0x1000>;
> > power-domains = < MT8183_POWER_DOMAIN_DISP>;
> > #clock-cells = <1>;
> > };
> >
> > But I got a kernel panic when boot,
> >
> > [3.458523] Unable to handle kernel paging request at virtual address
> > fdfb
> > [3.466999] Mem abort info:
> > [3.470116] ESR = 0x9605
> > [3.473268] Exception class = DABT (current EL), IL = 32 bits
> > [3.479375] SET = 0, FnV = 0
> > [3.482530] EA = 0, S1PTW = 0
> > [3.485785] Data abort info:
> > [3.488831] ISV = 0, ISS = 0x0005
> > [3.493067] CM = 0, WnR = 0
> > [3.496229] swapper pgtable: 4k pages, 39-bit VAs, pgdp =
> > 4f8fa26d
> > [3.503214] [fff
Re: [PATCH v7 13/13] arm64: dts: Add power controller device node of MT8183
Hi, Weiyi:
On Wed, 2019-08-28 at 17:11 +0800, Weiyi Lu wrote:
> Add power controller node and smi-common node for MT8183
> In scpsys node, it contains clocks and regmapping of
> infracfg and smi-common for bus protection.
>
> Signed-off-by: Weiyi Lu
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62
>
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index c2749c4..66aaa07 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -8,6 +8,7 @@
> #include
> #include
> #include
> +#include
> #include "mt8183-pinfunc.h"
>
> / {
> @@ -238,6 +239,62 @@
> #interrupt-cells = <2>;
> };
>
> + scpsys: syscon@10006000 {
> + compatible = "mediatek,mt8183-scpsys", "syscon";
> + #power-domain-cells = <1>;
> + reg = <0 0x10006000 0 0x1000>;
> + clocks = < CLK_TOP_MUX_AUD_INTBUS>,
> + < CLK_INFRA_AUDIO>,
> + < CLK_INFRA_AUDIO_26M_BCLK>,
> + < CLK_TOP_MUX_MFG>,
> + < CLK_TOP_MUX_MM>,
> + < CLK_TOP_MUX_CAM>,
> + < CLK_TOP_MUX_IMG>,
> + < CLK_TOP_MUX_IPU_IF>,
> + < CLK_TOP_MUX_DSP>,
> + < CLK_TOP_MUX_DSP1>,
> + < CLK_TOP_MUX_DSP2>,
> + < CLK_MM_SMI_COMMON>,
> + < CLK_MM_SMI_LARB0>,
> + < CLK_MM_SMI_LARB1>,
> + < CLK_MM_GALS_COMM0>,
> + < CLK_MM_GALS_COMM1>,
> + < CLK_MM_GALS_CCU2MM>,
> + < CLK_MM_GALS_IPU12MM>,
> + < CLK_MM_GALS_IMG2MM>,
> + < CLK_MM_GALS_CAM2MM>,
> + < CLK_MM_GALS_IPU2MM>,
Just mention the discussion in [1], we need to confirm this is hardware
limitation or not.
[1] https://patchwork.kernel.org/patch/11005731/
Regards,
CK
> + < CLK_IMG_LARB5>,
> + < CLK_IMG_LARB2>,
> + < CLK_CAM_LARB6>,
> + < CLK_CAM_LARB3>,
> + < CLK_CAM_SENINF>,
> + < CLK_CAM_CAMSV0>,
> + < CLK_CAM_CAMSV1>,
> + < CLK_CAM_CAMSV2>,
> + < CLK_CAM_CCU>,
> + <_conn CLK_IPU_CONN_IPU>,
> + <_conn CLK_IPU_CONN_AHB>,
> + <_conn CLK_IPU_CONN_AXI>,
> + <_conn CLK_IPU_CONN_ISP>,
> + <_conn CLK_IPU_CONN_CAM_ADL>,
> + <_conn CLK_IPU_CONN_IMG_ADL>;
> + clock-names = "audio", "audio1", "audio2",
> + "mfg", "mm", "cam",
> + "isp", "vpu", "vpu1",
> + "vpu2", "vpu3", "mm-0",
> + "mm-1", "mm-2", "mm-3",
> + "mm-4", "mm-5", "mm-6",
> + "mm-7", "mm-8", "mm-9",
> + "isp-0", "isp-1", "cam-0",
> + "cam-1", "cam-2", "cam-3",
> + "cam-4", "cam-5", "cam-6",
> + "vpu-0", "vpu-1", "vpu-2",
> + "vpu-3", "vpu-4", "vpu-5";
> + infracfg = <>;
> + smi_comm = <_common>;
> + };
> +
> apmixedsys: syscon@1000c000 {
> compatible = "mediatek,mt8183-apmixedsys", "syscon";
> reg = <0 0x1000c000 0 0x1000>;
> @@ -396,6 +453,11 @@
> #clock-cells = <1>;
> };
>
> + smi_common: smi@14019000 {
> + compatible = "mediatek,mt8183-smi-common", "syscon";
> + reg = <0 0x14019000 0 0x1000>;
> + };
> +
> imgsys: syscon@1502 {
> compatible = "mediatek,mt8183-imgsys", "syscon";
> reg = <0 0x1502 0 0x1000>;
Re: [PATCH v13 09/12] soc: mediatek: cmdq: define the instruction struct
Hi, Bibby:
On Tue, 2019-08-20 at 16:36 +0800, Bibby Hsieh wrote:
> Define an instruction structure for gce driver to append command.
> This structure can make the client's code more readability.
>
> Signed-off-by: Bibby Hsieh
> Reviewed-by: CK Hu
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 106 +++
> include/linux/mailbox/mtk-cmdq-mailbox.h | 2 +
> 2 files changed, 74 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 7aa0517ff2f3..cae6a794cc48 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -9,12 +9,24 @@
> #include
> #include
>
> -#define CMDQ_ARG_A_WRITE_MASK0x
> #define CMDQ_WRITE_ENABLE_MASK BIT(0)
> #define CMDQ_EOC_IRQ_EN BIT(0)
> #define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \
> << 32 | CMDQ_EOC_IRQ_EN)
>
> +struct cmdq_instruction {
> + union {
> + u32 value;
> + u32 mask;
> + };
> + union {
> + u16 offset;
> + u16 event;
> + };
> + u8 subsys;
> + u8 op;
> +};
> +
> static void cmdq_client_timeout(struct timer_list *t)
> {
> struct cmdq_client *client = from_timer(client, t, timer);
> @@ -110,10 +122,8 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt)
> }
> EXPORT_SYMBOL(cmdq_pkt_destroy);
>
> -static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
> -u32 arg_a, u32 arg_b)
> +static struct cmdq_instruction *cmdq_pkt_append_command(struct cmdq_pkt *pkt)
> {
> - u64 *cmd_ptr;
>
> if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) {
> /*
> @@ -127,81 +137,109 @@ static int cmdq_pkt_append_command(struct cmdq_pkt
> *pkt, enum cmdq_code code,
> pkt->cmd_buf_size += CMDQ_INST_SIZE;
> WARN_ONCE(1, "%s: buffer size %u is too small !\n",
> __func__, (u32)pkt->buf_size);
> - return -ENOMEM;
> + return NULL;
> }
> - cmd_ptr = pkt->va_base + pkt->cmd_buf_size;
> - (*cmd_ptr) = (u64)((code << CMDQ_OP_CODE_SHIFT) | arg_a) << 32 | arg_b;
> +
> pkt->cmd_buf_size += CMDQ_INST_SIZE;
> + *(u64 *)(pkt->va_base + pkt->cmd_buf_size) = 0;
I think this statement should before 'pkt->cmd_buf_size +=
CMDQ_INST_SIZE;'
Regards,
CK
>
> - return 0;
> + return pkt->va_base + pkt->cmd_buf_size - CMDQ_INST_SIZE;
> }
>
> int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
> {
> - u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) |
> - (subsys << CMDQ_SUBSYS_SHIFT);
> + struct cmdq_instruction *inst;
> +
> + inst = cmdq_pkt_append_command(pkt);
> + if (!inst)
> + return -ENOMEM;
> +
> + inst->op = CMDQ_CODE_WRITE;
> + inst->value = value;
> + inst->offset = offset;
> + inst->subsys = subsys;
>
> - return cmdq_pkt_append_command(pkt, CMDQ_CODE_WRITE, arg_a, value);
> + return 0;
> }
> EXPORT_SYMBOL(cmdq_pkt_write);
>
> int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
> u16 offset, u32 value, u32 mask)
> {
> - u32 offset_mask = offset;
> - int err = 0;
> + struct cmdq_instruction *inst;
> + u16 offset_mask = offset;
>
> if (mask != 0x) {
> - err = cmdq_pkt_append_command(pkt, CMDQ_CODE_MASK, 0, ~mask);
> + inst = cmdq_pkt_append_command(pkt);
> + if (!inst)
> + return -ENOMEM;
> +
> + inst->op = CMDQ_CODE_MASK;
> + inst->mask = ~mask;
> offset_mask |= CMDQ_WRITE_ENABLE_MASK;
> }
> - err |= cmdq_pkt_write(pkt, value, subsys, offset_mask);
>
> - return err;
> + return cmdq_pkt_write(pkt, subsys, offset_mask, value);
> }
> EXPORT_SYMBOL(cmdq_pkt_write_mask);
>
> int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
> {
> - u32 arg_b;
> + struct cmdq_instruction *inst;
>
> if (event >= CMDQ_MAX_EVENT)
> return -EINVAL;
>
> - /*
> - * WFE arg_b
> - * bit 0-11: wait value
> - * bit 15: 1 - wait, 0 - no wait
> - * bit 16-27: update value
> - * bit 31: 1 - update, 0 - no update
> - */
> - arg_b = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ
Re: [PATCH v12 11/12] soc: mediatek: cmdq: add cmdq_dev_get_client_reg function
Hi, Bibby:
On Mon, 2019-08-19 at 10:53 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the cmdq_client_reg structure.
Reviewed-by: CK Hu
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 29 ++
> include/linux/soc/mediatek/mtk-cmdq.h | 21 +++
> 2 files changed, 50 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 340a92a254e5..1bed07362b7a 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -27,6 +27,35 @@ struct cmdq_instruction {
> u8 op;
> };
>
> +int cmdq_dev_get_client_reg(struct device *dev,
> + struct cmdq_client_reg *client_reg, int idx)
> +{
> + struct of_phandle_args spec;
> + int err;
> +
> + if (!client_reg)
> + return -ENOENT;
> +
> + err = of_parse_phandle_with_fixed_args(dev->of_node,
> +"mediatek,gce-client-reg",
> +3, idx, );
> + if (err < 0) {
> + dev_err(dev,
> + "error %d can't parse gce-client-reg property (%d)",
> + err, idx);
> +
> + return err;
> + }
> +
> + client_reg->subsys = (u8)spec.args[0];
> + client_reg->offset = (u16)spec.args[1];
> + client_reg->size = (u16)spec.args[2];
> + of_node_put(spec.np);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(cmdq_dev_get_client_reg);
> +
> static void cmdq_client_timeout(struct timer_list *t)
> {
> struct cmdq_client *client = from_timer(client, t, timer);
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index a345870a6d10..6215d4fc4ba3 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -15,6 +15,12 @@
>
> struct cmdq_pkt;
>
> +struct cmdq_client_reg {
> + u8 subsys;
> + u16 offset;
> + u16 size;
> +};
> +
> struct cmdq_client {
> spinlock_t lock;
> u32 pkt_cnt;
> @@ -24,6 +30,21 @@ struct cmdq_client {
> u32 timeout_ms; /* in unit of microsecond */
> };
>
> +/**
> + * cmdq_dev_get_client_reg() - parse cmdq client reg from the device
> + * node of CMDQ client
> + * @dev: device of CMDQ mailbox clienti
> + * @client_reg: CMDQ client reg pointer
> + * @idx: the index of desired reg
> + *
> + * Return: 0 for success; else the error code is returned
> + *
> + * Help CMDQ client pasing the cmdq client reg
> + * from the device node of CMDQ client.
> + */
> +int cmdq_dev_get_client_reg(struct device *dev,
> + struct cmdq_client_reg *client_reg, int idx);
> +
> /**
> * cmdq_mbox_create() - create CMDQ mailbox client and channel
> * @dev: device of CMDQ mailbox client
Re: [PATCH v6 14/14] arm64: dts: Add power controller device node of MT8183
Hi, Weiyi:
On Tue, 2019-07-23 at 12:06 +0800, Weiyi Lu wrote:
> On Tue, 2019-07-16 at 09:50 +0800, CK Hu wrote:
> > Hi, Weiyi:
> >
> > On Mon, 2019-07-15 at 17:07 +0800, Weiyi Lu wrote:
> > > On Mon, 2019-07-15 at 16:07 +0800, CK Hu wrote:
> > > > Hi, Weiyi:
> > > >
> > > > On Mon, 2019-07-01 at 16:57 +0800, CK Hu wrote:
> > > > > Hi, Weiyi:
> > > > >
> > > > > On Thu, 2019-06-20 at 10:38 +0800, Weiyi Lu wrote:
> > > > > > Add power controller node and smi-common node for MT8183
> > > > > > In scpsys node, it contains clocks and regmapping of
> > > > > > infracfg and smi-common for bus protection.
> > > > > >
> > > > > > Signed-off-by: Weiyi Lu
> > > > > > ---
> > > > > > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62
> > > > > >
> > > > > > 1 file changed, 62 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > > > > > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > > > > > index 08274bf..75c4881 100644
> > > > > > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > > > > > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > > > > > @@ -8,6 +8,7 @@
> > > > > > #include
> > > > > > #include
> > > > > > #include
> > > > > > +#include
> > > > > >
> > > > > > / {
> > > > > > compatible = "mediatek,mt8183";
> > > > > > @@ -196,6 +197,62 @@
> > > > > > #clock-cells = <1>;
> > > > > > };
> > > > > >
> > > > > > + scpsys: syscon@10006000 {
> > > > > > + compatible = "mediatek,mt8183-scpsys", "syscon";
> > > > > > + #power-domain-cells = <1>;
> > > > > > + reg = <0 0x10006000 0 0x1000>;
> > > > > > + clocks = < CLK_TOP_MUX_AUD_INTBUS>,
> > > > > > +< CLK_INFRA_AUDIO>,
> > > > > > +< CLK_INFRA_AUDIO_26M_BCLK>,
> > > > > > +< CLK_TOP_MUX_MFG>,
> > > > > > +< CLK_TOP_MUX_MM>,
> > > > > > +< CLK_TOP_MUX_CAM>,
> > > > > > +< CLK_TOP_MUX_IMG>,
> > > > > > +< CLK_TOP_MUX_IPU_IF>,
> > > > > > +< CLK_TOP_MUX_DSP>,
> > > > > > +< CLK_TOP_MUX_DSP1>,
> > > > > > +< CLK_TOP_MUX_DSP2>,
> > > > > > +< CLK_MM_SMI_COMMON>,
> > > > > > +< CLK_MM_SMI_LARB0>,
> > > > > > +< CLK_MM_SMI_LARB1>,
> > > > > > +< CLK_MM_GALS_COMM0>,
> > > > > > +< CLK_MM_GALS_COMM1>,
> > > > > > +< CLK_MM_GALS_CCU2MM>,
> > > > > > +< CLK_MM_GALS_IPU12MM>,
> > > > > > +< CLK_MM_GALS_IMG2MM>,
> > > > > > +< CLK_MM_GALS_CAM2MM>,
> > > > > > +< CLK_MM_GALS_IPU2MM>,
> > > >
> > > > I've removed all mmsys clock in scpsys node and display still works, so
> > > > I think these subsys clock could be removed from scpsys node. It's
> > > > reasonable that subsys clock is controlled by subsys device or the
> > > > device use it. In MT2712 [1], the scpsys does not control subsys clock
> > > > and it works, so I think you should remove subsys clock in scpsys device
> > > > node.
> > > >
> > > > [1]
> > > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt2712e.dtsi?h=v5.2
> > > >
> > > > Regards,
> > > &g
Re: [PATCH v6 14/14] arm64: dts: Add power controller device node of MT8183
Hi, Weiyi:
On Mon, 2019-07-15 at 17:07 +0800, Weiyi Lu wrote:
> On Mon, 2019-07-15 at 16:07 +0800, CK Hu wrote:
> > Hi, Weiyi:
> >
> > On Mon, 2019-07-01 at 16:57 +0800, CK Hu wrote:
> > > Hi, Weiyi:
> > >
> > > On Thu, 2019-06-20 at 10:38 +0800, Weiyi Lu wrote:
> > > > Add power controller node and smi-common node for MT8183
> > > > In scpsys node, it contains clocks and regmapping of
> > > > infracfg and smi-common for bus protection.
> > > >
> > > > Signed-off-by: Weiyi Lu
> > > > ---
> > > > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62
> > > >
> > > > 1 file changed, 62 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > > > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > > > index 08274bf..75c4881 100644
> > > > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > > > @@ -8,6 +8,7 @@
> > > > #include
> > > > #include
> > > > #include
> > > > +#include
> > > >
> > > > / {
> > > > compatible = "mediatek,mt8183";
> > > > @@ -196,6 +197,62 @@
> > > > #clock-cells = <1>;
> > > > };
> > > >
> > > > + scpsys: syscon@10006000 {
> > > > + compatible = "mediatek,mt8183-scpsys", "syscon";
> > > > + #power-domain-cells = <1>;
> > > > + reg = <0 0x10006000 0 0x1000>;
> > > > + clocks = < CLK_TOP_MUX_AUD_INTBUS>,
> > > > +< CLK_INFRA_AUDIO>,
> > > > +< CLK_INFRA_AUDIO_26M_BCLK>,
> > > > +< CLK_TOP_MUX_MFG>,
> > > > +< CLK_TOP_MUX_MM>,
> > > > +< CLK_TOP_MUX_CAM>,
> > > > +< CLK_TOP_MUX_IMG>,
> > > > +< CLK_TOP_MUX_IPU_IF>,
> > > > +< CLK_TOP_MUX_DSP>,
> > > > +< CLK_TOP_MUX_DSP1>,
> > > > +< CLK_TOP_MUX_DSP2>,
> > > > +< CLK_MM_SMI_COMMON>,
> > > > +< CLK_MM_SMI_LARB0>,
> > > > +< CLK_MM_SMI_LARB1>,
> > > > +< CLK_MM_GALS_COMM0>,
> > > > +< CLK_MM_GALS_COMM1>,
> > > > +< CLK_MM_GALS_CCU2MM>,
> > > > +< CLK_MM_GALS_IPU12MM>,
> > > > +< CLK_MM_GALS_IMG2MM>,
> > > > +< CLK_MM_GALS_CAM2MM>,
> > > > +< CLK_MM_GALS_IPU2MM>,
> >
> > I've removed all mmsys clock in scpsys node and display still works, so
> > I think these subsys clock could be removed from scpsys node. It's
> > reasonable that subsys clock is controlled by subsys device or the
> > device use it. In MT2712 [1], the scpsys does not control subsys clock
> > and it works, so I think you should remove subsys clock in scpsys device
> > node.
> >
> > [1]
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt2712e.dtsi?h=v5.2
> >
> > Regards,
> > CK
> >
>
> Hello CK,
>
> Sorry, I can't agree with you at all.
> I thought you just created an environment where the MM (DISP) power
> domain could not be turned on and off properly.
> If you delete those mmsys clocks listed, bus protection will not work.
> These clocks are used for bus protection that I mentioned in patch [2].
> I guess you are now trying to solve the problem that mmsys blocks are
> used for probing two drivers. One for the display and another for the
> clock. Right?
> In the previous test you mentioned, you have affected the registration
> of mmsys clock first. This is why you saw the boot failure. I think boot
> failure is the real problem I should avoid if mmsys clock cann
Re: [PATCH v6 7/8] arm64: dts: mediatek: add mt6765 support
Hi, Macpaul:
On Fri, 2019-07-12 at 17:43 +0800, Macpaul Lin wrote:
> From: Mars Cheng
>
> Add basic chip support for Mediatek 6765, include
> uart node with correct uart clocks, pwrap device
>
> Add clock controller nodes, include topckgen, infracfg,
> apmixedsys and subsystem.
>
> Signed-off-by: Mars Cheng
> Signed-off-by: Owen Chen
> Signed-off-by: Macpaul Lin
> Acked-by: Marc Zyngier
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 +++
> arch/arm64/boot/dts/mediatek/mt6765.dtsi| 253
> 3 files changed, 287 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> b/arch/arm64/boot/dts/mediatek/Makefile
> index 458bbc422a94..22bdf1a99a62 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt6765-evb.dts
> b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts
> new file mode 100644
> index ..36dddff2b7f8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * dts file for Mediatek MT6765
> + *
> + * (C) Copyright 2018. Mediatek, Inc.
> + *
> + * Mars Cheng
> + */
> +
> +/dts-v1/;
> +#include "mt6765.dtsi"
> +
> +/ {
> + model = "MediaTek MT6765 EVB";
> + compatible = "mediatek,mt6765-evb", "mediatek,mt6765";
> +
> + aliases {
> + serial0 =
> + };
> +
> + memory@4000 {
> + device_type = "memory";
> + reg = <0 0x4000 0 0x1e80>;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +};
> +
> + {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt6765.dtsi
> b/arch/arm64/boot/dts/mediatek/mt6765.dtsi
> new file mode 100644
> index ..2662470fe607
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt6765.dtsi
> @@ -0,0 +1,253 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * dts file for Mediatek MT6765
> + *
> + * (C) Copyright 2018. Mediatek, Inc.
> + *
> + * Mars Cheng
> + */
> +
> +#include
> +#include
> +#include
> +
> +/ {
> + compatible = "mediatek,mt6765";
> + interrupt-parent = <>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x000>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x001>;
> + };
> +
> + cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x002>;
> + };
> +
> + cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x003>;
> + };
> +
> + cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x100>;
> + };
> +
> + cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x101>;
> + };
> +
> + cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x102>;
> + };
> +
> + cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x103>;
> + };
> + };
> +
> + clocks {
> + clk26m: clk26m {
> + compatible =
Re: [PATCH v6 14/14] arm64: dts: Add power controller device node of MT8183
Hi, Weiyi:
On Mon, 2019-07-01 at 16:57 +0800, CK Hu wrote:
> Hi, Weiyi:
>
> On Thu, 2019-06-20 at 10:38 +0800, Weiyi Lu wrote:
> > Add power controller node and smi-common node for MT8183
> > In scpsys node, it contains clocks and regmapping of
> > infracfg and smi-common for bus protection.
> >
> > Signed-off-by: Weiyi Lu
> > ---
> > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62
> >
> > 1 file changed, 62 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > index 08274bf..75c4881 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > @@ -8,6 +8,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > / {
> > compatible = "mediatek,mt8183";
> > @@ -196,6 +197,62 @@
> > #clock-cells = <1>;
> > };
> >
> > + scpsys: syscon@10006000 {
> > + compatible = "mediatek,mt8183-scpsys", "syscon";
> > + #power-domain-cells = <1>;
> > + reg = <0 0x10006000 0 0x1000>;
> > + clocks = < CLK_TOP_MUX_AUD_INTBUS>,
> > +< CLK_INFRA_AUDIO>,
> > +< CLK_INFRA_AUDIO_26M_BCLK>,
> > +< CLK_TOP_MUX_MFG>,
> > +< CLK_TOP_MUX_MM>,
> > +< CLK_TOP_MUX_CAM>,
> > +< CLK_TOP_MUX_IMG>,
> > +< CLK_TOP_MUX_IPU_IF>,
> > +< CLK_TOP_MUX_DSP>,
> > +< CLK_TOP_MUX_DSP1>,
> > +< CLK_TOP_MUX_DSP2>,
> > +< CLK_MM_SMI_COMMON>,
> > +< CLK_MM_SMI_LARB0>,
> > +< CLK_MM_SMI_LARB1>,
> > +< CLK_MM_GALS_COMM0>,
> > +< CLK_MM_GALS_COMM1>,
> > +< CLK_MM_GALS_CCU2MM>,
> > +< CLK_MM_GALS_IPU12MM>,
> > +< CLK_MM_GALS_IMG2MM>,
> > +< CLK_MM_GALS_CAM2MM>,
> > +< CLK_MM_GALS_IPU2MM>,
I've removed all mmsys clock in scpsys node and display still works, so
I think these subsys clock could be removed from scpsys node. It's
reasonable that subsys clock is controlled by subsys device or the
device use it. In MT2712 [1], the scpsys does not control subsys clock
and it works, so I think you should remove subsys clock in scpsys device
node.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt2712e.dtsi?h=v5.2
Regards,
CK
>
> Up to now, MT8183 mmsys has the same resource with another device node:
>
> mmsys: syscon@1400 {
> compatible = "mediatek,mt8183-mmsys", "syscon";
> reg = <0 0x1400 0 0x1000>;
> #clock-cells = <1>;
> };
>
> display_components: dispsys@1400 {
> compatible = "mediatek,mt8183-display";
> reg = <0 0x1400 0 0x1000>;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> };
>
> I think this two node should be merge into one node, so I've try to
> merge them:
>
> mmsys: syscon@1400 {
> compatible = "mediatek,mt8183-mmsys", "syscon";
> reg = <0 0x1400 0 0x1000>;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> #clock-cells = <1>;
> };
>
> But I got a kernel panic when boot,
>
> [3.458523] Unable to handle kernel paging request at virtual address
> fdfb
> [3.466999] Mem abort info:
> [3.470116] ESR = 0x9605
> [3.473268] Exception class = DABT (current EL), IL = 32 bits
> [3.479375] SET = 0, FnV = 0
> [3.482530] EA = 0, S1PTW = 0
> [3.485785] Data abort info:
> [3.488831] ISV = 0, ISS = 0x0005
> [3.493067] CM = 0, WnR = 0
> [3.496229] swapper pgtable: 4k pages,
Re: [PATCH v6 14/14] arm64: dts: Add power controller device node of MT8183
Hi, Weiyi:
On Thu, 2019-06-20 at 10:38 +0800, Weiyi Lu wrote:
> Add power controller node and smi-common node for MT8183
> In scpsys node, it contains clocks and regmapping of
> infracfg and smi-common for bus protection.
>
> Signed-off-by: Weiyi Lu
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62
>
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 08274bf..75c4881 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -8,6 +8,7 @@
> #include
> #include
> #include
> +#include
>
> / {
> compatible = "mediatek,mt8183";
> @@ -196,6 +197,62 @@
> #clock-cells = <1>;
> };
>
> + scpsys: syscon@10006000 {
> + compatible = "mediatek,mt8183-scpsys", "syscon";
> + #power-domain-cells = <1>;
> + reg = <0 0x10006000 0 0x1000>;
> + clocks = < CLK_TOP_MUX_AUD_INTBUS>,
> + < CLK_INFRA_AUDIO>,
> + < CLK_INFRA_AUDIO_26M_BCLK>,
> + < CLK_TOP_MUX_MFG>,
> + < CLK_TOP_MUX_MM>,
> + < CLK_TOP_MUX_CAM>,
> + < CLK_TOP_MUX_IMG>,
> + < CLK_TOP_MUX_IPU_IF>,
> + < CLK_TOP_MUX_DSP>,
> + < CLK_TOP_MUX_DSP1>,
> + < CLK_TOP_MUX_DSP2>,
> + < CLK_MM_SMI_COMMON>,
> + < CLK_MM_SMI_LARB0>,
> + < CLK_MM_SMI_LARB1>,
> + < CLK_MM_GALS_COMM0>,
> + < CLK_MM_GALS_COMM1>,
> + < CLK_MM_GALS_CCU2MM>,
> + < CLK_MM_GALS_IPU12MM>,
> + < CLK_MM_GALS_IMG2MM>,
> + < CLK_MM_GALS_CAM2MM>,
> + < CLK_MM_GALS_IPU2MM>,
Up to now, MT8183 mmsys has the same resource with another device node:
mmsys: syscon@1400 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x1400 0 0x1000>;
#clock-cells = <1>;
};
display_components: dispsys@1400 {
compatible = "mediatek,mt8183-display";
reg = <0 0x1400 0 0x1000>;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
};
I think this two node should be merge into one node, so I've try to
merge them:
mmsys: syscon@1400 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x1400 0 0x1000>;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
#clock-cells = <1>;
};
But I got a kernel panic when boot,
[3.458523] Unable to handle kernel paging request at virtual address
fdfb
[3.466999] Mem abort info:
[3.470116] ESR = 0x9605
[3.473268] Exception class = DABT (current EL), IL = 32 bits
[3.479375] SET = 0, FnV = 0
[3.482530] EA = 0, S1PTW = 0
[3.485785] Data abort info:
[3.488831] ISV = 0, ISS = 0x0005
[3.493067] CM = 0, WnR = 0
[3.496229] swapper pgtable: 4k pages, 39-bit VAs, pgdp =
4f8fa26d
[3.503214] [fdfb] pgd=,
pud=
[3.510408] Internal error: Oops: 9605 [#1] PREEMPT SMP
[3.515974] Modules linked in:
[3.519023] Process kworker/0:3 (pid: 106, stack limit =
0x281d0651)
[3.526066] CPU: 0 PID: 106 Comm: kworker/0:3 Tainted: GW
4.19.43 #208
[3.533974] Hardware name: MediaTek kukui rev1 board (DT)
[3.539374] Workqueue: events deferred_probe_work_func
[3.544507] pstate: 2005 (nzCv daif -PAN -UAO)
[3.549294] pc : clk_prepare+0x18/0x40
[3.553038] lr : scpsys_clk_enable+0x40/0xb4
[3.557299] sp : ff800855b9e0
[3.560606] x29: ff800855b9f0 x28: ff93e1e5f594
[3.565911] x27: 000f x26: ff93e1e5e9b8
[3.571217] x25: 3b9aca00 x24: ff800858530c
[3.576522] x23: x22: fdfb
[3.581827] x21: 000a x20: ffccb89aafc8
[3.587132] x19: fdfb x18: 5a5c77082016
[3.592438] x17: 0400 x16: 0001
[3.597743] x15: 0009 x14: ff93e271c908
[3.603048] x13: 0b22 x12: 0008
[3.608353] x11: 01d063de x10: 0008
[3.613659] x9 : ffed x8 :
[3.618964] x7 : 736d6c2dff7224fe x6 :
Re: [PATCH v10 11/12] soc: mediatek: cmdq: add cmdq_dev_get_client_reg function
Hi, Bibby:
On Mon, 2019-07-01 at 15:48 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the cmdq_client_reg structure.
>
Reviewed-by: CK Hu
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 28 ++
> include/linux/soc/mediatek/mtk-cmdq.h | 21 +++
> 2 files changed, 49 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 70ad4d806fac..ad52ac3ccfbb 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -27,6 +27,34 @@ struct cmdq_instruction {
> u8 op;
> };
>
> +int cmdq_dev_get_client_reg(struct device *dev,
> + struct cmdq_client_reg *client_reg, int idx)
> +{
> + struct of_phandle_args spec;
> + int err;
> +
> + if (!client_reg)
> + return -ENOENT;
> +
> + err = of_parse_phandle_with_args(dev->of_node,
> "mediatek,gce-client-reg",
> + "#subsys-cells", idx, );
> + if (err < 0) {
> + dev_err(dev,
> + "error %d can't parse gce-client-reg property (%d)",
> + err, idx);
> +
> + return err;
> + }
> +
> + client_reg->subsys = spec.args[0];
> + client_reg->offset = spec.args[1];
> + client_reg->size = spec.args[2];
> + of_node_put(spec.np);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(cmdq_dev_get_client_reg);
> +
> static void cmdq_client_timeout(struct timer_list *t)
> {
> struct cmdq_client *client = from_timer(client, t, timer);
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index a345870a6d10..be402c4c740e 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -15,6 +15,12 @@
>
> struct cmdq_pkt;
>
> +struct cmdq_client_reg {
> + u8 subsys;
> + u16 offset;
> + u16 size;
> +};
> +
> struct cmdq_client {
> spinlock_t lock;
> u32 pkt_cnt;
> @@ -142,4 +148,19 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt,
> cmdq_async_flush_cb cb,
> */
> int cmdq_pkt_flush(struct cmdq_pkt *pkt);
>
> +/**
> + * cmdq_dev_get_client_reg() - parse cmdq client reg from the device
> + * node of CMDQ client
> + * @dev: device of CMDQ mailbox clienti
> + * @client_reg: CMDQ client reg pointer
> + * @idx: the index of desired reg
> + *
> + * Return: 0 for success; else the error code is returned
> + *
> + * Help CMDQ client pasing the cmdq client reg
> + * from the device node of CMDQ client.
> + */
> +int cmdq_dev_get_client_reg(struct device *dev,
> + struct cmdq_client_reg *client_reg, int idx);
> +
> #endif /* __MTK_CMDQ_H__ */
Re: [PATCH v4 4/4] drm/mtk: add panel orientation property
Hi, Derek:
On Fri, 2019-06-21 at 20:41 -0700, Derek Basehore wrote:
> This inits the panel orientation property for the mediatek dsi driver
> if the panel orientation (connector.display_info.panel_orientation) is
> not DRM_MODE_PANEL_ORIENTATION_UNKNOWN.
>
Reviewed-by: CK Hu
> Signed-off-by: Derek Basehore
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 4a0b9150a7bb..08ffdc7526dd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -782,10 +782,18 @@ static int mtk_dsi_create_connector(struct drm_device
> *drm, struct mtk_dsi *dsi)
> DRM_ERROR("Failed to attach panel to drm\n");
> goto err_connector_cleanup;
> }
> +
> + ret = drm_connector_init_panel_orientation_property(>conn);
> + if (ret) {
> + DRM_ERROR("Failed to init panel orientation\n");
> + goto err_panel_detach;
> + }
> }
>
> return 0;
>
> +err_panel_detach:
> + drm_panel_detach(dsi->panel);
> err_connector_cleanup:
> drm_connector_cleanup(>conn);
> return ret;
Re: [v5 6/7] drm/mediatek: change the dsi phytiming calculate method
Hi, Jitao:
On Thu, 2019-06-27 at 16:01 +0800, Jitao Shi wrote:
> Change the method of frame rate calc which can get more accurate
> frame rate.
>
> data rate = pixel_clock * bit_per_pixel / lanes
> Adjust hfp_wc to adapt the additional phy_data
>
> if MIPI_DSI_MODE_VIDEO_BURST
> hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
> else
> hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;
>
> Note:
> //(2: 1 for sync, 1 for phy idle)
> data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;
>
> bpp: bit per pixel
>
> Signed-off-by: Jitao Shi
> Tested-by: Ryan Case
> Reviewed-by: CK Hu
This version is different than previous version, so you should remove
Reviewed-by tag. For this version, I still give you a
Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 117 -
> 1 file changed, 80 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 1621e8cdacc2..cefdcb1509cb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -144,12 +144,6 @@
> #define DATA_0 (0xff << 16)
> #define DATA_1 (0xff << 24)
>
> -#define T_LPX5
> -#define T_HS_PREP6
> -#define T_HS_TRAIL 8
> -#define T_HS_EXIT7
> -#define T_HS_ZERO10
> -
> #define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))
>
> #define MTK_DSI_HOST_IS_READ(type) \
> @@ -158,6 +152,25 @@
> (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
> (type == MIPI_DSI_DCS_READ))
>
> +struct mtk_phy_timing {
> + u32 lpx;
> + u32 da_hs_prepare;
> + u32 da_hs_zero;
> + u32 da_hs_trail;
> +
> + u32 ta_go;
> + u32 ta_sure;
> + u32 ta_get;
> + u32 da_hs_exit;
> +
> + u32 clk_hs_zero;
> + u32 clk_hs_trail;
> +
> + u32 clk_hs_prepare;
> + u32 clk_hs_post;
> + u32 clk_hs_exit;
> +};
> +
> struct phy;
>
> struct mtk_dsi_driver_data {
> @@ -188,6 +201,7 @@ struct mtk_dsi {
> enum mipi_dsi_pixel_format format;
> unsigned int lanes;
> struct videomode vm;
> + struct mtk_phy_timing phy_timing;
> int refcount;
> bool enabled;
> u32 irq_data;
> @@ -221,17 +235,36 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
> {
> u32 timcon0, timcon1, timcon2, timcon3;
> u32 ui, cycle_time;
> + struct mtk_phy_timing *timing = >phy_timing;
> +
> + ui = 10 / dsi->data_rate;
> + cycle_time = div_u64(80ULL, dsi->data_rate);
> +
> + timing->lpx = NS_TO_CYCLE(60, cycle_time);
> + timing->da_hs_prepare = NS_TO_CYCLE(40 + 5 * ui, cycle_time);
> + timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
> + timing->da_hs_trail = NS_TO_CYCLE(80 + 4 * ui, cycle_time);
>
> - ui = 1000 / dsi->data_rate + 0x01;
> - cycle_time = 8000 / dsi->data_rate + 0x01;
> + timing->ta_go = 4 * timing->lpx;
> + timing->ta_sure = 3 * timing->lpx / 2;
> + timing->ta_get = 5 * timing->lpx;
> + timing->da_hs_exit = 2 * timing->lpx;
>
> - timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
> - timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
> - T_HS_EXIT << 24;
> - timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
> - (NS_TO_CYCLE(0x150, cycle_time) << 16);
> - timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
> - NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
> + timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
> + timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
> +
> + timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
> + timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
> + timing->clk_hs_exit = 2 * timing->lpx;
> +
> + timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
> + timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
> + timcon1 = timing->ta_go | timing->ta_sure << 8 |
> + timing->ta_get << 16 | timing->da_hs_exit << 24;
> + timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
> + timing->clk_hs_trail << 24;
> + timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
> + tim
Re: [v5 4/7] drm/mediatek: add frame size control
Hi, Jitao:
On Thu, 2019-06-27 at 16:01 +0800, Jitao Shi wrote:
> Our new DSI chip has frame size control.
> So add the driver data to control for different chips.
>
> Signed-off-by: Jitao Shi
> Reviewed-by: CK Hu
This version is different than previous version, so you should remove
the reviewed-by tag. For this version, I still give you a
Reviewed-by: CK Hu
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 6b6550926db6..45e331055842 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -78,6 +78,7 @@
> #define DSI_VBP_NL 0x24
> #define DSI_VFP_NL 0x28
> #define DSI_VACT_NL 0x2C
> +#define DSI_SIZE_CON 0x38
> #define DSI_HSA_WC 0x50
> #define DSI_HBP_WC 0x54
> #define DSI_HFP_WC 0x58
> @@ -162,6 +163,7 @@ struct phy;
> struct mtk_dsi_driver_data {
> const u32 reg_cmdq_off;
> bool has_shadow_ctl;
> + bool has_size_ctl;
> };
>
> struct mtk_dsi {
> @@ -430,6 +432,10 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi
> *dsi)
> writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
> writel(vm->vactive, dsi->regs + DSI_VACT_NL);
>
> + if (dsi->driver_data->has_size_ctl)
> + writel(vm->vactive << 16 | vm->hactive,
> +dsi->regs + DSI_SIZE_CON);
> +
> horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
>
> if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
Re: [PATCH v9 11/12] soc: mediatek: cmdq: add cmdq_dev_get_client_reg function
Hi, Bibby:
On Thu, 2019-06-27 at 14:19 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the cmdq_client_reg structure.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 24
> include/linux/soc/mediatek/mtk-cmdq.h | 21 +
> 2 files changed, 45 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 70ad4d806fac..ceb1b569891f 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -27,6 +27,30 @@ struct cmdq_instruction {
> u8 op;
> };
>
> +int cmdq_dev_get_client_reg(struct device *dev,
> + struct cmdq_client_reg *client_reg, int idx)
> +{
> + struct of_phandle_args spec;
> +
> + if (!client_reg)
> + return -ENOENT;
> +
> + if (of_parse_phandle_with_args(dev->of_node, "mediatek,gce-client-reg",
> +"#subsys-cells", idx, )) {
> + dev_err(dev, "can't parse gce-client-reg property (%d)", idx);
> +
> + return -ENOENT;
Maybe my expression is not so clear. of_parse_phandle_with_args() may
return -ENOENT, but it also may return -EINVAL. My point is why do you
change the return value of of_parse_phandle_with_args(). What the error
you get from of_parse_phandle_with_args(), you could also return it to
the caller of cmdq_dev_get_client_reg().
Regards,
CK
> + }
> +
> + client_reg->subsys = spec.args[0];
> + client_reg->offset = spec.args[1];
> + client_reg->size = spec.args[2];
> + of_node_put(spec.np);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(cmdq_dev_get_client_reg);
> +
> static void cmdq_client_timeout(struct timer_list *t)
> {
> struct cmdq_client *client = from_timer(client, t, timer);
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index a345870a6d10..be402c4c740e 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -15,6 +15,12 @@
>
> struct cmdq_pkt;
>
> +struct cmdq_client_reg {
> + u8 subsys;
> + u16 offset;
> + u16 size;
> +};
> +
> struct cmdq_client {
> spinlock_t lock;
> u32 pkt_cnt;
> @@ -142,4 +148,19 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt,
> cmdq_async_flush_cb cb,
> */
> int cmdq_pkt_flush(struct cmdq_pkt *pkt);
>
> +/**
> + * cmdq_dev_get_client_reg() - parse cmdq client reg from the device
> + * node of CMDQ client
> + * @dev: device of CMDQ mailbox clienti
> + * @client_reg: CMDQ client reg pointer
> + * @idx: the index of desired reg
> + *
> + * Return: 0 for success; else the error code is returned
> + *
> + * Help CMDQ client pasing the cmdq client reg
> + * from the device node of CMDQ client.
> + */
> +int cmdq_dev_get_client_reg(struct device *dev,
> + struct cmdq_client_reg *client_reg, int idx);
> +
> #endif /* __MTK_CMDQ_H__ */
Re: [PATCH v3, 27/27] drm/mediatek: add support for mediatek SOC MT8183
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:43 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add support for mediatek SOC MT8183
> 1.ovl_2l share driver with ovl
> 2.rdma1 share drive with rdma0, but fifo size is different
> 3.add mt8183 mutex private data, and mmsys private data
> 4.add mt8183 main and external path module for crtc create
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c| 12
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 107
>
> drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47
> 6 files changed, 186 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 63072d1..efd41aa 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -382,11 +382,29 @@ static int mtk_disp_ovl_remove(struct platform_device
> *pdev)
> .fmt_rgb565_is_0 = true,
> };
>
> +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 4,
> + .fmt_rgb565_is_0 = true,
> +};
> +
> +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 2,
> + .fmt_rgb565_is_0 = true,
> +};
> +
> static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-ovl",
> .data = _ovl_driver_data},
> { .compatible = "mediatek,mt8173-disp-ovl",
> .data = _ovl_driver_data},
> + { .compatible = "mediatek,mt8183-disp-ovl",
> + .data = _ovl_driver_data},
> + { .compatible = "mediatek,mt8183-disp-ovl-2l",
> + .data = _ovl_2l_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index b0a5cff..5d62588 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -336,11 +336,23 @@ static int mtk_disp_rdma_remove(struct platform_device
> *pdev)
> .fifo_size = SZ_8K,
> };
>
> +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
> + .fifo_size = 5 * SZ_1K,
> +};
> +
> +static const struct mtk_disp_rdma_data mt8183_rdma1_driver_data = {
> + .fifo_size = SZ_2K,
> +};
> +
> static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = _rdma_driver_data},
> { .compatible = "mediatek,mt8173-disp-rdma",
> .data = _rdma_driver_data},
> + { .compatible = "mediatek,mt8183-disp-rdma",
> + .data = _rdma_driver_data},
> + { .compatible = "mediatek,mt8183-disp-rdma1",
"mediatek,mt8183-disp-rdma1" does not exist in binding document.
> + .data = _rdma1_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 28274d2..eaf2351 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -41,8 +41,36 @@
> #define DISP_REG_CONFIG_DSI_SEL 0x050
> #define DISP_REG_CONFIG_DPI_SEL 0x064
>
> +#define MT8183_DISP_OVL0_MOUT_EN 0xF00
> +#define OVL0_MOUT_EN_DISP_PATH0 BIT(0)
> +#define OVL0_MOUT_EN_OVL0_2L BIT(4)
> +#define MT8183_DISP_OVL0_2L_MOUT_EN 0xF04
> +#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
> +#define MT8183_DISP_OVL1_2L_MOUT_EN 0xF08
> +#define OVL1_2L_MOUT_EN_RDMA1BIT(4)
> +#define MT8183_DISP_DITHER0_MOUT_EN 0xF0C
> +#define DITHER0_MOUT_IN_DSI0 BIT(0)
> +#define MT8183_DISP_PATH0_SEL_IN 0xF24
> +#define DISP_PATH0_SEL_IN_OVL0 0x0
> +#define DISP_PATH0_SEL_IN_OVL0_2L0x1
> +#define MT8183_DISP_DSI0_SEL_IN 0xF2C
> +#define DSI0_SEL_IN_DITHER 0x0
> +#define DSI0_SEL_IN_RDMA00x1
> +#define MT8183_DSI0_SEL_IN_RDMA1 0x3
> +#define MT8183_DISP_DPI0_SEL_IN 0xF30
> +#define MT8183_DPI0_SEL_IN_RDMA0 0x1
> +#define MT8183_DPI0_SEL_IN_RDMA1 0x2
> +#define MT8183_DISP_RDMA0_SOUT_SEL_IN0xF50
> +#define MT8183_RDMA0_SOUT_DSI0 0x0
> +#define MT8183_RDMA0_SOUT_COLOR0 0x1
> +#define
Re: [PATCH v3, 26/27] drm/mediatek: add clock property check before get it
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:43 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add clock property check before get it
In the binding document [1], clock is required property. In this patch,
you change it to optional property. I think you should change the
binding document and describe _WHY_ do you do this.
[1]
https://www.kernel.org/doc/Documentation/devicetree/bindings/display/mediatek/mediatek%2Cdisp.txt
Regards,
CK
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 9986c61..28274d2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -689,10 +689,12 @@ static int mtk_ddp_probe(struct platform_device *pdev)
> for (i = 0; i < 10; i++)
> ddp->mutex[i].id = i;
>
> - ddp->clk = devm_clk_get(dev, NULL);
> - if (IS_ERR(ddp->clk)) {
> - dev_err(dev, "Failed to get clock\n");
> - return PTR_ERR(ddp->clk);
> + if (of_find_property(dev->of_node, "clocks", )) {
> + ddp->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(ddp->clk)) {
> + dev_err(dev, "Failed to get clock\n");
> + return PTR_ERR(ddp->clk);
> + }
> }
>
> regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Re: [PATCH v3, 19/27] drm/mediatek: add function to background color input select for ovl/ovl_2l direct link
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add function to background color input select for ovl/ovl_2l
> direct link
> for ovl/ovl_2l direct link usecase, we need set background color
> input select for these hardware.
> this is preparation patch for ovl/ovl_2l usecase
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 158c1e5..aa1e183 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -92,6 +92,9 @@ struct mtk_ddp_comp_funcs {
>struct mtk_plane_state *state);
> void (*gamma_set)(struct mtk_ddp_comp *comp,
> struct drm_crtc_state *state);
> + void (*bgclr_in_on)(struct mtk_ddp_comp *comp,
> + enum mtk_ddp_comp_id prev);
prev is useless, so remove it.
Regards,
CK
> + void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
> };
>
> struct mtk_ddp_comp {
> @@ -173,6 +176,19 @@ static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp
> *comp,
> comp->funcs->gamma_set(comp, state);
> }
>
> +static inline void mtk_ddp_comp_bgclr_in_on(struct mtk_ddp_comp *comp,
> + enum mtk_ddp_comp_id prev)
> +{
> + if (comp->funcs && comp->funcs->bgclr_in_on)
> + comp->funcs->bgclr_in_on(comp, prev);
> +}
> +
> +static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
> +{
> + if (comp->funcs && comp->funcs->bgclr_in_off)
> + comp->funcs->bgclr_in_off(comp);
> +}
> +
> int mtk_ddp_comp_get_id(struct device_node *node,
> enum mtk_ddp_comp_type comp_type);
> int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
Re: [PATCH v8 11/12] soc: mediatek: cmdq: add cmdq_dev_get_client_reg function
Hi, Bibby:
On Wed, 2019-06-12 at 16:53 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the cmdq_client_reg structure.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 24
> include/linux/soc/mediatek/mtk-cmdq.h | 20
> 2 files changed, 44 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 70ad4d806fac..fac4d33fd520 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -27,6 +27,30 @@ struct cmdq_instruction {
> u8 op;
> };
>
> +int cmdq_dev_get_client_reg(struct device *dev,
> + struct cmdq_client_reg *client_reg, int idx)
> +{
> + struct of_phandle_args spec;
> +
> + if (!client_reg)
> + return -EINVAL;
> +
> + if (of_parse_phandle_with_args(dev->of_node, "mediatek,gce-client-reg",
> +"#subsys-cells", idx, )) {
> + dev_err(dev, "can't parse gce-client-reg property (%d)", idx);
> +
> + return -EINVAL;
of_parse_phandle_with_args() may return -ENOENT, why do you change it to
-EINVAL?
Regards,
CK
> + }
> +
> + client_reg->subsys = spec.args[0];
> + client_reg->offset = spec.args[1];
> + client_reg->size = spec.args[2];
> + of_node_put(spec.np);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(cmdq_dev_get_client_reg);
> +
> static void cmdq_client_timeout(struct timer_list *t)
> {
> struct cmdq_client *client = from_timer(client, t, timer);
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index a345870a6d10..2e2a2274c231 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -15,6 +15,12 @@
>
> struct cmdq_pkt;
>
> +struct cmdq_client_reg {
> + u8 subsys;
> + u16 offset;
> + u16 size;
> +};
> +
> struct cmdq_client {
> spinlock_t lock;
> u32 pkt_cnt;
> @@ -142,4 +148,18 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt,
> cmdq_async_flush_cb cb,
> */
> int cmdq_pkt_flush(struct cmdq_pkt *pkt);
>
> +/**
> + * cmdq_dev_get_client_reg() - parse cmdq client reg from the device node of
> CMDQ client
> + * @dev: device of CMDQ mailbox clienti
> + * @client_reg: CMDQ client reg pointer
> + * @idx: the index of desired reg
> + *
> + * Return: 0 for success; else the error code is returned
> + *
> + * Help CMDQ client pasing the cmdq client reg
> + * from the device node of CMDQ client.
> + */
> +int cmdq_dev_get_client_reg(struct device *dev,
> + struct cmdq_client_reg *client_reg, int idx);
> +
> #endif /* __MTK_CMDQ_H__ */
Re: [PATCH v4 01/14] dt-bindings: Add binding for MT2712 MIPI-CSI2
Hi, Stu:
"mediatek,mt2712-mipicsi" and "mediatek,mt2712-mipicsi-common" have many
common part with "mediatek,mt8183-seninf", and I've a discussion in [1],
so I would like these two to be merged together.
[1] https://patchwork.kernel.org/patch/10979131/
Regards,
CK
On Tue, 2019-06-04 at 18:11 +0800, Stu Hsieh wrote:
> Add MIPI-CSI2 dt-binding for Mediatek MT2712 SoC
>
> Signed-off-by: Stu Hsieh
> ---
> .../bindings/media/mediatek-mipicsi.txt | 58 +++
> 1 file changed, 58 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
> b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
> new file mode 100644
> index ..e30b6a468129
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
> @@ -0,0 +1,58 @@
> +* Mediatek MIPI-CSI2 receiver
> +
> +Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in
> Mediatek SoCs
> +
> +Required properties:
> +- compatible: should be "mediatek,mt2712-mipicsi"
> +- reg : physical base address of the mipicsi receiver registers and length of
> + memory mapped region.
> +- power-domains: a phandle to the power domain, see
> + Documentation/devicetree/bindings/power/power_domain.txt for details.
> +- mediatek,larb: must contain the local arbiters in the current Socs, see
> + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
> + for details.
> +- iommus: should point to the respective IOMMU block with master port as
> + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
> + for details.
> +- mediatek,seninf_mux_camsv: seninf_mux_camsv the data go through of the
> mipicsi port
> + any mipicsi port can contain max four seninf_mux_camsv
> + The Total seninf_mux_camsv is six for mt2712
> +- mediatek,mipicsiid: the id of the mipicsi port, there are two port for
> mt2712
> +- mediatek,mipicsi: the common component of the two mipicsi port
> +- mediatek,mipicsi_max_vc: the number of virtual channel which subdev used
> +- mediatek,serdes_link_reg: the register of subdev to get the link status
> +
> +Example:
> + mipicsi0: mipicsi@10217000 {
> + compatible = "mediatek,mt2712-mipicsi";
> + mediatek,mipicsi = <>;
> + iommus = < M4U_PORT_CAM_DMA0>,
> + < M4U_PORT_CAM_DMA1>;
> + mediatek,larb = <>;
> + power-domains = < MT2712_POWER_DOMAIN_ISP>;
> +
> + mediatek,seninf_mux_camsv = <_mux_camsv0
> + _mux_camsv1
> + _mux_camsv2
> + _mux_camsv3>;
> + reg = <0 0x10217000 0 0x60>,
> + <0 0x15002100 0 0x4>,
> + <0 0x15002300 0 0x100>;
> + mediatek,mipicsiid = <0>;
> + mediatek,mipicsi_max_vc = <4>;
> + mediatek,serdes_link_reg = <0x49>;
> + };
> +
> + mipicsi1: mipicsi@10218000 {
> + compatible = "mediatek,mt2712-mipicsi";
> + mediatek,mipicsi = <>;
> + iommus = < M4U_PORT_CAM_DMA2>;
> + mediatek,larb = <>;
> + power-domains = < MT2712_POWER_DOMAIN_ISP>;
> + mediatek,seninf_mux_camsv = <_mux_camsv4
> + _mux_camsv5>;
> + reg = <0 0x10218000 0 0x60>,
> + <0 0x15002500 0 0x4>,
> + <0 0x15002700 0 0x100>;
> + mediatek,mipicsiid = <1>;
> + };
Re: [v4 3/7] drm/mediatek: add dsi reg commit disable control
Hi, Jitao:
On Sat, 2019-06-01 at 17:26 +0800, Jitao Shi wrote:
> New DSI IP has shadow register and working reg. The register
> values are writen to shadow register. And then trigger with
> commit reg, the register values will be moved working register.
>
> This fucntion is defualt on. But this driver doesn't use this
> function. So add the disable control.
Reviewed-by: CK Hu
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index a48db056df6c..eea47294079e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -131,6 +131,10 @@
> #define VM_CMD_ENBIT(0)
> #define TS_VFP_ENBIT(5)
>
> +#define DSI_SHADOW_DEBUG 0x190U
> +#define FORCE_COMMIT BIT(0)
> +#define BYPASS_SHADOWBIT(1)
> +
> #define CONFIG (0xff << 0)
> #define SHORT_PACKET 0
> #define LONG_PACKET 2
> @@ -157,6 +161,7 @@ struct phy;
>
> struct mtk_dsi_driver_data {
> const u32 reg_cmdq_off;
> + bool has_shadow_ctl;
> };
>
> struct mtk_dsi {
> @@ -594,6 +599,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> }
>
> mtk_dsi_enable(dsi);
> +
> + if (dsi->driver_data->has_shadow_ctl)
> + writel(FORCE_COMMIT | BYPASS_SHADOW,
> +dsi->regs + DSI_SHADOW_DEBUG);
> +
> mtk_dsi_reset_engine(dsi);
> mtk_dsi_phy_timconfig(dsi);
>
Re: [v3 7/7] drm: mediatek: adjust dsi and mipi_tx probe sequence
Hi, Jitao:
On Sun, 2019-05-19 at 17:25 +0800, Jitao Shi wrote:
> mtk_mipi_tx is the phy of mtk_dsi.
> mtk_dsi get the phy(mtk_mipi_tx) in probe().
>
> So, mtk_mipi_tx init should be ahead of mtk_dsi. Or mtk_dsi will
> defer to wait mtk_mipi_tx probe done.
Reviewed-by: CK Hu
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index cf59ea9bccfd..583d533d9574 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -633,8 +633,8 @@ static struct platform_driver * const mtk_drm_drivers[] =
> {
> _disp_rdma_driver,
> _dpi_driver,
> _drm_platform_driver,
> - _dsi_driver,
> _mipi_tx_driver,
> + _dsi_driver,
> };
>
> static int __init mtk_drm_init(void)
Re: [PATCH v3] gpu/drm: mediatek: call mtk_dsi_stop() after mtk_drm_crtc_atomic_disable()
Hi, Hsin-Yi:
On Tue, 2019-05-28 at 15:39 +0800, Hsin-Yi Wang wrote:
> mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(), which
> needs
> ovl irq for drm_crtc_wait_one_vblank(), since after mtk_dsi_stop() is called,
> ovl irq will be disabled. If drm_crtc_wait_one_vblank() is called after last
> irq, it will timeout with this message: "vblank wait timed out on crtc 0".
> This
> happens sometimes when turning off the screen.
>
> In drm_atomic_helper.c#disable_outputs(),
> the calling sequence when turning off the screen is:
>
> 1. mtk_dsi_encoder_disable()
> --> mtk_output_dsi_disable()
>--> mtk_dsi_stop(); // sometimes make vblank timeout in atomic_disable
>--> mtk_dsi_poweroff();
> 2. mtk_drm_crtc_atomic_disable()
> --> drm_crtc_wait_one_vblank();
> ...
>--> mtk_dsi_ddp_stop()
> --> mtk_dsi_poweroff();
>
> mtk_dsi_poweroff() has reference count design, change to make mtk_dsi_stop()
> called in mtk_dsi_poweroff() when refcount is 0.
>
> Fixes: 0707632b5bac ("drm/mediatek: update DSI sub driver flow for sending
> commands to panel")
> Signed-off-by: Hsin-Yi Wang
> ---
> change log v2->v3:
> * remove unnecessary codes in unbind
> * based on discussion in v2, if we move mtk_dsi_start() to mtk_dsi_poweron(),
> in order to make mtk_dsi_start() and mtk_dsi_stop() symmetric, will results in
> no irq for panel with bridge. So we keep mtk_dsi_start() in original place.
I think we've already discussed in [1]. I need a reason to understand
this is hardware behavior or software bug. If this is a software bug, we
need to fix the bug and code could be symmetric.
[1]
http://lists.infradead.org/pipermail/linux-mediatek/2019-March/018423.html
Regards,
CK
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index b00eb2d2e086..b7f829ecd3ad 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -630,6 +630,8 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
> if (--dsi->refcount != 0)
> return;
>
> + mtk_dsi_stop(dsi);
> +
> if (!mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500)) {
> if (dsi->panel) {
> if (drm_panel_unprepare(dsi->panel)) {
> @@ -696,7 +698,6 @@ static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
> }
> }
>
> - mtk_dsi_stop(dsi);
> mtk_dsi_poweroff(dsi);
>
> dsi->enabled = false;
Re: [PATCH v7 11/12] soc: mediatek: cmdq: add cmdq_dev_get_client_reg function
On Tue, 2019-05-21 at 09:11 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the cmdq_client_reg structure.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 25 +
> include/linux/soc/mediatek/mtk-cmdq.h | 18 ++
> 2 files changed, 43 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 70ad4d806fac..815845bb5982 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -27,6 +27,31 @@ struct cmdq_instruction {
> u8 op;
> };
>
> +struct cmdq_client_reg *cmdq_dev_get_client_reg(struct device *dev, int idx)
> +{
> + struct cmdq_client_reg *client_reg;
> + struct of_phandle_args spec;
> +
> + client_reg = devm_kzalloc(dev, sizeof(*client_reg), GFP_KERNEL);
> + if (!client_reg)
> + return NULL;
> +
> + if (of_parse_phandle_with_args(dev->of_node, "mediatek,gce-client-reg",
> +"#subsys-cells", idx, )) {
> + dev_err(dev, "can't parse gce-client-reg property (%d)", idx);
I think you should call devm_kfree(client_reg) here because this
function may not be called in client driver's probe function. But in
another view point, I would like you to move the memory allocation out
of this function. When client call cmdq_dev_get_client_reg() to get a
pointer, it's easy that client does not free it because you does not
provide free API, Some client may embed struct cmdq_client_reg with its
client structure together,
struct client {
struct cmdq_client_reg client_reg;
};
Because each client may have different memory allocation strategy, so I
would like you to move memory allocation out of this function to let
client driver have the flexibility.
Regards,
CK
> +
> + return NULL;
> + }
> +
> + client_reg->subsys = spec.args[0];
> + client_reg->offset = spec.args[1];
> + client_reg->size = spec.args[2];
> + of_node_put(spec.np);
> +
> + return client_reg;
> +}
> +EXPORT_SYMBOL(cmdq_dev_get_client_reg);
> +
> static void cmdq_client_timeout(struct timer_list *t)
> {
> struct cmdq_client *client = from_timer(client, t, timer);
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index a345870a6d10..d0dea3780f7a 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -15,6 +15,12 @@
>
> struct cmdq_pkt;
>
> +struct cmdq_client_reg {
> + u8 subsys;
> + u16 offset;
> + u16 size;
> +};
> +
> struct cmdq_client {
> spinlock_t lock;
> u32 pkt_cnt;
> @@ -142,4 +148,16 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt,
> cmdq_async_flush_cb cb,
> */
> int cmdq_pkt_flush(struct cmdq_pkt *pkt);
>
> +/**
> + * cmdq_dev_get_client_reg() - parse cmdq client reg from the device node of
> CMDQ client
> + * @dev: device of CMDQ mailbox client
> + * @idx: the index of desired reg
> + *
> + * Return: CMDQ client reg pointer
> + *
> + * Help CMDQ client pasing the cmdq client reg
> + * from the device node of CMDQ client.
> + */
> +struct cmdq_client_reg *cmdq_dev_get_client_reg(struct device *dev, int
> idx);
> +
> #endif /* __MTK_CMDQ_H__ */
Re: [PATCH v7 09/12] soc: mediatek: cmdq: define the instruction struct
Hi, Bibby:
On Tue, 2019-05-21 at 09:11 +0800, Bibby Hsieh wrote:
> Define an instruction structure for gce driver to append command.
> This structure can make the client's code more readability.
Reviewed-by: CK Hu
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 103 +++
> include/linux/mailbox/mtk-cmdq-mailbox.h | 2 +
> 2 files changed, 72 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 7aa0517ff2f3..0886c4967ca4 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -9,12 +9,24 @@
> #include
> #include
>
> -#define CMDQ_ARG_A_WRITE_MASK0x
> #define CMDQ_WRITE_ENABLE_MASK BIT(0)
> #define CMDQ_EOC_IRQ_EN BIT(0)
> #define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \
> << 32 | CMDQ_EOC_IRQ_EN)
>
> +struct cmdq_instruction {
> + union {
> + u32 value;
> + u32 mask;
> + };
> + union {
> + u16 offset;
> + u16 event;
> + };
> + u8 subsys;
> + u8 op;
> +};
> +
> static void cmdq_client_timeout(struct timer_list *t)
> {
> struct cmdq_client *client = from_timer(client, t, timer);
> @@ -110,10 +122,8 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt)
> }
> EXPORT_SYMBOL(cmdq_pkt_destroy);
>
> -static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
> -u32 arg_a, u32 arg_b)
> +static struct cmdq_instruction *cmdq_pkt_append_command(struct cmdq_pkt *pkt)
> {
> - u64 *cmd_ptr;
>
> if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) {
> /*
> @@ -127,81 +137,108 @@ static int cmdq_pkt_append_command(struct cmdq_pkt
> *pkt, enum cmdq_code code,
> pkt->cmd_buf_size += CMDQ_INST_SIZE;
> WARN_ONCE(1, "%s: buffer size %u is too small !\n",
> __func__, (u32)pkt->buf_size);
> - return -ENOMEM;
> + return NULL;
> }
> - cmd_ptr = pkt->va_base + pkt->cmd_buf_size;
> - (*cmd_ptr) = (u64)((code << CMDQ_OP_CODE_SHIFT) | arg_a) << 32 | arg_b;
> +
> pkt->cmd_buf_size += CMDQ_INST_SIZE;
>
> - return 0;
> + return pkt->va_base + pkt->cmd_buf_size - CMDQ_INST_SIZE;
> }
>
> int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
> {
> - u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) |
> - (subsys << CMDQ_SUBSYS_SHIFT);
> + struct cmdq_instruction *inst;
> +
> + inst = cmdq_pkt_append_command(pkt);
> + if (!inst)
> + return -ENOMEM;
> +
> + inst->op = CMDQ_CODE_WRITE;
> + inst->value = value;
> + inst->offset = offset;
> + inst->subsys = subsys;
>
> - return cmdq_pkt_append_command(pkt, CMDQ_CODE_WRITE, arg_a, value);
> + return 0;
> }
> EXPORT_SYMBOL(cmdq_pkt_write);
>
> int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
> u16 offset, u32 value, u32 mask)
> {
> + struct cmdq_instruction *inst;
> u32 offset_mask = offset;
> - int err = 0;
>
> if (mask != 0x) {
> - err = cmdq_pkt_append_command(pkt, CMDQ_CODE_MASK, 0, ~mask);
> + inst = cmdq_pkt_append_command(pkt);
> + if (!inst)
> + return -ENOMEM;
> +
> + inst->op = CMDQ_CODE_MASK;
> + inst->mask = ~mask;
> offset_mask |= CMDQ_WRITE_ENABLE_MASK;
> }
> - err |= cmdq_pkt_write(pkt, value, subsys, offset_mask);
>
> - return err;
> + return cmdq_pkt_write(pkt, subsys, offset_mask, value);
> }
> EXPORT_SYMBOL(cmdq_pkt_write_mask);
>
> int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
> {
> - u32 arg_b;
> + struct cmdq_instruction *inst;
>
> if (event >= CMDQ_MAX_EVENT)
> return -EINVAL;
>
> - /*
> - * WFE arg_b
> - * bit 0-11: wait value
> - * bit 15: 1 - wait, 0 - no wait
> - * bit 16-27: update value
> - * bit 31: 1 - update, 0 - no update
> - */
> - arg_b = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
> + inst = cmdq_pkt_append_command(pkt);
> + if (!inst)
> + return -ENOMEM;
> +
> + inst->op = CMDQ_CODE_WFE;
> + inst->va
Re: [PATCH v7 08/12] soc: mediatek: cmdq: change the type of input parameter
Hi, Bibby:
On Tue, 2019-05-21 at 09:11 +0800, Bibby Hsieh wrote:
> According to the cmdq hardware design, the subsys is u8,
> the offset is u16 and the event id is u16.
> This patch changes the type of subsys, offset and event id
> to the correct type.
Reviewed-by: CK Hu
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 10 +-
> include/linux/soc/mediatek/mtk-cmdq.h | 10 +-
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 082b8978651e..7aa0517ff2f3 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -136,7 +136,7 @@ static int cmdq_pkt_append_command(struct cmdq_pkt *pkt,
> enum cmdq_code code,
> return 0;
> }
>
> -int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 subsys, u32 offset, u32 value)
> +int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
> {
> u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) |
> (subsys << CMDQ_SUBSYS_SHIFT);
> @@ -145,8 +145,8 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 subsys, u32
> offset, u32 value)
> }
> EXPORT_SYMBOL(cmdq_pkt_write);
>
> -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 subsys,
> - u32 offset, u32 value, u32 mask)
> +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
> + u16 offset, u32 value, u32 mask)
> {
> u32 offset_mask = offset;
> int err = 0;
> @@ -161,7 +161,7 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 subsys,
> }
> EXPORT_SYMBOL(cmdq_pkt_write_mask);
>
> -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event)
> +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
> {
> u32 arg_b;
>
> @@ -181,7 +181,7 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event)
> }
> EXPORT_SYMBOL(cmdq_pkt_wfe);
>
> -int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event)
> +int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)
> {
> if (event >= CMDQ_MAX_EVENT)
> return -EINVAL;
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index 39d813dde4b4..9618debb9ceb 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -66,7 +66,7 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt);
> *
> * Return: 0 for success; else the error code is returned
> */
> -int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 subsys, u32 offset, u32 value);
> +int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
>
> /**
> * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet
> @@ -78,8 +78,8 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 subsys, u32
> offset, u32 value);
> *
> * Return: 0 for success; else the error code is returned
> */
> -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 subsys,
> - u32 offset, u32 value, u32 mask);
> +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
> + u16 offset, u32 value, u32 mask);
>
> /**
> * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
> @@ -88,7 +88,7 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 subsys,
> *
> * Return: 0 for success; else the error code is returned
> */
> -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event);
> +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
>
> /**
> * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
> @@ -97,7 +97,7 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event);
> *
> * Return: 0 for success; else the error code is returned
> */
> -int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event);
> +int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
>
> /**
> * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
Re: [PATCH v7 07/12] soc: mediatek: cmdq: reorder the parameter
Hi, Bibby:
On Tue, 2019-05-21 at 09:11 +0800, Bibby Hsieh wrote:
> The order of instructions gce knowed is [subsys offset value]
> so reorder the parameter of cmdq_pkt_write_mask
> and cmdq_pkt_write function.
>
Except the word 'knowed',
Reviewed-by: CK Hu
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 6 +++---
> include/linux/soc/mediatek/mtk-cmdq.h | 10 +-
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index ff9fef5a032b..082b8978651e 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -136,7 +136,7 @@ static int cmdq_pkt_append_command(struct cmdq_pkt *pkt,
> enum cmdq_code code,
> return 0;
> }
>
> -int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset)
> +int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 subsys, u32 offset, u32 value)
> {
> u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) |
> (subsys << CMDQ_SUBSYS_SHIFT);
> @@ -145,8 +145,8 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32
> subsys, u32 offset)
> }
> EXPORT_SYMBOL(cmdq_pkt_write);
>
> -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
> - u32 subsys, u32 offset, u32 mask)
> +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 subsys,
> + u32 offset, u32 value, u32 mask)
> {
> u32 offset_mask = offset;
> int err = 0;
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index 4e8899972db4..39d813dde4b4 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -60,26 +60,26 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt);
> /**
> * cmdq_pkt_write() - append write command to the CMDQ packet
> * @pkt: the CMDQ packet
> - * @value: the specified target register value
> * @subsys: the CMDQ sub system code
> * @offset: register offset from CMDQ sub system
> + * @value: the specified target register value
> *
> * Return: 0 for success; else the error code is returned
> */
> -int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset);
> +int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 subsys, u32 offset, u32 value);
>
> /**
> * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet
> * @pkt: the CMDQ packet
> - * @value: the specified target register value
> * @subsys: the CMDQ sub system code
> * @offset: register offset from CMDQ sub system
> + * @value: the specified target register value
> * @mask:the specified target register mask
> *
> * Return: 0 for success; else the error code is returned
> */
> -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
> - u32 subsys, u32 offset, u32 mask);
> +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 subsys,
> + u32 offset, u32 value, u32 mask);
>
> /**
> * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
Re: [v2 1/5] drm/mediatek: move mipi_dsi_host_register to probe
On Sun, 2019-05-19 at 17:36 +0800, Jitao Shi wrote:
> On Tue, 2019-05-07 at 17:52 +0800, CK Hu wrote:
> > Hi, Jitao:
> >
> > On Tue, 2019-04-16 at 14:04 +0800, Jitao Shi wrote:
> > > DSI panel driver need attach function which is inculde in
> > > mipi_dsi_host_ops.
> > >
> > > If mipi_dsi_host_register is not in probe, dsi panel will
> > > probe fail or more delay.
> >
> > I think this patch just prevent delay, not to prevent dsi panel probe
> > fail. In [1], you mention mipi_dsi_attach() is called in
> > panel_simple_dsi_probe(), but panel_simple_dsi_probe() is trigger by
> > mipi_dsi_host_register(), so the probe would success.
> >
> > [1]
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/panel/panel-simple.c?h=v5.0-rc6#n2987
> >
> >
>
> Yes, this just prevent delay.
>
> > >
> > > So move the mipi_dsi_host_register to probe from bind.
> > >
> > > Signed-off-by: Jitao Shi
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_dsi.c | 50 ++
> > > 1 file changed, 30 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > index b00eb2d2e086..6c4ac37f983d 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> > > @@ -1045,12 +1045,6 @@ static int mtk_dsi_bind(struct device *dev, struct
> > > device *master, void *data)
> > > return ret;
> > > }
> > >
> > > - ret = mipi_dsi_host_register(>host);
> > > - if (ret < 0) {
> > > - dev_err(dev, "failed to register DSI host: %d\n", ret);
> > > - goto err_ddp_comp_unregister;
> > > - }
> > > -
> > > ret = mtk_dsi_create_conn_enc(drm, dsi);
> > > if (ret) {
> > > DRM_ERROR("Encoder create failed with %d\n", ret);
> > > @@ -1060,8 +1054,6 @@ static int mtk_dsi_bind(struct device *dev, struct
> > > device *master, void *data)
> > > return 0;
> > >
> > > err_unregister:
> > > - mipi_dsi_host_unregister(>host);
> > > -err_ddp_comp_unregister:
> > > mtk_ddp_comp_unregister(drm, >ddp_comp);
> > > return ret;
> > > }
> > > @@ -1097,31 +1089,37 @@ static int mtk_dsi_probe(struct platform_device
> > > *pdev)
> > >
> > > dsi->host.ops = _dsi_ops;
> > > dsi->host.dev = dev;
> > > + dsi->dev = dev;
> >
> > Why do this?
> >
> > Regards,
> > CK
> >
>
> There are some error message require this poweron().
So this should not be in this patch. This patch is related to the timing
of mipi_dsi_host_register().
Regards,
CK
>
> > > + ret = mipi_dsi_host_register(>host);
> > > + if (ret < 0) {
> > > + dev_err(dev, "failed to register DSI host: %d\n", ret);
> > > + return ret;
> > > + }
> > >
> > > ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
> > > >panel, >bridge);
> > > if (ret)
> > > - return ret;
> > > + goto err_unregister_host;
> > >
> > > dsi->engine_clk = devm_clk_get(dev, "engine");
> > > if (IS_ERR(dsi->engine_clk)) {
> > > ret = PTR_ERR(dsi->engine_clk);
> > > dev_err(dev, "Failed to get engine clock: %d\n", ret);
> > > - return ret;
> > > + goto err_unregister_host;
> > > }
> > >
> > > dsi->digital_clk = devm_clk_get(dev, "digital");
> > > if (IS_ERR(dsi->digital_clk)) {
> > > ret = PTR_ERR(dsi->digital_clk);
> > > dev_err(dev, "Failed to get digital clock: %d\n", ret);
> > > - return ret;
> > > + goto err_unregister_host;
> > > }
> > >
> > > dsi->hs_clk = devm_clk_get(dev, "hs");
> > > if (IS_ERR(dsi->hs_clk)) {
> > > ret = PTR_ERR(dsi->hs_clk);
> > > dev_err(dev, "Failed to get hs clock: %d\n", ret);
> > > - return ret;
> > > + goto err_unregister_host;
> > > }
> > >
> > > regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >
> >
> >
>
>
Re: [PATCH v3 09/13] [media] mtk-mipicsi: add ISR for writing the data to buffer
Hi, Stu:
On Tue, 2019-05-14 at 14:13 +0800, Stu Hsieh wrote:
> This patch add ISR for writing the data to buffer
>
> When mipicsi HW complete to write the data in buffer,
> the interrupt woulb be trigger.
> So, the ISR need to clear interrupt status for next interrupt.
>
> Signed-off-by: Stu Hsieh
> ---
> .../media/platform/mtk-mipicsi/mtk_mipicsi.c | 110 ++
> 1 file changed, 110 insertions(+)
>
> diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
> b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
> index 44c01c8d566b..af5655345754 100644
> --- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
> +++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
> @@ -36,6 +36,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -93,6 +94,8 @@
> #define CAMSV_MODULE_EN 0x10
> #define CAMSV_FMT_SEL0x14
> #define CAMSV_INT_EN 0x18
> +#define CAMSV_INT_STATUS 0x1C
> +#define PASS1_DONE_STATUS10
> #define CAMSV_SW_CTL 0x20
> #define CAMSV_CLK_EN 0x30
>
> @@ -122,6 +125,8 @@ struct mtk_mipicsi_dev {
> struct platform_device *pdev;
> unsigned int camsv_num;
> struct device *larb_pdev;
> + unsigned intirq[MTK_CAMDMA_MAX_NUM];
> + bool irq_status[MTK_CAMDMA_MAX_NUM];
> void __iomem*ana;
> void __iomem*seninf_ctrl;
> void __iomem*seninf;
> @@ -132,6 +137,7 @@ struct mtk_mipicsi_dev {
> spinlock_t lock;
> spinlock_t queue_lock;
> struct mtk_mipicsi_buf cam_buf[MAX_BUFFER_NUM];
> + boolis_enable_irq[MTK_CAMDMA_MAX_NUM];
Useless, so remove it.
> bool streamon;
> unsigned int link;
> u8 link_reg_val;
> @@ -911,9 +917,96 @@ static const struct dev_pm_ops mtk_mipicsi_pm = {
> mtk_mipicsi_pm_resume, NULL)
> };
>
> +static int get_irq_channel(struct mtk_mipicsi_dev *mipicsi)
> +{
> + int ch;
> + u32 int_reg_val;
> +
> + for (ch = 0; ch < mipicsi->camsv_num; ++ch) {
> + int_reg_val = readl(mipicsi->camsv[ch] + CAMSV_INT_STATUS);
> + if ((int_reg_val & (1UL << PASS1_DONE_STATUS)) != 0UL)
> + return ch;
> + }
> +
> + return -1;
> +}
> +
> +static void mtk_mipicsi_irq_buf_process(struct mtk_mipicsi_dev *mipicsi)
> +{
> + unsigned int i = 0U;
> + struct mtk_mipicsi_buf *new_cam_buf = NULL;
> + struct mtk_mipicsi_buf *tmp = NULL;
> + unsigned int index = 0U;
> + unsigned int next = 0U;
> +
> + for (i = 0U; i < MTK_CAMDMA_MAX_NUM; ++i)
> + mipicsi->irq_status[i] = false;
> +
> + i = 0;
> +
> + /* only one buffer left */
> + if ((&(mipicsi->fb_list))->next->next == &(mipicsi->fb_list))
> + return;
> +
> + /*for each fb_lst 2 times to get the top 2 buffer.*/
> + list_for_each_entry_safe(new_cam_buf, tmp,
> + &(mipicsi->fb_list), queue) {
> + if (i == 0U) {
> + index = new_cam_buf->vb->index;
> + } else {
> + next = new_cam_buf->vb->index;
> + break;
> + }
> + ++i;
> + }
> +
> + /*
> + * fb_list has one more buffer. Free the first buffer to user
> + * and fill the second buffer to HW.
> + */
> + vb2_buffer_done(mipicsi->cam_buf[index].vb,
> + VB2_BUF_STATE_DONE);
> +
> + list_del_init(&(mipicsi->cam_buf[index].queue));
> +}
> +
> +static irqreturn_t mtk_mipicsi_isr(int irq, void *data)
> +{
> +
> + struct mtk_mipicsi_dev *mipicsi = data;
> + unsigned long flags = 0;
> + int isr_ch;
> + u8 irq_cnt = 0, i = 0;
> +
> + spin_lock_irqsave(>lock, flags);
> +
> + isr_ch = get_irq_channel(mipicsi);
I think you should pass data as camsv instance, so you need not to
search the camsv instance, and each camsv instance could pointer to the
same misicsi instance.
> + if (isr_ch < 0) {
> + spin_unlock_irqrestore(>lock, flags);
> + return IRQ_HANDLED;
> + }
> +
> + /* clear interrupt */
> + writel(1UL << PASS1_DONE_STATUS,
> + mipicsi->camsv[isr_ch] + CAMSV_INT_STATUS);
> + mipicsi->irq_status[isr_ch] = true;
> + for (i = 0U; i < MTK_CAMDMA_MAX_NUM; ++i) {
> + if (mipicsi->irq_status[i])
> + ++irq_cnt;
> + }
> +
> + if (irq_cnt == mipicsi->link)
> + mtk_mipicsi_irq_buf_process(mipicsi);
I think mtk_mipicsi_irq_buf_process() should not be processed in irq
handler. In irq handler, do as few things as possible.
Regards,
CK
> + spin_unlock_irqrestore(>lock, flags);
> +
> + return IRQ_HANDLED;
> +}
> +
> static int
Re: [PATCH v3 02/13] [media] mtk-mipicsi: add mediatek mipicsi driver for mt2712
Hi, Stu:
On Tue, 2019-05-14 at 14:13 +0800, Stu Hsieh wrote:
> This patch add mediatek mipicsi driver for mt2712,
> including probe function to get the value from device tree,
> and register to v4l2 the host device.
>
> Signed-off-by: Stu Hsieh
> ---
> drivers/media/platform/mtk-mipicsi/Makefile | 4 +
> .../media/platform/mtk-mipicsi/mtk_mipicsi.c | 587 ++
> 2 files changed, 591 insertions(+)
> create mode 100644 drivers/media/platform/mtk-mipicsi/Makefile
> create mode 100644 drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
>
> diff --git a/drivers/media/platform/mtk-mipicsi/Makefile
> b/drivers/media/platform/mtk-mipicsi/Makefile
> new file mode 100644
> index ..326a5e3808fa
> --- /dev/null
> +++ b/drivers/media/platform/mtk-mipicsi/Makefile
> @@ -0,0 +1,4 @@
> +mtk-mipicsi-y += mtk_mipicsi.o
> +
> +obj-$(CONFIG_VIDEO_MEDIATEK_MIPICSI) += mtk-mipicsi.o
> +
> diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
> b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
> new file mode 100644
> index ..4ae5b88abc5f
> --- /dev/null
> +++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
> @@ -0,0 +1,587 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 MediaTek Inc.
> + * Author: Ricky Zhang
> + * Baoyin Zhang
> + * Alan Yue
> + * Stu Hsieh
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * http://www.gnu.org/licenses/gpl-2.0.html for more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define MTK_MIPICSI_DRV_NAME "mtk-mipicsi"
> +#define MTK_PLATFORM_STR "platform:mt2712"
> +#define MIPICSI_COMMON_CLK 2
> +#define MTK_CAMDMA_MAX_NUM 4U
> +#define MIPICSI_CLK (MIPICSI_COMMON_CLK + MTK_CAMDMA_MAX_NUM)
> +
> +#define MIPI_RX_ANA00_CSI0x00
> +#define MIPI_RX_ANA04_CSI0x04
> +#define MIPI_RX_ANA08_CSI0x08
> +#define MIPI_RX_ANA0C_CSI0x0c
> +#define MIPI_RX_ANA10_CSI0x10
> +#define MIPI_RX_ANA20_CSI0x20
> +#define MIPI_RX_ANA24_CSI0x24
> +#define MIPI_RX_ANA4C_CSI0x4c
> +#define MIPI_RX_ANA50_CSI0x50
> +
> +#define SENINF_CTRL 0x00
> +
> +#define SENINF_NCSI2_CAL_24 0x24
> +#define SENINF_NCSI2_CAL_38 0x38
> +#define SENINF_NCSI2_CAL_3C 0x3C
> +#define SENINF_NCSI2_CTL 0xA0
> +#define SENINF_NCSI2_LNRD_TIMING 0xA8
> +#define SENINF_NCSI2_INT_EN 0xB0
> +#define SENINF_NCSI2_INT_STATUS 0xB4
> +#define SENINF_NCSI2_DBG_SEL 0xB8
> +#define SENINF_NCSI2_HSRX_DBG0xD8
> +#define SENINF_NCSI2_DI 0xDC
> +#define SENINF_NCSI2_DI_CTRL 0xE4
> +
> +#define SENINF_TOP_CTRL 0x00
> +#define SENINF_TOP_CMODEL_PAR0x04
> +#define SENINF_TOP_MUX 0x08
> +
> +#define SENINF_MUX_CTRL 0x00
> +
> +#define CAMSV_MODULE_EN 0x10
> +#define CAMSV_FMT_SEL0x14
> +#define CAMSV_INT_EN 0x18
> +#define CAMSV_CLK_EN 0x30
> +
> +#define CAMSV_TG_SEN_MODE0x500
> +#define CAMSV_TG_SEN_GRAB_PXL0x508
> +#define CAMSV_TG_SEN_GRAB_LIN0x50C
> +#define CAMSV_TG_PATH_CFG0x510
> +
> +#define IMGO_XSIZE 0x230
> +#define IMGO_YSIZE 0x234
> +#define IMGO_STRIDE 0x238
> +#define DMA_FRAME_HEADER_EN 0xE00
> +
> +struct mtk_mipicsi_dev {
> + struct platform_device *pdev;
> + unsigned int camsv_num;
> + struct device
Re: [PATCH v6 08/12] soc: mediatek: cmdq: define the instruction struct
Hi, Bibby: On Thu, 2019-05-16 at 17:02 +0800, Bibby Hsieh wrote: > Define a instruction structure for gce driver to append command. > This structure can make the client's code more readability. > > Signed-off-by: Bibby Hsieh > --- > drivers/soc/mediatek/mtk-cmdq-helper.c | 113 +++ > include/linux/mailbox/mtk-cmdq-mailbox.h | 2 + > include/linux/soc/mediatek/mtk-cmdq.h| 14 +-- > 3 files changed, 84 insertions(+), 45 deletions(-) > [snip] > > /** > * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet > * @pkt: the CMDQ packet > - * @value: the specified target register value > * @subsys: the CMDQ sub system code > * @offset: register offset from CMDQ sub system > + * @value: the specified target register value > * @mask:the specified target register mask > * > * Return: 0 for success; else the error code is returned > */ > -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value, > - u32 subsys, u32 offset, u32 mask); > +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset, > + u32 value, u32 mask); You have do two things for this interface: one is reordering the parameter, another one is changing type of subsys from u32 to u8. Define the instruction struct is not necessary to change the order and type. I would like you to separate these two things to another patches. So the patch sequence may be: 1. Reorder parameter of cmdq_pkt_write_mask() 2. Change subsys type to u8 3. define the instruction struct Regards, CK > > /** > * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet > @@ -88,7 +88,7 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value, > * > * Return: 0 for success; else the error code is returned > */ > -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event); > +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event); > > /** > * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet > @@ -97,7 +97,7 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event); > * > * Return: 0 for success; else the error code is returned > */ > -int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event); > +int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event); > > /** > * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
Re: [PATCH v6 03/12] dt-binding: gce: add binding for gce subsys property
Hi, Bibby: On Thu, 2019-05-16 at 17:02 +0800, Bibby Hsieh wrote: > tcmdq driver provide a function that get the relationship What is 'tcmdq'? > of sub system number from device node for client. > add specification for #subsys-cells, mediatek,gce-subsys. The property name is mediatek,gce-client-reg. Regards, CK > > Signed-off-by: Bibby Hsieh > --- > .../devicetree/bindings/mailbox/mtk-gce.txt | 15 --- > 1 file changed, 12 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > index 1f7f8f2a3f49..dceab63ccd06 100644 > --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > @@ -21,11 +21,19 @@ Required properties: > priority: Priority of GCE thread. > atomic_exec: GCE processing continuous packets of commands in atomic > way. > +- #subsys-cells: Should be 3. > + < subsys_number start_offset size> > + phandle: Label name of a gce node. > + subsys_number: specify the sub-system id which is corresponding > +to the register address. > + start_offset: the start offset of register address that GCE can access. > + size: the total size of register address that GCE can access. > > Required properties for a client device: > - mboxes: Client use mailbox to communicate with GCE, it should have this >property and list of phandle, mailbox specifiers. > -- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding > +Optional properties for a client device: > +- mediatek,gce-client-reg: u32, specify the sub-system id which is > corresponding >to the register address. > > Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' > @@ -40,6 +48,7 @@ Example: > clocks = < CLK_INFRA_GCE>; > clock-names = "gce"; > #mbox-cells = <3>; > + #subsys-cells = <3>; > }; > > Example for a client device: > @@ -48,9 +57,9 @@ Example for a client device: > compatible = "mediatek,mt8173-mmsys"; > mboxes = < 0 CMDQ_THR_PRIO_LOWEST 1>, >< 1 CMDQ_THR_PRIO_LOWEST 1>; > - mediatek,gce-subsys = ; > mutex-event-eof =CMDQ_EVENT_MUTEX1_STREAM_EOF>; > - > + mediatek,gce-client-reg = < SUBSYS_1400 0x3000 0x1000>, > + < SUBSYS_1401 0x2000 0x100>; > ... > };
Re: [PATCH v6 10/12] soc: mediatek: cmdq: add cmdq_dev_get_subsys function
Hi, Bibby:
On Thu, 2019-05-16 at 17:02 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the relationship of subsys
> and register base address.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 25 +
> include/linux/soc/mediatek/mtk-cmdq.h | 18 ++
> 2 files changed, 43 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index a53cdd71cfc2..a64060a34e01 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -27,6 +27,31 @@ struct cmdq_instruction {
> u8 op;
> };
>
> +struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx)
> +{
> + struct cmdq_subsys *subsys;
> + struct of_phandle_args spec;
> +
> + subsys = devm_kzalloc(dev, sizeof(*subsys), GFP_KERNEL);
> + if (!subsys)
> + return NULL;
> +
> + if (of_parse_phandle_with_args(dev->of_node, "mediatek,gce-client-reg",
> +"#subsys-cells", idx, )) {
> + dev_err(dev, "can't parse gce-client-reg property");
print the idx info.
> +
I think you should free the buffer you allocate. Don't expect this
function is called in caller's probe function.
> + return (struct cmdq_subsys *)-ENODEV;
Why not return NULL?
> + }
> +
> + subsys->id = spec.args[0];
> + subsys->offset = spec.args[1];
> + subsys->size = spec.args[2];
> + of_node_put(spec.np);
> +
> + return subsys;
> +}
> +EXPORT_SYMBOL(cmdq_dev_get_subsys);
> +
> static void cmdq_client_timeout(struct timer_list *t)
> {
> struct cmdq_client *client = from_timer(client, t, timer);
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index 0651a0bffa54..574006c5cd76 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -15,6 +15,12 @@
>
> struct cmdq_pkt;
>
> +struct cmdq_subsys {
May be cmdq_client_reg.
> + u8 id;
May be subsys.
Regards,
CK
> + u16 offset;
> + u16 size;
> +};
> +
> struct cmdq_client {
> spinlock_t lock;
> u32 pkt_cnt;
> @@ -142,4 +148,16 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt,
> cmdq_async_flush_cb cb,
> */
> int cmdq_pkt_flush(struct cmdq_pkt *pkt);
>
> +/**
> + * cmdq_dev_get_subsys() - parse sub system from the device node of CMDQ
> client
> + * @dev: device of CMDQ mailbox client
> + * @idx: the index of desired subsys
> + *
> + * Return: CMDQ subsys pointer
> + *
> + * Help CMDQ client pasing the sub system number
> + * from the device node of CMDQ client.
> + */
> +struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx);
> +
> #endif /* __MTK_CMDQ_H__ */
Re: [PATCH v6 11/12] soc: mediatek: cmdq: add cmdq_dev_get_event function
Hi, Bibby:
On Thu, 2019-05-16 at 17:02 +0800, Bibby Hsieh wrote:
> When client ask gce to clear or wait for event,
> client need to pass event number to the API.
> We suggest client store the event information in device node,
> so we provide an API for client parse the event property.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 18 ++
> include/linux/soc/mediatek/mtk-cmdq.h | 12
> 2 files changed, 30 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index a64060a34e01..e9658063c3d4 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -52,6 +52,24 @@ struct cmdq_subsys *cmdq_dev_get_subsys(struct device
> *dev, int idx)
> }
> EXPORT_SYMBOL(cmdq_dev_get_subsys);
>
> +s32 cmdq_dev_get_event(struct device *dev, int index)
> +{
> + s32 result;
> +
> + if (!dev)
> + return -EINVAL;
> +
> + if (of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
> +index, )) {
> + dev_err(dev, "can't parse gce-events property");
> +
> + return -ENODEV;
> + }
> +
> + return result;
This function just does one thing, so client driver could just directly
call of_property_read_u32_index().
Regards,
CK
> +}
> +EXPORT_SYMBOL(cmdq_dev_get_event);
> +
> static void cmdq_client_timeout(struct timer_list *t)
> {
> struct cmdq_client *client = from_timer(client, t, timer);
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index 574006c5cd76..525713bf79b5 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -160,4 +160,16 @@ int cmdq_pkt_flush(struct cmdq_pkt *pkt);
> */
> struct cmdq_subsys *cmdq_dev_get_subsys(struct device *dev, int idx);
>
> +/**
> + * cmdq_dev_get_event() - parse event from the device node of CMDQ client
> + * @dev: device of CMDQ mailbox client
> + * @index: the index of desired event
> + *
> + * Return: CMDQ event number
> + *
> + * Help CMDQ client pasing the event number
> + * from the device node of CMDQ client.
> + */
> +s32 cmdq_dev_get_event(struct device *dev, int index);
> +
> #endif /* __MTK_CMDQ_H__ */
Re: [PATCH v5 04/12] dt-binding: gce: add binding for gce event property
Hi, Bibby: On Fri, 2019-05-10 at 11:27 +0800, Bibby Hsieh wrote: > Hi, CK, > > On Wed, 2019-05-08 at 13:10 +0800, CK Hu wrote: > > Hi, Bibby: > > > > On Tue, 2019-05-07 at 16:13 +0800, Bibby Hsieh wrote: > > > Client hardware would send event to GCE hardware, > > > mediatek,gce-event-names and mediatek,gce-events > > > can be used to present the event. > > > > > > Signed-off-by: Bibby Hsieh > > > --- > > > Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 9 +++-- > > > 1 file changed, 7 insertions(+), 2 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > > > b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > > > index 8fd9479bc9f6..76491f194c56 100644 > > > --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > > > +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > > > @@ -35,6 +35,9 @@ Required properties for a client device: > > > Optional propertier for a client device: > > > - mediatek,gce-client-reg: u32, specify the sub-system id which is > > > corresponding > > >to the register address. > > > +- mediatek,gce-event-names: the event name can be defined by user. > > > > gce-event is like an interrupt from client hardware to GCE hardware, we > > do not give a name to an interrupt, so do we need to give a name for > > gce-event? > > > > Yes, we need to know the name of gce-ecent. > The name can help users to figure out the problems when GCE meet the > event time out errors. For debug, driver does not need this information. In your example, The event 'CMDQ_EVENT_MDP_RDMA0_SOF' is used by rdma driver. I think rdma driver should know why it need this event (it want to know whether 'rdma is starting to work (SOF)'), so when this event is time out, rdma driver should know what is timeout (it knows RDMA_SOF is timeout). Regards, CK > > > > Regards, > > CK > > > > > +- mediatek,gce-events: u32, the event number defined in > > > + 'dt-bindings/gce/mt8173-gce.h' or 'dt-binding/gce/mt8183-gce.h'. > > > > > > Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' > > > or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread > > > priority, event ids. > > > @@ -57,8 +60,10 @@ Example for a client device: > > > compatible = "mediatek,mt8173-mmsys"; > > > mboxes = < 0 CMDQ_THR_PRIO_LOWEST 1>, > > >< 1 CMDQ_THR_PRIO_LOWEST 1>; > > > - mutex-event-eof = > > - CMDQ_EVENT_MUTEX1_STREAM_EOF>; > > > + mediatek,gce-event-names = "rdma0_sof", > > > +"rsz0_sof"; > > > + mediatek,gce-events = , > > > + ; > > > mediatek,gce-client-reg = < SUBSYS_1400 0x3000 0x1000>, > > > < SUBSYS_1401 0x2000 0x100>; > > > ... > > > > >
Re: [PATCH v5 09/12] soc: mediatek: cmdq: add polling function
Hi, Bibby:
On Tue, 2019-05-07 at 16:13 +0800, Bibby Hsieh wrote:
> add polling function in cmdq helper functions
Reviewed-by: CK Hu
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 29
> include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
> include/linux/soc/mediatek/mtk-cmdq.h| 15
> 3 files changed, 45 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 17ee8196fb3d..716f8c4f207b 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -220,6 +220,34 @@ int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)
> }
> EXPORT_SYMBOL(cmdq_pkt_clear_event);
>
> +int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
> + u16 offset, u32 value, u32 mask)
> +{
> + struct cmdq_instruction *inst;
> +
> + if (mask != 0x) {
> + inst = cmdq_pkt_append_command(pkt);
> + if (!inst)
> + return -ENOMEM;
> +
> + inst->op = CMDQ_CODE_MASK;
> + inst->value = ~mask;
> + offset = offset | 0x1;
> + }
> +
> + inst = cmdq_pkt_append_command(pkt);
> + if (!inst)
> + return -ENOMEM;
> +
> + inst->op = CMDQ_CODE_POLL;
> + inst->value = value;
> + inst->offset = offset;
> + inst->subsys = subsys;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(cmdq_pkt_poll);
> +
> static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
> {
> struct cmdq_instruction *inst;
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h
> b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index f21801d32a3a..1dfd5ed5c8c5 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -46,6 +46,7 @@
> enum cmdq_code {
> CMDQ_CODE_MASK = 0x02,
> CMDQ_CODE_WRITE = 0x04,
> + CMDQ_CODE_POLL = 0x08,
> CMDQ_CODE_JUMP = 0x10,
> CMDQ_CODE_WFE = 0x20,
> CMDQ_CODE_EOC = 0x40,
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index 52f69c8db8de..0651a0bffa54 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -99,6 +99,21 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
> */
> int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
>
> +/**
> + * cmdq_pkt_poll() - Append polling command to the CMDQ packet, ask GCE to
> + *execute an instruction that wait for a specified hardware
> + *register to check for the value. All GCE hardware
> + *threads will be blocked by this instruction.
> + * @pkt: the CMDQ packet
> + * @subsys: the CMDQ sub system code
> + * @offset: register offset from CMDQ sub system
> + * @value: the specified target register value
> + * @mask:the specified target register mask
> + *
> + * Return: 0 for success; else the error code is returned
> + */
> +int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
> + u16 offset, u32 value, u32 mask);
> /**
> * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
> * packet and call back at the end of done packet
Re: [PATCH v5 08/12] soc: mediatek: cmdq: define the instruction struct
Hi, Bibby:
On Tue, 2019-05-07 at 16:13 +0800, Bibby Hsieh wrote:
> Define a instruction structure for gce driver to append command.
I would like you to describe _WHY_ do this. I think you do this for
'code readability'.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 113 +++
> include/linux/mailbox/mtk-cmdq-mailbox.h | 2 +
> include/linux/soc/mediatek/mtk-cmdq.h| 14 +--
> 3 files changed, 84 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index ff9fef5a032b..17ee8196fb3d 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -9,12 +9,24 @@
> #include
> #include
>
> -#define CMDQ_ARG_A_WRITE_MASK0x
> #define CMDQ_WRITE_ENABLE_MASK BIT(0)
> #define CMDQ_EOC_IRQ_EN BIT(0)
> #define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \
> << 32 | CMDQ_EOC_IRQ_EN)
>
> +struct cmdq_instruction {
> + union {
> + u32 value;
> + u32 mask;
> + };
> + union {
> + u16 offset;
> + u16 event;
> + };
> + u8 subsys;
> + u8 op;
> +};
> +
> static void cmdq_client_timeout(struct timer_list *t)
> {
> struct cmdq_client *client = from_timer(client, t, timer);
> @@ -110,10 +122,8 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt)
> }
> EXPORT_SYMBOL(cmdq_pkt_destroy);
>
> -static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
> -u32 arg_a, u32 arg_b)
> +static struct cmdq_instruction *cmdq_pkt_append_command(struct cmdq_pkt *pkt)
> {
> - u64 *cmd_ptr;
>
> if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) {
> /*
> @@ -127,81 +137,108 @@ static int cmdq_pkt_append_command(struct cmdq_pkt
> *pkt, enum cmdq_code code,
> pkt->cmd_buf_size += CMDQ_INST_SIZE;
> WARN_ONCE(1, "%s: buffer size %u is too small !\n",
> __func__, (u32)pkt->buf_size);
> - return -ENOMEM;
> + return NULL;
> }
> - cmd_ptr = pkt->va_base + pkt->cmd_buf_size;
> - (*cmd_ptr) = (u64)((code << CMDQ_OP_CODE_SHIFT) | arg_a) << 32 | arg_b;
> +
> pkt->cmd_buf_size += CMDQ_INST_SIZE;
>
> - return 0;
> + return pkt->va_base + pkt->cmd_buf_size - CMDQ_INST_SIZE;
> }
>
> -int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset)
> +int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
> {
> - u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) |
> - (subsys << CMDQ_SUBSYS_SHIFT);
> + struct cmdq_instruction *inst;
> +
> + inst = cmdq_pkt_append_command(pkt);
> + if (!inst)
> + return -ENOMEM;
> +
> + inst->op = CMDQ_CODE_WRITE;
> + inst->value = value;
> + inst->offset = offset;
> + inst->subsys = subsys;
>
> - return cmdq_pkt_append_command(pkt, CMDQ_CODE_WRITE, arg_a, value);
> + return 0;
> }
> EXPORT_SYMBOL(cmdq_pkt_write);
>
> -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
> - u32 subsys, u32 offset, u32 mask)
> +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset,
> + u32 value, u32 mask)
> {
> + struct cmdq_instruction *inst;
> u32 offset_mask = offset;
> - int err = 0;
>
> if (mask != 0x) {
> - err = cmdq_pkt_append_command(pkt, CMDQ_CODE_MASK, 0, ~mask);
> + inst = cmdq_pkt_append_command(pkt);
> + if (!inst)
> + return -ENOMEM;
> +
> + inst->op = CMDQ_CODE_MASK;
> + inst->mask = ~mask;
> offset_mask |= CMDQ_WRITE_ENABLE_MASK;
> }
> - err |= cmdq_pkt_write(pkt, value, subsys, offset_mask);
>
> - return err;
> + return cmdq_pkt_write(pkt, subsys, offset_mask, value);
> }
> EXPORT_SYMBOL(cmdq_pkt_write_mask);
>
> -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event)
> +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
> {
> - u32 arg_b;
> + struct cmdq_instruction *inst;
>
> if (event >= CMDQ_MAX_EVENT)
> return -EINVAL;
>
> - /*
> - * WFE arg_b
> - * bit 0-11: wait value
> - * bit 15: 1 - wait, 0 - no wait
> - * bit 16-27: update value
> - * bit 31: 1 - update, 0 - no update
> - */
> - arg_b = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
> + inst = cmdq_pkt_append_command(pkt);
> + if (!inst)
> + return -ENOMEM;
> +
> + inst->op = CMDQ_CODE_WFE;
> + inst->value = CMDQ_WFE_OPTION;
> + inst->event = event;
>
> - return cmdq_pkt_append_command(pkt, CMDQ_CODE_WFE, event, arg_b);
> + return 0;
> }
> EXPORT_SYMBOL(cmdq_pkt_wfe);
>
> -int
Re: [PATCH v5 04/12] dt-binding: gce: add binding for gce event property
Hi, Bibby: On Tue, 2019-05-07 at 16:13 +0800, Bibby Hsieh wrote: > Client hardware would send event to GCE hardware, > mediatek,gce-event-names and mediatek,gce-events > can be used to present the event. > > Signed-off-by: Bibby Hsieh > --- > Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 9 +++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > index 8fd9479bc9f6..76491f194c56 100644 > --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > @@ -35,6 +35,9 @@ Required properties for a client device: > Optional propertier for a client device: > - mediatek,gce-client-reg: u32, specify the sub-system id which is > corresponding >to the register address. > +- mediatek,gce-event-names: the event name can be defined by user. gce-event is like an interrupt from client hardware to GCE hardware, we do not give a name to an interrupt, so do we need to give a name for gce-event? Regards, CK > +- mediatek,gce-events: u32, the event number defined in > + 'dt-bindings/gce/mt8173-gce.h' or 'dt-binding/gce/mt8183-gce.h'. > > Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' > or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, > event ids. > @@ -57,8 +60,10 @@ Example for a client device: > compatible = "mediatek,mt8173-mmsys"; > mboxes = < 0 CMDQ_THR_PRIO_LOWEST 1>, >< 1 CMDQ_THR_PRIO_LOWEST 1>; > - mutex-event-eof = - CMDQ_EVENT_MUTEX1_STREAM_EOF>; > + mediatek,gce-event-names = "rdma0_sof", > +"rsz0_sof"; > + mediatek,gce-events = , > + ; > mediatek,gce-client-reg = < SUBSYS_1400 0x3000 0x1000>, > < SUBSYS_1401 0x2000 0x100>; > ...
Re: [PATCH v5 03/12] dt-binding: gce: add binding for gce subsys property
Hi, Bibby: On Tue, 2019-05-07 at 16:13 +0800, Bibby Hsieh wrote: > tcmdq driver provide a function that get the relationship > of sub system number from device node for client. > add specification for #subsys-cells, mediatek,gce-subsys. > > Signed-off-by: Bibby Hsieh > --- > .../devicetree/bindings/mailbox/mtk-gce.txt | 15 --- > 1 file changed, 12 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > index 1f7f8f2a3f49..8fd9479bc9f6 100644 > --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > @@ -21,11 +21,19 @@ Required properties: > priority: Priority of GCE thread. > atomic_exec: GCE processing continuous packets of commands in atomic > way. > +- #subsys-cells: Should be 3. > + < subsys_number start_offset size> > + phandle: Label name of a gce node. > + subsys_number: specify the sub-system id which is corresponding > +to the register address. > + start_offset: the start offset of register address that GCE can access. > + size: the total size of register address that GCE can access. > > Required properties for a client device: > - mboxes: Client use mailbox to communicate with GCE, it should have this >property and list of phandle, mailbox specifiers. > -- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding > +Optional propertier for a client device: properties Regards, CK > +- mediatek,gce-client-reg: u32, specify the sub-system id which is > corresponding >to the register address. > > Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' > @@ -40,6 +48,7 @@ Example: > clocks = < CLK_INFRA_GCE>; > clock-names = "gce"; > #mbox-cells = <3>; > + #subsys-cells = <3>; > }; > > Example for a client device: > @@ -48,9 +57,9 @@ Example for a client device: > compatible = "mediatek,mt8173-mmsys"; > mboxes = < 0 CMDQ_THR_PRIO_LOWEST 1>, >< 1 CMDQ_THR_PRIO_LOWEST 1>; > - mediatek,gce-subsys = ; > mutex-event-eof =CMDQ_EVENT_MUTEX1_STREAM_EOF>; > - > + mediatek,gce-client-reg = < SUBSYS_1400 0x3000 0x1000>, > + < SUBSYS_1401 0x2000 0x100>; > ... > };
Re: [v2 1/5] drm/mediatek: move mipi_dsi_host_register to probe
Hi, Jitao:
On Tue, 2019-04-16 at 14:04 +0800, Jitao Shi wrote:
> DSI panel driver need attach function which is inculde in
> mipi_dsi_host_ops.
>
> If mipi_dsi_host_register is not in probe, dsi panel will
> probe fail or more delay.
I think this patch just prevent delay, not to prevent dsi panel probe
fail. In [1], you mention mipi_dsi_attach() is called in
panel_simple_dsi_probe(), but panel_simple_dsi_probe() is trigger by
mipi_dsi_host_register(), so the probe would success.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/panel/panel-simple.c?h=v5.0-rc6#n2987
>
> So move the mipi_dsi_host_register to probe from bind.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 50 ++
> 1 file changed, 30 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index b00eb2d2e086..6c4ac37f983d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -1045,12 +1045,6 @@ static int mtk_dsi_bind(struct device *dev, struct
> device *master, void *data)
> return ret;
> }
>
> - ret = mipi_dsi_host_register(>host);
> - if (ret < 0) {
> - dev_err(dev, "failed to register DSI host: %d\n", ret);
> - goto err_ddp_comp_unregister;
> - }
> -
> ret = mtk_dsi_create_conn_enc(drm, dsi);
> if (ret) {
> DRM_ERROR("Encoder create failed with %d\n", ret);
> @@ -1060,8 +1054,6 @@ static int mtk_dsi_bind(struct device *dev, struct
> device *master, void *data)
> return 0;
>
> err_unregister:
> - mipi_dsi_host_unregister(>host);
> -err_ddp_comp_unregister:
> mtk_ddp_comp_unregister(drm, >ddp_comp);
> return ret;
> }
> @@ -1097,31 +1089,37 @@ static int mtk_dsi_probe(struct platform_device *pdev)
>
> dsi->host.ops = _dsi_ops;
> dsi->host.dev = dev;
> + dsi->dev = dev;
Why do this?
Regards,
CK
> + ret = mipi_dsi_host_register(>host);
> + if (ret < 0) {
> + dev_err(dev, "failed to register DSI host: %d\n", ret);
> + return ret;
> + }
>
> ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
> >panel, >bridge);
> if (ret)
> - return ret;
> + goto err_unregister_host;
>
> dsi->engine_clk = devm_clk_get(dev, "engine");
> if (IS_ERR(dsi->engine_clk)) {
> ret = PTR_ERR(dsi->engine_clk);
> dev_err(dev, "Failed to get engine clock: %d\n", ret);
> - return ret;
> + goto err_unregister_host;
> }
>
> dsi->digital_clk = devm_clk_get(dev, "digital");
> if (IS_ERR(dsi->digital_clk)) {
> ret = PTR_ERR(dsi->digital_clk);
> dev_err(dev, "Failed to get digital clock: %d\n", ret);
> - return ret;
> + goto err_unregister_host;
> }
>
> dsi->hs_clk = devm_clk_get(dev, "hs");
> if (IS_ERR(dsi->hs_clk)) {
> ret = PTR_ERR(dsi->hs_clk);
> dev_err(dev, "Failed to get hs clock: %d\n", ret);
> - return ret;
> + goto err_unregister_host;
> }
>
> regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Re: [v3 3/3] drm/mediatek: add mt8183 dpi support
Hi, Jitao:
On Tue, 2019-04-16 at 13:52 +0800, Jitao Shi wrote:
I need the commit message. Even though the code is easy to understand,
words for this patch is still necessary.
Regards,
CK
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 66405159141a..fbb087218775 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -681,6 +681,16 @@ static unsigned int mt2701_calculate_factor(int clock)
> return 2;
> }
>
> +static unsigned int mt8183_calculate_factor(int clock)
> +{
> + if (clock <= 27000)
> + return 8;
> + else if (clock <= 167000)
> + return 4;
> + else
> + return 2;
> +}
> +
> static const struct mtk_dpi_conf mt8173_conf = {
> .cal_factor = mt8173_calculate_factor,
> .reg_h_fre_con = 0xe0,
> @@ -692,6 +702,12 @@ static const struct mtk_dpi_conf mt2701_conf = {
> .edge_sel_en = true,
> };
>
> +static const struct mtk_dpi_conf mt8183_conf = {
> + .cal_factor = mt8183_calculate_factor,
> + .reg_h_fre_con = 0xe0,
> + .dual_edge = true,
> +};
> +
> static int mtk_dpi_probe(struct platform_device *pdev)
> {
> struct device *dev = >dev;
> @@ -787,6 +803,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
> { .compatible = "mediatek,mt8173-dpi",
> .data = _conf,
> },
> + { .compatible = "mediatek,mt8183-dpi",
> + .data = _conf,
> + },
> { },
> };
>
Re: [PATCH v4 08/12] soc: mediatek: cmdq: add packet encoder function
Hi, Bibby:
On Mon, 2019-04-15 at 20:58 +0800, Bibby Hsieh wrote:
> Implement a function can encode the GCE instructions
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 125 ---
> include/linux/mailbox/mtk-cmdq-mailbox.h | 2 +
> include/linux/soc/mediatek/mtk-cmdq.h| 14 +--
> 3 files changed, 99 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c
> b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index ff9fef5a032b..d3873ab21db3 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -9,11 +9,43 @@
> #include
> #include
>
> -#define CMDQ_ARG_A_WRITE_MASK0x
> +#define CMDQ_GET_ARG_B(arg) (((arg) & GENMASK(31, 16)) >> 16)
> +#define CMDQ_GET_ARG_C(arg) ((arg) & GENMASK(15, 0))
> #define CMDQ_WRITE_ENABLE_MASK BIT(0)
> #define CMDQ_EOC_IRQ_EN BIT(0)
> #define CMDQ_EOC_CMD ((u64)((CMDQ_CODE_EOC << CMDQ_OP_CODE_SHIFT)) \
> << 32 | CMDQ_EOC_IRQ_EN)
> +#define CMDQ_IMMEDIATE_VALUE 0
> +#define CMDQ_REG_TYPE1
> +
> +struct cmdq_instruction {
> + s16 arg_c:16;
> + s16 arg_b:16;
> + s16 arg_a:16;
> + u8 s_op:5;
> + u8 arg_c_type:1;
> + u8 arg_b_type:1;
> + u8 arg_a_type:1;
> + u8 op:8;
> +};
> +
> +static void cmdq_pkt_instr_encoder(struct cmdq_pkt *pkt, s16 arg_c, s16
> arg_b,
> +s16 arg_a, u8 s_op, u8 arg_c_type,
> +u8 arg_b_type, u8 arg_a_type, u8 op)
> +{
> + struct cmdq_instruction *cmdq_inst;
> +
> + cmdq_inst = pkt->va_base + pkt->cmd_buf_size;
> + cmdq_inst->op = op;
> + cmdq_inst->arg_a_type = arg_a_type;
> + cmdq_inst->arg_b_type = arg_b_type;
> + cmdq_inst->arg_c_type = arg_c_type;
> + cmdq_inst->s_op = s_op;
> + cmdq_inst->arg_a = arg_a;
> + cmdq_inst->arg_b = arg_b;
> + cmdq_inst->arg_c = arg_c;
> + pkt->cmd_buf_size += CMDQ_INST_SIZE;
> +}
>
> static void cmdq_client_timeout(struct timer_list *t)
> {
> @@ -110,10 +142,11 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt)
> }
> EXPORT_SYMBOL(cmdq_pkt_destroy);
>
> -static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, enum cmdq_code code,
> -u32 arg_a, u32 arg_b)
> +static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, s16 arg_c, s16
> arg_b,
> +s16 arg_a, u8 s_op, u8 arg_c_type,
> +u8 arg_b_type, u8 arg_a_type,
> +enum cmdq_code code)
> {
> - u64 *cmd_ptr;
>
> if (unlikely(pkt->cmd_buf_size + CMDQ_INST_SIZE > pkt->buf_size)) {
> /*
> @@ -129,65 +162,72 @@ static int cmdq_pkt_append_command(struct cmdq_pkt
> *pkt, enum cmdq_code code,
> __func__, (u32)pkt->buf_size);
> return -ENOMEM;
> }
> - cmd_ptr = pkt->va_base + pkt->cmd_buf_size;
> - (*cmd_ptr) = (u64)((code << CMDQ_OP_CODE_SHIFT) | arg_a) << 32 | arg_b;
> - pkt->cmd_buf_size += CMDQ_INST_SIZE;
> + cmdq_pkt_instr_encoder(pkt, arg_c, arg_b, arg_a, s_op, arg_c_type,
> +arg_b_type, arg_a_type, code);
>
> return 0;
> }
>
> -int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset)
> +int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value)
> {
> - u32 arg_a = (offset & CMDQ_ARG_A_WRITE_MASK) |
> - (subsys << CMDQ_SUBSYS_SHIFT);
> -
> - return cmdq_pkt_append_command(pkt, CMDQ_CODE_WRITE, arg_a, value);
> + return cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(value),
> +CMDQ_GET_ARG_B(value), offset, subsys,
> +CMDQ_IMMEDIATE_VALUE,
> +CMDQ_IMMEDIATE_VALUE,
> +CMDQ_IMMEDIATE_VALUE, CMDQ_CODE_WRITE);
I do not understand why you invent a encoder function. It neither reduce
the code size, nor make code easier for reading. If for easier reading,
I suggest this way:
struct cmdq_instruction {
union {
struct {
u32 value;
u16 offset;
u8 subsys;
};
struct {
...
};
};
u8 op;
};
struct cmdq_instruction *inst;
inst = cmdq_pkt_append_command(pkt);
if (!inst)
return -ENOMEM;
inst->op = CMDQ_CODE_WRITE;
inst->subsys = subsys;
inst->offset = offset;
inst->value = value;
Regards,
CK
> }
> EXPORT_SYMBOL(cmdq_pkt_write);
>
> -int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
> - u32 subsys, u32 offset, u32 mask)
> +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset,
> + u32 value, u32 mask)
> {
> u32 offset_mask
Re: [PATCH v4 07/12] soc: mediatek: cmdq: clear the event in cmdq initial flow
Hi, Bibby:
On Mon, 2019-04-15 at 20:58 +0800, Bibby Hsieh wrote:
> GCE hardware stored event information in own internal sysram,
> if the initial value in those sysram is not zero value
> it will cause a situation that gce can wait the event immediately
> after client ask gce to wait event but not really trigger the
> corresponding hardware.
>
> In order to make sure that the wait event function is
> exactly correct, we need to clear the sysram value in
> cmdq initial flow.
>
> Fixes: 623a6143a845 ("mailbox: mediatek: Add Mediatek CMDQ driver")
Reviewed-by: CK Hu
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 5 +
> include/linux/mailbox/mtk-cmdq-mailbox.h | 2 ++
> include/linux/soc/mediatek/mtk-cmdq.h| 3 ---
> 3 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 6db1e2dd2dea..4e744cf2c3fb 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -33,6 +33,7 @@
> #define CMDQ_THR_END_ADDR0x24
> #define CMDQ_THR_WAIT_TOKEN 0x30
> #define CMDQ_THR_PRIORITY0x40
> +#define CMDQ_SYNC_TOKEN_UPDATE 0x68
>
> #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
> #define CMDQ_THR_ENABLED 0x1
> @@ -103,8 +104,12 @@ static void cmdq_thread_resume(struct cmdq_thread
> *thread)
>
> static void cmdq_init(struct cmdq *cmdq)
> {
> + int i;
> +
> WARN_ON(clk_enable(cmdq->clock) < 0);
> writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
> + for (i = 0; i <= CMDQ_MAX_EVENT; i++)
> + writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
> clk_disable(cmdq->clock);
> }
>
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h
> b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index ccb73422c2fa..911475da7a53 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -19,6 +19,8 @@
> #define CMDQ_WFE_UPDATE BIT(31)
> #define CMDQ_WFE_WAITBIT(15)
> #define CMDQ_WFE_WAIT_VALUE 0x1
> +/** cmdq event maximum */
> +#define CMDQ_MAX_EVENT 0x3ff
>
> /*
> * CMDQ_CODE_MASK:
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h
> b/include/linux/soc/mediatek/mtk-cmdq.h
> index 54ade13a9b15..4e8899972db4 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -13,9 +13,6 @@
>
> #define CMDQ_NO_TIMEOUT 0xu
>
> -/** cmdq event maximum */
> -#define CMDQ_MAX_EVENT 0x3ff
> -
> struct cmdq_pkt;
>
> struct cmdq_client {
Re: [PATCH v4 06/12] soc: mediatek: cmdq: support mt8183 gce function
Hi, Bibby:
On Mon, 2019-04-15 at 20:58 +0800, Bibby Hsieh wrote:
> add mt8183 compatible name for supporting gce function
Reviewed-by: CK Hu
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 87617dc7504d..6db1e2dd2dea 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -538,6 +538,7 @@ static const struct dev_pm_ops cmdq_pm_ops = {
>
> static const struct of_device_id cmdq_of_ids[] = {
> {.compatible = "mediatek,mt8173-gce", .data = (void *)16},
> + {.compatible = "mediatek,mt8183-gce", .data = (void *)24},
> {}
> };
>
Re: [PATCH v4 05/12] soc: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data
Hi, Bibby:
On Mon, 2019-04-15 at 20:58 +0800, Bibby Hsieh wrote:
> The interrupt mask and thread number has positive correlation,
> so we move the CMDQ_IRQ_MASK into cmdq driver data and calculate
> it by thread number.
Reviewed-by: CK Hu
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 12 +++-
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 22811784dc7d..87617dc7504d 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -17,7 +17,6 @@
> #include
>
> #define CMDQ_OP_CODE_MASK(0xff << CMDQ_OP_CODE_SHIFT)
> -#define CMDQ_IRQ_MASK0x
> #define CMDQ_NUM_CMD(t) (t->cmd_buf_size /
> CMDQ_INST_SIZE)
>
> #define CMDQ_CURR_IRQ_STATUS 0x10
> @@ -71,6 +70,7 @@ struct cmdq {
> void __iomem*base;
> u32 irq;
> u32 thread_nr;
> + u32 irq_mask;
> struct cmdq_thread *thread;
> struct clk *clock;
> boolsuspended;
> @@ -284,11 +284,11 @@ static irqreturn_t cmdq_irq_handler(int irq, void *dev)
> unsigned long irq_status, flags = 0L;
> int bit;
>
> - irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & CMDQ_IRQ_MASK;
> - if (!(irq_status ^ CMDQ_IRQ_MASK))
> + irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
> + if (!(irq_status ^ cmdq->irq_mask))
> return IRQ_NONE;
>
> - for_each_clear_bit(bit, _status, fls(CMDQ_IRQ_MASK)) {
> + for_each_clear_bit(bit, _status, cmdq->thread_nr) {
> struct cmdq_thread *thread = >thread[bit];
>
> spin_lock_irqsave(>chan->lock, flags);
> @@ -472,6 +472,9 @@ static int cmdq_probe(struct platform_device *pdev)
> dev_err(dev, "failed to get irq\n");
> return -EINVAL;
> }
> +
> + cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
> + cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
> err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
> "mtk_cmdq", cmdq);
> if (err < 0) {
> @@ -488,7 +491,6 @@ static int cmdq_probe(struct platform_device *pdev)
> return PTR_ERR(cmdq->clock);
> }
>
> - cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
> cmdq->mbox.dev = dev;
> cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
> sizeof(*cmdq->mbox.chans), GFP_KERNEL);
Re: [PATCH v2 02/15] [media] mtk-mipicsi: add mediatek mipicsi driver for mt2712
Hi, Stu:
On Tue, 2019-04-16 at 17:30 +0800, Stu Hsieh wrote:
> This patch add mediatek mipicsi driver for mt2712,
> including probe function to get the value from device tree,
> and register to v4l2 the host device.
>
> Signed-off-by: Stu Hsieh
> ---
> drivers/media/platform/mtk-mipicsi/Makefile | 4 +
> .../media/platform/mtk-mipicsi/mtk_mipicsi.c | 767 ++
> 2 files changed, 771 insertions(+)
> create mode 100644 drivers/media/platform/mtk-mipicsi/Makefile
> create mode 100644 drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
>
> diff --git a/drivers/media/platform/mtk-mipicsi/Makefile
> b/drivers/media/platform/mtk-mipicsi/Makefile
> new file mode 100644
> index ..326a5e3808fa
> --- /dev/null
> +++ b/drivers/media/platform/mtk-mipicsi/Makefile
> @@ -0,0 +1,4 @@
> +mtk-mipicsi-y += mtk_mipicsi.o
> +
> +obj-$(CONFIG_VIDEO_MEDIATEK_MIPICSI) += mtk-mipicsi.o
> +
> diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
> b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
> new file mode 100644
> index ..e26bebe17fe5
> --- /dev/null
> +++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
> @@ -0,0 +1,767 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 MediaTek Inc.
> + * Author: Ricky Zhang
> + * Baoyin Zhang
> + * Alan Yue
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * http://www.gnu.org/licenses/gpl-2.0.html for more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#ifdef CONFIG_VB2_MEDIATEK_DMA_SG
> +#include "mtkbuf-dma-cache-sg.h"
> +#endif
> +
> +#define MTK_MIPICSI_DRV_NAME "mtk-mipicsi"
> +#define MTK_PLATFORM_STR "platform:mt2712"
> +#define MIPICSI_COMMON_CLK 2
> +#define MTK_CAMDMA_MAX_NUM 4U
> +#define MIPICSI_CLK (MIPICSI_COMMON_CLK + MTK_CAMDMA_MAX_NUM)
> +#define MTK_DATAWIDTH_8 (0x01U << 7U)
> +#define MAX_SUPPORT_WIDTH 4096U
> +#define MAX_SUPPORT_HEIGHT4096U
> +#define MAX_BUFFER_NUM 32U
> +#define VID_LIMIT_BYTES (100U * 1024U * 1024U)
> +
> +/* buffer for one video frame */
> +struct mtk_mipicsi_buf {
> + struct list_head queue;
> + struct vb2_buffer *vb;
> + dma_addr_t vb_dma_addr_phy;
> + int prepare_flag;
> +};
> +
> +struct mtk_mipicsi_dev {
> + struct soc_camera_host soc_host;
> + struct platform_device *pdev;
> + unsigned int camsv_num;
> + struct v4l2_device v4l2_dev;
> + struct device *larb_pdev;
> + void __iomem*ana;
> + void __iomem*seninf_ctrl;
Separating register control to another patch looks strange to me.
Register control is the bottom part and this patch is the top part. You
send a top part first then the bottom part. 'seninf_ctrl' is useless in
this patch, you may move this to the patch that use this variable or
merge that patch into this patch.
Regards,
CK
> + void __iomem*seninf;
> + struct regmap *seninf_top;
> + void __iomem*seninf_mux[MTK_CAMDMA_MAX_NUM];
> + void __iomem*camsv[MTK_CAMDMA_MAX_NUM];
> + const struct soc_camera_format_xlate *current_fmt;
> + u16 width_flags;/* max 12 bits */
> + struct list_headcapture_list[MTK_CAMDMA_MAX_NUM];
> + struct list_headfb_list;
> + spinlock_t lock;
> + spinlock_t queue_lock;
> + struct mtk_mipicsi_buf cam_buf[MAX_BUFFER_NUM];
> + bool streamon;
> + unsigned long frame_cnt[MTK_CAMDMA_MAX_NUM];
> + unsigned int link;
> + unsigned long enqueue_cnt;
> + unsigned long dequeue_cnt;
> + struct v4l2_ctrl_handler ctrl_hdl;
> + char drv_name[16];
> + u32 id;
> + int clk_num;
> + struct clk *clk[MIPICSI_CLK];
> +};
> +
Re: [PATCH V7 1/6] drm/mediatek: recalculate hdmi phy clock of MT2701 by querying hardware
On Wed, 2019-03-27 at 17:19 +0800, wangyan wang wrote:
> From: chunhui dai
>
> Recalculate the rate of this clock, by querying hardware.
You just describe _WHAT_ do you do here, I would like you to describe
_WHT_ do you do here. I think this patch is to make implementation of
recalc_rate() to match the definition.
>
> Signed-off-by: chunhui dai
> Signed-off-by: wangyan wang
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi_phy.c| 7 ++
> drivers/gpu/drm/mediatek/mtk_hdmi_phy.h| 3 +--
> drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 33
> ++
> drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 8 +++
> 4 files changed, 44 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> index 4ef9c57ffd44..13c5e65b9ead 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> @@ -29,12 +29,9 @@ long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned
> long rate,
> return rate;
> }
>
> -unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> -unsigned long parent_rate)
> +u32 mtk_hdmi_phy_read(struct mtk_hdmi_phy *hdmi_phy, u32 offset)
> {
> - struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
> -
> - return hdmi_phy->pll_rate;
> + return readl(hdmi_phy->regs + offset);
> }
This function is useless, so remove it.
Regards,
CK
>
> void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> index f39b1fc66612..fdad8b17a915 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> @@ -41,6 +41,7 @@ struct mtk_hdmi_phy {
> unsigned int ibias_up;
> };
>
> +u32 mtk_hdmi_phy_read(struct mtk_hdmi_phy *hdmi_phy, u32 offset);
> void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
>u32 bits);
> void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> @@ -50,8 +51,6 @@ void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32
> offset,
> struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
> long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
>unsigned long *parent_rate);
> -unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> -unsigned long parent_rate);
>
> extern struct platform_driver mtk_hdmi_phy_driver;
> extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> index fcc42dc6ea7f..9dcf9c2ff37a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> @@ -153,6 +153,39 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw,
> unsigned long rate,
> RG_HDMITX_DRV_IBIAS_MASK);
> return 0;
> }
> +static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> +unsigned long parent_rate)
> +{
> + struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
> + unsigned long out_rate, val;
> +
> + val = (readl(hdmi_phy->regs + HDMI_CON6)
> + & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV;
> + switch (val) {
> + case 0x00:
> + out_rate = parent_rate;
> + break;
> + case 0x01:
> + out_rate = parent_rate / 2;
> + break;
> + default:
> + out_rate = parent_rate / 4;
> + break;
> + }
> +
> + val = (readl(hdmi_phy->regs + HDMI_CON6)
> + & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV;
> + out_rate *= (val + 1) * 2;
> + val = (readl(hdmi_phy->regs + HDMI_CON2)
> + & RG_HDMITX_TX_POSDIV_MASK);
> +
> + out_rate >>= (val >> RG_HDMITX_TX_POSDIV);
> +
> + if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV)
> + out_rate = out_rate / 5;
> +
> + return out_rate;
> +}
>
> static const struct clk_ops mtk_hdmi_phy_pll_ops = {
> .prepare = mtk_hdmi_pll_prepare,
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> index ed5916b27658..cb23c1e4692a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> @@ -285,6 +285,14 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw,
> unsigned long rate,
> return 0;
> }
>
> +static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> +unsigned long parent_rate)
> +{
> + struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
> +
> + return hdmi_phy->pll_rate;
> +}
> +
> static const struct clk_ops
Re: [PATCH V6 8/8] drm/mediatek: fix the rate of parent for hdmi phy in MT2701
Hi, Wangyan:
On Wed, 2019-03-06 at 18:13 +0800, CK Hu wrote:
> Hi, Wangyan:
>
> On Mon, 2019-02-25 at 10:09 +0800, wangyan wang wrote:
> > From: chunhui dai
> >
> > We should not change the rate of parent for hdmi phy when
> > doing round_rate for this clock. The parent clock of hdmi
> > phy must be the same as it. We change it when doing set_rate
> > only.
> >
> > Signed-off-by: chunhui dai
> > Signed-off-by: wangyan wang
> > ---
> > drivers/gpu/drm/mediatek/mtk_hdmi_phy.c| 14 --
> > drivers/gpu/drm/mediatek/mtk_hdmi_phy.h| 3 ---
> > drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 11 +++
> > drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 14 ++
> > 4 files changed, 25 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> > b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> > index 370309d684ec..ca8bc1489f37 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> > @@ -15,20 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops = {
> > .owner = THIS_MODULE,
> > };
> >
> > -long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> > -unsigned long *parent_rate)
> > -{
> > - struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
> > -
> > - hdmi_phy->pll_rate = rate;
> > - if (rate <= 7425)
> > - *parent_rate = rate;
> > - else
> > - *parent_rate = rate / 2;
> > -
> > - return rate;
> > -}
> > -
> > u32 mtk_hdmi_phy_read(struct mtk_hdmi_phy *hdmi_phy, u32 offset)
> > {
> > return readl(hdmi_phy->regs + offset);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> > b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> > index 446e2acd1926..c6061ad15ff0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> > @@ -50,9 +50,6 @@ void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy,
> > u32 offset,
> > void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> >u32 val, u32 mask);
> > struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
> > -long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> > -unsigned long *parent_rate);
> > -
> > extern struct platform_driver mtk_hdmi_phy_driver;
> > extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
> > extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> > b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> > index 88dd9e812ca0..33893a180c2e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> > @@ -152,6 +152,17 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw,
> > unsigned long rate,
> > RG_HDMITX_DRV_IBIAS_MASK);
> > return 0;
> > }
> > +
> > +static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> > +unsigned long *parent_rate)
> > +{
> > + struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
> > +
> > + hdmi_phy->pll_rate = rate;
>
> I think you don't need to save the rate into pll_rate here, pll_rate
> would be set in set_rate() or recalc_rate().
As offline discuss, you mention that this function just need to return
current rate. I think you could just remove this line
'hdmi_phy->pll_rate = rate;' and return rate only. You don't need to
assign hdmi_phy->pll_rate here because it would be set later in
set_rate().
Regards,
CK
>
> Regards,
> CK
>
> > +
> > + return rate;
> > +}
> > +
> > static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> >unsigned long parent_rate)
> > {
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> > b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> > index 63dde42521b8..3a339f516613 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> > @@ -285,6 +285,20 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw,
> > unsigned long rate,
> > return 0;
> > }
> >
> > +static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> > +unsigned long *parent_rate)
> > +{
> > + struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
> > +
> > + hdmi_phy->pll_rate = rate;
> > + if (rate <= 7425)
> > + *parent_rate = rate;
> > + else
> > + *parent_rate = rate / 2;
> > +
> > + return rate;
> > +}
> > +
> > static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> >unsigned long parent_rate)
> > {
>
Re: [PATCH v2 02/10] dt-binding: gce: add binding for gce event property
Hi, Bibby: On Wed, 2019-03-06 at 17:50 +0800, Bibby Hsieh wrote: > cmdq driver provide a function that get event number > from device node for client. I think device tree is based on the view of hardware design, so you need not to mention how the driver design. Client hardware would send event to GCE hardware, so this property present this event. > add specification for #event-cells, > mediatek,gce-event-names, mediatek,gce-events. > > Signed-off-by: Bibby Hsieh > --- > Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 16 +--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > index 9c0d982..812698f 100644 > --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > @@ -21,12 +21,20 @@ Required properties: > priority: Priority of GCE thread. > atomic_exec: GCE processing continuous packets of commands in atomic > way. > +- #event-cells: Should be 1. > + < event_number> > + phandle: Label name of a gce node. > + event_number: the event number defined in 'dt-bindings/gce/mt8173-gce.h' > + or 'dt-binding/gce/mt8183-gce.h'. > > Required properties for a client device: > - mboxes: Client use mailbox to communicate with GCE, it should have this >property and list of phandle, mailbox specifiers. > - mediatek,gce-subsys: u32, specify the sub-system id which is corresponding >to the register address. > +- mediatek,gce-event-names: the event name can be defined by user. > +- mediatek,gce-events: u32, the event number defined in > + 'dt-bindings/gce/mt8173-gce.h' or 'dt-binding/gce/mt8183-gce.h'. I think both gce-subsys and gce-event are optional and depend on the hardware design. Regards, CK > > Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' > or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, > event ids. > @@ -41,6 +49,7 @@ Example: > clock-names = "gce"; > thread-num = CMDQ_THR_MAX_COUNT; > #mbox-cells = <3>; > + #event-cells = <1>; > }; > > Example for a client device: > @@ -50,8 +59,9 @@ Example for a client device: > mboxes = < 0 CMDQ_THR_PRIO_LOWEST 1>, >< 1 CMDQ_THR_PRIO_LOWEST 1>; > mediatek,gce-subsys = ; > - mutex-event-eof = - CMDQ_EVENT_MUTEX1_STREAM_EOF>; > - > + mediatek,gce-event-names = "rdma0_sof", > +"rsz0_sof"; > + mediatek,gce-events = < CMDQ_EVENT_MDP_RDMA0_SOF>, > + < CMDQ_EVENT_MDP_RSZ0_SOF>; > ... > };
