[PATCH 9/9] arm64: dts: marvell: add pinctrl support for Armada 7K/8K
Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs.
The CP master being different between Armada 7k and Armada 8k. This
commit introduces the intermediates files armada-70x0.dtsi and
armada-80x0.dtsi.
These new files will provide different compatible strings depending of
the SoC family. They will also be the location for the pinmux
configuration at the SoC level.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-7020.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-7040.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 53 ++-
arch/arm64/boot/dts/marvell/armada-8020.dtsi | 3 +-
arch/arm64/boot/dts/marvell/armada-8040.dtsi | 3 +-
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 60 -
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 4 +-
7 files changed, 121 insertions(+), 6 deletions(-)
create mode 100644 arch/arm64/boot/dts/marvell/armada-70x0.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/armada-80x0.dtsi
diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi
b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
index 975e73302753..4ab012991d9d 100644
--- a/arch/arm64/boot/dts/marvell/armada-7020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
@@ -46,7 +46,7 @@
*/
#include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-70x0.dtsi"
/ {
model = "Marvell Armada 7020";
diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi
b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
index 78d995d62707..cbe460b8fc00 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
@@ -46,7 +46,7 @@
*/
#include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-70x0.dtsi"
/ {
model = "Marvell Armada 7040";
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
new file mode 100644
index ..f6c22665d091
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 70x0 SoC
+ */
+
+#include "armada-cp110-master.dtsi"
+
+_syscon0 {
+ cpm_pinctrl: pinctrl {
+ compatible = "marvell,armada-7k-pinctrl";
+ };
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
index 7c08f1f28d9e..0ba0bc942598 100644
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
@@ -46,8 +46,7 @@
*/
#include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
+#include "armada-80x0.dtsi"
/ {
model = &q
[PATCH 9/9] arm64: dts: marvell: add pinctrl support for Armada 7K/8K
Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs.
The CP master being different between Armada 7k and Armada 8k. This
commit introduces the intermediates files armada-70x0.dtsi and
armada-80x0.dtsi.
These new files will provide different compatible strings depending of
the SoC family. They will also be the location for the pinmux
configuration at the SoC level.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-7020.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-7040.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 53 ++-
arch/arm64/boot/dts/marvell/armada-8020.dtsi | 3 +-
arch/arm64/boot/dts/marvell/armada-8040.dtsi | 3 +-
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 60 -
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 4 +-
7 files changed, 121 insertions(+), 6 deletions(-)
create mode 100644 arch/arm64/boot/dts/marvell/armada-70x0.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/armada-80x0.dtsi
diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi
b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
index 975e73302753..4ab012991d9d 100644
--- a/arch/arm64/boot/dts/marvell/armada-7020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
@@ -46,7 +46,7 @@
*/
#include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-70x0.dtsi"
/ {
model = "Marvell Armada 7020";
diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi
b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
index 78d995d62707..cbe460b8fc00 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
@@ -46,7 +46,7 @@
*/
#include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-70x0.dtsi"
/ {
model = "Marvell Armada 7040";
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
new file mode 100644
index ..f6c22665d091
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 70x0 SoC
+ */
+
+#include "armada-cp110-master.dtsi"
+
+_syscon0 {
+ cpm_pinctrl: pinctrl {
+ compatible = "marvell,armada-7k-pinctrl";
+ };
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
index 7c08f1f28d9e..0ba0bc942598 100644
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
@@ -46,8 +46,7 @@
*/
#include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
+#include "armada-80x0.dtsi"
/ {
model = "Marvell Armada 8020";
diff --git a/arc
[PATCH 1/9] MAINTAINERS: extend mvebu SoC entry with pinctrl drivers
There was no entry for the mvebu pinctrl drivers. As they are tightly linked to the SoCs and there is a lot of common code to support the various pinctrl of each SoCs, then add a new entry for the mvebu maintainers. Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index f7d568b8f133..42befcdec846 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1496,6 +1496,7 @@ F:arch/arm/boot/dts/armada* F: arch/arm/boot/dts/kirkwood* F: arch/arm64/boot/dts/marvell/armada* F: drivers/cpufreq/mvebu-cpufreq.c +F: drivers/pinctrl/mvebu/ F: arch/arm/configs/mvebu_*_defconfig ARM/Marvell Berlin SoC support -- git-series 0.9.1
[PATCH 1/9] MAINTAINERS: extend mvebu SoC entry with pinctrl drivers
There was no entry for the mvebu pinctrl drivers. As they are tightly linked to the SoCs and there is a lot of common code to support the various pinctrl of each SoCs, then add a new entry for the mvebu maintainers. Reviewed-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index f7d568b8f133..42befcdec846 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1496,6 +1496,7 @@ F:arch/arm/boot/dts/armada* F: arch/arm/boot/dts/kirkwood* F: arch/arm64/boot/dts/marvell/armada* F: drivers/cpufreq/mvebu-cpufreq.c +F: drivers/pinctrl/mvebu/ F: arch/arm/configs/mvebu_*_defconfig ARM/Marvell Berlin SoC support -- git-series 0.9.1
[PATCH 3/5] clk: mvebu: ap806: introduce a new binding
As for cp110, the initial intent when the binding of the ap806 system
controller was to have one flat node. The idea being that what is
currently a clock-only driver in drivers would become a MFD driver,
exposing the clock, GPIO and pinctrl functionality. However, after taking
a step back, this would lead to a messy binding. Indeed, a single node
would be a GPIO controller, clock controller, pinmux controller, and
more.
This patch adopts a more classical solution of a top-level syscon node
with sub-nodes for the individual devices. The main benefit will be to
have each functional block associated to its own sub-node where we can
put its own properties.
The introduction of the Armada 7K/8K is still in the early stage so the
plan is to remove the old binding. However, we don't want to break the
device tree compatibility for the few devices already in the field. For
this we still keep the support of the legacy compatible string with a big
warning in the kernel about updating the device tree.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt | 20
+++-
drivers/clk/mvebu/ap806-system-controller.c | 56
2 files changed, 59 insertions(+), 17 deletions(-)
diff --git
a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 3faab71dff9f..888c50e0d64f 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -7,6 +7,14 @@ registers giving access to numerous features: clocks,
pin-muxing and
many other SoC configuration items. This DT binding allows to describe
this system controller.
+For the top level node:
+ - compatible: must be: "syscon", "simple-mfd";
+ - reg: register area of the AP806 system controller
+
+Clocks:
+---
+
+
The Device Tree node representing the AP806 system controller provides
a number of clocks:
@@ -17,15 +25,17 @@ a number of clocks:
Required properties:
- - compatible: must be:
- "marvell,ap806-system-controller", "syscon"
- - reg: register area of the AP806 system controller
+ - compatible: must be: "marvell,ap806-clock"
- #clock-cells: must be set to 1
Example:
syscon: system-controller@6f4000 {
- compatible = "marvell,ap806-system-controller", "syscon";
- #clock-cells = <1>;
+ compatible = "syscon", "simple-mfd";
reg = <0x6f4000 0x1000>;
+
+ ap_clk: clock {
+ compatible = "marvell,ap806-clock";
+ #clock-cells = <1>;
+ };
};
diff --git a/drivers/clk/mvebu/ap806-system-controller.c
b/drivers/clk/mvebu/ap806-system-controller.c
index 95ae16e203ea..fa2fbd2cef4a 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -44,7 +44,8 @@ static char *ap806_unique_name(struct device *dev, struct
device_node *np,
(unsigned long long)addr, name);
}
-static int ap806_syscon_clk_probe(struct platform_device *pdev)
+static int ap806_syscon_common_probe(struct platform_device *pdev,
+struct device_node *syscon_node)
{
unsigned int freq_mode, cpuclk_freq;
const char *name, *fixedclk_name;
@@ -54,7 +55,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
u32 reg;
int ret;
- regmap = syscon_node_to_regmap(np);
+ regmap = syscon_node_to_regmap(syscon_node);
if (IS_ERR(regmap)) {
dev_err(dev, "cannot get regmap\n");
return PTR_ERR(regmap);
@@ -110,7 +111,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
cpuclk_freq *= 1000 * 1000;
/* CPU clocks depend on the Sample At Reset configuration */
- name = ap806_unique_name(dev, np, "cpu-cluster-0");
+ name = ap806_unique_name(dev, syscon_node, "cpu-cluster-0");
ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
0, cpuclk_freq);
if (IS_ERR(ap806_clks[0])) {
@@ -118,7 +119,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
goto fail0;
}
- name = ap806_unique_name(dev, np, "cpu-cluster-1");
+ name = ap806_unique_name(dev, syscon_node, "cpu-cluster-1");
ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
cpuclk_freq);
if (IS_ERR(ap806_c
[PATCH 3/5] clk: mvebu: ap806: introduce a new binding
As for cp110, the initial intent when the binding of the ap806 system
controller was to have one flat node. The idea being that what is
currently a clock-only driver in drivers would become a MFD driver,
exposing the clock, GPIO and pinctrl functionality. However, after taking
a step back, this would lead to a messy binding. Indeed, a single node
would be a GPIO controller, clock controller, pinmux controller, and
more.
This patch adopts a more classical solution of a top-level syscon node
with sub-nodes for the individual devices. The main benefit will be to
have each functional block associated to its own sub-node where we can
put its own properties.
The introduction of the Armada 7K/8K is still in the early stage so the
plan is to remove the old binding. However, we don't want to break the
device tree compatibility for the few devices already in the field. For
this we still keep the support of the legacy compatible string with a big
warning in the kernel about updating the device tree.
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt | 20
+++-
drivers/clk/mvebu/ap806-system-controller.c | 56
2 files changed, 59 insertions(+), 17 deletions(-)
diff --git
a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 3faab71dff9f..888c50e0d64f 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -7,6 +7,14 @@ registers giving access to numerous features: clocks,
pin-muxing and
many other SoC configuration items. This DT binding allows to describe
this system controller.
+For the top level node:
+ - compatible: must be: "syscon", "simple-mfd";
+ - reg: register area of the AP806 system controller
+
+Clocks:
+---
+
+
The Device Tree node representing the AP806 system controller provides
a number of clocks:
@@ -17,15 +25,17 @@ a number of clocks:
Required properties:
- - compatible: must be:
- "marvell,ap806-system-controller", "syscon"
- - reg: register area of the AP806 system controller
+ - compatible: must be: "marvell,ap806-clock"
- #clock-cells: must be set to 1
Example:
syscon: system-controller@6f4000 {
- compatible = "marvell,ap806-system-controller", "syscon";
- #clock-cells = <1>;
+ compatible = "syscon", "simple-mfd";
reg = <0x6f4000 0x1000>;
+
+ ap_clk: clock {
+ compatible = "marvell,ap806-clock";
+ #clock-cells = <1>;
+ };
};
diff --git a/drivers/clk/mvebu/ap806-system-controller.c
b/drivers/clk/mvebu/ap806-system-controller.c
index 95ae16e203ea..fa2fbd2cef4a 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -44,7 +44,8 @@ static char *ap806_unique_name(struct device *dev, struct
device_node *np,
(unsigned long long)addr, name);
}
-static int ap806_syscon_clk_probe(struct platform_device *pdev)
+static int ap806_syscon_common_probe(struct platform_device *pdev,
+struct device_node *syscon_node)
{
unsigned int freq_mode, cpuclk_freq;
const char *name, *fixedclk_name;
@@ -54,7 +55,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
u32 reg;
int ret;
- regmap = syscon_node_to_regmap(np);
+ regmap = syscon_node_to_regmap(syscon_node);
if (IS_ERR(regmap)) {
dev_err(dev, "cannot get regmap\n");
return PTR_ERR(regmap);
@@ -110,7 +111,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
cpuclk_freq *= 1000 * 1000;
/* CPU clocks depend on the Sample At Reset configuration */
- name = ap806_unique_name(dev, np, "cpu-cluster-0");
+ name = ap806_unique_name(dev, syscon_node, "cpu-cluster-0");
ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
0, cpuclk_freq);
if (IS_ERR(ap806_clks[0])) {
@@ -118,7 +119,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
goto fail0;
}
- name = ap806_unique_name(dev, np, "cpu-cluster-1");
+ name = ap806_unique_name(dev, syscon_node, "cpu-cluster-1");
ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
cpuclk_freq);
if (IS_ERR(ap806_clks[1])) {
@@ -127,7 +128,7 @@ static int
[PATCH 5/5] arm64: dts: marvell: use new binding for the system controller on ap806
The new binding for the system controller on ap806 moved the clock into a
subnode. This preliminary step will allow to add gpio and pinctrl
subnodes
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 0c25ec62a2a3..205037e3e7dc 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -193,7 +193,7 @@
#size-cells = <0>;
cell-index = <0>;
interrupts = ;
- clocks = <_syscon 3>;
+ clocks = <_clk 3>;
status = "disabled";
};
@@ -204,7 +204,7 @@
#size-cells = <0>;
interrupts = ;
timeout-ms = <1000>;
- clocks = <_syscon 3>;
+ clocks = <_clk 3>;
status = "disabled";
};
@@ -214,7 +214,7 @@
reg-shift = <2>;
interrupts = ;
reg-io-width = <1>;
- clocks = <_syscon 3>;
+ clocks = <_clk 3>;
status = "disabled";
};
@@ -224,7 +224,7 @@
reg-shift = <2>;
interrupts = ;
reg-io-width = <1>;
- clocks = <_syscon 3>;
+ clocks = <_clk 3>;
status = "disabled";
};
@@ -234,17 +234,20 @@
reg = <0x6e 0x300>;
interrupts = ;
clock-names = "core";
- clocks = <_syscon 4>;
+ clocks = <_clk 4>;
dma-coherent;
marvell,xenon-phy-slow-mode;
status = "disabled";
};
ap_syscon: system-controller@6f4000 {
- compatible = "marvell,ap806-system-controller",
-"syscon";
- #clock-cells = <1>;
+ compatible = "syscon", "simple-mfd";
reg = <0x6f4000 0x1000>;
+
+ ap_clk: clock {
+ compatible = "marvell,ap806-clock";
+ #clock-cells = <1>;
+ };
};
};
};
--
git-series 0.9.1
[PATCH 2/5] clk: mvebu: ap806: do not depend anymore of the *-clock-output-names
As it was done for the cp110, this patch modifies the way the clock names
are created. The name of each clock is now created by using its physical
address as a prefix (as it was done for the platform device
names). Thanks to this we have an automatic way to compute a unique name.
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt | 4
drivers/clk/mvebu/ap806-system-controller.c | 46
--
2 files changed, 24 insertions(+), 26 deletions(-)
diff --git
a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 8968371d84e2..3faab71dff9f 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -21,15 +21,11 @@ Required properties:
"marvell,ap806-system-controller", "syscon"
- reg: register area of the AP806 system controller
- #clock-cells: must be set to 1
- - clock-output-names: must be defined to:
-"ap-cpu-cluster-0", "ap-cpu-cluster-1", "ap-fixed", "ap-mss"
Example:
syscon: system-controller@6f4000 {
compatible = "marvell,ap806-system-controller", "syscon";
#clock-cells = <1>;
- clock-output-names = "ap-cpu-cluster-0", "ap-cpu-cluster-1",
-"ap-fixed", "ap-mss";
reg = <0x6f4000 0x1000>;
};
diff --git a/drivers/clk/mvebu/ap806-system-controller.c
b/drivers/clk/mvebu/ap806-system-controller.c
index b2666b5c944f..95ae16e203ea 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -32,6 +32,18 @@ static struct clk_onecell_data ap806_clk_data = {
.clk_num = AP806_CLK_NUM,
};
+static char *ap806_unique_name(struct device *dev, struct device_node *np,
+ char *name)
+{
+ const __be32 *reg;
+ u64 addr;
+
+ reg = of_get_property(np, "reg", NULL);
+ addr = of_translate_address(np, reg);
+ return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
+ (unsigned long long)addr, name);
+}
+
static int ap806_syscon_clk_probe(struct platform_device *pdev)
{
unsigned int freq_mode, cpuclk_freq;
@@ -98,8 +110,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
cpuclk_freq *= 1000 * 1000;
/* CPU clocks depend on the Sample At Reset configuration */
- of_property_read_string_index(np, "clock-output-names",
- 0, );
+ name = ap806_unique_name(dev, np, "cpu-cluster-0");
ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
0, cpuclk_freq);
if (IS_ERR(ap806_clks[0])) {
@@ -107,8 +118,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
goto fail0;
}
- of_property_read_string_index(np, "clock-output-names",
- 1, );
+ name = ap806_unique_name(dev, np, "cpu-cluster-1");
ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
cpuclk_freq);
if (IS_ERR(ap806_clks[1])) {
@@ -117,8 +127,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
}
/* Fixed clock is always 1200 Mhz */
- of_property_read_string_index(np, "clock-output-names",
- 2, _name);
+ fixedclk_name = ap806_unique_name(dev, np, "fixed");
ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
0, 1200 * 1000 * 1000);
if (IS_ERR(ap806_clks[2])) {
@@ -127,8 +136,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
}
/* MSS Clock is fixed clock divided by 6 */
- of_property_read_string_index(np, "clock-output-names",
- 3, );
+ name = ap806_unique_name(dev, np, "mss");
ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
0, 1, 6);
if (IS_ERR(ap806_clks[3])) {
@@ -136,20 +144,14 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
goto fail3;
}
- /* eMMC Clock is fixed clock divided by 3 */
- if (of_property_read_string_
[PATCH 5/5] arm64: dts: marvell: use new binding for the system controller on ap806
The new binding for the system controller on ap806 moved the clock into a
subnode. This preliminary step will allow to add gpio and pinctrl
subnodes
Reviewed-by: Thomas Petazzoni
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 0c25ec62a2a3..205037e3e7dc 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -193,7 +193,7 @@
#size-cells = <0>;
cell-index = <0>;
interrupts = ;
- clocks = <_syscon 3>;
+ clocks = <_clk 3>;
status = "disabled";
};
@@ -204,7 +204,7 @@
#size-cells = <0>;
interrupts = ;
timeout-ms = <1000>;
- clocks = <_syscon 3>;
+ clocks = <_clk 3>;
status = "disabled";
};
@@ -214,7 +214,7 @@
reg-shift = <2>;
interrupts = ;
reg-io-width = <1>;
- clocks = <_syscon 3>;
+ clocks = <_clk 3>;
status = "disabled";
};
@@ -224,7 +224,7 @@
reg-shift = <2>;
interrupts = ;
reg-io-width = <1>;
- clocks = <_syscon 3>;
+ clocks = <_clk 3>;
status = "disabled";
};
@@ -234,17 +234,20 @@
reg = <0x6e 0x300>;
interrupts = ;
clock-names = "core";
- clocks = <_syscon 4>;
+ clocks = <_clk 4>;
dma-coherent;
marvell,xenon-phy-slow-mode;
status = "disabled";
};
ap_syscon: system-controller@6f4000 {
- compatible = "marvell,ap806-system-controller",
-"syscon";
- #clock-cells = <1>;
+ compatible = "syscon", "simple-mfd";
reg = <0x6f4000 0x1000>;
+
+ ap_clk: clock {
+ compatible = "marvell,ap806-clock";
+ #clock-cells = <1>;
+ };
};
};
};
--
git-series 0.9.1
[PATCH 2/5] clk: mvebu: ap806: do not depend anymore of the *-clock-output-names
As it was done for the cp110, this patch modifies the way the clock names
are created. The name of each clock is now created by using its physical
address as a prefix (as it was done for the platform device
names). Thanks to this we have an automatic way to compute a unique name.
Reviewed-by: Thomas Petazzoni
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt | 4
drivers/clk/mvebu/ap806-system-controller.c | 46
--
2 files changed, 24 insertions(+), 26 deletions(-)
diff --git
a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 8968371d84e2..3faab71dff9f 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -21,15 +21,11 @@ Required properties:
"marvell,ap806-system-controller", "syscon"
- reg: register area of the AP806 system controller
- #clock-cells: must be set to 1
- - clock-output-names: must be defined to:
-"ap-cpu-cluster-0", "ap-cpu-cluster-1", "ap-fixed", "ap-mss"
Example:
syscon: system-controller@6f4000 {
compatible = "marvell,ap806-system-controller", "syscon";
#clock-cells = <1>;
- clock-output-names = "ap-cpu-cluster-0", "ap-cpu-cluster-1",
-"ap-fixed", "ap-mss";
reg = <0x6f4000 0x1000>;
};
diff --git a/drivers/clk/mvebu/ap806-system-controller.c
b/drivers/clk/mvebu/ap806-system-controller.c
index b2666b5c944f..95ae16e203ea 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -32,6 +32,18 @@ static struct clk_onecell_data ap806_clk_data = {
.clk_num = AP806_CLK_NUM,
};
+static char *ap806_unique_name(struct device *dev, struct device_node *np,
+ char *name)
+{
+ const __be32 *reg;
+ u64 addr;
+
+ reg = of_get_property(np, "reg", NULL);
+ addr = of_translate_address(np, reg);
+ return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
+ (unsigned long long)addr, name);
+}
+
static int ap806_syscon_clk_probe(struct platform_device *pdev)
{
unsigned int freq_mode, cpuclk_freq;
@@ -98,8 +110,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
cpuclk_freq *= 1000 * 1000;
/* CPU clocks depend on the Sample At Reset configuration */
- of_property_read_string_index(np, "clock-output-names",
- 0, );
+ name = ap806_unique_name(dev, np, "cpu-cluster-0");
ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
0, cpuclk_freq);
if (IS_ERR(ap806_clks[0])) {
@@ -107,8 +118,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
goto fail0;
}
- of_property_read_string_index(np, "clock-output-names",
- 1, );
+ name = ap806_unique_name(dev, np, "cpu-cluster-1");
ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
cpuclk_freq);
if (IS_ERR(ap806_clks[1])) {
@@ -117,8 +127,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
}
/* Fixed clock is always 1200 Mhz */
- of_property_read_string_index(np, "clock-output-names",
- 2, _name);
+ fixedclk_name = ap806_unique_name(dev, np, "fixed");
ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
0, 1200 * 1000 * 1000);
if (IS_ERR(ap806_clks[2])) {
@@ -127,8 +136,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
}
/* MSS Clock is fixed clock divided by 6 */
- of_property_read_string_index(np, "clock-output-names",
- 3, );
+ name = ap806_unique_name(dev, np, "mss");
ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
0, 1, 6);
if (IS_ERR(ap806_clks[3])) {
@@ -136,20 +144,14 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
goto fail3;
}
- /* eMMC Clock is fixed clock divided by 3 */
- if (of_property_read_string_index(np, "clock-output-names",
-
[PATCH 1/5] clk: mvebu: ap806: cosmetic improvement
Instead of using >dev all over the place, introduce a pointer
variable for it.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/clk/mvebu/ap806-system-controller.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/mvebu/ap806-system-controller.c
b/drivers/clk/mvebu/ap806-system-controller.c
index 8155baccc98e..b2666b5c944f 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -36,20 +36,21 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
{
unsigned int freq_mode, cpuclk_freq;
const char *name, *fixedclk_name;
- struct device_node *np = pdev->dev.of_node;
+ struct device *dev = >dev;
+ struct device_node *np = dev->of_node;
struct regmap *regmap;
u32 reg;
int ret;
regmap = syscon_node_to_regmap(np);
if (IS_ERR(regmap)) {
- dev_err(>dev, "cannot get regmap\n");
+ dev_err(dev, "cannot get regmap\n");
return PTR_ERR(regmap);
}
ret = regmap_read(regmap, AP806_SAR_REG, );
if (ret) {
- dev_err(>dev, "cannot read from regmap\n");
+ dev_err(dev, "cannot read from regmap\n");
return ret;
}
@@ -89,7 +90,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
cpuclk_freq = 600;
break;
default:
- dev_err(>dev, "invalid SAR value\n");
+ dev_err(dev, "invalid SAR value\n");
return -EINVAL;
}
@@ -99,7 +100,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
/* CPU clocks depend on the Sample At Reset configuration */
of_property_read_string_index(np, "clock-output-names",
0, );
- ap806_clks[0] = clk_register_fixed_rate(>dev, name, NULL,
+ ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
0, cpuclk_freq);
if (IS_ERR(ap806_clks[0])) {
ret = PTR_ERR(ap806_clks[0]);
@@ -108,7 +109,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
of_property_read_string_index(np, "clock-output-names",
1, );
- ap806_clks[1] = clk_register_fixed_rate(>dev, name, NULL, 0,
+ ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
cpuclk_freq);
if (IS_ERR(ap806_clks[1])) {
ret = PTR_ERR(ap806_clks[1]);
@@ -118,7 +119,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
/* Fixed clock is always 1200 Mhz */
of_property_read_string_index(np, "clock-output-names",
2, _name);
- ap806_clks[2] = clk_register_fixed_rate(>dev, fixedclk_name, NULL,
+ ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
0, 1200 * 1000 * 1000);
if (IS_ERR(ap806_clks[2])) {
ret = PTR_ERR(ap806_clks[2]);
--
git-series 0.9.1
[PATCH 4/5] arm64: dts: marvell: remove clock-output-names on ap806
The clock-output-names of the ap806-system-controller node are not used anymore, so remove them. Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 4 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index fe41bf9c301e..0c25ec62a2a3 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -244,10 +244,6 @@ compatible = "marvell,ap806-system-controller", "syscon"; #clock-cells = <1>; - clock-output-names = "ap-cpu-cluster-0", -"ap-cpu-cluster-1", -"ap-fixed", "ap-mss", -"ap-emmc"; reg = <0x6f4000 0x1000>; }; }; -- git-series 0.9.1
[PATCH 0/5] Improve ap806 clk support on Marvell Armada 7K/8K
Hi, This series modifies the device tree binding of the clock of the AP806 part that we find in the Marvell Armada 7K/8K SoCs. As for the CP110, we want to be able to ease the integration of new clocks without breaking the backward compatibility. It is done in patch 2. We also want to ease the integration of the pinctrl node in the device tree. It is the purpose of the patch 3. Here again the last two patches modify the device tree to take into account theses changes. They must be merged through the mvebu tree to avoid future conflict. In this series (as in the previous one for CP110), even if there is some change in the device tree binding we paid attention to the backward compatibility, and the driver can still work with the old device tree. Thanks, Gregory Gregory CLEMENT (5): clk: mvebu: ap806: cosmetic improvement clk: mvebu: ap806: do not depend anymore of the *-clock-output-names clk: mvebu: ap806: introduce a new binding arm64: dts: marvell: remove clock-output-names on ap806 arm64: dts: marvell: use new binding for the system controller on ap806 Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt | 24 ++-- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 23 +++ drivers/clk/mvebu/ap806-system-controller.c | 107 +++- 3 files changed, 97 insertions(+), 57 deletions(-) base-commit: 4139fcd6c66df1c3d3fa0a0a7cf7f8a8c601a16c -- git-series 0.9.1
[PATCH 1/5] clk: mvebu: ap806: cosmetic improvement
Instead of using >dev all over the place, introduce a pointer
variable for it.
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/ap806-system-controller.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/mvebu/ap806-system-controller.c
b/drivers/clk/mvebu/ap806-system-controller.c
index 8155baccc98e..b2666b5c944f 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -36,20 +36,21 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
{
unsigned int freq_mode, cpuclk_freq;
const char *name, *fixedclk_name;
- struct device_node *np = pdev->dev.of_node;
+ struct device *dev = >dev;
+ struct device_node *np = dev->of_node;
struct regmap *regmap;
u32 reg;
int ret;
regmap = syscon_node_to_regmap(np);
if (IS_ERR(regmap)) {
- dev_err(>dev, "cannot get regmap\n");
+ dev_err(dev, "cannot get regmap\n");
return PTR_ERR(regmap);
}
ret = regmap_read(regmap, AP806_SAR_REG, );
if (ret) {
- dev_err(>dev, "cannot read from regmap\n");
+ dev_err(dev, "cannot read from regmap\n");
return ret;
}
@@ -89,7 +90,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
cpuclk_freq = 600;
break;
default:
- dev_err(>dev, "invalid SAR value\n");
+ dev_err(dev, "invalid SAR value\n");
return -EINVAL;
}
@@ -99,7 +100,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
/* CPU clocks depend on the Sample At Reset configuration */
of_property_read_string_index(np, "clock-output-names",
0, );
- ap806_clks[0] = clk_register_fixed_rate(>dev, name, NULL,
+ ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
0, cpuclk_freq);
if (IS_ERR(ap806_clks[0])) {
ret = PTR_ERR(ap806_clks[0]);
@@ -108,7 +109,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
of_property_read_string_index(np, "clock-output-names",
1, );
- ap806_clks[1] = clk_register_fixed_rate(>dev, name, NULL, 0,
+ ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
cpuclk_freq);
if (IS_ERR(ap806_clks[1])) {
ret = PTR_ERR(ap806_clks[1]);
@@ -118,7 +119,7 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
/* Fixed clock is always 1200 Mhz */
of_property_read_string_index(np, "clock-output-names",
2, _name);
- ap806_clks[2] = clk_register_fixed_rate(>dev, fixedclk_name, NULL,
+ ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
0, 1200 * 1000 * 1000);
if (IS_ERR(ap806_clks[2])) {
ret = PTR_ERR(ap806_clks[2]);
--
git-series 0.9.1
[PATCH 4/5] arm64: dts: marvell: remove clock-output-names on ap806
The clock-output-names of the ap806-system-controller node are not used anymore, so remove them. Reviewed-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 4 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index fe41bf9c301e..0c25ec62a2a3 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -244,10 +244,6 @@ compatible = "marvell,ap806-system-controller", "syscon"; #clock-cells = <1>; - clock-output-names = "ap-cpu-cluster-0", -"ap-cpu-cluster-1", -"ap-fixed", "ap-mss", -"ap-emmc"; reg = <0x6f4000 0x1000>; }; }; -- git-series 0.9.1
[PATCH 0/5] Improve ap806 clk support on Marvell Armada 7K/8K
Hi, This series modifies the device tree binding of the clock of the AP806 part that we find in the Marvell Armada 7K/8K SoCs. As for the CP110, we want to be able to ease the integration of new clocks without breaking the backward compatibility. It is done in patch 2. We also want to ease the integration of the pinctrl node in the device tree. It is the purpose of the patch 3. Here again the last two patches modify the device tree to take into account theses changes. They must be merged through the mvebu tree to avoid future conflict. In this series (as in the previous one for CP110), even if there is some change in the device tree binding we paid attention to the backward compatibility, and the driver can still work with the old device tree. Thanks, Gregory Gregory CLEMENT (5): clk: mvebu: ap806: cosmetic improvement clk: mvebu: ap806: do not depend anymore of the *-clock-output-names clk: mvebu: ap806: introduce a new binding arm64: dts: marvell: remove clock-output-names on ap806 arm64: dts: marvell: use new binding for the system controller on ap806 Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt | 24 ++-- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 23 +++ drivers/clk/mvebu/ap806-system-controller.c | 107 +++- 3 files changed, 97 insertions(+), 57 deletions(-) base-commit: 4139fcd6c66df1c3d3fa0a0a7cf7f8a8c601a16c -- git-series 0.9.1
[PATCH 5/7] clk: mvebu: cp110: add sdio clock to cp-110 system controller
From: Konstantin Porotchkin <kos...@marvell.com>
This commit updates the CP110 system controller driver to add the
definition for a missing clock.
The SDIO clock is dedicated driving the SDHCI interface and its frequency
is 400MHz (2/5 of PLL source clock).
The SDIO interface should be bound to this clock and not the core clock
as in the older code.
Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while
the HW really supports up to 400 Mhz.
This patch also fixes the NAND clock relationship documentation.
Signed-off-by: Konstantin Porotchkin <kos...@marvell.com>
[gregory.clem...@free-electrons.com:
- use sdio instead of emmc to name the clock
- update binding documentation]
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
---
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt |
1 +
drivers/clk/mvebu/cp110-system-controller.c|
28 +++-
2 files changed, 24 insertions(+), 5 deletions(-)
diff --git
a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
index 139e46cc6786..e0b9ef5d3dde 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -34,6 +34,7 @@ The following clocks are available:
- 0 2 EIP
- 0 3 Core
- 0 4 NAND core
+ - 0 5 SDIO core
- Gatable clocks
- 1 0 Audio
- 1 1 Comm Unit
diff --git a/drivers/clk/mvebu/cp110-system-controller.c
b/drivers/clk/mvebu/cp110-system-controller.c
index ecbcae321424..8be7ae25c7eb 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -11,15 +11,16 @@
*/
/*
- * CP110 has 5 core clocks:
+ * CP110 has 6 core clocks:
*
* - APLL (1 Ghz)
*- PPv2 core (1/3 APLL)
*- EIP(1/2 APLL)
- * - Core (1/2 EIP)
+ * - Core (1/2 EIP)
+ *- SDIO (2/5 APLL)
*
* - NAND clock, which is either:
- *- Equal to the core clock
+ *- Equal to SDIO clock
*- 2/5 APLL
*
* CP110 has 32 gatable clocks, for the various peripherals in the
@@ -46,7 +47,7 @@ enum {
CP110_CLK_TYPE_GATABLE,
};
-#define CP110_MAX_CORE_CLOCKS 5
+#define CP110_MAX_CORE_CLOCKS 6
#define CP110_MAX_GATABLE_CLOCKS 32
#define CP110_CLK_NUM \
@@ -57,6 +58,7 @@ enum {
#define CP110_CORE_EIP 2
#define CP110_CORE_CORE3
#define CP110_CORE_NAND4
+#define CP110_CORE_SDIO5
/* A number of gatable clocks need special handling */
#define CP110_GATE_AUDIO 0
@@ -235,7 +237,8 @@ static int cp110_syscon_common_probe(struct platform_device
*pdev,
struct regmap *regmap;
struct device *dev = >dev;
struct device_node *np = dev->of_node;
- const char *ppv2_name, *apll_name, *core_name, *eip_name, *nand_name;
+ const char *ppv2_name, *apll_name, *core_name, *eip_name, *nand_name,
+ *sdio_name;
struct clk_hw_onecell_data *cp110_clk_data;
struct clk_hw *hw, **cp110_clks;
u32 nand_clk_ctrl;
@@ -315,6 +318,17 @@ static int cp110_syscon_common_probe(struct
platform_device *pdev,
cp110_clks[CP110_CORE_NAND] = hw;
+ /* SDIO clock is APLL/2.5 */
+ sdio_name = cp110_unique_name(dev, syscon_node, "sdio-core");
+ hw = clk_hw_register_fixed_factor(NULL, sdio_name,
+ apll_name, 0, 2, 5);
+ if (IS_ERR(hw)) {
+ ret = PTR_ERR(hw);
+ goto fail_sdio;
+ }
+
+ cp110_clks[CP110_CORE_SDIO] = hw;
+
/* create the unique name for all the gate clocks */
for (i = 0; i < ARRAY_SIZE(gate_base_names); i++)
gate_name[i] = cp110_unique_name(dev, syscon_node,
@@ -344,6 +358,8 @@ static int cp110_syscon_common_probe(struct platform_device
*pdev,
parent = ppv2_name;
break;
case CP110_GATE_SDIO:
+ parent = sdio_name;
+ break;
case CP110_GATE_GOP_DP:
parent = gate_name[CP110_GATE_GOP];
break;
@@ -391,6 +407,8 @@ static int cp110_syscon_common_probe(struct platform_device
*pdev,
cp110_unregister_gate(hw);
}
+ clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_SDIO]);
+fail_sdio:
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
fail_nand:
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
--
git-series 0.9.1
[PATCH 5/7] clk: mvebu: cp110: add sdio clock to cp-110 system controller
From: Konstantin Porotchkin
This commit updates the CP110 system controller driver to add the
definition for a missing clock.
The SDIO clock is dedicated driving the SDHCI interface and its frequency
is 400MHz (2/5 of PLL source clock).
The SDIO interface should be bound to this clock and not the core clock
as in the older code.
Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while
the HW really supports up to 400 Mhz.
This patch also fixes the NAND clock relationship documentation.
Signed-off-by: Konstantin Porotchkin
[gregory.clem...@free-electrons.com:
- use sdio instead of emmc to name the clock
- update binding documentation]
Signed-off-by: Gregory CLEMENT
Reviewed-by: Thomas Petazzoni
---
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt |
1 +
drivers/clk/mvebu/cp110-system-controller.c|
28 +++-
2 files changed, 24 insertions(+), 5 deletions(-)
diff --git
a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
index 139e46cc6786..e0b9ef5d3dde 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -34,6 +34,7 @@ The following clocks are available:
- 0 2 EIP
- 0 3 Core
- 0 4 NAND core
+ - 0 5 SDIO core
- Gatable clocks
- 1 0 Audio
- 1 1 Comm Unit
diff --git a/drivers/clk/mvebu/cp110-system-controller.c
b/drivers/clk/mvebu/cp110-system-controller.c
index ecbcae321424..8be7ae25c7eb 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -11,15 +11,16 @@
*/
/*
- * CP110 has 5 core clocks:
+ * CP110 has 6 core clocks:
*
* - APLL (1 Ghz)
*- PPv2 core (1/3 APLL)
*- EIP(1/2 APLL)
- * - Core (1/2 EIP)
+ * - Core (1/2 EIP)
+ *- SDIO (2/5 APLL)
*
* - NAND clock, which is either:
- *- Equal to the core clock
+ *- Equal to SDIO clock
*- 2/5 APLL
*
* CP110 has 32 gatable clocks, for the various peripherals in the
@@ -46,7 +47,7 @@ enum {
CP110_CLK_TYPE_GATABLE,
};
-#define CP110_MAX_CORE_CLOCKS 5
+#define CP110_MAX_CORE_CLOCKS 6
#define CP110_MAX_GATABLE_CLOCKS 32
#define CP110_CLK_NUM \
@@ -57,6 +58,7 @@ enum {
#define CP110_CORE_EIP 2
#define CP110_CORE_CORE3
#define CP110_CORE_NAND4
+#define CP110_CORE_SDIO5
/* A number of gatable clocks need special handling */
#define CP110_GATE_AUDIO 0
@@ -235,7 +237,8 @@ static int cp110_syscon_common_probe(struct platform_device
*pdev,
struct regmap *regmap;
struct device *dev = >dev;
struct device_node *np = dev->of_node;
- const char *ppv2_name, *apll_name, *core_name, *eip_name, *nand_name;
+ const char *ppv2_name, *apll_name, *core_name, *eip_name, *nand_name,
+ *sdio_name;
struct clk_hw_onecell_data *cp110_clk_data;
struct clk_hw *hw, **cp110_clks;
u32 nand_clk_ctrl;
@@ -315,6 +318,17 @@ static int cp110_syscon_common_probe(struct
platform_device *pdev,
cp110_clks[CP110_CORE_NAND] = hw;
+ /* SDIO clock is APLL/2.5 */
+ sdio_name = cp110_unique_name(dev, syscon_node, "sdio-core");
+ hw = clk_hw_register_fixed_factor(NULL, sdio_name,
+ apll_name, 0, 2, 5);
+ if (IS_ERR(hw)) {
+ ret = PTR_ERR(hw);
+ goto fail_sdio;
+ }
+
+ cp110_clks[CP110_CORE_SDIO] = hw;
+
/* create the unique name for all the gate clocks */
for (i = 0; i < ARRAY_SIZE(gate_base_names); i++)
gate_name[i] = cp110_unique_name(dev, syscon_node,
@@ -344,6 +358,8 @@ static int cp110_syscon_common_probe(struct platform_device
*pdev,
parent = ppv2_name;
break;
case CP110_GATE_SDIO:
+ parent = sdio_name;
+ break;
case CP110_GATE_GOP_DP:
parent = gate_name[CP110_GATE_GOP];
break;
@@ -391,6 +407,8 @@ static int cp110_syscon_common_probe(struct platform_device
*pdev,
cp110_unregister_gate(hw);
}
+ clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_SDIO]);
+fail_sdio:
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
fail_nand:
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
--
git-series 0.9.1
[PATCH 4/7] clk: mvebu: cp110: introduce a new binding
The initial intent when the binding of the cp110 system controller was to
have one flat node. The idea being that what is currently a clock-only
driver in drivers would become a MFD driver, exposing the clock, GPIO and
pinctrl functionality. However, after taking a step back, this would lead
to a messy binding. Indeed, a single node would be a GPIO controller,
clock controller, pinmux controller, and more.
This patch adopts a more classical solution of a top-level syscon node
with sub-nodes for the individual devices. The main benefit will be to
have each functional block associated to its own sub-node where we can
put its own properties.
The introduction of the Armada 7K/8K is still in the early stage so the
plan is to remove the old binding. However, we don't want to break the
device tree compatibility for the few devices already in the field. For
this we still keep the support of the legacy compatible string with a big
warning in the kernel about updating the device tree.
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt |
18 ++
drivers/clk/mvebu/cp110-system-controller.c|
63 ---
2 files changed, 62 insertions(+), 19 deletions(-)
diff --git
a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
index 47f1cf800e25..139e46cc6786 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -7,6 +7,13 @@ Controller 0 and System Controller 1. This Device Tree binding
allows
to describe the first system controller, which provides registers to
configure various aspects of the SoC.
+For the top level node:
+ - compatible: must be: "syscon", "simple-mfd";
+ - reg: register area of the CP110 system controller 0
+
+Clocks:
+---
+
The Device Tree node representing this System Controller 0 provides a
number of clocks:
@@ -56,14 +63,17 @@ The following clocks are available:
Required properties:
- compatible: must be:
- "marvell,cp110-system-controller0", "syscon";
- - reg: register area of the CP110 system controller 0
+ "marvell,cp110-clock"
- #clock-cells: must be set to 2
Example:
cpm_syscon0: system-controller@44 {
- compatible = "marvell,cp110-system-controller0", "syscon";
+ compatible = "syscon", "simple-mfd";
reg = <0x44 0x1000>;
- #clock-cells = <2>;
+
+ cpm_clk: clock {
+ compatible = "marvell,cp110-clock";
+ #clock-cells = <2>;
+ };
};
diff --git a/drivers/clk/mvebu/cp110-system-controller.c
b/drivers/clk/mvebu/cp110-system-controller.c
index c7df8a69ed9a..ecbcae321424 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -213,9 +213,9 @@ static struct clk_hw *cp110_of_clk_get(struct
of_phandle_args *clkspec,
return ERR_PTR(-EINVAL);
}
-static char *cp110_unique_name(struct device *dev, const char *name)
+static char *cp110_unique_name(struct device *dev, struct device_node *np,
+ const char *name)
{
- struct device_node *np = dev->of_node;
const __be32 *reg;
u64 addr;
@@ -229,7 +229,8 @@ static char *cp110_unique_name(struct device *dev, const
char *name)
(unsigned long long)addr, name);
}
-static int cp110_syscon_clk_probe(struct platform_device *pdev)
+static int cp110_syscon_common_probe(struct platform_device *pdev,
+struct device_node *syscon_node)
{
struct regmap *regmap;
struct device *dev = >dev;
@@ -241,7 +242,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
int i, ret;
char *gate_name[ARRAY_SIZE(gate_base_names)];
- regmap = syscon_node_to_regmap(np);
+ regmap = syscon_node_to_regmap(syscon_node);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
@@ -260,7 +261,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
cp110_clk_data->num = CP110_CLK_NUM;
/* Register the APLL which is the root of the hw tree */
- apll_name = cp110_unique_name(dev, "apll");
+ apll_name = cp110_unique_name(dev, syscon_node, "apll");
hw = clk_hw_register_fixed_rate(NULL, apll_name, NULL, 0,
1000 * 1000 * 1000);
if
[PATCH 6/7] arm64: dts: marvell: remove *-clock-output-names on cp110
The *-clock-output-names of the cp110-system-controller0 node are not
used anymore, so remove them.
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 13 +-
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 13 +-
2 files changed, 26 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 59259270964c..a0f57a8e5dcb 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -101,19 +101,6 @@
"syscon";
reg = <0x44 0x1000>;
#clock-cells = <2>;
- core-clock-output-names =
- "cpm-apll", "cpm-ppv2-core", "cpm-eip",
- "cpm-core", "cpm-nand-core";
- gate-clock-output-names =
- "cpm-audio", "cpm-communit", "cpm-nand",
- "cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
- "cpm-mg-core", "cpm-xor1", "cpm-xor0",
- "cpm-gop-dp", "none", "cpm-pcie_x10",
- "cpm-pcie_x11", "cpm-pcie_x4",
"cpm-pcie-xor",
- "cpm-sata", "cpm-sata-usb", "cpm-main",
- "cpm-gop", "none", "none",
- "cpm-slow-io", "cpm-usb3h0",
"cpm-usb3h1",
- "cpm-usb3dev", "cpm-eip150",
"cpm-eip197";
};
cpm_rtc: rtc@284000 {
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 046d3fe53cda..9584bc8d8b3f 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -108,19 +108,6 @@
"syscon";
reg = <0x44 0x1000>;
#clock-cells = <2>;
- core-clock-output-names =
- "cps-apll", "cps-ppv2-core", "cps-eip",
- "cps-core", "cps-nand-core";
- gate-clock-output-names =
- "cps-audio", "cps-communit", "cps-nand",
- "cps-ppv2", "cps-sdio", "cps-mg-domain",
- "cps-mg-core", "cps-xor1", "cps-xor0",
- "cps-gop-dp", "none", "cps-pcie_x10",
- "cps-pcie_x11", "cps-pcie_x4",
"cps-pcie-xor",
- "cps-sata", "cps-sata-usb", "cps-main",
- "cps-gop", "none", "none",
- "cps-slow-io", "cps-usb3h0",
"cps-usb3h1",
- "cps-usb3dev", "cps-eip150",
"cps-eip197";
};
cps_sata0: sata@54 {
--
git-series 0.9.1
[PATCH 4/7] clk: mvebu: cp110: introduce a new binding
The initial intent when the binding of the cp110 system controller was to
have one flat node. The idea being that what is currently a clock-only
driver in drivers would become a MFD driver, exposing the clock, GPIO and
pinctrl functionality. However, after taking a step back, this would lead
to a messy binding. Indeed, a single node would be a GPIO controller,
clock controller, pinmux controller, and more.
This patch adopts a more classical solution of a top-level syscon node
with sub-nodes for the individual devices. The main benefit will be to
have each functional block associated to its own sub-node where we can
put its own properties.
The introduction of the Armada 7K/8K is still in the early stage so the
plan is to remove the old binding. However, we don't want to break the
device tree compatibility for the few devices already in the field. For
this we still keep the support of the legacy compatible string with a big
warning in the kernel about updating the device tree.
Reviewed-by: Thomas Petazzoni
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt |
18 ++
drivers/clk/mvebu/cp110-system-controller.c|
63 ---
2 files changed, 62 insertions(+), 19 deletions(-)
diff --git
a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
index 47f1cf800e25..139e46cc6786 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -7,6 +7,13 @@ Controller 0 and System Controller 1. This Device Tree binding
allows
to describe the first system controller, which provides registers to
configure various aspects of the SoC.
+For the top level node:
+ - compatible: must be: "syscon", "simple-mfd";
+ - reg: register area of the CP110 system controller 0
+
+Clocks:
+---
+
The Device Tree node representing this System Controller 0 provides a
number of clocks:
@@ -56,14 +63,17 @@ The following clocks are available:
Required properties:
- compatible: must be:
- "marvell,cp110-system-controller0", "syscon";
- - reg: register area of the CP110 system controller 0
+ "marvell,cp110-clock"
- #clock-cells: must be set to 2
Example:
cpm_syscon0: system-controller@44 {
- compatible = "marvell,cp110-system-controller0", "syscon";
+ compatible = "syscon", "simple-mfd";
reg = <0x44 0x1000>;
- #clock-cells = <2>;
+
+ cpm_clk: clock {
+ compatible = "marvell,cp110-clock";
+ #clock-cells = <2>;
+ };
};
diff --git a/drivers/clk/mvebu/cp110-system-controller.c
b/drivers/clk/mvebu/cp110-system-controller.c
index c7df8a69ed9a..ecbcae321424 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -213,9 +213,9 @@ static struct clk_hw *cp110_of_clk_get(struct
of_phandle_args *clkspec,
return ERR_PTR(-EINVAL);
}
-static char *cp110_unique_name(struct device *dev, const char *name)
+static char *cp110_unique_name(struct device *dev, struct device_node *np,
+ const char *name)
{
- struct device_node *np = dev->of_node;
const __be32 *reg;
u64 addr;
@@ -229,7 +229,8 @@ static char *cp110_unique_name(struct device *dev, const
char *name)
(unsigned long long)addr, name);
}
-static int cp110_syscon_clk_probe(struct platform_device *pdev)
+static int cp110_syscon_common_probe(struct platform_device *pdev,
+struct device_node *syscon_node)
{
struct regmap *regmap;
struct device *dev = >dev;
@@ -241,7 +242,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
int i, ret;
char *gate_name[ARRAY_SIZE(gate_base_names)];
- regmap = syscon_node_to_regmap(np);
+ regmap = syscon_node_to_regmap(syscon_node);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
@@ -260,7 +261,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
cp110_clk_data->num = CP110_CLK_NUM;
/* Register the APLL which is the root of the hw tree */
- apll_name = cp110_unique_name(dev, "apll");
+ apll_name = cp110_unique_name(dev, syscon_node, "apll");
hw = clk_hw_register_fixed_rate(NULL, apll_name, NULL, 0,
1000 * 1000 * 1000);
if (IS_ERR(hw)) {
@@ -271,7 +272,7 @@ static int cp110_syscon_clk_probe(struct pla
[PATCH 6/7] arm64: dts: marvell: remove *-clock-output-names on cp110
The *-clock-output-names of the cp110-system-controller0 node are not
used anymore, so remove them.
Reviewed-by: Thomas Petazzoni
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 13 +-
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 13 +-
2 files changed, 26 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 59259270964c..a0f57a8e5dcb 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -101,19 +101,6 @@
"syscon";
reg = <0x44 0x1000>;
#clock-cells = <2>;
- core-clock-output-names =
- "cpm-apll", "cpm-ppv2-core", "cpm-eip",
- "cpm-core", "cpm-nand-core";
- gate-clock-output-names =
- "cpm-audio", "cpm-communit", "cpm-nand",
- "cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
- "cpm-mg-core", "cpm-xor1", "cpm-xor0",
- "cpm-gop-dp", "none", "cpm-pcie_x10",
- "cpm-pcie_x11", "cpm-pcie_x4",
"cpm-pcie-xor",
- "cpm-sata", "cpm-sata-usb", "cpm-main",
- "cpm-gop", "none", "none",
- "cpm-slow-io", "cpm-usb3h0",
"cpm-usb3h1",
- "cpm-usb3dev", "cpm-eip150",
"cpm-eip197";
};
cpm_rtc: rtc@284000 {
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 046d3fe53cda..9584bc8d8b3f 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -108,19 +108,6 @@
"syscon";
reg = <0x44 0x1000>;
#clock-cells = <2>;
- core-clock-output-names =
- "cps-apll", "cps-ppv2-core", "cps-eip",
- "cps-core", "cps-nand-core";
- gate-clock-output-names =
- "cps-audio", "cps-communit", "cps-nand",
- "cps-ppv2", "cps-sdio", "cps-mg-domain",
- "cps-mg-core", "cps-xor1", "cps-xor0",
- "cps-gop-dp", "none", "cps-pcie_x10",
- "cps-pcie_x11", "cps-pcie_x4",
"cps-pcie-xor",
- "cps-sata", "cps-sata-usb", "cps-main",
- "cps-gop", "none", "none",
- "cps-slow-io", "cps-usb3h0",
"cps-usb3h1",
- "cps-usb3dev", "cps-eip150",
"cps-eip197";
};
cps_sata0: sata@54 {
--
git-series 0.9.1
[PATCH 7/7] arm64: dts: marvell: use new binding for the system controller on cp110
The new binding for the system controller on cp110 moved the clock
controller into a subnode. This preliminary step will allow to add gpio
and pinctrl subnodes.
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 41 ++---
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 35 +--
2 files changed, 41 insertions(+), 35 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index a0f57a8e5dcb..96a4ff75b3b0 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -62,7 +62,7 @@
cpm_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x10>, <0x129000 0xb000>;
- clocks = <_syscon0 1 3>, <_syscon0 1
9>, <_syscon0 1 5>;
+ clocks = <_clk 1 3>, <_clk 1 9>,
<_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
status = "disabled";
dma-coherent;
@@ -97,10 +97,13 @@
};
cpm_syscon0: system-controller@44 {
- compatible = "marvell,cp110-system-controller0",
-"syscon";
+ compatible = "syscon", "simple-mfd";
reg = <0x44 0x1000>;
- #clock-cells = <2>;
+
+ cpm_clk: clock {
+ compatible = "marvell,cp110-clock";
+ #clock-cells = <2>;
+ };
};
cpm_rtc: rtc@284000 {
@@ -115,7 +118,7 @@
"generic-ahci";
reg = <0x54 0x3>;
interrupts = ;
- clocks = <_syscon0 1 15>;
+ clocks = <_clk 1 15>;
status = "disabled";
};
@@ -125,7 +128,7 @@
reg = <0x50 0x4000>;
dma-coherent;
interrupts = ;
- clocks = <_syscon0 1 22>;
+ clocks = <_clk 1 22>;
status = "disabled";
};
@@ -135,7 +138,7 @@
reg = <0x51 0x4000>;
dma-coherent;
interrupts = ;
- clocks = <_syscon0 1 23>;
+ clocks = <_clk 1 23>;
status = "disabled";
};
@@ -145,7 +148,7 @@
<0x6b 0x1000>;
dma-coherent;
msi-parent = <_v2m0>;
- clocks = <_syscon0 1 8>;
+ clocks = <_clk 1 8>;
};
cpm_xor1: xor@6c {
@@ -154,7 +157,7 @@
<0x6d 0x1000>;
dma-coherent;
msi-parent = <_v2m0>;
- clocks = <_syscon0 1 7>;
+ clocks = <_clk 1 7>;
};
cpm_spi0: spi@700600 {
@@ -163,7 +166,7 @@
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <1>;
- clocks = <_syscon0 1 21>;
+ clocks = <_clk 1 21>;
status = "disabled";
};
@@ -173,7 +176,7 @@
#address-cells = <1>;
#size-cells = <0>;
cell-index = <2>;
- clocks = <_syscon0 1 21>;
+ clocks = <_clk 1 21>;
[PATCH 0/7] Improve cp110 clk support on Marvell Armada 7K/8K
Hi, We got more information about the clock controllers and the clock tree of the CP110 part that we find in the Marvell Armada 7K/8K SoCs. The clock tree needs to be fixed, indeed the GOP clock is only the clock for the GOIP and not for the SDIO, it is fixed in the first patch. The second patch does a small improve of the code itself. The purpose of the third patch is to have an easier way to add new clocks without breaking the backward compatibility. Indeed, we expect to continue to have new update on the datasheet and this patch will allow integrating this change easier and faster. The forth patch is needed to ease the integration of the pinctrl node in the device tree. The fifth patch adds a new clock for the SDIO, it also fixes the clock tree. The last two patches modify the device tree to take into account theses changes. They must be merged through the mvebu tree to avoid future conflict. In this series, even if there is some change in the device tree binding, we paid attention to the backward compatibility, and the driver can still work with the old device tree. Thanks, Gregory Gregory CLEMENT (6): clk: mvebu: cp110 fix name of the GOP gate clock clk: mvebu: cp110: make failure labels more meaningful clk: mvebu: cp110: do not depend anymore of the *-clock-output-names clk: mvebu: cp110: introduce a new binding arm64: dts: marvell: remove *-clock-output-names on cp110 arm64: dts: marvell: use new binding for the system controller on cp110 Konstantin Porotchkin (1): clk: mvebu: cp110: add sdio clock to cp-110 system controller Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 35 +--- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 54 +++ arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi| 48 ++--- drivers/clk/mvebu/cp110-system-controller.c| 202 +--- 4 files changed, 196 insertions(+), 143 deletions(-) base-commit: 2ea659a9ef488125eb46da6eb571de5eae5c43f6 -- git-series 0.9.1
[PATCH 7/7] arm64: dts: marvell: use new binding for the system controller on cp110
The new binding for the system controller on cp110 moved the clock
controller into a subnode. This preliminary step will allow to add gpio
and pinctrl subnodes.
Reviewed-by: Thomas Petazzoni
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 41 ++---
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 35 +--
2 files changed, 41 insertions(+), 35 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index a0f57a8e5dcb..96a4ff75b3b0 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -62,7 +62,7 @@
cpm_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x10>, <0x129000 0xb000>;
- clocks = <_syscon0 1 3>, <_syscon0 1
9>, <_syscon0 1 5>;
+ clocks = <_clk 1 3>, <_clk 1 9>,
<_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
status = "disabled";
dma-coherent;
@@ -97,10 +97,13 @@
};
cpm_syscon0: system-controller@44 {
- compatible = "marvell,cp110-system-controller0",
-"syscon";
+ compatible = "syscon", "simple-mfd";
reg = <0x44 0x1000>;
- #clock-cells = <2>;
+
+ cpm_clk: clock {
+ compatible = "marvell,cp110-clock";
+ #clock-cells = <2>;
+ };
};
cpm_rtc: rtc@284000 {
@@ -115,7 +118,7 @@
"generic-ahci";
reg = <0x54 0x3>;
interrupts = ;
- clocks = <_syscon0 1 15>;
+ clocks = <_clk 1 15>;
status = "disabled";
};
@@ -125,7 +128,7 @@
reg = <0x50 0x4000>;
dma-coherent;
interrupts = ;
- clocks = <_syscon0 1 22>;
+ clocks = <_clk 1 22>;
status = "disabled";
};
@@ -135,7 +138,7 @@
reg = <0x51 0x4000>;
dma-coherent;
interrupts = ;
- clocks = <_syscon0 1 23>;
+ clocks = <_clk 1 23>;
status = "disabled";
};
@@ -145,7 +148,7 @@
<0x6b 0x1000>;
dma-coherent;
msi-parent = <_v2m0>;
- clocks = <_syscon0 1 8>;
+ clocks = <_clk 1 8>;
};
cpm_xor1: xor@6c {
@@ -154,7 +157,7 @@
<0x6d 0x1000>;
dma-coherent;
msi-parent = <_v2m0>;
- clocks = <_syscon0 1 7>;
+ clocks = <_clk 1 7>;
};
cpm_spi0: spi@700600 {
@@ -163,7 +166,7 @@
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <1>;
- clocks = <_syscon0 1 21>;
+ clocks = <_clk 1 21>;
status = "disabled";
};
@@ -173,7 +176,7 @@
#address-cells = <1>;
#size-cells = <0>;
cell-index = <2>;
- clocks = <_syscon0 1 21>;
+ clocks = <_clk 1 21>;
status = "disabled";
};
@@ -183,7 +186,7 @@
[PATCH 0/7] Improve cp110 clk support on Marvell Armada 7K/8K
Hi, We got more information about the clock controllers and the clock tree of the CP110 part that we find in the Marvell Armada 7K/8K SoCs. The clock tree needs to be fixed, indeed the GOP clock is only the clock for the GOIP and not for the SDIO, it is fixed in the first patch. The second patch does a small improve of the code itself. The purpose of the third patch is to have an easier way to add new clocks without breaking the backward compatibility. Indeed, we expect to continue to have new update on the datasheet and this patch will allow integrating this change easier and faster. The forth patch is needed to ease the integration of the pinctrl node in the device tree. The fifth patch adds a new clock for the SDIO, it also fixes the clock tree. The last two patches modify the device tree to take into account theses changes. They must be merged through the mvebu tree to avoid future conflict. In this series, even if there is some change in the device tree binding, we paid attention to the backward compatibility, and the driver can still work with the old device tree. Thanks, Gregory Gregory CLEMENT (6): clk: mvebu: cp110 fix name of the GOP gate clock clk: mvebu: cp110: make failure labels more meaningful clk: mvebu: cp110: do not depend anymore of the *-clock-output-names clk: mvebu: cp110: introduce a new binding arm64: dts: marvell: remove *-clock-output-names on cp110 arm64: dts: marvell: use new binding for the system controller on cp110 Konstantin Porotchkin (1): clk: mvebu: cp110: add sdio clock to cp-110 system controller Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 35 +--- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 54 +++ arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi| 48 ++--- drivers/clk/mvebu/cp110-system-controller.c| 202 +--- 4 files changed, 196 insertions(+), 143 deletions(-) base-commit: 2ea659a9ef488125eb46da6eb571de5eae5c43f6 -- git-series 0.9.1
[PATCH 1/7] clk: mvebu: cp110 fix name of the GOP gate clock
Actually the GOP clock (bit 18) is not at all used for emmc but only for GOP: let's fix the name. Changing the name in the device tree is not an issue because the name itself is not used to reference the clock. Thanks to this the ABI remains backward compatible. Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 6 +++--- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi| 2 +- drivers/clk/mvebu/cp110-system-controller.c| 5 +++-- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt index 07dbb358182c..eb6cf44caa0f 100644 --- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt +++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt @@ -45,7 +45,7 @@ The following clocks are available: - 1 15 SATA - 1 16 SATA USB - 1 17 Main - - 1 18 SD/MMC/GOP + - 1 18 GOP - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART) - 1 22 USB3H0 - 1 23 USB3H1 @@ -65,7 +65,7 @@ Required properties: "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none", "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", - "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io", + "cpm-sata-usb", "cpm-main", "cpm-gop", "none", "none", "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; Example: @@ -78,6 +78,6 @@ Example: gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none", "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", - "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io", + "cpm-sata-usb", "cpm-main", "cpm-gop", "none", "none", "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index ac8df5201cd6..59259270964c 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -111,7 +111,7 @@ "cpm-gop-dp", "none", "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", "cpm-sata-usb", "cpm-main", - "cpm-sd-mmc-gop", "none", "none", + "cpm-gop", "none", "none", "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 7740a75a8230..046d3fe53cda 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -118,7 +118,7 @@ "cps-gop-dp", "none", "cps-pcie_x10", "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor", "cps-sata", "cps-sata-usb", "cps-main", - "cps-sd-mmc-go
[PATCH 1/7] clk: mvebu: cp110 fix name of the GOP gate clock
Actually the GOP clock (bit 18) is not at all used for emmc but only for GOP: let's fix the name. Changing the name in the device tree is not an issue because the name itself is not used to reference the clock. Thanks to this the ABI remains backward compatible. Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 6 +++--- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi| 2 +- drivers/clk/mvebu/cp110-system-controller.c| 5 +++-- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt index 07dbb358182c..eb6cf44caa0f 100644 --- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt +++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt @@ -45,7 +45,7 @@ The following clocks are available: - 1 15 SATA - 1 16 SATA USB - 1 17 Main - - 1 18 SD/MMC/GOP + - 1 18 GOP - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART) - 1 22 USB3H0 - 1 23 USB3H1 @@ -65,7 +65,7 @@ Required properties: "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none", "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", - "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io", + "cpm-sata-usb", "cpm-main", "cpm-gop", "none", "none", "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; Example: @@ -78,6 +78,6 @@ Example: gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none", "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", - "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io", + "cpm-sata-usb", "cpm-main", "cpm-gop", "none", "none", "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index ac8df5201cd6..59259270964c 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -111,7 +111,7 @@ "cpm-gop-dp", "none", "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", "cpm-sata-usb", "cpm-main", - "cpm-sd-mmc-gop", "none", "none", + "cpm-gop", "none", "none", "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 7740a75a8230..046d3fe53cda 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -118,7 +118,7 @@ "cps-gop-dp", "none", "cps-pcie_x10", "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor", "cps-sata", "cps-sata-usb", "cps-main", - "cps-sd-mmc-gop", "none", &q
[PATCH 2/7] clk: mvebu: cp110: make failure labels more meaningful
In preparation to the addition of a new clock, rename the goto labels
used to handle the failure cases using a name related to the failure
cause. This will allow to insert additional failing cases without
renaming all the labels.
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/clk/mvebu/cp110-system-controller.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/mvebu/cp110-system-controller.c
b/drivers/clk/mvebu/cp110-system-controller.c
index 8f315c74997e..2a75397f9304 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -221,7 +221,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
1000 * 1000 * 1000);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto fail0;
+ goto fail_apll;
}
cp110_clks[CP110_CORE_APLL] = hw;
@@ -232,7 +232,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
hw = clk_hw_register_fixed_factor(NULL, ppv2_name, apll_name, 0, 1, 3);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto fail1;
+ goto fail_ppv2;
}
cp110_clks[CP110_CORE_PPV2] = hw;
@@ -243,7 +243,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
hw = clk_hw_register_fixed_factor(NULL, eip_name, apll_name, 0, 1, 2);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto fail2;
+ goto fail_eip;
}
cp110_clks[CP110_CORE_EIP] = hw;
@@ -254,7 +254,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
hw = clk_hw_register_fixed_factor(NULL, core_name, eip_name, 0, 1, 2);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto fail3;
+ goto fail_core;
}
cp110_clks[CP110_CORE_CORE] = hw;
@@ -270,7 +270,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
core_name, 0, 1, 1);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto fail4;
+ goto fail_nand;
}
cp110_clks[CP110_CORE_NAND] = hw;
@@ -366,15 +366,15 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
}
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
-fail4:
+fail_nand:
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
-fail3:
+fail_core:
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_EIP]);
-fail2:
+fail_eip:
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]);
-fail1:
+fail_ppv2:
clk_hw_unregister_fixed_rate(cp110_clks[CP110_CORE_APLL]);
-fail0:
+fail_apll:
return ret;
}
--
git-series 0.9.1
[PATCH 3/7] clk: mvebu: cp110: do not depend anymore of the *-clock-output-names
Using the *-clock-output-names property was a convenient way to have a
unique name for each clock even when there are multiple cp110 blocks
as we can find on Armada 8K.
However it has some drawbacks: the main one being a stronger link than
necessary between the driver and the device tree. For example the clock
name can't be changed, removed or moved. It is still the early stage of
introduction of the Armada 7K/8K and the hardware is still not totally
documented, especially for the clock part. By removing the use of
*-clock-output-names it will be easier to add new clocks without breaking
the compatibility.
The name of each clock is now created by using its physical address as a
prefix (as it was done for the platform device names). Thanks to this we
have an automatic way to compute a unique name.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt |
14 +--
drivers/clk/mvebu/cp110-system-controller.c|
106
2 files changed, 65 insertions(+), 55 deletions(-)
diff --git
a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
index eb6cf44caa0f..47f1cf800e25 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -59,14 +59,6 @@ Required properties:
"marvell,cp110-system-controller0", "syscon";
- reg: register area of the CP110 system controller 0
- #clock-cells: must be set to 2
- - core-clock-output-names must be set to:
- "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core"
- - gate-clock-output-names must be set to:
- "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
- "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp",
"none",
- "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
"cpm-sata",
- "cpm-sata-usb", "cpm-main", "cpm-gop", "none", "none", "cpm-slow-io",
- "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
Example:
@@ -74,10 +66,4 @@ Example:
compatible = "marvell,cp110-system-controller0", "syscon";
reg = <0x44 0x1000>;
#clock-cells = <2>;
- core-clock-output-names = "cpm-apll", "cpm-ppv2-core",
"cpm-eip", "cpm-core", "cpm-nand-core";
- gate-clock-output-names = "cpm-audio", "cpm-communit",
"cpm-nand", "cpm-ppv2", "cpm-sdio",
- "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0",
"cpm-gop-dp", "none",
- "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4",
"cpm-pcie-xor", "cpm-sata",
- "cpm-sata-usb", "cpm-main", "cpm-gop", "none", "none",
"cpm-slow-io",
- "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev",
"cpm-eip150", "cpm-eip197";
};
diff --git a/drivers/clk/mvebu/cp110-system-controller.c
b/drivers/clk/mvebu/cp110-system-controller.c
index 2a75397f9304..c7df8a69ed9a 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -84,6 +84,33 @@ enum {
#define CP110_GATE_EIP150 25
#define CP110_GATE_EIP197 26
+const char *gate_base_names[] = {
+ [CP110_GATE_AUDIO] = "audio",
+ [CP110_GATE_COMM_UNIT] = "communit",
+ [CP110_GATE_NAND] = "nand",
+ [CP110_GATE_PPV2] = "ppv2",
+ [CP110_GATE_SDIO] = "sdio",
+ [CP110_GATE_MG] = "mg-domain",
+ [CP110_GATE_MG_CORE]= "mg-core",
+ [CP110_GATE_XOR1] = "xor1",
+ [CP110_GATE_XOR0] = "xor0",
+ [CP110_GATE_GOP_DP] = "gop-dp",
+ [CP110_GATE_PCIE_X1_0] = "pcie_x10",
+ [CP110_GATE_PCIE_X1_1] = "pcie_x11",
+ [CP110_GATE_PCIE_X4]= "pcie_x4",
+ [CP110_GATE_PCIE_XOR] = "pcie-xor",
+ [CP110_GA
[PATCH 2/7] clk: mvebu: cp110: make failure labels more meaningful
In preparation to the addition of a new clock, rename the goto labels
used to handle the failure cases using a name related to the failure
cause. This will allow to insert additional failing cases without
renaming all the labels.
Reviewed-by: Thomas Petazzoni
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/cp110-system-controller.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/mvebu/cp110-system-controller.c
b/drivers/clk/mvebu/cp110-system-controller.c
index 8f315c74997e..2a75397f9304 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -221,7 +221,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
1000 * 1000 * 1000);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto fail0;
+ goto fail_apll;
}
cp110_clks[CP110_CORE_APLL] = hw;
@@ -232,7 +232,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
hw = clk_hw_register_fixed_factor(NULL, ppv2_name, apll_name, 0, 1, 3);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto fail1;
+ goto fail_ppv2;
}
cp110_clks[CP110_CORE_PPV2] = hw;
@@ -243,7 +243,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
hw = clk_hw_register_fixed_factor(NULL, eip_name, apll_name, 0, 1, 2);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto fail2;
+ goto fail_eip;
}
cp110_clks[CP110_CORE_EIP] = hw;
@@ -254,7 +254,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
hw = clk_hw_register_fixed_factor(NULL, core_name, eip_name, 0, 1, 2);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto fail3;
+ goto fail_core;
}
cp110_clks[CP110_CORE_CORE] = hw;
@@ -270,7 +270,7 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
core_name, 0, 1, 1);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto fail4;
+ goto fail_nand;
}
cp110_clks[CP110_CORE_NAND] = hw;
@@ -366,15 +366,15 @@ static int cp110_syscon_clk_probe(struct platform_device
*pdev)
}
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
-fail4:
+fail_nand:
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
-fail3:
+fail_core:
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_EIP]);
-fail2:
+fail_eip:
clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]);
-fail1:
+fail_ppv2:
clk_hw_unregister_fixed_rate(cp110_clks[CP110_CORE_APLL]);
-fail0:
+fail_apll:
return ret;
}
--
git-series 0.9.1
[PATCH 3/7] clk: mvebu: cp110: do not depend anymore of the *-clock-output-names
Using the *-clock-output-names property was a convenient way to have a
unique name for each clock even when there are multiple cp110 blocks
as we can find on Armada 8K.
However it has some drawbacks: the main one being a stronger link than
necessary between the driver and the device tree. For example the clock
name can't be changed, removed or moved. It is still the early stage of
introduction of the Armada 7K/8K and the hardware is still not totally
documented, especially for the clock part. By removing the use of
*-clock-output-names it will be easier to add new clocks without breaking
the compatibility.
The name of each clock is now created by using its physical address as a
prefix (as it was done for the platform device names). Thanks to this we
have an automatic way to compute a unique name.
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt |
14 +--
drivers/clk/mvebu/cp110-system-controller.c|
106
2 files changed, 65 insertions(+), 55 deletions(-)
diff --git
a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
index eb6cf44caa0f..47f1cf800e25 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -59,14 +59,6 @@ Required properties:
"marvell,cp110-system-controller0", "syscon";
- reg: register area of the CP110 system controller 0
- #clock-cells: must be set to 2
- - core-clock-output-names must be set to:
- "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core"
- - gate-clock-output-names must be set to:
- "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
- "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp",
"none",
- "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
"cpm-sata",
- "cpm-sata-usb", "cpm-main", "cpm-gop", "none", "none", "cpm-slow-io",
- "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
Example:
@@ -74,10 +66,4 @@ Example:
compatible = "marvell,cp110-system-controller0", "syscon";
reg = <0x44 0x1000>;
#clock-cells = <2>;
- core-clock-output-names = "cpm-apll", "cpm-ppv2-core",
"cpm-eip", "cpm-core", "cpm-nand-core";
- gate-clock-output-names = "cpm-audio", "cpm-communit",
"cpm-nand", "cpm-ppv2", "cpm-sdio",
- "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0",
"cpm-gop-dp", "none",
- "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4",
"cpm-pcie-xor", "cpm-sata",
- "cpm-sata-usb", "cpm-main", "cpm-gop", "none", "none",
"cpm-slow-io",
- "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev",
"cpm-eip150", "cpm-eip197";
};
diff --git a/drivers/clk/mvebu/cp110-system-controller.c
b/drivers/clk/mvebu/cp110-system-controller.c
index 2a75397f9304..c7df8a69ed9a 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -84,6 +84,33 @@ enum {
#define CP110_GATE_EIP150 25
#define CP110_GATE_EIP197 26
+const char *gate_base_names[] = {
+ [CP110_GATE_AUDIO] = "audio",
+ [CP110_GATE_COMM_UNIT] = "communit",
+ [CP110_GATE_NAND] = "nand",
+ [CP110_GATE_PPV2] = "ppv2",
+ [CP110_GATE_SDIO] = "sdio",
+ [CP110_GATE_MG] = "mg-domain",
+ [CP110_GATE_MG_CORE]= "mg-core",
+ [CP110_GATE_XOR1] = "xor1",
+ [CP110_GATE_XOR0] = "xor0",
+ [CP110_GATE_GOP_DP] = "gop-dp",
+ [CP110_GATE_PCIE_X1_0] = "pcie_x10",
+ [CP110_GATE_PCIE_X1_1] = "pcie_x11",
+ [CP110_GATE_PCIE_X4]= "pcie_x4",
+ [CP110_GATE_PCIE_XOR] = "pcie-xor",
+ [CP110_GATE_SATA] = "sata",
+ [CP11
Re: [PATCH v6 2/4] ARM: dts: mvebu: Add PWM properties to .dtsi files
Hi Ralph, On ven., mai 05 2017, Ralph Sennhauser <ralph.sennhau...@gmail.com> wrote: > On Mon, 24 Apr 2017 11:19:32 +0200 > Linus Walleij <linus.wall...@linaro.org> wrote: > >> On Fri, Apr 14, 2017 at 5:40 PM, Ralph Sennhauser >> <ralph.sennhau...@gmail.com> wrote: >> >> > From: Andrew Lunn <and...@lunn.ch> >> > >> > Add properties to the GPIO nodes to allow them to be also used as >> > PWM lines. >> > >> > Signed-off-by: Andrew Lunn <and...@lunn.ch> >> > URL: https://patchwork.ozlabs.org/patch/427294/ >> > [Ralph Sennhauser: Add new compatible string >> > marvell,armada-370-xp-gpio] Signed-off-by: Ralph Sennhauser >> > <ralph.sennhau...@gmail.com> Tested-by: Andrew Lunn >> > <and...@lunn.ch> >> >> Acked-by: Linus Walleij <linus.wall...@linaro.org> >> >> Please funnel this through ARM SoC. > > Hi Gregory, > > A reminder on the off chance you have missed this and it's not to late > already, Linus Walleij took the driver and submitted it for inclusion in > 4.12 [1]. So for completeness it be nice to have the dts(i) and > defconfig changes in as well. Unfortunately it was too late to applied and to push it to arm-soc when the gpio part was applied. So I will apply when 4.12-rc1 will be released and it will be included in the 4.13 release. Gregory > > Thanks > Ralph > > [1] https://lkml.org/lkml/2017/5/4/82 > >> >> Yours, >> Linus Walleij > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH v6 2/4] ARM: dts: mvebu: Add PWM properties to .dtsi files
Hi Ralph, On ven., mai 05 2017, Ralph Sennhauser wrote: > On Mon, 24 Apr 2017 11:19:32 +0200 > Linus Walleij wrote: > >> On Fri, Apr 14, 2017 at 5:40 PM, Ralph Sennhauser >> wrote: >> >> > From: Andrew Lunn >> > >> > Add properties to the GPIO nodes to allow them to be also used as >> > PWM lines. >> > >> > Signed-off-by: Andrew Lunn >> > URL: https://patchwork.ozlabs.org/patch/427294/ >> > [Ralph Sennhauser: Add new compatible string >> > marvell,armada-370-xp-gpio] Signed-off-by: Ralph Sennhauser >> > Tested-by: Andrew Lunn >> > >> >> Acked-by: Linus Walleij >> >> Please funnel this through ARM SoC. > > Hi Gregory, > > A reminder on the off chance you have missed this and it's not to late > already, Linus Walleij took the driver and submitted it for inclusion in > 4.12 [1]. So for completeness it be nice to have the dts(i) and > defconfig changes in as well. Unfortunately it was too late to applied and to push it to arm-soc when the gpio part was applied. So I will apply when 4.12-rc1 will be released and it will be included in the 4.13 release. Gregory > > Thanks > Ralph > > [1] https://lkml.org/lkml/2017/5/4/82 > >> >> Yours, >> Linus Walleij > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH] Documentation: earlycon: fix Marvell Armada 3700 UART name
Hi Andre, On jeu., mai 04 2017, Andre Przywara <andre.przyw...@arm.com> wrote: > The Marvell Armada 3700 UART uses "ar3700_uart" for its earlycon name. > Adjust documentation to match the code. Actually I think it was the code which was wrong. But as it is already part of the kernel it's too late to modify it. > > Signed-off-by: Andre Przywara <andre.przyw...@arm.com> Acked-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> Thanks, Gregory > --- > Documentation/admin-guide/kernel-parameters.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/admin-guide/kernel-parameters.txt > b/Documentation/admin-guide/kernel-parameters.txt > index facc20a..7ee86c2 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -973,7 +973,7 @@ > A valid base address must be provided, and the serial > port must already be setup and configured. > > - armada3700_uart, > + ar3700_uart, > Start an early, polled-mode console on the > Armada 3700 serial port at the specified > address. The serial port must already be setup > -- > 2.8.2 > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH] Documentation: earlycon: fix Marvell Armada 3700 UART name
Hi Andre, On jeu., mai 04 2017, Andre Przywara wrote: > The Marvell Armada 3700 UART uses "ar3700_uart" for its earlycon name. > Adjust documentation to match the code. Actually I think it was the code which was wrong. But as it is already part of the kernel it's too late to modify it. > > Signed-off-by: Andre Przywara Acked-by: Gregory CLEMENT Thanks, Gregory > --- > Documentation/admin-guide/kernel-parameters.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/admin-guide/kernel-parameters.txt > b/Documentation/admin-guide/kernel-parameters.txt > index facc20a..7ee86c2 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -973,7 +973,7 @@ > A valid base address must be provided, and the serial > port must already be setup and configured. > > - armada3700_uart, > + ar3700_uart, > Start an early, polled-mode console on the > Armada 3700 serial port at the specified > address. The serial port must already be setup > -- > 2.8.2 > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
[PATCH v5 1/1] pinctrl: armada-37xx: Add irqchip support
The Armada 37xx SoCs can handle interrupt through GPIO. However it can
only manage the edge ones.
The way the interrupt are managed is classical so we can use the generic
interrupt chip model.
The only unusual "feature" is that many interrupts are connected to the
parent interrupt controller. But we do not take advantage of this and use
the chained irq with all of them.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 229 +-
1 file changed, 229 insertions(+)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 5c96f5558310..001542f68627 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -13,7 +13,9 @@
#include
#include
#include
+#include
#include
+#include
#include
#include
#include
@@ -30,6 +32,11 @@
#define OUTPUT_CTL 0x20
#define SELECTION 0x30
+#define IRQ_EN 0x0
+#define IRQ_POL0x08
+#define IRQ_STATUS 0x10
+#define IRQ_WKUP 0x18
+
#define NB_FUNCS 2
#define GPIO_PER_REG 32
@@ -75,9 +82,12 @@ struct armada_37xx_pmx_func {
struct armada_37xx_pinctrl {
struct regmap *regmap;
+ void __iomem*base;
const struct armada_37xx_pin_data *data;
struct device *dev;
struct gpio_chipgpio_chip;
+ struct irq_chip irq_chip;
+ spinlock_t irq_lock;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
struct armada_37xx_pin_group*groups;
@@ -346,6 +356,14 @@ static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
return armada_37xx_pmx_set_by_name(pctldev, name, grp);
}
+static inline void armada_37xx_irq_update_reg(unsigned int *reg,
+ struct irq_data *d)
+{
+ int offset = irqd_to_hwirq(d);
+
+ armada_37xx_update_reg(reg, offset);
+}
+
static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
@@ -468,6 +486,214 @@ static const struct gpio_chip armada_37xx_gpiolib_chip = {
.owner = THIS_MODULE,
};
+static void armada_37xx_irq_ack(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 reg = IRQ_STATUS;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ writel(d->mask, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+}
+
+static void armada_37xx_irq_mask(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_EN;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ val = readl(info->base + reg);
+ writel(val & ~d->mask, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+}
+
+static void armada_37xx_irq_unmask(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_EN;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ val = readl(info->base + reg);
+ writel(val | d->mask, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+}
+
+static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_WKUP;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ val = readl(info->base + reg);
+ if (on)
+ val |= d->mask;
+ else
+ val &= ~d->mask;
+ writel(val, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+
+ return 0;
+}
+
+static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_POL;
+ unsigned long flags;
+
+ spin_lock_irqsave(>irq_lock, flags);
+ armada_37xx_irq_update_reg(, d);
+ val = readl(info->base + reg);
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ val &= ~d->mask;
+ break;
+ c
[PATCH v5 1/1] pinctrl: armada-37xx: Add irqchip support
The Armada 37xx SoCs can handle interrupt through GPIO. However it can
only manage the edge ones.
The way the interrupt are managed is classical so we can use the generic
interrupt chip model.
The only unusual "feature" is that many interrupts are connected to the
parent interrupt controller. But we do not take advantage of this and use
the chained irq with all of them.
Signed-off-by: Gregory CLEMENT
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 229 +-
1 file changed, 229 insertions(+)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 5c96f5558310..001542f68627 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -13,7 +13,9 @@
#include
#include
#include
+#include
#include
+#include
#include
#include
#include
@@ -30,6 +32,11 @@
#define OUTPUT_CTL 0x20
#define SELECTION 0x30
+#define IRQ_EN 0x0
+#define IRQ_POL0x08
+#define IRQ_STATUS 0x10
+#define IRQ_WKUP 0x18
+
#define NB_FUNCS 2
#define GPIO_PER_REG 32
@@ -75,9 +82,12 @@ struct armada_37xx_pmx_func {
struct armada_37xx_pinctrl {
struct regmap *regmap;
+ void __iomem*base;
const struct armada_37xx_pin_data *data;
struct device *dev;
struct gpio_chipgpio_chip;
+ struct irq_chip irq_chip;
+ spinlock_t irq_lock;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
struct armada_37xx_pin_group*groups;
@@ -346,6 +356,14 @@ static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
return armada_37xx_pmx_set_by_name(pctldev, name, grp);
}
+static inline void armada_37xx_irq_update_reg(unsigned int *reg,
+ struct irq_data *d)
+{
+ int offset = irqd_to_hwirq(d);
+
+ armada_37xx_update_reg(reg, offset);
+}
+
static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
@@ -468,6 +486,214 @@ static const struct gpio_chip armada_37xx_gpiolib_chip = {
.owner = THIS_MODULE,
};
+static void armada_37xx_irq_ack(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 reg = IRQ_STATUS;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ writel(d->mask, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+}
+
+static void armada_37xx_irq_mask(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_EN;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ val = readl(info->base + reg);
+ writel(val & ~d->mask, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+}
+
+static void armada_37xx_irq_unmask(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_EN;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ val = readl(info->base + reg);
+ writel(val | d->mask, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+}
+
+static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_WKUP;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ val = readl(info->base + reg);
+ if (on)
+ val |= d->mask;
+ else
+ val &= ~d->mask;
+ writel(val, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+
+ return 0;
+}
+
+static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_POL;
+ unsigned long flags;
+
+ spin_lock_irqsave(>irq_lock, flags);
+ armada_37xx_irq_update_reg(, d);
+ val = readl(info->base + reg);
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ val &= ~d->mask;
+ break;
+ case IR
[PATCH v5 0/1] Add support for pinctrl/gpio on Armada 37xx
Hi, This fifth version contain only one patch all the other ones have been applied on the pinctrl or the mvebu trees. For the record, this series adds support for the pin and gpio controllers present on the Armada 37xx SoCs. Each Armada 37xx SoC comes with 2 pin controllers: one on the south bridge (managing 28 pins) and one on the north bridge (managing 36 pins). At the hardware level the controller configure the pins by group and not pin by pin. The gpio controller is also capable to handle interrupt from gpio. Changelog v4 -> v5 - Removed all the patches already applied - Rebased on linux-next - Applied binding changes asked by Rob by removing the -nb and -sb part - Use d->mask directly directly when possible - Add comment about the check on gpio-controller child node - Use of_property_read_bool() instead of of_find_property() - Declared the armada_37xx_irq_*() functions as static - check status register for each iteration inside the irq handler v3 -> v4 - Some group are configured by several bits in the register: extend the armada_37xx_pin_group struct to manage it. - Fix the uart2 and cspi2/3 configuration - Document the armada_37xx_add_function(), armada_37xx_fill_group() and armada_37xx_fill_funcs(). - Use devm_gpiochip_add_data() - Use irq_find_mapping instead of irq_linear_revmap - Use handle_edge_irq instead of the wrong handle_level_irq - Add comment about the fact the we have multiple parent interrupt - Add comment about the mask usage of the irq_data struct - Use BIT() macro when possible - Select more CONFIG symbol needed for GPIO and interrupt support v2 -> v3 - use gpio-ranges (patch 4) - Document gpio-ranges usage (patch 1) - do not use anymore a global pin index (patch 3) v1 -> v2: - Update binding documentation making clear that mfd and syscon must be used (patch 1). - Split the fist patch adding pin controller support for Armada 37xx in arm64 part (for kconfig) and pinctrl part (patch 2 and 3) - Add MFD_SYSCON dependency (patch 3) - Add kerneldoc for the armada_37xx_pin_group struct (patch 3) - Rename _add_function() to armada_37xx_add_function() (patch 3) - Use an inline function to update the reg offset (patch 4) - Rename gpiolib_register to gpiochip_register (patch 4) - Add a comment about the two registers limit (patch 4) - Add explicit gpio node in the device tree (patch 4) - Convert the driver to use GPIOLIB_IRQCHIP (patch 5) - Add a critical section when accessing the hardware registers (patch 5) - Use the gpio subnode (patch 5) Thanks, Gregory Gregory CLEMENT (1): pinctrl: armada-37xx: Add irqchip support drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 229 +- 1 file changed, 229 insertions(+) base-commit: 5ae46f24f9b42187beeb512a5203126789cc791b -- git-series 0.9.1
[PATCH v5 0/1] Add support for pinctrl/gpio on Armada 37xx
Hi, This fifth version contain only one patch all the other ones have been applied on the pinctrl or the mvebu trees. For the record, this series adds support for the pin and gpio controllers present on the Armada 37xx SoCs. Each Armada 37xx SoC comes with 2 pin controllers: one on the south bridge (managing 28 pins) and one on the north bridge (managing 36 pins). At the hardware level the controller configure the pins by group and not pin by pin. The gpio controller is also capable to handle interrupt from gpio. Changelog v4 -> v5 - Removed all the patches already applied - Rebased on linux-next - Applied binding changes asked by Rob by removing the -nb and -sb part - Use d->mask directly directly when possible - Add comment about the check on gpio-controller child node - Use of_property_read_bool() instead of of_find_property() - Declared the armada_37xx_irq_*() functions as static - check status register for each iteration inside the irq handler v3 -> v4 - Some group are configured by several bits in the register: extend the armada_37xx_pin_group struct to manage it. - Fix the uart2 and cspi2/3 configuration - Document the armada_37xx_add_function(), armada_37xx_fill_group() and armada_37xx_fill_funcs(). - Use devm_gpiochip_add_data() - Use irq_find_mapping instead of irq_linear_revmap - Use handle_edge_irq instead of the wrong handle_level_irq - Add comment about the fact the we have multiple parent interrupt - Add comment about the mask usage of the irq_data struct - Use BIT() macro when possible - Select more CONFIG symbol needed for GPIO and interrupt support v2 -> v3 - use gpio-ranges (patch 4) - Document gpio-ranges usage (patch 1) - do not use anymore a global pin index (patch 3) v1 -> v2: - Update binding documentation making clear that mfd and syscon must be used (patch 1). - Split the fist patch adding pin controller support for Armada 37xx in arm64 part (for kconfig) and pinctrl part (patch 2 and 3) - Add MFD_SYSCON dependency (patch 3) - Add kerneldoc for the armada_37xx_pin_group struct (patch 3) - Rename _add_function() to armada_37xx_add_function() (patch 3) - Use an inline function to update the reg offset (patch 4) - Rename gpiolib_register to gpiochip_register (patch 4) - Add a comment about the two registers limit (patch 4) - Add explicit gpio node in the device tree (patch 4) - Convert the driver to use GPIOLIB_IRQCHIP (patch 5) - Add a critical section when accessing the hardware registers (patch 5) - Use the gpio subnode (patch 5) Thanks, Gregory Gregory CLEMENT (1): pinctrl: armada-37xx: Add irqchip support drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 229 +- 1 file changed, 229 insertions(+) base-commit: 5ae46f24f9b42187beeb512a5203126789cc791b -- git-series 0.9.1
Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support
Hi Linus,
On mer., avril 26 2017, Linus Walleij <linus.wall...@linaro.org> wrote:
> On Wed, Apr 26, 2017 at 11:23 AM, Gregory CLEMENT
> <gregory.clem...@free-electrons.com> wrote:
>> On lun., avril 24 2017, Linus Walleij <linus.wall...@linaro.org> wrote:
>
>>>> + spin_lock_irqsave(>irq_lock, flags);
>>>> + status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
>>>> + /* Manage only the interrupt that was enabled */
>>>> + status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
>>>> + spin_unlock_irqrestore(>irq_lock, flags);
>>>> + while (status) {
>>>> + u32 hwirq = ffs(status) - 1;
>>>> + u32 virq = irq_find_mapping(d, hwirq +
>>>> +i * GPIO_PER_REG);
>>>> +
>>>> + generic_handle_irq(virq);
>>>> + status &= ~BIT(hwirq);
>>>> + }
>>>
>>> You hae a problem here is a new IRQ appears while you are inside
>>> of this loop. You need to re-read the status register for each iteration
>>> (and &= with the IRQ_EN I guess).
>>
>> If a new IRQ appears during the loop, then the irq handler will be
>> called again because the cause of this new IRQ won't have been acked
>> yet. So I think we're fine here.
>
> That *might* be true. It is true if the CPU gets a level IRQ from the
> GPIO controller. But hardware dealing with edge IRQs can be very
> quirky here, and just send a pulse on the line to the CPU if the
> CPU-bound IRQ is also just edge triggered. And then that
> pulse would potentially be missed while dealing with the current
> IRQ in this handler. (And exactly this happened to us on other
> hardware.)
OK thanks for sharing your experience, you convinced me, I am going to
send a new version of the patch with this fix.
>
> But anyway: why let the irq handler be called again if you can avoid
> it?
> You would avoid a double context switch by just checking it again
> in the loop before exiting the handler. And that can be really nice
> for latency-sensitive stuff.
I wanted to avoid an uncached access in each loop if it was not
necessary. But as we finally need it, I will do it.
Gregory
>
> Yours,
> Linus Walleij
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support
Hi Linus,
On mer., avril 26 2017, Linus Walleij wrote:
> On Wed, Apr 26, 2017 at 11:23 AM, Gregory CLEMENT
> wrote:
>> On lun., avril 24 2017, Linus Walleij wrote:
>
>>>> + spin_lock_irqsave(>irq_lock, flags);
>>>> + status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
>>>> + /* Manage only the interrupt that was enabled */
>>>> + status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
>>>> + spin_unlock_irqrestore(>irq_lock, flags);
>>>> + while (status) {
>>>> + u32 hwirq = ffs(status) - 1;
>>>> + u32 virq = irq_find_mapping(d, hwirq +
>>>> +i * GPIO_PER_REG);
>>>> +
>>>> + generic_handle_irq(virq);
>>>> + status &= ~BIT(hwirq);
>>>> + }
>>>
>>> You hae a problem here is a new IRQ appears while you are inside
>>> of this loop. You need to re-read the status register for each iteration
>>> (and &= with the IRQ_EN I guess).
>>
>> If a new IRQ appears during the loop, then the irq handler will be
>> called again because the cause of this new IRQ won't have been acked
>> yet. So I think we're fine here.
>
> That *might* be true. It is true if the CPU gets a level IRQ from the
> GPIO controller. But hardware dealing with edge IRQs can be very
> quirky here, and just send a pulse on the line to the CPU if the
> CPU-bound IRQ is also just edge triggered. And then that
> pulse would potentially be missed while dealing with the current
> IRQ in this handler. (And exactly this happened to us on other
> hardware.)
OK thanks for sharing your experience, you convinced me, I am going to
send a new version of the patch with this fix.
>
> But anyway: why let the irq handler be called again if you can avoid
> it?
> You would avoid a double context switch by just checking it again
> in the loop before exiting the handler. And that can be really nice
> for latency-sensitive stuff.
I wanted to avoid an uncached access in each loop if it was not
necessary. But as we finally need it, I will do it.
Gregory
>
> Yours,
> Linus Walleij
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v4 6/7] ARM64: dts: marvell: Add pinctrl nodes for Armada 3700
Hi,
On mer., avril 05 2017, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> Add the nodes for the two pin controller present in the Armada 37xx SoCs.
>
> Initially the node was named gpio1 using the same name that for the
> register range in the datasheet. However renaming it pinctr_nb (nb for
> North Bridge) makes more sens.
>
> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 42 +++--
> 1 file changed, 39 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> index b48d668a6ab6..c02b13479458 100644
> --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> @@ -157,10 +157,29 @@
> #clock-cells = <1>;
> };
>
> - gpio1: gpio@13800 {
> - compatible = "marvell,mvebu-gpio-3700",
> + pinctrl_nb: pinctrl-nb@13800 {
> + compatible = "marvell,armada3710-nb-pinctrl",
> "syscon", "simple-mfd";
> - reg = <0x13800 0x500>;
> + reg = <0x13800 0x100>, <0x13C00 0x20>;
> + gpionb: gpionb {
> + #gpio-cells = <2>;
> + gpio-ranges = <_nb 0 0 36>;
> + gpio-controller;
> + interrupts =
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ;
> +
> + };
>
> xtalclk: xtal-clk {
> compatible =
> "marvell,armada-3700-xtal-clock";
> @@ -169,6 +188,23 @@
> };
> };
>
> + pinctrl_sb: pinctrl-sb@18800 {
> + compatible = "marvell,armada3710-sb-pinctrl",
> + "syscon", "simple-mfd";
> + reg = <0x18800 0x100>, <0x18C00 0x20>;
> + gpiosb: gpiosb {
> + #gpio-cells = <2>;
> + gpio-ranges = <_sb 0 0 29>;
> + gpio-controller;
> + interrupts =
> + ,
> + ,
> + ,
> + ,
> + ;
> + };
> + };
> +
> eth0: ethernet@3 {
> compatible = "marvell,armada-3700-neta";
> reg = <0x3 0x4000>;
> --
> git-series 0.9.1
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v4 7/7] ARM64: dts: marvell: armada37xx: add pinctrl definition
Hi,
On mer., avril 05 2017, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> Start to populate the device tree of the Armada 37xx with the pincontrol
> configuration used on the board providing a dts.
>
> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-3720-db.dts | 8 +-
> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 31 +++-
> 2 files changed, 39 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
> b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
> index 86602c907a61..e749c5727490 100644
> --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
> @@ -63,6 +63,8 @@
> };
>
> {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> status = "okay";
> };
>
> @@ -73,6 +75,8 @@
>
> {
> status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <_quad_pins>;
>
> m25p80@0 {
> compatible = "jedec,spi-nor";
> @@ -103,6 +107,8 @@
>
> /* Exported on the micro USB connector CON32 through an FTDI */
> {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> status = "okay";
> };
>
> @@ -128,6 +134,8 @@
> };
>
> {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> phy-mode = "rgmii-id";
> phy = <>;
> status = "okay";
> diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> index c02b13479458..2ac25f54d01d 100644
> --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> @@ -186,6 +186,31 @@
> clock-output-names = "xtal";
> #clock-cells = <0>;
> };
> +
> + spi_quad_pins: spi-quad-pins {
> + groups = "spi_quad";
> + function = "spi";
> + };
> +
> + i2c1_pins: i2c1-pins {
> + groups = "i2c1";
> + function = "i2c";
> + };
> +
> + i2c2_pins: i2c2-pins {
> + groups = "i2c2";
> + function = "i2c";
> + };
> +
> + uart1_pins: uart1-pins {
> + groups = "uart1";
> + function = "uart";
> + };
> +
> + uart2_pins: uart2-pins {
> + groups = "uart2";
> + function = "uart";
> + };
> };
>
> pinctrl_sb: pinctrl-sb@18800 {
> @@ -203,6 +228,12 @@
> ,
> ;
> };
> +
> + rgmii_pins: mii-pins {
> + groups = "rgmii";
> + function = "mii";
> + };
> +
> };
>
> eth0: ethernet@3 {
> --
> git-series 0.9.1
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v4 6/7] ARM64: dts: marvell: Add pinctrl nodes for Armada 3700
Hi,
On mer., avril 05 2017, Gregory CLEMENT
wrote:
> Add the nodes for the two pin controller present in the Armada 37xx SoCs.
>
> Initially the node was named gpio1 using the same name that for the
> register range in the datasheet. However renaming it pinctr_nb (nb for
> North Bridge) makes more sens.
>
> Signed-off-by: Gregory CLEMENT
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 42 +++--
> 1 file changed, 39 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> index b48d668a6ab6..c02b13479458 100644
> --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> @@ -157,10 +157,29 @@
> #clock-cells = <1>;
> };
>
> - gpio1: gpio@13800 {
> - compatible = "marvell,mvebu-gpio-3700",
> + pinctrl_nb: pinctrl-nb@13800 {
> + compatible = "marvell,armada3710-nb-pinctrl",
> "syscon", "simple-mfd";
> - reg = <0x13800 0x500>;
> + reg = <0x13800 0x100>, <0x13C00 0x20>;
> + gpionb: gpionb {
> + #gpio-cells = <2>;
> + gpio-ranges = <_nb 0 0 36>;
> + gpio-controller;
> + interrupts =
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ;
> +
> + };
>
> xtalclk: xtal-clk {
> compatible =
> "marvell,armada-3700-xtal-clock";
> @@ -169,6 +188,23 @@
> };
> };
>
> + pinctrl_sb: pinctrl-sb@18800 {
> + compatible = "marvell,armada3710-sb-pinctrl",
> + "syscon", "simple-mfd";
> + reg = <0x18800 0x100>, <0x18C00 0x20>;
> + gpiosb: gpiosb {
> + #gpio-cells = <2>;
> + gpio-ranges = <_sb 0 0 29>;
> + gpio-controller;
> + interrupts =
> + ,
> + ,
> + ,
> + ,
> + ;
> + };
> + };
> +
> eth0: ethernet@3 {
> compatible = "marvell,armada-3700-neta";
> reg = <0x3 0x4000>;
> --
> git-series 0.9.1
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v4 7/7] ARM64: dts: marvell: armada37xx: add pinctrl definition
Hi,
On mer., avril 05 2017, Gregory CLEMENT
wrote:
> Start to populate the device tree of the Armada 37xx with the pincontrol
> configuration used on the board providing a dts.
>
> Signed-off-by: Gregory CLEMENT
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-3720-db.dts | 8 +-
> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 31 +++-
> 2 files changed, 39 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
> b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
> index 86602c907a61..e749c5727490 100644
> --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
> @@ -63,6 +63,8 @@
> };
>
> {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> status = "okay";
> };
>
> @@ -73,6 +75,8 @@
>
> {
> status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <_quad_pins>;
>
> m25p80@0 {
> compatible = "jedec,spi-nor";
> @@ -103,6 +107,8 @@
>
> /* Exported on the micro USB connector CON32 through an FTDI */
> {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> status = "okay";
> };
>
> @@ -128,6 +134,8 @@
> };
>
> {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> phy-mode = "rgmii-id";
> phy = <>;
> status = "okay";
> diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> index c02b13479458..2ac25f54d01d 100644
> --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> @@ -186,6 +186,31 @@
> clock-output-names = "xtal";
> #clock-cells = <0>;
> };
> +
> + spi_quad_pins: spi-quad-pins {
> + groups = "spi_quad";
> + function = "spi";
> + };
> +
> + i2c1_pins: i2c1-pins {
> + groups = "i2c1";
> + function = "i2c";
> + };
> +
> + i2c2_pins: i2c2-pins {
> + groups = "i2c2";
> + function = "i2c";
> + };
> +
> + uart1_pins: uart1-pins {
> + groups = "uart1";
> + function = "uart";
> + };
> +
> + uart2_pins: uart2-pins {
> + groups = "uart2";
> + function = "uart";
> + };
> };
>
> pinctrl_sb: pinctrl-sb@18800 {
> @@ -203,6 +228,12 @@
> ,
> ;
> };
> +
> + rgmii_pins: mii-pins {
> + groups = "rgmii";
> + function = "mii";
> + };
> +
> };
>
> eth0: ethernet@3 {
> --
> git-series 0.9.1
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v4 2/7] arm64: marvell: enable the Armada 37xx pinctrl driver
Hi, On mer., avril 05 2017, Gregory CLEMENT <gregory.clem...@free-electrons.com> wrote: > This commit makes sure the driver for the Armada 37xx pin controller is > enabled. > > Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> Applied on mvebu/arm64 Thanks, Gregory > --- > arch/arm64/Kconfig.platforms | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms > index 129cc5ae4091..9aa71a3f3f50 100644 > --- a/arch/arm64/Kconfig.platforms > +++ b/arch/arm64/Kconfig.platforms > @@ -103,8 +103,13 @@ config ARCH_MVEBU > select ARMADA_AP806_SYSCON > select ARMADA_CP110_SYSCON > select ARMADA_37XX_CLK > + select GPIOLIB > + select GPIOLIB_IRQCHIP > select MVEBU_ODMI > select MVEBU_PIC > + select OF_GPIO > + select PINCTRL > + select PINCTRL_ARMADA_37XX > help > This enables support for Marvell EBU familly, including: > - Armada 3700 SoC Family > -- > git-series 0.9.1 -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH v4 2/7] arm64: marvell: enable the Armada 37xx pinctrl driver
Hi, On mer., avril 05 2017, Gregory CLEMENT wrote: > This commit makes sure the driver for the Armada 37xx pin controller is > enabled. > > Signed-off-by: Gregory CLEMENT Applied on mvebu/arm64 Thanks, Gregory > --- > arch/arm64/Kconfig.platforms | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms > index 129cc5ae4091..9aa71a3f3f50 100644 > --- a/arch/arm64/Kconfig.platforms > +++ b/arch/arm64/Kconfig.platforms > @@ -103,8 +103,13 @@ config ARCH_MVEBU > select ARMADA_AP806_SYSCON > select ARMADA_CP110_SYSCON > select ARMADA_37XX_CLK > + select GPIOLIB > + select GPIOLIB_IRQCHIP > select MVEBU_ODMI > select MVEBU_PIC > + select OF_GPIO > + select PINCTRL > + select PINCTRL_ARMADA_37XX > help > This enables support for Marvell EBU familly, including: > - Armada 3700 SoC Family > -- > git-series 0.9.1 -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support
Hi Linus,
On lun., avril 24 2017, Linus Walleij <linus.wall...@linaro.org> wrote:
> On Wed, Apr 5, 2017 at 5:18 PM, Gregory CLEMENT
> <gregory.clem...@free-electrons.com> wrote:
>
>> The Armada 37xx SoCs can handle interrupt through GPIO. However it can
>> only manage the edge ones.
>>
>> The way the interrupt are managed are classical so we can use the generic
>> interrupt chip model.
>>
>> The only unusual "feature" is that many interrupts are connected to the
>> parent interrupt controller. But we do not take advantage of this and use
>> the chained irq with all of them.
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>
> There are some issues with this patch.
>
> First:
> You need to add
> select GPIOLIB_IRQCHIP
> to the Kconfig entry. It's only working in your setup
> because something else is selecting this for you, probably.
It is done in patch 2 "arm64: marvell: enable the Armada 37xx pinctrl
driver".
>
> At all places like this:
>
>> + u32 mask = d->mask;
> (...)
>> + if (on)
>> + val |= mask;
>> + else
>> + val &= ~mask;
>
> Isn't it simpler to just use d->mask directly in the code and skip the local
> variable?
>
> if (on)
> val |= d->mask;
> (...)
Yes sure I cand do it.
>
>> +static void armada_37xx_irq_handler(struct irq_desc *desc)
>> +{
>> + struct gpio_chip *gc = irq_desc_get_handler_data(desc);
>> + struct irq_chip *chip = irq_desc_get_chip(desc);
>> + struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
>> + struct irq_domain *d = gc->irqdomain;
>> + int i;
>> +
>> + chained_irq_enter(chip, desc);
>> + for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
>> + u32 status;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(>irq_lock, flags);
>> + status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
>> + /* Manage only the interrupt that was enabled */
>> + status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
>> + spin_unlock_irqrestore(>irq_lock, flags);
>> + while (status) {
>> + u32 hwirq = ffs(status) - 1;
>> + u32 virq = irq_find_mapping(d, hwirq +
>> +i * GPIO_PER_REG);
>> +
>> + generic_handle_irq(virq);
>> + status &= ~BIT(hwirq);
>> + }
>
> You hae a problem here is a new IRQ appears while you are inside
> of this loop. You need to re-read the status register for each iteration
> (and &= with the IRQ_EN I guess).
If a new IRQ appears during the loop, then the irq handler will be
called again because the cause of this new IRQ won't have been acked
yet. So I think we're fine here.
>
>> +static int armada_37xx_irqchip_register(struct platform_device *pdev,
>> + struct armada_37xx_pinctrl *info)
>> +{
>> + struct device_node *np = info->dev->of_node;
>> + int nrirqs = info->data->nr_pins;
>> + struct gpio_chip *gc = >gpio_chip;
>> + struct irq_chip *irqchip = >irq_chip;
>> + struct resource res;
>> + int ret = -ENODEV, i, nr_irq_parent;
>> +
>
> This warrants a comment:
> /* Check if we have at least one gpio-controller child node */
>
OK
>> + for_each_child_of_node(info->dev->of_node, np) {
>> + if (of_find_property(np, "gpio-controller", NULL)) {
>> + ret = 0;
>> + break;
>> + }
>
> Rewrite:
>
> if (of_property_read_bool(np, "gpio-controller"))
>
OK
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support
Hi Linus,
On lun., avril 24 2017, Linus Walleij wrote:
> On Wed, Apr 5, 2017 at 5:18 PM, Gregory CLEMENT
> wrote:
>
>> The Armada 37xx SoCs can handle interrupt through GPIO. However it can
>> only manage the edge ones.
>>
>> The way the interrupt are managed are classical so we can use the generic
>> interrupt chip model.
>>
>> The only unusual "feature" is that many interrupts are connected to the
>> parent interrupt controller. But we do not take advantage of this and use
>> the chained irq with all of them.
>>
>> Signed-off-by: Gregory CLEMENT
>
> There are some issues with this patch.
>
> First:
> You need to add
> select GPIOLIB_IRQCHIP
> to the Kconfig entry. It's only working in your setup
> because something else is selecting this for you, probably.
It is done in patch 2 "arm64: marvell: enable the Armada 37xx pinctrl
driver".
>
> At all places like this:
>
>> + u32 mask = d->mask;
> (...)
>> + if (on)
>> + val |= mask;
>> + else
>> + val &= ~mask;
>
> Isn't it simpler to just use d->mask directly in the code and skip the local
> variable?
>
> if (on)
> val |= d->mask;
> (...)
Yes sure I cand do it.
>
>> +static void armada_37xx_irq_handler(struct irq_desc *desc)
>> +{
>> + struct gpio_chip *gc = irq_desc_get_handler_data(desc);
>> + struct irq_chip *chip = irq_desc_get_chip(desc);
>> + struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
>> + struct irq_domain *d = gc->irqdomain;
>> + int i;
>> +
>> + chained_irq_enter(chip, desc);
>> + for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
>> + u32 status;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(>irq_lock, flags);
>> + status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
>> + /* Manage only the interrupt that was enabled */
>> + status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
>> + spin_unlock_irqrestore(>irq_lock, flags);
>> + while (status) {
>> + u32 hwirq = ffs(status) - 1;
>> + u32 virq = irq_find_mapping(d, hwirq +
>> +i * GPIO_PER_REG);
>> +
>> + generic_handle_irq(virq);
>> + status &= ~BIT(hwirq);
>> + }
>
> You hae a problem here is a new IRQ appears while you are inside
> of this loop. You need to re-read the status register for each iteration
> (and &= with the IRQ_EN I guess).
If a new IRQ appears during the loop, then the irq handler will be
called again because the cause of this new IRQ won't have been acked
yet. So I think we're fine here.
>
>> +static int armada_37xx_irqchip_register(struct platform_device *pdev,
>> + struct armada_37xx_pinctrl *info)
>> +{
>> + struct device_node *np = info->dev->of_node;
>> + int nrirqs = info->data->nr_pins;
>> + struct gpio_chip *gc = >gpio_chip;
>> + struct irq_chip *irqchip = >irq_chip;
>> + struct resource res;
>> + int ret = -ENODEV, i, nr_irq_parent;
>> +
>
> This warrants a comment:
> /* Check if we have at least one gpio-controller child node */
>
OK
>> + for_each_child_of_node(info->dev->of_node, np) {
>> + if (of_find_property(np, "gpio-controller", NULL)) {
>> + ret = 0;
>> + break;
>> + }
>
> Rewrite:
>
> if (of_property_read_bool(np, "gpio-controller"))
>
OK
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH] clk: apn806: fix spelling mistake: "mising" -> "missing"
Hi Colin,
On mar., avril 11 2017, Colin King <colin.k...@canonical.com> wrote:
> From: Colin Ian King <colin.k...@canonical.com>
>
> trivial fix to spelling mistake in dev_warn message
>
> Fixes: f109ca864414dc ("clk: apn806: Turn the eMMC clock as optional for dts
> backwards compatible")
> Signed-off-by: Colin Ian King <colin.k...@canonical.com>
The intial patch was merged through the mmc subsystem while it modifies
a clk driver. So I would suggest either Ulf applying it or waiting for
v4.12-rc1 to apply the patch through the clk subsystem.
Gregory
> ---
> drivers/clk/mvebu/ap806-system-controller.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/mvebu/ap806-system-controller.c
> b/drivers/clk/mvebu/ap806-system-controller.c
> index 103fe18a3c29..8155baccc98e 100644
> --- a/drivers/clk/mvebu/ap806-system-controller.c
> +++ b/drivers/clk/mvebu/ap806-system-controller.c
> @@ -140,7 +140,7 @@ static int ap806_syscon_clk_probe(struct platform_device
> *pdev)
> 4, )) {
> ap806_clk_data.clk_num--;
> dev_warn(>dev,
> - "eMMC clock mising: update the device tree!\n");
> + "eMMC clock missing: update the device tree!\n");
> } else {
> ap806_clks[4] = clk_register_fixed_factor(NULL, name,
> fixedclk_name,
> --
> 2.11.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH] clk: apn806: fix spelling mistake: "mising" -> "missing"
Hi Colin,
On mar., avril 11 2017, Colin King wrote:
> From: Colin Ian King
>
> trivial fix to spelling mistake in dev_warn message
>
> Fixes: f109ca864414dc ("clk: apn806: Turn the eMMC clock as optional for dts
> backwards compatible")
> Signed-off-by: Colin Ian King
The intial patch was merged through the mmc subsystem while it modifies
a clk driver. So I would suggest either Ulf applying it or waiting for
v4.12-rc1 to apply the patch through the clk subsystem.
Gregory
> ---
> drivers/clk/mvebu/ap806-system-controller.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/mvebu/ap806-system-controller.c
> b/drivers/clk/mvebu/ap806-system-controller.c
> index 103fe18a3c29..8155baccc98e 100644
> --- a/drivers/clk/mvebu/ap806-system-controller.c
> +++ b/drivers/clk/mvebu/ap806-system-controller.c
> @@ -140,7 +140,7 @@ static int ap806_syscon_clk_probe(struct platform_device
> *pdev)
> 4, )) {
> ap806_clk_data.clk_num--;
> dev_warn(>dev,
> - "eMMC clock mising: update the device tree!\n");
> + "eMMC clock missing: update the device tree!\n");
> } else {
> ap806_clks[4] = clk_register_fixed_factor(NULL, name,
> fixedclk_name,
> --
> 2.11.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v5 0/4] gpio: mvebu: Add PWM fan support
Hi all,
On dim., avril 09 2017, Ralph Sennhauser <ralph.sennhau...@gmail.com> wrote:
> Hi Therry,
>
> Resending this as v5 with some minor changes since v4. What is missing is
> an ACK from you so Linus can merge the driver and Gregory the dts
> changes. For this driver to make it into 4.12 it would be nice to have
> it in next soon. I hope you can make some room in your schedule to have
> another look at this series.
If the other maintainer agree I can apply the arm-soc related patch (2,
3 and 4) to my mvebu branches. Actually even if the gpio driver is not
merged yet, these patches won't hurt. The only things I would like to
check is that the binding won't change.
Thanks,
Gregory
>
> Thanks
> Ralph
>
> ---
>
> Notes:
>
> About npwm = 1:
> The only way I can think of to achieve that requires reading the
> GPIO line from the device tree. This would prevent a user to
> dynamically choose a line. Which is fine for the fan found on Mamba
> but let's take some development board with freely accessible GPIOs
> and suddenly we limit the use of this driver. Given the above, npwm
> = ngpio with only one usable at a time is a more accurate
> description of the situation. The only downside is some "wasted"
> space.
>
> About the new compatible string:
> Orion was chosen for the SoC variant for the same reason as in
> commit 5f79c651e81e ("arm: mvebu: use global interrupts for GPIOs on
> Armada XP").
> The "pwm" property remains optional for the new compatible string so
> the compatiple string "marvell,armada-370-xp-gpio" can be used by
> all and not just the first two GPIO chips. A property to select "Set
> A" / "Set B" registers could be invented though.
>
> ---
>
> Pending:
> * Needs ACK from Thierry Reding to be merged via linux-gpio tree by Linus
> Walleij. (fine with the general approach, requested changes which
> should have been taken care of now)
>
> ---
>
> Changes v4->v5:
> All
> * add Tested-by: Andrew Lunn <and...@lunn.ch>, thanks
> Patch 2/4 mvebu: xp: Add PWM properties to .dtsi files
> * keep the old compatible stings, we don't have to drop them,
> therefore keep them (suggested by Gregory CLEMENT)
> * subject starts with ARM: dts: mvebu: (suggested by Gregory CLEMENT)
> Patch 4/4 mvebu: wrt1900ac: Use pwm-fan rather than gpio-fan
> * subject starts with ARM: dts: armada-xp: (suggested by Gregory CLEMENT)
>
> Changes v3->v4:
> Patch 1/4 gpio: mvebu: Add limited PWM support:
> * braces for both branches in if statement if one needs it. (suggested
> by Andrew Lunn)
> * introduce compatible string marvell,armada-370-xp-gpio (suggest by
> Rob Herring)
> * fix mvebu_pwmreg_blink_on_duration -> mvebu_pwmreg_blink_off_duration
> for period callculation in mvebu_pwm_get_state()
> Patch 4/4 mvebu: wrt1900ac: Use pwm-fan rather than gpio-fan
> * Drop flags from pwms for Mamba, as no longer used (suggested by
> Andrew Lunn)
> * Use again #pwm-cell = 2, the second cell is actually the period.
>
> Changes v2->v3:
> Patch 1/4 gpio: mvebu: Add limited PWM support:
> * drop pin from mvebu_pwn, can be infered (suggested by Thierry Reding)
> * rename pwm to mvpwm so pwm can be used for pwm_device as in the API,
> avoids some mental gymnastic.
> * drop id from struct mvebu_gpio_chip, select blink counter in
> mvebu_pwm_probe for all lines instead. We do not care about the
> unused ones. I think a clear improvement in readability.
> Makes coming up with a good comment simple as well.
> * Switch to new atomic PWM API (suggested by Thierry Reding)
> * rename use mvebu_gpioreg_blink_select to
> mvebu_gpioreg_blink_counter_select.
> * mark *_suspend() / *_resume() as __maybe_unused (suggested by Linus
> Walleij)
> * document #pwm-cells = 1 (suggested by Thierry Reding)
> Patch 2/4 mvebu: xp: Add PWM properties to .dtsi files
> * add missing reg-names / #pwm-cell properties to
> armada-xp-mv78260.dtsi gpio1 node
> * set pwm-cells = 1 (suggested by Thierry Reding)
> All:
> * always uppercase GPIO/PWM in prose (suggested by Thierry Reding)
>
> Changes v1 -> v2:
> Patch 1/4 gpio: mvebu: Add limited PWM support:
> * use BIT macro (suggested by Linus Walleij)
> * move id from struct mvebu_pwm to struct mvebu_gpio_chip, implement
> blink select as if else and comment on the chip id for code clarity
> (to accommodate Linus Walleijs request for a code clarification /
> comment. If you can wor
Re: [PATCH v5 0/4] gpio: mvebu: Add PWM fan support
Hi all,
On dim., avril 09 2017, Ralph Sennhauser wrote:
> Hi Therry,
>
> Resending this as v5 with some minor changes since v4. What is missing is
> an ACK from you so Linus can merge the driver and Gregory the dts
> changes. For this driver to make it into 4.12 it would be nice to have
> it in next soon. I hope you can make some room in your schedule to have
> another look at this series.
If the other maintainer agree I can apply the arm-soc related patch (2,
3 and 4) to my mvebu branches. Actually even if the gpio driver is not
merged yet, these patches won't hurt. The only things I would like to
check is that the binding won't change.
Thanks,
Gregory
>
> Thanks
> Ralph
>
> ---
>
> Notes:
>
> About npwm = 1:
> The only way I can think of to achieve that requires reading the
> GPIO line from the device tree. This would prevent a user to
> dynamically choose a line. Which is fine for the fan found on Mamba
> but let's take some development board with freely accessible GPIOs
> and suddenly we limit the use of this driver. Given the above, npwm
> = ngpio with only one usable at a time is a more accurate
> description of the situation. The only downside is some "wasted"
> space.
>
> About the new compatible string:
> Orion was chosen for the SoC variant for the same reason as in
> commit 5f79c651e81e ("arm: mvebu: use global interrupts for GPIOs on
> Armada XP").
> The "pwm" property remains optional for the new compatible string so
> the compatiple string "marvell,armada-370-xp-gpio" can be used by
> all and not just the first two GPIO chips. A property to select "Set
> A" / "Set B" registers could be invented though.
>
> ---
>
> Pending:
> * Needs ACK from Thierry Reding to be merged via linux-gpio tree by Linus
> Walleij. (fine with the general approach, requested changes which
> should have been taken care of now)
>
> ---
>
> Changes v4->v5:
> All
> * add Tested-by: Andrew Lunn , thanks
> Patch 2/4 mvebu: xp: Add PWM properties to .dtsi files
> * keep the old compatible stings, we don't have to drop them,
> therefore keep them (suggested by Gregory CLEMENT)
> * subject starts with ARM: dts: mvebu: (suggested by Gregory CLEMENT)
> Patch 4/4 mvebu: wrt1900ac: Use pwm-fan rather than gpio-fan
> * subject starts with ARM: dts: armada-xp: (suggested by Gregory CLEMENT)
>
> Changes v3->v4:
> Patch 1/4 gpio: mvebu: Add limited PWM support:
> * braces for both branches in if statement if one needs it. (suggested
> by Andrew Lunn)
> * introduce compatible string marvell,armada-370-xp-gpio (suggest by
> Rob Herring)
> * fix mvebu_pwmreg_blink_on_duration -> mvebu_pwmreg_blink_off_duration
> for period callculation in mvebu_pwm_get_state()
> Patch 4/4 mvebu: wrt1900ac: Use pwm-fan rather than gpio-fan
> * Drop flags from pwms for Mamba, as no longer used (suggested by
> Andrew Lunn)
> * Use again #pwm-cell = 2, the second cell is actually the period.
>
> Changes v2->v3:
> Patch 1/4 gpio: mvebu: Add limited PWM support:
> * drop pin from mvebu_pwn, can be infered (suggested by Thierry Reding)
> * rename pwm to mvpwm so pwm can be used for pwm_device as in the API,
> avoids some mental gymnastic.
> * drop id from struct mvebu_gpio_chip, select blink counter in
> mvebu_pwm_probe for all lines instead. We do not care about the
> unused ones. I think a clear improvement in readability.
> Makes coming up with a good comment simple as well.
> * Switch to new atomic PWM API (suggested by Thierry Reding)
> * rename use mvebu_gpioreg_blink_select to
> mvebu_gpioreg_blink_counter_select.
> * mark *_suspend() / *_resume() as __maybe_unused (suggested by Linus
> Walleij)
> * document #pwm-cells = 1 (suggested by Thierry Reding)
> Patch 2/4 mvebu: xp: Add PWM properties to .dtsi files
> * add missing reg-names / #pwm-cell properties to
> armada-xp-mv78260.dtsi gpio1 node
> * set pwm-cells = 1 (suggested by Thierry Reding)
> All:
> * always uppercase GPIO/PWM in prose (suggested by Thierry Reding)
>
> Changes v1 -> v2:
> Patch 1/4 gpio: mvebu: Add limited PWM support:
> * use BIT macro (suggested by Linus Walleij)
> * move id from struct mvebu_pwm to struct mvebu_gpio_chip, implement
> blink select as if else and comment on the chip id for code clarity
> (to accommodate Linus Walleijs request for a code clarification /
> comment. If you can word it better I'm all ears.)
> * Move function c
Re: [PATCH v2] ARM: dts: armada-38x: label USB and SATA nodes
Hi Ralph,
On sam., avril 08 2017, Ralph Sennhauser <ralph.sennhau...@gmail.com> wrote:
> Recently most nodes got labels to make them referenceable. The USB 3.0
> nodes as well as the nodes for the SATA controllers were left out,
> rectify the omission.
>
> The labels "sataX" are already used by some boards for the SATA ports,
> therefore use "ahciX" to label the SATA controller nodes.
>
> To avoid potential confusion by labeling an USB3.0 controller "usb2" use
> usb3_X as labels. This also coincides with the node names themselves
> (usb@x vs usb3@x).
>
> Signed-off-by: Ralph Sennhauser <ralph.sennhau...@gmail.com>
Applied on mvebu/dt
Thanks,
Gregory
> ---
>
> Hi everybody,
>
> Using satacX for controllers with satacXpY for ports might have been a
> possiblity, since ahciX is already used similarly (to avoid a conflict
> with current use of sataX) ahciX seems the better choice. Works well me
> thinks.
>
> The usb3_X labels still seem the best choice even though they aren't
> perfectly consitent, however, I don't see an alternative which would fit
> this requirement either.
>
> Regards
> Ralph
>
> ---
>
> Changes v1 -> v2:
> * use ahciX instead of satacX for the SATA controller nodes (suggested
> by Andrew Lunn)
>
>
> arch/arm/boot/dts/armada-38x.dtsi | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi
> b/arch/arm/boot/dts/armada-38x.dtsi
> index ba27ec1..8b165c3 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -530,7 +530,7 @@
> interrupts = ;
> };
>
> - sata@a8000 {
> + ahci0: sata@a8000 {
> compatible = "marvell,armada-380-ahci";
> reg = <0xa8000 0x2000>;
> interrupts = ;
> @@ -546,7 +546,7 @@
> status = "disabled";
> };
>
> - sata@e {
> + ahci1: sata@e {
> compatible = "marvell,armada-380-ahci";
> reg = <0xe 0x2000>;
> interrupts = ;
> @@ -590,7 +590,7 @@
> status = "disabled";
> };
>
> - usb3@f {
> + usb3_0: usb3@f {
> compatible = "marvell,armada-380-xhci";
> reg = <0xf 0x4000>,<0xf4000 0x4000>;
> interrupts = ;
> @@ -598,7 +598,7 @@
> status = "disabled";
> };
>
> - usb3@f8000 {
> + usb3_1: usb3@f8000 {
> compatible = "marvell,armada-380-xhci";
> reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
> interrupts = ;
> --
> 2.10.2
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v2] ARM: dts: armada-38x: label USB and SATA nodes
Hi Ralph,
On sam., avril 08 2017, Ralph Sennhauser wrote:
> Recently most nodes got labels to make them referenceable. The USB 3.0
> nodes as well as the nodes for the SATA controllers were left out,
> rectify the omission.
>
> The labels "sataX" are already used by some boards for the SATA ports,
> therefore use "ahciX" to label the SATA controller nodes.
>
> To avoid potential confusion by labeling an USB3.0 controller "usb2" use
> usb3_X as labels. This also coincides with the node names themselves
> (usb@x vs usb3@x).
>
> Signed-off-by: Ralph Sennhauser
Applied on mvebu/dt
Thanks,
Gregory
> ---
>
> Hi everybody,
>
> Using satacX for controllers with satacXpY for ports might have been a
> possiblity, since ahciX is already used similarly (to avoid a conflict
> with current use of sataX) ahciX seems the better choice. Works well me
> thinks.
>
> The usb3_X labels still seem the best choice even though they aren't
> perfectly consitent, however, I don't see an alternative which would fit
> this requirement either.
>
> Regards
> Ralph
>
> ---
>
> Changes v1 -> v2:
> * use ahciX instead of satacX for the SATA controller nodes (suggested
> by Andrew Lunn)
>
>
> arch/arm/boot/dts/armada-38x.dtsi | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi
> b/arch/arm/boot/dts/armada-38x.dtsi
> index ba27ec1..8b165c3 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -530,7 +530,7 @@
> interrupts = ;
> };
>
> - sata@a8000 {
> + ahci0: sata@a8000 {
> compatible = "marvell,armada-380-ahci";
> reg = <0xa8000 0x2000>;
> interrupts = ;
> @@ -546,7 +546,7 @@
> status = "disabled";
> };
>
> - sata@e {
> + ahci1: sata@e {
> compatible = "marvell,armada-380-ahci";
> reg = <0xe 0x2000>;
> interrupts = ;
> @@ -590,7 +590,7 @@
> status = "disabled";
> };
>
> - usb3@f {
> + usb3_0: usb3@f {
> compatible = "marvell,armada-380-xhci";
> reg = <0xf 0x4000>,<0xf4000 0x4000>;
> interrupts = ;
> @@ -598,7 +598,7 @@
> status = "disabled";
> };
>
> - usb3@f8000 {
> + usb3_1: usb3@f8000 {
> compatible = "marvell,armada-380-xhci";
> reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
> interrupts = ;
> --
> 2.10.2
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: linux-next: manual merge of the mvebu tree with the arm-soc tree
Hi Olof and Arnd,
On mer., avril 12 2017, Stephen Rothwell <s...@canb.auug.org.au> wrote:
> Hi all,
>
> Today's linux-next merge of the mvebu tree got a conflict in:
>
> arch/arm64/configs/defconfig
>
> between commit:
>
> 3c9d36192802 ("arm64: set CONFIG_MMC_BCM2835=y in defconfig")
>
> from the arm-soc tree and commit:
>
> 6ff829553345 ("arm64: configs: enable SDHCI driver for Xenon")
>
> from the mvebu tree.
How do you want to proceed with this conflict?
Do you want that I merged arm-soc/next/arm64 in my mvebu/defconfig64
branch before applying my patch ?
Or do you prefer that I continue to base my branch on v4.11-rc1 and then
you will take care of the conflict when pulling the branch?
Thanks,
Gregory
>
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging. You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
>
> BTW, that arm-soc commit has no Signed-off-by from its committer :-(
>
> --
> Cheers,
> Stephen Rothwell
>
> diff --cc arch/arm64/configs/defconfig
> index ab4461b6b226,93b0aab959c0..
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@@ -402,7 -401,7 +402,8 @@@ CONFIG_MMC_DW_EXYNOS=
> CONFIG_MMC_DW_K3=y
> CONFIG_MMC_DW_ROCKCHIP=y
> CONFIG_MMC_SUNXI=y
> +CONFIG_MMC_BCM2835=y
> + CONFIG_MMC_SDHCI_XENON=y
> CONFIG_NEW_LEDS=y
> CONFIG_LEDS_CLASS=y
> CONFIG_LEDS_GPIO=y
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: linux-next: manual merge of the mvebu tree with the arm-soc tree
Hi Olof and Arnd,
On mer., avril 12 2017, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the mvebu tree got a conflict in:
>
> arch/arm64/configs/defconfig
>
> between commit:
>
> 3c9d36192802 ("arm64: set CONFIG_MMC_BCM2835=y in defconfig")
>
> from the arm-soc tree and commit:
>
> 6ff829553345 ("arm64: configs: enable SDHCI driver for Xenon")
>
> from the mvebu tree.
How do you want to proceed with this conflict?
Do you want that I merged arm-soc/next/arm64 in my mvebu/defconfig64
branch before applying my patch ?
Or do you prefer that I continue to base my branch on v4.11-rc1 and then
you will take care of the conflict when pulling the branch?
Thanks,
Gregory
>
> I fixed it up (see below) and can carry the fix as necessary. This
> is now fixed as far as linux-next is concerned, but any non trivial
> conflicts should be mentioned to your upstream maintainer when your tree
> is submitted for merging. You may also want to consider cooperating
> with the maintainer of the conflicting tree to minimise any particularly
> complex conflicts.
>
> BTW, that arm-soc commit has no Signed-off-by from its committer :-(
>
> --
> Cheers,
> Stephen Rothwell
>
> diff --cc arch/arm64/configs/defconfig
> index ab4461b6b226,93b0aab959c0..
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@@ -402,7 -401,7 +402,8 @@@ CONFIG_MMC_DW_EXYNOS=
> CONFIG_MMC_DW_K3=y
> CONFIG_MMC_DW_ROCKCHIP=y
> CONFIG_MMC_SUNXI=y
> +CONFIG_MMC_BCM2835=y
> + CONFIG_MMC_SDHCI_XENON=y
> CONFIG_NEW_LEDS=y
> CONFIG_LEDS_CLASS=y
> CONFIG_LEDS_GPIO=y
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v4 1/7] pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
Hi Linus,
On lun., avril 10 2017, Rob Herring <r...@kernel.org> wrote:
> On Wed, Apr 05, 2017 at 05:18:02PM +0200, Gregory CLEMENT wrote:
>> +Example:
>> +pinctrl_sb: pinctrl-sb@18800 {
>
> Just pinctrl@...
>
>> +compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
>> +reg = <0x18800 0x100>, <0x18C00 0x20>;
>> +gpiosb: gpiosb {
>
> gpio {
>
> With that,
>
> Acked-by: Rob Herring <r...@kernel.org>
Could you do this change while applying the patches, or do you want a
new series?
Also, if the binding is also OK for you, do you agree that I apply the
last 2 patches on the mvebu trees? (of course with the same changes
asked by Rob)
Thanks,
Gregory
>
>
>> +#gpio-cells = <2>;
>> +gpio-ranges = <_sb 0 0 29>;
>> +gpio-controller;
>> +interrupts =
>> +,
>> +,
>> +,
>> +,
>> + ;
>> +};
>> +
>> +rgmii_pins: mii-pins {
>> +groups = "rgmii";
>> +function = "mii";
>> +};
>> +
>> +};
>> --
>> git-series 0.9.1
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v4 1/7] pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
Hi Linus,
On lun., avril 10 2017, Rob Herring wrote:
> On Wed, Apr 05, 2017 at 05:18:02PM +0200, Gregory CLEMENT wrote:
>> +Example:
>> +pinctrl_sb: pinctrl-sb@18800 {
>
> Just pinctrl@...
>
>> +compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
>> +reg = <0x18800 0x100>, <0x18C00 0x20>;
>> +gpiosb: gpiosb {
>
> gpio {
>
> With that,
>
> Acked-by: Rob Herring
Could you do this change while applying the patches, or do you want a
new series?
Also, if the binding is also OK for you, do you agree that I apply the
last 2 patches on the mvebu trees? (of course with the same changes
asked by Rob)
Thanks,
Gregory
>
>
>> +#gpio-cells = <2>;
>> +gpio-ranges = <_sb 0 0 29>;
>> +gpio-controller;
>> +interrupts =
>> +,
>> +,
>> +,
>> +,
>> + ;
>> + };
>> +
>> +rgmii_pins: mii-pins {
>> +groups = "rgmii";
>> +function = "mii";
>> +};
>> +
>> +};
>> --
>> git-series 0.9.1
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v7 00/13] mmc: Add support to Marvell Xenon SD Host Controller
Hi Ulf, On lun., avril 10 2017, Ulf Hansson <ulf.hans...@linaro.org> wrote: > On 30 March 2017 at 17:22, Gregory CLEMENT > <gregory.clem...@free-electrons.com> wrote: >> Hello, >> >> This the seventh version of the series adding support for the SDHCI >> Xenon controller. It can be currently found on the Armada 37xx and the >> Armada 7K/8K but will be also used in more Marvell SoC (and not only >> the mvebu ones actually). >> >> v6->v7: >> - Add comments on vqmmc and vmmc in examples in dt binding doc. >> >> - Fix all the issues pointed out by Ulf and Adrian: >> >>- Align the prefix of function and variable names. >>- Replace the if-else with switch statements when checking MMC_TIMING_* >>- Remove the spinlocks in set_ios. >>- Optimize the delay loop as Adrian patch does. >>- Add release of phy params structures >> >> - Add check of Vqmmc supply in Xenon signal voltage switch. If Vqmmc >> regulator doesn't exist, skip standard SD signal voltage regulator >> switch process. >> >> - Remove parse of child node mmc-card. Wait for a better solution. >> >> v5->v6: >> >> - Add a generic "mmc-card" parse in core layer. >> >> - Fix the spelling issues in Xenon dt binding doc and drivers. >> >> - Remove descriptions to common mmc properties from Xenon dt binding >> doc. >> >> - Split compatible string "marvell,armada-8k-sdhci" into >> "marvell,armada-ap806-sdhci" and "marvell,armada-cp110-sdhci". >> >> - Also updates the example in Xenon dt binding doc. >> >> - Remove unnecessary dependency on MMC_SDHCI from Xenon entry in >> Kconfig. >> >> - Move Xenon specific dt parse into a separate function. >> >> - Adjust warnings and condition check in Xenon PHY setting, to remove >> fragile hs200->hs400/hs400->hs200 sequence check function. >> >> - Enable PHY Slow Mode in MMC_TIMING_LEGACY timing if PHY Slow Mode is >> required in dts. >> >> - Add a patch allowing dts backwards compatible for the clock >> >> v4->v5: >> >> - Remove the patch to export sdhci_execute_tuning(). It is already >> exported in v4.10. >> >> - Introduce a patch adding a missing clock for the sdhci controller >> present on the CP master for A7K/A8K. There is no build dependency >> but obviously this patch is need to use the sdhci controller present >> on the CP part. >> >> - Adjust Xenon return setup, to avoid being overwritten by >>sdhci_add_host(). >> >> - Change Xenon register definition prefix to "XENON_". >> >> - Fix typos in Xenon driver and dt-binding docs. >> >> - Change compatible string "marvell,armada-7000-sdhci" to >> "marvell,armada-8k-sdhci". Actually the Armada 7K SoCs are a subset >> of the Armada 8K SoCs. Moreover, the use of the '000' is not >> consistent with all the other compatible string already used for the >> Armada 7K/8K family. >> >> - Added the Tested-by from Russell King on an Armada 8K based board. >> >> v3 -> v4: >> For this version a few change have been done: >> - fixes 2 bug reported by kbuild-bot >> - remove extra of_node_put() >> - convert 0 in false for function returning boolean >> >> - add a device tree node for the sdhci controller present on the CP >> master for A7K/A8K. It also led to rename the sdhci0 node on AP to >> ap_sdhci0 to make a distinction with the one present on CP master. >> >> v2 -> v3 >> I think that now most (if not all) the remarks had been taking into >> account since the second version. According to Ziji Hu, here are the >> following changes: >> " Changes in V3: >> Adjust and improve Xenon DT bindings. Move some caps setting from driver >> into >> DT. Use mmc-card sub-node to represent eMMC type. >> Remove PHY Sampling Fixed Delay Line scan in lower speed mode. >> Improve Xenon probe and ->init_card() functions. >> Export sdhci_enable_sdio_irq() and implement own SDIO IRQ control. >> Split PHY patch into two smaller patches. >> Temporarily remove AXI clock before its implementation is improved." >> >> Besides this changes I also >> - Removed the sdhci-xenon-phy.h and moved its content in the >> shc-xenon-phy.c file. >> - Fixed the tuning-count usage >> - Managed the error case for clk_prepare_enable >> >> For the record the change from v1 was: >> "
Re: [PATCH v7 00/13] mmc: Add support to Marvell Xenon SD Host Controller
Hi Ulf, On lun., avril 10 2017, Ulf Hansson wrote: > On 30 March 2017 at 17:22, Gregory CLEMENT > wrote: >> Hello, >> >> This the seventh version of the series adding support for the SDHCI >> Xenon controller. It can be currently found on the Armada 37xx and the >> Armada 7K/8K but will be also used in more Marvell SoC (and not only >> the mvebu ones actually). >> >> v6->v7: >> - Add comments on vqmmc and vmmc in examples in dt binding doc. >> >> - Fix all the issues pointed out by Ulf and Adrian: >> >>- Align the prefix of function and variable names. >>- Replace the if-else with switch statements when checking MMC_TIMING_* >>- Remove the spinlocks in set_ios. >>- Optimize the delay loop as Adrian patch does. >>- Add release of phy params structures >> >> - Add check of Vqmmc supply in Xenon signal voltage switch. If Vqmmc >> regulator doesn't exist, skip standard SD signal voltage regulator >> switch process. >> >> - Remove parse of child node mmc-card. Wait for a better solution. >> >> v5->v6: >> >> - Add a generic "mmc-card" parse in core layer. >> >> - Fix the spelling issues in Xenon dt binding doc and drivers. >> >> - Remove descriptions to common mmc properties from Xenon dt binding >> doc. >> >> - Split compatible string "marvell,armada-8k-sdhci" into >> "marvell,armada-ap806-sdhci" and "marvell,armada-cp110-sdhci". >> >> - Also updates the example in Xenon dt binding doc. >> >> - Remove unnecessary dependency on MMC_SDHCI from Xenon entry in >> Kconfig. >> >> - Move Xenon specific dt parse into a separate function. >> >> - Adjust warnings and condition check in Xenon PHY setting, to remove >> fragile hs200->hs400/hs400->hs200 sequence check function. >> >> - Enable PHY Slow Mode in MMC_TIMING_LEGACY timing if PHY Slow Mode is >> required in dts. >> >> - Add a patch allowing dts backwards compatible for the clock >> >> v4->v5: >> >> - Remove the patch to export sdhci_execute_tuning(). It is already >> exported in v4.10. >> >> - Introduce a patch adding a missing clock for the sdhci controller >> present on the CP master for A7K/A8K. There is no build dependency >> but obviously this patch is need to use the sdhci controller present >> on the CP part. >> >> - Adjust Xenon return setup, to avoid being overwritten by >>sdhci_add_host(). >> >> - Change Xenon register definition prefix to "XENON_". >> >> - Fix typos in Xenon driver and dt-binding docs. >> >> - Change compatible string "marvell,armada-7000-sdhci" to >> "marvell,armada-8k-sdhci". Actually the Armada 7K SoCs are a subset >> of the Armada 8K SoCs. Moreover, the use of the '000' is not >> consistent with all the other compatible string already used for the >> Armada 7K/8K family. >> >> - Added the Tested-by from Russell King on an Armada 8K based board. >> >> v3 -> v4: >> For this version a few change have been done: >> - fixes 2 bug reported by kbuild-bot >> - remove extra of_node_put() >> - convert 0 in false for function returning boolean >> >> - add a device tree node for the sdhci controller present on the CP >> master for A7K/A8K. It also led to rename the sdhci0 node on AP to >> ap_sdhci0 to make a distinction with the one present on CP master. >> >> v2 -> v3 >> I think that now most (if not all) the remarks had been taking into >> account since the second version. According to Ziji Hu, here are the >> following changes: >> " Changes in V3: >> Adjust and improve Xenon DT bindings. Move some caps setting from driver >> into >> DT. Use mmc-card sub-node to represent eMMC type. >> Remove PHY Sampling Fixed Delay Line scan in lower speed mode. >> Improve Xenon probe and ->init_card() functions. >> Export sdhci_enable_sdio_irq() and implement own SDIO IRQ control. >> Split PHY patch into two smaller patches. >> Temporarily remove AXI clock before its implementation is improved." >> >> Besides this changes I also >> - Removed the sdhci-xenon-phy.h and moved its content in the >> shc-xenon-phy.c file. >> - Fixed the tuning-count usage >> - Managed the error case for clk_prepare_enable >> >> For the record the change from v1 was: >> " Changes in V2: >> rebase on v4.9-rc2. >> Re-write Xeno
Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support
Argh, I sill have the typo in the title of this patch! :(
If you are going to apply it could you fix it, else it will be fixed in
the next version.
Sorry,
Gregory
On mer., avril 05 2017, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> The Armada 37xx SoCs can handle interrupt through GPIO. However it can
> only manage the edge ones.
>
> The way the interrupt are managed are classical so we can use the generic
> interrupt chip model.
>
> The only unusual "feature" is that many interrupts are connected to the
> parent interrupt controller. But we do not take advantage of this and use
> the chained irq with all of them.
>
> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
> ---
> drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 221 +-
> 1 file changed, 221 insertions(+)
>
> diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> index 5c96f5558310..7356516e0921 100644
> --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> @@ -13,7 +13,9 @@
> #include
> #include
> #include
> +#include
> #include
> +#include
> #include
> #include
> #include
> @@ -30,6 +32,11 @@
> #define OUTPUT_CTL 0x20
> #define SELECTION0x30
>
> +#define IRQ_EN 0x0
> +#define IRQ_POL 0x08
> +#define IRQ_STATUS 0x10
> +#define IRQ_WKUP 0x18
> +
> #define NB_FUNCS 2
> #define GPIO_PER_REG 32
>
> @@ -75,9 +82,12 @@ struct armada_37xx_pmx_func {
>
> struct armada_37xx_pinctrl {
> struct regmap *regmap;
> + void __iomem*base;
> const struct armada_37xx_pin_data *data;
> struct device *dev;
> struct gpio_chipgpio_chip;
> + struct irq_chip irq_chip;
> + spinlock_t irq_lock;
> struct pinctrl_desc pctl;
> struct pinctrl_dev *pctl_dev;
> struct armada_37xx_pin_group*groups;
> @@ -346,6 +356,14 @@ static int armada_37xx_pmx_set(struct pinctrl_dev
> *pctldev,
> return armada_37xx_pmx_set_by_name(pctldev, name, grp);
> }
>
> +static inline void armada_37xx_irq_update_reg(unsigned int *reg,
> + struct irq_data *d)
> +{
> + int offset = irqd_to_hwirq(d);
> +
> + armada_37xx_update_reg(reg, offset);
> +}
> +
> static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
> unsigned int offset)
> {
> @@ -468,6 +486,206 @@ static const struct gpio_chip armada_37xx_gpiolib_chip
> = {
> .owner = THIS_MODULE,
> };
>
> +void armada_37xx_irq_ack(struct irq_data *d)
> +{
> + struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
> + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
> + u32 reg = IRQ_STATUS, mask = d->mask;
> + unsigned long flags;
> +
> + armada_37xx_irq_update_reg(, d);
> + spin_lock_irqsave(>irq_lock, flags);
> + writel(mask, info->base + reg);
> + spin_unlock_irqrestore(>irq_lock, flags);
> +}
> +
> +void armada_37xx_irq_mask(struct irq_data *d)
> +{
> + struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
> + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
> + u32 val, reg = IRQ_EN, mask = d->mask;
> + unsigned long flags;
> +
> + armada_37xx_irq_update_reg(, d);
> + spin_lock_irqsave(>irq_lock, flags);
> + val = readl(info->base + reg);
> + writel(val & ~mask, info->base + reg);
> + spin_unlock_irqrestore(>irq_lock, flags);
> +}
> +
> +void armada_37xx_irq_unmask(struct irq_data *d)
> +{
> + struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
> + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
> + u32 val, reg = IRQ_EN, mask = d->mask;
> + unsigned long flags;
> +
> + armada_37xx_irq_update_reg(, d);
> + spin_lock_irqsave(>irq_lock, flags);
> + val = readl(info->base + reg);
> + writel(val | mask, info->base + reg);
> + spin_unlock_irqrestore(>irq_lock, flags);
> +}
> +
> +static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
> +{
> + struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
> + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
> + u32 val, reg = IRQ_WKUP, mask = d->mask;
> + unsigned long flags;
> +
> + armada_37xx_irq_update_reg(, d);
> + spin_lock_irqsav
Re: [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support
Argh, I sill have the typo in the title of this patch! :(
If you are going to apply it could you fix it, else it will be fixed in
the next version.
Sorry,
Gregory
On mer., avril 05 2017, Gregory CLEMENT
wrote:
> The Armada 37xx SoCs can handle interrupt through GPIO. However it can
> only manage the edge ones.
>
> The way the interrupt are managed are classical so we can use the generic
> interrupt chip model.
>
> The only unusual "feature" is that many interrupts are connected to the
> parent interrupt controller. But we do not take advantage of this and use
> the chained irq with all of them.
>
> Signed-off-by: Gregory CLEMENT
> ---
> drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 221 +-
> 1 file changed, 221 insertions(+)
>
> diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> index 5c96f5558310..7356516e0921 100644
> --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> @@ -13,7 +13,9 @@
> #include
> #include
> #include
> +#include
> #include
> +#include
> #include
> #include
> #include
> @@ -30,6 +32,11 @@
> #define OUTPUT_CTL 0x20
> #define SELECTION0x30
>
> +#define IRQ_EN 0x0
> +#define IRQ_POL 0x08
> +#define IRQ_STATUS 0x10
> +#define IRQ_WKUP 0x18
> +
> #define NB_FUNCS 2
> #define GPIO_PER_REG 32
>
> @@ -75,9 +82,12 @@ struct armada_37xx_pmx_func {
>
> struct armada_37xx_pinctrl {
> struct regmap *regmap;
> + void __iomem*base;
> const struct armada_37xx_pin_data *data;
> struct device *dev;
> struct gpio_chipgpio_chip;
> + struct irq_chip irq_chip;
> + spinlock_t irq_lock;
> struct pinctrl_desc pctl;
> struct pinctrl_dev *pctl_dev;
> struct armada_37xx_pin_group*groups;
> @@ -346,6 +356,14 @@ static int armada_37xx_pmx_set(struct pinctrl_dev
> *pctldev,
> return armada_37xx_pmx_set_by_name(pctldev, name, grp);
> }
>
> +static inline void armada_37xx_irq_update_reg(unsigned int *reg,
> + struct irq_data *d)
> +{
> + int offset = irqd_to_hwirq(d);
> +
> + armada_37xx_update_reg(reg, offset);
> +}
> +
> static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
> unsigned int offset)
> {
> @@ -468,6 +486,206 @@ static const struct gpio_chip armada_37xx_gpiolib_chip
> = {
> .owner = THIS_MODULE,
> };
>
> +void armada_37xx_irq_ack(struct irq_data *d)
> +{
> + struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
> + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
> + u32 reg = IRQ_STATUS, mask = d->mask;
> + unsigned long flags;
> +
> + armada_37xx_irq_update_reg(, d);
> + spin_lock_irqsave(>irq_lock, flags);
> + writel(mask, info->base + reg);
> + spin_unlock_irqrestore(>irq_lock, flags);
> +}
> +
> +void armada_37xx_irq_mask(struct irq_data *d)
> +{
> + struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
> + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
> + u32 val, reg = IRQ_EN, mask = d->mask;
> + unsigned long flags;
> +
> + armada_37xx_irq_update_reg(, d);
> + spin_lock_irqsave(>irq_lock, flags);
> + val = readl(info->base + reg);
> + writel(val & ~mask, info->base + reg);
> + spin_unlock_irqrestore(>irq_lock, flags);
> +}
> +
> +void armada_37xx_irq_unmask(struct irq_data *d)
> +{
> + struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
> + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
> + u32 val, reg = IRQ_EN, mask = d->mask;
> + unsigned long flags;
> +
> + armada_37xx_irq_update_reg(, d);
> + spin_lock_irqsave(>irq_lock, flags);
> + val = readl(info->base + reg);
> + writel(val | mask, info->base + reg);
> + spin_unlock_irqrestore(>irq_lock, flags);
> +}
> +
> +static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
> +{
> + struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
> + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
> + u32 val, reg = IRQ_WKUP, mask = d->mask;
> + unsigned long flags;
> +
> + armada_37xx_irq_update_reg(, d);
> + spin_lock_irqsave(>irq_lock, flags);
> + val = readl(info->base + reg);
> + if (on
Re: [PATCH] ARM: dts: armada-38x: label USB and SATA nodes
Hi Andrew,
On ven., mars 31 2017, Andrew Lunn <and...@lunn.ch> wrote:
> On Fri, Mar 31, 2017 at 07:39:20PM +0200, Ralph Sennhauser wrote:
>> On Fri, 31 Mar 2017 18:50:15 +0200
>> Andrew Lunn <and...@lunn.ch> wrote:
>>
>> > > -sata@a8000 {
>> > > +satac0: sata@a8000 {
>> >
>> > Hi Ralph
>> >
>> > Why the c in satac0?
>>
>> For controller and to not conflict with a use case of sata0 for a port,
>> similarly to pciec and pcie1. See armada-385-synology-ds116.dts.
>
> :~/linux/arch/arm/boot/dts$ ls *ds116*
> ls: cannot access '*ds116*': No such file or directory
>
> But anyway, a few boards seem to solve this by calling the controller
> node ahci0: and the port sata0:
>
>> > > -usb3@f {
>> > > +usb3_0: usb3@f {
>> > > compatible =
>> > > "marvell,armada-380-xhci"; reg = <0xf 0x4000>,<0xf4000 0x4000>;
>> > > interrupts = > > > IRQ_TYPE_LEVEL_HIGH>; @@ -598,7 +598,7 @@
>> > > status = "disabled";
>> > > };
>> > >
>> > > -usb3@f8000 {
>> > > +usb3_1: usb3@f8000 {
>> > > compatible =
>> > > "marvell,armada-380-xhci"; reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
>> > > interrupts = > > > IRQ_TYPE_LEVEL_HIGH>;
>> >
>> > I can understand what you are saying. But does anybody else care? Are
>> > there other .dtsi files differentiating between USB 1.1, 2 and 3?
>>
>> It's handled differently where ever I looked, some do some don't. A
>> case for distinguishing USB 2.0 and USB 3.0 like this is
>> armada-388-gp.dts.
Actually I care and I found confusing calling usb2 the second usb port if
it is controlled by an USB3 controller.
>
> Humm...
>
> /* CON4 */
> usb@58000 {
> vcc-supply = <_usb2_0_vbus>;
> status = "okay";
> };
>
>
> /* CON5 */
> usb3@f {
> usb-phy = <_1_phy>;
> status = "okay";
> };
>
> /* CON7 */
> usb3@f8000 {
> usb-phy = <_phy>;
> status = "okay";
> };
>
> Is this clear? Is CON5 a USB 3 host, but has a USB 2 PHY connected to
> it? CON7 is the only true USB 3 port? I think some comments written in
I can answer it: CON5 is indeed an USB3 host with a USB2 PHY connected
to it so we can use it only as an USB2. And indeed CON7 is the only true
USB3 port.
> schwiizerdütsch would be clearre.:-)
Actually all your assumption were correct so maybe it is not as
confusing as it looks! :) But I can add a comment if needed.
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH] ARM: dts: armada-38x: label USB and SATA nodes
Hi Andrew,
On ven., mars 31 2017, Andrew Lunn wrote:
> On Fri, Mar 31, 2017 at 07:39:20PM +0200, Ralph Sennhauser wrote:
>> On Fri, 31 Mar 2017 18:50:15 +0200
>> Andrew Lunn wrote:
>>
>> > > -sata@a8000 {
>> > > +satac0: sata@a8000 {
>> >
>> > Hi Ralph
>> >
>> > Why the c in satac0?
>>
>> For controller and to not conflict with a use case of sata0 for a port,
>> similarly to pciec and pcie1. See armada-385-synology-ds116.dts.
>
> :~/linux/arch/arm/boot/dts$ ls *ds116*
> ls: cannot access '*ds116*': No such file or directory
>
> But anyway, a few boards seem to solve this by calling the controller
> node ahci0: and the port sata0:
>
>> > > -usb3@f {
>> > > +usb3_0: usb3@f {
>> > > compatible =
>> > > "marvell,armada-380-xhci"; reg = <0xf 0x4000>,<0xf4000 0x4000>;
>> > > interrupts = > > > IRQ_TYPE_LEVEL_HIGH>; @@ -598,7 +598,7 @@
>> > > status = "disabled";
>> > > };
>> > >
>> > > -usb3@f8000 {
>> > > +usb3_1: usb3@f8000 {
>> > > compatible =
>> > > "marvell,armada-380-xhci"; reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
>> > > interrupts = > > > IRQ_TYPE_LEVEL_HIGH>;
>> >
>> > I can understand what you are saying. But does anybody else care? Are
>> > there other .dtsi files differentiating between USB 1.1, 2 and 3?
>>
>> It's handled differently where ever I looked, some do some don't. A
>> case for distinguishing USB 2.0 and USB 3.0 like this is
>> armada-388-gp.dts.
Actually I care and I found confusing calling usb2 the second usb port if
it is controlled by an USB3 controller.
>
> Humm...
>
> /* CON4 */
> usb@58000 {
> vcc-supply = <_usb2_0_vbus>;
> status = "okay";
> };
>
>
> /* CON5 */
> usb3@f {
> usb-phy = <_1_phy>;
> status = "okay";
> };
>
> /* CON7 */
> usb3@f8000 {
> usb-phy = <_phy>;
> status = "okay";
> };
>
> Is this clear? Is CON5 a USB 3 host, but has a USB 2 PHY connected to
> it? CON7 is the only true USB 3 port? I think some comments written in
I can answer it: CON5 is indeed an USB3 host with a USB2 PHY connected
to it so we can use it only as an USB2. And indeed CON7 is the only true
USB3 port.
> schwiizerdütsch would be clearre.:-)
Actually all your assumption were correct so maybe it is not as
confusing as it looks! :) But I can add a comment if needed.
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH] ARM: dts: armada-385-linksys: disk-activity trigger for all
Hi Ralph,
On ven., mars 31 2017, Andrew Lunn <and...@lunn.ch> wrote:
> On Thu, Mar 30, 2017 at 06:54:04PM +0200, Ralph Sennhauser wrote:
>> Commit a4ee7e18d808 ("ARM: dts: armada: Add default trigger for sata
>> led") adds the default trigger to individual boards, move it to
>> armada-385-linksys.dtsi which effectively enables the definition for
>> the WRT1900ACS (Shelby) as well as for future boards.
>>
>> Signed-off-by: Ralph Sennhauser <ralph.sennhau...@gmail.com>
>
> Centralising this makes sense.
>
> Reviewed-by: Andrew Lunn <and...@lunn.ch>
Applied on mvebu/dt
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH] ARM: dts: armada-385-linksys: disk-activity trigger for all
Hi Ralph,
On ven., mars 31 2017, Andrew Lunn wrote:
> On Thu, Mar 30, 2017 at 06:54:04PM +0200, Ralph Sennhauser wrote:
>> Commit a4ee7e18d808 ("ARM: dts: armada: Add default trigger for sata
>> led") adds the default trigger to individual boards, move it to
>> armada-385-linksys.dtsi which effectively enables the definition for
>> the WRT1900ACS (Shelby) as well as for future boards.
>>
>> Signed-off-by: Ralph Sennhauser
>
> Centralising this makes sense.
>
> Reviewed-by: Andrew Lunn
Applied on mvebu/dt
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
[PATCH v4 0/7] Add support for pinctrl/gpio on Armada 37xx
Hi, In this forth version I improved the driver based on the review from Linus Walleij and I fixed a configuration issue with uart2. For the record, this series adds support for the pin and gpio controllers present on the Armada 37xx SoCs. Each Armada 37xx SoC comes with 2 pin controllers: one on the south bridge (managing 28 pins) and one on the north bridge (managing 36 pins). At the hardware level the controller configure the pins by group and not pin by pin. The gpio controller is also capable to handle interrupt from gpio. Changelog v3 -> v4 - Some group are configured by several bits in the register: extend the armada_37xx_pin_group struct to manage it. - Fix the uart2 and cspi2/3 configuration - Document the armada_37xx_add_function(), armada_37xx_fill_group() and armada_37xx_fill_funcs(). - Use devm_gpiochip_add_data() - Use irq_find_mapping instead of irq_linear_revmap - Use handle_edge_irq instead of the wrong handle_level_irq - Add comment about the fact the we have multiple parent interrupt - Add comment about the mask usage of the irq_data struct - Use BIT() macro when possible - Select more CONFIG symbol needed for GPIO and interrupt support v2 -> v3 - use gpio-ranges (patch 4) - Document gpio-ranges usage (patch 1) - do not use anymore a global pin index (patch 3) v1 -> v2: - Update binding documentation making clear that mfd and syscon must be used (patch 1). - Split the fist patch adding pin controller support for Armada 37xx in arm64 part (for kconfig) and pinctrl part (patch 2 and 3) - Add MFD_SYSCON dependency (patch 3) - Add kerneldoc for the armada_37xx_pin_group struct (patch 3) - Rename _add_function() to armada_37xx_add_function() (patch 3) - Use an inline function to update the reg offset (patch 4) - Rename gpiolib_register to gpiochip_register (patch 4) - Add a comment about the two registers limit (patch 4) - Add explicit gpio node in the device tree (patch 4) - Convert the driver to use GPIOLIB_IRQCHIP (patch 5) - Add a critical section when accessing the hardware registers (patch 5) - Use the gpio subnode (patch 5) Thanks, Gregory Gregory CLEMENT (7): pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers arm64: marvell: enable the Armada 37xx pinctrl driver pinctrl: armada-37xx: Add pin controller support for Armada 37xx pinctrl: armada-37xx: Add gpio support pinctrl: aramda-37xx: Add irqchip support ARM64: dts: marvell: Add pinctrl nodes for Armada 3700 ARM64: dts: marvell: armada37xx: add pinctrl definition Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt | 7 +- Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt | 183 ++- arch/arm64/Kconfig.platforms | 5 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts| 8 +- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 73 - drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/mvebu/Kconfig | 7 +- drivers/pinctrl/mvebu/Makefile| 3 +- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 969 - 9 files changed, 1249 insertions(+), 8 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c base-commit: c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201 -- git-series 0.9.1
[PATCH v4 0/7] Add support for pinctrl/gpio on Armada 37xx
Hi, In this forth version I improved the driver based on the review from Linus Walleij and I fixed a configuration issue with uart2. For the record, this series adds support for the pin and gpio controllers present on the Armada 37xx SoCs. Each Armada 37xx SoC comes with 2 pin controllers: one on the south bridge (managing 28 pins) and one on the north bridge (managing 36 pins). At the hardware level the controller configure the pins by group and not pin by pin. The gpio controller is also capable to handle interrupt from gpio. Changelog v3 -> v4 - Some group are configured by several bits in the register: extend the armada_37xx_pin_group struct to manage it. - Fix the uart2 and cspi2/3 configuration - Document the armada_37xx_add_function(), armada_37xx_fill_group() and armada_37xx_fill_funcs(). - Use devm_gpiochip_add_data() - Use irq_find_mapping instead of irq_linear_revmap - Use handle_edge_irq instead of the wrong handle_level_irq - Add comment about the fact the we have multiple parent interrupt - Add comment about the mask usage of the irq_data struct - Use BIT() macro when possible - Select more CONFIG symbol needed for GPIO and interrupt support v2 -> v3 - use gpio-ranges (patch 4) - Document gpio-ranges usage (patch 1) - do not use anymore a global pin index (patch 3) v1 -> v2: - Update binding documentation making clear that mfd and syscon must be used (patch 1). - Split the fist patch adding pin controller support for Armada 37xx in arm64 part (for kconfig) and pinctrl part (patch 2 and 3) - Add MFD_SYSCON dependency (patch 3) - Add kerneldoc for the armada_37xx_pin_group struct (patch 3) - Rename _add_function() to armada_37xx_add_function() (patch 3) - Use an inline function to update the reg offset (patch 4) - Rename gpiolib_register to gpiochip_register (patch 4) - Add a comment about the two registers limit (patch 4) - Add explicit gpio node in the device tree (patch 4) - Convert the driver to use GPIOLIB_IRQCHIP (patch 5) - Add a critical section when accessing the hardware registers (patch 5) - Use the gpio subnode (patch 5) Thanks, Gregory Gregory CLEMENT (7): pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers arm64: marvell: enable the Armada 37xx pinctrl driver pinctrl: armada-37xx: Add pin controller support for Armada 37xx pinctrl: armada-37xx: Add gpio support pinctrl: aramda-37xx: Add irqchip support ARM64: dts: marvell: Add pinctrl nodes for Armada 3700 ARM64: dts: marvell: armada37xx: add pinctrl definition Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt | 7 +- Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt | 183 ++- arch/arm64/Kconfig.platforms | 5 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts| 8 +- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 73 - drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/mvebu/Kconfig | 7 +- drivers/pinctrl/mvebu/Makefile| 3 +- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 969 - 9 files changed, 1249 insertions(+), 8 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c base-commit: c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201 -- git-series 0.9.1
[PATCH v4 1/7] pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
Document the device tree binding for the pin controllers found on the
Armada 37xx SoCs.
Update the binding documention of the xtal clk which is a subnode of this
syscon node.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt |
7 +--
Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt |
183 -
2 files changed, 187 insertions(+), 3 deletions(-)
create mode 100644
Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
diff --git a/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
b/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
index a88f1f05fbd6..4c0807f28cfa 100644
--- a/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
+++ b/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
@@ -5,6 +5,7 @@ reading the gpio latch register.
This node must be a subnode of the node exposing the register address
of the GPIO block where the gpio latch is located.
+See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
Required properties:
- compatible : shall be one of the following:
@@ -16,9 +17,9 @@ Optional properties:
output names ("xtal")
Example:
-gpio1: gpio@13800 {
- compatible = "marvell,armada-3700-gpio", "syscon", "simple-mfd";
- reg = <0x13800 0x1000>;
+pinctrl_nb: pinctrl-nb@13800 {
+ compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd";
+ reg = <0x13800 0x100>, <0x13C00 0x20>;
xtalclk: xtal-clk {
compatible = "marvell,armada-3700-xtal-clock";
diff --git
a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
new file mode 100644
index ..2eda81e0bca1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
@@ -0,0 +1,183 @@
+* Marvell Armada 37xx SoC pin and gpio controller
+
+Each Armada 37xx SoC come with two pin and gpio controller one for the
+south bridge and the other for the north bridge.
+
+Inside this set of register the gpio latch allows exposing some
+configuration of the SoC and especially the clock frequency of the
+xtal. Hence, this node is a represent as syscon allowing sharing the
+register between multiple hardware block.
+
+GPIO and pin controller:
+
+
+Main node:
+
+Refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning
+of the phrase "pin configuration node".
+
+Required properties for pinctrl driver:
+
+- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
+ for the south bridge
+ "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
+ for the north bridge
+- reg: The first set of register are for pinctrl/gpio and the second
+ set for the interrupt controller
+- interrupts: list of the interrupt use by the gpio
+
+Available groups and functions for the North bridge:
+
+group: jtag
+ - pins 20-24
+ - functions jtag, gpio
+
+group sdio0
+ - pins 8-10
+ - functions sdio, gpio
+
+group emmc_nb
+ - pins 27-35
+ - functions emmc, gpio
+
+group pwm0
+ - pin 11 (GPIO1-11)
+ - functions pwm, gpio
+
+group pwm1
+ - pin 12
+ - functions pwm, gpio
+
+group pwm2
+ - pin 13
+ - functions pwm, gpio
+
+group pwm3
+ - pin 14
+ - functions pwm, gpio
+
+group pmic1
+ - pin 17
+ - functions pmic, gpio
+
+group pmic0
+ - pin 16
+ - functions pmic, gpio
+
+group i2c2
+ - pins 2-3
+ - functions i2c, gpio
+
+group i2c1
+ - pins 0-1
+ - functions i2c, gpio
+
+group spi_cs1
+ - pin 17
+ - functions spi, gpio
+
+group spi_cs2
+ - pin 18
+ - functions spi, gpio
+
+group spi_cs3
+ - pin 19
+ - functions spi, gpio
+
+group onewire
+ - pin 4
+ - functions onewire, gpio
+
+group uart1
+ - pins 25-26
+ - functions uart, gpio
+
+group spi_quad
+ - pins 15-16
+ - functions spi, gpio
+
+group uart_2
+ - pins 9-10
+ - functions uart, gpio
+
+Available groups and functions for the South bridge:
+
+group usb32_drvvbus0
+ - pin 36
+ - functions drvbus, gpio
+
+group usb2_drvvbus1
+ - pin 37
+ - functions drvbus, gpio
+
+group sdio_sb
+ - pins 60-64
+ - functions sdio, gpio
+
+group rgmii
+ - pins 42-55
+ - functions mii, gpio
+
+group pcie1
+ - pins 39-40
+ - functions pcie, gpio
+
+group ptp
+ - pins 56-58
+ - functions ptp, gpio
+
+group ptp_clk
+ - pin 57
+ - functions ptp, mii
+
+group ptp_trig
+ - pin 58
+ - functions ptp, mii
+
+group mii_col
+ - pin 59
+ - functions mii, mii_err
+
+GPIO subnode:
+
+Please refer to gpio.txt in this directory for details of gpio-ranges prop
[PATCH v4 1/7] pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
Document the device tree binding for the pin controllers found on the
Armada 37xx SoCs.
Update the binding documention of the xtal clk which is a subnode of this
syscon node.
Signed-off-by: Gregory CLEMENT
---
Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt |
7 +--
Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt |
183 -
2 files changed, 187 insertions(+), 3 deletions(-)
create mode 100644
Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
diff --git a/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
b/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
index a88f1f05fbd6..4c0807f28cfa 100644
--- a/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
+++ b/Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
@@ -5,6 +5,7 @@ reading the gpio latch register.
This node must be a subnode of the node exposing the register address
of the GPIO block where the gpio latch is located.
+See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
Required properties:
- compatible : shall be one of the following:
@@ -16,9 +17,9 @@ Optional properties:
output names ("xtal")
Example:
-gpio1: gpio@13800 {
- compatible = "marvell,armada-3700-gpio", "syscon", "simple-mfd";
- reg = <0x13800 0x1000>;
+pinctrl_nb: pinctrl-nb@13800 {
+ compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd";
+ reg = <0x13800 0x100>, <0x13C00 0x20>;
xtalclk: xtal-clk {
compatible = "marvell,armada-3700-xtal-clock";
diff --git
a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
new file mode 100644
index ..2eda81e0bca1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
@@ -0,0 +1,183 @@
+* Marvell Armada 37xx SoC pin and gpio controller
+
+Each Armada 37xx SoC come with two pin and gpio controller one for the
+south bridge and the other for the north bridge.
+
+Inside this set of register the gpio latch allows exposing some
+configuration of the SoC and especially the clock frequency of the
+xtal. Hence, this node is a represent as syscon allowing sharing the
+register between multiple hardware block.
+
+GPIO and pin controller:
+
+
+Main node:
+
+Refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning
+of the phrase "pin configuration node".
+
+Required properties for pinctrl driver:
+
+- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
+ for the south bridge
+ "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
+ for the north bridge
+- reg: The first set of register are for pinctrl/gpio and the second
+ set for the interrupt controller
+- interrupts: list of the interrupt use by the gpio
+
+Available groups and functions for the North bridge:
+
+group: jtag
+ - pins 20-24
+ - functions jtag, gpio
+
+group sdio0
+ - pins 8-10
+ - functions sdio, gpio
+
+group emmc_nb
+ - pins 27-35
+ - functions emmc, gpio
+
+group pwm0
+ - pin 11 (GPIO1-11)
+ - functions pwm, gpio
+
+group pwm1
+ - pin 12
+ - functions pwm, gpio
+
+group pwm2
+ - pin 13
+ - functions pwm, gpio
+
+group pwm3
+ - pin 14
+ - functions pwm, gpio
+
+group pmic1
+ - pin 17
+ - functions pmic, gpio
+
+group pmic0
+ - pin 16
+ - functions pmic, gpio
+
+group i2c2
+ - pins 2-3
+ - functions i2c, gpio
+
+group i2c1
+ - pins 0-1
+ - functions i2c, gpio
+
+group spi_cs1
+ - pin 17
+ - functions spi, gpio
+
+group spi_cs2
+ - pin 18
+ - functions spi, gpio
+
+group spi_cs3
+ - pin 19
+ - functions spi, gpio
+
+group onewire
+ - pin 4
+ - functions onewire, gpio
+
+group uart1
+ - pins 25-26
+ - functions uart, gpio
+
+group spi_quad
+ - pins 15-16
+ - functions spi, gpio
+
+group uart_2
+ - pins 9-10
+ - functions uart, gpio
+
+Available groups and functions for the South bridge:
+
+group usb32_drvvbus0
+ - pin 36
+ - functions drvbus, gpio
+
+group usb2_drvvbus1
+ - pin 37
+ - functions drvbus, gpio
+
+group sdio_sb
+ - pins 60-64
+ - functions sdio, gpio
+
+group rgmii
+ - pins 42-55
+ - functions mii, gpio
+
+group pcie1
+ - pins 39-40
+ - functions pcie, gpio
+
+group ptp
+ - pins 56-58
+ - functions ptp, gpio
+
+group ptp_clk
+ - pin 57
+ - functions ptp, mii
+
+group ptp_trig
+ - pin 58
+ - functions ptp, mii
+
+group mii_col
+ - pin 59
+ - functions mii, mii_err
+
+GPIO subnode:
+
+Please refer to gpio.txt in this directory for details of gpio-ranges property
+and the common GPIO bindings used by cl
[PATCH v4 2/7] arm64: marvell: enable the Armada 37xx pinctrl driver
This commit makes sure the driver for the Armada 37xx pin controller is enabled. Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- arch/arm64/Kconfig.platforms | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 129cc5ae4091..9aa71a3f3f50 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -103,8 +103,13 @@ config ARCH_MVEBU select ARMADA_AP806_SYSCON select ARMADA_CP110_SYSCON select ARMADA_37XX_CLK + select GPIOLIB + select GPIOLIB_IRQCHIP select MVEBU_ODMI select MVEBU_PIC + select OF_GPIO + select PINCTRL + select PINCTRL_ARMADA_37XX help This enables support for Marvell EBU familly, including: - Armada 3700 SoC Family -- git-series 0.9.1
[PATCH v4 2/7] arm64: marvell: enable the Armada 37xx pinctrl driver
This commit makes sure the driver for the Armada 37xx pin controller is enabled. Signed-off-by: Gregory CLEMENT --- arch/arm64/Kconfig.platforms | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 129cc5ae4091..9aa71a3f3f50 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -103,8 +103,13 @@ config ARCH_MVEBU select ARMADA_AP806_SYSCON select ARMADA_CP110_SYSCON select ARMADA_37XX_CLK + select GPIOLIB + select GPIOLIB_IRQCHIP select MVEBU_ODMI select MVEBU_PIC + select OF_GPIO + select PINCTRL + select PINCTRL_ARMADA_37XX help This enables support for Marvell EBU familly, including: - Armada 3700 SoC Family -- git-series 0.9.1
[PATCH v4 7/7] ARM64: dts: marvell: armada37xx: add pinctrl definition
Start to populate the device tree of the Armada 37xx with the pincontrol
configuration used on the board providing a dts.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 8 +-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 31 +++-
2 files changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 86602c907a61..e749c5727490 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -63,6 +63,8 @@
};
{
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
status = "okay";
};
@@ -73,6 +75,8 @@
{
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_quad_pins>;
m25p80@0 {
compatible = "jedec,spi-nor";
@@ -103,6 +107,8 @@
/* Exported on the micro USB connector CON32 through an FTDI */
{
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
status = "okay";
};
@@ -128,6 +134,8 @@
};
{
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
phy-mode = "rgmii-id";
phy = <>;
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index c02b13479458..2ac25f54d01d 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -186,6 +186,31 @@
clock-output-names = "xtal";
#clock-cells = <0>;
};
+
+ spi_quad_pins: spi-quad-pins {
+ groups = "spi_quad";
+ function = "spi";
+ };
+
+ i2c1_pins: i2c1-pins {
+ groups = "i2c1";
+ function = "i2c";
+ };
+
+ i2c2_pins: i2c2-pins {
+ groups = "i2c2";
+ function = "i2c";
+ };
+
+ uart1_pins: uart1-pins {
+ groups = "uart1";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ groups = "uart2";
+ function = "uart";
+ };
};
pinctrl_sb: pinctrl-sb@18800 {
@@ -203,6 +228,12 @@
,
;
};
+
+ rgmii_pins: mii-pins {
+ groups = "rgmii";
+ function = "mii";
+ };
+
};
eth0: ethernet@3 {
--
git-series 0.9.1
[PATCH v4 7/7] ARM64: dts: marvell: armada37xx: add pinctrl definition
Start to populate the device tree of the Armada 37xx with the pincontrol
configuration used on the board providing a dts.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 8 +-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 31 +++-
2 files changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 86602c907a61..e749c5727490 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -63,6 +63,8 @@
};
{
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
status = "okay";
};
@@ -73,6 +75,8 @@
{
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_quad_pins>;
m25p80@0 {
compatible = "jedec,spi-nor";
@@ -103,6 +107,8 @@
/* Exported on the micro USB connector CON32 through an FTDI */
{
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
status = "okay";
};
@@ -128,6 +134,8 @@
};
{
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
phy-mode = "rgmii-id";
phy = <>;
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index c02b13479458..2ac25f54d01d 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -186,6 +186,31 @@
clock-output-names = "xtal";
#clock-cells = <0>;
};
+
+ spi_quad_pins: spi-quad-pins {
+ groups = "spi_quad";
+ function = "spi";
+ };
+
+ i2c1_pins: i2c1-pins {
+ groups = "i2c1";
+ function = "i2c";
+ };
+
+ i2c2_pins: i2c2-pins {
+ groups = "i2c2";
+ function = "i2c";
+ };
+
+ uart1_pins: uart1-pins {
+ groups = "uart1";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ groups = "uart2";
+ function = "uart";
+ };
};
pinctrl_sb: pinctrl-sb@18800 {
@@ -203,6 +228,12 @@
,
;
};
+
+ rgmii_pins: mii-pins {
+ groups = "rgmii";
+ function = "mii";
+ };
+
};
eth0: ethernet@3 {
--
git-series 0.9.1
[PATCH v4 6/7] ARM64: dts: marvell: Add pinctrl nodes for Armada 3700
Add the nodes for the two pin controller present in the Armada 37xx SoCs.
Initially the node was named gpio1 using the same name that for the
register range in the datasheet. However renaming it pinctr_nb (nb for
North Bridge) makes more sens.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 42 +++--
1 file changed, 39 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index b48d668a6ab6..c02b13479458 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -157,10 +157,29 @@
#clock-cells = <1>;
};
- gpio1: gpio@13800 {
- compatible = "marvell,mvebu-gpio-3700",
+ pinctrl_nb: pinctrl-nb@13800 {
+ compatible = "marvell,armada3710-nb-pinctrl",
"syscon", "simple-mfd";
- reg = <0x13800 0x500>;
+ reg = <0x13800 0x100>, <0x13C00 0x20>;
+ gpionb: gpionb {
+ #gpio-cells = <2>;
+ gpio-ranges = <_nb 0 0 36>;
+ gpio-controller;
+ interrupts =
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+
+ };
xtalclk: xtal-clk {
compatible =
"marvell,armada-3700-xtal-clock";
@@ -169,6 +188,23 @@
};
};
+ pinctrl_sb: pinctrl-sb@18800 {
+ compatible = "marvell,armada3710-sb-pinctrl",
+ "syscon", "simple-mfd";
+ reg = <0x18800 0x100>, <0x18C00 0x20>;
+ gpiosb: gpiosb {
+ #gpio-cells = <2>;
+ gpio-ranges = <_sb 0 0 29>;
+ gpio-controller;
+ interrupts =
+ ,
+ ,
+ ,
+ ,
+ ;
+ };
+ };
+
eth0: ethernet@3 {
compatible = "marvell,armada-3700-neta";
reg = <0x3 0x4000>;
--
git-series 0.9.1
[PATCH v4 6/7] ARM64: dts: marvell: Add pinctrl nodes for Armada 3700
Add the nodes for the two pin controller present in the Armada 37xx SoCs.
Initially the node was named gpio1 using the same name that for the
register range in the datasheet. However renaming it pinctr_nb (nb for
North Bridge) makes more sens.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 42 +++--
1 file changed, 39 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index b48d668a6ab6..c02b13479458 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -157,10 +157,29 @@
#clock-cells = <1>;
};
- gpio1: gpio@13800 {
- compatible = "marvell,mvebu-gpio-3700",
+ pinctrl_nb: pinctrl-nb@13800 {
+ compatible = "marvell,armada3710-nb-pinctrl",
"syscon", "simple-mfd";
- reg = <0x13800 0x500>;
+ reg = <0x13800 0x100>, <0x13C00 0x20>;
+ gpionb: gpionb {
+ #gpio-cells = <2>;
+ gpio-ranges = <_nb 0 0 36>;
+ gpio-controller;
+ interrupts =
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+
+ };
xtalclk: xtal-clk {
compatible =
"marvell,armada-3700-xtal-clock";
@@ -169,6 +188,23 @@
};
};
+ pinctrl_sb: pinctrl-sb@18800 {
+ compatible = "marvell,armada3710-sb-pinctrl",
+ "syscon", "simple-mfd";
+ reg = <0x18800 0x100>, <0x18C00 0x20>;
+ gpiosb: gpiosb {
+ #gpio-cells = <2>;
+ gpio-ranges = <_sb 0 0 29>;
+ gpio-controller;
+ interrupts =
+ ,
+ ,
+ ,
+ ,
+ ;
+ };
+ };
+
eth0: ethernet@3 {
compatible = "marvell,armada-3700-neta";
reg = <0x3 0x4000>;
--
git-series 0.9.1
[PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support
The Armada 37xx SoCs can handle interrupt through GPIO. However it can
only manage the edge ones.
The way the interrupt are managed are classical so we can use the generic
interrupt chip model.
The only unusual "feature" is that many interrupts are connected to the
parent interrupt controller. But we do not take advantage of this and use
the chained irq with all of them.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 221 +-
1 file changed, 221 insertions(+)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 5c96f5558310..7356516e0921 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -13,7 +13,9 @@
#include
#include
#include
+#include
#include
+#include
#include
#include
#include
@@ -30,6 +32,11 @@
#define OUTPUT_CTL 0x20
#define SELECTION 0x30
+#define IRQ_EN 0x0
+#define IRQ_POL0x08
+#define IRQ_STATUS 0x10
+#define IRQ_WKUP 0x18
+
#define NB_FUNCS 2
#define GPIO_PER_REG 32
@@ -75,9 +82,12 @@ struct armada_37xx_pmx_func {
struct armada_37xx_pinctrl {
struct regmap *regmap;
+ void __iomem*base;
const struct armada_37xx_pin_data *data;
struct device *dev;
struct gpio_chipgpio_chip;
+ struct irq_chip irq_chip;
+ spinlock_t irq_lock;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
struct armada_37xx_pin_group*groups;
@@ -346,6 +356,14 @@ static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
return armada_37xx_pmx_set_by_name(pctldev, name, grp);
}
+static inline void armada_37xx_irq_update_reg(unsigned int *reg,
+ struct irq_data *d)
+{
+ int offset = irqd_to_hwirq(d);
+
+ armada_37xx_update_reg(reg, offset);
+}
+
static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
@@ -468,6 +486,206 @@ static const struct gpio_chip armada_37xx_gpiolib_chip = {
.owner = THIS_MODULE,
};
+void armada_37xx_irq_ack(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 reg = IRQ_STATUS, mask = d->mask;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ writel(mask, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+}
+
+void armada_37xx_irq_mask(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_EN, mask = d->mask;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ val = readl(info->base + reg);
+ writel(val & ~mask, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+}
+
+void armada_37xx_irq_unmask(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_EN, mask = d->mask;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ val = readl(info->base + reg);
+ writel(val | mask, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+}
+
+static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_WKUP, mask = d->mask;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ val = readl(info->base + reg);
+ if (on)
+ val |= mask;
+ else
+ val &= ~mask;
+ writel(val, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+
+ return 0;
+}
+
+static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_POL, mask = d->mask;
+ unsigned long flags;
+
+ spin_lock_irqsave(>irq_lock, flags);
+ armada_37xx_irq_update_reg(, d);
+ val = readl(info->base + reg);
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ val &=
[PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support
The Armada 37xx SoCs can handle interrupt through GPIO. However it can
only manage the edge ones.
The way the interrupt are managed are classical so we can use the generic
interrupt chip model.
The only unusual "feature" is that many interrupts are connected to the
parent interrupt controller. But we do not take advantage of this and use
the chained irq with all of them.
Signed-off-by: Gregory CLEMENT
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 221 +-
1 file changed, 221 insertions(+)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 5c96f5558310..7356516e0921 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -13,7 +13,9 @@
#include
#include
#include
+#include
#include
+#include
#include
#include
#include
@@ -30,6 +32,11 @@
#define OUTPUT_CTL 0x20
#define SELECTION 0x30
+#define IRQ_EN 0x0
+#define IRQ_POL0x08
+#define IRQ_STATUS 0x10
+#define IRQ_WKUP 0x18
+
#define NB_FUNCS 2
#define GPIO_PER_REG 32
@@ -75,9 +82,12 @@ struct armada_37xx_pmx_func {
struct armada_37xx_pinctrl {
struct regmap *regmap;
+ void __iomem*base;
const struct armada_37xx_pin_data *data;
struct device *dev;
struct gpio_chipgpio_chip;
+ struct irq_chip irq_chip;
+ spinlock_t irq_lock;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
struct armada_37xx_pin_group*groups;
@@ -346,6 +356,14 @@ static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
return armada_37xx_pmx_set_by_name(pctldev, name, grp);
}
+static inline void armada_37xx_irq_update_reg(unsigned int *reg,
+ struct irq_data *d)
+{
+ int offset = irqd_to_hwirq(d);
+
+ armada_37xx_update_reg(reg, offset);
+}
+
static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
@@ -468,6 +486,206 @@ static const struct gpio_chip armada_37xx_gpiolib_chip = {
.owner = THIS_MODULE,
};
+void armada_37xx_irq_ack(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 reg = IRQ_STATUS, mask = d->mask;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ writel(mask, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+}
+
+void armada_37xx_irq_mask(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_EN, mask = d->mask;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ val = readl(info->base + reg);
+ writel(val & ~mask, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+}
+
+void armada_37xx_irq_unmask(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_EN, mask = d->mask;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ val = readl(info->base + reg);
+ writel(val | mask, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+}
+
+static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_WKUP, mask = d->mask;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(, d);
+ spin_lock_irqsave(>irq_lock, flags);
+ val = readl(info->base + reg);
+ if (on)
+ val |= mask;
+ else
+ val &= ~mask;
+ writel(val, info->base + reg);
+ spin_unlock_irqrestore(>irq_lock, flags);
+
+ return 0;
+}
+
+static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_POL, mask = d->mask;
+ unsigned long flags;
+
+ spin_lock_irqsave(>irq_lock, flags);
+ armada_37xx_irq_update_reg(, d);
+ val = readl(info->base + reg);
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ val &= ~mask;
+ break;
+ case IR
[PATCH v4 3/7] pinctrl: armada-37xx: Add pin controller support for Armada 37xx
The Armada 37xx SoC come with 2 pin controllers: one on the south
bridge (managing 28 pins) and one on the north bridge (managing 36 pins).
At the hardware level the controller configure the pins by group and not
pin by pin. This constraint is reflected in the design of the driver:
only the group related functions are implemented.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/pinctrl/Makefile| 2 +-
drivers/pinctrl/mvebu/Kconfig | 7 +-
drivers/pinctrl/mvebu/Makefile | 3 +-
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 648 +-
4 files changed, 658 insertions(+), 2 deletions(-)
create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a251f439626f..95080811f36f 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -44,7 +44,7 @@ obj-y += bcm/
obj-$(CONFIG_PINCTRL_BERLIN) += berlin/
obj-y += freescale/
obj-$(CONFIG_X86) += intel/
-obj-$(CONFIG_PINCTRL_MVEBU)+= mvebu/
+obj-y += mvebu/
obj-y += nomadik/
obj-$(CONFIG_PINCTRL_PXA) += pxa/
obj-$(CONFIG_ARCH_QCOM)+= qcom/
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 170602407c0d..5bade32d3089 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -39,3 +39,10 @@ config PINCTRL_ORION
select PINCTRL_MVEBU
endif
+
+config PINCTRL_ARMADA_37XX
+ bool
+ select GENERIC_PINCONF
+ select MFD_SYSCON
+ select PINCONF
+ select PINMUX
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index 18270cd5ea43..60c245a60f39 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -1,4 +1,4 @@
-obj-y += pinctrl-mvebu.o
+obj-$(CONFIG_PINCTRL_MVEBU)+= pinctrl-mvebu.o
obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
@@ -6,4 +6,5 @@ obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o
obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
+obj-$(CONFIG_PINCTRL_ARMADA_37XX) += pinctrl-armada-37xx.o
obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
new file mode 100644
index ..8b769d77db22
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -0,0 +1,648 @@
+/*
+ * Marvell 37xx SoC pinctrl driver
+ *
+ * Copyright (C) 2017 Marvell
+ *
+ * Gregory CLEMENT <gregory.clem...@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2 or later. This program is licensed "as is"
+ * without any warranty of any kind, whether express or implied.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../pinctrl-utils.h"
+
+#define OUTPUT_EN 0x0
+#define OUTPUT_CTL 0x20
+#define SELECTION 0x30
+
+#define NB_FUNCS 2
+#define GPIO_PER_REG 32
+
+/**
+ * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
+ * The pins of a pinmux groups are composed of one or two groups of contiguous
+ * pins.
+ * @name: Name of the pin group, used to lookup the group.
+ * @start_pins:Index of the first pin of the main range of pins
belonging to
+ * the group
+ * @npins: Number of pins included in the first range
+ * @reg_mask: Bit mask matching the group in the selection register
+ * @extra_pins:Index of the first pin of the optional second range of
pins
+ * belonging to the group
+ * @npins: Number of pins included in the second optional range
+ * @funcs: A list of pinmux functions that can be selected for this group.
+ * @pins: List of the pins included in the group
+ */
+struct armada_37xx_pin_group {
+ const char *name;
+ unsigned intstart_pin;
+ unsigned intnpins;
+ u32 reg_mask;
+ u32 val[NB_FUNCS];
+ unsigned intextra_pin;
+ unsigned intextra_npins;
+ const char *funcs[NB_FUNCS];
+ unsigned int*pins;
+};
+
+struct armada_37xx_pin_data {
+ u8 nr_pins;
+ char*name;
+ struct armada_37xx_pin_group*groups;
+ int ngroups;
+};
+
+struct armada_37xx_pmx_func {
+ const char *name;
+ const char **groups;
+
[PATCH v4 3/7] pinctrl: armada-37xx: Add pin controller support for Armada 37xx
The Armada 37xx SoC come with 2 pin controllers: one on the south
bridge (managing 28 pins) and one on the north bridge (managing 36 pins).
At the hardware level the controller configure the pins by group and not
pin by pin. This constraint is reflected in the design of the driver:
only the group related functions are implemented.
Signed-off-by: Gregory CLEMENT
---
drivers/pinctrl/Makefile| 2 +-
drivers/pinctrl/mvebu/Kconfig | 7 +-
drivers/pinctrl/mvebu/Makefile | 3 +-
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 648 +-
4 files changed, 658 insertions(+), 2 deletions(-)
create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a251f439626f..95080811f36f 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -44,7 +44,7 @@ obj-y += bcm/
obj-$(CONFIG_PINCTRL_BERLIN) += berlin/
obj-y += freescale/
obj-$(CONFIG_X86) += intel/
-obj-$(CONFIG_PINCTRL_MVEBU)+= mvebu/
+obj-y += mvebu/
obj-y += nomadik/
obj-$(CONFIG_PINCTRL_PXA) += pxa/
obj-$(CONFIG_ARCH_QCOM)+= qcom/
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 170602407c0d..5bade32d3089 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -39,3 +39,10 @@ config PINCTRL_ORION
select PINCTRL_MVEBU
endif
+
+config PINCTRL_ARMADA_37XX
+ bool
+ select GENERIC_PINCONF
+ select MFD_SYSCON
+ select PINCONF
+ select PINMUX
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index 18270cd5ea43..60c245a60f39 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -1,4 +1,4 @@
-obj-y += pinctrl-mvebu.o
+obj-$(CONFIG_PINCTRL_MVEBU)+= pinctrl-mvebu.o
obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
@@ -6,4 +6,5 @@ obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o
obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
+obj-$(CONFIG_PINCTRL_ARMADA_37XX) += pinctrl-armada-37xx.o
obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
new file mode 100644
index ..8b769d77db22
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -0,0 +1,648 @@
+/*
+ * Marvell 37xx SoC pinctrl driver
+ *
+ * Copyright (C) 2017 Marvell
+ *
+ * Gregory CLEMENT
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2 or later. This program is licensed "as is"
+ * without any warranty of any kind, whether express or implied.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../pinctrl-utils.h"
+
+#define OUTPUT_EN 0x0
+#define OUTPUT_CTL 0x20
+#define SELECTION 0x30
+
+#define NB_FUNCS 2
+#define GPIO_PER_REG 32
+
+/**
+ * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
+ * The pins of a pinmux groups are composed of one or two groups of contiguous
+ * pins.
+ * @name: Name of the pin group, used to lookup the group.
+ * @start_pins:Index of the first pin of the main range of pins
belonging to
+ * the group
+ * @npins: Number of pins included in the first range
+ * @reg_mask: Bit mask matching the group in the selection register
+ * @extra_pins:Index of the first pin of the optional second range of
pins
+ * belonging to the group
+ * @npins: Number of pins included in the second optional range
+ * @funcs: A list of pinmux functions that can be selected for this group.
+ * @pins: List of the pins included in the group
+ */
+struct armada_37xx_pin_group {
+ const char *name;
+ unsigned intstart_pin;
+ unsigned intnpins;
+ u32 reg_mask;
+ u32 val[NB_FUNCS];
+ unsigned intextra_pin;
+ unsigned intextra_npins;
+ const char *funcs[NB_FUNCS];
+ unsigned int*pins;
+};
+
+struct armada_37xx_pin_data {
+ u8 nr_pins;
+ char*name;
+ struct armada_37xx_pin_group*groups;
+ int ngroups;
+};
+
+struct armada_37xx_pmx_func {
+ const char *name;
+ const char **groups;
+ unsigned intngroups;
+};
+
+struct armada_37xx_pinctrl {
+
[PATCH v4 4/7] pinctrl: armada-37xx: Add gpio support
GPIO management is pretty simple and is part of the same IP than the pin
controller for the Armada 37xx SoCs. This patch adds the GPIO support to
the pinctrl-armada-37xx.c file, it also allows sharing common functions
between the gpiolib and the pinctrl drivers.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 128 ++---
1 file changed, 114 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 8b769d77db22..5c96f5558310 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -10,6 +10,7 @@
* without any warranty of any kind, whether express or implied.
*/
+#include
#include
#include
#include
@@ -24,6 +25,8 @@
#include "../pinctrl-utils.h"
#define OUTPUT_EN 0x0
+#define INPUT_VAL 0x10
+#define OUTPUT_VAL 0x18
#define OUTPUT_CTL 0x20
#define SELECTION 0x30
@@ -74,6 +77,7 @@ struct armada_37xx_pinctrl {
struct regmap *regmap;
const struct armada_37xx_pin_data *data;
struct device *dev;
+ struct gpio_chipgpio_chip;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
struct armada_37xx_pin_group*groups;
@@ -178,6 +182,16 @@ const struct armada_37xx_pin_data armada_37xx_pin_sb = {
.ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
};
+static inline void armada_37xx_update_reg(unsigned int *reg,
+ unsigned int offset)
+{
+ /* We never have more than 2 registers */
+ if (offset >= GPIO_PER_REG) {
+ offset -= GPIO_PER_REG;
+ *reg += sizeof(u32);
+ }
+}
+
static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
const char *func)
{
@@ -332,49 +346,88 @@ static int armada_37xx_pmx_set(struct pinctrl_dev
*pctldev,
return armada_37xx_pmx_set_by_name(pctldev, name, grp);
}
-static int armada_37xx_pmx_direction_input(struct armada_37xx_pinctrl *info,
- unsigned int offset)
+static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
+ unsigned int offset)
{
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
unsigned int reg = OUTPUT_EN;
unsigned int mask;
- if (offset >= GPIO_PER_REG) {
- offset -= GPIO_PER_REG;
- reg += sizeof(u32);
- }
+ armada_37xx_update_reg(, offset);
mask = BIT(offset);
return regmap_update_bits(info->regmap, reg, mask, 0);
}
-static int armada_37xx_pmx_direction_output(struct armada_37xx_pinctrl *info,
- unsigned int offset, int value)
+static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
+ unsigned int offset)
{
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ unsigned int reg = OUTPUT_EN;
+ unsigned int val, mask;
+
+ armada_37xx_update_reg(, offset);
+ mask = BIT(offset);
+ regmap_read(info->regmap, reg, );
+
+ return !(val & mask);
+}
+
+static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
+unsigned int offset, int value)
+{
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
unsigned int reg = OUTPUT_EN;
unsigned int mask;
- if (offset >= GPIO_PER_REG) {
- offset -= GPIO_PER_REG;
- reg += sizeof(u32);
- }
+ armada_37xx_update_reg(, offset);
mask = BIT(offset);
return regmap_update_bits(info->regmap, reg, mask, mask);
}
+static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ unsigned int reg = INPUT_VAL;
+ unsigned int val, mask;
+
+ armada_37xx_update_reg(, offset);
+ mask = BIT(offset);
+
+ regmap_read(info->regmap, reg, );
+
+ return (val & mask) != 0;
+}
+
+static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
+int value)
+{
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ unsigned int reg = OUTPUT_VAL;
+ unsigned int mask, val;
+
+ armada_37xx_update_reg(, offset);
+ mask = BIT(offset);
+ val = value ? mask : 0;
+
+ regmap_update_bits(info->regmap, reg, mask, val);
+}
+
static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
[PATCH v4 4/7] pinctrl: armada-37xx: Add gpio support
GPIO management is pretty simple and is part of the same IP than the pin
controller for the Armada 37xx SoCs. This patch adds the GPIO support to
the pinctrl-armada-37xx.c file, it also allows sharing common functions
between the gpiolib and the pinctrl drivers.
Signed-off-by: Gregory CLEMENT
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 128 ++---
1 file changed, 114 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 8b769d77db22..5c96f5558310 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -10,6 +10,7 @@
* without any warranty of any kind, whether express or implied.
*/
+#include
#include
#include
#include
@@ -24,6 +25,8 @@
#include "../pinctrl-utils.h"
#define OUTPUT_EN 0x0
+#define INPUT_VAL 0x10
+#define OUTPUT_VAL 0x18
#define OUTPUT_CTL 0x20
#define SELECTION 0x30
@@ -74,6 +77,7 @@ struct armada_37xx_pinctrl {
struct regmap *regmap;
const struct armada_37xx_pin_data *data;
struct device *dev;
+ struct gpio_chipgpio_chip;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
struct armada_37xx_pin_group*groups;
@@ -178,6 +182,16 @@ const struct armada_37xx_pin_data armada_37xx_pin_sb = {
.ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
};
+static inline void armada_37xx_update_reg(unsigned int *reg,
+ unsigned int offset)
+{
+ /* We never have more than 2 registers */
+ if (offset >= GPIO_PER_REG) {
+ offset -= GPIO_PER_REG;
+ *reg += sizeof(u32);
+ }
+}
+
static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
const char *func)
{
@@ -332,49 +346,88 @@ static int armada_37xx_pmx_set(struct pinctrl_dev
*pctldev,
return armada_37xx_pmx_set_by_name(pctldev, name, grp);
}
-static int armada_37xx_pmx_direction_input(struct armada_37xx_pinctrl *info,
- unsigned int offset)
+static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
+ unsigned int offset)
{
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
unsigned int reg = OUTPUT_EN;
unsigned int mask;
- if (offset >= GPIO_PER_REG) {
- offset -= GPIO_PER_REG;
- reg += sizeof(u32);
- }
+ armada_37xx_update_reg(, offset);
mask = BIT(offset);
return regmap_update_bits(info->regmap, reg, mask, 0);
}
-static int armada_37xx_pmx_direction_output(struct armada_37xx_pinctrl *info,
- unsigned int offset, int value)
+static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
+ unsigned int offset)
{
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ unsigned int reg = OUTPUT_EN;
+ unsigned int val, mask;
+
+ armada_37xx_update_reg(, offset);
+ mask = BIT(offset);
+ regmap_read(info->regmap, reg, );
+
+ return !(val & mask);
+}
+
+static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
+unsigned int offset, int value)
+{
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
unsigned int reg = OUTPUT_EN;
unsigned int mask;
- if (offset >= GPIO_PER_REG) {
- offset -= GPIO_PER_REG;
- reg += sizeof(u32);
- }
+ armada_37xx_update_reg(, offset);
mask = BIT(offset);
return regmap_update_bits(info->regmap, reg, mask, mask);
}
+static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ unsigned int reg = INPUT_VAL;
+ unsigned int val, mask;
+
+ armada_37xx_update_reg(, offset);
+ mask = BIT(offset);
+
+ regmap_read(info->regmap, reg, );
+
+ return (val & mask) != 0;
+}
+
+static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
+int value)
+{
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ unsigned int reg = OUTPUT_VAL;
+ unsigned int mask, val;
+
+ armada_37xx_update_reg(, offset);
+ mask = BIT(offset);
+ val = value ? mask : 0;
+
+ regmap_update_bits(info->regmap, reg, mask, val);
+}
+
static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned
Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support
Hi Linus, On mer., mars 29 2017, Linus Walleij <linus.wall...@linaro.org> wrote: >>> It has irq_create_mapping(gpiochip->irqdomain, offset); that get >>> called for every IRQ, and that will eventually call irq_of_parse_and_map() >>> if the IRQs are defined in the device tree. (IIRC) >> >> When I followed the functions called I never find a call to >> irq_of_parse_and_map(), the closer things related to device tree I found >> was: >> "virq = irq_domain_alloc_descs(-1, 1, hwirq, of_node_to_nid(of_node), >> NULL);" >> http://elixir.free-electrons.com/source/kernel/irq/irqdomain.c?v=4.11-rc4#L507 > > I don't know if I'm rambling or what. I'm pretty sure it gets called, maybe > even earlier, like when the DT is parsed for the platform. We have so many > drivers not seemingly needing this, but if your driver needs it, all others > may need to be fixed too. > > Can you put a print in irq_of_parse_and_map() and see what happens? So if I don't call it explicitly in my driver, then this function is never called for the gpio. Gregory -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH v2 5/7] pinctrl: aramda-37xx: Add irqchip support
Hi Linus, On mer., mars 29 2017, Linus Walleij wrote: >>> It has irq_create_mapping(gpiochip->irqdomain, offset); that get >>> called for every IRQ, and that will eventually call irq_of_parse_and_map() >>> if the IRQs are defined in the device tree. (IIRC) >> >> When I followed the functions called I never find a call to >> irq_of_parse_and_map(), the closer things related to device tree I found >> was: >> "virq = irq_domain_alloc_descs(-1, 1, hwirq, of_node_to_nid(of_node), >> NULL);" >> http://elixir.free-electrons.com/source/kernel/irq/irqdomain.c?v=4.11-rc4#L507 > > I don't know if I'm rambling or what. I'm pretty sure it gets called, maybe > even earlier, like when the DT is parsed for the platform. We have so many > drivers not seemingly needing this, but if your driver needs it, all others > may need to be fixed too. > > Can you put a print in irq_of_parse_and_map() and see what happens? So if I don't call it explicitly in my driver, then this function is never called for the gpio. Gregory -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH v3 1/7] pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
Hi Rob,
On mer., mars 29 2017, Rob Herring <r...@kernel.org> wrote:
>> +GPIO subnode:
>> +
>> +Please refer to gpio.txt in this directory for details of gpio-ranges
>> property
>> +and the common GPIO bindings used by client devices.
>> +
>> +Required properties for gpio driver under the gpio subnode:
>
> Why does this need to be a sub node? You should probably have a
> compatible if it is.
It is needed to be able to have a phandle associated to the gpio. Then
the other node can refer to it.
But if we can do without it I would happy to do it.
>
>> +- interrupts: List of interrupt specifier for the controllers interrupt.
>> +- gpio-controller: Marks the device node as a gpio controller.
>> +- #gpio-cells: Should be 2. The first cell is the GPIO number and the
>> + second cell specifies GPIO flags, as defined in
>> + . Only the GPIO_ACTIVE_HIGH and
>> + GPIO_ACTIVE_LOW flags are supported.
>> +- gpio-ranges: Range of pins managed by the GPIO controller.
>> +
>> +Xtal Clock bindings for Marvell Armada 37xx SoCs
>> +
>> +
>> +see Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
>> +
>> +
>> +Example:
>> +pinctrl_sb: pinctrl-sb@18800 {
>
> pinctrl@
OK
>
>> +compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
>> +reg = <0x18800 0x100>, <0x18C00 0x20>;
>> +gpiosb: gpiosb {
>
> gpio@
There is no reg property so we don't use the @
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v3 1/7] pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
Hi Rob,
On mer., mars 29 2017, Rob Herring wrote:
>> +GPIO subnode:
>> +
>> +Please refer to gpio.txt in this directory for details of gpio-ranges
>> property
>> +and the common GPIO bindings used by client devices.
>> +
>> +Required properties for gpio driver under the gpio subnode:
>
> Why does this need to be a sub node? You should probably have a
> compatible if it is.
It is needed to be able to have a phandle associated to the gpio. Then
the other node can refer to it.
But if we can do without it I would happy to do it.
>
>> +- interrupts: List of interrupt specifier for the controllers interrupt.
>> +- gpio-controller: Marks the device node as a gpio controller.
>> +- #gpio-cells: Should be 2. The first cell is the GPIO number and the
>> + second cell specifies GPIO flags, as defined in
>> + . Only the GPIO_ACTIVE_HIGH and
>> + GPIO_ACTIVE_LOW flags are supported.
>> +- gpio-ranges: Range of pins managed by the GPIO controller.
>> +
>> +Xtal Clock bindings for Marvell Armada 37xx SoCs
>> +
>> +
>> +see Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
>> +
>> +
>> +Example:
>> +pinctrl_sb: pinctrl-sb@18800 {
>
> pinctrl@
OK
>
>> +compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
>> +reg = <0x18800 0x100>, <0x18C00 0x20>;
>> +gpiosb: gpiosb {
>
> gpio@
There is no reg property so we don't use the @
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v4 0/4] gpio: mvebu: Add PWM fan support
Hi Ralph, On lun., mars 27 2017, Ralph Sennhauser <ralph.sennhau...@gmail.com> wrote: [...] > Andrew Lunn (4): > gpio: mvebu: Add limited PWM support > mvebu: xp: Add PWM properties to .dtsi files > ARM: mvebu: Enable SENSORS_PWM_FAN in defconfig > mvebu: wrt1900ac: Use pwm-fan rather than gpio-fan I didn't see any big problem with this 3 patches, I will applied them once the first one will be applied on the gpio tree or at least acked. Thanks, Gregory > > .../devicetree/bindings/gpio/gpio-mvebu.txt| 32 ++ > MAINTAINERS| 2 + > arch/arm/boot/dts/armada-370.dtsi | 16 +- > arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 +- > arch/arm/boot/dts/armada-xp-mv78230.dtsi | 14 +- > arch/arm/boot/dts/armada-xp-mv78260.dtsi | 16 +- > arch/arm/boot/dts/armada-xp-mv78460.dtsi | 16 +- > arch/arm/configs/mvebu_v7_defconfig| 2 + > drivers/gpio/gpio-mvebu.c | 324 > - > 9 files changed, 394 insertions(+), 36 deletions(-) > > -- > 2.10.2 > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH v4 0/4] gpio: mvebu: Add PWM fan support
Hi Ralph, On lun., mars 27 2017, Ralph Sennhauser wrote: [...] > Andrew Lunn (4): > gpio: mvebu: Add limited PWM support > mvebu: xp: Add PWM properties to .dtsi files > ARM: mvebu: Enable SENSORS_PWM_FAN in defconfig > mvebu: wrt1900ac: Use pwm-fan rather than gpio-fan I didn't see any big problem with this 3 patches, I will applied them once the first one will be applied on the gpio tree or at least acked. Thanks, Gregory > > .../devicetree/bindings/gpio/gpio-mvebu.txt| 32 ++ > MAINTAINERS| 2 + > arch/arm/boot/dts/armada-370.dtsi | 16 +- > arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 +- > arch/arm/boot/dts/armada-xp-mv78230.dtsi | 14 +- > arch/arm/boot/dts/armada-xp-mv78260.dtsi | 16 +- > arch/arm/boot/dts/armada-xp-mv78460.dtsi | 16 +- > arch/arm/configs/mvebu_v7_defconfig| 2 + > drivers/gpio/gpio-mvebu.c | 324 > - > 9 files changed, 394 insertions(+), 36 deletions(-) > > -- > 2.10.2 > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH v4 4/4] mvebu: wrt1900ac: Use pwm-fan rather than gpio-fan
Hi Ralph,
On lun., mars 27 2017, Ralph Sennhauser <ralph.sennhau...@gmail.com> wrote:
Here again the title should start with ARM: dts: armada-xp.
As for the other patch if there is no need for a v5 I will fix it while
appliig it.
Thanks,
Gregory
> From: Andrew Lunn <and...@lunn.ch>
>
> The mvebu GPIO driver can also perform PWM on some pins. Use the pwm-fan
> driver to control the fan of the WRT1900AC, giving us finer grained control
> over its speed and hence noise.
>
> Signed-off-by: Andrew Lunn <and...@lunn.ch>
> URL: https://patchwork.ozlabs.org/patch/427291/
> [Ralph Sennhauser: drop flags paramter from pwms, no longer used]
> Signed-off-by: Ralph Sennhauser <ralph.sennhau...@gmail.com>
> ---
> arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> index 9efcf59..6d705f5 100644
> --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> @@ -308,13 +308,11 @@
> };
> };
>
> - gpio_fan {
> + pwm_fan {
> /* SUNON HA4010V4--C99 */
> - compatible = "gpio-fan";
> - gpios = < 24 0>;
>
> - gpio-fan,speed-map = <00
> - 4500 1>;
> + compatible = "pwm-fan";
> + pwms = < 24 4000>;
> };
>
> dsa {
> --
> 2.10.2
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v4 4/4] mvebu: wrt1900ac: Use pwm-fan rather than gpio-fan
Hi Ralph,
On lun., mars 27 2017, Ralph Sennhauser wrote:
Here again the title should start with ARM: dts: armada-xp.
As for the other patch if there is no need for a v5 I will fix it while
appliig it.
Thanks,
Gregory
> From: Andrew Lunn
>
> The mvebu GPIO driver can also perform PWM on some pins. Use the pwm-fan
> driver to control the fan of the WRT1900AC, giving us finer grained control
> over its speed and hence noise.
>
> Signed-off-by: Andrew Lunn
> URL: https://patchwork.ozlabs.org/patch/427291/
> [Ralph Sennhauser: drop flags paramter from pwms, no longer used]
> Signed-off-by: Ralph Sennhauser
> ---
> arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> index 9efcf59..6d705f5 100644
> --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
> @@ -308,13 +308,11 @@
> };
> };
>
> - gpio_fan {
> + pwm_fan {
> /* SUNON HA4010V4--C99 */
> - compatible = "gpio-fan";
> - gpios = < 24 0>;
>
> - gpio-fan,speed-map = <00
> - 4500 1>;
> + compatible = "pwm-fan";
> + pwms = < 24 4000>;
> };
>
> dsa {
> --
> 2.10.2
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v4 2/4] mvebu: xp: Add PWM properties to .dtsi files
Hi Ralph,
On lun., mars 27 2017, Ralph Sennhauser <ralph.sennhau...@gmail.com> wrote:
The title should start by ARM: dts: mvebu:
If there is no need to have a v5 then I wil take care of modifying the
title while applying it.
> From: Andrew Lunn <and...@lunn.ch>
>
> Add properties to the GPIO nodes to allow them to be also used as PWM
> lines.
>
> Signed-off-by: Andrew Lunn <and...@lunn.ch>
> URL: https://patchwork.ozlabs.org/patch/427294/
> [Ralph Sennhauser:
> * Use new compatible string marvell,armada-370-xp-gpio
> * Add missing reg-names / #pwm-cell properties to armada-xp-mv78260.dtsi
> 'gpio1' node]
> Signed-off-by: Ralph Sennhauser <ralph.sennhau...@gmail.com>
> ---
> arch/arm/boot/dts/armada-370.dtsi| 16 +++-
> arch/arm/boot/dts/armada-xp-mv78230.dtsi | 14 ++
> arch/arm/boot/dts/armada-xp-mv78260.dtsi | 16 +++-
> arch/arm/boot/dts/armada-xp-mv78460.dtsi | 16 +++-
> 4 files changed, 43 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-370.dtsi
> b/arch/arm/boot/dts/armada-370.dtsi
> index cc011c8..e30b076 100644
> --- a/arch/arm/boot/dts/armada-370.dtsi
> +++ b/arch/arm/boot/dts/armada-370.dtsi
> @@ -137,29 +137,35 @@
> };
>
> gpio0: gpio@18100 {
> - compatible = "marvell,orion-gpio";
> - reg = <0x18100 0x40>;
> + compatible = "marvell,armada-370-xp-gpio";
I think we should keep the "marvell,orion-gpio" too because the hardware
is still compatible with it. Morever it will allow to use a recent dtb
with an old kernel.
> + reg = <0x18100 0x40>, <0x181c0 0x08>;
> + reg-names = "gpio", "pwm";
> ngpios = <32>;
> gpio-controller;
> #gpio-cells = <2>;
> + #pwm-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> interrupts = <82>, <83>, <84>, <85>;
> + clocks = < 0>;
> };
>
> gpio1: gpio@18140 {
> - compatible = "marvell,orion-gpio";
> - reg = <0x18140 0x40>;
> + compatible = "marvell,armada-370-xp-gpio";
Same here and for all the others...
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH v4 2/4] mvebu: xp: Add PWM properties to .dtsi files
Hi Ralph,
On lun., mars 27 2017, Ralph Sennhauser wrote:
The title should start by ARM: dts: mvebu:
If there is no need to have a v5 then I wil take care of modifying the
title while applying it.
> From: Andrew Lunn
>
> Add properties to the GPIO nodes to allow them to be also used as PWM
> lines.
>
> Signed-off-by: Andrew Lunn
> URL: https://patchwork.ozlabs.org/patch/427294/
> [Ralph Sennhauser:
> * Use new compatible string marvell,armada-370-xp-gpio
> * Add missing reg-names / #pwm-cell properties to armada-xp-mv78260.dtsi
> 'gpio1' node]
> Signed-off-by: Ralph Sennhauser
> ---
> arch/arm/boot/dts/armada-370.dtsi| 16 +++-
> arch/arm/boot/dts/armada-xp-mv78230.dtsi | 14 ++
> arch/arm/boot/dts/armada-xp-mv78260.dtsi | 16 +++-
> arch/arm/boot/dts/armada-xp-mv78460.dtsi | 16 +++-
> 4 files changed, 43 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-370.dtsi
> b/arch/arm/boot/dts/armada-370.dtsi
> index cc011c8..e30b076 100644
> --- a/arch/arm/boot/dts/armada-370.dtsi
> +++ b/arch/arm/boot/dts/armada-370.dtsi
> @@ -137,29 +137,35 @@
> };
>
> gpio0: gpio@18100 {
> - compatible = "marvell,orion-gpio";
> - reg = <0x18100 0x40>;
> + compatible = "marvell,armada-370-xp-gpio";
I think we should keep the "marvell,orion-gpio" too because the hardware
is still compatible with it. Morever it will allow to use a recent dtb
with an old kernel.
> + reg = <0x18100 0x40>, <0x181c0 0x08>;
> + reg-names = "gpio", "pwm";
> ngpios = <32>;
> gpio-controller;
> #gpio-cells = <2>;
> + #pwm-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> interrupts = <82>, <83>, <84>, <85>;
> + clocks = < 0>;
> };
>
> gpio1: gpio@18140 {
> - compatible = "marvell,orion-gpio";
> - reg = <0x18140 0x40>;
> + compatible = "marvell,armada-370-xp-gpio";
Same here and for all the others...
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH] ARM: orion5x: only call into phylib when available
Hi Arnd,
On mar., mars 28 2017, Arnd Bergmann <a...@arndb.de> wrote:
> Board code cannot call mdiobus_register_board_info() when phylib
> or mdio_device is a loadable module:
>
> arch/arm/plat-orion/common.o: In function `orion_ge00_switch_init':
> :(.init.text+0x474): undefined reference to `mdiobus_register_board_info'
>
> I had a number of ideas for how this could be solved, but after the MDIO
> code got split out from PHYLIB it has gotten too hard, so I'm basically
> giving up, and only call the mdiobus_register_board_info() function
> if the MDIO layer is built-in to avoid the link error. This is similar
> to how we handle PHY registration on other ARM platforms.
>
> Fixes: 90eff9096c01 ("net: phy: Allow splitting MDIO bus/device support from
> PHYs")
> Fixes: 648ea0134069 ("net: phy: Allow pre-declaration of MDIO devices")
> Signed-off-by: Arnd Bergmann <a...@arndb.de>
Applied on mvebu/fixes
Thanks,
Gregory
> ---
> arch/arm/mach-orion5x/Kconfig | 1 +
> arch/arm/plat-orion/common.c | 5 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index 468b8cb7fd5f..e3429c8c2e38 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -6,6 +6,7 @@ menuconfig ARCH_ORION5X
> select GPIOLIB
> select MVEBU_MBUS
> select PCI
> + select PHYLIB if NETDEVICES
> select PLAT_ORION_LEGACY
> help
> Support for the following Marvell Orion 5x series SoCs:
> diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
> index 9255b6d67ba5..aff6994950ba 100644
> --- a/arch/arm/plat-orion/common.c
> +++ b/arch/arm/plat-orion/common.c
> @@ -468,6 +468,7 @@ void __init orion_ge11_init(struct
> mv643xx_eth_platform_data *eth_data,
> eth_data, _ge11);
> }
>
> +#ifdef CONFIG_ARCH_ORION5X
>
> /*
> * Ethernet switch
>
> /
> @@ -480,6 +481,9 @@ void __init orion_ge00_switch_init(struct dsa_chip_data
> *d)
> struct mdio_board_info *bd;
> unsigned int i;
>
> + if (!IS_BUILTIN(CONFIG_PHYLIB))
> + return;
> +
> for (i = 0; i < ARRAY_SIZE(d->port_names); i++)
> if (!strcmp(d->port_names[i], "cpu"))
> break;
> @@ -493,6 +497,7 @@ void __init orion_ge00_switch_init(struct dsa_chip_data
> *d)
>
> mdiobus_register_board_info(_ge00_switch_board_info, 1);
> }
> +#endif
>
>
> /*
> * I2C
> --
> 2.9.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH] ARM: orion5x: only call into phylib when available
Hi Arnd,
On mar., mars 28 2017, Arnd Bergmann wrote:
> Board code cannot call mdiobus_register_board_info() when phylib
> or mdio_device is a loadable module:
>
> arch/arm/plat-orion/common.o: In function `orion_ge00_switch_init':
> :(.init.text+0x474): undefined reference to `mdiobus_register_board_info'
>
> I had a number of ideas for how this could be solved, but after the MDIO
> code got split out from PHYLIB it has gotten too hard, so I'm basically
> giving up, and only call the mdiobus_register_board_info() function
> if the MDIO layer is built-in to avoid the link error. This is similar
> to how we handle PHY registration on other ARM platforms.
>
> Fixes: 90eff9096c01 ("net: phy: Allow splitting MDIO bus/device support from
> PHYs")
> Fixes: 648ea0134069 ("net: phy: Allow pre-declaration of MDIO devices")
> Signed-off-by: Arnd Bergmann
Applied on mvebu/fixes
Thanks,
Gregory
> ---
> arch/arm/mach-orion5x/Kconfig | 1 +
> arch/arm/plat-orion/common.c | 5 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
> index 468b8cb7fd5f..e3429c8c2e38 100644
> --- a/arch/arm/mach-orion5x/Kconfig
> +++ b/arch/arm/mach-orion5x/Kconfig
> @@ -6,6 +6,7 @@ menuconfig ARCH_ORION5X
> select GPIOLIB
> select MVEBU_MBUS
> select PCI
> + select PHYLIB if NETDEVICES
> select PLAT_ORION_LEGACY
> help
> Support for the following Marvell Orion 5x series SoCs:
> diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
> index 9255b6d67ba5..aff6994950ba 100644
> --- a/arch/arm/plat-orion/common.c
> +++ b/arch/arm/plat-orion/common.c
> @@ -468,6 +468,7 @@ void __init orion_ge11_init(struct
> mv643xx_eth_platform_data *eth_data,
> eth_data, _ge11);
> }
>
> +#ifdef CONFIG_ARCH_ORION5X
>
> /*
> * Ethernet switch
>
> /
> @@ -480,6 +481,9 @@ void __init orion_ge00_switch_init(struct dsa_chip_data
> *d)
> struct mdio_board_info *bd;
> unsigned int i;
>
> + if (!IS_BUILTIN(CONFIG_PHYLIB))
> + return;
> +
> for (i = 0; i < ARRAY_SIZE(d->port_names); i++)
> if (!strcmp(d->port_names[i], "cpu"))
> break;
> @@ -493,6 +497,7 @@ void __init orion_ge00_switch_init(struct dsa_chip_data
> *d)
>
> mdiobus_register_board_info(_ge00_switch_board_info, 1);
> }
> +#endif
>
>
> /*
> * I2C
> --
> 2.9.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
[PATCH v7 04/13] mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c
From: Hu Ziji <huz...@marvell.com>
Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Acked-by: Adrian Hunter <adrian.hun...@intel.com>
---
drivers/mmc/host/sdhci.c | 5 +++--
drivers/mmc/host/sdhci.h | 2 ++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index d5bca886419d..cc5bb9fb7706 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1847,8 +1847,8 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc,
int enable)
spin_unlock_irqrestore(>lock, flags);
}
-static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
-struct mmc_ios *ios)
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
u16 ctrl;
@@ -1940,6 +1940,7 @@ static int sdhci_start_signal_voltage_switch(struct
mmc_host *mmc,
return 0;
}
}
+EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
static int sdhci_card_busy(struct mmc_host *mmc)
{
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index b0cb805937c0..a741d8da6227 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -704,6 +704,8 @@ void sdhci_reset(struct sdhci_host *host, u8 mask);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios);
#ifdef CONFIG_PM
int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.9.1
[PATCH v7 01/13] clk: apn806: Add eMMC clock to system controller driver
From: Konstantin Porotchkin <kos...@marvell.com>
Add fixed clock of 400MHz to system controller driver. This clock is
used as SD/eMMC clock source.
Signed-off-by: Konstantin Porotchkin <kos...@marvell.com>
Reviewed-by: Omri Itach <om...@marvell.com>
Reviewed-by: Hanna Hawa <han...@marvell.com>
[fixed up conflicts, added error handling --rmk]
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Acked-by: Stephen Boyd <sb...@codeaurora.org>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 3 ++-
drivers/clk/mvebu/ap806-system-controller.c | 15 ++-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index a749ba2edec4..5019c8f4acd0 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -235,7 +235,8 @@
#clock-cells = <1>;
clock-output-names = "ap-cpu-cluster-0",
"ap-cpu-cluster-1",
-"ap-fixed", "ap-mss";
+"ap-fixed", "ap-mss",
+"ap-emmc";
reg = <0x6f4000 0x1000>;
};
};
diff --git a/drivers/clk/mvebu/ap806-system-controller.c
b/drivers/clk/mvebu/ap806-system-controller.c
index f17702107ac5..901d89c4ab4a 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -23,7 +23,7 @@
#define AP806_SAR_REG 0x400
#define AP806_SAR_CLKFREQ_MODE_MASK0x1f
-#define AP806_CLK_NUM 4
+#define AP806_CLK_NUM 5
static struct clk *ap806_clks[AP806_CLK_NUM];
@@ -135,6 +135,17 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
goto fail3;
}
+ /* eMMC Clock is fixed clock divided by 3 */
+ of_property_read_string_index(np, "clock-output-names",
+ 4, );
+ ap806_clks[4] = clk_register_fixed_factor(NULL, name, fixedclk_name,
+ 0, 1, 3);
+ if (IS_ERR(ap806_clks[4])) {
+ ret = PTR_ERR(ap806_clks[4]);
+ goto fail4;
+ }
+
+ of_clk_add_provider(np, of_clk_src_onecell_get, _clk_data);
ret = of_clk_add_provider(np, of_clk_src_onecell_get, _clk_data);
if (ret)
goto fail_clk_add;
@@ -142,6 +153,8 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
return 0;
fail_clk_add:
+ clk_unregister_fixed_factor(ap806_clks[4]);
+fail4:
clk_unregister_fixed_factor(ap806_clks[3]);
fail3:
clk_unregister_fixed_rate(ap806_clks[2]);
--
git-series 0.9.1
[PATCH v7 04/13] mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c
From: Hu Ziji
Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.
Signed-off-by: Hu Ziji
Signed-off-by: Gregory CLEMENT
Acked-by: Adrian Hunter
---
drivers/mmc/host/sdhci.c | 5 +++--
drivers/mmc/host/sdhci.h | 2 ++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index d5bca886419d..cc5bb9fb7706 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1847,8 +1847,8 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc,
int enable)
spin_unlock_irqrestore(>lock, flags);
}
-static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
-struct mmc_ios *ios)
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
u16 ctrl;
@@ -1940,6 +1940,7 @@ static int sdhci_start_signal_voltage_switch(struct
mmc_host *mmc,
return 0;
}
}
+EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
static int sdhci_card_busy(struct mmc_host *mmc)
{
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index b0cb805937c0..a741d8da6227 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -704,6 +704,8 @@ void sdhci_reset(struct sdhci_host *host, u8 mask);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios);
#ifdef CONFIG_PM
int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.9.1
[PATCH v7 01/13] clk: apn806: Add eMMC clock to system controller driver
From: Konstantin Porotchkin
Add fixed clock of 400MHz to system controller driver. This clock is
used as SD/eMMC clock source.
Signed-off-by: Konstantin Porotchkin
Reviewed-by: Omri Itach
Reviewed-by: Hanna Hawa
[fixed up conflicts, added error handling --rmk]
Signed-off-by: Russell King
Acked-by: Stephen Boyd
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 3 ++-
drivers/clk/mvebu/ap806-system-controller.c | 15 ++-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index a749ba2edec4..5019c8f4acd0 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -235,7 +235,8 @@
#clock-cells = <1>;
clock-output-names = "ap-cpu-cluster-0",
"ap-cpu-cluster-1",
-"ap-fixed", "ap-mss";
+"ap-fixed", "ap-mss",
+"ap-emmc";
reg = <0x6f4000 0x1000>;
};
};
diff --git a/drivers/clk/mvebu/ap806-system-controller.c
b/drivers/clk/mvebu/ap806-system-controller.c
index f17702107ac5..901d89c4ab4a 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -23,7 +23,7 @@
#define AP806_SAR_REG 0x400
#define AP806_SAR_CLKFREQ_MODE_MASK0x1f
-#define AP806_CLK_NUM 4
+#define AP806_CLK_NUM 5
static struct clk *ap806_clks[AP806_CLK_NUM];
@@ -135,6 +135,17 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
goto fail3;
}
+ /* eMMC Clock is fixed clock divided by 3 */
+ of_property_read_string_index(np, "clock-output-names",
+ 4, );
+ ap806_clks[4] = clk_register_fixed_factor(NULL, name, fixedclk_name,
+ 0, 1, 3);
+ if (IS_ERR(ap806_clks[4])) {
+ ret = PTR_ERR(ap806_clks[4]);
+ goto fail4;
+ }
+
+ of_clk_add_provider(np, of_clk_src_onecell_get, _clk_data);
ret = of_clk_add_provider(np, of_clk_src_onecell_get, _clk_data);
if (ret)
goto fail_clk_add;
@@ -142,6 +153,8 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
return 0;
fail_clk_add:
+ clk_unregister_fixed_factor(ap806_clks[4]);
+fail4:
clk_unregister_fixed_factor(ap806_clks[3]);
fail3:
clk_unregister_fixed_rate(ap806_clks[2]);
--
git-series 0.9.1
