[PATCH v10 1/7] dt-bindings: PCI: mediatek-gen3: Add YAML schema

[Jianjun Wang]

Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
Reviewed-by: Rob Herring 
---
 .../bindings/pci/mediatek-pcie-gen3.yaml  | 181 ++
 1 file changed, 181 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
new file mode 100644
index ..e7b1f9892da4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -0,0 +1,181 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gen3 PCIe controller on MediaTek SoCs
+
+maintainers:
+  - Jianjun Wang 
+
+description: |+
+  PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
+  and compatible with Gen2, Gen1 speed.
+
+  This PCIe controller supports up to 256 MSI vectors, the MSI hardware
+  block diagram is as follows:
+
++-+
+| GIC |
++-+
+   ^
+   |
+   port->irq
+   |
+   +-+-+-+-+-+-+-+-+
+   |0|1|2|3|4|5|6|7| (PCIe intc)
+   +-+-+-+-+-+-+-+-+
+^ ^   ^
+| |...|
++---+ +--++---+
+|||
+  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
+  |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
+  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
+   ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
+   | |  |  || |  |  || |  |  |  (MSI vectors)
+   | |  |  || |  |  || |  |  |
+
+(MSI SET0)   (MSI SET1)  ...   (MSI SET7)
+
+  With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
+  each set has its own address for MSI message, and supports 32 MSI vectors
+  to generate interrupt.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+const: mediatek,mt8192-pcie
+
+  reg:
+maxItems: 1
+
+  reg-names:
+items:
+  - const: pcie-mac
+
+  interrupts:
+maxItems: 1
+
+  ranges:
+minItems: 1
+maxItems: 8
+
+  resets:
+minItems: 1
+maxItems: 2
+
+  reset-names:
+minItems: 1
+maxItems: 2
+items:
+  - const: phy
+  - const: mac
+
+  clocks:
+maxItems: 6
+
+  clock-names:
+items:
+  - const: pl_250m
+  - const: tl_26m
+  - const: tl_96m
+  - const: tl_32k
+  - const: peri_26m
+  - const: top_133m
+
+  assigned-clocks:
+maxItems: 1
+
+  assigned-clock-parents:
+maxItems: 1
+
+  phys:
+maxItems: 1
+
+  '#interrupt-cells':
+const: 1
+
+  interrupt-controller:
+description: Interrupt controller node for handling legacy PCI interrupts.
+type: object
+properties:
+  '#address-cells':
+const: 0
+  '#interrupt-cells':
+const: 1
+  interrupt-controller: true
+
+required:
+  - '#address-cells'
+  - '#interrupt-cells'
+  - interrupt-controller
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - ranges
+  - clocks
+  - '#interrupt-cells'
+  - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+pcie: pcie@1123 {
+compatible = "mediatek,mt8192-pcie";
+device_type = "pci";
+#address-cells = <3>;
+#size-cells = <2>;
+reg = <0x00 0x1123 0x00 0x4000>;
+reg-names = "pcie-mac";
+interrupts = ;
+bus-range = <0x00 0xff>;
+ranges = <0x8200 0x00 0x1200 0x00
+  0x1200 0x00 0x100>;
+clocks = <&infracfg 44>,
+ <&infracfg 40>,
+ <&infracfg 43>,
+ <&infracfg 97>,
+ <&infracfg 99>,
+ <&infracfg 111>;
+clock-names = "pl_250m", "tl_26m", "tl_96m",
+  "tl_32k", "peri_26m", "top_133m";
+assigned-clocks = <&topckgen 50>;
+assigned-clock-parents = <&topckgen 91>;
+
+phys = <&pciephy>;
+phy-names = "pcie-phy";
+
+resets = <&infracfg_rst 2>,
+  

[PATCH v10 7/7] MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer

[Jianjun Wang]

Update entry for MediaTek PCIe controller, add Jianjun Wang
as MediaTek PCI co-maintainer.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85ca831d..8050c14e6a7a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13919,6 +13919,7 @@ F:  drivers/pci/controller/dwc/pcie-histb.c
 
 PCIE DRIVER FOR MEDIATEK
 M: Ryder Lee 
+M: Jianjun Wang 
 L: linux-...@vger.kernel.org
 L: linux-media...@lists.infradead.org
 S: Supported
-- 
2.25.1

[PATCH v10 6/7] PCI: mediatek-gen3: Add system PM support

[Jianjun Wang]

Add suspend_noirq and resume_noirq callback functions to implement PM
system suspend and resume hooks for the MediaTek Gen3 PCIe controller.

When the system suspends, trigger the PCIe link to enter the L2 state
and pull down the PERST# pin, gating the clocks of the MAC layer, and
then power-off the physical layer to provide power-saving.

When the system resumes, the PCIe link should be re-established and the
related control register values should be restored.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 113 
 1 file changed, 113 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
index ee1b51207d11..20165e4a75b2 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -45,6 +45,9 @@
 #define PCIE_PE_RSTB   BIT(3)
 
 #define PCIE_LTSSM_STATUS_REG  0x150
+#define PCIE_LTSSM_STATE_MASK  GENMASK(28, 24)
+#define PCIE_LTSSM_STATE(val)  ((val & PCIE_LTSSM_STATE_MASK) >> 24)
+#define PCIE_LTSSM_STATE_L2_IDLE   0x14
 
 #define PCIE_LINK_STATUS_REG   0x154
 #define PCIE_PORT_LINKUP   BIT(8)
@@ -73,6 +76,9 @@
 #define PCIE_MSI_SET_ADDR_HI_BASE  0xc80
 #define PCIE_MSI_SET_ADDR_HI_OFFSET0x04
 
+#define PCIE_ICMD_PM_REG   0x198
+#define PCIE_TURN_OFF_LINK BIT(4)
+
 #define PCIE_TRANS_TABLE_BASE_REG  0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
@@ -95,10 +101,12 @@
  * struct mtk_msi_set - MSI information for each set
  * @base: IO mapped register base
  * @msg_addr: MSI message address
+ * @saved_irq_state: IRQ enable state saved at suspend time
  */
 struct mtk_msi_set {
void __iomem *base;
phys_addr_t msg_addr;
+   u32 saved_irq_state;
 };
 
 /**
@@ -112,6 +120,7 @@ struct mtk_msi_set {
  * @clks: PCIe clocks
  * @num_clks: PCIe clocks count for this port
  * @irq: PCIe controller interrupt number
+ * @saved_irq_state: IRQ enable state saved at suspend time
  * @irq_lock: lock protecting IRQ register access
  * @intx_domain: legacy INTx IRQ domain
  * @msi_domain: MSI IRQ domain
@@ -131,6 +140,7 @@ struct mtk_pcie_port {
int num_clks;
 
int irq;
+   u32 saved_irq_state;
raw_spinlock_t irq_lock;
struct irq_domain *intx_domain;
struct irq_domain *msi_domain;
@@ -894,6 +904,108 @@ static int mtk_pcie_remove(struct platform_device *pdev)
return 0;
 }
 
+static void __maybe_unused mtk_pcie_irq_save(struct mtk_pcie_port *port)
+{
+   int i;
+
+   raw_spin_lock(&port->irq_lock);
+
+   port->saved_irq_state = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+
+   for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
+   struct mtk_msi_set *msi_set = &port->msi_sets[i];
+
+   msi_set->saved_irq_state = readl_relaxed(msi_set->base +
+  PCIE_MSI_SET_ENABLE_OFFSET);
+   }
+
+   raw_spin_unlock(&port->irq_lock);
+}
+
+static void __maybe_unused mtk_pcie_irq_restore(struct mtk_pcie_port *port)
+{
+   int i;
+
+   raw_spin_lock(&port->irq_lock);
+
+   writel_relaxed(port->saved_irq_state, port->base + PCIE_INT_ENABLE_REG);
+
+   for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
+   struct mtk_msi_set *msi_set = &port->msi_sets[i];
+
+   writel_relaxed(msi_set->saved_irq_state,
+  msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
+   }
+
+   raw_spin_unlock(&port->irq_lock);
+}
+
+static int __maybe_unused mtk_pcie_turn_off_link(struct mtk_pcie_port *port)
+{
+   u32 val;
+
+   val = readl_relaxed(port->base + PCIE_ICMD_PM_REG);
+   val |= PCIE_TURN_OFF_LINK;
+   writel_relaxed(val, port->base + PCIE_ICMD_PM_REG);
+
+   /* Check the link is L2 */
+   return readl_poll_timeout(port->base + PCIE_LTSSM_STATUS_REG, val,
+ (PCIE_LTSSM_STATE(val) ==
+  PCIE_LTSSM_STATE_L2_IDLE), 20,
+  50 * USEC_PER_MSEC);
+}
+
+static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
+{
+   struct mtk_pcie_port *port = dev_get_drvdata(dev);
+   int err;
+   u32 val;
+
+   /* Trigger link to L2 state */
+   err = mtk_pcie_turn_off_link(port);
+   if (err) {
+   dev_err(port->dev, "cannot enter L2 state\n");
+   return err;
+   }
+
+   /* Pull down the PERST# pin */
+   val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
+   val |= PCIE_PE_RSTB;
+   writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
+
+   dev_dbg(port->dev, "entered L2 states successfully");
+
+   mtk_pcie_i

[PATCH v10 5/7] PCI: mediatek-gen3: Add MSI support

[Jianjun Wang]

Add MSI support for MediaTek Gen3 PCIe controller.

This PCIe controller supports up to 256 MSI vectors, the MSI hardware
block diagram is as follows:

  +-+
  | GIC |
  +-+
 ^
 |
 port->irq
 |
 +-+-+-+-+-+-+-+-+
 |0|1|2|3|4|5|6|7| (PCIe intc)
 +-+-+-+-+-+-+-+-+
  ^ ^   ^
  | |...|
  +---+ +--++---+
  |||
+-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
|0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
+-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
 ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
 | |  |  || |  |  || |  |  |  (MSI vectors)
 | |  |  || |  |  || |  |  |

  (MSI SET0)   (MSI SET1)  ...   (MSI SET7)

With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
each set has its own address for MSI message, and supports 32 MSI vectors
to generate interrupt.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
Reviewed-by: Marc Zyngier 
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 276 
 1 file changed, 276 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
index ff91ad587461..ee1b51207d11 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -48,12 +49,29 @@
 #define PCIE_LINK_STATUS_REG   0x154
 #define PCIE_PORT_LINKUP   BIT(8)
 
+#define PCIE_MSI_SET_NUM   8
+#define PCIE_MSI_IRQS_PER_SET  32
+#define PCIE_MSI_IRQS_NUM \
+   (PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM)
+
 #define PCIE_INT_ENABLE_REG0x180
+#define PCIE_MSI_ENABLEGENMASK(PCIE_MSI_SET_NUM + 8 - 
1, 8)
+#define PCIE_MSI_SHIFT 8
 #define PCIE_INTX_SHIFT24
 #define PCIE_INTX_ENABLE \
GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
 
 #define PCIE_INT_STATUS_REG0x184
+#define PCIE_MSI_SET_ENABLE_REG0x190
+#define PCIE_MSI_SET_ENABLEGENMASK(PCIE_MSI_SET_NUM - 1, 0)
+
+#define PCIE_MSI_SET_BASE_REG  0xc00
+#define PCIE_MSI_SET_OFFSET0x10
+#define PCIE_MSI_SET_STATUS_OFFSET 0x04
+#define PCIE_MSI_SET_ENABLE_OFFSET 0x08
+
+#define PCIE_MSI_SET_ADDR_HI_BASE  0xc80
+#define PCIE_MSI_SET_ADDR_HI_OFFSET0x04
 
 #define PCIE_TRANS_TABLE_BASE_REG  0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
@@ -73,6 +91,16 @@
 #define PCIE_ATR_TLP_TYPE_MEM  PCIE_ATR_TLP_TYPE(0)
 #define PCIE_ATR_TLP_TYPE_IO   PCIE_ATR_TLP_TYPE(2)
 
+/**
+ * struct mtk_msi_set - MSI information for each set
+ * @base: IO mapped register base
+ * @msg_addr: MSI message address
+ */
+struct mtk_msi_set {
+   void __iomem *base;
+   phys_addr_t msg_addr;
+};
+
 /**
  * struct mtk_pcie_port - PCIe port information
  * @dev: pointer to PCIe device
@@ -86,6 +114,11 @@
  * @irq: PCIe controller interrupt number
  * @irq_lock: lock protecting IRQ register access
  * @intx_domain: legacy INTx IRQ domain
+ * @msi_domain: MSI IRQ domain
+ * @msi_bottom_domain: MSI IRQ bottom domain
+ * @msi_sets: MSI sets information
+ * @lock: lock protecting IRQ bit map
+ * @msi_irq_in_use: bit map for assigned MSI IRQ
  */
 struct mtk_pcie_port {
struct device *dev;
@@ -100,6 +133,11 @@ struct mtk_pcie_port {
int irq;
raw_spinlock_t irq_lock;
struct irq_domain *intx_domain;
+   struct irq_domain *msi_domain;
+   struct irq_domain *msi_bottom_domain;
+   struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
+   struct mutex lock;
+   DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
 };
 
 /**
@@ -196,6 +234,35 @@ static int mtk_pcie_set_trans_table(struct mtk_pcie_port 
*port,
return 0;
 }
 
+static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
+{
+   int i;
+   u32 val;
+
+   for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
+   struct mtk_msi_set *msi_set = &port->msi_sets[i];
+
+   msi_set->base = port->base + PCIE_MSI_SET_BASE_REG +
+   i * PCIE_MSI_SET_OFFSET;
+   msi_set->msg_addr = port->reg_base + PCIE_MSI_SET_BASE_REG +
+   i * PCIE_MSI_SET_OFFSET;
+
+   /* Configure the MSI capture address */
+   writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base);
+   writel_relaxed(upper_32_bits(msi_set->msg_addr),
+  port->base + PCIE_MSI_SET_ADDR_HI_BASE +
+  i * PCIE_MSI_SET_ADDR_HI_OFFSET);
+ 

[PATCH v10 3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
compatible with Gen2, Gen1 speed.

Add support for new Gen3 controller which can be found on MT8192.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/Kconfig  |  13 +
 drivers/pci/controller/Makefile |   1 +
 drivers/pci/controller/pcie-mediatek-gen3.c | 464 
 3 files changed, 478 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 5aa8977d7b0f..1e925ac47279 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -233,6 +233,19 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable PCIe controller support on
  MediaTek SoCs.
 
+config PCIE_MEDIATEK_GEN3
+   tristate "MediaTek Gen3 PCIe controller"
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   depends on PCI_MSI_IRQ_DOMAIN
+   help
+ Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
+ This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed,
+ and support up to 256 MSI interrupt numbers for
+ multi-function devices.
+
+ Say Y here if you want to enable Gen3 PCIe controller support on
+ MediaTek SoCs.
+
 config VMD
depends on PCI_MSI && X86_64 && SRCU
tristate "Intel Volume Management Device Driver"
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index e4559f2182f2..579973327815 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
 obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
 obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
new file mode 100644
index ..3546e53b3c85
--- /dev/null
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -0,0 +1,464 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Jianjun Wang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pci.h"
+
+#define PCIE_SETTING_REG   0x80
+#define PCIE_PCI_IDS_1 0x9c
+#define PCI_CLASS(class)   (class << 8)
+#define PCIE_RC_MODE   BIT(0)
+
+#define PCIE_CFGNUM_REG0x140
+#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
+#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
+#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
16))
+#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
+#define PCIE_CFG_OFFSET_ADDR   0x1000
+#define PCIE_CFG_HEADER(bus, devfn) \
+   (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
+
+#define PCIE_RST_CTRL_REG  0x148
+#define PCIE_MAC_RSTB  BIT(0)
+#define PCIE_PHY_RSTB  BIT(1)
+#define PCIE_BRG_RSTB  BIT(2)
+#define PCIE_PE_RSTB   BIT(3)
+
+#define PCIE_LTSSM_STATUS_REG  0x150
+
+#define PCIE_LINK_STATUS_REG   0x154
+#define PCIE_PORT_LINKUP   BIT(8)
+
+#define PCIE_TRANS_TABLE_BASE_REG  0x800
+#define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
+#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
+#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET  0xc
+#define PCIE_ATR_TRSL_PARAM_OFFSET 0x10
+#define PCIE_ATR_TLB_SET_OFFSET0x20
+
+#define PCIE_MAX_TRANS_TABLES  8
+#define PCIE_ATR_ENBIT(0)
+#define PCIE_ATR_SIZE(size) \
+   (size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
+#define PCIE_ATR_ID(id)((id) & GENMASK(3, 0))
+#define PCIE_ATR_TYPE_MEM  PCIE_ATR_ID(0)
+#define PCIE_ATR_TYPE_IO   PCIE_ATR_ID(1)
+#define PCIE_ATR_TLP_TYPE(type)(((type) << 16) & GENMASK(18, 
16))
+#define PCIE_ATR_TLP_TYPE_MEM  PCIE_ATR_TLP_TYPE(0)
+#define PCIE_ATR_TLP_TYPE_IO   PCIE_ATR_TLP_TYPE(2)
+
+/**
+ * struct mtk_pcie_port - PCIe port information
+ * @dev: pointer to PCIe device
+ * @base: IO mapped register base
+ * @reg_base: physical register base
+ * @mac_reset: MAC reset control
+ * @phy_reset: PHY reset control
+ * @phy: PHY controller block
+ * @clks: PCIe clocks
+ * @num_clks: PCIe clock

[PATCH v10 4/7] PCI: mediatek-gen3: Add INTx support

[Jianjun Wang]

Add INTx support for MediaTek Gen3 PCIe controller.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
Reviewed-by: Marc Zyngier 
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 172 
 1 file changed, 172 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
index 3546e53b3c85..ff91ad587461 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -9,6 +9,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -45,6 +48,13 @@
 #define PCIE_LINK_STATUS_REG   0x154
 #define PCIE_PORT_LINKUP   BIT(8)
 
+#define PCIE_INT_ENABLE_REG0x180
+#define PCIE_INTX_SHIFT24
+#define PCIE_INTX_ENABLE \
+   GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
+
+#define PCIE_INT_STATUS_REG0x184
+
 #define PCIE_TRANS_TABLE_BASE_REG  0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
@@ -73,6 +83,9 @@
  * @phy: PHY controller block
  * @clks: PCIe clocks
  * @num_clks: PCIe clocks count for this port
+ * @irq: PCIe controller interrupt number
+ * @irq_lock: lock protecting IRQ register access
+ * @intx_domain: legacy INTx IRQ domain
  */
 struct mtk_pcie_port {
struct device *dev;
@@ -83,6 +96,10 @@ struct mtk_pcie_port {
struct phy *phy;
struct clk_bulk_data *clks;
int num_clks;
+
+   int irq;
+   raw_spinlock_t irq_lock;
+   struct irq_domain *intx_domain;
 };
 
 /**
@@ -198,6 +215,11 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port 
*port)
val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8);
writel_relaxed(val, port->base + PCIE_PCI_IDS_1);
 
+   /* Mask all INTx interrupts */
+   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+   val &= ~PCIE_INTX_ENABLE;
+   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+
/* Assert all reset signals */
val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
@@ -261,6 +283,150 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port 
*port)
return 0;
 }
 
+static int mtk_pcie_set_affinity(struct irq_data *data,
+const struct cpumask *mask, bool force)
+{
+   return -EINVAL;
+}
+
+static void mtk_intx_mask(struct irq_data *data)
+{
+   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+   unsigned long flags;
+   u32 val;
+
+   raw_spin_lock_irqsave(&port->irq_lock, flags);
+   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+   val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
+   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+   raw_spin_unlock_irqrestore(&port->irq_lock, flags);
+}
+
+static void mtk_intx_unmask(struct irq_data *data)
+{
+   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+   unsigned long flags;
+   u32 val;
+
+   raw_spin_lock_irqsave(&port->irq_lock, flags);
+   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+   val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
+   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+   raw_spin_unlock_irqrestore(&port->irq_lock, flags);
+}
+
+/**
+ * mtk_intx_eoi() - Clear INTx IRQ status at the end of interrupt
+ * @data: pointer to chip specific data
+ *
+ * As an emulated level IRQ, its interrupt status will remain
+ * until the corresponding de-assert message is received; hence that
+ * the status can only be cleared when the interrupt has been serviced.
+ */
+static void mtk_intx_eoi(struct irq_data *data)
+{
+   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+   unsigned long hwirq;
+
+   hwirq = data->hwirq + PCIE_INTX_SHIFT;
+   writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG);
+}
+
+static struct irq_chip mtk_intx_irq_chip = {
+   .irq_mask   = mtk_intx_mask,
+   .irq_unmask = mtk_intx_unmask,
+   .irq_eoi= mtk_intx_eoi,
+   .irq_set_affinity   = mtk_pcie_set_affinity,
+   .name   = "INTx",
+};
+
+static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
+irq_hw_number_t hwirq)
+{
+   irq_set_chip_data(irq, domain->host_data);
+   irq_set_chip_and_handler_name(irq, &mtk_intx_irq_chip,
+ handle_fasteoi_irq, "INTx");
+   return 0;
+}
+
+static const struct irq_domain_ops intx_domain_ops = {
+   .map = mtk_pcie_intx_map,
+};
+
+static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port)
+{
+   struct device *dev = port->dev;
+   struct device_n

[PATCH v10 2/7] PCI: Export pci_pio_to_address() for module use

[Jianjun Wang]

This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.

Signed-off-by: Jianjun Wang 
Acked-by: Bjorn Helgaas 
---
 drivers/pci/pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 16a17215f633..09f1714e23be 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4052,6 +4052,7 @@ phys_addr_t pci_pio_to_address(unsigned long pio)
 
return address;
 }
+EXPORT_SYMBOL_GPL(pci_pio_to_address);
 
 unsigned long __weak pci_address_to_pio(phys_addr_t address)
 {
-- 
2.25.1

[PATCH v10 0/7] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

From: mtk15901 

These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.

Changes in v10:
1. Fix the subject line format in commit message;
2. Use EXPORT_SYMBOL_GPL() to export pci_pio_to_address().

Changes in v9:
1. Use mtk_pcie_parse_port() to get the hw resources;
2. Remove unnecessary logs;
3. Add local IRQ enable status save/restore instead of
   the enable/disable callbacks;
4. Fix typos.

Changes in v8:
1. Add irq_clock to protect IRQ register access;
2. Mask all INTx interrupt when startup port;
3. Remove activate/deactivate callbacks from bottom_domain_ops;
4. Add unmask/mask callbacks in mtk_msi_bottom_irq_chip;
5. Add property information for reg-names.

Changes in v7:
1. Split the driver patch to core PCIe, INTx, MSI and PM patches;
2. Reshape MSI init and handle flow,
   use msi_bottom_domain to cover all sets;
3. Replace readl/writel with their relaxed version;
4. Add MSI description in binding document;
5. Add pl_250m clock in binding document.

Changes in v6:
1. Export pci_pio_to_address() to support compiling as kernel module;
2. Replace usleep_range(100 * 1000, 120 * 1000) with msleep(100);
3. Replace dev_notice with dev_err;
4. Fix MSI get hwirq flow;
5. Fix warning for possible recursive locking in mtk_pcie_set_affinity.

Changes in v5:
1. Remove unused macros
2. Modify the config read/write callbacks, set the config byte field
   in TLP header and use pci_generic_config_read32/write32
   to access the config space
3. Fix the settings of translation window, both MEM and IO regions
   works properly
4. Fix typos

Changes in v4:
1. Fix PCIe power up/down flow
2. Use "mac" and "phy" for reset names
3. Add clock names
4. Fix the variables type

Changes in v3:
1. Remove standard property in binding document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs

Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown

Jianjun Wang (7):
  dt-bindings: PCI: mediatek-gen3: Add YAML schema
  PCI: Export pci_pio_to_address() for module use
  PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192
  PCI: mediatek-gen3: Add INTx support
  PCI: mediatek-gen3: Add MSI support
  PCI: mediatek-gen3: Add system PM support
  MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer

 .../bindings/pci/mediatek-pcie-gen3.yaml  |  181 +++
 MAINTAINERS   |1 +
 drivers/pci/controller/Kconfig|   13 +
 drivers/pci/controller/Makefile   |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c   | 1025 +
 drivers/pci/pci.c |1 +
 6 files changed, 1222 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

-- 
2.25.1

Re: [v9,0/7] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

On Mon, 2021-04-19 at 11:44 +0100, Lorenzo Pieralisi wrote:
> On Fri, Apr 16, 2021 at 02:21:00PM -0500, Bjorn Helgaas wrote:
> > On Wed, Mar 24, 2021 at 11:05:03AM +0800, Jianjun Wang wrote:
> > > These series patches add pcie-mediatek-gen3.c and dt-bindings file to
> > > support new generation PCIe controller.
> > 
> > Incidental: b4 doesn't work on this thread, I suspect because the
> > usual subject line format is:
> > 
> >   [PATCH v9 9/7]
> > 
> > instead of:
> > 
> >   [v9,0/7]
> > 
> > For b4 info, see 
> > https://git.kernel.org/pub/scm/utils/b4/b4.git/tree/README.rst
> 
> Jianjun will update the series accordingly (and please add to v10 the
> review tags you received.
> 
> Lorenzo

Yes, I will update this series in v10 to fix the subject line format and
use EXPORT_SYMBOL_GPL(), thanks for your comments.

Thanks.

Re: [v9,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

Hi Bjorn, Lorenzo,

Just gentle ping for this patch set, please kindly let me know your
comments about this patch set.

Thanks.

On Wed, 2021-03-24 at 11:05 +0800, Jianjun Wang wrote:
> MediaTek's PCIe host controller has three generation HWs, the new
> generation HW is an individual bridge, it supports Gen3 speed and
> compatible with Gen2, Gen1 speed.
> 
> Add support for new Gen3 controller which can be found on MT8192.
> 
> Signed-off-by: Jianjun Wang 
> Acked-by: Ryder Lee 
> ---
>  drivers/pci/controller/Kconfig  |  13 +
>  drivers/pci/controller/Makefile |   1 +
>  drivers/pci/controller/pcie-mediatek-gen3.c | 464 
>  3 files changed, 478 insertions(+)
>  create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c
> 
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 5aa8977d7b0f..1e925ac47279 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -233,6 +233,19 @@ config PCIE_MEDIATEK
> Say Y here if you want to enable PCIe controller support on
> MediaTek SoCs.
>  
> +config PCIE_MEDIATEK_GEN3
> + tristate "MediaTek Gen3 PCIe controller"
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + depends on PCI_MSI_IRQ_DOMAIN
> + help
> +   Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> +   This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed,
> +   and support up to 256 MSI interrupt numbers for
> +   multi-function devices.
> +
> +   Say Y here if you want to enable Gen3 PCIe controller support on
> +   MediaTek SoCs.
> +
>  config VMD
>   depends on PCI_MSI && X86_64 && SRCU
>   tristate "Intel Volume Management Device Driver"
> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> index e4559f2182f2..579973327815 100644
> --- a/drivers/pci/controller/Makefile
> +++ b/drivers/pci/controller/Makefile
> @@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
>  obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
>  obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
>  obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> +obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
>  obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o
>  obj-$(CONFIG_VMD) += vmd.o
>  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
> b/drivers/pci/controller/pcie-mediatek-gen3.c
> new file mode 100644
> index ..3546e53b3c85
> --- /dev/null
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -0,0 +1,464 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * MediaTek PCIe host controller driver.
> + *
> + * Copyright (c) 2020 MediaTek Inc.
> + * Author: Jianjun Wang 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "../pci.h"
> +
> +#define PCIE_SETTING_REG 0x80
> +#define PCIE_PCI_IDS_1   0x9c
> +#define PCI_CLASS(class) (class << 8)
> +#define PCIE_RC_MODE BIT(0)
> +
> +#define PCIE_CFGNUM_REG  0x140
> +#define PCIE_CFG_DEVFN(devfn)((devfn) & GENMASK(7, 0))
> +#define PCIE_CFG_BUS(bus)(((bus) << 8) & GENMASK(15, 8))
> +#define PCIE_CFG_BYTE_EN(bytes)  (((bytes) << 16) & GENMASK(19, 
> 16))
> +#define PCIE_CFG_FORCE_BYTE_EN   BIT(20)
> +#define PCIE_CFG_OFFSET_ADDR 0x1000
> +#define PCIE_CFG_HEADER(bus, devfn) \
> + (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
> +
> +#define PCIE_RST_CTRL_REG0x148
> +#define PCIE_MAC_RSTBBIT(0)
> +#define PCIE_PHY_RSTBBIT(1)
> +#define PCIE_BRG_RSTBBIT(2)
> +#define PCIE_PE_RSTB BIT(3)
> +
> +#define PCIE_LTSSM_STATUS_REG0x150
> +
> +#define PCIE_LINK_STATUS_REG 0x154
> +#define PCIE_PORT_LINKUP BIT(8)
> +
> +#define PCIE_TRANS_TABLE_BASE_REG0x800
> +#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
> +#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET0x8
> +#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET0xc
> +#define PCIE_ATR_TRSL_PARAM_OFFSET   0x10
> +#define PCIE_ATR_TLB_SET_OFFSET  0x20
> +
> +#define PCIE_MAX_TRANS_TABLES8
> +#define PCIE_ATR_EN  BIT(0)
> +#define PCIE_ATR_SIZE(size) \
> + (size) - 1) &

[v9,5/7] PCI: mediatek-gen3: Add MSI support

[Jianjun Wang]

Add MSI support for MediaTek Gen3 PCIe controller.

This PCIe controller supports up to 256 MSI vectors, the MSI hardware
block diagram is as follows:

  +-+
  | GIC |
  +-+
 ^
 |
 port->irq
 |
 +-+-+-+-+-+-+-+-+
 |0|1|2|3|4|5|6|7| (PCIe intc)
 +-+-+-+-+-+-+-+-+
  ^ ^   ^
  | |...|
  +---+ +--++---+
  |||
+-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
|0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
+-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
 ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
 | |  |  || |  |  || |  |  |  (MSI vectors)
 | |  |  || |  |  || |  |  |

  (MSI SET0)   (MSI SET1)  ...   (MSI SET7)

With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
each set has its own address for MSI message, and supports 32 MSI vectors
to generate interrupt.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 276 
 1 file changed, 276 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
index ff91ad587461..ee1b51207d11 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -48,12 +49,29 @@
 #define PCIE_LINK_STATUS_REG   0x154
 #define PCIE_PORT_LINKUP   BIT(8)
 
+#define PCIE_MSI_SET_NUM   8
+#define PCIE_MSI_IRQS_PER_SET  32
+#define PCIE_MSI_IRQS_NUM \
+   (PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM)
+
 #define PCIE_INT_ENABLE_REG0x180
+#define PCIE_MSI_ENABLEGENMASK(PCIE_MSI_SET_NUM + 8 - 
1, 8)
+#define PCIE_MSI_SHIFT 8
 #define PCIE_INTX_SHIFT24
 #define PCIE_INTX_ENABLE \
GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
 
 #define PCIE_INT_STATUS_REG0x184
+#define PCIE_MSI_SET_ENABLE_REG0x190
+#define PCIE_MSI_SET_ENABLEGENMASK(PCIE_MSI_SET_NUM - 1, 0)
+
+#define PCIE_MSI_SET_BASE_REG  0xc00
+#define PCIE_MSI_SET_OFFSET0x10
+#define PCIE_MSI_SET_STATUS_OFFSET 0x04
+#define PCIE_MSI_SET_ENABLE_OFFSET 0x08
+
+#define PCIE_MSI_SET_ADDR_HI_BASE  0xc80
+#define PCIE_MSI_SET_ADDR_HI_OFFSET0x04
 
 #define PCIE_TRANS_TABLE_BASE_REG  0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
@@ -73,6 +91,16 @@
 #define PCIE_ATR_TLP_TYPE_MEM  PCIE_ATR_TLP_TYPE(0)
 #define PCIE_ATR_TLP_TYPE_IO   PCIE_ATR_TLP_TYPE(2)
 
+/**
+ * struct mtk_msi_set - MSI information for each set
+ * @base: IO mapped register base
+ * @msg_addr: MSI message address
+ */
+struct mtk_msi_set {
+   void __iomem *base;
+   phys_addr_t msg_addr;
+};
+
 /**
  * struct mtk_pcie_port - PCIe port information
  * @dev: pointer to PCIe device
@@ -86,6 +114,11 @@
  * @irq: PCIe controller interrupt number
  * @irq_lock: lock protecting IRQ register access
  * @intx_domain: legacy INTx IRQ domain
+ * @msi_domain: MSI IRQ domain
+ * @msi_bottom_domain: MSI IRQ bottom domain
+ * @msi_sets: MSI sets information
+ * @lock: lock protecting IRQ bit map
+ * @msi_irq_in_use: bit map for assigned MSI IRQ
  */
 struct mtk_pcie_port {
struct device *dev;
@@ -100,6 +133,11 @@ struct mtk_pcie_port {
int irq;
raw_spinlock_t irq_lock;
struct irq_domain *intx_domain;
+   struct irq_domain *msi_domain;
+   struct irq_domain *msi_bottom_domain;
+   struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
+   struct mutex lock;
+   DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
 };
 
 /**
@@ -196,6 +234,35 @@ static int mtk_pcie_set_trans_table(struct mtk_pcie_port 
*port,
return 0;
 }
 
+static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
+{
+   int i;
+   u32 val;
+
+   for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
+   struct mtk_msi_set *msi_set = &port->msi_sets[i];
+
+   msi_set->base = port->base + PCIE_MSI_SET_BASE_REG +
+   i * PCIE_MSI_SET_OFFSET;
+   msi_set->msg_addr = port->reg_base + PCIE_MSI_SET_BASE_REG +
+   i * PCIE_MSI_SET_OFFSET;
+
+   /* Configure the MSI capture address */
+   writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base);
+   writel_relaxed(upper_32_bits(msi_set->msg_addr),
+  port->base + PCIE_MSI_SET_ADDR_HI_BASE +
+  i * PCIE_MSI_SET_ADDR_HI_OFFSET);
+   }
+
+

[v9,6/7] PCI: mediatek-gen3: Add system PM support

[Jianjun Wang]

Add suspend_noirq and resume_noirq callback functions to implement PM
system suspend and resume hooks for the MediaTek Gen3 PCIe controller.

When the system suspends, trigger the PCIe link to enter the L2 state
and pull down the PERST# pin, gating the clocks of the MAC layer, and
then power-off the physical layer to provide power-saving.

When the system resumes, the PCIe link should be re-established and the
related control register values should be restored.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 113 
 1 file changed, 113 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
index ee1b51207d11..20165e4a75b2 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -45,6 +45,9 @@
 #define PCIE_PE_RSTB   BIT(3)
 
 #define PCIE_LTSSM_STATUS_REG  0x150
+#define PCIE_LTSSM_STATE_MASK  GENMASK(28, 24)
+#define PCIE_LTSSM_STATE(val)  ((val & PCIE_LTSSM_STATE_MASK) >> 24)
+#define PCIE_LTSSM_STATE_L2_IDLE   0x14
 
 #define PCIE_LINK_STATUS_REG   0x154
 #define PCIE_PORT_LINKUP   BIT(8)
@@ -73,6 +76,9 @@
 #define PCIE_MSI_SET_ADDR_HI_BASE  0xc80
 #define PCIE_MSI_SET_ADDR_HI_OFFSET0x04
 
+#define PCIE_ICMD_PM_REG   0x198
+#define PCIE_TURN_OFF_LINK BIT(4)
+
 #define PCIE_TRANS_TABLE_BASE_REG  0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
@@ -95,10 +101,12 @@
  * struct mtk_msi_set - MSI information for each set
  * @base: IO mapped register base
  * @msg_addr: MSI message address
+ * @saved_irq_state: IRQ enable state saved at suspend time
  */
 struct mtk_msi_set {
void __iomem *base;
phys_addr_t msg_addr;
+   u32 saved_irq_state;
 };
 
 /**
@@ -112,6 +120,7 @@ struct mtk_msi_set {
  * @clks: PCIe clocks
  * @num_clks: PCIe clocks count for this port
  * @irq: PCIe controller interrupt number
+ * @saved_irq_state: IRQ enable state saved at suspend time
  * @irq_lock: lock protecting IRQ register access
  * @intx_domain: legacy INTx IRQ domain
  * @msi_domain: MSI IRQ domain
@@ -131,6 +140,7 @@ struct mtk_pcie_port {
int num_clks;
 
int irq;
+   u32 saved_irq_state;
raw_spinlock_t irq_lock;
struct irq_domain *intx_domain;
struct irq_domain *msi_domain;
@@ -894,6 +904,108 @@ static int mtk_pcie_remove(struct platform_device *pdev)
return 0;
 }
 
+static void __maybe_unused mtk_pcie_irq_save(struct mtk_pcie_port *port)
+{
+   int i;
+
+   raw_spin_lock(&port->irq_lock);
+
+   port->saved_irq_state = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+
+   for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
+   struct mtk_msi_set *msi_set = &port->msi_sets[i];
+
+   msi_set->saved_irq_state = readl_relaxed(msi_set->base +
+  PCIE_MSI_SET_ENABLE_OFFSET);
+   }
+
+   raw_spin_unlock(&port->irq_lock);
+}
+
+static void __maybe_unused mtk_pcie_irq_restore(struct mtk_pcie_port *port)
+{
+   int i;
+
+   raw_spin_lock(&port->irq_lock);
+
+   writel_relaxed(port->saved_irq_state, port->base + PCIE_INT_ENABLE_REG);
+
+   for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
+   struct mtk_msi_set *msi_set = &port->msi_sets[i];
+
+   writel_relaxed(msi_set->saved_irq_state,
+  msi_set->base + PCIE_MSI_SET_ENABLE_OFFSET);
+   }
+
+   raw_spin_unlock(&port->irq_lock);
+}
+
+static int __maybe_unused mtk_pcie_turn_off_link(struct mtk_pcie_port *port)
+{
+   u32 val;
+
+   val = readl_relaxed(port->base + PCIE_ICMD_PM_REG);
+   val |= PCIE_TURN_OFF_LINK;
+   writel_relaxed(val, port->base + PCIE_ICMD_PM_REG);
+
+   /* Check the link is L2 */
+   return readl_poll_timeout(port->base + PCIE_LTSSM_STATUS_REG, val,
+ (PCIE_LTSSM_STATE(val) ==
+  PCIE_LTSSM_STATE_L2_IDLE), 20,
+  50 * USEC_PER_MSEC);
+}
+
+static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
+{
+   struct mtk_pcie_port *port = dev_get_drvdata(dev);
+   int err;
+   u32 val;
+
+   /* Trigger link to L2 state */
+   err = mtk_pcie_turn_off_link(port);
+   if (err) {
+   dev_err(port->dev, "cannot enter L2 state\n");
+   return err;
+   }
+
+   /* Pull down the PERST# pin */
+   val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
+   val |= PCIE_PE_RSTB;
+   writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
+
+   dev_dbg(port->dev, "entered L2 states successfully");
+
+   mtk_pcie_i

[v9,4/7] PCI: mediatek-gen3: Add INTx support

[Jianjun Wang]

Add INTx support for MediaTek Gen3 PCIe controller.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 172 
 1 file changed, 172 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
index 3546e53b3c85..ff91ad587461 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -9,6 +9,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -45,6 +48,13 @@
 #define PCIE_LINK_STATUS_REG   0x154
 #define PCIE_PORT_LINKUP   BIT(8)
 
+#define PCIE_INT_ENABLE_REG0x180
+#define PCIE_INTX_SHIFT24
+#define PCIE_INTX_ENABLE \
+   GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
+
+#define PCIE_INT_STATUS_REG0x184
+
 #define PCIE_TRANS_TABLE_BASE_REG  0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
@@ -73,6 +83,9 @@
  * @phy: PHY controller block
  * @clks: PCIe clocks
  * @num_clks: PCIe clocks count for this port
+ * @irq: PCIe controller interrupt number
+ * @irq_lock: lock protecting IRQ register access
+ * @intx_domain: legacy INTx IRQ domain
  */
 struct mtk_pcie_port {
struct device *dev;
@@ -83,6 +96,10 @@ struct mtk_pcie_port {
struct phy *phy;
struct clk_bulk_data *clks;
int num_clks;
+
+   int irq;
+   raw_spinlock_t irq_lock;
+   struct irq_domain *intx_domain;
 };
 
 /**
@@ -198,6 +215,11 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port 
*port)
val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8);
writel_relaxed(val, port->base + PCIE_PCI_IDS_1);
 
+   /* Mask all INTx interrupts */
+   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+   val &= ~PCIE_INTX_ENABLE;
+   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+
/* Assert all reset signals */
val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
@@ -261,6 +283,150 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port 
*port)
return 0;
 }
 
+static int mtk_pcie_set_affinity(struct irq_data *data,
+const struct cpumask *mask, bool force)
+{
+   return -EINVAL;
+}
+
+static void mtk_intx_mask(struct irq_data *data)
+{
+   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+   unsigned long flags;
+   u32 val;
+
+   raw_spin_lock_irqsave(&port->irq_lock, flags);
+   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+   val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
+   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+   raw_spin_unlock_irqrestore(&port->irq_lock, flags);
+}
+
+static void mtk_intx_unmask(struct irq_data *data)
+{
+   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+   unsigned long flags;
+   u32 val;
+
+   raw_spin_lock_irqsave(&port->irq_lock, flags);
+   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+   val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
+   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+   raw_spin_unlock_irqrestore(&port->irq_lock, flags);
+}
+
+/**
+ * mtk_intx_eoi() - Clear INTx IRQ status at the end of interrupt
+ * @data: pointer to chip specific data
+ *
+ * As an emulated level IRQ, its interrupt status will remain
+ * until the corresponding de-assert message is received; hence that
+ * the status can only be cleared when the interrupt has been serviced.
+ */
+static void mtk_intx_eoi(struct irq_data *data)
+{
+   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+   unsigned long hwirq;
+
+   hwirq = data->hwirq + PCIE_INTX_SHIFT;
+   writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG);
+}
+
+static struct irq_chip mtk_intx_irq_chip = {
+   .irq_mask   = mtk_intx_mask,
+   .irq_unmask = mtk_intx_unmask,
+   .irq_eoi= mtk_intx_eoi,
+   .irq_set_affinity   = mtk_pcie_set_affinity,
+   .name   = "INTx",
+};
+
+static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
+irq_hw_number_t hwirq)
+{
+   irq_set_chip_data(irq, domain->host_data);
+   irq_set_chip_and_handler_name(irq, &mtk_intx_irq_chip,
+ handle_fasteoi_irq, "INTx");
+   return 0;
+}
+
+static const struct irq_domain_ops intx_domain_ops = {
+   .map = mtk_pcie_intx_map,
+};
+
+static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port)
+{
+   struct device *dev = port->dev;
+   struct device_node *intc_node, *node

[v9,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
compatible with Gen2, Gen1 speed.

Add support for new Gen3 controller which can be found on MT8192.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/Kconfig  |  13 +
 drivers/pci/controller/Makefile |   1 +
 drivers/pci/controller/pcie-mediatek-gen3.c | 464 
 3 files changed, 478 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 5aa8977d7b0f..1e925ac47279 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -233,6 +233,19 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable PCIe controller support on
  MediaTek SoCs.
 
+config PCIE_MEDIATEK_GEN3
+   tristate "MediaTek Gen3 PCIe controller"
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   depends on PCI_MSI_IRQ_DOMAIN
+   help
+ Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
+ This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed,
+ and support up to 256 MSI interrupt numbers for
+ multi-function devices.
+
+ Say Y here if you want to enable Gen3 PCIe controller support on
+ MediaTek SoCs.
+
 config VMD
depends on PCI_MSI && X86_64 && SRCU
tristate "Intel Volume Management Device Driver"
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index e4559f2182f2..579973327815 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
 obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
 obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
new file mode 100644
index ..3546e53b3c85
--- /dev/null
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -0,0 +1,464 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Jianjun Wang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pci.h"
+
+#define PCIE_SETTING_REG   0x80
+#define PCIE_PCI_IDS_1 0x9c
+#define PCI_CLASS(class)   (class << 8)
+#define PCIE_RC_MODE   BIT(0)
+
+#define PCIE_CFGNUM_REG0x140
+#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
+#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
+#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
16))
+#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
+#define PCIE_CFG_OFFSET_ADDR   0x1000
+#define PCIE_CFG_HEADER(bus, devfn) \
+   (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
+
+#define PCIE_RST_CTRL_REG  0x148
+#define PCIE_MAC_RSTB  BIT(0)
+#define PCIE_PHY_RSTB  BIT(1)
+#define PCIE_BRG_RSTB  BIT(2)
+#define PCIE_PE_RSTB   BIT(3)
+
+#define PCIE_LTSSM_STATUS_REG  0x150
+
+#define PCIE_LINK_STATUS_REG   0x154
+#define PCIE_PORT_LINKUP   BIT(8)
+
+#define PCIE_TRANS_TABLE_BASE_REG  0x800
+#define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
+#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
+#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET  0xc
+#define PCIE_ATR_TRSL_PARAM_OFFSET 0x10
+#define PCIE_ATR_TLB_SET_OFFSET0x20
+
+#define PCIE_MAX_TRANS_TABLES  8
+#define PCIE_ATR_ENBIT(0)
+#define PCIE_ATR_SIZE(size) \
+   (size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
+#define PCIE_ATR_ID(id)((id) & GENMASK(3, 0))
+#define PCIE_ATR_TYPE_MEM  PCIE_ATR_ID(0)
+#define PCIE_ATR_TYPE_IO   PCIE_ATR_ID(1)
+#define PCIE_ATR_TLP_TYPE(type)(((type) << 16) & GENMASK(18, 
16))
+#define PCIE_ATR_TLP_TYPE_MEM  PCIE_ATR_TLP_TYPE(0)
+#define PCIE_ATR_TLP_TYPE_IO   PCIE_ATR_TLP_TYPE(2)
+
+/**
+ * struct mtk_pcie_port - PCIe port information
+ * @dev: pointer to PCIe device
+ * @base: IO mapped register base
+ * @reg_base: physical register base
+ * @mac_reset: MAC reset control
+ * @phy_reset: PHY reset control
+ * @phy: PHY controller block
+ * @clks: PCIe clocks
+ * @num_clks: PCIe clock

[v9,7/7] MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer

[Jianjun Wang]

Update entry for MediaTek PCIe controller, add Jianjun Wang
as MediaTek PCI co-maintainer.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85ca831d..8050c14e6a7a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13919,6 +13919,7 @@ F:  drivers/pci/controller/dwc/pcie-histb.c
 
 PCIE DRIVER FOR MEDIATEK
 M: Ryder Lee 
+M: Jianjun Wang 
 L: linux-...@vger.kernel.org
 L: linux-media...@lists.infradead.org
 S: Supported
-- 
2.25.1

[v9,1/7] dt-bindings: PCI: mediatek-gen3: Add YAML schema

[Jianjun Wang]

Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
Reviewed-by: Rob Herring 
---
 .../bindings/pci/mediatek-pcie-gen3.yaml  | 181 ++
 1 file changed, 181 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
new file mode 100644
index ..e7b1f9892da4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -0,0 +1,181 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gen3 PCIe controller on MediaTek SoCs
+
+maintainers:
+  - Jianjun Wang 
+
+description: |+
+  PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
+  and compatible with Gen2, Gen1 speed.
+
+  This PCIe controller supports up to 256 MSI vectors, the MSI hardware
+  block diagram is as follows:
+
++-+
+| GIC |
++-+
+   ^
+   |
+   port->irq
+   |
+   +-+-+-+-+-+-+-+-+
+   |0|1|2|3|4|5|6|7| (PCIe intc)
+   +-+-+-+-+-+-+-+-+
+^ ^   ^
+| |...|
++---+ +--++---+
+|||
+  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
+  |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
+  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
+   ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
+   | |  |  || |  |  || |  |  |  (MSI vectors)
+   | |  |  || |  |  || |  |  |
+
+(MSI SET0)   (MSI SET1)  ...   (MSI SET7)
+
+  With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
+  each set has its own address for MSI message, and supports 32 MSI vectors
+  to generate interrupt.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+const: mediatek,mt8192-pcie
+
+  reg:
+maxItems: 1
+
+  reg-names:
+items:
+  - const: pcie-mac
+
+  interrupts:
+maxItems: 1
+
+  ranges:
+minItems: 1
+maxItems: 8
+
+  resets:
+minItems: 1
+maxItems: 2
+
+  reset-names:
+minItems: 1
+maxItems: 2
+items:
+  - const: phy
+  - const: mac
+
+  clocks:
+maxItems: 6
+
+  clock-names:
+items:
+  - const: pl_250m
+  - const: tl_26m
+  - const: tl_96m
+  - const: tl_32k
+  - const: peri_26m
+  - const: top_133m
+
+  assigned-clocks:
+maxItems: 1
+
+  assigned-clock-parents:
+maxItems: 1
+
+  phys:
+maxItems: 1
+
+  '#interrupt-cells':
+const: 1
+
+  interrupt-controller:
+description: Interrupt controller node for handling legacy PCI interrupts.
+type: object
+properties:
+  '#address-cells':
+const: 0
+  '#interrupt-cells':
+const: 1
+  interrupt-controller: true
+
+required:
+  - '#address-cells'
+  - '#interrupt-cells'
+  - interrupt-controller
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - ranges
+  - clocks
+  - '#interrupt-cells'
+  - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+pcie: pcie@1123 {
+compatible = "mediatek,mt8192-pcie";
+device_type = "pci";
+#address-cells = <3>;
+#size-cells = <2>;
+reg = <0x00 0x1123 0x00 0x4000>;
+reg-names = "pcie-mac";
+interrupts = ;
+bus-range = <0x00 0xff>;
+ranges = <0x8200 0x00 0x1200 0x00
+  0x1200 0x00 0x100>;
+clocks = <&infracfg 44>,
+ <&infracfg 40>,
+ <&infracfg 43>,
+ <&infracfg 97>,
+ <&infracfg 99>,
+ <&infracfg 111>;
+clock-names = "pl_250m", "tl_26m", "tl_96m",
+  "tl_32k", "peri_26m", "top_133m";
+assigned-clocks = <&topckgen 50>;
+assigned-clock-parents = <&topckgen 91>;
+
+phys = <&pciephy>;
+phy-names = "pcie-phy";
+
+resets = <&infracfg_rst 2>,
+  

[v9,2/7] PCI: Export pci_pio_to_address() for module use

[Jianjun Wang]

This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.

Signed-off-by: Jianjun Wang 
---
 drivers/pci/pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 16a17215f633..12bba221c9f2 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4052,6 +4052,7 @@ phys_addr_t pci_pio_to_address(unsigned long pio)
 
return address;
 }
+EXPORT_SYMBOL(pci_pio_to_address);
 
 unsigned long __weak pci_address_to_pio(phys_addr_t address)
 {
-- 
2.25.1

[v9,0/7] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.

Changes in v9:
1. Use mtk_pcie_parse_port() to get the hw resources;
2. Remove unnecessary logs;
3. Add local IRQ enable status save/restore instead of
   the enable/disable callbacks for suspend/resume;
4. Fix typos.

Changes in v8:
1. Add irq_clock to protect IRQ register access;
2. Mask all INTx interrupt when startup port;
3. Remove activate/deactivate callbacks from bottom_domain_ops;
4. Add unmask/mask callbacks in mtk_msi_bottom_irq_chip;
5. Add property information for reg-names.

Changes in v7:
1. Split the driver patch to core PCIe, INTx, MSI and PM patches;
2. Reshape MSI init and handle flow, use msi_bottom_domain to cover all sets;
3. Replace readl/writel with their relaxed version;
4. Add MSI description in binding document;
5. Add pl_250m clock in binding document.

Changes in v6:
1. Export pci_pio_to_address() to support compiling as kernel module;
2. Replace usleep_range(100 * 1000, 120 * 1000) with msleep(100);
3. Replace dev_notice with dev_err;
4. Fix MSI get hwirq flow;
5. Fix warning for possible recursive locking in mtk_pcie_set_affinity.

Changes in v5:
1. Remove unused macros
2. Modify the config read/write callbacks, set the config byte field
   in TLP header and use pci_generic_config_read32/write32
   to access the config space
3. Fix the settings of translation window, both MEM and IO regions
   works properly
4. Fix typos

Changes in v4:
1. Fix PCIe power up/down flow
2. Use "mac" and "phy" for reset names
3. Add clock names
4. Fix the variables type

Changes in v3:
1. Remove standard property in binding document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs

Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown

Jianjun Wang (7):
  dt-bindings: PCI: mediatek-gen3: Add YAML schema
  PCI: Export pci_pio_to_address() for module use
  PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192
  PCI: mediatek-gen3: Add INTx support
  PCI: mediatek-gen3: Add MSI support
  PCI: mediatek-gen3: Add system PM support
  MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer

 .../bindings/pci/mediatek-pcie-gen3.yaml  |  181 +++
 MAINTAINERS   |1 +
 drivers/pci/controller/Kconfig|   13 +
 drivers/pci/controller/Makefile   |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c   | 1025 +
 drivers/pci/pci.c |1 +
 6 files changed, 1222 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

-- 
2.25.1

Re: [v8,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

On Fri, 2021-03-19 at 19:53 +0100, Pali Rohár wrote:
> On Thursday 18 March 2021 13:48:07 Jianjun Wang wrote:
> > On Thu, 2021-03-18 at 01:02 +0100, Pali Rohár wrote:
> > > On Saturday 13 March 2021 15:43:14 Jianjun Wang wrote:
> > > > On Thu, 2021-03-11 at 13:38 +0100, Pali Rohár wrote:
> > > > > On Wednesday 24 February 2021 14:11:28 Jianjun Wang wrote:
> > > > > > +static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
> > > > > > +{
> > > > > ...
> > > > > > +
> > > > > > +   /* Delay 100ms to wait the reference clocks become stable */
> > > > > > +   msleep(100);
> > > > > > +
> > > > > > +   /* De-assert PERST# signal */
> > > > > > +   val &= ~PCIE_PE_RSTB;
> > > > > > +   writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
> > > > > 
> > > > > Hello! This is a new driver which introduce yet another custom timeout
> > > > > prior PERST# signal for PCIe card is de-asserted. Timeouts for other
> > > > > drivers I collected in older email [2].
> > > > > 
> > > > > Please look at my email [1] about PCIe Warm Reset if you have any clue
> > > > > about it. Lorenzo and Rob already expressed that this timeout should 
> > > > > not
> > > > > be driver specific. But nobody was able to "decode" and "understand"
> > > > > PCIe spec yet about these timeouts.
> > > > 
> > > > Hi Pali,
> > > > 
> > > > I think this is more like a platform specific timeout, which is used to
> > > > wait for the reference clocks to become stable and finish the reset flow
> > > > of HW blocks.
> > > > 
> > > > Here is the steps to start a link training in this HW:
> > > > 
> > > > 1. Assert all reset signals which including the transaction layer, PIPE
> > > > interface and internal bus interface;
> > > > 
> > > > 2. De-assert reset signals except the PERST#, this will make the
> > > > physical layer active and start to output the reference clock, but the
> > > > EP device remains in the reset state.
> > > >Before releasing the PERST# signal, the HW blocks needs at least 10ms
> > > > to finish the reset flow, and ref-clk needs about 30us to become stable.
> > > > 
> > > > 3. De-assert PERST# signal, wait LTSSM enter L0 state.
> > > > 
> > > > This 100ms timeout is reference to TPVPERL in the PCIe CEM spec. Since
> > > > we are in the kernel stage, the power supply has already stabled, this
> > > > timeout may not take that long.
> > > 
> > > I think that this is not platform specific timeout or platform specific
> > > steps. This matches generic steps as defined in PCIe CEM spec, section
> > > 2.2.1. Initial Power-Up (G3 to S0).
> > > 
> > > What is platform specific is just how to achieve these steps.
> > > 
> > > Am I right?
> > > 
> > > ...
> > > 
> > > TPVPERL is one of my timeout candidates as minimal required timeout for
> > > Warm Reset. I have wrote it in email:
> > > 
> > > https://lore.kernel.org/linux-pci/20200430082245.xblvb7xeamm4e336@pali/
> > > 
> > > But I'm not sure as specially in none diagram is described just warm
> > > reset as defined in mPCIe CEM (3.2.4.3. PERST# Signal).
> > > 
> > > ...
> > > 
> > > Anyway, I would suggest to define constants for those timeouts. I guess
> > > that in future we could be able to define "generic" timeout constants
> > > which would not be in private driver section, but in some common header
> > > file.
> > 
> > I agree with this, but I'm not sure if we really need that long time in
> > the kernel stage, because the power supply has already stable and it's
> > really impact the boot time, especially when the platform have multi
> > ports and not connect any EP device, we need to wait 200ms for each port
> > when system bootup.
> 
> Ports are independent. So you can initialize them in parallel, right?
> 
> If you initialize each port in separate worker then during msleep calls
> kernel can schedule other kernel thread to run and so it does not
> increase boot time. While pcie is sleeping kernel can do other things.
> So the result is that whole boot time is not increased, just reordered.
> 
> > F

Re: [v8,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

On Thu, 2021-03-18 at 01:02 +0100, Pali Rohár wrote:
> On Saturday 13 March 2021 15:43:14 Jianjun Wang wrote:
> > On Thu, 2021-03-11 at 13:38 +0100, Pali Rohár wrote:
> > > On Wednesday 24 February 2021 14:11:28 Jianjun Wang wrote:
> > > > +static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
> > > > +{
> > > ...
> > > > +
> > > > +   /* Delay 100ms to wait the reference clocks become stable */
> > > > +   msleep(100);
> > > > +
> > > > +   /* De-assert PERST# signal */
> > > > +   val &= ~PCIE_PE_RSTB;
> > > > +   writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
> > > 
> > > Hello! This is a new driver which introduce yet another custom timeout
> > > prior PERST# signal for PCIe card is de-asserted. Timeouts for other
> > > drivers I collected in older email [2].
> > > 
> > > Please look at my email [1] about PCIe Warm Reset if you have any clue
> > > about it. Lorenzo and Rob already expressed that this timeout should not
> > > be driver specific. But nobody was able to "decode" and "understand"
> > > PCIe spec yet about these timeouts.
> > 
> > Hi Pali,
> > 
> > I think this is more like a platform specific timeout, which is used to
> > wait for the reference clocks to become stable and finish the reset flow
> > of HW blocks.
> > 
> > Here is the steps to start a link training in this HW:
> > 
> > 1. Assert all reset signals which including the transaction layer, PIPE
> > interface and internal bus interface;
> > 
> > 2. De-assert reset signals except the PERST#, this will make the
> > physical layer active and start to output the reference clock, but the
> > EP device remains in the reset state.
> >Before releasing the PERST# signal, the HW blocks needs at least 10ms
> > to finish the reset flow, and ref-clk needs about 30us to become stable.
> > 
> > 3. De-assert PERST# signal, wait LTSSM enter L0 state.
> > 
> > This 100ms timeout is reference to TPVPERL in the PCIe CEM spec. Since
> > we are in the kernel stage, the power supply has already stabled, this
> > timeout may not take that long.
> 
> I think that this is not platform specific timeout or platform specific
> steps. This matches generic steps as defined in PCIe CEM spec, section
> 2.2.1. Initial Power-Up (G3 to S0).
> 
> What is platform specific is just how to achieve these steps.
> 
> Am I right?
> 
> ...
> 
> TPVPERL is one of my timeout candidates as minimal required timeout for
> Warm Reset. I have wrote it in email:
> 
> https://lore.kernel.org/linux-pci/20200430082245.xblvb7xeamm4e336@pali/
> 
> But I'm not sure as specially in none diagram is described just warm
> reset as defined in mPCIe CEM (3.2.4.3. PERST# Signal).
> 
> ...
> 
> Anyway, I would suggest to define constants for those timeouts. I guess
> that in future we could be able to define "generic" timeout constants
> which would not be in private driver section, but in some common header
> file.

I agree with this, but I'm not sure if we really need that long time in
the kernel stage, because the power supply has already stable and it's
really impact the boot time, especially when the platform have multi
ports and not connect any EP device, we need to wait 200ms for each port
when system bootup.

For this PCIe controller driver, I would like to change the timeout
value to 10ms to comply with the HW design, and save some boot time.

> 
> > > > +
> > > > +   /* Check if the link is up or not */
> > > > +   err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_REG, val,
> > > > +!!(val & PCIE_PORT_LINKUP), 20,
> > > > +50 * USEC_PER_MSEC);
> > > 
> > > IIRC, you need to wait at least 100ms after de-asserting PERST# signal
> > > as it is required by PCIe specs and also because experiments proved that
> > > some Compex wifi cards (e.g. WLE900VX) are not detected if you do not
> > > wait this minimal time.
> > 
> > Yes, this should be 100ms, I will fix it at next version, thanks for
> > your review.
> 
> In past Bjorn suggested to use msleep(PCI_PM_D3COLD_WAIT); macro for
> this step during reviewing aardvark driver.
> 
> https://lore.kernel.org/linux-pci/20190426161050.ga189...@google.com/
> 
> And next iteration used this PCI_PM_D3COLD_WAIT macro instead of 100:
> 
> https://lore.kernel.org/linux-pci/20190522213351.21366-2-r...@triplefau.lt/

Sure, I will use PCI_PM_D3COLD_WAIT macro instead in the next version.

Thanks.

> 
> > Thanks.
> > > 
> > > > +   if (err) {
> > > > +   val = readl_relaxed(port->base + PCIE_LTSSM_STATUS_REG);
> > > > +   dev_err(port->dev, "PCIe link down, ltssm reg val: 
> > > > %#x\n", val);
> > > > +   return err;
> > > > +   }
> > > 
> > > [1] - 
> > > https://lore.kernel.org/linux-pci/20210310110535.zh4pnn4vpmvzwl5q@pali/
> > > [2] - 
> > > https://lore.kernel.org/linux-pci/20200424092546.25p3hdtkehohe3xw@pali/
> > 

Re: [v8,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

On Thu, 2021-03-11 at 13:38 +0100, Pali Rohár wrote:
> On Wednesday 24 February 2021 14:11:28 Jianjun Wang wrote:
> > +static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
> > +{
> ...
> > +
> > +   /* Delay 100ms to wait the reference clocks become stable */
> > +   msleep(100);
> > +
> > +   /* De-assert PERST# signal */
> > +   val &= ~PCIE_PE_RSTB;
> > +   writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
> 
> Hello! This is a new driver which introduce yet another custom timeout
> prior PERST# signal for PCIe card is de-asserted. Timeouts for other
> drivers I collected in older email [2].
> 
> Please look at my email [1] about PCIe Warm Reset if you have any clue
> about it. Lorenzo and Rob already expressed that this timeout should not
> be driver specific. But nobody was able to "decode" and "understand"
> PCIe spec yet about these timeouts.

Hi Pali,

I think this is more like a platform specific timeout, which is used to
wait for the reference clocks to become stable and finish the reset flow
of HW blocks.

Here is the steps to start a link training in this HW:

1. Assert all reset signals which including the transaction layer, PIPE
interface and internal bus interface;

2. De-assert reset signals except the PERST#, this will make the
physical layer active and start to output the reference clock, but the
EP device remains in the reset state.
   Before releasing the PERST# signal, the HW blocks needs at least 10ms
to finish the reset flow, and ref-clk needs about 30us to become stable.

3. De-assert PERST# signal, wait LTSSM enter L0 state.

This 100ms timeout is reference to TPVPERL in the PCIe CEM spec. Since
we are in the kernel stage, the power supply has already stabled, this
timeout may not take that long.

> > +
> > +   /* Check if the link is up or not */
> > +   err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_REG, val,
> > +!!(val & PCIE_PORT_LINKUP), 20,
> > +50 * USEC_PER_MSEC);
> 
> IIRC, you need to wait at least 100ms after de-asserting PERST# signal
> as it is required by PCIe specs and also because experiments proved that
> some Compex wifi cards (e.g. WLE900VX) are not detected if you do not
> wait this minimal time.

Yes, this should be 100ms, I will fix it at next version, thanks for
your review.

Thanks.
> 
> > +   if (err) {
> > +   val = readl_relaxed(port->base + PCIE_LTSSM_STATUS_REG);
> > +   dev_err(port->dev, "PCIe link down, ltssm reg val: %#x\n", val);
> > +   return err;
> > +   }
> 
> [1] - https://lore.kernel.org/linux-pci/20210310110535.zh4pnn4vpmvzwl5q@pali/
> [2] - https://lore.kernel.org/linux-pci/20200424092546.25p3hdtkehohe3xw@pali/

Re: [v8,5/7] PCI: mediatek-gen3: Add MSI support

[Jianjun Wang]

On Thu, 2021-03-11 at 08:19 +, Marc Zyngier wrote:
> On 2021-03-11 00:05, Pali Rohár wrote:
> > On Wednesday 24 February 2021 14:11:30 Jianjun Wang wrote:
> >> +static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain,
> >> + unsigned int virq, unsigned int nr_irqs,
> >> + void *arg)
> >> +{
> >> +  struct mtk_pcie_port *port = domain->host_data;
> >> +  struct mtk_msi_set *msi_set;
> >> +  int i, hwirq, set_idx;
> >> +
> >> +  mutex_lock(&port->lock);
> >> +
> >> +  hwirq = bitmap_find_free_region(port->msi_irq_in_use, 
> >> PCIE_MSI_IRQS_NUM,
> >> +  order_base_2(nr_irqs));
> >> +
> >> +  mutex_unlock(&port->lock);
> >> +
> >> +  if (hwirq < 0)
> >> +  return -ENOSPC;
> >> +
> >> +  set_idx = hwirq / PCIE_MSI_IRQS_PER_SET;
> >> +  msi_set = &port->msi_sets[set_idx];
> >> +
> >> +  for (i = 0; i < nr_irqs; i++)
> >> +  irq_domain_set_info(domain, virq + i, hwirq + i,
> >> +  &mtk_msi_bottom_irq_chip, msi_set,
> >> +  handle_edge_irq, NULL, NULL);
> >> +
> >> +  return 0;
> >> +}
> >> +
> >> +static void mtk_msi_bottom_domain_free(struct irq_domain *domain,
> >> + unsigned int virq, unsigned int nr_irqs)
> >> +{
> >> +  struct mtk_pcie_port *port = domain->host_data;
> >> +  struct irq_data *data = irq_domain_get_irq_data(domain, virq);
> >> +
> >> +  mutex_lock(&port->lock);
> >> +
> >> +  bitmap_clear(port->msi_irq_in_use, data->hwirq, nr_irqs);
> > 
> > Marc, should not be there bitmap_release_region() with order_base_2()?
> > 
> > bitmap_release_region(port->msi_irq_in_use, data->hwirq, 
> > order_base_2(nr_irqs));
> > 
> > Because mtk_msi_bottom_domain_alloc() is allocating
> > order_base_2(nr_irqs) interrupts, not only nr_irqs.
> 
> Indeed, good catch.

I will fix it in the next version, thanks for your review.

> 
> Thanks,
> 
>  M.

Re: [v8,5/7] PCI: mediatek-gen3: Add MSI support

[Jianjun Wang]

On Wed, 2021-03-10 at 09:41 +, Marc Zyngier wrote:
> On Wed, 10 Mar 2021 06:48:49 +,
> Jianjun Wang  wrote:
> > > > +static struct irq_chip mtk_msi_irq_chip = {
> > > > +   .name = "MSI",
> > > > +   .irq_enable = mtk_pcie_irq_unmask,
> > > > +   .irq_disable = mtk_pcie_irq_mask,
> > > 
> > > Same comment as for the previous patch: enable/disable serve no
> > > purpose here.
> > 
> > Replied in the previous patch, the enable/disable callback is used when
> > the system suspend/resume.
> 
> As I said, your suspend/resume should be self contained, and not rely
> on the irq subsystem to restore a viable state.

OK, I will try to find another way to save and restore the enabled state
of interrupts when the system suspend/resume.

> 
> [...]
> 
> > > > @@ -408,6 +677,14 @@ static void mtk_pcie_irq_handler(struct irq_desc 
> > > > *desc)
> > > > generic_handle_irq(virq);
> > > > }
> > > >  
> > > > +   irq_bit = PCIE_MSI_SHIFT;
> > > > +   for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM +
> > > > + PCIE_MSI_SHIFT) {
> > > > +   mtk_pcie_msi_handler(port, irq_bit - PCIE_MSI_SHIFT);
> > > > +
> > > > +   writel_relaxed(BIT(irq_bit), port->base + 
> > > > PCIE_INT_STATUS_REG);
> > > 
> > > Isn't this write the same thing you have for EOI in the INTx case?
> > > While I could understand your description in that case (this is a
> > > resampling operation), I don't get what this does here. Either this is
> > > also an EOI, but your initial description doesn't make sense, or it is
> > > an Ack, and it should be moved to the right place.
> > > 
> > > Which one is it?
> > 
> > I think it should be an EOI which used to clear the interrupt status of
> > a single set in the PCIe intc field, maybe I should move it to the end
> > of the mtk_pcie_msi_handler() function.
> 
> I doubt this is an EOI. If, as I suspect, it instructs the HW to clear
> the bit so that new pending bits can be recorded, it must take place
> *before* the interrupt is handled, or you may lose MSIs in the
> interval between the handling of the interrupt and the clearing of the
> pending bit. To satisfy this requirement, this should be an ACK, which
> is consistent with the way most MSI controllers such as this one work.

These bits are similar with the interrupt status of INTx, and the
interrupt status will remain until all the status of the corresponding
set are cleared. There is a while loop in mtk_pcie_msi_handler() which
is used to continuously polling and ACK the status of the MSI set, I
think the MSI may not be lose in this case.
 
> 
> > 
> >   +-+
> >   | GIC |
> >   +-+
> >  ^
> >  |
> >  port->irq
> >  |
> >  +-+-+-+-+-+-+-+-+
> >  |0|1|2|3|4|5|6|7| (PCIe intc)
> >  +-+-+-+-+-+-+-+-+
> >   ^ ^   ^
> >   | |...|
> >   +---+ +--++---+
> >   |||
> > +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
> > |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
> > +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
> >  ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
> >  | |  |  || |  |  || |  |  |  (MSI vectors)
> >  | |  |  || |  |  || |  |  |
> > 
> >   (MSI SET0)   (MSI SET1)  ...   (MSI SET7)
> > 
> > I would like to ask another question. In this interrupt architecture, we
> > cannot implement an affinity for PCIe interrupts, so we return a
> > negative value in the mtk_pcie_set_affinity callback as follows: 
> > 
> > +static int mtk_pcie_set_affinity(struct irq_data *data,
> > +const struct cpumask *mask, bool force)
> > +{
> > +   return -EINVAL;
> > +}
> > 
> > But there will always be error logs when hotplug a CPU:
> > 
> > ~ # echo 0 > /sys/devices/system/cpu/cpu1/online
> > [   93.633059] IRQ255: set affinity failed(-22).
> > [   93.633624] IRQ256: set affinity failed(-22).
> > [   93.634222] CPU1: shutdown
> > [   93.634586] psci: CPU1 killed (polled 0 ms)
> > 
> > Or when the system suspends:
> > 
> &

Re: [v8,5/7] PCI: mediatek-gen3: Add MSI support

[Jianjun Wang]

Hi Marc,

Thanks for your review.

On Tue, 2021-03-09 at 11:23 +, Marc Zyngier wrote:
> On Wed, 24 Feb 2021 06:11:30 +,
> Jianjun Wang  wrote:
> > 
> > Add MSI support for MediaTek Gen3 PCIe controller.
> > 
> > This PCIe controller supports up to 256 MSI vectors, the MSI hardware
> > block diagram is as follows:
> > 
> >   +-+
> >   | GIC |
> >   +-+
> >  ^
> >  |
> >  port->irq
> >  |
> >  +-+-+-+-+-+-+-+-+
> >  |0|1|2|3|4|5|6|7| (PCIe intc)
> >  +-+-+-+-+-+-+-+-+
> >   ^ ^   ^
> >   | |...|
> >   +---+ +--++---+
> >   |||
> > +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
> > |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
> > +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
> >  ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
> >  | |  |  || |  |  || |  |  |  (MSI vectors)
> >  | |  |  || |  |  || |  |  |
> > 
> >   (MSI SET0)   (MSI SET1)  ...   (MSI SET7)
> > 
> > With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
> > each set has its own address for MSI message, and supports 32 MSI vectors
> > to generate interrupt.
> > 
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> > ---
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 277 
> >  1 file changed, 277 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > index 8b3b5f838b69..3cbec22ece0c 100644
> > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -14,6 +14,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -48,12 +49,29 @@
> >  #define PCIE_LINK_STATUS_REG   0x154
> >  #define PCIE_PORT_LINKUP   BIT(8)
> >  
> > +#define PCIE_MSI_SET_NUM   8
> > +#define PCIE_MSI_IRQS_PER_SET  32
> > +#define PCIE_MSI_IRQS_NUM \
> > +   (PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM)
> > +
> >  #define PCIE_INT_ENABLE_REG0x180
> > +#define PCIE_MSI_ENABLEGENMASK(PCIE_MSI_SET_NUM + 8 - 
> > 1, 8)
> > +#define PCIE_MSI_SHIFT 8
> >  #define PCIE_INTX_SHIFT24
> >  #define PCIE_INTX_ENABLE \
> > GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
> >  
> >  #define PCIE_INT_STATUS_REG0x184
> > +#define PCIE_MSI_SET_ENABLE_REG0x190
> > +#define PCIE_MSI_SET_ENABLEGENMASK(PCIE_MSI_SET_NUM - 1, 0)
> > +
> > +#define PCIE_MSI_SET_BASE_REG  0xc00
> > +#define PCIE_MSI_SET_OFFSET0x10
> > +#define PCIE_MSI_SET_STATUS_OFFSET 0x04
> > +#define PCIE_MSI_SET_ENABLE_OFFSET 0x08
> > +
> > +#define PCIE_MSI_SET_ADDR_HI_BASE  0xc80
> > +#define PCIE_MSI_SET_ADDR_HI_OFFSET0x04
> >  
> >  #define PCIE_TRANS_TABLE_BASE_REG  0x800
> >  #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
> > @@ -73,6 +91,16 @@
> >  #define PCIE_ATR_TLP_TYPE_MEM  PCIE_ATR_TLP_TYPE(0)
> >  #define PCIE_ATR_TLP_TYPE_IO   PCIE_ATR_TLP_TYPE(2)
> >  
> > +/**
> > + * struct mtk_pcie_msi - MSI information for each set
> > + * @base: IO mapped register base
> > + * @msg_addr: MSI message address
> > + */
> > +struct mtk_msi_set {
> > +   void __iomem *base;
> > +   phys_addr_t msg_addr;
> > +};
> > +
> >  /**
> >   * struct mtk_pcie_port - PCIe port information
> >   * @dev: pointer to PCIe device
> > @@ -86,6 +114,11 @@
> >   * @irq: PCIe controller interrupt number
> >   * @irq_lock: lock protecting IRQ register access
> >   * @intx_domain: legacy INTx IRQ domain
> > + * @msi_domain: MSI IRQ domain
> > + * @msi_bottom_domain: MSI IRQ bottom domain
> > + * @msi_sets: MSI sets information
> > + * @lock: lock protecting IRQ bit map
> > + * @msi_irq_in_use: bit map for assigned MSI IRQ
> >   */
> >  struct mtk_pcie_port {
> > struct device *dev;
> > @@ -100,6 +133,11 @@ struct mtk_pcie_port {
> > int irq;
> 

Re: [v8,4/7] PCI: mediatek-gen3: Add INTx support

[Jianjun Wang]

On Tue, 2021-03-09 at 11:10 +, Marc Zyngier wrote:
> On Wed, 24 Feb 2021 06:11:29 +,
> Jianjun Wang  wrote:
> > 
> > Add INTx support for MediaTek Gen3 PCIe controller.
> > 
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> > ---
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 176 
> >  1 file changed, 176 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > index c602beb9afec..8b3b5f838b69 100644
> > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -9,6 +9,9 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -45,6 +48,13 @@
> >  #define PCIE_LINK_STATUS_REG   0x154
> >  #define PCIE_PORT_LINKUP   BIT(8)
> >  
> > +#define PCIE_INT_ENABLE_REG0x180
> > +#define PCIE_INTX_SHIFT24
> > +#define PCIE_INTX_ENABLE \
> > +   GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
> > +
> > +#define PCIE_INT_STATUS_REG0x184
> > +
> >  #define PCIE_TRANS_TABLE_BASE_REG  0x800
> >  #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
> >  #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
> > @@ -73,6 +83,9 @@
> >   * @phy: PHY controller block
> >   * @clks: PCIe clocks
> >   * @num_clks: PCIe clocks count for this port
> > + * @irq: PCIe controller interrupt number
> > + * @irq_lock: lock protecting IRQ register access
> > + * @intx_domain: legacy INTx IRQ domain
> >   */
> >  struct mtk_pcie_port {
> > struct device *dev;
> > @@ -83,6 +96,10 @@ struct mtk_pcie_port {
> > struct phy *phy;
> > struct clk_bulk_data *clks;
> > int num_clks;
> > +
> > +   int irq;
> > +   raw_spinlock_t irq_lock;
> > +   struct irq_domain *intx_domain;
> >  };
> >  
> >  /**
> > @@ -199,6 +216,11 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port 
> > *port)
> > val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8);
> > writel_relaxed(val, port->base + PCIE_PCI_IDS_1);
> >  
> > +   /* Mask all INTx interrupts */
> > +   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
> > +   val &= ~PCIE_INTX_ENABLE;
> > +   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
> > +
> > /* Assert all reset signals */
> > val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
> > val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
> > @@ -262,6 +284,154 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port 
> > *port)
> > return 0;
> >  }
> >  
> > +static int mtk_pcie_set_affinity(struct irq_data *data,
> > +const struct cpumask *mask, bool force)
> > +{
> > +   return -EINVAL;
> > +}
> > +
> > +static void mtk_intx_mask(struct irq_data *data)
> > +{
> > +   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
> > +   unsigned long flags;
> > +   u32 val;
> > +
> > +   raw_spin_lock_irqsave(&port->irq_lock, flags);
> > +   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
> > +   val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
> > +   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
> > +   raw_spin_unlock_irqrestore(&port->irq_lock, flags);
> > +}
> > +
> > +static void mtk_intx_unmask(struct irq_data *data)
> > +{
> > +   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
> > +   unsigned long flags;
> > +   u32 val;
> > +
> > +   raw_spin_lock_irqsave(&port->irq_lock, flags);
> > +   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
> > +   val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
> > +   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
> > +   raw_spin_unlock_irqrestore(&port->irq_lock, flags);
> > +}
> > +
> > +/**
> > + * mtk_intx_eoi
> > + * @data: pointer to chip specific data
> > + *
> > + * As an emulated level IRQ, its interrupt status will remain
> > + * until the corresponding de-assert message is received; hence that
> > + * the status can only be cleared when the interrupt has been serviced.
> > + */
> > +static void mtk_intx_eoi(struct irq_data *data)
> > +{
> > +   struct mtk_pcie_

Re: [v8,6/7] PCI: mediatek-gen3: Add system PM support

[Jianjun Wang]

Hi Krzysztof,

Thanks for your suggestion, I will fix it in the next version.

On Thu, 2021-02-25 at 23:00 +0100, Krzysztof Wilczyński wrote:
> Hi Jianjun,
> 
> [...]
> > Thanks for your review,
> 
> Thank YOU for all the work here!
>  
> [...]
> > > > Add suspend_noirq and resume_noirq callback functions to implement
> > > > PM system suspend hooks for MediaTek Gen3 PCIe controller.
> > > 
> > > So, "systems suspend" and "resume" hooks, correct?
> > 
> > The callback functions is suspend_noirq and resume_noirq, should I use
> > "systems suspend" and "resume" in the commit message?
> [...]
> 
> 
> What I meant was something along these lines:
> 
>   Add suspend_noirq and resume_noirq callback functions to implement PM
>   system suspend and resume hooks for the MediaTek Gen3 PCIe controller.
>   
>   When the system suspends, trigger the PCIe link to enter the L2 state
>   and pull down the PERST# pin, gating the clocks of the MAC layer, and
>   then power-off the physical layer to provide power-saving.
>   
>   When the system resumes, the PCIe link should be re-established and the
>   related control register values should be restored.
> 
> The above is just a suggestion, thus feel tree to ignore it completely,
> and it's heavily based on your original commit message.
> 
> Krzysztof

Thanks.

Re: [v8,6/7] PCI: mediatek-gen3: Add system PM support

[Jianjun Wang]

Hi Krzysztof,

Thanks for your review,

On Wed, 2021-02-24 at 15:10 +0100, Krzysztof Wilczyński wrote:
> Hi Jianjun,
> 
> > Add suspend_noirq and resume_noirq callback functions to implement
> > PM system suspend hooks for MediaTek Gen3 PCIe controller.
> 
> So, "systems suspend" and "resume" hooks, correct?

The callback functions is suspend_noirq and resume_noirq, should I use
"systems suspend" and "resume" in the commit message?

> 
> > When system suspend, trigger the PCIe link to L2 state and pull down
> 
> It probably would be "the system suspends".
> 
> [...]
> > When system resum, the PCIe link should be re-established and the
> > related control register values should be restored.
> 
> Similarly to the above: "the system resumes".
> 
> [...]
> > +   if (err) {
> > +   dev_err(port->dev, "can not enter L2 state\n");
> > +   return err;
> > +   }
> 
> Most likely you want "cannot" or "can't" in the above error message.
> 
> > +   /* Pull down the PERST# pin */
> > +   val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
> > +   val |= PCIE_PE_RSTB;
> > +   writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
> > +
> > +   dev_dbg(port->dev, "enter L2 state success");
> 
> Just a nitpick.  What about "entered L2 states successfully"?
> 
> [...]
> > +   if (err) {
> > +   dev_err(port->dev, "resume failed\n");
> > +   return err;
> > +   }
> 
> This error message does not quite convey that the mtk_pcie_startup_port()
> was the function that failed, which is only a part of what you have to do
> to successfully resume.
> 
> > +   dev_dbg(port->dev, "resume done\n");
> 
> A nitpick.  Probably not needed, as lack of error message would mean
> that the device resumed successfully after being suspended.
> 
> Krzysztof

Thanks.

Re: [v8,4/7] PCI: mediatek-gen3: Add INTx support

[Jianjun Wang]

Hi Krzysztof,

Thanks for your review, I will fix it at next version.

On Wed, 2021-02-24 at 15:24 +0100, Krzysztof Wilczyński wrote:
> Hi Jianjun,
> 
> [...]
> > +/**
> > + * mtk_intx_eoi
> > + * @data: pointer to chip specific data
> > + *
> > + * As an emulated level IRQ, its interrupt status will remain
> > + * until the corresponding de-assert message is received; hence that
> > + * the status can only be cleared when the interrupt has been serviced.
> > + */
> [...]
> 
> See my comment about the kernel-doc from the following:
> 
>   https://lore.kernel.org/linux-pci/YDZWUGcKet%2FlNWlF@rocinante/
> 
> [...]
> > +   if (err) {
> > +   dev_err(dev, "failed to init PCIe IRQ domain\n");
> > +   return err;
> > +   }
> [...]
> 
> Just a nitpick.  What about using "initialize" in the above?
> 
> Krzysztof

Thanks.

Re: [v8,5/7] PCI: mediatek-gen3: Add MSI support

[Jianjun Wang]

Hi Krzysztof,

Thanks for your review, I will fix it at next version.

On Wed, 2021-02-24 at 15:31 +0100, Krzysztof Wilczyński wrote:
> Hi Jianjun,
> 
> [...]
> > +static struct irq_chip mtk_msi_irq_chip = {
> > +   .name = "MSI",
> > +   .irq_enable = mtk_pcie_irq_unmask,
> > +   .irq_disable = mtk_pcie_irq_mask,
> > +   .irq_ack = irq_chip_ack_parent,
> > +   .irq_mask = mtk_pcie_irq_mask,
> > +   .irq_unmask = mtk_pcie_irq_unmask,
> > +};
> 
> For consistency sake, what about aligning this like the
> struct mtk_msi_bottom_irq_chip has been?  See immediately below.
> 
> [...]
> > +static struct irq_chip mtk_msi_bottom_irq_chip = {
> > +   .irq_ack= mtk_msi_bottom_irq_ack,
> > +   .irq_mask   = mtk_msi_bottom_irq_mask,
> > +   .irq_unmask = mtk_msi_bottom_irq_unmask,
> > +   .irq_compose_msi_msg= mtk_compose_msi_msg,
> > +   .irq_set_affinity   = mtk_pcie_set_affinity,
> > +   .name   = "MSI",
> > +};
> 
> Krzysztof

Thanks.

Re: [v8,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

Hi Krzysztof,

Thanks for your review, I will fix these at next version.

Thanks.

On Wed, 2021-02-24 at 14:36 +0100, Krzysztof Wilczyński wrote:
> Hi Jianjun,
> 
> Thank you for all the work here!
> 
> [...]
> > + * struct mtk_pcie_port - PCIe port information
> > + * @dev: pointer to PCIe device
> > + * @base: IO mapped register base
> > + * @reg_base: Physical register base
> > + * @mac_reset: mac reset control
> > + * @phy_reset: phy reset control
> > + * @phy: PHY controller block
> > + * @clks: PCIe clocks
> > + * @num_clks: PCIe clocks count for this port
> 
> It would be "MAC" and "PHY" in the above.
> 
> [...]
> > + * mtk_pcie_config_tlp_header
> > + * @bus: PCI bus to query
> > + * @devfn: device/function number
> > + * @where: offset in config space
> > + * @size: data size in TLP header
> > + *
> > + * Set byte enable field and device information in configuration TLP 
> > header.
> 
> The kernel-doc above might be missing brief function description.  See
> the following for more concrete example:
> 
>   
> https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#function-documentation
> 
> [...]
> > +static int mtk_pcie_set_trans_table(struct mtk_pcie_port *port,
> > +   resource_size_t cpu_addr,
> > +   resource_size_t pci_addr,
> > +   resource_size_t size,
> > +   unsigned long type, int num)
> > +{
> > +   void __iomem *table;
> > +   u32 val;
> > +
> > +   if (num >= PCIE_MAX_TRANS_TABLES) {
> > +   dev_err(port->dev, "not enough translate table[%d] for addr: 
> > %#llx, limited to [%d]\n",
> 
> The wording of this error message is a little confusing.
> 
> > +   num, (unsigned long long) cpu_addr,
> 
> No space between the bracket and the variable name.
> 
> [...]
> > +   err = phy_init(port->phy);
> > +   if (err) {
> > +   dev_err(dev, "failed to initialize PCIe phy\n");
> > +   goto err_phy_init;
> > +   }
> > +
> > +   err = phy_power_on(port->phy);
> > +   if (err) {
> > +   dev_err(dev, "failed to power on PCIe phy\n");
> > +   goto err_phy_on;
> > +   }
> [...]
> 
> It would be "PHY" in the error messages above.
> 
> [...]
> > +   if (err) {
> > +   dev_err(dev, "clock init failed\n");
> > +   goto err_clk_init;
> > +   }
> [...]
> 
> A nitpick, so feel free to ignore it, of course.  What about "failed to
> initialize clock" to keep the style consistent.
> 
> [...]
> > +   err = mtk_pcie_startup_port(port);
> > +   if (err) {
> > +   dev_err(dev, "PCIe startup failed\n");
> [...]
> 
> Also a nitpick.  What about "failed to bring PCIe link up"?
> 
> Krzysztof

[v8,7/7] MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer

[Jianjun Wang]

Update entry for MediaTek PCIe controller, add Jianjun Wang
as MediaTek PCI co-maintainer.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 546aa66428c9..bef7f4017473 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13826,6 +13826,7 @@ F:  drivers/pci/controller/dwc/pcie-histb.c
 
 PCIE DRIVER FOR MEDIATEK
 M: Ryder Lee 
+M: Jianjun Wang 
 L: linux-...@vger.kernel.org
 L: linux-media...@lists.infradead.org
 S: Supported
-- 
2.25.1

[v8,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
compatible with Gen2, Gen1 speed.

Add support for new Gen3 controller which can be found on MT8192.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/Kconfig  |  13 +
 drivers/pci/controller/Makefile |   1 +
 drivers/pci/controller/pcie-mediatek-gen3.c | 457 
 3 files changed, 471 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 64e2f5e379aa..b242b17025b3 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -242,6 +242,19 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable PCIe controller support on
  MediaTek SoCs.
 
+config PCIE_MEDIATEK_GEN3
+   tristate "MediaTek Gen3 PCIe controller"
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   depends on PCI_MSI_IRQ_DOMAIN
+   help
+ Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
+ This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed,
+ and support up to 256 MSI interrupt numbers for
+ multi-function devices.
+
+ Say Y here if you want to enable Gen3 PCIe controller support on
+ MediaTek SoCs.
+
 config PCIE_TANGO_SMP8759
bool "Tango SMP8759 PCIe controller (DANGEROUS)"
depends on ARCH_TANGO && PCI_MSI && OF
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 04c6edc285c5..df5d77d72a9d 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
 obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
new file mode 100644
index ..c602beb9afec
--- /dev/null
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -0,0 +1,457 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Jianjun Wang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pci.h"
+
+#define PCIE_SETTING_REG   0x80
+#define PCIE_PCI_IDS_1 0x9c
+#define PCI_CLASS(class)   (class << 8)
+#define PCIE_RC_MODE   BIT(0)
+
+#define PCIE_CFGNUM_REG0x140
+#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
+#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
+#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
16))
+#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
+#define PCIE_CFG_OFFSET_ADDR   0x1000
+#define PCIE_CFG_HEADER(bus, devfn) \
+   (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
+
+#define PCIE_RST_CTRL_REG  0x148
+#define PCIE_MAC_RSTB  BIT(0)
+#define PCIE_PHY_RSTB  BIT(1)
+#define PCIE_BRG_RSTB  BIT(2)
+#define PCIE_PE_RSTB   BIT(3)
+
+#define PCIE_LTSSM_STATUS_REG  0x150
+
+#define PCIE_LINK_STATUS_REG   0x154
+#define PCIE_PORT_LINKUP   BIT(8)
+
+#define PCIE_TRANS_TABLE_BASE_REG  0x800
+#define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
+#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
+#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET  0xc
+#define PCIE_ATR_TRSL_PARAM_OFFSET 0x10
+#define PCIE_ATR_TLB_SET_OFFSET0x20
+
+#define PCIE_MAX_TRANS_TABLES  8
+#define PCIE_ATR_ENBIT(0)
+#define PCIE_ATR_SIZE(size) \
+   (size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
+#define PCIE_ATR_ID(id)((id) & GENMASK(3, 0))
+#define PCIE_ATR_TYPE_MEM  PCIE_ATR_ID(0)
+#define PCIE_ATR_TYPE_IO   PCIE_ATR_ID(1)
+#define PCIE_ATR_TLP_TYPE(type)(((type) << 16) & GENMASK(18, 
16))
+#define PCIE_ATR_TLP_TYPE_MEM  PCIE_ATR_TLP_TYPE(0)
+#define PCIE_ATR_TLP_TYPE_IO   PCIE_ATR_TLP_TYPE(2)
+
+/**
+ * struct mtk_pcie_port - PCIe port information
+ * @dev: pointer to PCIe device
+ * @base: IO mapped register base
+ * @reg_base: Physical register base
+ * @mac_reset: mac reset control
+ * @phy_reset: phy reset control
+ * @phy: PHY controller block
+ * @clks: PCIe clocks
+ * @num_clks: PCIe clock

[v8,5/7] PCI: mediatek-gen3: Add MSI support

[Jianjun Wang]

Add MSI support for MediaTek Gen3 PCIe controller.

This PCIe controller supports up to 256 MSI vectors, the MSI hardware
block diagram is as follows:

  +-+
  | GIC |
  +-+
 ^
 |
 port->irq
 |
 +-+-+-+-+-+-+-+-+
 |0|1|2|3|4|5|6|7| (PCIe intc)
 +-+-+-+-+-+-+-+-+
  ^ ^   ^
  | |...|
  +---+ +--++---+
  |||
+-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
|0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
+-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
 ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
 | |  |  || |  |  || |  |  |  (MSI vectors)
 | |  |  || |  |  || |  |  |

  (MSI SET0)   (MSI SET1)  ...   (MSI SET7)

With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
each set has its own address for MSI message, and supports 32 MSI vectors
to generate interrupt.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 277 
 1 file changed, 277 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
index 8b3b5f838b69..3cbec22ece0c 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -48,12 +49,29 @@
 #define PCIE_LINK_STATUS_REG   0x154
 #define PCIE_PORT_LINKUP   BIT(8)
 
+#define PCIE_MSI_SET_NUM   8
+#define PCIE_MSI_IRQS_PER_SET  32
+#define PCIE_MSI_IRQS_NUM \
+   (PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM)
+
 #define PCIE_INT_ENABLE_REG0x180
+#define PCIE_MSI_ENABLEGENMASK(PCIE_MSI_SET_NUM + 8 - 
1, 8)
+#define PCIE_MSI_SHIFT 8
 #define PCIE_INTX_SHIFT24
 #define PCIE_INTX_ENABLE \
GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
 
 #define PCIE_INT_STATUS_REG0x184
+#define PCIE_MSI_SET_ENABLE_REG0x190
+#define PCIE_MSI_SET_ENABLEGENMASK(PCIE_MSI_SET_NUM - 1, 0)
+
+#define PCIE_MSI_SET_BASE_REG  0xc00
+#define PCIE_MSI_SET_OFFSET0x10
+#define PCIE_MSI_SET_STATUS_OFFSET 0x04
+#define PCIE_MSI_SET_ENABLE_OFFSET 0x08
+
+#define PCIE_MSI_SET_ADDR_HI_BASE  0xc80
+#define PCIE_MSI_SET_ADDR_HI_OFFSET0x04
 
 #define PCIE_TRANS_TABLE_BASE_REG  0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
@@ -73,6 +91,16 @@
 #define PCIE_ATR_TLP_TYPE_MEM  PCIE_ATR_TLP_TYPE(0)
 #define PCIE_ATR_TLP_TYPE_IO   PCIE_ATR_TLP_TYPE(2)
 
+/**
+ * struct mtk_pcie_msi - MSI information for each set
+ * @base: IO mapped register base
+ * @msg_addr: MSI message address
+ */
+struct mtk_msi_set {
+   void __iomem *base;
+   phys_addr_t msg_addr;
+};
+
 /**
  * struct mtk_pcie_port - PCIe port information
  * @dev: pointer to PCIe device
@@ -86,6 +114,11 @@
  * @irq: PCIe controller interrupt number
  * @irq_lock: lock protecting IRQ register access
  * @intx_domain: legacy INTx IRQ domain
+ * @msi_domain: MSI IRQ domain
+ * @msi_bottom_domain: MSI IRQ bottom domain
+ * @msi_sets: MSI sets information
+ * @lock: lock protecting IRQ bit map
+ * @msi_irq_in_use: bit map for assigned MSI IRQ
  */
 struct mtk_pcie_port {
struct device *dev;
@@ -100,6 +133,11 @@ struct mtk_pcie_port {
int irq;
raw_spinlock_t irq_lock;
struct irq_domain *intx_domain;
+   struct irq_domain *msi_domain;
+   struct irq_domain *msi_bottom_domain;
+   struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
+   struct mutex lock;
+   DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
 };
 
 /**
@@ -197,6 +235,35 @@ static int mtk_pcie_set_trans_table(struct mtk_pcie_port 
*port,
return 0;
 }
 
+static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
+{
+   int i;
+   u32 val;
+
+   val = readl_relaxed(port->base + PCIE_MSI_SET_ENABLE_REG);
+   val |= PCIE_MSI_SET_ENABLE;
+   writel_relaxed(val, port->base + PCIE_MSI_SET_ENABLE_REG);
+
+   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+   val |= PCIE_MSI_ENABLE;
+   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+
+   for (i = 0; i < PCIE_MSI_SET_NUM; i++) {
+   struct mtk_msi_set *msi_set = &port->msi_sets[i];
+
+   msi_set->base = port->base + PCIE_MSI_SET_BASE_REG +
+   i * PCIE_MSI_SET_OFFSET;
+   msi_set->msg_addr = port->reg_base + PCIE_MSI_SET_BASE_REG +
+   i * PCIE_MSI_SET_OFFSET;
+
+  

[v8,4/7] PCI: mediatek-gen3: Add INTx support

[Jianjun Wang]

Add INTx support for MediaTek Gen3 PCIe controller.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 176 
 1 file changed, 176 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
index c602beb9afec..8b3b5f838b69 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -9,6 +9,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -45,6 +48,13 @@
 #define PCIE_LINK_STATUS_REG   0x154
 #define PCIE_PORT_LINKUP   BIT(8)
 
+#define PCIE_INT_ENABLE_REG0x180
+#define PCIE_INTX_SHIFT24
+#define PCIE_INTX_ENABLE \
+   GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
+
+#define PCIE_INT_STATUS_REG0x184
+
 #define PCIE_TRANS_TABLE_BASE_REG  0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
@@ -73,6 +83,9 @@
  * @phy: PHY controller block
  * @clks: PCIe clocks
  * @num_clks: PCIe clocks count for this port
+ * @irq: PCIe controller interrupt number
+ * @irq_lock: lock protecting IRQ register access
+ * @intx_domain: legacy INTx IRQ domain
  */
 struct mtk_pcie_port {
struct device *dev;
@@ -83,6 +96,10 @@ struct mtk_pcie_port {
struct phy *phy;
struct clk_bulk_data *clks;
int num_clks;
+
+   int irq;
+   raw_spinlock_t irq_lock;
+   struct irq_domain *intx_domain;
 };
 
 /**
@@ -199,6 +216,11 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port 
*port)
val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8);
writel_relaxed(val, port->base + PCIE_PCI_IDS_1);
 
+   /* Mask all INTx interrupts */
+   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+   val &= ~PCIE_INTX_ENABLE;
+   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+
/* Assert all reset signals */
val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
@@ -262,6 +284,154 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port 
*port)
return 0;
 }
 
+static int mtk_pcie_set_affinity(struct irq_data *data,
+const struct cpumask *mask, bool force)
+{
+   return -EINVAL;
+}
+
+static void mtk_intx_mask(struct irq_data *data)
+{
+   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+   unsigned long flags;
+   u32 val;
+
+   raw_spin_lock_irqsave(&port->irq_lock, flags);
+   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+   val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
+   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+   raw_spin_unlock_irqrestore(&port->irq_lock, flags);
+}
+
+static void mtk_intx_unmask(struct irq_data *data)
+{
+   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+   unsigned long flags;
+   u32 val;
+
+   raw_spin_lock_irqsave(&port->irq_lock, flags);
+   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+   val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
+   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+   raw_spin_unlock_irqrestore(&port->irq_lock, flags);
+}
+
+/**
+ * mtk_intx_eoi
+ * @data: pointer to chip specific data
+ *
+ * As an emulated level IRQ, its interrupt status will remain
+ * until the corresponding de-assert message is received; hence that
+ * the status can only be cleared when the interrupt has been serviced.
+ */
+static void mtk_intx_eoi(struct irq_data *data)
+{
+   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+   unsigned long hwirq;
+
+   hwirq = data->hwirq + PCIE_INTX_SHIFT;
+   writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG);
+}
+
+static struct irq_chip mtk_intx_irq_chip = {
+   .irq_enable = mtk_intx_unmask,
+   .irq_disable= mtk_intx_mask,
+   .irq_mask   = mtk_intx_mask,
+   .irq_unmask = mtk_intx_unmask,
+   .irq_eoi= mtk_intx_eoi,
+   .irq_set_affinity   = mtk_pcie_set_affinity,
+   .name   = "INTx",
+};
+
+static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
+irq_hw_number_t hwirq)
+{
+   irq_set_chip_data(irq, domain->host_data);
+   irq_set_chip_and_handler_name(irq, &mtk_intx_irq_chip,
+ handle_fasteoi_irq, "INTx");
+   return 0;
+}
+
+static const struct irq_domain_ops intx_domain_ops = {
+   .map = mtk_pcie_intx_map,
+};
+
+static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port)
+{
+   struct device *dev = port->de

[v8,1/7] dt-bindings: PCI: mediatek-gen3: Add YAML schema

[Jianjun Wang]

Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 .../bindings/pci/mediatek-pcie-gen3.yaml  | 181 ++
 1 file changed, 181 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
new file mode 100644
index ..e7b1f9892da4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -0,0 +1,181 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gen3 PCIe controller on MediaTek SoCs
+
+maintainers:
+  - Jianjun Wang 
+
+description: |+
+  PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
+  and compatible with Gen2, Gen1 speed.
+
+  This PCIe controller supports up to 256 MSI vectors, the MSI hardware
+  block diagram is as follows:
+
++-+
+| GIC |
++-+
+   ^
+   |
+   port->irq
+   |
+   +-+-+-+-+-+-+-+-+
+   |0|1|2|3|4|5|6|7| (PCIe intc)
+   +-+-+-+-+-+-+-+-+
+^ ^   ^
+| |...|
++---+ +--++---+
+|||
+  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
+  |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
+  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
+   ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
+   | |  |  || |  |  || |  |  |  (MSI vectors)
+   | |  |  || |  |  || |  |  |
+
+(MSI SET0)   (MSI SET1)  ...   (MSI SET7)
+
+  With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
+  each set has its own address for MSI message, and supports 32 MSI vectors
+  to generate interrupt.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+const: mediatek,mt8192-pcie
+
+  reg:
+maxItems: 1
+
+  reg-names:
+items:
+  - const: pcie-mac
+
+  interrupts:
+maxItems: 1
+
+  ranges:
+minItems: 1
+maxItems: 8
+
+  resets:
+minItems: 1
+maxItems: 2
+
+  reset-names:
+minItems: 1
+maxItems: 2
+items:
+  - const: phy
+  - const: mac
+
+  clocks:
+maxItems: 6
+
+  clock-names:
+items:
+  - const: pl_250m
+  - const: tl_26m
+  - const: tl_96m
+  - const: tl_32k
+  - const: peri_26m
+  - const: top_133m
+
+  assigned-clocks:
+maxItems: 1
+
+  assigned-clock-parents:
+maxItems: 1
+
+  phys:
+maxItems: 1
+
+  '#interrupt-cells':
+const: 1
+
+  interrupt-controller:
+description: Interrupt controller node for handling legacy PCI interrupts.
+type: object
+properties:
+  '#address-cells':
+const: 0
+  '#interrupt-cells':
+const: 1
+  interrupt-controller: true
+
+required:
+  - '#address-cells'
+  - '#interrupt-cells'
+  - interrupt-controller
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - ranges
+  - clocks
+  - '#interrupt-cells'
+  - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+pcie: pcie@1123 {
+compatible = "mediatek,mt8192-pcie";
+device_type = "pci";
+#address-cells = <3>;
+#size-cells = <2>;
+reg = <0x00 0x1123 0x00 0x4000>;
+reg-names = "pcie-mac";
+interrupts = ;
+bus-range = <0x00 0xff>;
+ranges = <0x8200 0x00 0x1200 0x00
+  0x1200 0x00 0x100>;
+clocks = <&infracfg 44>,
+ <&infracfg 40>,
+ <&infracfg 43>,
+ <&infracfg 97>,
+ <&infracfg 99>,
+ <&infracfg 111>;
+clock-names = "pl_250m", "tl_26m", "tl_96m",
+  "tl_32k", "peri_26m", "top_133m";
+assigned-clocks = <&topckgen 50>;
+assigned-clock-parents = <&topckgen 91>;
+
+phys = <&pciephy>;
+phy-names = "pcie-phy";
+
+resets = <&infracfg_rst 2>,
+  

[v8,2/7] PCI: Export pci_pio_to_address() for module use

[Jianjun Wang]

This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.

Signed-off-by: Jianjun Wang 
---
 drivers/pci/pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index b9fecc25d213..7ce72a82bec5 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4047,6 +4047,7 @@ phys_addr_t pci_pio_to_address(unsigned long pio)
 
return address;
 }
+EXPORT_SYMBOL(pci_pio_to_address);
 
 unsigned long __weak pci_address_to_pio(phys_addr_t address)
 {
-- 
2.25.1

[v8,6/7] PCI: mediatek-gen3: Add system PM support

[Jianjun Wang]

Add suspend_noirq and resume_noirq callback functions to implement
PM system suspend hooks for MediaTek Gen3 PCIe controller.

When system suspend, trigger the PCIe link to L2 state and pull down
the PERST# pin, gating the clocks of MAC layer and power off the
physical layer for the sake of power saving.

When system resum, the PCIe link should be re-established and the
related control register values should be restored.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 84 +
 1 file changed, 84 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
index fde9de591888..fd13540d37fe 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -45,6 +45,9 @@
 #define PCIE_PE_RSTB   BIT(3)
 
 #define PCIE_LTSSM_STATUS_REG  0x150
+#define PCIE_LTSSM_STATE_MASK  GENMASK(28, 24)
+#define PCIE_LTSSM_STATE(val)  ((val & PCIE_LTSSM_STATE_MASK) >> 24)
+#define PCIE_LTSSM_STATE_L2_IDLE   0x14
 
 #define PCIE_LINK_STATUS_REG   0x154
 #define PCIE_PORT_LINKUP   BIT(8)
@@ -73,6 +76,9 @@
 #define PCIE_MSI_SET_ADDR_HI_BASE  0xc80
 #define PCIE_MSI_SET_ADDR_HI_OFFSET0x04
 
+#define PCIE_ICMD_PM_REG   0x198
+#define PCIE_TURN_OFF_LINK BIT(4)
+
 #define PCIE_TRANS_TABLE_BASE_REG  0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
@@ -892,6 +898,83 @@ static int mtk_pcie_remove(struct platform_device *pdev)
return 0;
 }
 
+static int __maybe_unused mtk_pcie_turn_off_link(struct mtk_pcie_port *port)
+{
+   u32 val;
+
+   val = readl_relaxed(port->base + PCIE_ICMD_PM_REG);
+   val |= PCIE_TURN_OFF_LINK;
+   writel_relaxed(val, port->base + PCIE_ICMD_PM_REG);
+
+   /* Check the link is L2 */
+   return readl_poll_timeout(port->base + PCIE_LTSSM_STATUS_REG, val,
+ (PCIE_LTSSM_STATE(val) ==
+  PCIE_LTSSM_STATE_L2_IDLE), 20,
+  50 * USEC_PER_MSEC);
+}
+
+static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
+{
+   struct mtk_pcie_port *port = dev_get_drvdata(dev);
+   int err;
+   u32 val;
+
+   /* Trigger link to L2 state */
+   err = mtk_pcie_turn_off_link(port);
+   if (err) {
+   dev_err(port->dev, "can not enter L2 state\n");
+   return err;
+   }
+
+   /* Pull down the PERST# pin */
+   val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
+   val |= PCIE_PE_RSTB;
+   writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
+
+   dev_dbg(port->dev, "enter L2 state success");
+
+   clk_bulk_disable_unprepare(port->num_clks, port->clks);
+
+   reset_control_assert(port->mac_reset);
+
+   phy_power_off(port->phy);
+   reset_control_assert(port->phy_reset);
+
+   return 0;
+}
+
+static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
+{
+   struct mtk_pcie_port *port = dev_get_drvdata(dev);
+   int err;
+
+   reset_control_deassert(port->phy_reset);
+   phy_power_on(port->phy);
+
+   reset_control_deassert(port->mac_reset);
+
+   err = clk_bulk_prepare_enable(port->num_clks, port->clks);
+   if (err) {
+   dev_dbg(dev, "failed to enable PCIe clocks\n");
+   return err;
+   }
+
+   err = mtk_pcie_startup_port(port);
+   if (err) {
+   dev_err(port->dev, "resume failed\n");
+   return err;
+   }
+
+   dev_dbg(port->dev, "resume done\n");
+
+   return 0;
+}
+
+static const struct dev_pm_ops mtk_pcie_pm_ops = {
+   SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
+ mtk_pcie_resume_noirq)
+};
+
 static const struct of_device_id mtk_pcie_of_match[] = {
{ .compatible = "mediatek,mt8192-pcie" },
{},
@@ -903,6 +986,7 @@ static struct platform_driver mtk_pcie_driver = {
.driver = {
.name = "mtk-pcie",
.of_match_table = mtk_pcie_of_match,
+   .pm = &mtk_pcie_pm_ops,
},
 };
 
-- 
2.25.1

[v8,0/7] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.

Changes in v8:
1. Add irq_clock to protect IRQ register access;
2. Mask all INTx interrupt when startup port;
3. Remove activate/deactivate callbacks from bottom_domain_ops;
4. Add unmask/mask callbacks in mtk_msi_bottom_irq_chip;
5. Add property information for reg-names.

Changes in v7:
1. Split the driver patch to core PCIe, INTx, MSI and PM patches;
2. Reshape MSI init and handle flow, use msi_bottom_domain to cover all sets;
3. Replace readl/writel with their relaxed version;
4. Add MSI description in binding document;
5. Add pl_250m clock in binding document.

Changes in v6:
1. Export pci_pio_to_address() to support compiling as kernel module;
2. Replace usleep_range(100 * 1000, 120 * 1000) with msleep(100);
3. Replace dev_notice with dev_err;
4. Fix MSI get hwirq flow;
5. Fix warning for possible recursive locking in mtk_pcie_set_affinity.

Changes in v5:
1. Remove unused macros
2. Modify the config read/write callbacks, set the config byte field
   in TLP header and use pci_generic_config_read32/write32
   to access the config space
3. Fix the settings of translation window, both MEM and IO regions
   works properly
4. Fix typos

Changes in v4:
1. Fix PCIe power up/down flow
2. Use "mac" and "phy" for reset names
3. Add clock names
4. Fix the variables type

Changes in v3:
1. Remove standard property in binding document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs

Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown

Jianjun Wang (7):
  dt-bindings: PCI: mediatek-gen3: Add YAML schema
  PCI: Export pci_pio_to_address() for module use
  PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192
  PCI: mediatek-gen3: Add INTx support
  PCI: mediatek-gen3: Add MSI support
  PCI: mediatek-gen3: Add system PM support
  MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer

 .../bindings/pci/mediatek-pcie-gen3.yaml  | 181 
 MAINTAINERS   |   1 +
 drivers/pci/controller/Kconfig|  13 +
 drivers/pci/controller/Makefile   |   1 +
 drivers/pci/controller/pcie-mediatek-gen3.c   | 994 ++
 drivers/pci/pci.c |   1 +
 6 files changed, 1191 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

-- 
2.25.1

Re: [v7,5/7] PCI: mediatek-gen3: Add MSI support

[Jianjun Wang]

On Wed, 2021-01-27 at 13:05 +, Marc Zyngier wrote:
> On 2021-01-27 12:31, Jianjun Wang wrote:
> > On Tue, 2021-01-26 at 13:57 +, Marc Zyngier wrote:
> >> On 2021-01-13 11:39, Jianjun Wang wrote:
> >> > Add MSI support for MediaTek Gen3 PCIe controller.
> >> >
> >> > This PCIe controller supports up to 256 MSI vectors, the MSI hardware
> >> > block diagram is as follows:
> >> >
> >> >   +-+
> >> >   | GIC |
> >> >   +-+
> >> >  ^
> >> >  |
> >> >  port->irq
> >> >  |
> >> >  +-+-+-+-+-+-+-+-+
> >> >  |0|1|2|3|4|5|6|7| (PCIe intc)
> >> >  +-+-+-+-+-+-+-+-+
> >> >   ^ ^   ^
> >> >   | |...|
> >> >   +---+ +--++---+
> >> >   |||
> >> > +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
> >> > |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
> >> > +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
> >> >  ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
> >> >  | |  |  || |  |  || |  |  |  (MSI vectors)
> >> >  | |  |  || |  |  || |  |  |
> >> >
> >> >   (MSI SET0)   (MSI SET1)  ...   (MSI SET7)
> >> >
> >> > With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
> >> > each set has its own address for MSI message, and supports 32 MSI
> >> > vectors
> >> > to generate interrupt.
> >> >
> >> > Signed-off-by: Jianjun Wang 
> >> > Acked-by: Ryder Lee 
> >> > ---
> >> >  drivers/pci/controller/pcie-mediatek-gen3.c | 261 
> >> >  1 file changed, 261 insertions(+)
> >> >
> >> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
> >> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> >> > index 7979a2856c35..471d97cd1ef9 100644
> >> > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> >> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> >> > @@ -14,6 +14,7 @@
> >> >  #include 
> >> >  #include 
> >> >  #include 
> >> > +#include 
> >> >  #include 
> >> >  #include 
> >> >  #include 
> >> > @@ -52,11 +53,28 @@
> >> >  #define PCIE_LINK_STATUS_REG0x154
> >> >  #define PCIE_PORT_LINKUPBIT(8)
> >> >
> >> > +#define PCIE_MSI_SET_NUM8
> >> > +#define PCIE_MSI_IRQS_PER_SET   32
> >> > +#define PCIE_MSI_IRQS_NUM \
> >> > +(PCIE_MSI_IRQS_PER_SET * (PCIE_MSI_SET_NUM))
> >> 
> >> Spurious inner bracketing.
> >> 
> >> > +
> >> >  #define PCIE_INT_ENABLE_REG 0x180
> >> > +#define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 
> >> > 1, 8)
> >> > +#define PCIE_MSI_SHIFT  8
> >> >  #define PCIE_INTX_SHIFT 24
> >> >  #define PCIE_INTX_MASK  GENMASK(27, 24)
> >> >
> >> >  #define PCIE_INT_STATUS_REG 0x184
> >> > +#define PCIE_MSI_SET_ENABLE_REG 0x190
> >> > +#define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
> >> > +
> >> > +#define PCIE_MSI_SET_BASE_REG   0xc00
> >> > +#define PCIE_MSI_SET_OFFSET 0x10
> >> > +#define PCIE_MSI_SET_STATUS_OFFSET  0x04
> >> > +#define PCIE_MSI_SET_ENABLE_OFFSET  0x08
> >> > +
> >> > +#define PCIE_MSI_SET_ADDR_HI_BASE   0xc80
> >> > +#define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04
> >> >
> >> >  #define PCIE_TRANS_TABLE_BASE_REG   0x800
> >> >  #define PCIE_ATR_SRC_ADDR_MSB_OFFSET0x4
> >> > @@ -76,6 +94,18 @@
> >> >  #define PCIE_ATR_TLP_TYPE_MEM   PCIE_ATR_TLP_TYPE(0)
> >> >  #define PCIE_ATR_TLP_TYPE_IOPCIE_ATR_TLP_TYPE(2)
> >> >
> >> > +/**
> >> > + * struct mtk_pcie_msi - MSI information for each set
> >> > + * @dev: pointer to PCIe device
> >> > + * @base: IO mapped register base
> &

Re: [v7,4/7] PCI: mediatek-gen3: Add INTx support

[Jianjun Wang]

On Tue, 2021-01-26 at 12:25 +, Marc Zyngier wrote:
> On 2021-01-13 11:39, Jianjun Wang wrote:
> > Add INTx support for MediaTek Gen3 PCIe controller.
> > 
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> > ---
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 163 
> >  1 file changed, 163 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > index c00ea7c167de..7979a2856c35 100644
> > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -9,6 +9,9 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -49,6 +52,12 @@
> >  #define PCIE_LINK_STATUS_REG   0x154
> >  #define PCIE_PORT_LINKUP   BIT(8)
> > 
> > +#define PCIE_INT_ENABLE_REG0x180
> > +#define PCIE_INTX_SHIFT24
> > +#define PCIE_INTX_MASK GENMASK(27, 24)
> 
> I guess this '24' is actually PCIE_INTX_SHIFT? In this case,
> please write it as
> 
> GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
> 
> to make it clear that you are dealing with one bit per INTx.

Yes, I will fix it in the next version, thanks for your review.
> 
> > +
> > +#define PCIE_INT_STATUS_REG0x184
> > +
> >  #define PCIE_TRANS_TABLE_BASE_REG  0x800
> >  #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
> >  #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
> > @@ -77,6 +86,8 @@
> >   * @phy: PHY controller block
> >   * @clks: PCIe clocks
> >   * @num_clks: PCIe clocks count for this port
> > + * @irq: PCIe controller interrupt number
> > + * @intx_domain: legacy INTx IRQ domain
> >   */
> >  struct mtk_pcie_port {
> > struct device *dev;
> > @@ -87,6 +98,9 @@ struct mtk_pcie_port {
> > struct phy *phy;
> > struct clk_bulk_data *clks;
> > int num_clks;
> > +
> > +   int irq;
> > +   struct irq_domain *intx_domain;
> >  };
> > 
> >  /**
> > @@ -266,6 +280,149 @@ static int mtk_pcie_startup_port(struct
> > mtk_pcie_port *port)
> > return 0;
> >  }
> > 
> > +static int mtk_pcie_set_affinity(struct irq_data *data,
> > +const struct cpumask *mask, bool force)
> > +{
> > +   return -EINVAL;
> > +}
> > +
> > +static void mtk_intx_mask(struct irq_data *data)
> > +{
> > +   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
> > +   u32 val;
> > +
> > +   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
> > +   val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
> > +   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
> 
> This is missing some locking. Otherwise, two concurrent mask/unmask
> for different interrupts will corrupt each other's state.
> 
> > +}
> > +
> > +static void mtk_intx_unmask(struct irq_data *data)
> > +{
> > +   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
> > +   u32 val;
> > +
> > +   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
> > +   val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
> > +   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
> 
> Same thing here.
> 
> > +}
> > +
> > +/**
> > + * mtk_intx_eoi
> > + * @data: pointer to chip specific data
> > + *
> > + * As an emulated level IRQ, its interrupt status will remain
> > + * until the corresponding de-assert message is received; hence that
> > + * the status can only be cleared when the interrupt has been 
> > serviced.
> > + */
> > +static void mtk_intx_eoi(struct irq_data *data)
> > +{
> > +   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
> > +   unsigned long hwirq;
> > +
> > +   hwirq = data->hwirq + PCIE_INTX_SHIFT;
> > +   writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG);
> > +}
> > +
> > +static struct irq_chip mtk_intx_irq_chip = {
> > +   .irq_mask   = mtk_intx_mask,
> > +   .irq_unmask = mtk_intx_unmask,
> > +   .irq_eoi= mtk_intx_eoi,
> > +   .irq_set_affinity   = mtk_pcie_set_affinity,
> > +   .name   = "PCIe",
> 
> nit: "PCIe" is not really descriptive. &qu

Re: [v7,5/7] PCI: mediatek-gen3: Add MSI support

[Jianjun Wang]

On Tue, 2021-01-26 at 13:57 +, Marc Zyngier wrote:
> On 2021-01-13 11:39, Jianjun Wang wrote:
> > Add MSI support for MediaTek Gen3 PCIe controller.
> > 
> > This PCIe controller supports up to 256 MSI vectors, the MSI hardware
> > block diagram is as follows:
> > 
> >   +-+
> >   | GIC |
> >   +-+
> >  ^
> >  |
> >  port->irq
> >  |
> >  +-+-+-+-+-+-+-+-+
> >  |0|1|2|3|4|5|6|7| (PCIe intc)
> >  +-+-+-+-+-+-+-+-+
> >   ^ ^   ^
> >   | |...|
> >   +---+ +--++---+
> >   |||
> > +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
> > |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
> > +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
> >  ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
> >  | |  |  || |  |  || |  |  |  (MSI vectors)
> >  | |  |  || |  |  || |  |  |
> > 
> >   (MSI SET0)   (MSI SET1)  ...   (MSI SET7)
> > 
> > With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
> > each set has its own address for MSI message, and supports 32 MSI 
> > vectors
> > to generate interrupt.
> > 
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> > ---
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 261 
> >  1 file changed, 261 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > index 7979a2856c35..471d97cd1ef9 100644
> > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -14,6 +14,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -52,11 +53,28 @@
> >  #define PCIE_LINK_STATUS_REG   0x154
> >  #define PCIE_PORT_LINKUP   BIT(8)
> > 
> > +#define PCIE_MSI_SET_NUM   8
> > +#define PCIE_MSI_IRQS_PER_SET  32
> > +#define PCIE_MSI_IRQS_NUM \
> > +   (PCIE_MSI_IRQS_PER_SET * (PCIE_MSI_SET_NUM))
> 
> Spurious inner bracketing.
> 
> > +
> >  #define PCIE_INT_ENABLE_REG0x180
> > +#define PCIE_MSI_ENABLEGENMASK(PCIE_MSI_SET_NUM + 8 - 
> > 1, 8)
> > +#define PCIE_MSI_SHIFT 8
> >  #define PCIE_INTX_SHIFT24
> >  #define PCIE_INTX_MASK GENMASK(27, 24)
> > 
> >  #define PCIE_INT_STATUS_REG0x184
> > +#define PCIE_MSI_SET_ENABLE_REG0x190
> > +#define PCIE_MSI_SET_ENABLEGENMASK(PCIE_MSI_SET_NUM - 1, 0)
> > +
> > +#define PCIE_MSI_SET_BASE_REG  0xc00
> > +#define PCIE_MSI_SET_OFFSET0x10
> > +#define PCIE_MSI_SET_STATUS_OFFSET 0x04
> > +#define PCIE_MSI_SET_ENABLE_OFFSET 0x08
> > +
> > +#define PCIE_MSI_SET_ADDR_HI_BASE  0xc80
> > +#define PCIE_MSI_SET_ADDR_HI_OFFSET0x04
> > 
> >  #define PCIE_TRANS_TABLE_BASE_REG  0x800
> >  #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
> > @@ -76,6 +94,18 @@
> >  #define PCIE_ATR_TLP_TYPE_MEM  PCIE_ATR_TLP_TYPE(0)
> >  #define PCIE_ATR_TLP_TYPE_IO   PCIE_ATR_TLP_TYPE(2)
> > 
> > +/**
> > + * struct mtk_pcie_msi - MSI information for each set
> > + * @dev: pointer to PCIe device
> > + * @base: IO mapped register base
> > + * @msg_addr: MSI message address
> > + */
> > +struct mtk_msi_set {
> > +   struct device *dev;
> > +   void __iomem *base;
> > +   phys_addr_t msg_addr;
> > +};
> > +
> >  /**
> >   * struct mtk_pcie_port - PCIe port information
> >   * @dev: pointer to PCIe device
> > @@ -88,6 +118,11 @@
> >   * @num_clks: PCIe clocks count for this port
> >   * @irq: PCIe controller interrupt number
> >   * @intx_domain: legacy INTx IRQ domain
> > + * @msi_domain: MSI IRQ domain
> > + * @msi_bottom_domain: MSI IRQ bottom domain
> > + * @msi_sets: MSI sets information
> > + * @lock: lock protecting IRQ bit map
> > + * @msi_irq_in_use: bit map for assigned MSI IRQ
> >   */
> >  struct mtk_pcie_port {
> > struct device *dev;
> > @@ -101,6 +136,11 @@ struct mtk_pcie_port {
> > 
> >

Re: [v7,1/7] dt-bindings: PCI: mediatek-gen3: Add YAML schema

[Jianjun Wang]

On Mon, 2021-01-25 at 14:22 -0600, Rob Herring wrote:
> On Wed, Jan 13, 2021 at 07:39:55PM +0800, Jianjun Wang wrote:
> > Add YAML schemas documentation for Gen3 PCIe controller on
> > MediaTek SoCs.
> > 
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> > ---
> >  .../bindings/pci/mediatek-pcie-gen3.yaml  | 172 ++
> >  1 file changed, 172 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
> > b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > new file mode 100644
> > index ..f133fb0184f1
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > @@ -0,0 +1,172 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Gen3 PCIe controller on MediaTek SoCs
> > +
> > +maintainers:
> > +  - Jianjun Wang 
> > +
> > +description: |+
> > +  PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
> > +  and compatible with Gen2, Gen1 speed.
> > +
> > +  This PCIe controller supports up to 256 MSI vectors, the MSI hardware
> > +  block diagram is as follows:
> > +
> > ++-+
> > +| GIC |
> > ++-+
> > +   ^
> > +   |
> > +   port->irq
> > +   |
> > +   +-+-+-+-+-+-+-+-+
> > +   |0|1|2|3|4|5|6|7| (PCIe intc)
> > +   +-+-+-+-+-+-+-+-+
> > +^ ^   ^
> > +| |...|
> > ++---+ +--++---+
> > +|||
> > +  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
> > +  |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
> > +  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
> > +   ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
> > +   | |  |  || |  |  || |  |  |  (MSI vectors)
> > +   | |  |  || |  |  || |  |  |
> > +
> > +(MSI SET0)   (MSI SET1)  ...   (MSI SET7)
> > +
> > +  With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
> > +  each set has its own address for MSI message, and supports 32 MSI vectors
> > +  to generate interrupt.
> > +
> > +allOf:
> > +  - $ref: /schemas/pci/pci-bus.yaml#
> > +
> > +properties:
> > +  compatible:
> > +const: mediatek,mt8192-pcie
> > +
> > +  reg:
> > +maxItems: 1
> > +
> > +  interrupts:
> > +maxItems: 1
> > +
> > +  ranges:
> > +minItems: 1
> > +maxItems: 8
> > +
> > +  resets:
> > +minItems: 1
> > +maxItems: 2
> 
> Why the range? The SoC either has the reset lines or it doesn't.
> 
> > +
> > +  reset-names:
> > +anyOf:
> > +  - const: mac
> > +  - const: phy
> 
> I don't think this should stay, but if so, better expressed like this:
> 
> minItems: 1
> maxItems: 2
> items:
>   enum: [ mac, phy ]

Hi Rob,

Thanks for your review, does this means that I should merge the resets
and reset-names together as the following property?

resets:
  minItems: 1
  maxItems: 2
  items:
enum: [ mac, phy ]
> 
> 
> > +
> > +  clocks:
> > +maxItems: 6
> > +
> > +  clock-names:
> > +items:
> > +  - const: pl_250m
> > +  - const: tl_26m
> > +  - const: tl_96m
> > +  - const: tl_32k
> > +  - const: peri_26m
> > +  - const: top_133m
> > +
> > +  assigned-clocks:
> > +maxItems: 1
> > +
> > +  assigned-clock-parents:
> > +maxItems: 1
> > +
> > +  phys:
> > +maxItems: 1
> > +
> > +  '#interrupt-cells':
> > +const: 1
> > +
> > +  interrupt-controller:
> > +description: Interrupt controller node for handling legacy PCI 
> > interrupts.
> > +type: object
> > +properties:
> > +  '#address-cells':
> > +const: 0
> > +  '#interrupt-cells':
> > +const: 1
> > +  interrupt-controller: true
> > +
> 

Re: [v7,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

On Mon, 2021-01-25 at 13:54 -0600, Rob Herring wrote:
> On Wed, Jan 13, 2021 at 07:39:57PM +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supports Gen3 speed and
> > compatible with Gen2, Gen1 speed.
> > 
> > Add support for new Gen3 controller which can be found on MT8192.
> > 
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> > ---
> >  drivers/pci/controller/Kconfig  |  13 +
> >  drivers/pci/controller/Makefile |   1 +
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 463 
> >  3 files changed, 477 insertions(+)
> >  create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c
> > 
> > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > index 64e2f5e379aa..b242b17025b3 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -242,6 +242,19 @@ config PCIE_MEDIATEK
> >   Say Y here if you want to enable PCIe controller support on
> >   MediaTek SoCs.
> >  
> > +config PCIE_MEDIATEK_GEN3
> > +   tristate "MediaTek Gen3 PCIe controller"
> > +   depends on ARCH_MEDIATEK || COMPILE_TEST
> > +   depends on PCI_MSI_IRQ_DOMAIN
> > +   help
> > + Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> > + This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed,
> > + and support up to 256 MSI interrupt numbers for
> > + multi-function devices.
> > +
> > + Say Y here if you want to enable Gen3 PCIe controller support on
> > + MediaTek SoCs.
> > +
> >  config PCIE_TANGO_SMP8759
> > bool "Tango SMP8759 PCIe controller (DANGEROUS)"
> > depends on ARCH_TANGO && PCI_MSI && OF
> > diff --git a/drivers/pci/controller/Makefile 
> > b/drivers/pci/controller/Makefile
> > index 04c6edc285c5..df5d77d72a9d 100644
> > --- a/drivers/pci/controller/Makefile
> > +++ b/drivers/pci/controller/Makefile
> > @@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
> >  obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
> >  obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
> >  obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > +obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
> >  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> >  obj-$(CONFIG_VMD) += vmd.o
> >  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > new file mode 100644
> > index ..c00ea7c167de
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -0,0 +1,463 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * MediaTek PCIe host controller driver.
> > + *
> > + * Copyright (c) 2020 MediaTek Inc.
> > + * Author: Jianjun Wang 
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> 
> I don't think these 4 are needed.

Yes, I will drop these in the next version.
> 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "../pci.h"
> > +
> > +#define PCIE_SETTING_REG   0x80
> > +#define PCIE_PCI_IDS_1 0x9c
> > +#define PCI_CLASS(class)   (class << 8)
> > +#define PCIE_RC_MODE   BIT(0)
> > +
> > +#define PCIE_CFGNUM_REG0x140
> > +#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
> > +#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
> > +#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
> > 16))
> > +#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
> > +#define PCIE_CFG_OFFSET_ADDR   0x1000
> > +#define PCIE_CFG_HEADER(bus, devfn) \
> > +   (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
> > +
> > +#define PCIE_RST_CTRL_REG  0x148
> > +#define PCIE_MAC_RSTB  BIT(0)
> > +#define PCIE_PHY_RSTB  BIT(1)
> > +#define PCIE_BRG_RSTB  BIT(2)
> > +#define PCIE_PE_RSTB   BIT(3)
> > +
> > +#define PCIE_LTSSM_STATUS_RE

[v7,0/7] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.

Changes in v7:
1. Split the driver patch to core PCIe, INTx, MSI and PM patches;
2. Reshape MSI init and handle flow, use msi_bottom_domain to cover all sets;
3. Replace readl/writel with their relaxed version;
4. Add MSI description in binding document;
5. Add pl_250m clock in binding document.

Changes in v6:
1. Export pci_pio_to_address() to support compiling as kernel module;
2. Replace usleep_range(100 * 1000, 120 * 1000) with msleep(100);
3. Replace dev_notice with dev_err;
4. Fix MSI get hwirq flow;
5. Fix warning for possible recursive locking in mtk_pcie_set_affinity.

Changes in v5:
1. Remove unused macros
2. Modify the config read/write callbacks, set the config byte field
   in TLP header and use pci_generic_config_read32/write32
   to access the config space
3. Fix the settings of translation window, both MEM and IO regions
   works properly
4. Fix typos

Changes in v4:
1. Fix PCIe power up/down flow
2. Use "mac" and "phy" for reset names
3. Add clock names
4. Fix the variables type

Changes in v3:
1. Remove standard property in binding document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs

Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown


Jianjun Wang (7):
  dt-bindings: PCI: mediatek-gen3: Add YAML schema
  PCI: Export pci_pio_to_address() for module use
  PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192
  PCI: mediatek-gen3: Add INTx support
  PCI: mediatek-gen3: Add MSI support
  PCI: mediatek-gen3: Add system PM support
  MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer

 .../bindings/pci/mediatek-pcie-gen3.yaml  | 172 
 MAINTAINERS   |   1 +
 drivers/pci/controller/Kconfig|  13 +
 drivers/pci/controller/Makefile   |   1 +
 drivers/pci/controller/pcie-mediatek-gen3.c   | 965 ++
 drivers/pci/pci.c |   1 +
 6 files changed, 1153 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

-- 
2.25.1

[v7,5/7] PCI: mediatek-gen3: Add MSI support

[Jianjun Wang]

Add MSI support for MediaTek Gen3 PCIe controller.

This PCIe controller supports up to 256 MSI vectors, the MSI hardware
block diagram is as follows:

  +-+
  | GIC |
  +-+
 ^
 |
 port->irq
 |
 +-+-+-+-+-+-+-+-+
 |0|1|2|3|4|5|6|7| (PCIe intc)
 +-+-+-+-+-+-+-+-+
  ^ ^   ^
  | |...|
  +---+ +--++---+
  |||
+-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
|0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
+-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
 ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
 | |  |  || |  |  || |  |  |  (MSI vectors)
 | |  |  || |  |  || |  |  |

  (MSI SET0)   (MSI SET1)  ...   (MSI SET7)

With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
each set has its own address for MSI message, and supports 32 MSI vectors
to generate interrupt.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 261 
 1 file changed, 261 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
index 7979a2856c35..471d97cd1ef9 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -52,11 +53,28 @@
 #define PCIE_LINK_STATUS_REG   0x154
 #define PCIE_PORT_LINKUP   BIT(8)
 
+#define PCIE_MSI_SET_NUM   8
+#define PCIE_MSI_IRQS_PER_SET  32
+#define PCIE_MSI_IRQS_NUM \
+   (PCIE_MSI_IRQS_PER_SET * (PCIE_MSI_SET_NUM))
+
 #define PCIE_INT_ENABLE_REG0x180
+#define PCIE_MSI_ENABLEGENMASK(PCIE_MSI_SET_NUM + 8 - 
1, 8)
+#define PCIE_MSI_SHIFT 8
 #define PCIE_INTX_SHIFT24
 #define PCIE_INTX_MASK GENMASK(27, 24)
 
 #define PCIE_INT_STATUS_REG0x184
+#define PCIE_MSI_SET_ENABLE_REG0x190
+#define PCIE_MSI_SET_ENABLEGENMASK(PCIE_MSI_SET_NUM - 1, 0)
+
+#define PCIE_MSI_SET_BASE_REG  0xc00
+#define PCIE_MSI_SET_OFFSET0x10
+#define PCIE_MSI_SET_STATUS_OFFSET 0x04
+#define PCIE_MSI_SET_ENABLE_OFFSET 0x08
+
+#define PCIE_MSI_SET_ADDR_HI_BASE  0xc80
+#define PCIE_MSI_SET_ADDR_HI_OFFSET0x04
 
 #define PCIE_TRANS_TABLE_BASE_REG  0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
@@ -76,6 +94,18 @@
 #define PCIE_ATR_TLP_TYPE_MEM  PCIE_ATR_TLP_TYPE(0)
 #define PCIE_ATR_TLP_TYPE_IO   PCIE_ATR_TLP_TYPE(2)
 
+/**
+ * struct mtk_pcie_msi - MSI information for each set
+ * @dev: pointer to PCIe device
+ * @base: IO mapped register base
+ * @msg_addr: MSI message address
+ */
+struct mtk_msi_set {
+   struct device *dev;
+   void __iomem *base;
+   phys_addr_t msg_addr;
+};
+
 /**
  * struct mtk_pcie_port - PCIe port information
  * @dev: pointer to PCIe device
@@ -88,6 +118,11 @@
  * @num_clks: PCIe clocks count for this port
  * @irq: PCIe controller interrupt number
  * @intx_domain: legacy INTx IRQ domain
+ * @msi_domain: MSI IRQ domain
+ * @msi_bottom_domain: MSI IRQ bottom domain
+ * @msi_sets: MSI sets information
+ * @lock: lock protecting IRQ bit map
+ * @msi_irq_in_use: bit map for assigned MSI IRQ
  */
 struct mtk_pcie_port {
struct device *dev;
@@ -101,6 +136,11 @@ struct mtk_pcie_port {
 
int irq;
struct irq_domain *intx_domain;
+   struct irq_domain *msi_domain;
+   struct irq_domain *msi_bottom_domain;
+   struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
+   struct mutex lock;
+   DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
 };
 
 /**
@@ -243,6 +283,15 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port 
*port)
return err;
}
 
+   /* Enable MSI */
+   val = readl_relaxed(port->base + PCIE_MSI_SET_ENABLE_REG);
+   val |= PCIE_MSI_SET_ENABLE;
+   writel_relaxed(val, port->base + PCIE_MSI_SET_ENABLE_REG);
+
+   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+   val |= PCIE_MSI_ENABLE;
+   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+
/* Set PCIe translation windows */
resource_list_for_each_entry(entry, &host->windows) {
struct resource *res = entry->res;
@@ -286,6 +335,129 @@ static int mtk_pcie_set_affinity(struct irq_data *data,
return -EINVAL;
 }
 
+static struct irq_chip mtk_msi_irq_chip = {
+   .name = "MSI",
+   .irq_ack = irq_chip_ack_parent,
+};
+
+static struct msi_domain_info mtk_msi_domain_info = {
+   .flags  = (MSI_FLAG_

[v7,7/7] MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer

[Jianjun Wang]

Update entry for MediaTek PCIe controller, add Jianjun Wang
as MediaTek PCI co-maintainer.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index e73636b75f29..1a033812c7f9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13622,6 +13622,7 @@ F:  drivers/pci/controller/dwc/pcie-histb.c
 
 PCIE DRIVER FOR MEDIATEK
 M: Ryder Lee 
+M: Jianjun Wang 
 L: linux-...@vger.kernel.org
 L: linux-media...@lists.infradead.org
 S: Supported
-- 
2.25.1

[v7,6/7] PCI: mediatek-gen3: Add system PM support

[Jianjun Wang]

Add suspend_noirq and resume_noirq callback functions to implement
PM system suspend hooks for MediaTek Gen3 PCIe controller.

When system suspend, trigger the PCIe link to L2 state and pull down
the PERST# pin, gating the clocks of MAC layer and power off the
physical layer for the sake of power saving.

When system resum, the PCIe link should be re-established and the
related control register values should be restored.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 78 +
 1 file changed, 78 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
index 152820f28da1..ac6c43cea575 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -49,6 +49,9 @@
 #define PCIE_PE_RSTB   BIT(3)
 
 #define PCIE_LTSSM_STATUS_REG  0x150
+#define PCIE_LTSSM_STATE_MASK  GENMASK(28, 24)
+#define PCIE_LTSSM_STATE(val)  ((val & PCIE_LTSSM_STATE_MASK) >> 24)
+#define PCIE_LTSSM_STATE_L2_IDLE   0x14
 
 #define PCIE_LINK_STATUS_REG   0x154
 #define PCIE_PORT_LINKUP   BIT(8)
@@ -76,6 +79,9 @@
 #define PCIE_MSI_SET_ADDR_HI_BASE  0xc80
 #define PCIE_MSI_SET_ADDR_HI_OFFSET0x04
 
+#define PCIE_ICMD_PM_REG   0x198
+#define PCIE_TURN_OFF_LINK BIT(4)
+
 #define PCIE_TRANS_TABLE_BASE_REG  0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
@@ -869,6 +875,77 @@ static int mtk_pcie_remove(struct platform_device *pdev)
return 0;
 }
 
+static int __maybe_unused mtk_pcie_turn_off_link(struct mtk_pcie_port *port)
+{
+   u32 val;
+
+   val = readl_relaxed(port->base + PCIE_ICMD_PM_REG);
+   val |= PCIE_TURN_OFF_LINK;
+   writel_relaxed(val, port->base + PCIE_ICMD_PM_REG);
+
+   /* Check the link is L2 */
+   return readl_poll_timeout(port->base + PCIE_LTSSM_STATUS_REG, val,
+ (PCIE_LTSSM_STATE(val) ==
+  PCIE_LTSSM_STATE_L2_IDLE), 20,
+  50 * USEC_PER_MSEC);
+}
+
+static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
+{
+   struct mtk_pcie_port *port = dev_get_drvdata(dev);
+   int err;
+   u32 val;
+
+   /* Trigger link to L2 state */
+   err = mtk_pcie_turn_off_link(port);
+   if (err) {
+   dev_err(port->dev, "can not enter L2 state\n");
+   return err;
+   }
+
+   /* Pull down the PERST# pin */
+   val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
+   val |= PCIE_PE_RSTB;
+   writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
+
+   dev_dbg(port->dev, "enter L2 state success");
+
+   clk_bulk_disable_unprepare(port->num_clks, port->clks);
+
+   phy_power_off(port->phy);
+
+   return 0;
+}
+
+static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
+{
+   struct mtk_pcie_port *port = dev_get_drvdata(dev);
+   int err;
+
+   phy_power_on(port->phy);
+
+   err = clk_bulk_prepare_enable(port->num_clks, port->clks);
+   if (err) {
+   dev_dbg(dev, "failed to enable PCIe clocks\n");
+   return err;
+   }
+
+   err = mtk_pcie_startup_port(port);
+   if (err) {
+   dev_err(port->dev, "resume failed\n");
+   return err;
+   }
+
+   dev_dbg(port->dev, "resume done\n");
+
+   return 0;
+}
+
+static const struct dev_pm_ops mtk_pcie_pm_ops = {
+   SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
+ mtk_pcie_resume_noirq)
+};
+
 static const struct of_device_id mtk_pcie_of_match[] = {
{ .compatible = "mediatek,mt8192-pcie" },
{},
@@ -880,6 +957,7 @@ static struct platform_driver mtk_pcie_driver = {
.driver = {
.name = "mtk-pcie",
.of_match_table = mtk_pcie_of_match,
+   .pm = &mtk_pcie_pm_ops,
},
 };
 
-- 
2.25.1

[v7,4/7] PCI: mediatek-gen3: Add INTx support

[Jianjun Wang]

Add INTx support for MediaTek Gen3 PCIe controller.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 163 
 1 file changed, 163 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
index c00ea7c167de..7979a2856c35 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -9,6 +9,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -49,6 +52,12 @@
 #define PCIE_LINK_STATUS_REG   0x154
 #define PCIE_PORT_LINKUP   BIT(8)
 
+#define PCIE_INT_ENABLE_REG0x180
+#define PCIE_INTX_SHIFT24
+#define PCIE_INTX_MASK GENMASK(27, 24)
+
+#define PCIE_INT_STATUS_REG0x184
+
 #define PCIE_TRANS_TABLE_BASE_REG  0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
@@ -77,6 +86,8 @@
  * @phy: PHY controller block
  * @clks: PCIe clocks
  * @num_clks: PCIe clocks count for this port
+ * @irq: PCIe controller interrupt number
+ * @intx_domain: legacy INTx IRQ domain
  */
 struct mtk_pcie_port {
struct device *dev;
@@ -87,6 +98,9 @@ struct mtk_pcie_port {
struct phy *phy;
struct clk_bulk_data *clks;
int num_clks;
+
+   int irq;
+   struct irq_domain *intx_domain;
 };
 
 /**
@@ -266,6 +280,149 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port 
*port)
return 0;
 }
 
+static int mtk_pcie_set_affinity(struct irq_data *data,
+const struct cpumask *mask, bool force)
+{
+   return -EINVAL;
+}
+
+static void mtk_intx_mask(struct irq_data *data)
+{
+   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+   u32 val;
+
+   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+   val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT);
+   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+}
+
+static void mtk_intx_unmask(struct irq_data *data)
+{
+   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+   u32 val;
+
+   val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG);
+   val |= BIT(data->hwirq + PCIE_INTX_SHIFT);
+   writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
+}
+
+/**
+ * mtk_intx_eoi
+ * @data: pointer to chip specific data
+ *
+ * As an emulated level IRQ, its interrupt status will remain
+ * until the corresponding de-assert message is received; hence that
+ * the status can only be cleared when the interrupt has been serviced.
+ */
+static void mtk_intx_eoi(struct irq_data *data)
+{
+   struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
+   unsigned long hwirq;
+
+   hwirq = data->hwirq + PCIE_INTX_SHIFT;
+   writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG);
+}
+
+static struct irq_chip mtk_intx_irq_chip = {
+   .irq_mask   = mtk_intx_mask,
+   .irq_unmask = mtk_intx_unmask,
+   .irq_eoi= mtk_intx_eoi,
+   .irq_set_affinity   = mtk_pcie_set_affinity,
+   .name   = "PCIe",
+};
+
+static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
+irq_hw_number_t hwirq)
+{
+   irq_set_chip_and_handler_name(irq, &mtk_intx_irq_chip,
+ handle_fasteoi_irq, "INTx");
+   irq_set_chip_data(irq, domain->host_data);
+
+   return 0;
+}
+
+static const struct irq_domain_ops intx_domain_ops = {
+   .map = mtk_pcie_intx_map,
+};
+
+static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port,
+struct device_node *node)
+{
+   struct device *dev = port->dev;
+   struct device_node *intc_node;
+
+   /* Setup INTx */
+   intc_node = of_get_child_by_name(node, "interrupt-controller");
+   if (!intc_node) {
+   dev_err(dev, "missing PCIe Intc node\n");
+   return -ENODEV;
+   }
+
+   port->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX,
+ &intx_domain_ops, port);
+   if (!port->intx_domain) {
+   dev_err(dev, "failed to get INTx IRQ domain\n");
+   return -ENODEV;
+   }
+
+   return 0;
+}
+
+static void mtk_pcie_irq_teardown(struct mtk_pcie_port *port)
+{
+   irq_set_chained_handler_and_data(port->irq, NULL, NULL);
+
+   if (port->intx_domain)
+   irq_domain_remove(port->intx_domain);
+
+   irq_dispose_mapping(port->irq);
+}
+
+static void mtk_pcie_irq_handler(struct irq_desc *desc)
+{
+   struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
+   struct irq_chip *irqchip = irq

[v7,2/7] PCI: Export pci_pio_to_address() for module use

[Jianjun Wang]

This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.

Signed-off-by: Jianjun Wang 
---
 drivers/pci/pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 6d4d5a2f923d..3de714db2557 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4016,6 +4016,7 @@ phys_addr_t pci_pio_to_address(unsigned long pio)
 
return address;
 }
+EXPORT_SYMBOL(pci_pio_to_address);
 
 unsigned long __weak pci_address_to_pio(phys_addr_t address)
 {
-- 
2.25.1

[v7,1/7] dt-bindings: PCI: mediatek-gen3: Add YAML schema

[Jianjun Wang]

Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 .../bindings/pci/mediatek-pcie-gen3.yaml  | 172 ++
 1 file changed, 172 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
new file mode 100644
index ..f133fb0184f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -0,0 +1,172 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gen3 PCIe controller on MediaTek SoCs
+
+maintainers:
+  - Jianjun Wang 
+
+description: |+
+  PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
+  and compatible with Gen2, Gen1 speed.
+
+  This PCIe controller supports up to 256 MSI vectors, the MSI hardware
+  block diagram is as follows:
+
++-+
+| GIC |
++-+
+   ^
+   |
+   port->irq
+   |
+   +-+-+-+-+-+-+-+-+
+   |0|1|2|3|4|5|6|7| (PCIe intc)
+   +-+-+-+-+-+-+-+-+
+^ ^   ^
+| |...|
++---+ +--++---+
+|||
+  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
+  |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
+  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
+   ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
+   | |  |  || |  |  || |  |  |  (MSI vectors)
+   | |  |  || |  |  || |  |  |
+
+(MSI SET0)   (MSI SET1)  ...   (MSI SET7)
+
+  With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
+  each set has its own address for MSI message, and supports 32 MSI vectors
+  to generate interrupt.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+const: mediatek,mt8192-pcie
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  ranges:
+minItems: 1
+maxItems: 8
+
+  resets:
+minItems: 1
+maxItems: 2
+
+  reset-names:
+anyOf:
+  - const: mac
+  - const: phy
+
+  clocks:
+maxItems: 6
+
+  clock-names:
+items:
+  - const: pl_250m
+  - const: tl_26m
+  - const: tl_96m
+  - const: tl_32k
+  - const: peri_26m
+  - const: top_133m
+
+  assigned-clocks:
+maxItems: 1
+
+  assigned-clock-parents:
+maxItems: 1
+
+  phys:
+maxItems: 1
+
+  '#interrupt-cells':
+const: 1
+
+  interrupt-controller:
+description: Interrupt controller node for handling legacy PCI interrupts.
+type: object
+properties:
+  '#address-cells':
+const: 0
+  '#interrupt-cells':
+const: 1
+  interrupt-controller: true
+
+required:
+  - '#address-cells'
+  - '#interrupt-cells'
+  - interrupt-controller
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - ranges
+  - clocks
+  - '#interrupt-cells'
+  - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+pcie: pcie@1123 {
+compatible = "mediatek,mt8192-pcie";
+device_type = "pci";
+#address-cells = <3>;
+#size-cells = <2>;
+reg = <0x00 0x1123 0x00 0x4000>;
+reg-names = "pcie-mac";
+interrupts = ;
+bus-range = <0x00 0xff>;
+ranges = <0x8200 0x00 0x1200 0x00
+  0x1200 0x00 0x100>;
+clocks = <&infracfg 44>,
+ <&infracfg 40>,
+ <&infracfg 43>,
+ <&infracfg 97>,
+ <&infracfg 99>,
+ <&infracfg 111>;
+clock-names = "pl_250m", "tl_26m", "tl_96m",
+  "tl_32k", "peri_26m", "top_133m";
+assigned-clocks = <&topckgen 50>;
+assigned-clock-parents = <&topckgen 91>;
+
+phys = <&pciephy>;
+phy-names = "pcie-phy";
+resets = <&infracfg_rst 0>;
+reset-names = "phy";
+
+#interrupt-cells = <1>;
+interrupt-map-

[v7,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
compatible with Gen2, Gen1 speed.

Add support for new Gen3 controller which can be found on MT8192.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/Kconfig  |  13 +
 drivers/pci/controller/Makefile |   1 +
 drivers/pci/controller/pcie-mediatek-gen3.c | 463 
 3 files changed, 477 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 64e2f5e379aa..b242b17025b3 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -242,6 +242,19 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable PCIe controller support on
  MediaTek SoCs.
 
+config PCIE_MEDIATEK_GEN3
+   tristate "MediaTek Gen3 PCIe controller"
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   depends on PCI_MSI_IRQ_DOMAIN
+   help
+ Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
+ This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed,
+ and support up to 256 MSI interrupt numbers for
+ multi-function devices.
+
+ Say Y here if you want to enable Gen3 PCIe controller support on
+ MediaTek SoCs.
+
 config PCIE_TANGO_SMP8759
bool "Tango SMP8759 PCIe controller (DANGEROUS)"
depends on ARCH_TANGO && PCI_MSI && OF
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 04c6edc285c5..df5d77d72a9d 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
 obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
new file mode 100644
index ..c00ea7c167de
--- /dev/null
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -0,0 +1,463 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Jianjun Wang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pci.h"
+
+#define PCIE_SETTING_REG   0x80
+#define PCIE_PCI_IDS_1 0x9c
+#define PCI_CLASS(class)   (class << 8)
+#define PCIE_RC_MODE   BIT(0)
+
+#define PCIE_CFGNUM_REG0x140
+#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
+#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
+#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
16))
+#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
+#define PCIE_CFG_OFFSET_ADDR   0x1000
+#define PCIE_CFG_HEADER(bus, devfn) \
+   (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
+
+#define PCIE_RST_CTRL_REG  0x148
+#define PCIE_MAC_RSTB  BIT(0)
+#define PCIE_PHY_RSTB  BIT(1)
+#define PCIE_BRG_RSTB  BIT(2)
+#define PCIE_PE_RSTB   BIT(3)
+
+#define PCIE_LTSSM_STATUS_REG  0x150
+
+#define PCIE_LINK_STATUS_REG   0x154
+#define PCIE_PORT_LINKUP   BIT(8)
+
+#define PCIE_TRANS_TABLE_BASE_REG  0x800
+#define PCIE_ATR_SRC_ADDR_MSB_OFFSET   0x4
+#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET  0x8
+#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET  0xc
+#define PCIE_ATR_TRSL_PARAM_OFFSET 0x10
+#define PCIE_ATR_TLB_SET_OFFSET0x20
+
+#define PCIE_MAX_TRANS_TABLES  8
+#define PCIE_ATR_ENBIT(0)
+#define PCIE_ATR_SIZE(size) \
+   (size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
+#define PCIE_ATR_ID(id)((id) & GENMASK(3, 0))
+#define PCIE_ATR_TYPE_MEM  PCIE_ATR_ID(0)
+#define PCIE_ATR_TYPE_IO   PCIE_ATR_ID(1)
+#define PCIE_ATR_TLP_TYPE(type)(((type) << 16) & GENMASK(18, 
16))
+#define PCIE_ATR_TLP_TYPE_MEM  PCIE_ATR_TLP_TYPE(0)
+#define PCIE_ATR_TLP_TYPE_IO   PCIE_ATR_TLP_TYPE(2)
+
+/**
+ * struct mtk_pcie_port - PCIe port information
+ * @dev: pointer to PCIe device
+ * @base: IO mapped register base
+ * @reg_base: Physical register base
+ * @mac_reset: mac reset control
+ * @phy_reset: phy reset control
+ * @phy: PHY controller block
+ * @clk

Re: [v6,3/4] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

On Mon, 2020-12-28 at 15:12 +, Marc Zyngier wrote:
> On Mon, 28 Dec 2020 12:01:57 +,
> Jianjun Wang  wrote:
> > 
> > On Fri, 2020-12-25 at 19:22 +, Marc Zyngier wrote:
> 
> Dropped   , as it
> bounces:
> 
> : host
> mailgw01.mediatek.com[216.200.240.184] said: 550 Relaying mail to
> project_global_chrome_upstream_gr...@mediatek.com is not allowed (in reply
> to RCPT TO command)
> 
> Please make sure you don't Cc email addresses that cannot accept email
> form the outside world.

Apology, they are team members of mt8192 project, who want to know the
status of this patch. I will replace with the specified email address at
next time, instead of this group address.

> [...]
> 
> > > > +/**
> > > > + * struct mtk_pcie_msi - MSI information for each set
> > > > + * @base: IO mapped register base
> > > > + * @irq: MSI set Interrupt number
> > > > + * @index: MSI set number
> > > > + * @msg_addr: MSI message address
> > > > + * @domain: IRQ domain
> > > > + */
> > > > +struct mtk_pcie_msi {
> > > > +   void __iomem *base;
> > > > +   unsigned int irq;
> > > > +   int index;
> > > > +   phys_addr_t msg_addr;
> > > > +   struct irq_domain *domain;
> > > > +};
> > > 
> > > This looks odd. You seem to say that this covers a set if MSIs, and
> > > yet the irq field here clearly isn't part of a set. Is that per MSI
> > > instead? Either way, something is not quite as it should be.
> > > 
> > 
> > Appreciate all these comments, please allow me to explain the MSI
> > interrupt design in this HW.
> > 
> > The HW design of MSI interrupts will be like the following:
> > 
> >   +-+
> >   | GIC |
> >   +-+
> >  ^
> >  |
> >  |[port->irq]
> >  |
> >  +-+-+-+-+-+-+-+-+
> >  |0|1|2|3|4|5|6|7|[PCIe intc]
> >  +-+-+-+-+-+-+-+-+
> >   ^ ^   ^
> >   | |...|[msi_info->irq]
> >   +---+ +--++---+
> >   |||
> > +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
> > |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31|[MSI sets]
> > +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
> >  ^ ^  ^  ^^ ^  ^  ^^ ^  ^  ^
> >  | |  |  || |  |  || |  |  | [MSI irq]
> >  | |  |  || |  |  || |  |  |
> > 
> >   (MSI SET0)   (MSI SET1)  ...   (MSI SET7)
> > 
> 
> Thanks, that's really helpful. You should consider adding this to the
> driver code, as part of the documentation.

Sure, I will add this to the driver documentation in the next version.

> 
> > In software parts, the port->msi_top_domain is created to maintains 8
> > MSI IRQs from the PCIe intc layer, its hardware IRQ will be mapped to
> > msi_info->irq by irq_create_mapping.
> > 
> > The port->msi_domain contains 256 MSI IRQs in total, it consist of 8 MSI
> > sets, and each MSI set contains 32 MSI IRQs.
> > 
> > The structure of mtk_pcie_msi is used to describe the MSI set, I think
> > it will be more convenient and comply with the HW design when use this
> > structure, we can get the information of MSI set directly, instead of
> > calculated by port->base.
> > 
> > When a MSI interrupt is received, the interrupt handle flow will be like
> > the following:
> > 
> >   mtk_pcie_irq_handler (port->irq)
> > |
> > |(find mapping in msi_top_domain)
> > |
> > v
> > mtk_pcie_msi_handler (msi_info->irq)
> > |
> > |(find mapping in msi_domain)
> > |
> > v
> >  handle_edge_irq  (MSI irq)
> > |
> > |
> > v
> > (dispatch to device handler)
> > 
> > Yes, I had to admit that it's not a quite good solution of irqdomains,
> > since the local irq domain is partial coupled with the standard PCI MSI
> > irqdomain.
> > 
> > Should I need to create another irqdomain to maintain the MSI sets
> > laye

Re: [v6,3/4] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

On Fri, 2020-12-25 at 19:22 +, Marc Zyngier wrote:
> Hi Jianjun,
> 
> On Fri, 25 Dec 2020 10:03:07 +,
> Jianjun Wang  wrote:
> > 
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supports Gen3 speed and
> > up to 256 MSI interrupt numbers for multi-function devices.
> > 
> > Add support for new Gen3 controller which can be found on MT8192.
> > 
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> > ---
> >  drivers/pci/controller/Kconfig  |   13 +
> >  drivers/pci/controller/Makefile |1 +
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 1084 +++
> >  3 files changed, 1098 insertions(+)
> >  create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c
> 
> This is a pretty large patch, and it'd be great if you would split it
> into at least 4 parts (core PCIe, PM, MSI, INTx).

Hi Marc,

Thanks for your review, I will try to split it to those parts in the
next version.
> 
> > 
> > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > index 64e2f5e379aa..b242b17025b3 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -242,6 +242,19 @@ config PCIE_MEDIATEK
> >   Say Y here if you want to enable PCIe controller support on
> >   MediaTek SoCs.
> >  
> > +config PCIE_MEDIATEK_GEN3
> > +   tristate "MediaTek Gen3 PCIe controller"
> > +   depends on ARCH_MEDIATEK || COMPILE_TEST
> > +   depends on PCI_MSI_IRQ_DOMAIN
> > +   help
> > + Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> > + This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed,
> > + and support up to 256 MSI interrupt numbers for
> > + multi-function devices.
> > +
> > + Say Y here if you want to enable Gen3 PCIe controller support on
> > + MediaTek SoCs.
> > +
> >  config PCIE_TANGO_SMP8759
> > bool "Tango SMP8759 PCIe controller (DANGEROUS)"
> > depends on ARCH_TANGO && PCI_MSI && OF
> > diff --git a/drivers/pci/controller/Makefile 
> > b/drivers/pci/controller/Makefile
> > index 04c6edc285c5..df5d77d72a9d 100644
> > --- a/drivers/pci/controller/Makefile
> > +++ b/drivers/pci/controller/Makefile
> > @@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
> >  obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
> >  obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
> >  obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > +obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
> >  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> >  obj-$(CONFIG_VMD) += vmd.o
> >  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > new file mode 100644
> > index ..00cdb598a9f5
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -0,0 +1,1084 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * MediaTek PCIe host controller driver.
> > + *
> > + * Copyright (c) 2020 MediaTek Inc.
> > + * Author: Jianjun Wang 
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "../pci.h"
> > +
> > +#define PCIE_SETTING_REG   0x80
> > +#define PCIE_PCI_IDS_1 0x9c
> > +#define PCI_CLASS(class)   (class << 8)
> > +#define PCIE_RC_MODE   BIT(0)
> > +
> > +#define PCIE_CFGNUM_REG0x140
> > +#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
> > +#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
> > +#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
> > 16))
> > +#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
> > +#define PCIE_CFG_OFFSET_ADDR   0x1000
> > +#define PCIE_CFG_HEADER(bus, devfn) \
> > +   (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
> > +
> > +#define PCIE_RST_CTRL_REG  0x148
>

[v6,3/4] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.

Add support for new Gen3 controller which can be found on MT8192.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/Kconfig  |   13 +
 drivers/pci/controller/Makefile |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c | 1084 +++
 3 files changed, 1098 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 64e2f5e379aa..b242b17025b3 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -242,6 +242,19 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable PCIe controller support on
  MediaTek SoCs.
 
+config PCIE_MEDIATEK_GEN3
+   tristate "MediaTek Gen3 PCIe controller"
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   depends on PCI_MSI_IRQ_DOMAIN
+   help
+ Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
+ This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed,
+ and support up to 256 MSI interrupt numbers for
+ multi-function devices.
+
+ Say Y here if you want to enable Gen3 PCIe controller support on
+ MediaTek SoCs.
+
 config PCIE_TANGO_SMP8759
bool "Tango SMP8759 PCIe controller (DANGEROUS)"
depends on ARCH_TANGO && PCI_MSI && OF
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 04c6edc285c5..df5d77d72a9d 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
 obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
new file mode 100644
index ..00cdb598a9f5
--- /dev/null
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -0,0 +1,1084 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Jianjun Wang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pci.h"
+
+#define PCIE_SETTING_REG   0x80
+#define PCIE_PCI_IDS_1 0x9c
+#define PCI_CLASS(class)   (class << 8)
+#define PCIE_RC_MODE   BIT(0)
+
+#define PCIE_CFGNUM_REG0x140
+#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
+#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
+#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
16))
+#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
+#define PCIE_CFG_OFFSET_ADDR   0x1000
+#define PCIE_CFG_HEADER(bus, devfn) \
+   (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
+
+#define PCIE_RST_CTRL_REG  0x148
+#define PCIE_MAC_RSTB  BIT(0)
+#define PCIE_PHY_RSTB  BIT(1)
+#define PCIE_BRG_RSTB  BIT(2)
+#define PCIE_PE_RSTB   BIT(3)
+
+#define PCIE_LTSSM_STATUS_REG  0x150
+#define PCIE_LTSSM_STATE_MASK  GENMASK(28, 24)
+#define PCIE_LTSSM_STATE(val)  ((val & PCIE_LTSSM_STATE_MASK) >> 24)
+#define PCIE_LTSSM_STATE_L2_IDLE   0x14
+
+#define PCIE_LINK_STATUS_REG   0x154
+#define PCIE_PORT_LINKUP   BIT(8)
+
+#define PCIE_MSI_SET_NUM   8
+#define PCIE_MSI_IRQS_PER_SET  32
+#define PCIE_MSI_IRQS_NUM \
+   (PCIE_MSI_IRQS_PER_SET * (PCIE_MSI_SET_NUM))
+
+#define PCIE_INT_ENABLE_REG0x180
+#define PCIE_MSI_MASK  GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
+#define PCIE_MSI_SHIFT 8
+#define PCIE_INTX_SHIFT24
+#define PCIE_INTX_MASK GENMASK(27, 24)
+
+#define PCIE_INT_STATUS_REG0x184
+#define PCIE_MSI_SET_ENABLE_REG0x190
+
+#define PCIE_ICMD_PM_REG   0x198
+#define PCIE_TURN_OFF_LINK BIT(4)
+
+#define PCIE_MSI_ADDR_BASE_REG 0xc00
+#define PCIE_MSI_SET_OFFSET0x10
+#define PCIE_MSI_STATUS_OFFSET 0x04
+#define PCIE_MSI_ENABLE_OFFSET 0x08
+
+#define PCIE_TRANS_TABLE_BASE_REG  0x800
+#def

[v6,4/4] MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer

[Jianjun Wang]

Update entry for MediaTek PCIe controller, add Jianjun Wang
as MediaTek PCI co-maintainer.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index e73636b75f29..1a033812c7f9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13622,6 +13622,7 @@ F:  drivers/pci/controller/dwc/pcie-histb.c
 
 PCIE DRIVER FOR MEDIATEK
 M: Ryder Lee 
+M: Jianjun Wang 
 L: linux-...@vger.kernel.org
 L: linux-media...@lists.infradead.org
 S: Supported
-- 
2.25.1

[v6,1/4] dt-bindings: PCI: mediatek: Add YAML schema

[Jianjun Wang]

Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
Reviewed-by: Rob Herring 
---
 .../bindings/pci/mediatek-pcie-gen3.yaml  | 135 ++
 1 file changed, 135 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
new file mode 100644
index ..e2aecbb56e57
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gen3 PCIe controller on MediaTek SoCs
+
+maintainers:
+  - Jianjun Wang 
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+const: mediatek,mt8192-pcie
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  ranges:
+minItems: 1
+maxItems: 8
+
+  resets:
+minItems: 1
+maxItems: 2
+
+  reset-names:
+anyOf:
+  - const: mac
+  - const: phy
+
+  clocks:
+maxItems: 5
+
+  clock-names:
+items:
+  - const: tl_26m
+  - const: tl_96m
+  - const: tl_32k
+  - const: peri_26m
+  - const: top_133m
+
+  assigned-clocks:
+maxItems: 1
+
+  assigned-clock-parents:
+maxItems: 1
+
+  phys:
+maxItems: 1
+
+  '#interrupt-cells':
+const: 1
+
+  interrupt-controller:
+description: Interrupt controller node for handling legacy PCI interrupts.
+type: object
+properties:
+  '#address-cells':
+const: 0
+  '#interrupt-cells':
+const: 1
+  interrupt-controller: true
+
+required:
+  - '#address-cells'
+  - '#interrupt-cells'
+  - interrupt-controller
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - ranges
+  - clocks
+  - '#interrupt-cells'
+  - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+pcie: pcie@1123 {
+compatible = "mediatek,mt8192-pcie";
+device_type = "pci";
+#address-cells = <3>;
+#size-cells = <2>;
+reg = <0x00 0x1123 0x00 0x4000>;
+reg-names = "pcie-mac";
+interrupts = ;
+bus-range = <0x00 0xff>;
+ranges = <0x8200 0x00 0x1200 0x00
+  0x1200 0x00 0x100>;
+clocks = <&infracfg 40>,
+ <&infracfg 43>,
+ <&infracfg 97>,
+ <&infracfg 99>,
+ <&infracfg 111>;
+clock-names = "tl_26m", "tl_96m", "tl_32k", "peri_26m", "top_133m";
+assigned-clocks = <&topckgen 50>;
+assigned-clock-parents = <&topckgen 91>;
+
+phys = <&pciephy>;
+phy-names = "pcie-phy";
+resets = <&infracfg_rst 0>;
+reset-names = "phy";
+
+#interrupt-cells = <1>;
+interrupt-map-mask = <0 0 0 0x7>;
+interrupt-map = <0 0 0 1 &pcie_intc 0>,
+<0 0 0 2 &pcie_intc 1>,
+<0 0 0 3 &pcie_intc 2>,
+<0 0 0 4 &pcie_intc 3>;
+pcie_intc: interrupt-controller {
+  #address-cells = <0>;
+  #interrupt-cells = <1>;
+  interrupt-controller;
+};
+};
+};
-- 
2.25.1

[v6,0/4] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.

Changes in v6:
1. Export pci_pio_to_address() to support compiling as kernel module;
2. Replace usleep_range(100 * 1000, 120 * 1000) with msleep(100);
3. Replace dev_notice with dev_err;
4. Fix MSI get hwirq flow;
5. Fix warning for possible recursive locking in mtk_pcie_set_affinity.

Changes in v5:
1. Remove unused macros
2. Modify the config read/write callbacks, set the config byte field
   in TLP header and use pci_generic_config_read32/write32
   to access the config space
3. Fix the settings of translation window, both MEM and IO regions
   works properly
4. Fix typos

Changes in v4:
1. Fix PCIe power up/down flow
2. Use "mac" and "phy" for reset names
3. Add clock names
4. Fix the variables type

Changes in v3:
1. Remove standard property in binding document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs

Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown

Jianjun Wang (4):
  dt-bindings: PCI: mediatek: Add YAML schema
  PCI: Export pci_pio_to_address() for module use
  PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192
  MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer

 .../bindings/pci/mediatek-pcie-gen3.yaml  |  135 ++
 MAINTAINERS   |1 +
 drivers/pci/controller/Kconfig|   13 +
 drivers/pci/controller/Makefile   |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c   | 1084 +
 drivers/pci/pci.c |1 +
 6 files changed, 1235 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

-- 
2.25.1

[v6,2/4] PCI: Export pci_pio_to_address() for module use

[Jianjun Wang]

This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.

Signed-off-by: Jianjun Wang 
---
 drivers/pci/pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 6d4d5a2f923d..3de714db2557 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4016,6 +4016,7 @@ phys_addr_t pci_pio_to_address(unsigned long pio)
 
return address;
 }
+EXPORT_SYMBOL(pci_pio_to_address);
 
 unsigned long __weak pci_address_to_pio(phys_addr_t address)
 {
-- 
2.25.1

Re: [v5,2/3] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

On Tue, 2020-12-22 at 11:55 +0800, Nicolas Boichat wrote:
> On Tue, Dec 22, 2020 at 11:38 AM Jianjun Wang  
> wrote:
> >
> > On Mon, 2020-12-21 at 10:18 +0800, Nicolas Boichat wrote:
> > > On Wed, Dec 2, 2020 at 9:39 PM Jianjun Wang  
> > > wrote:
> > > > [snip]
> > > > +static irq_hw_number_t mtk_pcie_msi_get_hwirq(struct msi_domain_info 
> > > > *info,
> > > > + msi_alloc_info_t *arg)
> > > > +{
> > > > +   struct msi_desc *entry = arg->desc;
> > > > +   struct mtk_pcie_port *port = info->chip_data;
> > > > +   int hwirq;
> > > > +
> > > > +   mutex_lock(&port->lock);
> > > > +
> > > > +   hwirq = bitmap_find_free_region(port->msi_irq_in_use, 
> > > > PCIE_MSI_IRQS_NUM,
> > > > +   order_base_2(entry->nvec_used));
> > > > +   if (hwirq < 0) {
> > > > +   mutex_unlock(&port->lock);
> > > > +   return -ENOSPC;
> > > > +   }
> > > > +
> > > > +   mutex_unlock(&port->lock);
> > > > +
> > > > +   return hwirq;
> > >
> > > Code is good, but I had to look twice to make sure the mutex is
> > > unlocked. Is the following marginally better?
> > >
> > > hwirq = ...;
> > >
> > > mutex_unlock(&port->lock);
> > >
> > > if (hwirq < 0)
> > >return -ENOSPC;
> > >
> > > return hwirq;
> >
> > Impressive, I will fix it in the next version, and I think the hwirq can
> > be returned directly since it will be a negative value if
> > bitmap_find_free_region is failed. The code will be like the following:
> >
> > hwirq = ...;
> >
> > mutex_unlock(&port->lock);
> >
> > return hwirq;
> 
> SG, as long as you're okay with returning -ENOMEM instead of -ENOSPC.
> 
> But now I'm having doubt if negative return values are ok, as
> irq_hw_number_t is unsigned long.
> 
> msi_domain_alloc
> (https://elixir.bootlin.com/linux/latest/source/kernel/irq/msi.c#L143)
> uses it to call irq_find_mapping
> (https://elixir.bootlin.com/linux/latest/source/kernel/irq/irqdomain.c#L882)
> without check, and I'm not convinced irq_find_mapping will error out
> gracefully...
> 
I see, it seems the msi_domain_alloc function assume the get_hwirq
callback always success, maybe I should allocate the real hwirq in the
msi_prepare
(https://elixir.bootlin.com/linux/latest/source/kernel/irq/msi.c#L304)
and set it to arg->hwirq, and override the set_desc
(https://elixir.bootlin.com/linux/latest/source/drivers/pci/msi.c#L1405)
to prevent the modify of arg->hwirq.

> > >
> > > > +}
> > > > +
> > > > [snip]
> > > > +static void mtk_pcie_msi_handler(struct irq_desc *desc)
> > > > +{
> > > > +   struct mtk_pcie_msi *msi_info = irq_desc_get_handler_data(desc);
> > > > +   struct irq_chip *irqchip = irq_desc_get_chip(desc);
> > > > +   unsigned long msi_enable, msi_status;
> > > > +   unsigned int virq;
> > > > +   irq_hw_number_t bit, hwirq;
> > > > +
> > > > +   chained_irq_enter(irqchip, desc);
> > > > +
> > > > +   msi_enable = readl(msi_info->base + PCIE_MSI_ENABLE_OFFSET);
> > > > +   while ((msi_status = readl(msi_info->base + 
> > > > PCIE_MSI_STATUS_OFFSET))) {
> > > > +   msi_status &= msi_enable;
> > >
> > > I don't know much about MSI, but what happens if you have a bit that
> > > is set in PCIE_MSI_STATUS_OFFSET register, but not in msi_enable?
> >
> > If the bit that in PCIE_MSI_STATUS_OFFSET register is set but not in
> > msi_enable, it must be an abnormal usage of MSI or something goes wrong,
> > it should be ignored in case we can not find the corresponding handler.
> >
> > > Sounds like you'll just spin-loop forever without acknowledging the
> > > interrupt.
> >
> > The interrupt will be acknowledged in the irq_ack callback of
> > mtk_msi_irq_chip, which belongs to the msi_domain.
> 
> Let's try to go through it (and please explain to me if I get this wrong).
> 
> Say we have:
> 
> msi_enable = [PCIE_MSI_ENABLE_OFFSET] = 0x1;
> 
> while loop:
> 
> msi_status = [PCIE_MSI_STATUS_OFFSET] = 0x3;
> msi_status &= msi_enable => msi_status = 0x3 & 0x1 = 0x1;
> for_each_set_bit(msi_status) {
>do something that presumably will disable the MSI interrupt status?

Yes, the corresponding interrupt status will be cleared.

> }
> (next loop iteration)
> 
> msi_status = [PCIE_MSI_STATUS_OFFSET] = 0x2;
> msi_status &= msi_enable => msi_status = 0x2 & 0x1 = 0x0;
> for_each_set_bit(msi_status) => does nothing.
> 
> msi_status = [PCIE_MSI_STATUS_OFFSET] = 0x2;
> (infinite loop)
> 
> Basically, I'm wondering if you should replace the while condition
> statement with:
> 
> while ((msi_status = readl(msi_info->base + PCIE_MSI_STATUS_OFFSET) &
> msi_enable))
> 

Yes, it will be a dead loop if we receive an abnormal interrupt status,
I will fix it in the next version, thanks for your kindly review.

> ___
> Linux-mediatek mailing list
> linux-media...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [v5,2/3] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

On Mon, 2020-12-21 at 10:18 +0800, Nicolas Boichat wrote:
> On Wed, Dec 2, 2020 at 9:39 PM Jianjun Wang  wrote:
> >
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supports Gen3 speed and
> > up to 256 MSI interrupt numbers for multi-function devices.
> >
> > Add support for new Gen3 controller which can be found on MT8192.
> >
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> 
> FWIW, I looked at Rob and Bjorn's comments on v4, and they seem to
> have been addressed (with one small nit highlighted below).
> 
> > ---
> > This patch dependents on "PCI: Export pci_pio_to_address() for module 
> > use"[1]
> > to build as a kernel module.
> >
> > This interface will be used by PCI host drivers for PIO translation,
> > export it to support compiling those drivers as kernel modules.
> >
> > [1]http://lists.infradead.org/pipermail/linux-mediatek/2020-December/019504.html
> > ---
> >  drivers/pci/controller/Kconfig  |   13 +
> >  drivers/pci/controller/Makefile |1 +
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 1039 +++
> >  3 files changed, 1053 insertions(+)
> >  create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c
> >
> > [snip]
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > new file mode 100644
> > index ..d30ea734ac0a
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -0,0 +1,1039 @@
> > [snip]
> > +static int mtk_pcie_set_trans_table(struct mtk_pcie_port *port,
> > +   resource_size_t cpu_addr,
> > +   resource_size_t pci_addr,
> > +   resource_size_t size,
> > +   unsigned long type, int num)
> > +{
> > +   void __iomem *table;
> > +   u32 val = 0;
> 
> You don't need to init val to 0.
> 
> > +
> > +   if (num >= PCIE_MAX_TRANS_TABLES) {
> > +   dev_notice(port->dev, "not enough translate table[%d] for 
> > addr: %#llx, limited to [%d]\n",
> > +  num, (unsigned long long) cpu_addr,
> > +  PCIE_MAX_TRANS_TABLES);
> > +   return -ENODEV;
> > +   }
> > +
> > +   table = port->base + PCIE_TRANS_TABLE_BASE_REG +
> > +   num * PCIE_ATR_TLB_SET_OFFSET;
> > +
> > +   writel(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(size) - 1), 
> > table);
> > +   writel(upper_32_bits(cpu_addr), table + 
> > PCIE_ATR_SRC_ADDR_MSB_OFFSET);
> > +   writel(lower_32_bits(pci_addr), table + 
> > PCIE_ATR_TRSL_ADDR_LSB_OFFSET);
> > +   writel(upper_32_bits(pci_addr), table + 
> > PCIE_ATR_TRSL_ADDR_MSB_OFFSET);
> > +
> > +   if (type == IORESOURCE_IO)
> > +   val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO;
> > +   else
> > +   val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM;
> > +
> > +   writel(val, table + PCIE_ATR_TRSL_PARAM_OFFSET);
> > +
> > +   return 0;
> > +}
> > +
> > +static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
> > +{
> > +   struct resource_entry *entry;
> > +   struct pci_host_bridge *host = pci_host_bridge_from_priv(port);
> > +   unsigned int table_index = 0;
> > +   int err;
> > +   u32 val;
> > +
> > +   /* Set as RC mode */
> > +   val = readl(port->base + PCIE_SETTING_REG);
> > +   val |= PCIE_RC_MODE;
> > +   writel(val, port->base + PCIE_SETTING_REG);
> > +
> > +   /* Set class code */
> > +   val = readl(port->base + PCIE_PCI_IDS_1);
> > +   val &= ~GENMASK(31, 8);
> > +   val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8);
> > +   writel(val, port->base + PCIE_PCI_IDS_1);
> > +
> > +   /* Assert all reset signals */
> > +   val = readl(port->base + PCIE_RST_CTRL_REG);
> > +   val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
> > +   writel(val, port->base + PCIE_RST_CTRL_REG);
> > +
> > +   /* De-assert reset signals */
> > +   val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
> > +   writel(val, port->base + PCIE_RST_CTRL_REG);
> > +
> > +   /* Delay 100ms to wait th

Re: [v4,2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

On Fri, 2020-12-04 at 12:30 -0600, Bjorn Helgaas wrote:
> On Fri, Dec 04, 2020 at 08:39:09AM +0100, Lukas Wunner wrote:
> > On Mon, Nov 30, 2020 at 11:30:05AM -0600, Bjorn Helgaas wrote:
> > > On Mon, Nov 23, 2020 at 02:45:13PM +0800, Jianjun Wang wrote:
> > > > On Thu, 2020-11-19 at 14:28 -0600, Bjorn Helgaas wrote:
> > > > > > +static int mtk_pcie_setup(struct mtk_pcie_port *port)
> > > > > > +{
> > [...]
> > > > > > +   /* Try link up */
> > > > > > +   err = mtk_pcie_startup_port(port);
> > > > > > +   if (err) {
> > > > > > +   dev_notice(dev, "PCIe link down\n");
> > > > > > +   goto err_setup;
> > > > > 
> > > > > Generally it should not be a fatal error if the link is not up at
> > > > > probe-time.  You may be able to hot-add a device, or the device may
> > > > > have some external power control that will power it up later.
> > > > 
> > > > This is for the power saving requirement. If there is no device
> > > > connected with the PCIe slot, the PCIe MAC and PHY should be powered
> > > > off.
> > > > 
> > > > Is there any standard flow to support power down the hardware at
> > > > probe-time if no device is connected and power it up when hot-add a
> > > > device?
> > > 
> > > That's a good question.  I assume this looks like a standard PCIe
> > > hot-add event?
> > > 
> > > When you hot-add a device, does the Root Port generate a Presence
> > > Detect Changed interrupt?  The pciehp driver should field that
> > > interrupt and turn on power to the slot via the Power Controller
> > > Control bit in the Slot Control register.
> > > 
> > > Does your hardware require something more than that to control the MAC
> > > and PHY power?
> > 
> > Power saving of unused PCIe ports is generally achieved through the
> > runtime PM framework.  When a PCIe port runtime suspends, the PCIe
> > core will transition it to D3hot.  On top of that, the platform
> > may be able to transition the port to D3cold.  Currently only the
> > ACPI platform supports that.  Conceivably, devicetree-based systems
> > may want to disable certain clocks or regulators when a PCIe port
> > runtime suspends.  I think we do not support that yet but it could
> > be added to drivers/pci/pcie/portdrv*.
> > 
> > A hotplug port is expected to signal PDC and DLLSC interrupts even
> > when in D3hot.  At least that's our experience with Thunderbolt.
> > To support hotplug interrupts in D3cold, some external mechanism
> > (such as a PME) is necessary to wake up the port on hotplug.
> > This is also supported with recent Thunderbolt systems.
> > 
> > Because we've seen various incompatibilities when runtime suspending
> > PCIe ports, certain conditions must be satisfied for runtime PM
> > to be enabled.  They're encoded in pci_bridge_d3_possible().
> > Generally, hotplug ports only runtime suspend if they belong to
> > a Thunderbolt controller or if the ACPI platform explicitly allows
> > runtime PM (through presence of a _PR3 method or a device property).
> > Non-hotplug ports runtime suspend if the BIOS is newer than 2015
> > (as specified by DMI).
> > 
> > Obviously, this policy is very x86-focussed because both Thunderbolt
> > and DMI are only really a thing on x86.  That's about to change though
> > because Apple's new arm64-based Macs have Thunderbolt integrated into
> > the SoC and arm64 SoCs are making inroads in the datacenter, which is
> > an important use case for PCIe hotplug (hot-swappable NVMe drives).
> > So we may have to amend pci_bridge_d3_possible() to whitelist
> > PCIe ports for runtime PM on specific arches or systems.
> 
> Thanks for all this very useful information!
> 
> My interpretation for the mediatek situation:
> 
>   - I assume this patch leaves or puts the Root Port in D3cold if no
> downstream devices are present.
> 
>   - I don't see any support for PME or similar mechanisms to signal a
> hot-add while the RP is in D3cold.
> 
>   - So I assume you don't support hot-add if the slot was empty at
> boot and that's acceptable for your platform.

Yes, the hardware of Root Port will be totally powered off by gating its
MTCMOS and clocks if the slot is empty at boot time. Because we are
focus on the scenario of power saving, it's acceptable if we don't
support hot-add.

Thanks.

Re: [v1] PCI: Export pci_pio_to_address() for module use

[Jianjun Wang]

On Wed, 2020-12-02 at 07:49 -0600, Bjorn Helgaas wrote:
> On Wed, Dec 02, 2020 at 09:12:55PM +0800, Jianjun Wang wrote:
> > This interface will be used by PCI host drivers for PIO translation,
> > export it to support compiling those drivers as kernel modules.
> > 
> > Signed-off-by: Jianjun Wang 
> 
> Please include this in a series that adds a modular host driver or
> converts an existing one to be modular.  That way we know we have at
> least one user and things get merged in the right order.

Hi Bjorn,

OK, I will include this patch in the next version of pcie-mediatek-gen3
series.

thanks.
> 
> > ---
> >  drivers/pci/pci.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> > index a458c46d7e39..509008899182 100644
> > --- a/drivers/pci/pci.c
> > +++ b/drivers/pci/pci.c
> > @@ -4003,6 +4003,7 @@ phys_addr_t pci_pio_to_address(unsigned long pio)
> >  
> > return address;
> >  }
> > +EXPORT_SYMBOL(pci_pio_to_address);
> >  
> >  unsigned long __weak pci_address_to_pio(phys_addr_t address)
> >  {
> > -- 
> > 2.25.1
> > 

[v5,2/3] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192

[Jianjun Wang]

MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.

Add support for new Gen3 controller which can be found on MT8192.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
This patch dependents on "PCI: Export pci_pio_to_address() for module use"[1]
to build as a kernel module.

This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.

[1]http://lists.infradead.org/pipermail/linux-mediatek/2020-December/019504.html
---
 drivers/pci/controller/Kconfig  |   13 +
 drivers/pci/controller/Makefile |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c | 1039 +++
 3 files changed, 1053 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index f18c3725ef80..519461642193 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -239,6 +239,19 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable PCIe controller support on
  MediaTek SoCs.
 
+config PCIE_MEDIATEK_GEN3
+   tristate "MediaTek Gen3 PCIe controller"
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   depends on PCI_MSI_IRQ_DOMAIN
+   help
+ Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
+ This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed,
+ and support up to 256 MSI interrupt numbers for
+ multi-function devices.
+
+ Say Y here if you want to enable Gen3 PCIe controller support on
+ MediaTek SoCs.
+
 config PCIE_TANGO_SMP8759
bool "Tango SMP8759 PCIe controller (DANGEROUS)"
depends on ARCH_TANGO && PCI_MSI && OF
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index bcdbf49ab1e4..9c1b96777597 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
 obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
new file mode 100644
index ..d30ea734ac0a
--- /dev/null
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -0,0 +1,1039 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Jianjun Wang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pci.h"
+
+#define PCIE_SETTING_REG   0x80
+#define PCIE_PCI_IDS_1 0x9c
+#define PCI_CLASS(class)   (class << 8)
+#define PCIE_RC_MODE   BIT(0)
+
+#define PCIE_CFGNUM_REG0x140
+#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
+#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
+#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
16))
+#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
+#define PCIE_CFG_OFFSET_ADDR   0x1000
+#define PCIE_CFG_HEADER(bus, devfn) \
+   (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
+
+#define PCIE_RST_CTRL_REG  0x148
+#define PCIE_MAC_RSTB  BIT(0)
+#define PCIE_PHY_RSTB  BIT(1)
+#define PCIE_BRG_RSTB  BIT(2)
+#define PCIE_PE_RSTB   BIT(3)
+
+#define PCIE_LTSSM_STATUS_REG  0x150
+#define PCIE_LTSSM_STATE_MASK  GENMASK(28, 24)
+#define PCIE_LTSSM_STATE(val)  ((val & PCIE_LTSSM_STATE_MASK) >> 24)
+#define PCIE_LTSSM_STATE_L2_IDLE   0x14
+
+#define PCIE_LINK_STATUS_REG   0x154
+#define PCIE_PORT_LINKUP   BIT(8)
+
+#define PCIE_MSI_SET_NUM   8
+#define PCIE_MSI_IRQS_PER_SET  32
+#define PCIE_MSI_IRQS_NUM \
+   (PCIE_MSI_IRQS_PER_SET * (PCIE_MSI_SET_NUM))
+
+#define PCIE_INT_ENABLE_REG0x180
+#define PCIE_MSI_MASK  GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
+#define PCIE_MSI_SHIFT 8
+#define PCIE_INTX_SHIFT24
+#define PCIE_INTX_MASK GENMASK(27, 24)
+
+#define PCIE_INT_STATUS_REG0x184
+#define PCIE_MSI_SET_ENABLE_REG  

[v5,1/3] dt-bindings: PCI: mediatek: Add YAML schema

[Jianjun Wang]

Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
Reviewed-by: Rob Herring 
---
 .../bindings/pci/mediatek-pcie-gen3.yaml  | 135 ++
 1 file changed, 135 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
new file mode 100644
index ..e2aecbb56e57
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gen3 PCIe controller on MediaTek SoCs
+
+maintainers:
+  - Jianjun Wang 
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+const: mediatek,mt8192-pcie
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  ranges:
+minItems: 1
+maxItems: 8
+
+  resets:
+minItems: 1
+maxItems: 2
+
+  reset-names:
+anyOf:
+  - const: mac
+  - const: phy
+
+  clocks:
+maxItems: 5
+
+  clock-names:
+items:
+  - const: tl_26m
+  - const: tl_96m
+  - const: tl_32k
+  - const: peri_26m
+  - const: top_133m
+
+  assigned-clocks:
+maxItems: 1
+
+  assigned-clock-parents:
+maxItems: 1
+
+  phys:
+maxItems: 1
+
+  '#interrupt-cells':
+const: 1
+
+  interrupt-controller:
+description: Interrupt controller node for handling legacy PCI interrupts.
+type: object
+properties:
+  '#address-cells':
+const: 0
+  '#interrupt-cells':
+const: 1
+  interrupt-controller: true
+
+required:
+  - '#address-cells'
+  - '#interrupt-cells'
+  - interrupt-controller
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - ranges
+  - clocks
+  - '#interrupt-cells'
+  - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+pcie: pcie@1123 {
+compatible = "mediatek,mt8192-pcie";
+device_type = "pci";
+#address-cells = <3>;
+#size-cells = <2>;
+reg = <0x00 0x1123 0x00 0x4000>;
+reg-names = "pcie-mac";
+interrupts = ;
+bus-range = <0x00 0xff>;
+ranges = <0x8200 0x00 0x1200 0x00
+  0x1200 0x00 0x100>;
+clocks = <&infracfg 40>,
+ <&infracfg 43>,
+ <&infracfg 97>,
+ <&infracfg 99>,
+ <&infracfg 111>;
+clock-names = "tl_26m", "tl_96m", "tl_32k", "peri_26m", "top_133m";
+assigned-clocks = <&topckgen 50>;
+assigned-clock-parents = <&topckgen 91>;
+
+phys = <&pciephy>;
+phy-names = "pcie-phy";
+resets = <&infracfg_rst 0>;
+reset-names = "phy";
+
+#interrupt-cells = <1>;
+interrupt-map-mask = <0 0 0 0x7>;
+interrupt-map = <0 0 0 1 &pcie_intc 0>,
+<0 0 0 2 &pcie_intc 1>,
+<0 0 0 3 &pcie_intc 2>,
+<0 0 0 4 &pcie_intc 3>;
+pcie_intc: interrupt-controller {
+  #address-cells = <0>;
+  #interrupt-cells = <1>;
+  interrupt-controller;
+};
+};
+};
-- 
2.25.1

[v5,3/3] MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer

[Jianjun Wang]

Update entry for MediaTek PCIe controller, add Jianjun Wang
as MediaTek PCI co-maintainer.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..5c6110468526 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13459,6 +13459,7 @@ F:  drivers/pci/controller/dwc/pcie-histb.c
 
 PCIE DRIVER FOR MEDIATEK
 M: Ryder Lee 
+M: Jianjun Wang 
 L: linux-...@vger.kernel.org
 L: linux-media...@lists.infradead.org
 S: Supported
-- 
2.25.1

[v5,0/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.

Changes in v5:
1. Remove unused macros
2. Modify the config read/write callbacks, set the config byte field
   in TLP header and use pci_generic_config_read32/write32
   to access the config space
3. Fix the settings of translation window, both MEM and IO regions
   works properly
4. Fix typos

Changes in v4:
1. Fix PCIe power up/down flow
2. Use "mac" and "phy" for reset names
3. Add clock names
4. Fix the variables type

Changes in v3:
1. Remove standard property in binding document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs

Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown

Jianjun Wang (3):
  dt-bindings: PCI: mediatek: Add YAML schema
  PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192
  MAINTAINERS: update entry for MediaTek PCIe controller

 .../bindings/pci/mediatek-pcie-gen3.yaml  |  135 +++
 MAINTAINERS   |1 +
 drivers/pci/controller/Kconfig|   13 +
 drivers/pci/controller/Makefile   |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c   | 1039 +
 5 files changed, 1189 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

-- 
2.25.1

[v1] PCI: Export pci_pio_to_address() for module use

[Jianjun Wang]

This interface will be used by PCI host drivers for PIO translation,
export it to support compiling those drivers as kernel modules.

Signed-off-by: Jianjun Wang 
---
 drivers/pci/pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index a458c46d7e39..509008899182 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4003,6 +4003,7 @@ phys_addr_t pci_pio_to_address(unsigned long pio)
 
return address;
 }
+EXPORT_SYMBOL(pci_pio_to_address);
 
 unsigned long __weak pci_address_to_pio(phys_addr_t address)
 {
-- 
2.25.1

Re: [v4,2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

On Mon, 2020-11-30 at 11:30 -0600, Bjorn Helgaas wrote:
> [+cc Lukas, pciehp power control question]
> 
> On Mon, Nov 23, 2020 at 02:45:13PM +0800, Jianjun Wang wrote:
> > On Thu, 2020-11-19 at 14:28 -0600, Bjorn Helgaas wrote:
> > > "Add new generation" really contains no information.  And "mediatek"
> > > is already used for the pcie-mediatek.c driver, so we should have a
> > > new tag for this new driver.  Include useful information in the
> > > subject, e.g.,
> > > 
> > >   PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192
> 
> > > > +static int mtk_pcie_setup(struct mtk_pcie_port *port)
> > > > +{
> > > > +   struct device *dev = port->dev;
> > > > +   struct platform_device *pdev = to_platform_device(dev);
> > > > +   struct resource *regs;
> > > > +   int err;
> > > > +
> > > > +   regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, 
> > > > "pcie-mac");
> > > > +   port->base = devm_ioremap_resource(dev, regs);
> > > > +   if (IS_ERR(port->base)) {
> > > > +   dev_notice(dev, "failed to map register base\n");
> > > > +   return PTR_ERR(port->base);
> > > > +   }
> > > > +
> > > > +   port->reg_base = regs->start;
> > > > +
> > > > +   /* Don't touch the hardware registers before power up */
> > > > +   err = mtk_pcie_power_up(port);
> > > > +   if (err)
> > > > +   return err;
> > > > +
> > > > +   /* Try link up */
> > > > +   err = mtk_pcie_startup_port(port);
> > > > +   if (err) {
> > > > +   dev_notice(dev, "PCIe link down\n");
> > > > +   goto err_setup;
> > > 
> > > Generally it should not be a fatal error if the link is not up at
> > > probe-time.  You may be able to hot-add a device, or the device may
> > > have some external power control that will power it up later.
> > 
> > This is for the power saving requirement. If there is no device
> > connected with the PCIe slot, the PCIe MAC and PHY should be powered
> > off.
> > 
> > Is there any standard flow to support power down the hardware at
> > probe-time if no device is connected and power it up when hot-add a
> > device?
> 
> That's a good question.  I assume this looks like a standard PCIe
> hot-add event?
> 
> When you hot-add a device, does the Root Port generate a Presence
> Detect Changed interrupt?  The pciehp driver should field that
> interrupt and turn on power to the slot via the Power Controller
> Control bit in the Slot Control register.
> 
> Does your hardware require something more than that to control the MAC
> and PHY power?
> 
> Bjorn

The hardware support to generate a Presence Detect Changed interrupt
when hot-add a device.

But it seems that we should keep the PHY's power and clocks to ensure
the data link layer state change can be detected, and keep the MAC layer
active for routing the interrupt event to pciehp driver handler.

For the power saving requirement, the modules that is not used when
probe-time must be powered off, so I think we may not support hot-plug
in this case.

Thanks

Re: [v4,2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

On Thu, 2020-11-19 at 14:28 -0600, Bjorn Helgaas wrote:
> "Add new generation" really contains no information.  And "mediatek"
> is already used for the pcie-mediatek.c driver, so we should have a
> new tag for this new driver.  Include useful information in the
> subject, e.g.,
> 
>   PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192
> 
> On Wed, Nov 18, 2020 at 04:29:34PM +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supoorts Gen3 speed and
> > up to 256 MSI interrupt numbers for multi-function devices.
> 
> s/supoorts/supports/
> 
> > Add support for new Gen3 controller which can be found on MT8192.
> > 
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> > ---
> >  drivers/pci/controller/Kconfig  |   14 +
> >  drivers/pci/controller/Makefile |1 +
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 1031 +++
> >  3 files changed, 1046 insertions(+)
> >  create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c
> > 
> > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > index f18c3725ef80..83daa772595b 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -239,6 +239,20 @@ config PCIE_MEDIATEK
> >   Say Y here if you want to enable PCIe controller support on
> >   MediaTek SoCs.
> >  
> > +config PCIE_MEDIATEK_GEN3
> > +   tristate "MediaTek GEN3 PCIe controller"
> 
> s/GEN3/Gen3/
> 
> > +   depends on ARCH_MEDIATEK || COMPILE_TEST
> > +   depends on OF
> 
> Do you really need "depends on OF"?  There are stubs to cover most
> interfaces even when CONFIG_OF is not set.  Depending on OF reduces
> compile-test coverage.
> 
> > +   depends on PCI_MSI_IRQ_DOMAIN
> > +   help
> > + Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> > + This PCIe controller provides the capable of Gen3, Gen2 and
> 
> "provides the capable of" doesn't parse.
> 
> > + Gen1 speed, and support up to 256 MSI interrupt numbers for
> > + multi-function devices.
> > +
> > + Say Y here if you want to enable Gen3 PCIe controller support on
> > + MediaTek SoCs.
> > +
> >  config PCIE_TANGO_SMP8759
> > bool "Tango SMP8759 PCIe controller (DANGEROUS)"
> > depends on ARCH_TANGO && PCI_MSI && OF
> > diff --git a/drivers/pci/controller/Makefile 
> > b/drivers/pci/controller/Makefile
> > index bcdbf49ab1e4..9c1b96777597 100644
> > --- a/drivers/pci/controller/Makefile
> > +++ b/drivers/pci/controller/Makefile
> > @@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
> >  obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
> >  obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
> >  obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > +obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
> >  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> >  obj-$(CONFIG_VMD) += vmd.o
> >  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > new file mode 100644
> > index ..dd454cfee373
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -0,0 +1,1031 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * MediaTek PCIe host controller driver.
> > + *
> > + * Copyright (c) 2020 MediaTek Inc.
> > + * Author: Jianjun Wang 
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "../pci.h"
> > +
> > +#define PCIE_SETTING_REG   0x80
> > +#define PCIE_PCI_IDS_1 0x9c
> > +#define PCI_CLASS(class)   (class << 8)
> > +#define PCIE_RC_MODE   BIT(0)
> > +
> > +#define PCIE_CFGNUM_REG0x140
> > +#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
> > +#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK

Re: [v4,2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

On Thu, 2020-11-19 at 09:22 -0600, Rob Herring wrote:
> On Wed, Nov 18, 2020 at 04:29:34PM +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supoorts Gen3 speed and
> > up to 256 MSI interrupt numbers for multi-function devices.
> > 
> > Add support for new Gen3 controller which can be found on MT8192.
> > 
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> > ---
> >  drivers/pci/controller/Kconfig  |   14 +
> >  drivers/pci/controller/Makefile |1 +
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 1031 +++
> >  3 files changed, 1046 insertions(+)
> >  create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c
> > 
> > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > index f18c3725ef80..83daa772595b 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -239,6 +239,20 @@ config PCIE_MEDIATEK
> >   Say Y here if you want to enable PCIe controller support on
> >   MediaTek SoCs.
> >  
> > +config PCIE_MEDIATEK_GEN3
> > +   tristate "MediaTek GEN3 PCIe controller"
> > +   depends on ARCH_MEDIATEK || COMPILE_TEST
> > +   depends on OF
> > +   depends on PCI_MSI_IRQ_DOMAIN
> > +   help
> > + Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> > + This PCIe controller provides the capable of Gen3, Gen2 and
> > + Gen1 speed, and support up to 256 MSI interrupt numbers for
> > + multi-function devices.
> > +
> > + Say Y here if you want to enable Gen3 PCIe controller support on
> > + MediaTek SoCs.
> > +
> >  config PCIE_TANGO_SMP8759
> > bool "Tango SMP8759 PCIe controller (DANGEROUS)"
> > depends on ARCH_TANGO && PCI_MSI && OF
> > diff --git a/drivers/pci/controller/Makefile 
> > b/drivers/pci/controller/Makefile
> > index bcdbf49ab1e4..9c1b96777597 100644
> > --- a/drivers/pci/controller/Makefile
> > +++ b/drivers/pci/controller/Makefile
> > @@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
> >  obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
> >  obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
> >  obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > +obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
> >  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> >  obj-$(CONFIG_VMD) += vmd.o
> >  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > new file mode 100644
> > index ..dd454cfee373
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -0,0 +1,1031 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * MediaTek PCIe host controller driver.
> > + *
> > + * Copyright (c) 2020 MediaTek Inc.
> > + * Author: Jianjun Wang 
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "../pci.h"
> > +
> > +#define PCIE_SETTING_REG   0x80
> > +#define PCIE_PCI_IDS_1 0x9c
> > +#define PCI_CLASS(class)   (class << 8)
> > +#define PCIE_RC_MODE   BIT(0)
> > +
> > +#define PCIE_CFGNUM_REG0x140
> > +#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
> > +#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
> > +#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
> > 16))
> > +#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
> > +#define PCIE_CFG_OFFSET_ADDR   0x1000
> > +#define PCIE_CFG_HEADER(devfn, bus) \
> > +   (PCIE_CFG_DEVFN(devfn) | PCIE_CFG_BUS(bus))
> > +
> > +#define PCIE_CFG_HEADER_FORCE_BE(devfn, bus, bytes) \
> > +   (PCIE_CFG_HEADER(devfn, bus) | PCIE_CFG_BYTE_EN(bytes) \
> > +| PCIE_CFG_FORCE_BYTE_EN)
> > +
> > +#define PCIE_RST_CTRL_REG  0x148
> > +#define PCIE_MAC_RSTB  BIT(0)
&g

[v4,2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supoorts Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.

Add support for new Gen3 controller which can be found on MT8192.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/Kconfig  |   14 +
 drivers/pci/controller/Makefile |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c | 1031 +++
 3 files changed, 1046 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index f18c3725ef80..83daa772595b 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -239,6 +239,20 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable PCIe controller support on
  MediaTek SoCs.
 
+config PCIE_MEDIATEK_GEN3
+   tristate "MediaTek GEN3 PCIe controller"
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   depends on OF
+   depends on PCI_MSI_IRQ_DOMAIN
+   help
+ Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
+ This PCIe controller provides the capable of Gen3, Gen2 and
+ Gen1 speed, and support up to 256 MSI interrupt numbers for
+ multi-function devices.
+
+ Say Y here if you want to enable Gen3 PCIe controller support on
+ MediaTek SoCs.
+
 config PCIE_TANGO_SMP8759
bool "Tango SMP8759 PCIe controller (DANGEROUS)"
depends on ARCH_TANGO && PCI_MSI && OF
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index bcdbf49ab1e4..9c1b96777597 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
 obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
new file mode 100644
index ..dd454cfee373
--- /dev/null
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -0,0 +1,1031 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Jianjun Wang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pci.h"
+
+#define PCIE_SETTING_REG   0x80
+#define PCIE_PCI_IDS_1 0x9c
+#define PCI_CLASS(class)   (class << 8)
+#define PCIE_RC_MODE   BIT(0)
+
+#define PCIE_CFGNUM_REG0x140
+#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
+#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
+#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
16))
+#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
+#define PCIE_CFG_OFFSET_ADDR   0x1000
+#define PCIE_CFG_HEADER(devfn, bus) \
+   (PCIE_CFG_DEVFN(devfn) | PCIE_CFG_BUS(bus))
+
+#define PCIE_CFG_HEADER_FORCE_BE(devfn, bus, bytes) \
+   (PCIE_CFG_HEADER(devfn, bus) | PCIE_CFG_BYTE_EN(bytes) \
+| PCIE_CFG_FORCE_BYTE_EN)
+
+#define PCIE_RST_CTRL_REG  0x148
+#define PCIE_MAC_RSTB  BIT(0)
+#define PCIE_PHY_RSTB  BIT(1)
+#define PCIE_BRG_RSTB  BIT(2)
+#define PCIE_PE_RSTB   BIT(3)
+
+#define PCIE_MISC_STATUS_REG   0x14C
+#define PCIE_LTR_MSG_RECEIVED  BIT(0)
+#define PCIE_PCIE_MSG_RECEIVED BIT(1)
+
+#define PCIE_LTSSM_STATUS_REG  0x150
+#define PCIE_LTSSM_STATE_MASK  GENMASK(28, 24)
+#define PCIE_LTSSM_STATE(val)  ((val & PCIE_LTSSM_STATE_MASK) >> 24)
+#define PCIE_LTSSM_STATE_L00x10
+#define PCIE_LTSSM_STATE_L1_IDLE   0x13
+#define PCIE_LTSSM_STATE_L2_IDLE   0x14
+
+#define PCIE_LINK_STATUS_REG   0x154
+#define PCIE_PORT_LINKUP   BIT(8)
+
+#define PCIE_MSI_SET_NUM   8
+#define PCIE_MSI_IRQS_PER_SET  32
+#define PCIE_MSI_IRQS_NUM \
+   (PCIE_MSI_IRQS_PER_SET * (PCIE_MSI_SET_NUM))
+
+#define PCIE_INT_ENABLE_REG0x180
+#define PCIE_MSI_MASK  GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
+#define PCIE_MSI_SHIFT 8
+#define PCIE_INTX_SHIFT24
+#define PCIE_INTX_MASK GENMASK(27, 24)
+#define PCIE

[v4,3/3] MAINTAINERS: update entry for MediaTek PCIe controller

[Jianjun Wang]

Add maintainer for MediaTek PCIe controller driver.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..5c6110468526 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13459,6 +13459,7 @@ F:  drivers/pci/controller/dwc/pcie-histb.c
 
 PCIE DRIVER FOR MEDIATEK
 M: Ryder Lee 
+M: Jianjun Wang 
 L: linux-...@vger.kernel.org
 L: linux-media...@lists.infradead.org
 S: Supported
-- 
2.25.1

[v4,1/3] dt-bindings: PCI: mediatek: Add YAML schema

[Jianjun Wang]

Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 .../bindings/pci/mediatek-pcie-gen3.yaml  | 135 ++
 1 file changed, 135 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
new file mode 100644
index ..e2aecbb56e57
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gen3 PCIe controller on MediaTek SoCs
+
+maintainers:
+  - Jianjun Wang 
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+const: mediatek,mt8192-pcie
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  ranges:
+minItems: 1
+maxItems: 8
+
+  resets:
+minItems: 1
+maxItems: 2
+
+  reset-names:
+anyOf:
+  - const: mac
+  - const: phy
+
+  clocks:
+maxItems: 5
+
+  clock-names:
+items:
+  - const: tl_26m
+  - const: tl_96m
+  - const: tl_32k
+  - const: peri_26m
+  - const: top_133m
+
+  assigned-clocks:
+maxItems: 1
+
+  assigned-clock-parents:
+maxItems: 1
+
+  phys:
+maxItems: 1
+
+  '#interrupt-cells':
+const: 1
+
+  interrupt-controller:
+description: Interrupt controller node for handling legacy PCI interrupts.
+type: object
+properties:
+  '#address-cells':
+const: 0
+  '#interrupt-cells':
+const: 1
+  interrupt-controller: true
+
+required:
+  - '#address-cells'
+  - '#interrupt-cells'
+  - interrupt-controller
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - ranges
+  - clocks
+  - '#interrupt-cells'
+  - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+pcie: pcie@1123 {
+compatible = "mediatek,mt8192-pcie";
+device_type = "pci";
+#address-cells = <3>;
+#size-cells = <2>;
+reg = <0x00 0x1123 0x00 0x4000>;
+reg-names = "pcie-mac";
+interrupts = ;
+bus-range = <0x00 0xff>;
+ranges = <0x8200 0x00 0x1200 0x00
+  0x1200 0x00 0x100>;
+clocks = <&infracfg 40>,
+ <&infracfg 43>,
+ <&infracfg 97>,
+ <&infracfg 99>,
+ <&infracfg 111>;
+clock-names = "tl_26m", "tl_96m", "tl_32k", "peri_26m", "top_133m";
+assigned-clocks = <&topckgen 50>;
+assigned-clock-parents = <&topckgen 91>;
+
+phys = <&pciephy>;
+phy-names = "pcie-phy";
+resets = <&infracfg_rst 0>;
+reset-names = "phy";
+
+#interrupt-cells = <1>;
+interrupt-map-mask = <0 0 0 0x7>;
+interrupt-map = <0 0 0 1 &pcie_intc 0>,
+<0 0 0 2 &pcie_intc 1>,
+<0 0 0 3 &pcie_intc 2>,
+<0 0 0 4 &pcie_intc 3>;
+pcie_intc: interrupt-controller {
+  #address-cells = <0>;
+  #interrupt-cells = <1>;
+  interrupt-controller;
+};
+};
+};
-- 
2.25.1

[v4,0/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.

Changes in v4:
1. Fix PCIe power up/down flow
2. Use "mac" and "phy" for reset names
3. Add clock names
4. Fix the variables type

Changes in v3:
1. Remove standard property in binding document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs

Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown

Jianjun Wang (3):
  dt-bindings: PCI: mediatek: Add YAML schema
  PCI: mediatek: Add new generation controller support
  MAINTAINERS: update entry for MediaTek PCIe controller

 .../bindings/pci/mediatek-pcie-gen3.yaml  |  135 +++
 MAINTAINERS   |1 +
 drivers/pci/controller/Kconfig|   14 +
 drivers/pci/controller/Makefile   |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c   | 1032 +
 5 files changed, 1183 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

-- 
2.25.1

Re: [v3,2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

On Mon, 2020-09-28 at 10:32 +0200, Philipp Zabel wrote:
> Hi Jianjun,
> 
> On Sun, 2020-09-27 at 15:45 +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supoorts Gen3 speed and
> > up to 256 MSI interrupt numbers for multi-function devices.
> > 
> > Add support for new Gen3 controller which can be found on MT8192.
> > 
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> > ---
> >  drivers/pci/controller/Kconfig  |   14 +
> >  drivers/pci/controller/Makefile |1 +
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 1024 +++
> >  3 files changed, 1039 insertions(+)
> >  create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c
> > 
> [...]
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > new file mode 100644
> > index ..ad69c789b24d
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -0,0 +1,1024 @@
> [...]
> > +static int mtk_pcie_power_up(struct mtk_pcie_port *port)
> > +{
> > +   struct device *dev = port->dev;
> > +   int err;
> > +
> > +   port->phy_reset = devm_reset_control_get_optional_exclusive(dev,
> > +   "phy-rst");
> > +   if (IS_ERR(port->phy_reset))
> > +   return PTR_ERR(port->phy_reset);
> > +
> > +   reset_control_deassert(port->phy_reset);
> 
> In general, it is better to request all required resources before
> starting to activate the hardware.
> 
> > +
> > +   /* PHY power on and enable pipe clock */
> > +   port->phy = devm_phy_optional_get(dev, "pcie-phy");
> > +   if (IS_ERR(port->phy))
> > +   return PTR_ERR(port->phy);
> 
> For example, if the PHY driver is not loaded yet and this returns
> -EPROBE_DEFER, it was not useful to take the PHY out of reset above.
> Also, phy-rst is kept deasserted if this fails.
> 
> > +
> > +   err = phy_init(port->phy);
> > +   if (err) {
> > +   dev_notice(dev, "failed to initialize pcie phy\n");
> > +   return err;
> 
> phy-rst is kept deasserted if this fails.
> 
> > +   }
> > +
> > +   err = phy_power_on(port->phy);
> > +   if (err) {
> > +   dev_notice(dev, "failed to power on pcie phy\n");
> > +   goto err_phy_on;
> > +   }
> > +
> > +   port->mac_reset = devm_reset_control_get_optional_exclusive(dev,
> > +   "mac-rst");
> > +   if (IS_ERR(port->mac_reset))
> > +   return PTR_ERR(port->mac_reset);
> 
> The PHY is not powered down if this fails.
> 
> > +
> > +   reset_control_deassert(port->mac_reset);
> > +
> > +   /* MAC power on and enable transaction layer clocks */
> > +   pm_runtime_enable(dev);
> > +   pm_runtime_get_sync(dev);
> > +
> > +   err = mtk_pcie_clk_init(port);
> > +   if (err) {
> > +   dev_notice(dev, "clock init failed\n");
> > +   goto err_clk_init;
> > +   }
> > +
> > +   return 0;
> > +
> > +err_clk_init:
> > +   pm_runtime_put_sync(dev);
> > +   pm_runtime_disable(dev);
> > +   reset_control_assert(port->mac_reset);
> > +   phy_power_off(port->phy);
> > +err_phy_on:
> > +   phy_exit(port->phy);
> > +   reset_control_assert(port->phy_reset);
> > +
> > +   return -EBUSY;
> > +}
> > +
> > +static void mtk_pcie_power_down(struct mtk_pcie_port *port)
> > +{
> > +   phy_power_off(port->phy);
> > +   phy_exit(port->phy);
> > +
> > +   clk_bulk_disable_unprepare(port->num_clks, port->clks);
> 
> In the power-up sequence clocks are enabled last, but here they are not
> disabled before the PHY is powered off. Is this on purpose?
> 
> > +
> > +   pm_runtime_put_sync(port->dev);
> > +   pm_runtime_disable(port->dev);
> 
> In the power-up error path, PHY and controller resets are asserted
> again, but here they are kept deasserted. Should they be asserted here
> as well?
> 
> regards
> Philipp

Hi Philipp,

Sorry for the late responding and thanks for your review, I will fix it
in the next version.

Thanks.

[v3,2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supoorts Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.

Add support for new Gen3 controller which can be found on MT8192.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/Kconfig  |   14 +
 drivers/pci/controller/Makefile |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c | 1024 +++
 3 files changed, 1039 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index f18c3725ef80..83daa772595b 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -239,6 +239,20 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable PCIe controller support on
  MediaTek SoCs.
 
+config PCIE_MEDIATEK_GEN3
+   tristate "MediaTek GEN3 PCIe controller"
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   depends on OF
+   depends on PCI_MSI_IRQ_DOMAIN
+   help
+ Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
+ This PCIe controller provides the capable of Gen3, Gen2 and
+ Gen1 speed, and support up to 256 MSI interrupt numbers for
+ multi-function devices.
+
+ Say Y here if you want to enable Gen3 PCIe controller support on
+ MediaTek SoCs.
+
 config PCIE_TANGO_SMP8759
bool "Tango SMP8759 PCIe controller (DANGEROUS)"
depends on ARCH_TANGO && PCI_MSI && OF
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index bcdbf49ab1e4..9c1b96777597 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
 obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
new file mode 100644
index ..ad69c789b24d
--- /dev/null
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -0,0 +1,1024 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Jianjun Wang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pci.h"
+
+#define PCIE_SETTING_REG   0x80
+#define PCIE_PCI_IDS_1 0x9c
+#define PCI_CLASS(class)   (class << 8)
+#define PCIE_RC_MODE   BIT(0)
+
+#define PCIE_CFGNUM_REG0x140
+#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
+#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
+#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
16))
+#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
+#define PCIE_CFG_OFFSET_ADDR   0x1000
+#define PCIE_CFG_HEADER(devfn, bus) \
+   (PCIE_CFG_DEVFN(devfn) | PCIE_CFG_BUS(bus))
+
+#define PCIE_CFG_HEADER_FORCE_BE(devfn, bus, bytes) \
+   (PCIE_CFG_HEADER(devfn, bus) | PCIE_CFG_BYTE_EN(bytes) \
+| PCIE_CFG_FORCE_BYTE_EN)
+
+#define PCIE_RST_CTRL_REG  0x148
+#define PCIE_MAC_RSTB  BIT(0)
+#define PCIE_PHY_RSTB  BIT(1)
+#define PCIE_BRG_RSTB  BIT(2)
+#define PCIE_PE_RSTB   BIT(3)
+
+#define PCIE_MISC_STATUS_REG   0x14C
+#define PCIE_LTR_MSG_RECEIVED  BIT(0)
+#define PCIE_PCIE_MSG_RECEIVED BIT(1)
+
+#define PCIE_LTSSM_STATUS_REG  0x150
+#define PCIE_LTSSM_STATE_MASK  GENMASK(28, 24)
+#define PCIE_LTSSM_STATE(val)  ((val & PCIE_LTSSM_STATE_MASK) >> 24)
+#define PCIE_LTSSM_STATE_L00x10
+#define PCIE_LTSSM_STATE_L1_IDLE   0x13
+#define PCIE_LTSSM_STATE_L2_IDLE   0x14
+
+#define PCIE_LINK_STATUS_REG   0x154
+#define PCIE_PORT_LINKUP   BIT(8)
+
+#define PCIE_MSI_SET_NUM   8
+#define PCIE_MSI_IRQS_PER_SET  32
+#define PCIE_MSI_IRQS_NUM \
+   (PCIE_MSI_IRQS_PER_SET * (PCIE_MSI_SET_NUM))
+
+#define PCIE_INT_ENABLE_REG0x180
+#define PCIE_MSI_MASK  GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
+#define PCIE_MSI_SHIFT 8
+#define PCIE_INTX_SHIFT24
+#define PCIE_INTX_MASK GENMASK(27, 24)
+#define PCIE

[v3,1/3] dt-bindings: PCI: mediatek: Add YAML schema

[Jianjun Wang]

Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 .../bindings/pci/mediatek-pcie-gen3.yaml  | 126 ++
 1 file changed, 126 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
new file mode 100644
index ..c7b5dd132ebd
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gen3 PCIe controller on MediaTek SoCs
+
+maintainers:
+  - Jianjun Wang 
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+oneOf:
+  - const: mediatek,mt8192-pcie
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  ranges:
+minItems: 1
+maxItems: 8
+
+  resets:
+minItems: 1
+maxItems: 2
+
+  reset-names:
+anyOf:
+  - const: mac-rst
+  - const: phy-rst
+
+  clocks:
+maxItems: 5
+
+  assigned-clocks:
+maxItems: 1
+
+  assigned-clock-parents:
+maxItems: 1
+
+  phys:
+maxItems: 1
+
+  '#interrupt-cells':
+const: 1
+
+  interrupt-controller:
+description: Interrupt controller node for handling legacy PCI interrupts.
+type: object
+properties:
+  '#address-cells':
+const: 0
+  '#interrupt-cells':
+const: 1
+  interrupt-controller: true
+
+required:
+  - '#address-cells'
+  - '#interrupt-cells'
+  - interrupt-controller
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - ranges
+  - clocks
+  - '#interrupt-cells'
+  - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+pcie: pcie@1123 {
+compatible = "mediatek,mt8192-pcie";
+device_type = "pci";
+#address-cells = <3>;
+#size-cells = <2>;
+reg = <0x00 0x1123 0x00 0x4000>;
+reg-names = "pcie-mac";
+interrupts = ;
+bus-range = <0x00 0xff>;
+ranges = <0x8200 0x00 0x1200 0x00 0x1200 0x00 
0x100>;
+clocks = <&infracfg 40>,
+ <&infracfg 43>,
+ <&infracfg 97>,
+ <&infracfg 99>,
+ <&infracfg 111>;
+assigned-clocks = <&topckgen 50>;
+assigned-clock-parents = <&topckgen 91>;
+
+phys = <&pciephy>;
+phy-names = "pcie-phy";
+resets = <&infracfg_rst 0>;
+reset-names = "phy-rst";
+
+#interrupt-cells = <1>;
+interrupt-map-mask = <0 0 0 0x7>;
+interrupt-map = <0 0 0 1 &pcie_intc 0>,
+<0 0 0 2 &pcie_intc 1>,
+<0 0 0 3 &pcie_intc 2>,
+<0 0 0 4 &pcie_intc 3>;
+pcie_intc: interrupt-controller {
+  #address-cells = <0>;
+  #interrupt-cells = <1>;
+  interrupt-controller;
+};
+};
+};
-- 
2.25.1

[v3,0/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.

Changes in v3:
1. Remove standard property in binding document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs

Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown

Jianjun Wang (3):
  dt-bindings: PCI: mediatek: Add YAML schema
  PCI: mediatek: Add new generation controller support
  MAINTAINERS: update entry for MediaTek PCIe controller

 .../bindings/pci/mediatek-pcie-gen3.yaml  |  126 ++
 MAINTAINERS   |1 +
 drivers/pci/controller/Kconfig|   14 +
 drivers/pci/controller/Makefile   |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c   | 1024 +
 5 files changed, 1166 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

-- 
2.25.1

[v3,3/3] MAINTAINERS: update entry for MediaTek PCIe controller

[Jianjun Wang]

Add maintainer for MediaTek PCIe controller driver.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..5c6110468526 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13459,6 +13459,7 @@ F:  drivers/pci/controller/dwc/pcie-histb.c
 
 PCIE DRIVER FOR MEDIATEK
 M: Ryder Lee 
+M: Jianjun Wang 
 L: linux-...@vger.kernel.org
 L: linux-media...@lists.infradead.org
 S: Supported
-- 
2.25.1

Re: [v2,2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

On Mon, 2020-09-14 at 08:32 -0600, Rob Herring wrote:
> On Mon, Sep 14, 2020 at 5:07 AM Jianjun Wang  
> wrote:
> >
> > On Fri, 2020-09-11 at 16:44 -0600, Rob Herring wrote:
> > > On Thu, Sep 10, 2020 at 11:45:35AM +0800, Jianjun Wang wrote:
> > > > MediaTek's PCIe host controller has three generation HWs, the new
> > > > generation HW is an individual bridge, it supoorts Gen3 speed and
> > > > up to 256 MSI interrupt numbers for multi-function devices.
> > > >
> > > > Add support for new Gen3 controller which can be found on MT8192.
> > > >
> > > > Signed-off-by: Jianjun Wang 
> > > > Acked-by: Ryder Lee 
> > > > ---
> > > >  drivers/pci/controller/Kconfig  |   14 +
> > > >  drivers/pci/controller/Makefile |1 +
> > > >  drivers/pci/controller/pcie-mediatek-gen3.c | 1076 +++
> > > >  3 files changed, 1091 insertions(+)
> > > >  create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c
> > > >
> > > > diff --git a/drivers/pci/controller/Kconfig 
> > > > b/drivers/pci/controller/Kconfig
> > > > index f18c3725ef80..83daa772595b 100644
> > > > --- a/drivers/pci/controller/Kconfig
> > > > +++ b/drivers/pci/controller/Kconfig
> > > > @@ -239,6 +239,20 @@ config PCIE_MEDIATEK
> > > >   Say Y here if you want to enable PCIe controller support on
> > > >   MediaTek SoCs.
> > > >
> > > > +config PCIE_MEDIATEK_GEN3
> > > > +   tristate "MediaTek GEN3 PCIe controller"
> > > > +   depends on ARCH_MEDIATEK || COMPILE_TEST
> > > > +   depends on OF
> > > > +   depends on PCI_MSI_IRQ_DOMAIN
> > > > +   help
> > > > + Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> > > > + This PCIe controller provides the capable of Gen3, Gen2 and
> > > > + Gen1 speed, and support up to 256 MSI interrupt numbers for
> > > > + multi-function devices.
> > > > +
> > > > + Say Y here if you want to enable Gen3 PCIe controller support on
> > > > + MediaTek SoCs.
> > > > +
> > > >  config PCIE_TANGO_SMP8759
> > > > bool "Tango SMP8759 PCIe controller (DANGEROUS)"
> > > > depends on ARCH_TANGO && PCI_MSI && OF
> > > > diff --git a/drivers/pci/controller/Makefile 
> > > > b/drivers/pci/controller/Makefile
> > > > index bcdbf49ab1e4..9c1b96777597 100644
> > > > --- a/drivers/pci/controller/Makefile
> > > > +++ b/drivers/pci/controller/Makefile
> > > > @@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
> > > >  obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
> > > >  obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
> > > >  obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > > > +obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
> > > >  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> > > >  obj-$(CONFIG_VMD) += vmd.o
> > > >  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
> > > > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > > > new file mode 100644
> > > > index ..f8c8bdf88d33
> > > > --- /dev/null
> > > > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > > > @@ -0,0 +1,1076 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * MediaTek PCIe host controller driver.
> > > > + *
> > > > + * Copyright (c) 2020 MediaTek Inc.
> > > > + * Author: Jianjun Wang 
> > > > + */
> > > > +
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +
> > > > +#include "../pci.h"
> > > > +
> > > > +#define PCIE_SETTING_REG   0x80
> &g

Re: [v2,2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

On Fri, 2020-09-11 at 16:44 -0600, Rob Herring wrote:
> On Thu, Sep 10, 2020 at 11:45:35AM +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supoorts Gen3 speed and
> > up to 256 MSI interrupt numbers for multi-function devices.
> > 
> > Add support for new Gen3 controller which can be found on MT8192.
> > 
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> > ---
> >  drivers/pci/controller/Kconfig  |   14 +
> >  drivers/pci/controller/Makefile |1 +
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 1076 +++
> >  3 files changed, 1091 insertions(+)
> >  create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c
> > 
> > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > index f18c3725ef80..83daa772595b 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -239,6 +239,20 @@ config PCIE_MEDIATEK
> >   Say Y here if you want to enable PCIe controller support on
> >   MediaTek SoCs.
> >  
> > +config PCIE_MEDIATEK_GEN3
> > +   tristate "MediaTek GEN3 PCIe controller"
> > +   depends on ARCH_MEDIATEK || COMPILE_TEST
> > +   depends on OF
> > +   depends on PCI_MSI_IRQ_DOMAIN
> > +   help
> > + Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
> > + This PCIe controller provides the capable of Gen3, Gen2 and
> > + Gen1 speed, and support up to 256 MSI interrupt numbers for
> > + multi-function devices.
> > +
> > + Say Y here if you want to enable Gen3 PCIe controller support on
> > + MediaTek SoCs.
> > +
> >  config PCIE_TANGO_SMP8759
> > bool "Tango SMP8759 PCIe controller (DANGEROUS)"
> > depends on ARCH_TANGO && PCI_MSI && OF
> > diff --git a/drivers/pci/controller/Makefile 
> > b/drivers/pci/controller/Makefile
> > index bcdbf49ab1e4..9c1b96777597 100644
> > --- a/drivers/pci/controller/Makefile
> > +++ b/drivers/pci/controller/Makefile
> > @@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
> >  obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
> >  obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
> >  obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > +obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
> >  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> >  obj-$(CONFIG_VMD) += vmd.o
> >  obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > new file mode 100644
> > index ..f8c8bdf88d33
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -0,0 +1,1076 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * MediaTek PCIe host controller driver.
> > + *
> > + * Copyright (c) 2020 MediaTek Inc.
> > + * Author: Jianjun Wang 
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "../pci.h"
> > +
> > +#define PCIE_SETTING_REG   0x80
> > +#define PCIE_PCI_IDS_1 0x9c
> > +#define PCI_CLASS(class)   (class << 8)
> > +#define PCIE_RC_MODE   BIT(0)
> > +
> > +#define PCIE_CFGNUM_REG0x140
> > +#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
> > +#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
> > +#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
> > 16))
> > +#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
> > +#define PCIE_CFG_OFFSET_ADDR   0x1000
> > +#define PCIE_CFG_HEADER(devfn, bus) \
> > +   (PCIE_CFG_DEVFN(devfn) | PCIE_CFG_BUS(bus))
> > +
> > +#define PCIE_CFG_HEADER_FORCE_BE(devfn, bus, bytes) \
> > +   (PCIE_CFG_HEADER(devfn, bus) | PCIE_CFG_BYTE_EN(bytes) \
> > +| PCIE_CFG_FORCE_BYTE_EN)
> > +
> > +#define PCIE_RST_CTRL_REG  0x148
> > +#define PCIE_MAC_RSTB  BIT(0)
&g

Re: [v2,1/3] dt-bindings: PCI: mediatek: Add YAML schema

[Jianjun Wang]

On Fri, 2020-09-11 at 16:45 -0600, Rob Herring wrote:
> On Thu, Sep 10, 2020 at 11:45:34AM +0800, Jianjun Wang wrote:
> > Add YAML schemas documentation for Gen3 PCIe controller on
> > MediaTek SoCs.
> > 
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> > ---
> >  .../bindings/pci/mediatek-pcie-gen3.yaml  | 130 ++
> >  1 file changed, 130 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
> > b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > new file mode 100644
> > index ..a2dfc0d15d2e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > @@ -0,0 +1,130 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Gen3 PCIe controller on MediaTek SoCs
> > +
> > +maintainers:
> > +  - Jianjun Wang 
> > +
> > +allOf:
> > +  - $ref: /schemas/pci/pci-bus.yaml#
> > +
> > +properties:
> > +  compatible:
> > +oneOf:
> > +  - const: mediatek,gen3-pcie
> 
> Generic compatibles like this should only be a fallback string, not on 
> its own.
> 
> > +  - const: mediatek,mt8192-pcie
> > +
> > +  reg:
> > +maxItems: 1
> > +
> > +  interrupts:
> > +maxItems: 1
> > +
> > +  bus-range:
> > +description: Range of bus numbers associated with this controller.
> 
> Drop this. Standard property.

Thanks for your review, I will drop it in the next version.
> 
> > +
> > +  ranges:
> > +minItems: 1
> > +maxItems: 8
> > +
> > +  resets:
> > +minItems: 1
> > +maxItems: 2
> > +
> > +  reset-names:
> > +anyOf:
> > +  - const: mac-rst
> > +  - const: phy-rst
> > +
> > +  clocks:
> > +maxItems: 5
> > +
> > +  assigned-clocks:
> > +maxItems: 1
> > +
> > +  assigned-clock-parents:
> > +maxItems: 1
> > +
> > +  phys:
> > +maxItems: 1
> > +
> > +  '#interrupt-cells':
> > +const: 1
> > +
> > +  interrupt-controller:
> > +description: Interrupt controller node for handling legacy PCI 
> > interrupts.
> > +type: object
> > +properties:
> > +  '#address-cells':
> > +const: 0
> > +  '#interrupt-cells':
> > +const: 1
> > +  interrupt-controller: true
> > +
> > +required:
> > +  - '#address-cells'
> > +  - '#interrupt-cells'
> > +  - interrupt-controller
> > +
> > +additionalProperties: false
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - ranges
> > +  - clocks
> > +  - '#interrupt-cells'
> > +  - interrupt-controller
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > +  - |
> > +#include 
> > +#include 
> > +
> > +bus {
> > +#address-cells = <2>;
> > +#size-cells = <2>;
> > +
> > +pcie: pcie@1123 {
> > +compatible = "mediatek,mt8192-pcie";
> > +device_type = "pci";
> > +#address-cells = <3>;
> > +#size-cells = <2>;
> > +reg = <0x00 0x1123 0x00 0x4000>;
> > +reg-names = "pcie-mac";
> > +interrupts = ;
> > +bus-range = <0x00 0xff>;
> > +ranges = <0x8200 0x00 0x1200 0x00 0x1200 0x00 
> > 0x100>;
> > +clocks = <&infracfg 40>,
> > + <&infracfg 43>,
> > + <&infracfg 97>,
> > + <&infracfg 99>,
> > + <&infracfg 111>;
> > +assigned-clocks = <&topckgen 50>;
> > +assigned-clock-parents = <&topckgen 91>;
> > +
> > +phys = <&pciephy>;
> > +phy-names = "pcie-phy";
> > +resets = <&infracfg_rst 0>;
> > +reset-names = "phy-rst";
> > +
> > +#interrupt-cells = <1>;
> > +interrupt-map-mask = <0 0 0 0x7>;
> > +interrupt-map = <0 0 0 1 &pcie_intc 0>,
> > +<0 0 0 2 &pcie_intc 1>,
> > +<0 0 0 3 &pcie_intc 2>,
> > +<0 0 0 4 &pcie_intc 3>;
> > +pcie_intc: interrupt-controller {
> > +  #address-cells = <0>;
> > +  #interrupt-cells = <1>;
> > +  interrupt-controller;
> > +};
> > +};
> > +};
> > -- 
> > 2.25.1

Re: [v2,2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

On Fri, 2020-09-11 at 16:33 +0200, Philipp Zabel wrote:
> Hi Jianjun,
> 
> On Thu, 2020-09-10 at 11:45 +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supoorts Gen3 speed and
> > up to 256 MSI interrupt numbers for multi-function devices.
> > 
> > Add support for new Gen3 controller which can be found on MT8192.
> > 
> > Signed-off-by: Jianjun Wang 
> > Acked-by: Ryder Lee 
> > ---
> >  drivers/pci/controller/Kconfig  |   14 +
> >  drivers/pci/controller/Makefile |1 +
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 1076 +++
> >  3 files changed, 1091 insertions(+)
> >  create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c
> > 
> [...]
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > new file mode 100644
> > index ..f8c8bdf88d33
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> [...]
> > +static int mtk_pcie_power_up(struct mtk_pcie_port *port)
> > +{
> > +   struct device *dev = port->dev;
> > +   int err;
> > +
> > +   port->phy_reset = devm_reset_control_get_optional(dev, "phy-rst");
> 
> Please use devm_reset_control_get_optional_exclusive() instead.
> 
> > +   if (PTR_ERR(port->phy_reset) == -EPROBE_DEFER)
> > +   return PTR_ERR(port->phy_reset);
> 
> This should be
> 
>   if (IS_ERR(port->phy_reset))
>   return PTR_ERR(port->phy_reset);
> 
> there is no reason to continue if this throws -ENOMEM, for example.
> 
> regards
> Philipp

Thanks for your review, I will fix it in the next version.

[v2,2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supoorts Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.

Add support for new Gen3 controller which can be found on MT8192.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 drivers/pci/controller/Kconfig  |   14 +
 drivers/pci/controller/Makefile |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c | 1076 +++
 3 files changed, 1091 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index f18c3725ef80..83daa772595b 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -239,6 +239,20 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable PCIe controller support on
  MediaTek SoCs.
 
+config PCIE_MEDIATEK_GEN3
+   tristate "MediaTek GEN3 PCIe controller"
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   depends on OF
+   depends on PCI_MSI_IRQ_DOMAIN
+   help
+ Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
+ This PCIe controller provides the capable of Gen3, Gen2 and
+ Gen1 speed, and support up to 256 MSI interrupt numbers for
+ multi-function devices.
+
+ Say Y here if you want to enable Gen3 PCIe controller support on
+ MediaTek SoCs.
+
 config PCIE_TANGO_SMP8759
bool "Tango SMP8759 PCIe controller (DANGEROUS)"
depends on ARCH_TANGO && PCI_MSI && OF
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index bcdbf49ab1e4..9c1b96777597 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
 obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
new file mode 100644
index ..f8c8bdf88d33
--- /dev/null
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -0,0 +1,1076 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Jianjun Wang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pci.h"
+
+#define PCIE_SETTING_REG   0x80
+#define PCIE_PCI_IDS_1 0x9c
+#define PCI_CLASS(class)   (class << 8)
+#define PCIE_RC_MODE   BIT(0)
+
+#define PCIE_CFGNUM_REG0x140
+#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
+#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
+#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
16))
+#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
+#define PCIE_CFG_OFFSET_ADDR   0x1000
+#define PCIE_CFG_HEADER(devfn, bus) \
+   (PCIE_CFG_DEVFN(devfn) | PCIE_CFG_BUS(bus))
+
+#define PCIE_CFG_HEADER_FORCE_BE(devfn, bus, bytes) \
+   (PCIE_CFG_HEADER(devfn, bus) | PCIE_CFG_BYTE_EN(bytes) \
+| PCIE_CFG_FORCE_BYTE_EN)
+
+#define PCIE_RST_CTRL_REG  0x148
+#define PCIE_MAC_RSTB  BIT(0)
+#define PCIE_PHY_RSTB  BIT(1)
+#define PCIE_BRG_RSTB  BIT(2)
+#define PCIE_PE_RSTB   BIT(3)
+
+#define PCIE_MISC_STATUS_REG   0x14C
+#define PCIE_LTR_MSG_RECEIVED  BIT(0)
+#define PCIE_PCIE_MSG_RECEIVED BIT(1)
+
+#define PCIE_LTSSM_STATUS_REG  0x150
+#define PCIE_LTSSM_STATE_MASK  GENMASK(28, 24)
+#define PCIE_LTSSM_STATE(val)  ((val & PCIE_LTSSM_STATE_MASK) >> 24)
+#define PCIE_LTSSM_STATE_L00x10
+#define PCIE_LTSSM_STATE_L1_IDLE   0x13
+#define PCIE_LTSSM_STATE_L2_IDLE   0x14
+
+#define PCIE_LINK_STATUS_REG   0x154
+#define PCIE_PORT_LINKUP   BIT(8)
+
+#define PCIE_MSI_SET_NUM   8
+#define PCIE_MSI_IRQS_PER_SET  32
+#define PCIE_MSI_IRQS_NUM \
+   (PCIE_MSI_IRQS_PER_SET * (PCIE_MSI_SET_NUM))
+
+#define PCIE_INT_ENABLE_REG0x180
+#define PCIE_MSI_MASK  GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
+#define PCIE_MSI_SHIFT 8
+#define PCIE_INTX_SHIFT24
+#define PCIE_INTX_MASK GENMASK(27, 24)
+#define PCIE

[v2,3/3] MAINTAINERS: update entry for MediaTek PCIe controller

[Jianjun Wang]

Add maintainer for MediaTek PCIe controller driver.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..5c6110468526 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13459,6 +13459,7 @@ F:  drivers/pci/controller/dwc/pcie-histb.c
 
 PCIE DRIVER FOR MEDIATEK
 M: Ryder Lee 
+M: Jianjun Wang 
 L: linux-...@vger.kernel.org
 L: linux-media...@lists.infradead.org
 S: Supported
-- 
2.25.1

[v2,1/3] dt-bindings: PCI: mediatek: Add YAML schema

[Jianjun Wang]

Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.

Signed-off-by: Jianjun Wang 
Acked-by: Ryder Lee 
---
 .../bindings/pci/mediatek-pcie-gen3.yaml  | 130 ++
 1 file changed, 130 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
new file mode 100644
index ..a2dfc0d15d2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gen3 PCIe controller on MediaTek SoCs
+
+maintainers:
+  - Jianjun Wang 
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+oneOf:
+  - const: mediatek,gen3-pcie
+  - const: mediatek,mt8192-pcie
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  bus-range:
+description: Range of bus numbers associated with this controller.
+
+  ranges:
+minItems: 1
+maxItems: 8
+
+  resets:
+minItems: 1
+maxItems: 2
+
+  reset-names:
+anyOf:
+  - const: mac-rst
+  - const: phy-rst
+
+  clocks:
+maxItems: 5
+
+  assigned-clocks:
+maxItems: 1
+
+  assigned-clock-parents:
+maxItems: 1
+
+  phys:
+maxItems: 1
+
+  '#interrupt-cells':
+const: 1
+
+  interrupt-controller:
+description: Interrupt controller node for handling legacy PCI interrupts.
+type: object
+properties:
+  '#address-cells':
+const: 0
+  '#interrupt-cells':
+const: 1
+  interrupt-controller: true
+
+required:
+  - '#address-cells'
+  - '#interrupt-cells'
+  - interrupt-controller
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - ranges
+  - clocks
+  - '#interrupt-cells'
+  - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+pcie: pcie@1123 {
+compatible = "mediatek,mt8192-pcie";
+device_type = "pci";
+#address-cells = <3>;
+#size-cells = <2>;
+reg = <0x00 0x1123 0x00 0x4000>;
+reg-names = "pcie-mac";
+interrupts = ;
+bus-range = <0x00 0xff>;
+ranges = <0x8200 0x00 0x1200 0x00 0x1200 0x00 
0x100>;
+clocks = <&infracfg 40>,
+ <&infracfg 43>,
+ <&infracfg 97>,
+ <&infracfg 99>,
+ <&infracfg 111>;
+assigned-clocks = <&topckgen 50>;
+assigned-clock-parents = <&topckgen 91>;
+
+phys = <&pciephy>;
+phy-names = "pcie-phy";
+resets = <&infracfg_rst 0>;
+reset-names = "phy-rst";
+
+#interrupt-cells = <1>;
+interrupt-map-mask = <0 0 0 0x7>;
+interrupt-map = <0 0 0 1 &pcie_intc 0>,
+<0 0 0 2 &pcie_intc 1>,
+<0 0 0 3 &pcie_intc 2>,
+<0 0 0 4 &pcie_intc 3>;
+pcie_intc: interrupt-controller {
+  #address-cells = <0>;
+  #interrupt-cells = <1>;
+  interrupt-controller;
+};
+};
+};
-- 
2.25.1

[v2,0/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.

Change in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown

Jianjun Wang (3):
  dt-bindings: PCI: mediatek: Add YAML schema
  PCI: mediatek: Add new generation controller support
  MAINTAINERS: update entry for MediaTek PCIe controller

 .../bindings/pci/mediatek-pcie-gen3.yaml  |  130 ++
 MAINTAINERS   |1 +
 drivers/pci/controller/Kconfig|   14 +
 drivers/pci/controller/Makefile   |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c   | 1076 +
 5 files changed, 1222 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

-- 
2.25.1

Re: [v1,1/3] dt-bindings: Add YAML schemas for Gen3 PCIe controller

[Jianjun Wang]

On Tue, 2020-09-08 at 14:21 -0600, Rob Herring wrote:
> On Mon, Sep 07, 2020 at 08:08:50PM +0800, Jianjun Wang wrote:
> > Add YAML schemas documentation for Gen3 PCIe controller on
> > MediaTek SoCs.
> 
> dt-bindings: PCI: mediatek: ... for the subject.
> 
> > 
> > Acked-by: Ryder Lee 
> > Signed-off-by: Jianjun Wang 
> > ---
> >  .../bindings/pci/mediatek-pcie-gen3.yaml  | 158 ++
> >  1 file changed, 158 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
> > b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > new file mode 100644
> > index ..108d29259c05
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > @@ -0,0 +1,158 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Gen3 PCIe controller on MediaTek SoCs
> > +
> > +maintainers:
> > +  - Jianjun Wang 
> > +
> > +allOf:
> > +  - $ref: /schemas/pci/pci-bus.yaml#
> > +
> > +properties:
> > +  compatible:
> > +oneOf:
> > +  - const: mediatek,gen3-pcie
> > +  - const: mediatek,mt8192-pcie
> > +
> 
> > +  device_type:
> > +const: pci
> > +
> > +  "#address-cells":
> > +const: 3
> > +
> > +  "#size-cells":
> > +const: 2
> 
> Can drop these 3. Already in pci-bus.yaml.
> 
> > +
> > +  reg:
> > +items:
> > +  - description: Controller control and status registers.
> 
> Just 'maxItems: 1'. The description doesn't add any value.
> 
> > +
> > +  reg-names:
> > +items:
> > +  - const: pcie-mac
> 
> Don't really need a name here.
> 
> > +
> > +  interrupts:
> > +maxItems: 1
> > +
> > +  bus-range:
> > +description: Range of bus numbers associated with this controller.
> > +
> > +  ranges:
> > +minItems: 1
> > +maxItems: 8
> > +
> > +  resets:
> > +minItems: 1
> > +maxItems: 2
> > +
> > +  reset-names:
> > +anyOf:
> > +  - const: mac-rst
> > +  - const: phy-rst
> 
> Doesn't the PHY's reset belong in the PHY node?

There are some cases that we don't need the PHY driver, but for the
reason of power saving, the HW still remain the PHY's reset in infra
domain and it will be asserted before kernel stage, so we still need to
release this reset in the PCIe MAC driver.
> 
> > +
> > +  clocks:
> > +maxItems: 5
> > +
> > +  assigned-clocks:
> > +maxItems: 1
> > +
> > +  assigned-clock-parents:
> > +maxItems: 1
> > +
> > +  phys:
> > +maxItems: 1
> > +
> > +  phy-names:
> > +const: pcie-phy
> 
> Not really a useful name and there's only one. Please drop.
> 
> > +
> > +  '#interrupt-cells':
> > +const: 1
> > +
> 
> > +  interrupt-map-mask:
> > +description: Standard PCI IRQ mapping properties.
> > +
> > +  interrupt-map:
> > +description: Standard PCI IRQ mapping properties.
> 
> Can drop these.
> 
> > +
> > +  legacy-interrupt-controller:
> 
> Just 'interrupt-controller'
> 
> And don't copy the same bug of using 'of_get_next_child'. You should get 
> the child node by name.
> 
> > +description: Interrupt controller node for handling legacy PCI 
> > interrupts.
> > +type: object
> > +properties:
> > +  "#address-cells":
> > +const: 0
> > +  "#interrupt-cells":
> > +const: 1
> > +  interrupt-controller: true
> > +
> > +required:
> > +  - "#address-cells"
> > +  - "#interrupt-cells"
> > +  - interrupt-controller
> 
>additionalProperties: false
> 
> > +
> > +required:
> > +  - compatible
> 
> > +  - device_type
> > +  - "#address-cells"
> > +  - "#size-cells"
> 
> Don't need these, pci-bus.yaml already requires them.
> 
> > +  - reg
> > +  - reg-names
> > +  - bus-range
> 
> If the range is

Re: [v1,1/3] dt-bindings: Add YAML schemas for Gen3 PCIe controller

[Jianjun Wang]

On Tue, 2020-09-08 at 15:04 -0500, Bjorn Helgaas wrote:
> On Mon, Sep 07, 2020 at 08:08:50PM +0800, Jianjun Wang wrote:
> > Add YAML schemas documentation for Gen3 PCIe controller on
> > MediaTek SoCs.
> 
> Please mention "mediatek" in the subject line so "git log --oneline"
> is more useful.
> 
> The convention (not universally observed) seems to be something like:
> 
>   dt-bindings: PCI: : Add YAML schema

Thanks for your review, I will fix it in the next version.

Re: [v1,1/3] dt-bindings: Add YAML schemas for Gen3 PCIe controller

[Jianjun Wang]

On Tue, 2020-09-08 at 13:50 -0600, Rob Herring wrote:
> On Mon, 07 Sep 2020 20:08:50 +0800, Jianjun Wang wrote:
> > Add YAML schemas documentation for Gen3 PCIe controller on
> > MediaTek SoCs.
> > 
> > Acked-by: Ryder Lee 
> > Signed-off-by: Jianjun Wang 
> > ---
> >  .../bindings/pci/mediatek-pcie-gen3.yaml  | 158 ++
> >  1 file changed, 158 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > 
> 
> 
> My bot found errors running 'make dt_binding_check' on your patch:
> 
> Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.example.dts:55.56-59.19:
>  Warning (pci_device_reg): 
> /example-0/bus/pcie@1123/legacy-interrupt-controller: missing PCI reg 
> property
> 
> 
> See https://patchwork.ozlabs.org/patch/1359119
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure dt-schema is up to date:
> 
> pip3 install git+https://github.com/devicetree-org/dt-schema.git@master 
> --upgrade
> 
> Please check and re-submit.
> 

Yes, I have already found this warning message, but I'm confused with
how to add this reg property, since the interrupt-controller has inherit
the pci device type but does not have its own registers.

Could you please tell me how to fix this error, or which docs can I
refer to?

Thanks.

[v1,0/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.

Jianjun Wang (3):
  dt-bindings: Add YAML schemas for Gen3 PCIe controller
  PCI: mediatek: Add new generation controller support
  MAINTAINERS: update entry for MediaTek PCIe controller

 .../bindings/pci/mediatek-pcie-gen3.yaml  |  158 +++
 MAINTAINERS   |1 +
 drivers/pci/controller/Kconfig|   14 +
 drivers/pci/controller/Makefile   |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c   | 1063 +
 5 files changed, 1237 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

-- 
2.25.1

[v1,2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supoorts Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.

Add support for new Gen3 controller which can be found on MT8192.

Acked-by: Ryder Lee 
Signed-off-by: Jianjun Wang 
---
 drivers/pci/controller/Kconfig  |   14 +
 drivers/pci/controller/Makefile |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c | 1063 +++
 3 files changed, 1078 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index f18c3725ef80..83daa772595b 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -239,6 +239,20 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable PCIe controller support on
  MediaTek SoCs.
 
+config PCIE_MEDIATEK_GEN3
+   tristate "MediaTek GEN3 PCIe controller"
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   depends on OF
+   depends on PCI_MSI_IRQ_DOMAIN
+   help
+ Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
+ This PCIe controller provides the capable of Gen3, Gen2 and
+ Gen1 speed, and support up to 256 MSI interrupt numbers for
+ multi-function devices.
+
+ Say Y here if you want to enable Gen3 PCIe controller support on
+ MediaTek SoCs.
+
 config PCIE_TANGO_SMP8759
bool "Tango SMP8759 PCIe controller (DANGEROUS)"
depends on ARCH_TANGO && PCI_MSI && OF
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index bcdbf49ab1e4..9c1b96777597 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
 obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
new file mode 100644
index ..b76baeac3b98
--- /dev/null
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -0,0 +1,1063 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Jianjun Wang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pci.h"
+
+#define PCIE_SETTING_REG   0x80
+#define PCIE_PCI_IDS_1 0x9c
+#define PCI_CLASS(class)   (class << 8)
+#define PCIE_RC_MODE   BIT(0)
+
+#define PCIE_CFGNUM_REG0x140
+#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
+#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
+#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
16))
+#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
+#define PCIE_CFG_OFFSET_ADDR   0x1000
+#define PCIE_CFG_HEADER(devfn, bus) \
+   (PCIE_CFG_DEVFN(devfn) | PCIE_CFG_BUS(bus))
+
+#define PCIE_CFG_HEADER_FORCE_BE(devfn, bus, bytes) \
+   (PCIE_CFG_HEADER(devfn, bus) | PCIE_CFG_BYTE_EN(bytes) \
+| PCIE_CFG_FORCE_BYTE_EN)
+
+#define PCIE_RST_CTRL_REG  0x148
+#define PCIE_MAC_RSTB  BIT(0)
+#define PCIE_PHY_RSTB  BIT(1)
+#define PCIE_BRG_RSTB  BIT(2)
+#define PCIE_PE_RSTB   BIT(3)
+
+#define PCIE_MISC_STATUS_REG   0x14C
+#define PCIE_LTR_MSG_RECEIVED  BIT(0)
+#define PCIE_PCIE_MSG_RECEIVED BIT(1)
+
+#define PCIE_LTSSM_STATUS_REG  0x150
+#define PCIE_LTSSM_STATE_MASK  GENMASK(28, 24)
+#define PCIE_LTSSM_STATE(val)  ((val & PCIE_LTSSM_STATE_MASK) >> 24)
+#define PCIE_LTSSM_STATE_L00x10
+#define PCIE_LTSSM_STATE_L1_IDLE   0x13
+#define PCIE_LTSSM_STATE_L2_IDLE   0x14
+
+#define PCIE_LINK_STATUS_REG   0x154
+#define PCIE_PORT_LINKUP   BIT(8)
+
+#define PCIE_MSI_SET_NUM   8
+#define PCIE_MSI_IRQS_PER_SET  32
+#define PCIE_MSI_IRQS_NUM \
+   (PCIE_MSI_IRQS_PER_SET * (PCIE_MSI_SET_NUM))
+
+#define PCIE_INT_ENABLE_REG0x180
+#define PCIE_MSI_MASK  GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
+#define PCIE_MSI_SHIFT 8
+#define PCIE_INTX_SHIFT24
+#define PCIE_INTX_MASK GENMASK(27, 24)
+#define PCIE

[v1,3/3] MAINTAINERS: update entry for MediaTek PCIe controller

[Jianjun Wang]

Add maintainer for MediaTek PCIe controller driver.

Acked-by: Ryder Lee 
Signed-off-by: Jianjun Wang 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..5c6110468526 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13459,6 +13459,7 @@ F:  drivers/pci/controller/dwc/pcie-histb.c
 
 PCIE DRIVER FOR MEDIATEK
 M: Ryder Lee 
+M: Jianjun Wang 
 L: linux-...@vger.kernel.org
 L: linux-media...@lists.infradead.org
 S: Supported
-- 
2.25.1

[v1,1/3] dt-bindings: Add YAML schemas for Gen3 PCIe controller

[Jianjun Wang]

Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.

Acked-by: Ryder Lee 
Signed-off-by: Jianjun Wang 
---
 .../bindings/pci/mediatek-pcie-gen3.yaml  | 158 ++
 1 file changed, 158 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
new file mode 100644
index ..108d29259c05
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -0,0 +1,158 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gen3 PCIe controller on MediaTek SoCs
+
+maintainers:
+  - Jianjun Wang 
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+oneOf:
+  - const: mediatek,gen3-pcie
+  - const: mediatek,mt8192-pcie
+
+  device_type:
+const: pci
+
+  "#address-cells":
+const: 3
+
+  "#size-cells":
+const: 2
+
+  reg:
+items:
+  - description: Controller control and status registers.
+
+  reg-names:
+items:
+  - const: pcie-mac
+
+  interrupts:
+maxItems: 1
+
+  bus-range:
+description: Range of bus numbers associated with this controller.
+
+  ranges:
+minItems: 1
+maxItems: 8
+
+  resets:
+minItems: 1
+maxItems: 2
+
+  reset-names:
+anyOf:
+  - const: mac-rst
+  - const: phy-rst
+
+  clocks:
+maxItems: 5
+
+  assigned-clocks:
+maxItems: 1
+
+  assigned-clock-parents:
+maxItems: 1
+
+  phys:
+maxItems: 1
+
+  phy-names:
+const: pcie-phy
+
+  '#interrupt-cells':
+const: 1
+
+  interrupt-map-mask:
+description: Standard PCI IRQ mapping properties.
+
+  interrupt-map:
+description: Standard PCI IRQ mapping properties.
+
+  legacy-interrupt-controller:
+description: Interrupt controller node for handling legacy PCI interrupts.
+type: object
+properties:
+  "#address-cells":
+const: 0
+  "#interrupt-cells":
+const: 1
+  interrupt-controller: true
+
+required:
+  - "#address-cells"
+  - "#interrupt-cells"
+  - interrupt-controller
+
+required:
+  - compatible
+  - device_type
+  - "#address-cells"
+  - "#size-cells"
+  - reg
+  - reg-names
+  - bus-range
+  - interrupts
+  - ranges
+  - clocks
+  - '#interrupt-cells'
+  - interrupt-map
+  - interrupt-map-mask
+  - legacy-interrupt-controller
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+pcie: pcie@1123 {
+compatible = "mediatek,mt8192-pcie";
+device_type = "pci";
+#address-cells = <3>;
+#size-cells = <2>;
+reg = <0x00 0x1123 0x00 0x4000>;
+reg-names = "pcie-mac";
+interrupts = ;
+bus-range = <0x00 0xff>;
+ranges = <0x8200 0x00 0x1200 0x00 0x1200 0x00 
0x100>;
+clocks = <&infracfg 40>,
+ <&infracfg 43>,
+ <&infracfg 97>,
+ <&infracfg 99>,
+ <&infracfg 111>;
+assigned-clocks = <&topckgen 50>;
+assigned-clock-parents = <&topckgen 91>;
+
+phys = <&pciephy>;
+phy-names = "pcie-phy";
+resets = <&infracfg_rst 0>;
+reset-names = "phy-rst";
+
+#interrupt-cells = <1>;
+interrupt-map-mask = <0 0 0 0x7>;
+interrupt-map = <0 0 0 1 &pcie_intc 0>,
+<0 0 0 2 &pcie_intc 1>,
+<0 0 0 3 &pcie_intc 2>,
+<0 0 0 4 &pcie_intc 3>;
+pcie_intc: legacy-interrupt-controller {
+  #address-cells = <0>;
+  #interrupt-cells = <1>;
+  interrupt-controller;
+};
+};
+};
-- 
2.25.1

[PATCH 2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supoorts Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.

Add support for new Gen3 controller which can be found on MT8192.

Signed-off-by: Jianjun Wang 
---
 drivers/pci/controller/Kconfig  |   14 +
 drivers/pci/controller/Makefile |1 +
 drivers/pci/controller/pcie-mediatek-gen3.c | 1063 +++
 3 files changed, 1078 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index f18c3725ef80..83daa772595b 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -239,6 +239,20 @@ config PCIE_MEDIATEK
  Say Y here if you want to enable PCIe controller support on
  MediaTek SoCs.
 
+config PCIE_MEDIATEK_GEN3
+   tristate "MediaTek GEN3 PCIe controller"
+   depends on ARCH_MEDIATEK || COMPILE_TEST
+   depends on OF
+   depends on PCI_MSI_IRQ_DOMAIN
+   help
+ Adds support for PCIe Gen3 MAC controller for MediaTek SoCs.
+ This PCIe controller provides the capable of Gen3, Gen2 and
+ Gen1 speed, and support up to 256 MSI interrupt numbers for
+ multi-function devices.
+
+ Say Y here if you want to enable Gen3 PCIe controller support on
+ MediaTek SoCs.
+
 config PCIE_TANGO_SMP8759
bool "Tango SMP8759 PCIe controller (DANGEROUS)"
depends on ARCH_TANGO && PCI_MSI && OF
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index bcdbf49ab1e4..9c1b96777597 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
 obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
 obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
+obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
 obj-$(CONFIG_VMD) += vmd.o
 obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c 
b/drivers/pci/controller/pcie-mediatek-gen3.c
new file mode 100644
index ..b76baeac3b98
--- /dev/null
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -0,0 +1,1063 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Jianjun Wang 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pci.h"
+
+#define PCIE_SETTING_REG   0x80
+#define PCIE_PCI_IDS_1 0x9c
+#define PCI_CLASS(class)   (class << 8)
+#define PCIE_RC_MODE   BIT(0)
+
+#define PCIE_CFGNUM_REG0x140
+#define PCIE_CFG_DEVFN(devfn)  ((devfn) & GENMASK(7, 0))
+#define PCIE_CFG_BUS(bus)  (((bus) << 8) & GENMASK(15, 8))
+#define PCIE_CFG_BYTE_EN(bytes)(((bytes) << 16) & GENMASK(19, 
16))
+#define PCIE_CFG_FORCE_BYTE_EN BIT(20)
+#define PCIE_CFG_OFFSET_ADDR   0x1000
+#define PCIE_CFG_HEADER(devfn, bus) \
+   (PCIE_CFG_DEVFN(devfn) | PCIE_CFG_BUS(bus))
+
+#define PCIE_CFG_HEADER_FORCE_BE(devfn, bus, bytes) \
+   (PCIE_CFG_HEADER(devfn, bus) | PCIE_CFG_BYTE_EN(bytes) \
+| PCIE_CFG_FORCE_BYTE_EN)
+
+#define PCIE_RST_CTRL_REG  0x148
+#define PCIE_MAC_RSTB  BIT(0)
+#define PCIE_PHY_RSTB  BIT(1)
+#define PCIE_BRG_RSTB  BIT(2)
+#define PCIE_PE_RSTB   BIT(3)
+
+#define PCIE_MISC_STATUS_REG   0x14C
+#define PCIE_LTR_MSG_RECEIVED  BIT(0)
+#define PCIE_PCIE_MSG_RECEIVED BIT(1)
+
+#define PCIE_LTSSM_STATUS_REG  0x150
+#define PCIE_LTSSM_STATE_MASK  GENMASK(28, 24)
+#define PCIE_LTSSM_STATE(val)  ((val & PCIE_LTSSM_STATE_MASK) >> 24)
+#define PCIE_LTSSM_STATE_L00x10
+#define PCIE_LTSSM_STATE_L1_IDLE   0x13
+#define PCIE_LTSSM_STATE_L2_IDLE   0x14
+
+#define PCIE_LINK_STATUS_REG   0x154
+#define PCIE_PORT_LINKUP   BIT(8)
+
+#define PCIE_MSI_SET_NUM   8
+#define PCIE_MSI_IRQS_PER_SET  32
+#define PCIE_MSI_IRQS_NUM \
+   (PCIE_MSI_IRQS_PER_SET * (PCIE_MSI_SET_NUM))
+
+#define PCIE_INT_ENABLE_REG0x180
+#define PCIE_MSI_MASK  GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
+#define PCIE_MSI_SHIFT 8
+#define PCIE_INTX_SHIFT24
+#define PCIE_INTX_MASK GENMASK(27, 24)
+#define PCIE_MSG_MASK

[PATCH 1/3] dt-bindings: Add YAML schemas for Gen3 PCIe controller

[Jianjun Wang]

Add YAML schemas documentation for Gen3 PCIe controller on
MediaTek SoCs.

Change-Id: I2a022c7291c7e7e161b3a7e8bce28781e0f09b90
Signed-off-by: Jianjun Wang 
---
 .../bindings/pci/mediatek-pcie-gen3.yaml  | 158 ++
 1 file changed, 158 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml 
b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
new file mode 100644
index ..108d29259c05
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -0,0 +1,158 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Gen3 PCIe controller on MediaTek SoCs
+
+maintainers:
+  - Jianjun Wang 
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+oneOf:
+  - const: mediatek,gen3-pcie
+  - const: mediatek,mt8192-pcie
+
+  device_type:
+const: pci
+
+  "#address-cells":
+const: 3
+
+  "#size-cells":
+const: 2
+
+  reg:
+items:
+  - description: Controller control and status registers.
+
+  reg-names:
+items:
+  - const: pcie-mac
+
+  interrupts:
+maxItems: 1
+
+  bus-range:
+description: Range of bus numbers associated with this controller.
+
+  ranges:
+minItems: 1
+maxItems: 8
+
+  resets:
+minItems: 1
+maxItems: 2
+
+  reset-names:
+anyOf:
+  - const: mac-rst
+  - const: phy-rst
+
+  clocks:
+maxItems: 5
+
+  assigned-clocks:
+maxItems: 1
+
+  assigned-clock-parents:
+maxItems: 1
+
+  phys:
+maxItems: 1
+
+  phy-names:
+const: pcie-phy
+
+  '#interrupt-cells':
+const: 1
+
+  interrupt-map-mask:
+description: Standard PCI IRQ mapping properties.
+
+  interrupt-map:
+description: Standard PCI IRQ mapping properties.
+
+  legacy-interrupt-controller:
+description: Interrupt controller node for handling legacy PCI interrupts.
+type: object
+properties:
+  "#address-cells":
+const: 0
+  "#interrupt-cells":
+const: 1
+  interrupt-controller: true
+
+required:
+  - "#address-cells"
+  - "#interrupt-cells"
+  - interrupt-controller
+
+required:
+  - compatible
+  - device_type
+  - "#address-cells"
+  - "#size-cells"
+  - reg
+  - reg-names
+  - bus-range
+  - interrupts
+  - ranges
+  - clocks
+  - '#interrupt-cells'
+  - interrupt-map
+  - interrupt-map-mask
+  - legacy-interrupt-controller
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+
+pcie: pcie@1123 {
+compatible = "mediatek,mt8192-pcie";
+device_type = "pci";
+#address-cells = <3>;
+#size-cells = <2>;
+reg = <0x00 0x1123 0x00 0x4000>;
+reg-names = "pcie-mac";
+interrupts = ;
+bus-range = <0x00 0xff>;
+ranges = <0x8200 0x00 0x1200 0x00 0x1200 0x00 
0x100>;
+clocks = <&infracfg 40>,
+ <&infracfg 43>,
+ <&infracfg 97>,
+ <&infracfg 99>,
+ <&infracfg 111>;
+assigned-clocks = <&topckgen 50>;
+assigned-clock-parents = <&topckgen 91>;
+
+phys = <&pciephy>;
+phy-names = "pcie-phy";
+resets = <&infracfg_rst 0>;
+reset-names = "phy-rst";
+
+#interrupt-cells = <1>;
+interrupt-map-mask = <0 0 0 0x7>;
+interrupt-map = <0 0 0 1 &pcie_intc 0>,
+<0 0 0 2 &pcie_intc 1>,
+<0 0 0 3 &pcie_intc 2>,
+<0 0 0 4 &pcie_intc 3>;
+pcie_intc: legacy-interrupt-controller {
+  #address-cells = <0>;
+  #interrupt-cells = <1>;
+  interrupt-controller;
+};
+};
+};
-- 
2.18.0

[PATCH 3/3] MAINTAINERS: update entry for MediaTek PCIe controller

[Jianjun Wang]

Add maintainer for MediaTek PCIe controller driver.

Signed-off-by: Jianjun Wang 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..5c6110468526 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13459,6 +13459,7 @@ F:  drivers/pci/controller/dwc/pcie-histb.c
 
 PCIE DRIVER FOR MEDIATEK
 M: Ryder Lee 
+M: Jianjun Wang 
 L: linux-...@vger.kernel.org
 L: linux-media...@lists.infradead.org
 S: Supported
-- 
2.18.0

Re: [v2,2/2] PCI: mediatek: Add controller support for MT7629

[Jianjun Wang]

On Fri, 2019-06-28 at 15:34 +0800, Jianjun Wang wrote:
> MT7629 is an ARM platform SoC which has the same PCIe IP with MT7622.
> 
> The HW default value of its Device ID is invalid, fix its Device ID to
> match the hardware implementation.
> 
> Acked-by: Ryder Lee 
> Signed-off-by: Jianjun Wang 
> ---
>  drivers/pci/controller/pcie-mediatek.c | 18 ++
>  include/linux/pci_ids.h|  1 +
>  2 files changed, 19 insertions(+)
> 
> diff --git a/drivers/pci/controller/pcie-mediatek.c 
> b/drivers/pci/controller/pcie-mediatek.c
> index 80601e1b939e..e5e6740b635d 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
> @@ -73,6 +73,7 @@
>  #define PCIE_MSI_VECTOR  0x0c0
>  
>  #define PCIE_CONF_VEND_ID0x100
> +#define PCIE_CONF_DEVICE_ID  0x102
>  #define PCIE_CONF_CLASS_ID   0x106
>  
>  #define PCIE_INT_MASK0x420
> @@ -141,12 +142,16 @@ struct mtk_pcie_port;
>  /**
>   * struct mtk_pcie_soc - differentiate between host generations
>   * @need_fix_class_id: whether this host's class ID needed to be fixed or not
> + * @need_fix_device_id: whether this host's Device ID needed to be fixed or 
> not
> + * @device_id: Device ID which this host need to be fixed
>   * @ops: pointer to configuration access functions
>   * @startup: pointer to controller setting functions
>   * @setup_irq: pointer to initialize IRQ functions
>   */
>  struct mtk_pcie_soc {
>   bool need_fix_class_id;
> + bool need_fix_device_id;
> + unsigned int device_id;
>   struct pci_ops *ops;
>   int (*startup)(struct mtk_pcie_port *port);
>   int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
> @@ -696,6 +701,9 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port 
> *port)
>   writew(val, port->base + PCIE_CONF_CLASS_ID);
>   }
>  
> + if (soc->need_fix_device_id)
> + writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
> +
>   /* 100ms timeout value should be enough for Gen1/2 training */
>   err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
>!!(val & PCIE_PORT_LINKUP_V2), 20,
> @@ -1216,11 +1224,21 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 
> = {
>   .setup_irq = mtk_pcie_setup_irq,
>  };
>  
> +static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
> + .need_fix_class_id = true,
> + .need_fix_device_id = true,
> + .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
> + .ops = &mtk_pcie_ops_v2,
> + .startup = mtk_pcie_startup_port_v2,
> + .setup_irq = mtk_pcie_setup_irq,
> +};
> +
>  static const struct of_device_id mtk_pcie_ids[] = {
>   { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
>   { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
>   { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
>   { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
> + { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
>   {},
>  };
>  
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 70e86148cb1e..aa32962759b2 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -2131,6 +2131,7 @@
>  #define PCI_VENDOR_ID_MYRICOM0x14c1
>  
>  #define PCI_VENDOR_ID_MEDIATEK   0x14c3
> +#define PCI_DEVICE_ID_MEDIATEK_7629  0x7629
>  
>  #define PCI_VENDOR_ID_TITAN  0x14D2
>  #define PCI_DEVICE_ID_TITAN_010L 0x8001

Hi Bjorn & Lorenzo,

Is this patch ok or is there anything I need to fixed?

Thanks.

[v2,1/2] dt-bindings: PCI: Add support for MT7629

[Jianjun Wang]

MT7629 is an ARM platform Soc which has the same PCIe IP with MT7622.

Reviewed-by: Rob Herring 
Acked-by: Ryder Lee 
Signed-off-by: Jianjun Wang 
---
 Documentation/devicetree/bindings/pci/mediatek-pcie.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt 
b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
index 92437a366e5f..7468d666763a 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
@@ -6,6 +6,7 @@ Required properties:
"mediatek,mt2712-pcie"
"mediatek,mt7622-pcie"
"mediatek,mt7623-pcie"
+   "mediatek,mt7629-pcie"
 - device_type: Must be "pci"
 - reg: Base addresses and lengths of the PCIe subsys and root ports.
 - reg-names: Names of the above areas to use during resource lookup.
-- 
2.18.0

[v2,2/2] PCI: mediatek: Add controller support for MT7629

[Jianjun Wang]

MT7629 is an ARM platform SoC which has the same PCIe IP with MT7622.

The HW default value of its Device ID is invalid, fix its Device ID to
match the hardware implementation.

Acked-by: Ryder Lee 
Signed-off-by: Jianjun Wang 
---
 drivers/pci/controller/pcie-mediatek.c | 18 ++
 include/linux/pci_ids.h|  1 +
 2 files changed, 19 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek.c 
b/drivers/pci/controller/pcie-mediatek.c
index 80601e1b939e..e5e6740b635d 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -73,6 +73,7 @@
 #define PCIE_MSI_VECTOR0x0c0
 
 #define PCIE_CONF_VEND_ID  0x100
+#define PCIE_CONF_DEVICE_ID0x102
 #define PCIE_CONF_CLASS_ID 0x106
 
 #define PCIE_INT_MASK  0x420
@@ -141,12 +142,16 @@ struct mtk_pcie_port;
 /**
  * struct mtk_pcie_soc - differentiate between host generations
  * @need_fix_class_id: whether this host's class ID needed to be fixed or not
+ * @need_fix_device_id: whether this host's Device ID needed to be fixed or not
+ * @device_id: Device ID which this host need to be fixed
  * @ops: pointer to configuration access functions
  * @startup: pointer to controller setting functions
  * @setup_irq: pointer to initialize IRQ functions
  */
 struct mtk_pcie_soc {
bool need_fix_class_id;
+   bool need_fix_device_id;
+   unsigned int device_id;
struct pci_ops *ops;
int (*startup)(struct mtk_pcie_port *port);
int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
@@ -696,6 +701,9 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port 
*port)
writew(val, port->base + PCIE_CONF_CLASS_ID);
}
 
+   if (soc->need_fix_device_id)
+   writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
+
/* 100ms timeout value should be enough for Gen1/2 training */
err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
 !!(val & PCIE_PORT_LINKUP_V2), 20,
@@ -1216,11 +1224,21 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
.setup_irq = mtk_pcie_setup_irq,
 };
 
+static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
+   .need_fix_class_id = true,
+   .need_fix_device_id = true,
+   .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
+   .ops = &mtk_pcie_ops_v2,
+   .startup = mtk_pcie_startup_port_v2,
+   .setup_irq = mtk_pcie_setup_irq,
+};
+
 static const struct of_device_id mtk_pcie_ids[] = {
{ .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
{ .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
{ .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
{ .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
+   { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
{},
 };
 
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 70e86148cb1e..aa32962759b2 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2131,6 +2131,7 @@
 #define PCI_VENDOR_ID_MYRICOM  0x14c1
 
 #define PCI_VENDOR_ID_MEDIATEK 0x14c3
+#define PCI_DEVICE_ID_MEDIATEK_76290x7629
 
 #define PCI_VENDOR_ID_TITAN0x14D2
 #define PCI_DEVICE_ID_TITAN_010L   0x8001
-- 
2.18.0