[PATCH v3] pinctrl: rockchip: do coding style for mux route struct

[Jianqun Xu]

The mux route tables take many lines for each SoC, and it will be more
instances for newly SoC, that makes the file size increase larger.

This patch only do coding style for mux route struct, by adding a new
definition and replace the structs by script which supplied by
huang...@rock-chips.com

sed -i -e "
/static struct rockchip_mux_route_data /bcheck
b
:append-next-line
N
:check
/^[^;]*$/bappend-next-line
s/[[:blank:]]*.bank_num = \([[:digit:]]*,\)\n/\tRK_MUXROUTE_SAME(\1/g
s/[[:blank:]]*.pin =[[:blank:]]*0,\n/ RK_PA0,/g
s/[[:blank:]]*.pin =[[:blank:]]*1,\n/ RK_PA1,/g
s/[[:blank:]]*.pin =[[:blank:]]*2,\n/ RK_PA2,/g
s/[[:blank:]]*.pin =[[:blank:]]*3,\n/ RK_PA3,/g
s/[[:blank:]]*.pin =[[:blank:]]*4,\n/ RK_PA4,/g
s/[[:blank:]]*.pin =[[:blank:]]*5,\n/ RK_PA5,/g
s/[[:blank:]]*.pin =[[:blank:]]*6,\n/ RK_PA6,/g
s/[[:blank:]]*.pin =[[:blank:]]*7,\n/ RK_PA7,/g
s/[[:blank:]]*.pin =[[:blank:]]*8,\n/ RK_PB0,/g
s/[[:blank:]]*.pin =[[:blank:]]*9,\n/ RK_PB1,/g
s/[[:blank:]]*.pin =[[:blank:]]*10,\n/ RK_PB2,/g
s/[[:blank:]]*.pin =[[:blank:]]*11,\n/ RK_PB3,/g
s/[[:blank:]]*.pin =[[:blank:]]*12,\n/ RK_PB4,/g
s/[[:blank:]]*.pin =[[:blank:]]*13,\n/ RK_PB5,/g
s/[[:blank:]]*.pin =[[:blank:]]*14,\n/ RK_PB6,/g
s/[[:blank:]]*.pin =[[:blank:]]*15,\n/ RK_PB7,/g
s/[[:blank:]]*.pin =[[:blank:]]*16,\n/ RK_PC0,/g
s/[[:blank:]]*.pin =[[:blank:]]*17,\n/ RK_PC1,/g
s/[[:blank:]]*.pin =[[:blank:]]*18,\n/ RK_PC2,/g
s/[[:blank:]]*.pin =[[:blank:]]*19,\n/ RK_PC3,/g
s/[[:blank:]]*.pin =[[:blank:]]*20,\n/ RK_PC4,/g
s/[[:blank:]]*.pin =[[:blank:]]*21,\n/ RK_PC5,/g
s/[[:blank:]]*.pin =[[:blank:]]*22,\n/ RK_PC6,/g
s/[[:blank:]]*.pin =[[:blank:]]*23,\n/ RK_PC7,/g
s/[[:blank:]]*.pin =[[:blank:]]*24,\n/ RK_PD0,/g
s/[[:blank:]]*.pin =[[:blank:]]*25,\n/ RK_PD1,/g
s/[[:blank:]]*.pin =[[:blank:]]*26,\n/ RK_PD2,/g
s/[[:blank:]]*.pin =[[:blank:]]*27,\n/ RK_PD3,/g
s/[[:blank:]]*.pin =[[:blank:]]*28,\n/ RK_PD4,/g
s/[[:blank:]]*.pin =[[:blank:]]*29,\n/ RK_PD5,/g
s/[[:blank:]]*.pin =[[:blank:]]*30,\n/ RK_PD6,/g
s/[[:blank:]]*.pin =[[:blank:]]*31,\n/ RK_PD7,/g
s/[[:blank:]]*.func = \([[:digit:]]*,\)\n/ \1/g
s/[[:blank:]]*.route_location =[[:blank:]]*\([[:print:]]*,\)\n//g
s/[[:blank:]]*.route_offset = \(0x[[:xdigit:]]*,\)\n/ \1/g
s/[[:blank:]]*.route_val =[[:blank:]]*\([[:print:]]*\),\n/ \1),/g
s/\t{\n//g
s/\t}, {\n//g
s/\t},//g
s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),\n/\tRK_MUXROUTE_SAME(\2),
 \1\n/g
s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),/\tRK_MUXROUTE_SAME(\2),
 \1\n/g
" drivers/pinctrl/pinctrl-rockchip.c

Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
v3:
 - remove change-id
v2:
 - add reviewed-by heiko

 drivers/pinctrl/pinctrl-rockchip.c | 650 -
 1 file changed, 80 insertions(+), 570 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index aa1a1c850d05..c135ea847c54 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -801,597 +801,107 @@ static void rockchip_get_recalced_mux(struct 
rockchip_pin_bank *bank, int pin,
 }
 
 static struct rockchip_mux_route_data px30_mux_route_data[] = {
-   {
-   /* cif-d2m0 */
-   .bank_num = 2,
-   .pin = 0,
-   .func = 1,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 7),
-   }, {
-   /* cif-d2m1 */
-   .bank_num = 3,
-   .pin = 3,
-   .func = 3,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 7) | BIT(7),
-   }, {
-   /* pdm-m0 */
-   .bank_num = 3,
-   .pin = 22,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 8),
-   }, {
-   /* pdm-m1 */
-   .bank_num = 2,
-   .pin = 22,
-   .func = 1,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 8) | BIT(8),
-   }, {
-   /* uart2-rxm0 */
-   .bank_num = 1,
-   .pin = 27,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 10),
-   }, {
-   /* uart2-rxm1 */
-   .bank_num = 2,
-   .pin = 14,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 10) | BIT(10),
-   }, {
-   /* uart3-rxm0 */
-   .bank_num = 0,
-   .pin = 17,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 9),
-   }, {
-   /* uart3-rxm1 */
-   .bank_num = 1,
-   .pin = 15,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 9) | BIT(9),
-   },
+   RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x1

[PATCH v2] pinctrl: rockchip: do coding style for mux route struct

[Jianqun Xu]

The mux route tables take many lines for each SoC, and it will be more
instances for newly SoC, that makes the file size increase larger.

This patch only do coding style for mux route struct, by adding a new
definition and replace the structs by script which supplied by
huang...@rock-chips.com

sed -i -e "
/static struct rockchip_mux_route_data /bcheck
b
:append-next-line
N
:check
/^[^;]*$/bappend-next-line
s/[[:blank:]]*.bank_num = \([[:digit:]]*,\)\n/\tRK_MUXROUTE_SAME(\1/g
s/[[:blank:]]*.pin =[[:blank:]]*0,\n/ RK_PA0,/g
s/[[:blank:]]*.pin =[[:blank:]]*1,\n/ RK_PA1,/g
s/[[:blank:]]*.pin =[[:blank:]]*2,\n/ RK_PA2,/g
s/[[:blank:]]*.pin =[[:blank:]]*3,\n/ RK_PA3,/g
s/[[:blank:]]*.pin =[[:blank:]]*4,\n/ RK_PA4,/g
s/[[:blank:]]*.pin =[[:blank:]]*5,\n/ RK_PA5,/g
s/[[:blank:]]*.pin =[[:blank:]]*6,\n/ RK_PA6,/g
s/[[:blank:]]*.pin =[[:blank:]]*7,\n/ RK_PA7,/g
s/[[:blank:]]*.pin =[[:blank:]]*8,\n/ RK_PB0,/g
s/[[:blank:]]*.pin =[[:blank:]]*9,\n/ RK_PB1,/g
s/[[:blank:]]*.pin =[[:blank:]]*10,\n/ RK_PB2,/g
s/[[:blank:]]*.pin =[[:blank:]]*11,\n/ RK_PB3,/g
s/[[:blank:]]*.pin =[[:blank:]]*12,\n/ RK_PB4,/g
s/[[:blank:]]*.pin =[[:blank:]]*13,\n/ RK_PB5,/g
s/[[:blank:]]*.pin =[[:blank:]]*14,\n/ RK_PB6,/g
s/[[:blank:]]*.pin =[[:blank:]]*15,\n/ RK_PB7,/g
s/[[:blank:]]*.pin =[[:blank:]]*16,\n/ RK_PC0,/g
s/[[:blank:]]*.pin =[[:blank:]]*17,\n/ RK_PC1,/g
s/[[:blank:]]*.pin =[[:blank:]]*18,\n/ RK_PC2,/g
s/[[:blank:]]*.pin =[[:blank:]]*19,\n/ RK_PC3,/g
s/[[:blank:]]*.pin =[[:blank:]]*20,\n/ RK_PC4,/g
s/[[:blank:]]*.pin =[[:blank:]]*21,\n/ RK_PC5,/g
s/[[:blank:]]*.pin =[[:blank:]]*22,\n/ RK_PC6,/g
s/[[:blank:]]*.pin =[[:blank:]]*23,\n/ RK_PC7,/g
s/[[:blank:]]*.pin =[[:blank:]]*24,\n/ RK_PD0,/g
s/[[:blank:]]*.pin =[[:blank:]]*25,\n/ RK_PD1,/g
s/[[:blank:]]*.pin =[[:blank:]]*26,\n/ RK_PD2,/g
s/[[:blank:]]*.pin =[[:blank:]]*27,\n/ RK_PD3,/g
s/[[:blank:]]*.pin =[[:blank:]]*28,\n/ RK_PD4,/g
s/[[:blank:]]*.pin =[[:blank:]]*29,\n/ RK_PD5,/g
s/[[:blank:]]*.pin =[[:blank:]]*30,\n/ RK_PD6,/g
s/[[:blank:]]*.pin =[[:blank:]]*31,\n/ RK_PD7,/g
s/[[:blank:]]*.func = \([[:digit:]]*,\)\n/ \1/g
s/[[:blank:]]*.route_location =[[:blank:]]*\([[:print:]]*,\)\n//g
s/[[:blank:]]*.route_offset = \(0x[[:xdigit:]]*,\)\n/ \1/g
s/[[:blank:]]*.route_val =[[:blank:]]*\([[:print:]]*\),\n/ \1),/g
s/\t{\n//g
s/\t}, {\n//g
s/\t},//g
s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),\n/\tRK_MUXROUTE_SAME(\2),
 \1\n/g
s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),/\tRK_MUXROUTE_SAME(\2),
 \1\n/g
" drivers/pinctrl/pinctrl-rockchip.c

Signed-off-by: Jianqun Xu 
Reviewed-by: Heiko Stuebner 
Change-Id: I50a12f00ae127df8938221d10f94e6733baab1c5
---
v2:
 - remove change-id
 - reviewed-by heiko

 drivers/pinctrl/pinctrl-rockchip.c | 650 -
 1 file changed, 80 insertions(+), 570 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index aa1a1c850d05..c135ea847c54 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -801,597 +801,107 @@ static void rockchip_get_recalced_mux(struct 
rockchip_pin_bank *bank, int pin,
 }
 
 static struct rockchip_mux_route_data px30_mux_route_data[] = {
-   {
-   /* cif-d2m0 */
-   .bank_num = 2,
-   .pin = 0,
-   .func = 1,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 7),
-   }, {
-   /* cif-d2m1 */
-   .bank_num = 3,
-   .pin = 3,
-   .func = 3,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 7) | BIT(7),
-   }, {
-   /* pdm-m0 */
-   .bank_num = 3,
-   .pin = 22,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 8),
-   }, {
-   /* pdm-m1 */
-   .bank_num = 2,
-   .pin = 22,
-   .func = 1,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 8) | BIT(8),
-   }, {
-   /* uart2-rxm0 */
-   .bank_num = 1,
-   .pin = 27,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 10),
-   }, {
-   /* uart2-rxm1 */
-   .bank_num = 2,
-   .pin = 14,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 10) | BIT(10),
-   }, {
-   /* uart3-rxm0 */
-   .bank_num = 0,
-   .pin = 17,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 9),
-   }, {
-   /* uart3-rxm1 */
-   .bank_num = 1,
-   .pin = 15,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 

[PATCH] pinctrl: rockchip: do coding style for mux route struct

[Jianqun Xu]

The mux route tables take many lines for each SoC, and it will be more
instances for newly SoC, that makes the file size increase larger.

This patch only do coding style for mux route struct, by adding a new
definition and replace the structs by script which supplied by
huang...@rock-chips.com

sed -i -e "
/static struct rockchip_mux_route_data /bcheck
b
:append-next-line
N
:check
/^[^;]*$/bappend-next-line
s/[[:blank:]]*.bank_num = \([[:digit:]]*,\)\n/\tRK_MUXROUTE_SAME(\1/g
s/[[:blank:]]*.pin =[[:blank:]]*0,\n/ RK_PA0,/g
s/[[:blank:]]*.pin =[[:blank:]]*1,\n/ RK_PA1,/g
s/[[:blank:]]*.pin =[[:blank:]]*2,\n/ RK_PA2,/g
s/[[:blank:]]*.pin =[[:blank:]]*3,\n/ RK_PA3,/g
s/[[:blank:]]*.pin =[[:blank:]]*4,\n/ RK_PA4,/g
s/[[:blank:]]*.pin =[[:blank:]]*5,\n/ RK_PA5,/g
s/[[:blank:]]*.pin =[[:blank:]]*6,\n/ RK_PA6,/g
s/[[:blank:]]*.pin =[[:blank:]]*7,\n/ RK_PA7,/g
s/[[:blank:]]*.pin =[[:blank:]]*8,\n/ RK_PB0,/g
s/[[:blank:]]*.pin =[[:blank:]]*9,\n/ RK_PB1,/g
s/[[:blank:]]*.pin =[[:blank:]]*10,\n/ RK_PB2,/g
s/[[:blank:]]*.pin =[[:blank:]]*11,\n/ RK_PB3,/g
s/[[:blank:]]*.pin =[[:blank:]]*12,\n/ RK_PB4,/g
s/[[:blank:]]*.pin =[[:blank:]]*13,\n/ RK_PB5,/g
s/[[:blank:]]*.pin =[[:blank:]]*14,\n/ RK_PB6,/g
s/[[:blank:]]*.pin =[[:blank:]]*15,\n/ RK_PB7,/g
s/[[:blank:]]*.pin =[[:blank:]]*16,\n/ RK_PC0,/g
s/[[:blank:]]*.pin =[[:blank:]]*17,\n/ RK_PC1,/g
s/[[:blank:]]*.pin =[[:blank:]]*18,\n/ RK_PC2,/g
s/[[:blank:]]*.pin =[[:blank:]]*19,\n/ RK_PC3,/g
s/[[:blank:]]*.pin =[[:blank:]]*20,\n/ RK_PC4,/g
s/[[:blank:]]*.pin =[[:blank:]]*21,\n/ RK_PC5,/g
s/[[:blank:]]*.pin =[[:blank:]]*22,\n/ RK_PC6,/g
s/[[:blank:]]*.pin =[[:blank:]]*23,\n/ RK_PC7,/g
s/[[:blank:]]*.pin =[[:blank:]]*24,\n/ RK_PD0,/g
s/[[:blank:]]*.pin =[[:blank:]]*25,\n/ RK_PD1,/g
s/[[:blank:]]*.pin =[[:blank:]]*26,\n/ RK_PD2,/g
s/[[:blank:]]*.pin =[[:blank:]]*27,\n/ RK_PD3,/g
s/[[:blank:]]*.pin =[[:blank:]]*28,\n/ RK_PD4,/g
s/[[:blank:]]*.pin =[[:blank:]]*29,\n/ RK_PD5,/g
s/[[:blank:]]*.pin =[[:blank:]]*30,\n/ RK_PD6,/g
s/[[:blank:]]*.pin =[[:blank:]]*31,\n/ RK_PD7,/g
s/[[:blank:]]*.func = \([[:digit:]]*,\)\n/ \1/g
s/[[:blank:]]*.route_location =[[:blank:]]*\([[:print:]]*,\)\n//g
s/[[:blank:]]*.route_offset = \(0x[[:xdigit:]]*,\)\n/ \1/g
s/[[:blank:]]*.route_val =[[:blank:]]*\([[:print:]]*\),\n/ \1),/g
s/\t{\n//g
s/\t}, {\n//g
s/\t},//g
s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),\n/\tRK_MUXROUTE_SAME(\2),
 \1\n/g
s/[[:blank:]]*\(\/\*[[:print:]]*\*\/\)\n[[:blank:]]*RK_MUXROUTE_SAME(\([[:print:]]*\)),/\tRK_MUXROUTE_SAME(\2),
 \1\n/g
" drivers/pinctrl/pinctrl-rockchip.c

Signed-off-by: Jianqun Xu 
Change-Id: Ifc823d9557605b9dfcc9c0455a739f04f3fce5be
---
 drivers/pinctrl/pinctrl-rockchip.c | 669 +
 1 file changed, 99 insertions(+), 570 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index deabfbc74a01..6ba31c66ef8b 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -292,6 +292,25 @@ struct rockchip_pin_bank {
.pull_type[3] = pull3,  \
}
 
+#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG)
\
+   {   \
+   .bank_num   = ID,   \
+   .pin= PIN,  \
+   .func   = FUNC, \
+   .route_offset   = REG,  \
+   .route_val  = VAL,  \
+   .route_location = FLAG, \
+   }
+
+#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL)  \
+   PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
+
+#define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL)   \
+   PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
+
+#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL)   \
+   PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
+
 /**
  * struct rockchip_mux_recalced_data: represent a pin iomux data.
  * @num: bank number.
@@ -803,597 +822,107 @@ static void rockchip_get_recalced_mux(struct 
rockchip_pin_bank *bank, int pin,
 }
 
 static struct rockchip_mux_route_data px30_mux_route_data[] = {
-   {
-   /* cif-d2m0 */
-   .bank_num = 2,
-   .pin = 0,
-   .func = 1,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 7),
-   }, {
-   /* cif-d2m1 */
-   .bank_num = 3,
-   .pin = 3,
-   .func = 3,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 7) | BIT(7),
-   }, {
-   /* pdm-m0 */
-   .bank_num = 3,
-   .pin = 22,
-  

[PATCH 7/7] gpio/rockchip: drop irq_gc_lock/irq_gc_unlock for irq set type

[Jianqun Xu]

There has spin lock for irq set type already, so drop irq_gc_lock and
irq_gc_unlock.

Signed-off-by: Jianqun Xu 
---
 drivers/gpio/gpio-rockchip.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index 048e7eecddba..c9c55614bbef 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -406,7 +406,6 @@ static int rockchip_irq_set_type(struct irq_data *d, 
unsigned int type)
irq_set_handler_locked(d, handle_level_irq);
 
raw_spin_lock_irqsave(>slock, flags);
-   irq_gc_lock(gc);
 
level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
@@ -461,7 +460,6 @@ static int rockchip_irq_set_type(struct irq_data *d, 
unsigned int type)
rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
 out:
-   irq_gc_unlock(gc);
raw_spin_unlock_irqrestore(>slock, flags);
 
return ret;
-- 
2.25.1

[PATCH 6/7] gpio/rockchip: always enable clock for gpio controller

[Jianqun Xu]

Since gate and ungate pclk of gpio has very litte benifit for system
power consumption, just keep it always ungate.

Signed-off-by: Jianqun Xu 
---
 drivers/gpio/gpio-rockchip.c | 68 +---
 1 file changed, 9 insertions(+), 59 deletions(-)

diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index 92aaf1848449..048e7eecddba 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -139,17 +139,8 @@ static int rockchip_gpio_get_direction(struct gpio_chip 
*chip,
 {
struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
u32 data;
-   int ret;
 
-   ret = clk_enable(bank->clk);
-   if (ret < 0) {
-   dev_err(bank->drvdata->dev,
-   "failed to enable clock for bank %s\n", bank->name);
-   return ret;
-   }
data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
-   clk_disable(bank->clk);
-
if (data & BIT(offset))
return GPIO_LINE_DIRECTION_OUT;
 
@@ -163,11 +154,9 @@ static int rockchip_gpio_set_direction(struct gpio_chip 
*chip,
unsigned long flags;
u32 data = input ? 0 : 1;
 
-   clk_enable(bank->clk);
raw_spin_lock_irqsave(>slock, flags);
rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
raw_spin_unlock_irqrestore(>slock, flags);
-   clk_disable(bank->clk);
 
return 0;
 }
@@ -178,11 +167,9 @@ static void rockchip_gpio_set(struct gpio_chip *gc, 
unsigned int offset,
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
unsigned long flags;
 
-   clk_enable(bank->clk);
raw_spin_lock_irqsave(>slock, flags);
rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
raw_spin_unlock_irqrestore(>slock, flags);
-   clk_disable(bank->clk);
 }
 
 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
@@ -190,11 +177,10 @@ static int rockchip_gpio_get(struct gpio_chip *gc, 
unsigned int offset)
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
u32 data;
 
-   clk_enable(bank->clk);
data = readl(bank->reg_base + bank->gpio_regs->ext_port);
-   clk_disable(bank->clk);
data >>= offset;
data &= 1;
+
return data;
 }
 
@@ -315,9 +301,7 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, 
unsigned int offset)
if (!bank->domain)
return -ENXIO;
 
-   clk_enable(bank->clk);
virq = irq_create_mapping(bank->domain, offset);
-   clk_disable(bank->clk);
 
return (virq) ? : -ENXIO;
 }
@@ -409,7 +393,6 @@ static int rockchip_irq_set_type(struct irq_data *d, 
unsigned int type)
unsigned long flags;
int ret = 0;
 
-   clk_enable(bank->clk);
raw_spin_lock_irqsave(>slock, flags);
 
rockchip_gpio_writel_bit(bank, d->hwirq, 0,
@@ -480,7 +463,6 @@ static int rockchip_irq_set_type(struct irq_data *d, 
unsigned int type)
 out:
irq_gc_unlock(gc);
raw_spin_unlock_irqrestore(>slock, flags);
-   clk_disable(bank->clk);
 
return ret;
 }
@@ -490,10 +472,8 @@ static void rockchip_irq_suspend(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
 
-   clk_enable(bank->clk);
bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
-   clk_disable(bank->clk);
 }
 
 static void rockchip_irq_resume(struct irq_data *d)
@@ -501,27 +481,7 @@ static void rockchip_irq_resume(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
 
-   clk_enable(bank->clk);
irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
-   clk_disable(bank->clk);
-}
-
-static void rockchip_irq_enable(struct irq_data *d)
-{
-   struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-   struct rockchip_pin_bank *bank = gc->private;
-
-   clk_enable(bank->clk);
-   irq_gc_mask_clr_bit(d);
-}
-
-static void rockchip_irq_disable(struct irq_data *d)
-{
-   struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-   struct rockchip_pin_bank *bank = gc->private;
-
-   irq_gc_mask_set_bit(d);
-   clk_disable(bank->clk);
 }
 
 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
@@ -530,19 +490,11 @@ static int rockchip_interrupts_register(struct 
rockchip_pin_bank *bank)
struct irq_chip_generic *gc;
int ret;
 
-   ret = clk_enable(bank->clk);
-   if (ret) {
-   dev_err(bank->

[PATCH 5/7] gpio/rockchip: support next version gpio controller

[Jianqun Xu]

The next version gpio controller on SoCs like rk3568 have more write
mask bits for registers.

Signed-off-by: Jianqun Xu 
---
 drivers/gpio/gpio-rockchip.c   | 280 ++---
 drivers/pinctrl/pinctrl-rockchip.h |   2 +
 2 files changed, 215 insertions(+), 67 deletions(-)

diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index b12db3a523d0..92aaf1848449 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -25,6 +25,7 @@
 #include "../pinctrl/pinctrl-rockchip.h"
 
 #define GPIO_TYPE_V1   (0)   /* GPIO Version ID reserved */
+#define GPIO_TYPE_V2   (0x01000C2B)  /* GPIO Version ID 0x01000C2B */
 
 static const struct rockchip_gpio_regs gpio_regs_v1 = {
.port_dr = 0x00,
@@ -40,6 +41,99 @@ static const struct rockchip_gpio_regs gpio_regs_v1 = {
.ext_port = 0x50,
 };
 
+static const struct rockchip_gpio_regs gpio_regs_v2 = {
+   .port_dr = 0x00,
+   .port_ddr = 0x08,
+   .int_en = 0x10,
+   .int_mask = 0x18,
+   .int_type = 0x20,
+   .int_polarity = 0x28,
+   .int_bothedge = 0x30,
+   .int_status = 0x50,
+   .int_rawstatus = 0x58,
+   .debounce = 0x38,
+   .dbclk_div_en = 0x40,
+   .dbclk_div_con = 0x48,
+   .port_eoi = 0x60,
+   .ext_port = 0x70,
+   .version_id = 0x78,
+};
+
+static inline void gpio_writel_v2(u32 val, void __iomem *reg)
+{
+   writel((val & 0x) | 0x, reg);
+   writel((val >> 16) | 0x, reg + 0x4);
+}
+
+static inline u32 gpio_readl_v2(void __iomem *reg)
+{
+   return readl(reg + 0x4) << 16 | readl(reg);
+}
+
+static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
+   u32 value, unsigned int offset)
+{
+   void __iomem *reg = bank->reg_base + offset;
+
+   if (bank->gpio_type == GPIO_TYPE_V2)
+   gpio_writel_v2(value, reg);
+   else
+   writel(value, reg);
+}
+
+static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
+ unsigned int offset)
+{
+   void __iomem *reg = bank->reg_base + offset;
+   u32 value;
+
+   if (bank->gpio_type == GPIO_TYPE_V2)
+   value = gpio_readl_v2(reg);
+   else
+   value = readl(reg);
+
+   return value;
+}
+
+static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
+   u32 bit, u32 value,
+   unsigned int offset)
+{
+   void __iomem *reg = bank->reg_base + offset;
+   u32 data;
+
+   if (bank->gpio_type == GPIO_TYPE_V2) {
+   if (value)
+   data = BIT(bit % 16) | BIT(bit % 16 + 16);
+   else
+   data = BIT(bit % 16 + 16);
+   writel(data, bit >= 16 ? reg + 0x4 : reg);
+   } else {
+   data = readl(reg);
+   data &= ~BIT(bit);
+   if (value)
+   data |= BIT(bit);
+   writel(data, reg);
+   }
+}
+
+static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
+ u32 bit, unsigned int offset)
+{
+   void __iomem *reg = bank->reg_base + offset;
+   u32 data;
+
+   if (bank->gpio_type == GPIO_TYPE_V2) {
+   data = readl(bit >= 16 ? reg + 0x4 : reg);
+   data >>= bit % 16;
+   } else {
+   data = readl(reg);
+   data >>= bit;
+   }
+
+   return data & (0x1);
+}
+
 static int rockchip_gpio_get_direction(struct gpio_chip *chip,
   unsigned int offset)
 {
@@ -53,7 +147,7 @@ static int rockchip_gpio_get_direction(struct gpio_chip 
*chip,
"failed to enable clock for bank %s\n", bank->name);
return ret;
}
-   data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
+   data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
clk_disable(bank->clk);
 
if (data & BIT(offset))
@@ -67,19 +161,11 @@ static int rockchip_gpio_set_direction(struct gpio_chip 
*chip,
 {
struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
unsigned long flags;
-   u32 data;
+   u32 data = input ? 0 : 1;
 
clk_enable(bank->clk);
raw_spin_lock_irqsave(>slock, flags);
-
-   data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
-   /* set bit to 1 for output, 0 for input */
-   if (!input)
-   data |= BIT(offset);
-   else
-   data &= ~BIT(offset);
-   writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr);
-
+   rockchip_gpio_writel_bit(bank, offset, data, bank-&

[PATCH 1/7] pinctrl/rockchip: separate struct rockchip_pin_bank to a head file

[Jianqun Xu]

Separate struct rockchip_pin_bank to pinctrl-rockchip.h file, which will
be used by gpio-rockchip driver in the future.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 224 +-
 drivers/pinctrl/pinctrl-rockchip.h | 244 +
 2 files changed, 245 insertions(+), 223 deletions(-)
 create mode 100644 drivers/pinctrl/pinctrl-rockchip.h

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index deabfbc74a01..625ebc1cdfd5 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -37,6 +37,7 @@
 
 #include "core.h"
 #include "pinconf.h"
+#include "pinctrl-rockchip.h"
 
 /* GPIO control registers */
 #define GPIO_SWPORT_DR 0x00
@@ -52,19 +53,6 @@
 #define GPIO_EXT_PORT  0x50
 #define GPIO_LS_SYNC   0x60
 
-enum rockchip_pinctrl_type {
-   PX30,
-   RV1108,
-   RK2928,
-   RK3066B,
-   RK3128,
-   RK3188,
-   RK3288,
-   RK3308,
-   RK3368,
-   RK3399,
-};
-
 /*
  * Encode variants of iomux registers into a type variable
  */
@@ -75,103 +63,6 @@ enum rockchip_pinctrl_type {
 #define IOMUX_WIDTH_3BIT   BIT(4)
 #define IOMUX_WIDTH_2BIT   BIT(5)
 
-/**
- * struct rockchip_iomux
- * @type: iomux variant using IOMUX_* constants
- * @offset: if initialized to -1 it will be autocalculated, by specifying
- * an initial offset value the relevant source offset can be reset
- * to a new value for autocalculating the following iomux registers.
- */
-struct rockchip_iomux {
-   int type;
-   int offset;
-};
-
-/*
- * enum type index corresponding to rockchip_perpin_drv_list arrays index.
- */
-enum rockchip_pin_drv_type {
-   DRV_TYPE_IO_DEFAULT = 0,
-   DRV_TYPE_IO_1V8_OR_3V0,
-   DRV_TYPE_IO_1V8_ONLY,
-   DRV_TYPE_IO_1V8_3V0_AUTO,
-   DRV_TYPE_IO_3V3_ONLY,
-   DRV_TYPE_MAX
-};
-
-/*
- * enum type index corresponding to rockchip_pull_list arrays index.
- */
-enum rockchip_pin_pull_type {
-   PULL_TYPE_IO_DEFAULT = 0,
-   PULL_TYPE_IO_1V8_ONLY,
-   PULL_TYPE_MAX
-};
-
-/**
- * struct rockchip_drv
- * @drv_type: drive strength variant using rockchip_perpin_drv_type
- * @offset: if initialized to -1 it will be autocalculated, by specifying
- * an initial offset value the relevant source offset can be reset
- * to a new value for autocalculating the following drive strength
- * registers. if used chips own cal_drv func instead to calculate
- * registers offset, the variant could be ignored.
- */
-struct rockchip_drv {
-   enum rockchip_pin_drv_type  drv_type;
-   int offset;
-};
-
-/**
- * struct rockchip_pin_bank
- * @reg_base: register base of the gpio bank
- * @regmap_pull: optional separate register for additional pull settings
- * @clk: clock of the gpio bank
- * @irq: interrupt of the gpio bank
- * @saved_masks: Saved content of GPIO_INTEN at suspend time.
- * @pin_base: first pin number
- * @nr_pins: number of pins in this bank
- * @name: name of the bank
- * @bank_num: number of the bank, to account for holes
- * @iomux: array describing the 4 iomux sources of the bank
- * @drv: array describing the 4 drive strength sources of the bank
- * @pull_type: array describing the 4 pull type sources of the bank
- * @valid: is all necessary information present
- * @of_node: dt node of this bank
- * @drvdata: common pinctrl basedata
- * @domain: irqdomain of the gpio bank
- * @gpio_chip: gpiolib chip
- * @grange: gpio range
- * @slock: spinlock for the gpio bank
- * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
- * @recalced_mask: bit mask to indicate a need to recalulate the mask
- * @route_mask: bits describing the routing pins of per bank
- */
-struct rockchip_pin_bank {
-   void __iomem*reg_base;
-   struct regmap   *regmap_pull;
-   struct clk  *clk;
-   int irq;
-   u32 saved_masks;
-   u32 pin_base;
-   u8  nr_pins;
-   char*name;
-   u8  bank_num;
-   struct rockchip_iomux   iomux[4];
-   struct rockchip_drv drv[4];
-   enum rockchip_pin_pull_type pull_type[4];
-   boolvalid;
-   struct device_node  *of_node;
-   struct rockchip_pinctrl *drvdata;
-   struct irq_domain   *domain;
-   struct gpio_chipgpio_chip;
-   struct pinctrl_gpio_range   grange;
-   raw_spinlock_t  slock;
-   u32 toggle_edge_mode;
-   u32 

[PATCH 4/7] gpio/rockchip: use struct rockchip_gpio_regs for gpio controller

[Jianqun Xu]

Store register offsets in the struct rockchip_gpio_regs, this patch
prepare for the driver update for new gpio controller.

Signed-off-by: Jianqun Xu 
---
 drivers/gpio/gpio-rockchip.c   | 85 --
 drivers/pinctrl/pinctrl-rockchip.h | 38 +
 2 files changed, 84 insertions(+), 39 deletions(-)

diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index 03a3d251faae..b12db3a523d0 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -24,19 +24,21 @@
 #include "../pinctrl/core.h"
 #include "../pinctrl/pinctrl-rockchip.h"
 
-/* GPIO control registers */
-#define GPIO_SWPORT_DR 0x00
-#define GPIO_SWPORT_DDR0x04
-#define GPIO_INTEN 0x30
-#define GPIO_INTMASK   0x34
-#define GPIO_INTTYPE_LEVEL 0x38
-#define GPIO_INT_POLARITY  0x3c
-#define GPIO_INT_STATUS0x40
-#define GPIO_INT_RAWSTATUS 0x44
-#define GPIO_DEBOUNCE  0x48
-#define GPIO_PORTS_EOI 0x4c
-#define GPIO_EXT_PORT  0x50
-#define GPIO_LS_SYNC   0x60
+#define GPIO_TYPE_V1   (0)   /* GPIO Version ID reserved */
+
+static const struct rockchip_gpio_regs gpio_regs_v1 = {
+   .port_dr = 0x00,
+   .port_ddr = 0x04,
+   .int_en = 0x30,
+   .int_mask = 0x34,
+   .int_type = 0x38,
+   .int_polarity = 0x3c,
+   .int_status = 0x40,
+   .int_rawstatus = 0x44,
+   .debounce = 0x48,
+   .port_eoi = 0x4c,
+   .ext_port = 0x50,
+};
 
 static int rockchip_gpio_get_direction(struct gpio_chip *chip,
   unsigned int offset)
@@ -51,7 +53,7 @@ static int rockchip_gpio_get_direction(struct gpio_chip *chip,
"failed to enable clock for bank %s\n", bank->name);
return ret;
}
-   data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
+   data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
clk_disable(bank->clk);
 
if (data & BIT(offset))
@@ -70,13 +72,13 @@ static int rockchip_gpio_set_direction(struct gpio_chip 
*chip,
clk_enable(bank->clk);
raw_spin_lock_irqsave(>slock, flags);
 
-   data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
+   data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr);
/* set bit to 1 for output, 0 for input */
if (!input)
data |= BIT(offset);
else
data &= ~BIT(offset);
-   writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
+   writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr);
 
raw_spin_unlock_irqrestore(>slock, flags);
clk_disable(bank->clk);
@@ -88,7 +90,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned 
int offset,
  int value)
 {
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
-   void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
+   void __iomem *reg = bank->reg_base + bank->gpio_regs->port_dr;
unsigned long flags;
u32 data;
 
@@ -111,7 +113,7 @@ static int rockchip_gpio_get(struct gpio_chip *gc, unsigned 
int offset)
u32 data;
 
clk_enable(bank->clk);
-   data = readl(bank->reg_base + GPIO_EXT_PORT);
+   data = readl(bank->reg_base + bank->gpio_regs->ext_port);
clk_disable(bank->clk);
data >>= offset;
data &= 1;
@@ -122,7 +124,7 @@ static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
   unsigned int offset, bool enable)
 {
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
-   void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
+   void __iomem *reg = bank->reg_base + bank->gpio_regs->debounce;
unsigned long flags;
u32 data;
 
@@ -226,7 +228,7 @@ static void rockchip_irq_demux(struct irq_desc *desc)
 
chained_irq_enter(chip, desc);
 
-   pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
+   pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
 
while (pend) {
unsigned int irq, virq;
@@ -250,24 +252,26 @@ static void rockchip_irq_demux(struct irq_desc *desc)
u32 data, data_old, polarity;
unsigned long flags;
 
-   data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
+   data = readl_relaxed(bank->reg_base +
+bank->gpio_regs->ext_port);
do {
raw_spin_lock_irqsave(>slock, flags);
 
polarity = readl_relaxed(bank->reg_base +
-  

[PATCH 3/7] gpio: separate gpio driver from pinctrl-rockchip driver

[Jianqun Xu]

Separate the gpio driver from the pinctrl driver.

Signed-off-by: Jianqun Xu 
---
 drivers/gpio/Kconfig   |   8 +
 drivers/gpio/Makefile  |   1 +
 drivers/gpio/gpio-rockchip.c   | 657 +++
 drivers/pinctrl/pinctrl-rockchip.c | 685 +
 4 files changed, 684 insertions(+), 667 deletions(-)
 create mode 100644 drivers/gpio/gpio-rockchip.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e3607ec4c2e8..702fb6db3e46 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -508,6 +508,14 @@ config GPIO_REG
  A 32-bit single register GPIO fixed in/out implementation.  This
  can be used to represent any register as a set of GPIO signals.
 
+config GPIO_ROCKCHIP
+   tristate "Rockchip GPIO support"
+   depends on ARCH_ROCKCHIP || COMPILE_TEST
+   select GPIOLIB_IRQCHIP
+   default ARCH_ROCKCHIP
+   help
+ Say yes here to support GPIO on Rockchip SoCs.
+
 config GPIO_SAMA5D2_PIOBU
tristate "SAMA5D2 PIOBU GPIO support"
depends on MFD_SYSCON
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index c58a90a3c3b1..1432694f3b3a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -125,6 +125,7 @@ obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
 obj-$(CONFIG_GPIO_RDA) += gpio-rda.o
 obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
 obj-$(CONFIG_GPIO_REG) += gpio-reg.o
+obj-$(CONFIG_GPIO_ROCKCHIP)+= gpio-rockchip.o
 obj-$(CONFIG_ARCH_SA1100)  += gpio-sa1100.o
 obj-$(CONFIG_GPIO_SAMA5D2_PIOBU)   += gpio-sama5d2-piobu.o
 obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
new file mode 100644
index ..03a3d251faae
--- /dev/null
+++ b/drivers/gpio/gpio-rockchip.c
@@ -0,0 +1,657 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner 
+ *
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pinctrl/core.h"
+#include "../pinctrl/pinctrl-rockchip.h"
+
+/* GPIO control registers */
+#define GPIO_SWPORT_DR 0x00
+#define GPIO_SWPORT_DDR0x04
+#define GPIO_INTEN 0x30
+#define GPIO_INTMASK   0x34
+#define GPIO_INTTYPE_LEVEL 0x38
+#define GPIO_INT_POLARITY  0x3c
+#define GPIO_INT_STATUS0x40
+#define GPIO_INT_RAWSTATUS 0x44
+#define GPIO_DEBOUNCE  0x48
+#define GPIO_PORTS_EOI 0x4c
+#define GPIO_EXT_PORT  0x50
+#define GPIO_LS_SYNC   0x60
+
+static int rockchip_gpio_get_direction(struct gpio_chip *chip,
+  unsigned int offset)
+{
+   struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
+   u32 data;
+   int ret;
+
+   ret = clk_enable(bank->clk);
+   if (ret < 0) {
+   dev_err(bank->drvdata->dev,
+   "failed to enable clock for bank %s\n", bank->name);
+   return ret;
+   }
+   data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
+   clk_disable(bank->clk);
+
+   if (data & BIT(offset))
+   return GPIO_LINE_DIRECTION_OUT;
+
+   return GPIO_LINE_DIRECTION_IN;
+}
+
+static int rockchip_gpio_set_direction(struct gpio_chip *chip,
+  unsigned int offset, bool input)
+{
+   struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
+   unsigned long flags;
+   u32 data;
+
+   clk_enable(bank->clk);
+   raw_spin_lock_irqsave(>slock, flags);
+
+   data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
+   /* set bit to 1 for output, 0 for input */
+   if (!input)
+   data |= BIT(offset);
+   else
+   data &= ~BIT(offset);
+   writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
+
+   raw_spin_unlock_irqrestore(>slock, flags);
+   clk_disable(bank->clk);
+
+   return 0;
+}
+
+static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
+ int value)
+{
+   struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
+   void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
+   unsigned long flags;
+   u32 data;
+
+   clk_enable(bank->clk);
+   raw_spin_lock_irqsave(>slock, flags);
+
+   data = readl(reg);
+   data &= ~BIT(offset);
+   if (value)
+   data |= BIT(offset);
+   writel(data, reg);
+
+   raw_spin_unlock_irqrestore(>slock, flags);
+   clk_disable(bank->clk);
+}
+
+static int rockchip_gpio_get(struct gpi

[PATCH RESEND 0/7] gpio-rockchip driver

[Jianqun Xu]

Separate gpio driver from pinctrl driver, and support v2 controller.

Jianqun Xu (7):
  pinctrl/rockchip: separate struct rockchip_pin_bank to a head file
  pinctrl/pinctrl-rockchip.h: add pinctrl device to gpio bank struct
  gpio: separate gpio driver from pinctrl-rockchip driver
  gpio/rockchip: use struct rockchip_gpio_regs for gpio controller
  gpio/rockchip: support next version gpio controller
  gpio/rockchip: always enable clock for gpio controller
  gpio/rockchip: drop irq_gc_lock/irq_gc_unlock for irq set type

 drivers/gpio/Kconfig   |   8 +
 drivers/gpio/Makefile  |   1 +
 drivers/gpio/gpio-rockchip.c   | 758 
 drivers/pinctrl/pinctrl-rockchip.c | 909 +
 drivers/pinctrl/pinctrl-rockchip.h | 286 +
 5 files changed, 1072 insertions(+), 890 deletions(-)
 create mode 100644 drivers/gpio/gpio-rockchip.c
 create mode 100644 drivers/pinctrl/pinctrl-rockchip.h

-- 
2.25.1

[PATCH 2/7] pinctrl/pinctrl-rockchip.h: add pinctrl device to gpio bank struct

[Jianqun Xu]

Store a pointer from the pinctrl device for the gpio bank.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.h 
b/drivers/pinctrl/pinctrl-rockchip.h
index ba4afab2845f..20f734ce3933 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -80,6 +80,7 @@ struct rockchip_drv {
 
 /**
  * struct rockchip_pin_bank
+ * @dev: the pinctrl device bind to the bank
  * @reg_base: register base of the gpio bank
  * @regmap_pull: optional separate register for additional pull settings
  * @clk: clock of the gpio bank
@@ -104,6 +105,7 @@ struct rockchip_drv {
  * @route_mask: bits describing the routing pins of per bank
  */
 struct rockchip_pin_bank {
+   struct device   *dev;
void __iomem*reg_base;
struct regmap   *regmap_pull;
struct clk  *clk;
-- 
2.25.1

[PATCH 2/3] pinctrl/pinctrl-rockchip.h: add pinctrl device to gpio bank struct

[Jianqun Xu]

Store a pointer from the pinctrl device for the gpio bank.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.h 
b/drivers/pinctrl/pinctrl-rockchip.h
index 69e4639214b5..0a816e256ae6 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -80,6 +80,7 @@ struct rockchip_drv {
 
 /**
  * struct rockchip_pin_bank
+ * @dev: the pinctrl device bind to the bank
  * @reg_base: register base of the gpio bank
  * @regmap_pull: optional separate register for additional pull settings
  * @clk: clock of the gpio bank
@@ -104,6 +105,7 @@ struct rockchip_drv {
  * @route_mask: bits describing the routing pins of per bank
  */
 struct rockchip_pin_bank {
+   struct device   *dev;
void __iomem*reg_base;
struct regmap   *regmap_pull;
struct clk  *clk;
-- 
2.25.1

[PATCH 0/3] gpio-rockchip driver

[Jianqun Xu]

Separate gpio driver from pinctrl driver.

Jianqun Xu (3):
  pinctrl/rockchip: separate struct rockchip_pin_bank to a head file
  pinctrl/pinctrl-rockchip.h: add pinctrl device to gpio bank struct
  gpio: separate gpio driver from pinctrl-rockchip driver

 drivers/gpio/Kconfig   |   8 +
 drivers/gpio/Makefile  |   1 +
 drivers/gpio/gpio-rockchip.c   | 650 +
 drivers/pinctrl/pinctrl-rockchip.c | 909 +
 drivers/pinctrl/pinctrl-rockchip.h | 246 
 5 files changed, 924 insertions(+), 890 deletions(-)
 create mode 100644 drivers/gpio/gpio-rockchip.c
 create mode 100644 drivers/pinctrl/pinctrl-rockchip.h

-- 
2.25.1

[PATCH 1/3] pinctrl/rockchip: separate struct rockchip_pin_bank to a head file

[Jianqun Xu]

Separate struct rockchip_pin_bank to pinctrl-rockchip.h file, which will
be used by gpio-rockchip driver in the future.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 224 +-
 drivers/pinctrl/pinctrl-rockchip.h | 244 +
 2 files changed, 245 insertions(+), 223 deletions(-)
 create mode 100644 drivers/pinctrl/pinctrl-rockchip.h

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index deabfbc74a01..625ebc1cdfd5 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -37,6 +37,7 @@
 
 #include "core.h"
 #include "pinconf.h"
+#include "pinctrl-rockchip.h"
 
 /* GPIO control registers */
 #define GPIO_SWPORT_DR 0x00
@@ -52,19 +53,6 @@
 #define GPIO_EXT_PORT  0x50
 #define GPIO_LS_SYNC   0x60
 
-enum rockchip_pinctrl_type {
-   PX30,
-   RV1108,
-   RK2928,
-   RK3066B,
-   RK3128,
-   RK3188,
-   RK3288,
-   RK3308,
-   RK3368,
-   RK3399,
-};
-
 /*
  * Encode variants of iomux registers into a type variable
  */
@@ -75,103 +63,6 @@ enum rockchip_pinctrl_type {
 #define IOMUX_WIDTH_3BIT   BIT(4)
 #define IOMUX_WIDTH_2BIT   BIT(5)
 
-/**
- * struct rockchip_iomux
- * @type: iomux variant using IOMUX_* constants
- * @offset: if initialized to -1 it will be autocalculated, by specifying
- * an initial offset value the relevant source offset can be reset
- * to a new value for autocalculating the following iomux registers.
- */
-struct rockchip_iomux {
-   int type;
-   int offset;
-};
-
-/*
- * enum type index corresponding to rockchip_perpin_drv_list arrays index.
- */
-enum rockchip_pin_drv_type {
-   DRV_TYPE_IO_DEFAULT = 0,
-   DRV_TYPE_IO_1V8_OR_3V0,
-   DRV_TYPE_IO_1V8_ONLY,
-   DRV_TYPE_IO_1V8_3V0_AUTO,
-   DRV_TYPE_IO_3V3_ONLY,
-   DRV_TYPE_MAX
-};
-
-/*
- * enum type index corresponding to rockchip_pull_list arrays index.
- */
-enum rockchip_pin_pull_type {
-   PULL_TYPE_IO_DEFAULT = 0,
-   PULL_TYPE_IO_1V8_ONLY,
-   PULL_TYPE_MAX
-};
-
-/**
- * struct rockchip_drv
- * @drv_type: drive strength variant using rockchip_perpin_drv_type
- * @offset: if initialized to -1 it will be autocalculated, by specifying
- * an initial offset value the relevant source offset can be reset
- * to a new value for autocalculating the following drive strength
- * registers. if used chips own cal_drv func instead to calculate
- * registers offset, the variant could be ignored.
- */
-struct rockchip_drv {
-   enum rockchip_pin_drv_type  drv_type;
-   int offset;
-};
-
-/**
- * struct rockchip_pin_bank
- * @reg_base: register base of the gpio bank
- * @regmap_pull: optional separate register for additional pull settings
- * @clk: clock of the gpio bank
- * @irq: interrupt of the gpio bank
- * @saved_masks: Saved content of GPIO_INTEN at suspend time.
- * @pin_base: first pin number
- * @nr_pins: number of pins in this bank
- * @name: name of the bank
- * @bank_num: number of the bank, to account for holes
- * @iomux: array describing the 4 iomux sources of the bank
- * @drv: array describing the 4 drive strength sources of the bank
- * @pull_type: array describing the 4 pull type sources of the bank
- * @valid: is all necessary information present
- * @of_node: dt node of this bank
- * @drvdata: common pinctrl basedata
- * @domain: irqdomain of the gpio bank
- * @gpio_chip: gpiolib chip
- * @grange: gpio range
- * @slock: spinlock for the gpio bank
- * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
- * @recalced_mask: bit mask to indicate a need to recalulate the mask
- * @route_mask: bits describing the routing pins of per bank
- */
-struct rockchip_pin_bank {
-   void __iomem*reg_base;
-   struct regmap   *regmap_pull;
-   struct clk  *clk;
-   int irq;
-   u32 saved_masks;
-   u32 pin_base;
-   u8  nr_pins;
-   char*name;
-   u8  bank_num;
-   struct rockchip_iomux   iomux[4];
-   struct rockchip_drv drv[4];
-   enum rockchip_pin_pull_type pull_type[4];
-   boolvalid;
-   struct device_node  *of_node;
-   struct rockchip_pinctrl *drvdata;
-   struct irq_domain   *domain;
-   struct gpio_chipgpio_chip;
-   struct pinctrl_gpio_range   grange;
-   raw_spinlock_t  slock;
-   u32 toggle_edge_mode;
-   u32 

[PATCH 3/3] gpio: separate gpio driver from pinctrl-rockchip driver

[Jianqun Xu]

Separate the gpio driver from the pinctrl driver.

Signed-off-by: Jianqun Xu 
---
 drivers/gpio/Kconfig   |   8 +
 drivers/gpio/Makefile  |   1 +
 drivers/gpio/gpio-rockchip.c   | 650 +++
 drivers/pinctrl/pinctrl-rockchip.c | 685 +
 4 files changed, 677 insertions(+), 667 deletions(-)
 create mode 100644 drivers/gpio/gpio-rockchip.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e3607ec4c2e8..702fb6db3e46 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -508,6 +508,14 @@ config GPIO_REG
  A 32-bit single register GPIO fixed in/out implementation.  This
  can be used to represent any register as a set of GPIO signals.
 
+config GPIO_ROCKCHIP
+   tristate "Rockchip GPIO support"
+   depends on ARCH_ROCKCHIP || COMPILE_TEST
+   select GPIOLIB_IRQCHIP
+   default ARCH_ROCKCHIP
+   help
+ Say yes here to support GPIO on Rockchip SoCs.
+
 config GPIO_SAMA5D2_PIOBU
tristate "SAMA5D2 PIOBU GPIO support"
depends on MFD_SYSCON
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index c58a90a3c3b1..1432694f3b3a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -125,6 +125,7 @@ obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
 obj-$(CONFIG_GPIO_RDA) += gpio-rda.o
 obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
 obj-$(CONFIG_GPIO_REG) += gpio-reg.o
+obj-$(CONFIG_GPIO_ROCKCHIP)+= gpio-rockchip.o
 obj-$(CONFIG_ARCH_SA1100)  += gpio-sa1100.o
 obj-$(CONFIG_GPIO_SAMA5D2_PIOBU)   += gpio-sama5d2-piobu.o
 obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
new file mode 100644
index ..1387323c5aad
--- /dev/null
+++ b/drivers/gpio/gpio-rockchip.c
@@ -0,0 +1,650 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "../pinctrl/core.h"
+#include "../pinctrl/pinctrl-rockchip.h"
+
+/* GPIO control registers */
+#define GPIO_SWPORT_DR 0x00
+#define GPIO_SWPORT_DDR0x04
+#define GPIO_INTEN 0x30
+#define GPIO_INTMASK   0x34
+#define GPIO_INTTYPE_LEVEL 0x38
+#define GPIO_INT_POLARITY  0x3c
+#define GPIO_INT_STATUS0x40
+#define GPIO_INT_RAWSTATUS 0x44
+#define GPIO_DEBOUNCE  0x48
+#define GPIO_PORTS_EOI 0x4c
+#define GPIO_EXT_PORT  0x50
+#define GPIO_LS_SYNC   0x60
+
+static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned int 
offset)
+{
+   struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
+   u32 data;
+   int ret;
+
+   ret = clk_enable(bank->clk);
+   if (ret < 0) {
+   dev_err(bank->drvdata->dev,
+   "failed to enable clock for bank %s\n", bank->name);
+   return ret;
+   }
+   data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
+   clk_disable(bank->clk);
+
+   if (data & BIT(offset))
+   return GPIO_LINE_DIRECTION_OUT;
+
+   return GPIO_LINE_DIRECTION_IN;
+}
+
+static int rockchip_gpio_set_direction(struct gpio_chip *chip,
+  unsigned int offset, bool input)
+{
+   struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
+   unsigned long flags;
+   u32 data;
+
+   clk_enable(bank->clk);
+   raw_spin_lock_irqsave(>slock, flags);
+
+   data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
+   /* set bit to 1 for output, 0 for input */
+   if (!input)
+   data |= BIT(offset);
+   else
+   data &= ~BIT(offset);
+   writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
+
+   raw_spin_unlock_irqrestore(>slock, flags);
+   clk_disable(bank->clk);
+
+   return 0;
+}
+
+static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
+ int value)
+{
+   struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
+   void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
+   unsigned long flags;
+   u32 data;
+
+   clk_enable(bank->clk);
+   raw_spin_lock_irqsave(>slock, flags);
+
+   data = readl(reg);
+   data &= ~BIT(offset);
+   if (value)
+   data |= BIT(offset);
+   writel(data, reg);
+
+   raw_spin_unlock_irqrestore(>slock, flags);
+   clk_disable(bank->clk);
+}
+
+static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+   struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
+   u32 d

[PATCH] mm/slab: kmalloc with GFP_DMA32 allocate from SLAB_CACHE_DMA32

[Jianqun Xu]

The flag GFP_DMA32 only effect in kmalloc_large currently.

This patch will create caches with GFP_DMA32 to support kmalloc with
size under KMALLOC_MAX_CACHE_SIZE.

Signed-off-by: Jianqun Xu 
---
 include/linux/slab.h |  7 +++
 mm/slab_common.c | 14 ++
 2 files changed, 21 insertions(+)

diff --git a/include/linux/slab.h b/include/linux/slab.h
index be4ba5867ac5..f4317663d148 100644
--- a/include/linux/slab.h
+++ b/include/linux/slab.h
@@ -307,6 +307,9 @@ enum kmalloc_cache_type {
KMALLOC_RECLAIM,
 #ifdef CONFIG_ZONE_DMA
KMALLOC_DMA,
+#endif
+#ifdef CONFIG_ZONE_DMA32
+   KMALLOC_DMA32,
 #endif
NR_KMALLOC_TYPES
 };
@@ -331,6 +334,10 @@ static __always_inline enum kmalloc_cache_type 
kmalloc_type(gfp_t flags)
 */
return flags & __GFP_DMA ? KMALLOC_DMA : KMALLOC_RECLAIM;
 #else
+#ifdef CONFIG_ZONE_DMA32
+   if (unlikely(flags & __GFP_DMA32))
+   return KMALLOC_DMA32;
+#endif
return flags & __GFP_RECLAIMABLE ? KMALLOC_RECLAIM : KMALLOC_NORMAL;
 #endif
 }
diff --git a/mm/slab_common.c b/mm/slab_common.c
index e981c80d216c..2a04736fe8f5 100644
--- a/mm/slab_common.c
+++ b/mm/slab_common.c
@@ -805,6 +805,20 @@ void __init create_kmalloc_caches(slab_flags_t flags)
}
}
 #endif
+#ifdef CONFIG_ZONE_DMA32
+   for (i = 0; i <= KMALLOC_SHIFT_HIGH; i++) {
+   struct kmem_cache *s = kmalloc_caches[KMALLOC_NORMAL][i];
+
+   if (s) {
+   unsigned int size = kmalloc_size(i);
+   const char *n = kmalloc_cache_name("dma32-kmalloc", 
size);
+
+   BUG_ON(!n);
+   kmalloc_caches[KMALLOC_DMA32][i] = create_kmalloc_cache(
+   n, size, SLAB_CACHE_DMA32 | flags, 0, 0);
+   }
+   }
+#endif
 }
 #endif /* !CONFIG_SLOB */
 
-- 
2.25.1

[PATCH] kernel/irq: export irq_gc_set_wake

[Jianqun Xu]

Module driver may use irq_gc_set_wake.

Signed-off-by: Jianqun Xu 
---
 kernel/irq/generic-chip.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index a23ac2bbf433..f8f23af6ab0d 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -200,6 +200,7 @@ int irq_gc_set_wake(struct irq_data *d, unsigned int on)
irq_gc_unlock(gc);
return 0;
 }
+EXPORT_SYMBOL_GPL(irq_gc_set_wake);
 
 static u32 irq_readl_be(void __iomem *addr)
 {
-- 
2.25.1

[PATCH v3 2/3] pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq

[Jianqun Xu]

There need to enable pclk_gpio when do irq_create_mapping, since it will
do access to gpio controller.

Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 927d132d6716..a2f361aa6d05 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3157,7 +3157,9 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, 
unsigned offset)
if (!bank->domain)
return -ENXIO;
 
+   clk_enable(bank->clk);
virq = irq_create_mapping(bank->domain, offset);
+   clk_disable(bank->clk);
 
return (virq) ? : -ENXIO;
 }
-- 
2.17.1

[PATCH v3 0/3] rockchip-pinctrl fixes

[Jianqun Xu]

These patches are required by GKI.

Jianqun Xu (3):
  pinctrl: rockchip: make driver be tristate module
  pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq
  pinctrl: rockchip: create irq mapping in gpio_to_irq

 drivers/pinctrl/Kconfig|  2 +-
 drivers/pinctrl/pinctrl-rockchip.c | 43 +++---
 2 files changed, 28 insertions(+), 17 deletions(-)

-- 
2.17.1

[PATCH v3 1/3] pinctrl: rockchip: make driver be tristate module

[Jianqun Xu]

Make pinctrl-rockchip driver to be tristate module, support to build as
a module, this is useful for GKI.

Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/Kconfig|  2 +-
 drivers/pinctrl/pinctrl-rockchip.c | 13 +
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 815095326e2d..bc9774c1ae8d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -207,7 +207,7 @@ config PINCTRL_OXNAS
select MFD_SYSCON
 
 config PINCTRL_ROCKCHIP
-   bool
+   tristate "Rockchip gpio and pinctrl driver"
depends on OF
select PINMUX
select GENERIC_PINCONF
diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 0401c1da79dd..927d132d6716 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -16,10 +16,12 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -4258,3 +4260,14 @@ static int __init rockchip_pinctrl_drv_register(void)
return platform_driver_register(_pinctrl_driver);
 }
 postcore_initcall(rockchip_pinctrl_drv_register);
+
+static void __exit rockchip_pinctrl_drv_unregister(void)
+{
+   platform_driver_unregister(_pinctrl_driver);
+}
+module_exit(rockchip_pinctrl_drv_unregister);
+
+MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pinctrl-rockchip");
+MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
-- 
2.17.1

[PATCH v3 3/3] pinctrl: rockchip: create irq mapping in gpio_to_irq

[Jianqun Xu]

Remove totally irq mappings create in probe, the gpio irq mapping will
be created when do
gpio_to_irq ->
rockchip_gpio_to_irq ->
irq_create_mapping

This patch can speed up system boot on, also abandon many unused irq
mappings' create.

Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 28 
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index a2f361aa6d05..70dc03af5699 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3198,7 +3198,7 @@ static void rockchip_irq_demux(struct irq_desc *desc)
 
irq = __ffs(pend);
pend &= ~BIT(irq);
-   virq = irq_linear_revmap(bank->domain, irq);
+   virq = irq_find_mapping(bank->domain, irq);
 
if (!virq) {
dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
@@ -3377,7 +3377,7 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
int ret;
-   int i, j;
+   int i;
 
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
if (!bank->valid) {
@@ -3404,7 +3404,7 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
 
ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
 "rockchip_gpio_irq", handle_level_irq,
-clr, 0, IRQ_GC_INIT_MASK_CACHE);
+clr, 0, 0);
if (ret) {
dev_err(>dev, "could not alloc generic chips for 
bank %s\n",
bank->name);
@@ -3413,14 +3413,6 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
continue;
}
 
-   /*
-* Linux assumes that all interrupts start out disabled/masked.
-* Our driver only uses the concept of masked and always keeps
-* things enabled, so for us that's all masked and all enabled.
-*/
-   writel_relaxed(0x, bank->reg_base + GPIO_INTMASK);
-   writel_relaxed(0x, bank->reg_base + GPIO_INTEN);
-
gc = irq_get_domain_generic_chip(bank->domain, 0);
gc->reg_base = bank->reg_base;
gc->private = bank;
@@ -3437,13 +3429,17 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
 
+   /*
+* Linux assumes that all interrupts start out disabled/masked.
+* Our driver only uses the concept of masked and always keeps
+* things enabled, so for us that's all masked and all enabled.
+*/
+   writel_relaxed(0x, bank->reg_base + GPIO_INTMASK);
+   writel_relaxed(0x, bank->reg_base + GPIO_INTEN);
+   gc->mask_cache = 0x;
+
irq_set_chained_handler_and_data(bank->irq,
 rockchip_irq_demux, bank);
-
-   /* map the gpio irqs here, when the clock is still running */
-   for (j = 0 ; j < 32 ; j++)
-   irq_create_mapping(bank->domain, j);
-
clk_disable(bank->clk);
}
 
-- 
2.17.1

[PATCH 2/2] pinctrl: rockchip: make driver be tristate module

[Jianqun Xu]

Make pinctrl-rockchip driver to be tristate module, support to build as
a module, this is useful for GKI.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/Kconfig|  2 +-
 drivers/pinctrl/pinctrl-rockchip.c | 13 +
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 4284f39a5c61..743eb2bb8709 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -207,7 +207,7 @@ config PINCTRL_OXNAS
select MFD_SYSCON
 
 config PINCTRL_ROCKCHIP
-   bool
+   tristate "Rockchip gpio and pinctrl driver"
depends on OF
select PINMUX
select GENERIC_PINCONF
diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 0401c1da79dd..927d132d6716 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -16,10 +16,12 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -4258,3 +4260,14 @@ static int __init rockchip_pinctrl_drv_register(void)
return platform_driver_register(_pinctrl_driver);
 }
 postcore_initcall(rockchip_pinctrl_drv_register);
+
+static void __exit rockchip_pinctrl_drv_unregister(void)
+{
+   platform_driver_unregister(_pinctrl_driver);
+}
+module_exit(rockchip_pinctrl_drv_unregister);
+
+MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pinctrl-rockchip");
+MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
-- 
2.17.1

[PATCH] pinctrl: rockchip: populate platform device for rockchip gpio

[Jianqun Xu]

Register both gpio driver and device as part of driver model, so that
the '-gpio'/'-gpios' dependency in dts can be correctly handled by
of_devlink/of_fwlink.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 305 +
 1 file changed, 175 insertions(+), 130 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index c98bd352f831..2e4fc711d0d1 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3370,139 +3370,121 @@ static void rockchip_irq_disable(struct irq_data *d)
 }
 
 static int rockchip_interrupts_register(struct platform_device *pdev,
-   struct rockchip_pinctrl *info)
+   struct rockchip_pin_bank *bank)
 {
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
-   struct rockchip_pin_bank *bank = ctrl->pin_banks;
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
int ret;
-   int i;
 
-   for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
-   if (!bank->valid) {
-   dev_warn(>dev, "bank %s is not valid\n",
-bank->name);
-   continue;
-   }
+   if (!bank->valid) {
+   dev_warn(>dev, "bank %s is not valid\n",
+bank->name);
+   return -EINVAL;
+   }
 
-   ret = clk_enable(bank->clk);
-   if (ret) {
-   dev_err(>dev, "failed to enable clock for bank 
%s\n",
-   bank->name);
-   continue;
-   }
+   ret = clk_enable(bank->clk);
+   if (ret) {
+   dev_err(>dev, "failed to enable clock for bank %s\n",
+   bank->name);
+   return ret;
+   }
 
-   bank->domain = irq_domain_add_linear(bank->of_node, 32,
-   _generic_chip_ops, NULL);
-   if (!bank->domain) {
-   dev_warn(>dev, "could not initialize irq domain 
for bank %s\n",
-bank->name);
-   clk_disable(bank->clk);
-   continue;
-   }
+   bank->domain = irq_domain_add_linear(bank->of_node, 32,
+   _generic_chip_ops, NULL);
+   if (!bank->domain) {
+   dev_warn(>dev, "could not initialize irq domain for bank 
%s\n",
+bank->name);
+   clk_disable(bank->clk);
+   return -EINVAL;
+   }
 
-   ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
-"rockchip_gpio_irq", handle_level_irq,
-clr, 0, 0);
-   if (ret) {
-   dev_err(>dev, "could not alloc generic chips for 
bank %s\n",
-   bank->name);
-   irq_domain_remove(bank->domain);
-   clk_disable(bank->clk);
-   continue;
-   }
+   ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
+"rockchip_gpio_irq", handle_level_irq,
+clr, 0, 0);
+   if (ret) {
+   dev_err(>dev, "could not alloc generic chips for bank 
%s\n",
+   bank->name);
+   irq_domain_remove(bank->domain);
+   clk_disable(bank->clk);
+   return ret;
+   }
 
-   gc = irq_get_domain_generic_chip(bank->domain, 0);
-   gc->reg_base = bank->reg_base;
-   gc->private = bank;
-   gc->chip_types[0].regs.mask = GPIO_INTMASK;
-   gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
-   gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
-   gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
-   gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
-   gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
-   gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
-   gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
-   gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
-   gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
-   gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
-   gc->wake_enabled = IRQ_MSK(bank->nr_pins);
+   gc = irq_get_doma

[PATCH 5/5] pinctrl: rockchip: populate platform device for rockchip gpio

[Jianqun Xu]

Register both gpio driver and device as part of driver model, so that
the '-gpio'/'-gpios' dependency in dts can be correctly handled by
of_devlink/of_fwlink.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 261 +
 1 file changed, 150 insertions(+), 111 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index c98bd352f831..67850a9386d7 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3370,139 +3370,121 @@ static void rockchip_irq_disable(struct irq_data *d)
 }
 
 static int rockchip_interrupts_register(struct platform_device *pdev,
-   struct rockchip_pinctrl *info)
+   struct rockchip_pin_bank *bank)
 {
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
-   struct rockchip_pin_bank *bank = ctrl->pin_banks;
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
int ret;
-   int i;
 
-   for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
-   if (!bank->valid) {
-   dev_warn(>dev, "bank %s is not valid\n",
-bank->name);
-   continue;
-   }
+   if (!bank->valid) {
+   dev_warn(>dev, "bank %s is not valid\n",
+bank->name);
+   return -EINVAL;
+   }
 
-   ret = clk_enable(bank->clk);
-   if (ret) {
-   dev_err(>dev, "failed to enable clock for bank 
%s\n",
-   bank->name);
-   continue;
-   }
+   ret = clk_enable(bank->clk);
+   if (ret) {
+   dev_err(>dev, "failed to enable clock for bank %s\n",
+   bank->name);
+   return ret;
+   }
 
-   bank->domain = irq_domain_add_linear(bank->of_node, 32,
-   _generic_chip_ops, NULL);
-   if (!bank->domain) {
-   dev_warn(>dev, "could not initialize irq domain 
for bank %s\n",
-bank->name);
-   clk_disable(bank->clk);
-   continue;
-   }
+   bank->domain = irq_domain_add_linear(bank->of_node, 32,
+   _generic_chip_ops, NULL);
+   if (!bank->domain) {
+   dev_warn(>dev, "could not initialize irq domain for bank 
%s\n",
+bank->name);
+   clk_disable(bank->clk);
+   return -EINVAL;
+   }
 
-   ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
-"rockchip_gpio_irq", handle_level_irq,
-clr, 0, 0);
-   if (ret) {
-   dev_err(>dev, "could not alloc generic chips for 
bank %s\n",
-   bank->name);
-   irq_domain_remove(bank->domain);
-   clk_disable(bank->clk);
-   continue;
-   }
+   ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
+"rockchip_gpio_irq", handle_level_irq,
+clr, 0, 0);
+   if (ret) {
+   dev_err(>dev, "could not alloc generic chips for bank 
%s\n",
+   bank->name);
+   irq_domain_remove(bank->domain);
+   clk_disable(bank->clk);
+   return ret;
+   }
 
-   gc = irq_get_domain_generic_chip(bank->domain, 0);
-   gc->reg_base = bank->reg_base;
-   gc->private = bank;
-   gc->chip_types[0].regs.mask = GPIO_INTMASK;
-   gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
-   gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
-   gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
-   gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
-   gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
-   gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
-   gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
-   gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
-   gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
-   gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
-   gc->wake_enabled = IRQ_MSK(bank->nr_pins);
+   gc = irq_get_doma

[PATCH 3/5] pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq

[Jianqun Xu]

There need to enable pclk_gpio when do irq_create_mapping, since it will
do access to gpio controller.

Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index cc7512acfc5f..58fd4d822591 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3157,7 +3157,9 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, 
unsigned offset)
if (!bank->domain)
return -ENXIO;
 
+   clk_enable(bank->clk);
virq = irq_create_mapping(bank->domain, offset);
+   clk_disable(bank->clk);
 
return (virq) ? : -ENXIO;
 }
-- 
2.17.1

[PATCH v2 0/5] rockchip-pinctrl fixes for GKI

[Jianqun Xu]

These patches will fix some issues and modify for GKI.

Heiko Stuebner (1):
  pinctrl: rockchip: depend on OF

Jianqun Xu (4):
  pinctrl: rockchip: make driver be tristate module
  pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq
  pinctrl: rockchip: create irq mapping in gpio_to_irq
  pinctrl: rockchip: populate platform device for rockchip gpio

 drivers/pinctrl/Kconfig|   4 +-
 drivers/pinctrl/pinctrl-rockchip.c | 289 +
 2 files changed, 175 insertions(+), 118 deletions(-)

-- 
2.17.1

[PATCH 1/5] pinctrl: rockchip: depend on OF

[Jianqun Xu]

From: Heiko Stuebner 

The Rockchip pinctrl driver needs to handle information from Devicetree
so only makes sense getting compiled on systems with CONFIG_OF enabled.

This also fixes a problem found by the "kernel-test-robot" when compiling
the driver on test-builds that do not have CONFIG_OF enabled:

  drivers/pinctrl/pinctrl-rockchip.c: In function 
'rockchip_pinctrl_parse_groups':
>> drivers/pinctrl/pinctrl-rockchip.c:2881:9: error: implicit declaration of 
>> function 'pinconf_generic_parse_dt_config'; did you mean 
>> 'pinconf_generic_dump_config'? [-Werror=implicit-function-declaration]
2881 |   ret = pinconf_generic_parse_dt_config(np_config, NULL,
 | ^~~
 | pinconf_generic_dump_config
   drivers/pinctrl/pinctrl-rockchip.c: In function 'rockchip_gpiolib_register':
>> drivers/pinctrl/pinctrl-rockchip.c:3473:5: error: 'struct gpio_chip' has no 
>> member named 'of_node'
3473 |   gc->of_node = bank->of_node;

Reported-by: kernel test robot 
Signed-off-by: Heiko Stuebner 
---
 drivers/pinctrl/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8828613c4e0e..4284f39a5c61 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -208,10 +208,12 @@ config PINCTRL_OXNAS
 
 config PINCTRL_ROCKCHIP
bool
+   depends on OF
select PINMUX
select GENERIC_PINCONF
select GENERIC_IRQ_CHIP
select MFD_SYSCON
+   select OF_GPIO
 
 config PINCTRL_RZA1
bool "Renesas RZ/A1 gpio and pinctrl driver"
-- 
2.17.1

[PATCH 2/5] pinctrl: rockchip: make driver be tristate module

[Jianqun Xu]

Make pinctrl-rockchip driver to be tristate module, support to build as
a module, this is useful for GKI.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/Kconfig|  2 +-
 drivers/pinctrl/pinctrl-rockchip.c | 18 ++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 4284f39a5c61..743eb2bb8709 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -207,7 +207,7 @@ config PINCTRL_OXNAS
select MFD_SYSCON
 
 config PINCTRL_ROCKCHIP
-   bool
+   tristate "Rockchip gpio and pinctrl driver"
depends on OF
select PINMUX
select GENERIC_PINCONF
diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 0401c1da79dd..cc7512acfc5f 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -16,10 +16,12 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -4257,4 +4259,20 @@ static int __init rockchip_pinctrl_drv_register(void)
 {
return platform_driver_register(_pinctrl_driver);
 }
+
+static void __exit rockchip_pinctrl_drv_unregister(void)
+{
+   platform_driver_unregister(_pinctrl_driver);
+}
+
+#ifdef CONFIG_PINCTRL_ROCKCHIP_MODULE
+module_init(rockchip_pinctrl_drv_register);
+#else
 postcore_initcall(rockchip_pinctrl_drv_register);
+#endif
+module_exit(rockchip_pinctrl_drv_unregister);
+
+MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pinctrl-rockchip");
+MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
-- 
2.17.1

[PATCH 4/5] pinctrl: rockchip: create irq mapping in gpio_to_irq

[Jianqun Xu]

Remove totally irq mappings create in probe, the gpio irq mapping will
be created when do
gpio_to_irq ->
rockchip_gpio_to_irq ->
irq_create_mapping

This patch can speed up system boot on, also abandon many unused irq
mappings' create.

Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 28 
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 58fd4d822591..c98bd352f831 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3198,7 +3198,7 @@ static void rockchip_irq_demux(struct irq_desc *desc)
 
irq = __ffs(pend);
pend &= ~BIT(irq);
-   virq = irq_linear_revmap(bank->domain, irq);
+   virq = irq_find_mapping(bank->domain, irq);
 
if (!virq) {
dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
@@ -3377,7 +3377,7 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
int ret;
-   int i, j;
+   int i;
 
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
if (!bank->valid) {
@@ -3404,7 +3404,7 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
 
ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
 "rockchip_gpio_irq", handle_level_irq,
-clr, 0, IRQ_GC_INIT_MASK_CACHE);
+clr, 0, 0);
if (ret) {
dev_err(>dev, "could not alloc generic chips for 
bank %s\n",
bank->name);
@@ -3413,14 +3413,6 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
continue;
}
 
-   /*
-* Linux assumes that all interrupts start out disabled/masked.
-* Our driver only uses the concept of masked and always keeps
-* things enabled, so for us that's all masked and all enabled.
-*/
-   writel_relaxed(0x, bank->reg_base + GPIO_INTMASK);
-   writel_relaxed(0x, bank->reg_base + GPIO_INTEN);
-
gc = irq_get_domain_generic_chip(bank->domain, 0);
gc->reg_base = bank->reg_base;
gc->private = bank;
@@ -3437,13 +3429,17 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
 
+   /*
+* Linux assumes that all interrupts start out disabled/masked.
+* Our driver only uses the concept of masked and always keeps
+* things enabled, so for us that's all masked and all enabled.
+*/
+   writel_relaxed(0x, bank->reg_base + GPIO_INTMASK);
+   writel_relaxed(0x, bank->reg_base + GPIO_INTEN);
+   gc->mask_cache = 0x;
+
irq_set_chained_handler_and_data(bank->irq,
 rockchip_irq_demux, bank);
-
-   /* map the gpio irqs here, when the clock is still running */
-   for (j = 0 ; j < 32 ; j++)
-   irq_create_mapping(bank->domain, j);
-
clk_disable(bank->clk);
}
 
-- 
2.17.1

[PATCH 5/6] pinctrl: rockchip: fix crash caused by invalid gpio bank

[Jianqun Xu]

Add valid check for gpio bank.

Change-Id: Ia4609c3045b5df7879beab3c15d791ff54a1f49b
Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 6080573155f6..5b16b69e311f 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2526,9 +2526,9 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, 
unsigned selector,
break;
}
 
-   if (ret) {
+   if (ret && cnt) {
/* revert the already done pin settings */
-   for (cnt--; cnt >= 0; cnt--)
+   for (cnt--; cnt >= 0 && !data[cnt].func; cnt--)
rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 
return ret;
@@ -2599,9 +2599,13 @@ static int rockchip_pmx_gpio_set_direction(struct 
pinctrl_dev *pctldev,
  unsigned offset, bool input)
 {
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+   struct rockchip_pin_bank *bank = >ctrl->pin_banks[offset / 32];
struct gpio_chip *chip;
int pin;
 
+   if (!bank || !bank->valid)
+   return 0;
+
chip = range->gc;
pin = offset - chip->base;
dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
@@ -3022,6 +3026,8 @@ static int rockchip_pinctrl_register(struct 
platform_device *pdev,
 
for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
pin_bank = >ctrl->pin_banks[bank];
+   if (!pin_bank->valid)
+   continue;
pin_bank->grange.name = pin_bank->name;
pin_bank->grange.id = bank;
pin_bank->grange.pin_base = pin_bank->pin_base;
-- 
2.17.1

[PATCH 6/6] pinctrl: rockchip: populate platform device for rockchip gpio

[Jianqun Xu]

Register both gpio driver and device as part of driver model, so that
the '-gpio'/'-gpios' dependency in dts can be correctly handled by
of_devlink/of_fwlink.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 256 -
 1 file changed, 145 insertions(+), 111 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 5b16b69e311f..9dc8daf38e63 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3380,139 +3380,121 @@ static void rockchip_irq_disable(struct irq_data *d)
 }
 
 static int rockchip_interrupts_register(struct platform_device *pdev,
-   struct rockchip_pinctrl *info)
+   struct rockchip_pin_bank *bank)
 {
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
-   struct rockchip_pin_bank *bank = ctrl->pin_banks;
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
int ret;
-   int i;
 
-   for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
-   if (!bank->valid) {
-   dev_warn(>dev, "bank %s is not valid\n",
-bank->name);
-   continue;
-   }
+   if (!bank->valid) {
+   dev_warn(>dev, "bank %s is not valid\n",
+bank->name);
+   return -EINVAL;
+   }
 
-   ret = clk_enable(bank->clk);
-   if (ret) {
-   dev_err(>dev, "failed to enable clock for bank 
%s\n",
-   bank->name);
-   continue;
-   }
+   ret = clk_enable(bank->clk);
+   if (ret) {
+   dev_err(>dev, "failed to enable clock for bank %s\n",
+   bank->name);
+   return ret;
+   }
 
-   bank->domain = irq_domain_add_linear(bank->of_node, 32,
-   _generic_chip_ops, NULL);
-   if (!bank->domain) {
-   dev_warn(>dev, "could not initialize irq domain 
for bank %s\n",
-bank->name);
-   clk_disable(bank->clk);
-   continue;
-   }
+   bank->domain = irq_domain_add_linear(bank->of_node, 32,
+   _generic_chip_ops, NULL);
+   if (!bank->domain) {
+   dev_warn(>dev, "could not initialize irq domain for bank 
%s\n",
+bank->name);
+   clk_disable(bank->clk);
+   return -EINVAL;
+   }
 
-   ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
-"rockchip_gpio_irq", handle_level_irq,
-clr, 0, 0);
-   if (ret) {
-   dev_err(>dev, "could not alloc generic chips for 
bank %s\n",
-   bank->name);
-   irq_domain_remove(bank->domain);
-   clk_disable(bank->clk);
-   continue;
-   }
+   ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
+"rockchip_gpio_irq", handle_level_irq,
+clr, 0, 0);
+   if (ret) {
+   dev_err(>dev, "could not alloc generic chips for bank 
%s\n",
+   bank->name);
+   irq_domain_remove(bank->domain);
+   clk_disable(bank->clk);
+   return ret;
+   }
 
-   gc = irq_get_domain_generic_chip(bank->domain, 0);
-   gc->reg_base = bank->reg_base;
-   gc->private = bank;
-   gc->chip_types[0].regs.mask = GPIO_INTMASK;
-   gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
-   gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
-   gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
-   gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
-   gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
-   gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
-   gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
-   gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
-   gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
-   gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
-   gc->wake_enabled = IRQ_MSK(bank->nr_pins);
+   gc = irq_get_doma

[PATCH 2/6] pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq

[Jianqun Xu]

There need to enable pclk_gpio when do irq_create_mapping, since it will
do access to gpio controller.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 24dfc814dee1..54abda7b7be8 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3155,7 +3155,9 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, 
unsigned offset)
if (!bank->domain)
return -ENXIO;
 
+   clk_enable(bank->clk);
virq = irq_create_mapping(bank->domain, offset);
+   clk_disable(bank->clk);
 
return (virq) ? : -ENXIO;
 }
-- 
2.17.1

[PATCH 4/6] pinctrl: rockchip: do not set gpio if bank invalid

[Jianqun Xu]

Add valid check for gpio bank.

Change-Id: Ib03e2910a7316bd61df18236151e371c4d04077a
Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 265d64b8c4f5..6080573155f6 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2687,6 +2687,9 @@ static int rockchip_pinconf_set(struct pinctrl_dev 
*pctldev, unsigned int pin,
return rc;
break;
case PIN_CONFIG_OUTPUT:
+   if (!bank->valid)
+   return -ENOTSUPP;
+
rockchip_gpio_set(>gpio_chip,
  pin - bank->pin_base, arg);
rc = _rockchip_pmx_gpio_set_direction(>gpio_chip,
@@ -2752,6 +2755,9 @@ static int rockchip_pinconf_get(struct pinctrl_dev 
*pctldev, unsigned int pin,
arg = 1;
break;
case PIN_CONFIG_OUTPUT:
+   if (!bank->valid)
+   return -ENOTSUPP;
+
rc = rockchip_get_mux(bank, pin - bank->pin_base);
if (rc != RK_FUNC_GPIO)
return -EINVAL;
-- 
2.17.1

[PATCH 3/6] pinctrl: rockchip: create irq mapping in gpio_to_irq

[Jianqun Xu]

Remove totally irq mappings create in probe, the gpio irq mapping will
be created when do
gpio_to_irq ->
rockchip_gpio_to_irq ->
irq_create_mapping

This patch can speed up system boot on, also abandon many unused irq
mappings' create.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 28 
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 54abda7b7be8..265d64b8c4f5 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3196,7 +3196,7 @@ static void rockchip_irq_demux(struct irq_desc *desc)
 
irq = __ffs(pend);
pend &= ~BIT(irq);
-   virq = irq_linear_revmap(bank->domain, irq);
+   virq = irq_find_mapping(bank->domain, irq);
 
if (!virq) {
dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
@@ -3375,7 +3375,7 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
int ret;
-   int i, j;
+   int i;
 
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
if (!bank->valid) {
@@ -3402,7 +3402,7 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
 
ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
 "rockchip_gpio_irq", handle_level_irq,
-clr, 0, IRQ_GC_INIT_MASK_CACHE);
+clr, 0, 0);
if (ret) {
dev_err(>dev, "could not alloc generic chips for 
bank %s\n",
bank->name);
@@ -3411,14 +3411,6 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
continue;
}
 
-   /*
-* Linux assumes that all interrupts start out disabled/masked.
-* Our driver only uses the concept of masked and always keeps
-* things enabled, so for us that's all masked and all enabled.
-*/
-   writel_relaxed(0x, bank->reg_base + GPIO_INTMASK);
-   writel_relaxed(0x, bank->reg_base + GPIO_INTEN);
-
gc = irq_get_domain_generic_chip(bank->domain, 0);
gc->reg_base = bank->reg_base;
gc->private = bank;
@@ -3435,13 +3427,17 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
 
+   /*
+* Linux assumes that all interrupts start out disabled/masked.
+* Our driver only uses the concept of masked and always keeps
+* things enabled, so for us that's all masked and all enabled.
+*/
+   writel_relaxed(0x, bank->reg_base + GPIO_INTMASK);
+   writel_relaxed(0x, bank->reg_base + GPIO_INTEN);
+   gc->mask_cache = 0x;
+
irq_set_chained_handler_and_data(bank->irq,
 rockchip_irq_demux, bank);
-
-   /* map the gpio irqs here, when the clock is still running */
-   for (j = 0 ; j < 32 ; j++)
-   irq_create_mapping(bank->domain, j);
-
clk_disable(bank->clk);
}
 
-- 
2.17.1

[PATCH 0/6] rockchip-pinctrl fixes for GKI

[Jianqun Xu]

Fix rockchip pinctrl driver for GKI

Jianqun Xu (6):
  pinctrl: rockchip: make driver be tristate module
  pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq
  pinctrl: rockchip: create irq mapping in gpio_to_irq
  pinctrl: rockchip: do not set gpio if bank invalid
  pinctrl: rockchip: fix crash caused by invalid gpio bank
  pinctrl: rockchip: populate platform device for rockchip gpio

 drivers/pinctrl/Kconfig|   2 +-
 drivers/pinctrl/pinctrl-rockchip.c | 289 +
 2 files changed, 171 insertions(+), 120 deletions(-)

-- 
2.17.1

[PATCH 1/6] pinctrl: rockchip: make driver be tristate module

[Jianqun Xu]

Make pinctrl-rockchip driver to be tristate module, support to build as
a module, this is useful for GKI.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/Kconfig| 2 +-
 drivers/pinctrl/pinctrl-rockchip.c | 7 +++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8828613c4e0e..dd4874e2ac67 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -207,7 +207,7 @@ config PINCTRL_OXNAS
select MFD_SYSCON
 
 config PINCTRL_ROCKCHIP
-   bool
+   tristate "Rockchip gpio and pinctrl driver"
select PINMUX
select GENERIC_PINCONF
select GENERIC_IRQ_CHIP
diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index c07324d1f265..24dfc814dee1 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -16,10 +16,12 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -4256,3 +4258,8 @@ static int __init rockchip_pinctrl_drv_register(void)
return platform_driver_register(_pinctrl_driver);
 }
 postcore_initcall(rockchip_pinctrl_drv_register);
+
+MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pinctrl-rockchip");
+MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
-- 
2.17.1

[PATCH 10/13] pinctrl: rockchip: Add RK3288 definitions to separate from other SoCs

[Jianqun Xu]

Add RK3288 definitions to separate from other SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 21 +
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index ec6a1a08f8b1..04e7027ec8e1 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1855,6 +1855,11 @@ static void rk3188_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
 }
 
 #define RK3288_PULL_OFFSET 0x140
+#define RK3288_PULL_PMU_OFFSET 0x64
+#define RK3288_PULL_BITS_PER_PIN   2
+#define RK3288_PULL_PINS_PER_REG   8
+#define RK3288_PULL_BANK_STRIDE16
+
 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
@@ -1864,22 +1869,22 @@ static void rk3288_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
-   *reg = RK3188_PULL_PMU_OFFSET;
+   *reg = RK3288_PULL_PMU_OFFSET;
 
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
-   *bit = pin_num % RK3188_PULL_PINS_PER_REG;
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4);
+   *bit = pin_num % RK3288_PULL_PINS_PER_REG;
+   *bit *= RK3288_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3288_PULL_OFFSET;
 
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3288_PULL_BANK_STRIDE;
+   *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *bit = (pin_num % RK3288_PULL_PINS_PER_REG);
+   *bit *= RK3288_PULL_BITS_PER_PIN;
}
 }
 
-- 
2.17.1

[PATCH 11/13] pinctrl: rockchip: Add RK3128 definitions to separate from other SoCs

[Jianqun Xu]

Add RK3128 definitions to separate from other SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 04e7027ec8e1..3b74455dcdb2 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1799,6 +1799,8 @@ static void rk2928_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
 };
 
 #define RK3128_PULL_OFFSET 0x118
+#define RK3128_PULL_PINS_PER_REG   16
+#define RK3128_PULL_BANK_STRIDE8
 
 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 int pin_num, struct regmap **regmap,
@@ -1808,10 +1810,10 @@ static void rk3128_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
*regmap = info->regmap_base;
*reg = RK3128_PULL_OFFSET;
-   *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
-   *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3128_PULL_BANK_STRIDE;
+   *reg += ((pin_num / RK3128_PULL_PINS_PER_REG) * 4);
 
-   *bit = pin_num % RK2928_PULL_PINS_PER_REG;
+   *bit = pin_num % RK3128_PULL_PINS_PER_REG;
 }
 
 #define RK3188_PULL_OFFSET 0x164
-- 
2.17.1

[PATCH 09/13] pinctrl: rockchip: Add RK3228 definitions to separate from other SoCs

[Jianqun Xu]

Add RK3228 definitions to separate from other SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 22 ++
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 44f051af97c6..ec6a1a08f8b1 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1918,6 +1918,9 @@ static void rk3288_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 }
 
 #define RK3228_PULL_OFFSET 0x100
+#define RK3228_PULL_BITS_PER_PIN   2
+#define RK3228_PULL_PINS_PER_REG   8
+#define RK3228_PULL_BANK_STRIDE16
 
 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1927,14 +1930,17 @@ static void rk3228_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
*regmap = info->regmap_base;
*reg = RK3228_PULL_OFFSET;
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3228_PULL_BANK_STRIDE;
+   *reg += ((pin_num / RK3228_PULL_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *bit = (pin_num % RK3228_PULL_PINS_PER_REG);
+   *bit *= RK3228_PULL_BITS_PER_PIN;
 }
 
 #define RK3228_DRV_GRF_OFFSET  0x200
+#define RK3228_DRV_BITS_PER_PIN2
+#define RK3228_DRV_PINS_PER_REG8
+#define RK3228_DRV_BANK_STRIDE 16
 
 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1944,11 +1950,11 @@ static void rk3228_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
*regmap = info->regmap_base;
*reg = RK3228_DRV_GRF_OFFSET;
-   *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
-   *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3228_DRV_BANK_STRIDE;
+   *reg += ((pin_num / RK3228_DRV_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
-   *bit *= RK3288_DRV_BITS_PER_PIN;
+   *bit = (pin_num % RK3228_DRV_PINS_PER_REG);
+   *bit *= RK3228_DRV_BITS_PER_PIN;
 }
 
 #define RK3308_PULL_OFFSET 0xa0
-- 
2.17.1

[PATCH 12/13] pinctrl: rockchip: define common codes without special chip name

[Jianqun Xu]

Modify RK3399_DRV_3BITS_PER_PIN to ROCKCHIP_DRV_3BITS_PER_PIN, and
modify RK3288_DRV_BITS_PER_PIN to ROCKCHIP_DRV_BITS_PER_PIN.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 3b74455dcdb2..71a367896297 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -75,6 +75,9 @@ enum rockchip_pinctrl_type {
 #define IOMUX_WIDTH_3BIT   BIT(4)
 #define IOMUX_WIDTH_2BIT   BIT(5)
 
+#define ROCKCHIP_DRV_3BITS_PER_PIN (3)
+#define ROCKCHIP_DRV_BITS_PER_PIN  (2)
+
 /**
  * @type: iomux variant using IOMUX_* constants
  * @offset: if initialized to -1 it will be autocalculated, by specifying
@@ -2074,7 +2077,6 @@ static void rk3368_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
 #define RK3399_PULL_GRF_OFFSET 0xe040
 #define RK3399_PULL_PMU_OFFSET 0x40
-#define RK3399_DRV_3BITS_PER_PIN   3
 #define RK3399_PULL_BITS_PER_PIN   2
 #define RK3399_PULL_PINS_PER_REG   8
 #define RK3399_PULL_BANK_STRIDE16
@@ -2154,7 +2156,7 @@ static int rockchip_get_drive_perpin(struct 
rockchip_pin_bank *bank,
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
-   rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+   rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
@@ -2197,7 +2199,7 @@ static int rockchip_get_drive_perpin(struct 
rockchip_pin_bank *bank,
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
-   rmask_bits = RK3288_DRV_BITS_PER_PIN;
+   rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
break;
default:
dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
@@ -2251,7 +2253,7 @@ static int rockchip_set_drive_perpin(struct 
rockchip_pin_bank *bank,
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
-   rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+   rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
@@ -2291,7 +2293,7 @@ static int rockchip_set_drive_perpin(struct 
rockchip_pin_bank *bank,
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
-   rmask_bits = RK3288_DRV_BITS_PER_PIN;
+   rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
break;
default:
dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
-- 
2.17.1

[PATCH 13/13] pinctrl: rockchip: do codingstyle by adding mux route definitions

[Jianqun Xu]

Add MR_SAME/MR_GRF/MR_PMU definitions, and update data in mux route
structures.

This patch do nothing change, only do some codingstyle.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 674 +
 1 file changed, 104 insertions(+), 570 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 71a367896297..50558ffcc05c 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -78,6 +78,9 @@ enum rockchip_pinctrl_type {
 #define ROCKCHIP_DRV_3BITS_PER_PIN (3)
 #define ROCKCHIP_DRV_BITS_PER_PIN  (2)
 
+#define RK_GENMASK_VAL(h, l, v) \
+   (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l
+
 /**
  * @type: iomux variant using IOMUX_* constants
  * @offset: if initialized to -1 it will be autocalculated, by specifying
@@ -290,6 +293,25 @@ struct rockchip_pin_bank {
.pull_type[3] = pull3,  \
}
 
+#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG)
\
+   {   \
+   .bank_num   = ID,   \
+   .pin= PIN,  \
+   .func   = FUNC, \
+   .route_offset   = REG,  \
+   .route_val  = VAL,  \
+   .route_location = FLAG, \
+   }
+
+#define MR_SAME(ID, PIN, FUNC, REG, VAL) \
+   PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
+
+#define MR_GRF(ID, PIN, FUNC, REG, VAL)\
+   PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
+
+#define MR_PMU(ID, PIN, FUNC, REG, VAL)\
+   PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
+
 /**
  * struct rockchip_mux_recalced_data: represent a pin iomux data.
  * @num: bank number.
@@ -804,597 +826,109 @@ static void rockchip_get_recalced_mux(struct 
rockchip_pin_bank *bank, int pin,
 }
 
 static struct rockchip_mux_route_data px30_mux_route_data[] = {
-   {
-   /* cif-d2m0 */
-   .bank_num = 2,
-   .pin = 0,
-   .func = 1,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 7),
-   }, {
-   /* cif-d2m1 */
-   .bank_num = 3,
-   .pin = 3,
-   .func = 3,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 7) | BIT(7),
-   }, {
-   /* pdm-m0 */
-   .bank_num = 3,
-   .pin = 22,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 8),
-   }, {
-   /* pdm-m1 */
-   .bank_num = 2,
-   .pin = 22,
-   .func = 1,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 8) | BIT(8),
-   }, {
-   /* uart2-rxm0 */
-   .bank_num = 1,
-   .pin = 27,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 10),
-   }, {
-   /* uart2-rxm1 */
-   .bank_num = 2,
-   .pin = 14,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 10) | BIT(10),
-   }, {
-   /* uart3-rxm0 */
-   .bank_num = 0,
-   .pin = 17,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 9),
-   }, {
-   /* uart3-rxm1 */
-   .bank_num = 1,
-   .pin = 15,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 9) | BIT(9),
-   },
+   MR_SAME(2, 0, 1, 0x184, RK_GENMASK_VAL(7, 7, 0)), /* cif-d2m0 */
+   MR_SAME(3, 3, 3, 0x184, RK_GENMASK_VAL(7, 7, 1)), /* cif-d2m1 */
+   MR_SAME(3, 22, 2, 0x184, RK_GENMASK_VAL(8, 8, 0)), /* pdm-m0 */
+   MR_SAME(2, 22, 1, 0x184, RK_GENMASK_VAL(8, 8, 1)), /* pdm-m1 */
+   MR_SAME(0, 17, 2, 0x184, RK_GENMASK_VAL(9, 9, 0)), /* uart3-rxm0 */
+   MR_SAME(1, 15, 2, 0x184, RK_GENMASK_VAL(9, 9, 1)), /* uart3-rxm1 */
+   MR_SAME(1, 27, 2, 0x184, RK_GENMASK_VAL(10, 10, 0)), /* uart2-rxm0 */
+   MR_SAME(2, 14, 2, 0x184, RK_GENMASK_VAL(10, 10, 1)), /* uart2-rxm1 */
 };
 
 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
-   {
-   /* spi-0 */
-   .bank_num = 1,
-   .pin = 10,
-   .func = 1,
-   .route_offset = 0x144,
-   .route_val = BIT(16 + 3) | BIT(16 + 4),
-   }, {
-   /* spi-1 */
-   .bank_num = 1,
- 

[PATCH 06/13] pinctrl: rockchip: Add RK3399 definitions to separate from other SoCs

[Jianqun Xu]

Add RK3399 definitions to separate from other SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 1be4627f3877..71335ed003b3 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2050,6 +2050,9 @@ static void rk3368_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 #define RK3399_PULL_GRF_OFFSET 0xe040
 #define RK3399_PULL_PMU_OFFSET 0x40
 #define RK3399_DRV_3BITS_PER_PIN   3
+#define RK3399_PULL_BITS_PER_PIN   2
+#define RK3399_PULL_PINS_PER_REG   8
+#define RK3399_PULL_BANK_STRIDE16
 
 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 int pin_num, struct regmap **regmap,
@@ -2062,22 +2065,22 @@ static void rk3399_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3399_PULL_PMU_OFFSET;
 
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+   *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
 
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
-   *bit = pin_num % RK3188_PULL_PINS_PER_REG;
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
+   *bit = pin_num % RK3399_PULL_PINS_PER_REG;
+   *bit *= RK3399_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3399_PULL_GRF_OFFSET;
 
/* correct the offset, as we're starting with the 3rd bank */
*reg -= 0x20;
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
+   *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *bit = (pin_num % RK3399_PULL_PINS_PER_REG);
+   *bit *= RK3399_PULL_BITS_PER_PIN;
}
 }
 
-- 
2.17.1

[PATCH 05/13] pinctrl: rockchip: create irq mapping in gpio_to_irq

[Jianqun Xu]

Remove totally irq mappings create in probe, the gpio irq mapping will
be created when do
gpio_to_irq ->
rockchip_gpio_to_irq ->
irq_create_mapping

This patch can speed up system boot on, also abandon many unused irq
mappings' create.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 28 
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index d34fada39227..1be4627f3877 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3196,7 +3196,7 @@ static void rockchip_irq_demux(struct irq_desc *desc)
 
irq = __ffs(pend);
pend &= ~BIT(irq);
-   virq = irq_linear_revmap(bank->domain, irq);
+   virq = irq_find_mapping(bank->domain, irq);
 
if (!virq) {
dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
@@ -3375,7 +3375,7 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
int ret;
-   int i, j;
+   int i;
 
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
if (!bank->valid) {
@@ -3402,7 +3402,7 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
 
ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
 "rockchip_gpio_irq", handle_level_irq,
-clr, 0, IRQ_GC_INIT_MASK_CACHE);
+clr, 0, 0);
if (ret) {
dev_err(>dev, "could not alloc generic chips for 
bank %s\n",
bank->name);
@@ -3411,14 +3411,6 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
continue;
}
 
-   /*
-* Linux assumes that all interrupts start out disabled/masked.
-* Our driver only uses the concept of masked and always keeps
-* things enabled, so for us that's all masked and all enabled.
-*/
-   writel_relaxed(0x, bank->reg_base + GPIO_INTMASK);
-   writel_relaxed(0x, bank->reg_base + GPIO_INTEN);
-
gc = irq_get_domain_generic_chip(bank->domain, 0);
gc->reg_base = bank->reg_base;
gc->private = bank;
@@ -3435,13 +3427,17 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
 
+   /*
+* Linux assumes that all interrupts start out disabled/masked.
+* Our driver only uses the concept of masked and always keeps
+* things enabled, so for us that's all masked and all enabled.
+*/
+   writel_relaxed(0x, bank->reg_base + GPIO_INTMASK);
+   writel_relaxed(0x, bank->reg_base + GPIO_INTEN);
+   gc->mask_cache = 0x;
+
irq_set_chained_handler_and_data(bank->irq,
 rockchip_irq_demux, bank);
-
-   /* map the gpio irqs here, when the clock is still running */
-   for (j = 0 ; j < 32 ; j++)
-   irq_create_mapping(bank->domain, j);
-
clk_disable(bank->clk);
}
 
-- 
2.17.1

[PATCH 07/13] pinctrl: rockchip: Add RK3368 definitions to separate from other SoCs

[Jianqun Xu]

Add RK3368 definitions to separate from other SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 34 ++
 1 file changed, 20 insertions(+), 14 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 71335ed003b3..8e3fa9011165 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1987,6 +1987,9 @@ static void rk3308_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
 #define RK3368_PULL_GRF_OFFSET 0x100
 #define RK3368_PULL_PMU_OFFSET 0x10
+#define RK3368_PULL_BITS_PER_PIN   2
+#define RK3368_PULL_PINS_PER_REG   8
+#define RK3368_PULL_BANK_STRIDE16
 
 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1999,25 +2002,28 @@ static void rk3368_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3368_PULL_PMU_OFFSET;
 
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
-   *bit = pin_num % RK3188_PULL_PINS_PER_REG;
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4);
+   *bit = pin_num % RK3368_PULL_PINS_PER_REG;
+   *bit *= RK3368_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_PULL_GRF_OFFSET;
 
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3368_PULL_BANK_STRIDE;
+   *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *bit = (pin_num % RK3368_PULL_PINS_PER_REG);
+   *bit *= RK3368_PULL_BITS_PER_PIN;
}
 }
 
 #define RK3368_DRV_PMU_OFFSET  0x20
 #define RK3368_DRV_GRF_OFFSET  0x200
+#define RK3368_DRV_BITS_PER_PIN2
+#define RK3368_DRV_PINS_PER_REG8
+#define RK3368_DRV_BANK_STRIDE 16
 
 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -2030,20 +2036,20 @@ static void rk3368_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3368_DRV_PMU_OFFSET;
 
-   *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
-   *bit = pin_num % RK3288_DRV_PINS_PER_REG;
-   *bit *= RK3288_DRV_BITS_PER_PIN;
+   *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4);
+   *bit = pin_num % RK3368_DRV_PINS_PER_REG;
+   *bit *= RK3368_DRV_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_DRV_GRF_OFFSET;
 
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
-   *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
-   *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3368_DRV_BANK_STRIDE;
+   *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
-   *bit *= RK3288_DRV_BITS_PER_PIN;
+   *bit = (pin_num % RK3368_DRV_PINS_PER_REG);
+   *bit *= RK3368_DRV_BITS_PER_PIN;
}
 }
 
-- 
2.17.1

[PATCH 08/13] pinctrl: rockchip: Add RK3308 definitions to separate from other SoCs

[Jianqun Xu]

Add RK3308 definitions to separate from other SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 22 ++
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 8e3fa9011165..44f051af97c6 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1952,6 +1952,9 @@ static void rk3228_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 }
 
 #define RK3308_PULL_OFFSET 0xa0
+#define RK3308_PULL_BITS_PER_PIN   2
+#define RK3308_PULL_PINS_PER_REG   8
+#define RK3308_PULL_BANK_STRIDE16
 
 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1961,14 +1964,17 @@ static void rk3308_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
*regmap = info->regmap_base;
*reg = RK3308_PULL_OFFSET;
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3308_PULL_BANK_STRIDE;
+   *reg += ((pin_num / RK3308_PULL_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *bit = (pin_num % RK3308_PULL_PINS_PER_REG);
+   *bit *= RK3308_PULL_BITS_PER_PIN;
 }
 
 #define RK3308_DRV_GRF_OFFSET  0x100
+#define RK3308_DRV_BITS_PER_PIN2
+#define RK3308_DRV_PINS_PER_REG8
+#define RK3308_DRV_BANK_STRIDE 16
 
 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1978,11 +1984,11 @@ static void rk3308_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
*regmap = info->regmap_base;
*reg = RK3308_DRV_GRF_OFFSET;
-   *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
-   *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3308_DRV_BANK_STRIDE;
+   *reg += ((pin_num / RK3308_DRV_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
-   *bit *= RK3288_DRV_BITS_PER_PIN;
+   *bit = (pin_num % RK3308_DRV_PINS_PER_REG);
+   *bit *= RK3308_DRV_BITS_PER_PIN;
 }
 
 #define RK3368_PULL_GRF_OFFSET 0x100
-- 
2.17.1

[PATCH 04/13] pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq

[Jianqun Xu]

There need to enable pclk_gpio when do irq_create_mapping, since it will
do access to gpio controller.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index ec509ef8bd8d..d34fada39227 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3155,7 +3155,9 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, 
unsigned offset)
if (!bank->domain)
return -ENXIO;
 
+   clk_enable(bank->clk);
virq = irq_create_mapping(bank->domain, offset);
+   clk_disable(bank->clk);
 
return (virq) ? : -ENXIO;
 }
-- 
2.17.1

[PATCH 02/13] pinctrl: rockchip: modify rockchip_pin_ctrl to const struct

[Jianqun Xu]

The rockchip_pin_ctrl structure actually is soc data structure for
pinctrl on Rockchip SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 62 +++---
 1 file changed, 31 insertions(+), 31 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index bc465da68f26..77c1e6744f6c 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -392,7 +392,7 @@ struct rockchip_pinctrl {
struct regmap   *regmap_pull;
struct regmap   *regmap_pmu;
struct device   *dev;
-   struct rockchip_pin_ctrl*ctrl;
+   const struct rockchip_pin_ctrl  *ctrl;
struct pinctrl_desc pctl;
struct pinctrl_dev  *pctl_dev;
struct rockchip_pin_group   *groups;
@@ -779,7 +779,7 @@ static void rockchip_get_recalced_mux(struct 
rockchip_pin_bank *bank, int pin,
  int *reg, u8 *bit, int *mask)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_mux_recalced_data *data;
int i;
 
@@ -1396,7 +1396,7 @@ static bool rockchip_get_mux_route(struct 
rockchip_pin_bank *bank, int pin,
   int mux, u32 *loc, u32 *reg, u32 *value)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_mux_route_data *data;
int i;
 
@@ -2112,7 +2112,7 @@ static int rockchip_get_drive_perpin(struct 
rockchip_pin_bank *bank,
 int pin_num)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u32 data, temp, rmask_bits;
@@ -2189,7 +2189,7 @@ static int rockchip_set_drive_perpin(struct 
rockchip_pin_bank *bank,
 int pin_num, int strength)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret, i;
u32 data, rmask, rmask_bits, temp;
@@ -2297,7 +2297,7 @@ static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret, pull_type;
u8 bit;
@@ -2341,7 +2341,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank 
*bank,
int pin_num, int pull)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret, i, pull_type;
u8 bit;
@@ -2427,7 +2427,7 @@ static int rk3328_calc_schmitt_reg_and_bit(struct 
rockchip_pin_bank *bank,
 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u8 bit;
@@ -2449,7 +2449,7 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank 
*bank,
int pin_num, int enable)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u8 bit;
@@ -2621,7 +2621,7 @@ static const struct pinmux_ops rockchip_pmx_ops = {
  * Pinconf_ops handling
  */
 
-static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
+static bool rockchip_pinconf_pull_valid(const struct rockchip_pin_ctrl *ctrl,
enum pin_config_param pull)
 {
switch (ctrl->type) {
@@ -3366,7 +3366,7 @@ static void rockchip_irq_disable(struct irq_data *d)
 static int rockchip_interrupts_register(struct platform_device *pdev,
struct rockchip_pinctrl *info)
 {
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_pin_bank *bank = ctrl->pin_banks;
unsigned int c

[PATCH 03/13] pinctrl: rockchip: make driver be tristate module

[Jianqun Xu]

Make pinctrl-rockchip driver to be tristate module, support to build as
a module, this is useful for GKI.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/Kconfig| 2 +-
 drivers/pinctrl/pinctrl-rockchip.c | 7 +++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8828613c4e0e..dd4874e2ac67 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -207,7 +207,7 @@ config PINCTRL_OXNAS
select MFD_SYSCON
 
 config PINCTRL_ROCKCHIP
-   bool
+   tristate "Rockchip gpio and pinctrl driver"
select PINMUX
select GENERIC_PINCONF
select GENERIC_IRQ_CHIP
diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 77c1e6744f6c..ec509ef8bd8d 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -16,10 +16,12 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -4259,6 +4261,7 @@ static const struct of_device_id 
rockchip_pinctrl_dt_match[] = {
.data = _pin_ctrl },
{},
 };
+MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
 
 static struct platform_driver rockchip_pinctrl_driver = {
.probe  = rockchip_pinctrl_probe,
@@ -4274,3 +4277,7 @@ static int __init rockchip_pinctrl_drv_register(void)
return platform_driver_register(_pinctrl_driver);
 }
 postcore_initcall(rockchip_pinctrl_drv_register);
+
+MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pinctrl-rockchip");
-- 
2.17.1

[PATCH 01/13] pinctrl: rockchip: add nr_pins to rockchip_pin_ctrl

[Jianqun Xu]

Add nr_pins to rockchip_pin_ctrl by hand, instead of calculating during
driver probe. This patch is prepare work for making rockchip_pin_ctrl to
be const type.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 22 --
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index c07324d1f265..bc465da68f26 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3573,6 +3573,7 @@ static struct rockchip_pin_ctrl 
*rockchip_pinctrl_get_soc_data(
struct rockchip_pin_ctrl *ctrl;
struct rockchip_pin_bank *bank;
int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
+   u32 nr_pins;
 
match = of_match_node(rockchip_pinctrl_dt_match, node);
ctrl = (struct rockchip_pin_ctrl *)match->data;
@@ -3599,13 +3600,14 @@ static struct rockchip_pin_ctrl 
*rockchip_pinctrl_get_soc_data(
drv_pmu_offs = ctrl->pmu_drv_offset;
drv_grf_offs = ctrl->grf_drv_offset;
bank = ctrl->pin_banks;
+   nr_pins = 0;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
int bank_pins = 0;
 
raw_spin_lock_init(>slock);
bank->drvdata = d;
-   bank->pin_base = ctrl->nr_pins;
-   ctrl->nr_pins += bank->nr_pins;
+   bank->pin_base = nr_pins;
+   nr_pins += bank->nr_pins;
 
/* calculate iomux and drv offsets */
for (j = 0; j < 4; j++) {
@@ -3692,6 +3694,8 @@ static struct rockchip_pin_ctrl 
*rockchip_pinctrl_get_soc_data(
}
}
 
+   WARN_ON(nr_pins != ctrl->nr_pins);
+
return ctrl;
 }
 
@@ -3852,6 +3856,7 @@ static struct rockchip_pin_bank px30_pin_banks[] = {
 static struct rockchip_pin_ctrl px30_pin_ctrl = {
.pin_banks  = px30_pin_banks,
.nr_banks   = ARRAY_SIZE(px30_pin_banks),
+   .nr_pins= 128,
.label  = "PX30-GPIO",
.type   = PX30,
.grf_mux_offset = 0x0,
@@ -3876,6 +3881,7 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = {
 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.pin_banks  = rv1108_pin_banks,
.nr_banks   = ARRAY_SIZE(rv1108_pin_banks),
+   .nr_pins= 128,
.label  = "RV1108-GPIO",
.type   = RV1108,
.grf_mux_offset = 0x10,
@@ -3897,6 +3903,7 @@ static struct rockchip_pin_bank rk2928_pin_banks[] = {
 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
.pin_banks  = rk2928_pin_banks,
.nr_banks   = ARRAY_SIZE(rk2928_pin_banks),
+   .nr_pins= 128,
.label  = "RK2928-GPIO",
.type   = RK2928,
.grf_mux_offset = 0xa8,
@@ -3912,6 +3919,7 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = {
 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
.pin_banks  = rk3036_pin_banks,
.nr_banks   = ARRAY_SIZE(rk3036_pin_banks),
+   .nr_pins= 96,
.label  = "RK3036-GPIO",
.type   = RK2928,
.grf_mux_offset = 0xa8,
@@ -3930,6 +3938,7 @@ static struct rockchip_pin_bank rk3066a_pin_banks[] = {
 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
.pin_banks  = rk3066a_pin_banks,
.nr_banks   = ARRAY_SIZE(rk3066a_pin_banks),
+   .nr_pins= 176,
.label  = "RK3066a-GPIO",
.type   = RK2928,
.grf_mux_offset = 0xa8,
@@ -3946,6 +3955,7 @@ static struct rockchip_pin_bank rk3066b_pin_banks[] = {
 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
.pin_banks  = rk3066b_pin_banks,
.nr_banks   = ARRAY_SIZE(rk3066b_pin_banks),
+   .nr_pins= 128,
.label  = "RK3066b-GPIO",
.type   = RK3066B,
.grf_mux_offset = 0x60,
@@ -3961,6 +3971,7 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = {
 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
.pin_banks  = rk3128_pin_banks,
.nr_banks   = ARRAY_SIZE(rk3128_pin_banks),
+   .nr_pins= 128,
.label  = "RK3128-GPIO",
.type   = RK3128,
  

[PATCH RESEND 00/13] pinctrl: rockchip: prepare work for split driver

[Jianqun Xu]

This serial patchs include 12 codingstyle patches and 1 bug fix (enable
gpio pclk for rockchip_gpio_to_irq).

Also it's prepare for split driver work.

Jianqun Xu (13):
  pinctrl: rockchip: add nr_pins to rockchip_pin_ctrl
  pinctrl: rockchip: modify rockchip_pin_ctrl to const struct
  pinctrl: rockchip: make driver be tristate module
  pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq
  pinctrl: rockchip: create irq mapping in gpio_to_irq
  pinctrl: rockchip: Add RK3399 definitions to separate from other SoCs
  pinctrl: rockchip: Add RK3368 definitions to separate from other SoCs
  pinctrl: rockchip: Add RK3308 definitions to separate from other SoCs
  pinctrl: rockchip: Add RK3228 definitions to separate from other SoCs
  pinctrl: rockchip: Add RK3288 definitions to separate from other SoCs
  pinctrl: rockchip: Add RK3128 definitions to separate from other SoCs
  pinctrl: rockchip: define common codes without special chip name
  pinctrl: rockchip: do codingstyle by adding mux route definitions

 drivers/pinctrl/Kconfig|   2 +-
 drivers/pinctrl/pinctrl-rockchip.c | 933 -
 2 files changed, 261 insertions(+), 674 deletions(-)

-- 
2.17.1

[PATCH 09/13] pinctrl: rockchip: do codingstyle

[Jianqun Xu]

Add RK3228 definitions to separate from other SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 22 ++
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 44f051af97c6..ec6a1a08f8b1 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1918,6 +1918,9 @@ static void rk3288_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 }
 
 #define RK3228_PULL_OFFSET 0x100
+#define RK3228_PULL_BITS_PER_PIN   2
+#define RK3228_PULL_PINS_PER_REG   8
+#define RK3228_PULL_BANK_STRIDE16
 
 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1927,14 +1930,17 @@ static void rk3228_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
*regmap = info->regmap_base;
*reg = RK3228_PULL_OFFSET;
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3228_PULL_BANK_STRIDE;
+   *reg += ((pin_num / RK3228_PULL_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *bit = (pin_num % RK3228_PULL_PINS_PER_REG);
+   *bit *= RK3228_PULL_BITS_PER_PIN;
 }
 
 #define RK3228_DRV_GRF_OFFSET  0x200
+#define RK3228_DRV_BITS_PER_PIN2
+#define RK3228_DRV_PINS_PER_REG8
+#define RK3228_DRV_BANK_STRIDE 16
 
 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1944,11 +1950,11 @@ static void rk3228_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
*regmap = info->regmap_base;
*reg = RK3228_DRV_GRF_OFFSET;
-   *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
-   *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3228_DRV_BANK_STRIDE;
+   *reg += ((pin_num / RK3228_DRV_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
-   *bit *= RK3288_DRV_BITS_PER_PIN;
+   *bit = (pin_num % RK3228_DRV_PINS_PER_REG);
+   *bit *= RK3228_DRV_BITS_PER_PIN;
 }
 
 #define RK3308_PULL_OFFSET 0xa0
-- 
2.17.1

[PATCH 13/13] pinctrl: rockchip: do codingstyle by adding mux route definitions

[Jianqun Xu]

Add MR_SAME/MR_GRF/MR_PMU definitions, and update data in mux route
structures.

This patch do nothing change, only do some codingstyle.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 674 +
 1 file changed, 104 insertions(+), 570 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 71a367896297..50558ffcc05c 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -78,6 +78,9 @@ enum rockchip_pinctrl_type {
 #define ROCKCHIP_DRV_3BITS_PER_PIN (3)
 #define ROCKCHIP_DRV_BITS_PER_PIN  (2)
 
+#define RK_GENMASK_VAL(h, l, v) \
+   (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l
+
 /**
  * @type: iomux variant using IOMUX_* constants
  * @offset: if initialized to -1 it will be autocalculated, by specifying
@@ -290,6 +293,25 @@ struct rockchip_pin_bank {
.pull_type[3] = pull3,  \
}
 
+#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG)
\
+   {   \
+   .bank_num   = ID,   \
+   .pin= PIN,  \
+   .func   = FUNC, \
+   .route_offset   = REG,  \
+   .route_val  = VAL,  \
+   .route_location = FLAG, \
+   }
+
+#define MR_SAME(ID, PIN, FUNC, REG, VAL) \
+   PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
+
+#define MR_GRF(ID, PIN, FUNC, REG, VAL)\
+   PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
+
+#define MR_PMU(ID, PIN, FUNC, REG, VAL)\
+   PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
+
 /**
  * struct rockchip_mux_recalced_data: represent a pin iomux data.
  * @num: bank number.
@@ -804,597 +826,109 @@ static void rockchip_get_recalced_mux(struct 
rockchip_pin_bank *bank, int pin,
 }
 
 static struct rockchip_mux_route_data px30_mux_route_data[] = {
-   {
-   /* cif-d2m0 */
-   .bank_num = 2,
-   .pin = 0,
-   .func = 1,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 7),
-   }, {
-   /* cif-d2m1 */
-   .bank_num = 3,
-   .pin = 3,
-   .func = 3,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 7) | BIT(7),
-   }, {
-   /* pdm-m0 */
-   .bank_num = 3,
-   .pin = 22,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 8),
-   }, {
-   /* pdm-m1 */
-   .bank_num = 2,
-   .pin = 22,
-   .func = 1,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 8) | BIT(8),
-   }, {
-   /* uart2-rxm0 */
-   .bank_num = 1,
-   .pin = 27,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 10),
-   }, {
-   /* uart2-rxm1 */
-   .bank_num = 2,
-   .pin = 14,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 10) | BIT(10),
-   }, {
-   /* uart3-rxm0 */
-   .bank_num = 0,
-   .pin = 17,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 9),
-   }, {
-   /* uart3-rxm1 */
-   .bank_num = 1,
-   .pin = 15,
-   .func = 2,
-   .route_offset = 0x184,
-   .route_val = BIT(16 + 9) | BIT(9),
-   },
+   MR_SAME(2, 0, 1, 0x184, RK_GENMASK_VAL(7, 7, 0)), /* cif-d2m0 */
+   MR_SAME(3, 3, 3, 0x184, RK_GENMASK_VAL(7, 7, 1)), /* cif-d2m1 */
+   MR_SAME(3, 22, 2, 0x184, RK_GENMASK_VAL(8, 8, 0)), /* pdm-m0 */
+   MR_SAME(2, 22, 1, 0x184, RK_GENMASK_VAL(8, 8, 1)), /* pdm-m1 */
+   MR_SAME(0, 17, 2, 0x184, RK_GENMASK_VAL(9, 9, 0)), /* uart3-rxm0 */
+   MR_SAME(1, 15, 2, 0x184, RK_GENMASK_VAL(9, 9, 1)), /* uart3-rxm1 */
+   MR_SAME(1, 27, 2, 0x184, RK_GENMASK_VAL(10, 10, 0)), /* uart2-rxm0 */
+   MR_SAME(2, 14, 2, 0x184, RK_GENMASK_VAL(10, 10, 1)), /* uart2-rxm1 */
 };
 
 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
-   {
-   /* spi-0 */
-   .bank_num = 1,
-   .pin = 10,
-   .func = 1,
-   .route_offset = 0x144,
-   .route_val = BIT(16 + 3) | BIT(16 + 4),
-   }, {
-   /* spi-1 */
-   .bank_num = 1,
- 

[PATCH 12/13] pinctrl: rockchip: define common codes without special chip name

[Jianqun Xu]

Modify RK3399_DRV_3BITS_PER_PIN to ROCKCHIP_DRV_3BITS_PER_PIN, and
modify RK3288_DRV_BITS_PER_PIN to ROCKCHIP_DRV_BITS_PER_PIN.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 3b74455dcdb2..71a367896297 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -75,6 +75,9 @@ enum rockchip_pinctrl_type {
 #define IOMUX_WIDTH_3BIT   BIT(4)
 #define IOMUX_WIDTH_2BIT   BIT(5)
 
+#define ROCKCHIP_DRV_3BITS_PER_PIN (3)
+#define ROCKCHIP_DRV_BITS_PER_PIN  (2)
+
 /**
  * @type: iomux variant using IOMUX_* constants
  * @offset: if initialized to -1 it will be autocalculated, by specifying
@@ -2074,7 +2077,6 @@ static void rk3368_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
 #define RK3399_PULL_GRF_OFFSET 0xe040
 #define RK3399_PULL_PMU_OFFSET 0x40
-#define RK3399_DRV_3BITS_PER_PIN   3
 #define RK3399_PULL_BITS_PER_PIN   2
 #define RK3399_PULL_PINS_PER_REG   8
 #define RK3399_PULL_BANK_STRIDE16
@@ -2154,7 +2156,7 @@ static int rockchip_get_drive_perpin(struct 
rockchip_pin_bank *bank,
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
-   rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+   rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
@@ -2197,7 +2199,7 @@ static int rockchip_get_drive_perpin(struct 
rockchip_pin_bank *bank,
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
-   rmask_bits = RK3288_DRV_BITS_PER_PIN;
+   rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
break;
default:
dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
@@ -2251,7 +2253,7 @@ static int rockchip_set_drive_perpin(struct 
rockchip_pin_bank *bank,
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
-   rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+   rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
@@ -2291,7 +2293,7 @@ static int rockchip_set_drive_perpin(struct 
rockchip_pin_bank *bank,
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
-   rmask_bits = RK3288_DRV_BITS_PER_PIN;
+   rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
break;
default:
dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
-- 
2.17.1

[PATCH 11/13] pinctrl: rockchip: do codingstyle

[Jianqun Xu]

Add RK3128 definitions to separate from other SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 04e7027ec8e1..3b74455dcdb2 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1799,6 +1799,8 @@ static void rk2928_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
 };
 
 #define RK3128_PULL_OFFSET 0x118
+#define RK3128_PULL_PINS_PER_REG   16
+#define RK3128_PULL_BANK_STRIDE8
 
 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 int pin_num, struct regmap **regmap,
@@ -1808,10 +1810,10 @@ static void rk3128_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
*regmap = info->regmap_base;
*reg = RK3128_PULL_OFFSET;
-   *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
-   *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3128_PULL_BANK_STRIDE;
+   *reg += ((pin_num / RK3128_PULL_PINS_PER_REG) * 4);
 
-   *bit = pin_num % RK2928_PULL_PINS_PER_REG;
+   *bit = pin_num % RK3128_PULL_PINS_PER_REG;
 }
 
 #define RK3188_PULL_OFFSET 0x164
-- 
2.17.1

[PATCH 07/13] pinctrl: rockchip: do codingstyle

[Jianqun Xu]

Add RK3368 definitions to separate from other SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 34 ++
 1 file changed, 20 insertions(+), 14 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 71335ed003b3..8e3fa9011165 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1987,6 +1987,9 @@ static void rk3308_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
 #define RK3368_PULL_GRF_OFFSET 0x100
 #define RK3368_PULL_PMU_OFFSET 0x10
+#define RK3368_PULL_BITS_PER_PIN   2
+#define RK3368_PULL_PINS_PER_REG   8
+#define RK3368_PULL_BANK_STRIDE16
 
 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1999,25 +2002,28 @@ static void rk3368_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3368_PULL_PMU_OFFSET;
 
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
-   *bit = pin_num % RK3188_PULL_PINS_PER_REG;
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4);
+   *bit = pin_num % RK3368_PULL_PINS_PER_REG;
+   *bit *= RK3368_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_PULL_GRF_OFFSET;
 
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3368_PULL_BANK_STRIDE;
+   *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *bit = (pin_num % RK3368_PULL_PINS_PER_REG);
+   *bit *= RK3368_PULL_BITS_PER_PIN;
}
 }
 
 #define RK3368_DRV_PMU_OFFSET  0x20
 #define RK3368_DRV_GRF_OFFSET  0x200
+#define RK3368_DRV_BITS_PER_PIN2
+#define RK3368_DRV_PINS_PER_REG8
+#define RK3368_DRV_BANK_STRIDE 16
 
 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -2030,20 +2036,20 @@ static void rk3368_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3368_DRV_PMU_OFFSET;
 
-   *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
-   *bit = pin_num % RK3288_DRV_PINS_PER_REG;
-   *bit *= RK3288_DRV_BITS_PER_PIN;
+   *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4);
+   *bit = pin_num % RK3368_DRV_PINS_PER_REG;
+   *bit *= RK3368_DRV_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_DRV_GRF_OFFSET;
 
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
-   *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
-   *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3368_DRV_BANK_STRIDE;
+   *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
-   *bit *= RK3288_DRV_BITS_PER_PIN;
+   *bit = (pin_num % RK3368_DRV_PINS_PER_REG);
+   *bit *= RK3368_DRV_BITS_PER_PIN;
}
 }
 
-- 
2.17.1

[PATCH 08/13] pinctrl: rockchip: do codingstyle

[Jianqun Xu]

Add RK3308 definitions to separate from other SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 22 ++
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 8e3fa9011165..44f051af97c6 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1952,6 +1952,9 @@ static void rk3228_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 }
 
 #define RK3308_PULL_OFFSET 0xa0
+#define RK3308_PULL_BITS_PER_PIN   2
+#define RK3308_PULL_PINS_PER_REG   8
+#define RK3308_PULL_BANK_STRIDE16
 
 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1961,14 +1964,17 @@ static void rk3308_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
*regmap = info->regmap_base;
*reg = RK3308_PULL_OFFSET;
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3308_PULL_BANK_STRIDE;
+   *reg += ((pin_num / RK3308_PULL_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *bit = (pin_num % RK3308_PULL_PINS_PER_REG);
+   *bit *= RK3308_PULL_BITS_PER_PIN;
 }
 
 #define RK3308_DRV_GRF_OFFSET  0x100
+#define RK3308_DRV_BITS_PER_PIN2
+#define RK3308_DRV_PINS_PER_REG8
+#define RK3308_DRV_BANK_STRIDE 16
 
 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1978,11 +1984,11 @@ static void rk3308_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 
*regmap = info->regmap_base;
*reg = RK3308_DRV_GRF_OFFSET;
-   *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
-   *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3308_DRV_BANK_STRIDE;
+   *reg += ((pin_num / RK3308_DRV_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
-   *bit *= RK3288_DRV_BITS_PER_PIN;
+   *bit = (pin_num % RK3308_DRV_PINS_PER_REG);
+   *bit *= RK3308_DRV_BITS_PER_PIN;
 }
 
 #define RK3368_PULL_GRF_OFFSET 0x100
-- 
2.17.1

[PATCH 10/13] pinctrl: rockchip: do codingstyle

[Jianqun Xu]

Add RK3288 definitons to separate from other SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 21 +
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index ec6a1a08f8b1..04e7027ec8e1 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1855,6 +1855,11 @@ static void rk3188_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
 }
 
 #define RK3288_PULL_OFFSET 0x140
+#define RK3288_PULL_PMU_OFFSET 0x64
+#define RK3288_PULL_BITS_PER_PIN   2
+#define RK3288_PULL_PINS_PER_REG   8
+#define RK3288_PULL_BANK_STRIDE16
+
 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
@@ -1864,22 +1869,22 @@ static void rk3288_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
-   *reg = RK3188_PULL_PMU_OFFSET;
+   *reg = RK3288_PULL_PMU_OFFSET;
 
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
-   *bit = pin_num % RK3188_PULL_PINS_PER_REG;
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4);
+   *bit = pin_num % RK3288_PULL_PINS_PER_REG;
+   *bit *= RK3288_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3288_PULL_OFFSET;
 
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3288_PULL_BANK_STRIDE;
+   *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *bit = (pin_num % RK3288_PULL_PINS_PER_REG);
+   *bit *= RK3288_PULL_BITS_PER_PIN;
}
 }
 
-- 
2.17.1

[PATCH 06/13] pinctrl: rockchip: do codingstyle

[Jianqun Xu]

Add RK3399 definitions to separate from other SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 1be4627f3877..71335ed003b3 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2050,6 +2050,9 @@ static void rk3368_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 #define RK3399_PULL_GRF_OFFSET 0xe040
 #define RK3399_PULL_PMU_OFFSET 0x40
 #define RK3399_DRV_3BITS_PER_PIN   3
+#define RK3399_PULL_BITS_PER_PIN   2
+#define RK3399_PULL_PINS_PER_REG   8
+#define RK3399_PULL_BANK_STRIDE16
 
 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 int pin_num, struct regmap **regmap,
@@ -2062,22 +2065,22 @@ static void rk3399_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3399_PULL_PMU_OFFSET;
 
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+   *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
 
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
-   *bit = pin_num % RK3188_PULL_PINS_PER_REG;
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
+   *bit = pin_num % RK3399_PULL_PINS_PER_REG;
+   *bit *= RK3399_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3399_PULL_GRF_OFFSET;
 
/* correct the offset, as we're starting with the 3rd bank */
*reg -= 0x20;
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
+   *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *bit = (pin_num % RK3399_PULL_PINS_PER_REG);
+   *bit *= RK3399_PULL_BITS_PER_PIN;
}
 }
 
-- 
2.17.1

[PATCH 05/13] pinctrl: rockchip: create irq mapping in gpio_to_irq

[Jianqun Xu]

Remove totally irq mappings create in probe, the gpio irq mapping will
be created when do
gpio_to_irq ->
rockchip_gpio_to_irq ->
irq_create_mapping

This patch can speed up system boot on, also abandon many unused irq
mappings' create.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 28 
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index d34fada39227..1be4627f3877 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3196,7 +3196,7 @@ static void rockchip_irq_demux(struct irq_desc *desc)
 
irq = __ffs(pend);
pend &= ~BIT(irq);
-   virq = irq_linear_revmap(bank->domain, irq);
+   virq = irq_find_mapping(bank->domain, irq);
 
if (!virq) {
dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
@@ -3375,7 +3375,7 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
int ret;
-   int i, j;
+   int i;
 
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
if (!bank->valid) {
@@ -3402,7 +3402,7 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
 
ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
 "rockchip_gpio_irq", handle_level_irq,
-clr, 0, IRQ_GC_INIT_MASK_CACHE);
+clr, 0, 0);
if (ret) {
dev_err(>dev, "could not alloc generic chips for 
bank %s\n",
bank->name);
@@ -3411,14 +3411,6 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
continue;
}
 
-   /*
-* Linux assumes that all interrupts start out disabled/masked.
-* Our driver only uses the concept of masked and always keeps
-* things enabled, so for us that's all masked and all enabled.
-*/
-   writel_relaxed(0x, bank->reg_base + GPIO_INTMASK);
-   writel_relaxed(0x, bank->reg_base + GPIO_INTEN);
-
gc = irq_get_domain_generic_chip(bank->domain, 0);
gc->reg_base = bank->reg_base;
gc->private = bank;
@@ -3435,13 +3427,17 @@ static int rockchip_interrupts_register(struct 
platform_device *pdev,
gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
 
+   /*
+* Linux assumes that all interrupts start out disabled/masked.
+* Our driver only uses the concept of masked and always keeps
+* things enabled, so for us that's all masked and all enabled.
+*/
+   writel_relaxed(0x, bank->reg_base + GPIO_INTMASK);
+   writel_relaxed(0x, bank->reg_base + GPIO_INTEN);
+   gc->mask_cache = 0x;
+
irq_set_chained_handler_and_data(bank->irq,
 rockchip_irq_demux, bank);
-
-   /* map the gpio irqs here, when the clock is still running */
-   for (j = 0 ; j < 32 ; j++)
-   irq_create_mapping(bank->domain, j);
-
clk_disable(bank->clk);
}
 
-- 
2.17.1

[PATCH 06/13] pinctrl: rockchip: do codingstyle

[Jianqun Xu]

Add RK3399 definitions to separate from other SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 1be4627f3877..71335ed003b3 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2050,6 +2050,9 @@ static void rk3368_calc_drv_reg_and_bit(struct 
rockchip_pin_bank *bank,
 #define RK3399_PULL_GRF_OFFSET 0xe040
 #define RK3399_PULL_PMU_OFFSET 0x40
 #define RK3399_DRV_3BITS_PER_PIN   3
+#define RK3399_PULL_BITS_PER_PIN   2
+#define RK3399_PULL_PINS_PER_REG   8
+#define RK3399_PULL_BANK_STRIDE16
 
 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 int pin_num, struct regmap **regmap,
@@ -2062,22 +2065,22 @@ static void rk3399_calc_pull_reg_and_bit(struct 
rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3399_PULL_PMU_OFFSET;
 
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+   *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
 
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
-   *bit = pin_num % RK3188_PULL_PINS_PER_REG;
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
+   *bit = pin_num % RK3399_PULL_PINS_PER_REG;
+   *bit *= RK3399_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3399_PULL_GRF_OFFSET;
 
/* correct the offset, as we're starting with the 3rd bank */
*reg -= 0x20;
-   *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
-   *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+   *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
+   *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
 
-   *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
-   *bit *= RK3188_PULL_BITS_PER_PIN;
+   *bit = (pin_num % RK3399_PULL_PINS_PER_REG);
+   *bit *= RK3399_PULL_BITS_PER_PIN;
}
 }
 
-- 
2.17.1

[PATCH 03/13] pinctrl: rockchip: make driver be tristate module

[Jianqun Xu]

Make pinctrl-rockchip driver to be tristate module, support to build as
a module, this is useful for GKI.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/Kconfig| 2 +-
 drivers/pinctrl/pinctrl-rockchip.c | 7 +++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8828613c4e0e..dd4874e2ac67 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -207,7 +207,7 @@ config PINCTRL_OXNAS
select MFD_SYSCON
 
 config PINCTRL_ROCKCHIP
-   bool
+   tristate "Rockchip gpio and pinctrl driver"
select PINMUX
select GENERIC_PINCONF
select GENERIC_IRQ_CHIP
diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index 77c1e6744f6c..ec509ef8bd8d 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -16,10 +16,12 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -4259,6 +4261,7 @@ static const struct of_device_id 
rockchip_pinctrl_dt_match[] = {
.data = _pin_ctrl },
{},
 };
+MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
 
 static struct platform_driver rockchip_pinctrl_driver = {
.probe  = rockchip_pinctrl_probe,
@@ -4274,3 +4277,7 @@ static int __init rockchip_pinctrl_drv_register(void)
return platform_driver_register(_pinctrl_driver);
 }
 postcore_initcall(rockchip_pinctrl_drv_register);
+
+MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pinctrl-rockchip");
-- 
2.17.1

[PATCH 02/13] pinctrl: rockchip: modify rockchip_pin_ctrl to const struct

[Jianqun Xu]

The rockchip_pin_ctrl structure actually is soc data structure for
pinctrl on Rockchip SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 62 +++---
 1 file changed, 31 insertions(+), 31 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index bc465da68f26..77c1e6744f6c 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -392,7 +392,7 @@ struct rockchip_pinctrl {
struct regmap   *regmap_pull;
struct regmap   *regmap_pmu;
struct device   *dev;
-   struct rockchip_pin_ctrl*ctrl;
+   const struct rockchip_pin_ctrl  *ctrl;
struct pinctrl_desc pctl;
struct pinctrl_dev  *pctl_dev;
struct rockchip_pin_group   *groups;
@@ -779,7 +779,7 @@ static void rockchip_get_recalced_mux(struct 
rockchip_pin_bank *bank, int pin,
  int *reg, u8 *bit, int *mask)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_mux_recalced_data *data;
int i;
 
@@ -1396,7 +1396,7 @@ static bool rockchip_get_mux_route(struct 
rockchip_pin_bank *bank, int pin,
   int mux, u32 *loc, u32 *reg, u32 *value)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_mux_route_data *data;
int i;
 
@@ -2112,7 +2112,7 @@ static int rockchip_get_drive_perpin(struct 
rockchip_pin_bank *bank,
 int pin_num)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u32 data, temp, rmask_bits;
@@ -2189,7 +2189,7 @@ static int rockchip_set_drive_perpin(struct 
rockchip_pin_bank *bank,
 int pin_num, int strength)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret, i;
u32 data, rmask, rmask_bits, temp;
@@ -2297,7 +2297,7 @@ static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret, pull_type;
u8 bit;
@@ -2341,7 +2341,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank 
*bank,
int pin_num, int pull)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret, i, pull_type;
u8 bit;
@@ -2427,7 +2427,7 @@ static int rk3328_calc_schmitt_reg_and_bit(struct 
rockchip_pin_bank *bank,
 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u8 bit;
@@ -2449,7 +2449,7 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank 
*bank,
int pin_num, int enable)
 {
struct rockchip_pinctrl *info = bank->drvdata;
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u8 bit;
@@ -2621,7 +2621,7 @@ static const struct pinmux_ops rockchip_pmx_ops = {
  * Pinconf_ops handling
  */
 
-static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
+static bool rockchip_pinconf_pull_valid(const struct rockchip_pin_ctrl *ctrl,
enum pin_config_param pull)
 {
switch (ctrl->type) {
@@ -3366,7 +3366,7 @@ static void rockchip_irq_disable(struct irq_data *d)
 static int rockchip_interrupts_register(struct platform_device *pdev,
struct rockchip_pinctrl *info)
 {
-   struct rockchip_pin_ctrl *ctrl = info->ctrl;
+   const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_pin_bank *bank = ctrl->pin_banks;
unsigned int c

[PATCH 01/13] pinctrl: rockchip: add nr_pins to rockchip_pin_ctrl

[Jianqun Xu]

Add nr_pins to rockchip_pin_ctrl by hand, instead of calculating during
driver probe. This patch is prepare work for making rockchip_pin_ctrl to
be const type.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 22 --
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index c07324d1f265..bc465da68f26 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3573,6 +3573,7 @@ static struct rockchip_pin_ctrl 
*rockchip_pinctrl_get_soc_data(
struct rockchip_pin_ctrl *ctrl;
struct rockchip_pin_bank *bank;
int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
+   u32 nr_pins;
 
match = of_match_node(rockchip_pinctrl_dt_match, node);
ctrl = (struct rockchip_pin_ctrl *)match->data;
@@ -3599,13 +3600,14 @@ static struct rockchip_pin_ctrl 
*rockchip_pinctrl_get_soc_data(
drv_pmu_offs = ctrl->pmu_drv_offset;
drv_grf_offs = ctrl->grf_drv_offset;
bank = ctrl->pin_banks;
+   nr_pins = 0;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
int bank_pins = 0;
 
raw_spin_lock_init(>slock);
bank->drvdata = d;
-   bank->pin_base = ctrl->nr_pins;
-   ctrl->nr_pins += bank->nr_pins;
+   bank->pin_base = nr_pins;
+   nr_pins += bank->nr_pins;
 
/* calculate iomux and drv offsets */
for (j = 0; j < 4; j++) {
@@ -3692,6 +3694,8 @@ static struct rockchip_pin_ctrl 
*rockchip_pinctrl_get_soc_data(
}
}
 
+   WARN_ON(nr_pins != ctrl->nr_pins);
+
return ctrl;
 }
 
@@ -3852,6 +3856,7 @@ static struct rockchip_pin_bank px30_pin_banks[] = {
 static struct rockchip_pin_ctrl px30_pin_ctrl = {
.pin_banks  = px30_pin_banks,
.nr_banks   = ARRAY_SIZE(px30_pin_banks),
+   .nr_pins= 128,
.label  = "PX30-GPIO",
.type   = PX30,
.grf_mux_offset = 0x0,
@@ -3876,6 +3881,7 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = {
 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.pin_banks  = rv1108_pin_banks,
.nr_banks   = ARRAY_SIZE(rv1108_pin_banks),
+   .nr_pins= 128,
.label  = "RV1108-GPIO",
.type   = RV1108,
.grf_mux_offset = 0x10,
@@ -3897,6 +3903,7 @@ static struct rockchip_pin_bank rk2928_pin_banks[] = {
 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
.pin_banks  = rk2928_pin_banks,
.nr_banks   = ARRAY_SIZE(rk2928_pin_banks),
+   .nr_pins= 128,
.label  = "RK2928-GPIO",
.type   = RK2928,
.grf_mux_offset = 0xa8,
@@ -3912,6 +3919,7 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = {
 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
.pin_banks  = rk3036_pin_banks,
.nr_banks   = ARRAY_SIZE(rk3036_pin_banks),
+   .nr_pins= 96,
.label  = "RK3036-GPIO",
.type   = RK2928,
.grf_mux_offset = 0xa8,
@@ -3930,6 +3938,7 @@ static struct rockchip_pin_bank rk3066a_pin_banks[] = {
 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
.pin_banks  = rk3066a_pin_banks,
.nr_banks   = ARRAY_SIZE(rk3066a_pin_banks),
+   .nr_pins= 176,
.label  = "RK3066a-GPIO",
.type   = RK2928,
.grf_mux_offset = 0xa8,
@@ -3946,6 +3955,7 @@ static struct rockchip_pin_bank rk3066b_pin_banks[] = {
 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
.pin_banks  = rk3066b_pin_banks,
.nr_banks   = ARRAY_SIZE(rk3066b_pin_banks),
+   .nr_pins= 128,
.label  = "RK3066b-GPIO",
.type   = RK3066B,
.grf_mux_offset = 0x60,
@@ -3961,6 +3971,7 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = {
 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
.pin_banks  = rk3128_pin_banks,
.nr_banks   = ARRAY_SIZE(rk3128_pin_banks),
+   .nr_pins= 128,
.label  = "RK3128-GPIO",
.type   = RK3128,
  

[PATCH 04/13] pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq

[Jianqun Xu]

There need to enable pclk_gpio when do irq_create_mapping, since it will
do access to gpio controller.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index ec509ef8bd8d..d34fada39227 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3155,7 +3155,9 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, 
unsigned offset)
if (!bank->domain)
return -ENXIO;
 
+   clk_enable(bank->clk);
virq = irq_create_mapping(bank->domain, offset);
+   clk_disable(bank->clk);
 
return (virq) ? : -ENXIO;
 }
-- 
2.17.1

[PATCH 00/13] pinctrl: rockchip: prepare work for split driver

[Jianqun Xu]

This serial patchs include 12 codingstyle patches and 1 bug fix (enable
gpio pclk for rockchip_gpio_to_irq).

Also it's prepare for split driver work.

Jianqun Xu (13):
  pinctrl: rockchip: add nr_pins to rockchip_pin_ctrl
  pinctrl: rockchip: modify rockchip_pin_ctrl to const struct
  pinctrl: rockchip: make driver be tristate module
  pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq
  pinctrl: rockchip: create irq mapping in gpio_to_irq
  pinctrl: rockchip: do codingstyle
  pinctrl: rockchip: do codingstyle
  pinctrl: rockchip: do codingstyle
  pinctrl: rockchip: do codingstyle
  pinctrl: rockchip: do codingstyle
  pinctrl: rockchip: do codingstyle
  pinctrl: rockchip: define common codes without special chip name
  pinctrl: rockchip: do codingstyle by adding mux route definitions

 drivers/pinctrl/Kconfig|   2 +-
 drivers/pinctrl/pinctrl-rockchip.c | 933 -
 2 files changed, 261 insertions(+), 674 deletions(-)

-- 
2.17.1

[PATCH] mm/cma: fix NULL pointer dereference when cma could not be activated

[Jianqun Xu]

In some case the cma area could not be activated, but the cma_alloc be
used under this case, then the kernel will crash caused by NULL pointer
dereference.

Add bitmap valid check in cma_alloc to avoid this issue.

Signed-off-by: Jianqun Xu 
---
 mm/cma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mm/cma.c b/mm/cma.c
index 0463ad2ce06b..488496fa2972 100644
--- a/mm/cma.c
+++ b/mm/cma.c
@@ -425,7 +425,7 @@ struct page *cma_alloc(struct cma *cma, size_t count, 
unsigned int align,
struct page *page = NULL;
int ret = -ENOMEM;
 
-   if (!cma || !cma->count)
+   if (!cma || !cma->count || !cma->bitmap)
return NULL;
 
pr_debug("%s(cma %p, count %zu, align %d)\n", __func__, (void *)cma,
-- 
2.17.1

[PATCH v3 2/2] pinctrl: rockchip: add rk3308 SoC support

[Jianqun Xu]

This patch do support pinctrl for RK3308 SoCs.

Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
changes since v2:
- Fix increase offset according to iomux width

changes since v1:
- Add type case for pull get/set
- Add Reviewed-by: Heiko Stuebner 

 drivers/pinctrl/pinctrl-rockchip.c | 382 -
 1 file changed, 381 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index dc0bbf198cbc..fc9a2a9959d9 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -58,6 +58,7 @@ enum rockchip_pinctrl_type {
RK3128,
RK3188,
RK3288,
+   RK3308,
RK3368,
RK3399,
 };
@@ -70,6 +71,7 @@ enum rockchip_pinctrl_type {
 #define IOMUX_SOURCE_PMU   BIT(2)
 #define IOMUX_UNROUTED BIT(3)
 #define IOMUX_WIDTH_3BIT   BIT(4)
+#define IOMUX_WIDTH_2BIT   BIT(5)
 
 /**
  * @type: iomux variant using IOMUX_* constants
@@ -656,6 +658,100 @@ static  struct rockchip_mux_recalced_data 
rk3128_mux_recalced_data[] = {
},
 };
 
+static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
+   {
+   .num = 1,
+   .pin = 14,
+   .reg = 0x28,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 15,
+   .reg = 0x2c,
+   .bit = 0,
+   .mask = 0x3
+   }, {
+   .num = 1,
+   .pin = 18,
+   .reg = 0x30,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 19,
+   .reg = 0x30,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 20,
+   .reg = 0x30,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 21,
+   .reg = 0x34,
+   .bit = 0,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 22,
+   .reg = 0x34,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 23,
+   .reg = 0x34,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 12,
+   .reg = 0x68,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 13,
+   .reg = 0x68,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 2,
+   .pin = 2,
+   .reg = 0x608,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 3,
+   .reg = 0x608,
+   .bit = 4,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 16,
+   .reg = 0x610,
+   .bit = 8,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 10,
+   .reg = 0x610,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 11,
+   .reg = 0x610,
+   .bit = 4,
+   .mask = 0x7
+   },
+};
+
 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
{
.num = 2,
@@ -982,6 +1078,192 @@ static struct rockchip_mux_route_data 
rk3288_mux_route_data[] = {
},
 };
 
+static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
+   {
+   /* rtc_clk */
+   .bank_num = 0,
+   .pin = 19,
+   .func = 1,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 0) | BIT(0),
+   }, {
+   /* uart2_rxm0 */
+   .bank_num = 1,
+   .pin = 22,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3),
+   }, {
+   /* uart2_rxm1 */
+   .bank_num = 4,
+   .pin = 26,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
+   }, {
+   /* i2c3_sdam0 */
+   .bank_num = 0,
+   .pin = 15,
+   .func = 2,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16 + 9),
+   }, {
+   /* i2c3_sdam1 */
+   .bank_num = 3,
+   .pin = 12,
+   .func = 2,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
+   }, {
+   /* i2c3_sdam2 */
+   .bank_num = 2,
+   .pin = 0,
+   .func = 3

[PATCH v3 1/2] dt-bindings: pinctrl: rockchip: add rk3308 SoC support

[Jianqun Xu]

Add rk3308 SoC support to rockchip pinctrl.

Acked-by: Rob Herring 
Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
changes since v2:
- Add Acked-by: Rob Herring 

changes since v1:
- Add Reviewed-by: Heiko Stuebner 

 Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 0919db294c17..2113cfaa26e6 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -29,6 +29,7 @@ Required properties for iomux controller:
"rockchip,rk3188-pinctrl":  for Rockchip RK3188
"rockchip,rk3228-pinctrl":  for Rockchip RK3228
"rockchip,rk3288-pinctrl":  for Rockchip RK3288
+   "rockchip,rk3308-pinctrl":  for Rockchip RK3308
"rockchip,rk3328-pinctrl":  for Rockchip RK3328
"rockchip,rk3368-pinctrl":  for Rockchip RK3368
"rockchip,rk3399-pinctrl":  for Rockchip RK3399
-- 
2.17.1

[PATCH v3 0/2] pinctrl: rockchip: support rk3308 SoC

[Jianqun Xu]

Add support for rk3308 SoC from rockchip.

Jianqun Xu (2):
  dt-bindings: pinctrl: rockchip: add rk3308 SoC support
  pinctrl: rockchip: add rk3308 SoC support

 .../bindings/pinctrl/rockchip,pinctrl.txt |   1 +
 drivers/pinctrl/pinctrl-rockchip.c| 382 +-
 2 files changed, 382 insertions(+), 1 deletion(-)

-- 
changes since v2:
- Add Acked-by: Rob Herring 

changes since v1:
- Add type case for pull get/set
- Add Reviewed-by: Heiko Stuebner 


2.17.1

[PATCH v3 2/2] pinctrl: rockchip: add rk3308 SoC support

[Jianqun Xu]

This patch do support pinctrl for RK3308 SoCs.

Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
changes since v2:
- Fix increase offset according to iomux width

changes since v1:
- Add type case for pull get/set
- Add Reviewed-by: Heiko Stuebner 

 drivers/pinctrl/pinctrl-rockchip.c | 382 -
 1 file changed, 381 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index dc0bbf198cbc..fc9a2a9959d9 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -58,6 +58,7 @@ enum rockchip_pinctrl_type {
RK3128,
RK3188,
RK3288,
+   RK3308,
RK3368,
RK3399,
 };
@@ -70,6 +71,7 @@ enum rockchip_pinctrl_type {
 #define IOMUX_SOURCE_PMU   BIT(2)
 #define IOMUX_UNROUTED BIT(3)
 #define IOMUX_WIDTH_3BIT   BIT(4)
+#define IOMUX_WIDTH_2BIT   BIT(5)
 
 /**
  * @type: iomux variant using IOMUX_* constants
@@ -656,6 +658,100 @@ static  struct rockchip_mux_recalced_data 
rk3128_mux_recalced_data[] = {
},
 };
 
+static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
+   {
+   .num = 1,
+   .pin = 14,
+   .reg = 0x28,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 15,
+   .reg = 0x2c,
+   .bit = 0,
+   .mask = 0x3
+   }, {
+   .num = 1,
+   .pin = 18,
+   .reg = 0x30,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 19,
+   .reg = 0x30,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 20,
+   .reg = 0x30,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 21,
+   .reg = 0x34,
+   .bit = 0,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 22,
+   .reg = 0x34,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 23,
+   .reg = 0x34,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 12,
+   .reg = 0x68,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 13,
+   .reg = 0x68,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 2,
+   .pin = 2,
+   .reg = 0x608,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 3,
+   .reg = 0x608,
+   .bit = 4,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 16,
+   .reg = 0x610,
+   .bit = 8,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 10,
+   .reg = 0x610,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 11,
+   .reg = 0x610,
+   .bit = 4,
+   .mask = 0x7
+   },
+};
+
 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
{
.num = 2,
@@ -982,6 +1078,192 @@ static struct rockchip_mux_route_data 
rk3288_mux_route_data[] = {
},
 };
 
+static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
+   {
+   /* rtc_clk */
+   .bank_num = 0,
+   .pin = 19,
+   .func = 1,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 0) | BIT(0),
+   }, {
+   /* uart2_rxm0 */
+   .bank_num = 1,
+   .pin = 22,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3),
+   }, {
+   /* uart2_rxm1 */
+   .bank_num = 4,
+   .pin = 26,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
+   }, {
+   /* i2c3_sdam0 */
+   .bank_num = 0,
+   .pin = 15,
+   .func = 2,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16 + 9),
+   }, {
+   /* i2c3_sdam1 */
+   .bank_num = 3,
+   .pin = 12,
+   .func = 2,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
+   }, {
+   /* i2c3_sdam2 */
+   .bank_num = 2,
+   .pin = 0,
+   .func = 3

[PATCH v3 0/2] pinctrl: rockchip: support rk3308 SoC

[Jianqun Xu]

Add support for rk3308 SoC from rockchip.

Jianqun Xu (2):
  dt-bindings: pinctrl: rockchip: add rk3308 SoC support
  pinctrl: rockchip: add rk3308 SoC support

 .../bindings/pinctrl/rockchip,pinctrl.txt |   1 +
 drivers/pinctrl/pinctrl-rockchip.c| 382 +-
 2 files changed, 382 insertions(+), 1 deletion(-)

-- 
changes since v2:
- Add Acked-by: Rob Herring 

changes since v1:
- Add type case for pull get/set
- Add Reviewed-by: Heiko Stuebner 


2.17.1

[PATCH v3 1/2] dt-bindings: pinctrl: rockchip: add rk3308 SoC support

[Jianqun Xu]

Add rk3308 SoC support to rockchip pinctrl.

Acked-by: Rob Herring 
Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
changes since v2:
- Add Acked-by: Rob Herring 

changes since v1:
- Add Reviewed-by: Heiko Stuebner 

 Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 0919db294c17..2113cfaa26e6 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -29,6 +29,7 @@ Required properties for iomux controller:
"rockchip,rk3188-pinctrl":  for Rockchip RK3188
"rockchip,rk3228-pinctrl":  for Rockchip RK3228
"rockchip,rk3288-pinctrl":  for Rockchip RK3288
+   "rockchip,rk3308-pinctrl":  for Rockchip RK3308
"rockchip,rk3328-pinctrl":  for Rockchip RK3328
"rockchip,rk3368-pinctrl":  for Rockchip RK3368
"rockchip,rk3399-pinctrl":  for Rockchip RK3399
-- 
2.17.1

[PATCH v2 2/2] pinctrl: rockchip: add rk3308 SoC support

[Jianqun Xu]

This patch do support pinctrl for RK3308 SoCs.

Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
changes since v1:
- Add type case for pull get/set
- Add Reviewed-by: Heiko Stuebner 

 drivers/pinctrl/pinctrl-rockchip.c | 379 +
 1 file changed, 379 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index dc0bbf198cbc..15eff9676ad0 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -58,6 +58,7 @@ enum rockchip_pinctrl_type {
RK3128,
RK3188,
RK3288,
+   RK3308,
RK3368,
RK3399,
 };
@@ -70,6 +71,7 @@ enum rockchip_pinctrl_type {
 #define IOMUX_SOURCE_PMU   BIT(2)
 #define IOMUX_UNROUTED BIT(3)
 #define IOMUX_WIDTH_3BIT   BIT(4)
+#define IOMUX_WIDTH_2BIT   BIT(5)
 
 /**
  * @type: iomux variant using IOMUX_* constants
@@ -656,6 +658,100 @@ static  struct rockchip_mux_recalced_data 
rk3128_mux_recalced_data[] = {
},
 };
 
+static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
+   {
+   .num = 1,
+   .pin = 14,
+   .reg = 0x28,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 15,
+   .reg = 0x2c,
+   .bit = 0,
+   .mask = 0x3
+   }, {
+   .num = 1,
+   .pin = 18,
+   .reg = 0x30,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 19,
+   .reg = 0x30,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 20,
+   .reg = 0x30,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 21,
+   .reg = 0x34,
+   .bit = 0,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 22,
+   .reg = 0x34,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 23,
+   .reg = 0x34,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 12,
+   .reg = 0x68,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 13,
+   .reg = 0x68,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 2,
+   .pin = 2,
+   .reg = 0x608,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 3,
+   .reg = 0x608,
+   .bit = 4,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 16,
+   .reg = 0x610,
+   .bit = 8,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 10,
+   .reg = 0x610,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 11,
+   .reg = 0x610,
+   .bit = 4,
+   .mask = 0x7
+   },
+};
+
 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
{
.num = 2,
@@ -982,6 +1078,192 @@ static struct rockchip_mux_route_data 
rk3288_mux_route_data[] = {
},
 };
 
+static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
+   {
+   /* rtc_clk */
+   .bank_num = 0,
+   .pin = 19,
+   .func = 1,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 0) | BIT(0),
+   }, {
+   /* uart2_rxm0 */
+   .bank_num = 1,
+   .pin = 22,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3),
+   }, {
+   /* uart2_rxm1 */
+   .bank_num = 4,
+   .pin = 26,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
+   }, {
+   /* i2c3_sdam0 */
+   .bank_num = 0,
+   .pin = 15,
+   .func = 2,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16 + 9),
+   }, {
+   /* i2c3_sdam1 */
+   .bank_num = 3,
+   .pin = 12,
+   .func = 2,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
+   }, {
+   /* i2c3_sdam2 */
+   .bank_num = 2,
+   .pin = 0,
+   .func = 3,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16

[PATCH v2 1/2] dt-bindings: pinctrl: rockchip: add rk3308 SoC support

[Jianqun Xu]

Add rk3308 SoC support to rockchip pinctrl.

Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
changes since v1:
- Add Reviewed-by: Heiko Stuebner 

 Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 0919db294c17..2113cfaa26e6 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -29,6 +29,7 @@ Required properties for iomux controller:
"rockchip,rk3188-pinctrl":  for Rockchip RK3188
"rockchip,rk3228-pinctrl":  for Rockchip RK3228
"rockchip,rk3288-pinctrl":  for Rockchip RK3288
+   "rockchip,rk3308-pinctrl":  for Rockchip RK3308
"rockchip,rk3328-pinctrl":  for Rockchip RK3328
"rockchip,rk3368-pinctrl":  for Rockchip RK3368
"rockchip,rk3399-pinctrl":  for Rockchip RK3399
-- 
2.17.1

[PATCH v2 0/2] pinctrl: rockchip: support rk3308 SoC

[Jianqun Xu]

Add support for rk3308 SoC from rockchip.

Jianqun Xu (2):
  dt-bindings: pinctrl: rockchip: add rk3308 SoC support
  pinctrl: rockchip: add rk3308 SoC support

 .../bindings/pinctrl/rockchip,pinctrl.txt |   1 +
 drivers/pinctrl/pinctrl-rockchip.c| 379 ++
 2 files changed, 380 insertions(+)

-- 
changes since v1:
- Add type case for pull get/set
- Add Reviewed-by: Heiko Stuebner 


2.17.1

[PATCH v2 1/2] dt-bindings: pinctrl: rockchip: add rk3308 SoC support

[Jianqun Xu]

Add rk3308 SoC support to rockchip pinctrl.

Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
changes since v1:
- Add Reviewed-by: Heiko Stuebner 

 Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 0919db294c17..2113cfaa26e6 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -29,6 +29,7 @@ Required properties for iomux controller:
"rockchip,rk3188-pinctrl":  for Rockchip RK3188
"rockchip,rk3228-pinctrl":  for Rockchip RK3228
"rockchip,rk3288-pinctrl":  for Rockchip RK3288
+   "rockchip,rk3308-pinctrl":  for Rockchip RK3308
"rockchip,rk3328-pinctrl":  for Rockchip RK3328
"rockchip,rk3368-pinctrl":  for Rockchip RK3368
"rockchip,rk3399-pinctrl":  for Rockchip RK3399
-- 
2.17.1

[PATCH v2 0/2] pinctrl: rockchip: support rk3308 SoC

[Jianqun Xu]

Add support for rk3308 SoC from rockchip.

Jianqun Xu (2):
  dt-bindings: pinctrl: rockchip: add rk3308 SoC support
  pinctrl: rockchip: add rk3308 SoC support

 .../bindings/pinctrl/rockchip,pinctrl.txt |   1 +
 drivers/pinctrl/pinctrl-rockchip.c| 377 ++
 2 files changed, 378 insertions(+)

--
changes since v1:
- add Reviewed-by: Heiko Stuebner , thanks Heiko

2.17.1

[PATCH v2 2/2] pinctrl: rockchip: add rk3308 SoC support

[Jianqun Xu]

This patch do support pinctrl for RK3308 SoCs.

Reviewed-by: Heiko Stuebner 
Signed-off-by: Jianqun Xu 
---
changes since v1:
- Add Reviewed-by: Heiko Stuebner 

 drivers/pinctrl/pinctrl-rockchip.c | 377 +
 1 file changed, 377 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index dc0bbf198cbc..9e19db402ee5 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -58,6 +58,7 @@ enum rockchip_pinctrl_type {
RK3128,
RK3188,
RK3288,
+   RK3308,
RK3368,
RK3399,
 };
@@ -70,6 +71,7 @@ enum rockchip_pinctrl_type {
 #define IOMUX_SOURCE_PMU   BIT(2)
 #define IOMUX_UNROUTED BIT(3)
 #define IOMUX_WIDTH_3BIT   BIT(4)
+#define IOMUX_WIDTH_2BIT   BIT(5)
 
 /**
  * @type: iomux variant using IOMUX_* constants
@@ -656,6 +658,100 @@ static  struct rockchip_mux_recalced_data 
rk3128_mux_recalced_data[] = {
},
 };
 
+static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
+   {
+   .num = 1,
+   .pin = 14,
+   .reg = 0x28,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 15,
+   .reg = 0x2c,
+   .bit = 0,
+   .mask = 0x3
+   }, {
+   .num = 1,
+   .pin = 18,
+   .reg = 0x30,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 19,
+   .reg = 0x30,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 20,
+   .reg = 0x30,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 21,
+   .reg = 0x34,
+   .bit = 0,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 22,
+   .reg = 0x34,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 23,
+   .reg = 0x34,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 12,
+   .reg = 0x68,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 13,
+   .reg = 0x68,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 2,
+   .pin = 2,
+   .reg = 0x608,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 3,
+   .reg = 0x608,
+   .bit = 4,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 16,
+   .reg = 0x610,
+   .bit = 8,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 10,
+   .reg = 0x610,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 11,
+   .reg = 0x610,
+   .bit = 4,
+   .mask = 0x7
+   },
+};
+
 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
{
.num = 2,
@@ -982,6 +1078,192 @@ static struct rockchip_mux_route_data 
rk3288_mux_route_data[] = {
},
 };
 
+static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
+   {
+   /* rtc_clk */
+   .bank_num = 0,
+   .pin = 19,
+   .func = 1,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 0) | BIT(0),
+   }, {
+   /* uart2_rxm0 */
+   .bank_num = 1,
+   .pin = 22,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3),
+   }, {
+   /* uart2_rxm1 */
+   .bank_num = 4,
+   .pin = 26,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
+   }, {
+   /* i2c3_sdam0 */
+   .bank_num = 0,
+   .pin = 15,
+   .func = 2,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16 + 9),
+   }, {
+   /* i2c3_sdam1 */
+   .bank_num = 3,
+   .pin = 12,
+   .func = 2,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
+   }, {
+   /* i2c3_sdam2 */
+   .bank_num = 2,
+   .pin = 0,
+   .func = 3,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9

[PATCH 2/2] pinctrl: rockchip: add rk3308 SoC support

[Jianqun Xu]

This patch do support pinctrl for RK3308 SoCs.

Signed-off-by: Jianqun Xu 
---
 drivers/pinctrl/pinctrl-rockchip.c | 377 +
 1 file changed, 377 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index dc0bbf198cbc..9e19db402ee5 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -58,6 +58,7 @@ enum rockchip_pinctrl_type {
RK3128,
RK3188,
RK3288,
+   RK3308,
RK3368,
RK3399,
 };
@@ -70,6 +71,7 @@ enum rockchip_pinctrl_type {
 #define IOMUX_SOURCE_PMU   BIT(2)
 #define IOMUX_UNROUTED BIT(3)
 #define IOMUX_WIDTH_3BIT   BIT(4)
+#define IOMUX_WIDTH_2BIT   BIT(5)
 
 /**
  * @type: iomux variant using IOMUX_* constants
@@ -656,6 +658,100 @@ static  struct rockchip_mux_recalced_data 
rk3128_mux_recalced_data[] = {
},
 };
 
+static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
+   {
+   .num = 1,
+   .pin = 14,
+   .reg = 0x28,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 15,
+   .reg = 0x2c,
+   .bit = 0,
+   .mask = 0x3
+   }, {
+   .num = 1,
+   .pin = 18,
+   .reg = 0x30,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 19,
+   .reg = 0x30,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 20,
+   .reg = 0x30,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 21,
+   .reg = 0x34,
+   .bit = 0,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 22,
+   .reg = 0x34,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 23,
+   .reg = 0x34,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 12,
+   .reg = 0x68,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 13,
+   .reg = 0x68,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 2,
+   .pin = 2,
+   .reg = 0x608,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 3,
+   .reg = 0x608,
+   .bit = 4,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 16,
+   .reg = 0x610,
+   .bit = 8,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 10,
+   .reg = 0x610,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 11,
+   .reg = 0x610,
+   .bit = 4,
+   .mask = 0x7
+   },
+};
+
 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
{
.num = 2,
@@ -982,6 +1078,192 @@ static struct rockchip_mux_route_data 
rk3288_mux_route_data[] = {
},
 };
 
+static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
+   {
+   /* rtc_clk */
+   .bank_num = 0,
+   .pin = 19,
+   .func = 1,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 0) | BIT(0),
+   }, {
+   /* uart2_rxm0 */
+   .bank_num = 1,
+   .pin = 22,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3),
+   }, {
+   /* uart2_rxm1 */
+   .bank_num = 4,
+   .pin = 26,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
+   }, {
+   /* i2c3_sdam0 */
+   .bank_num = 0,
+   .pin = 15,
+   .func = 2,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16 + 9),
+   }, {
+   /* i2c3_sdam1 */
+   .bank_num = 3,
+   .pin = 12,
+   .func = 2,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
+   }, {
+   /* i2c3_sdam2 */
+   .bank_num = 2,
+   .pin = 0,
+   .func = 3,
+   .route_offset = 0x608,
+   .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
+   }, {
+   /* i2s-8ch-1-sclktxm0 */
+   .bank_num = 1

[PATCH 0/2] pinctrl: rockchip: support rk3308 SoC

[Jianqun Xu]

Add support for rk3308 SoC from rockchip.

Jianqun Xu (2):
  dt-bindings: pinctrl: rockchip: add rk3308 SoC support
  pinctrl: rockchip: add rk3308 SoC support

 .../bindings/pinctrl/rockchip,pinctrl.txt |   1 +
 drivers/pinctrl/pinctrl-rockchip.c| 377 ++
 2 files changed, 378 insertions(+)

-- 
2.17.1

[PATCH 1/2] dt-bindings: pinctrl: rockchip: add rk3308 SoC support

[Jianqun Xu]

Add rk3308 SoC support to rockchip pinctrl.

Signed-off-by: Jianqun Xu 
---
 Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 0919db294c17..2113cfaa26e6 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -29,6 +29,7 @@ Required properties for iomux controller:
"rockchip,rk3188-pinctrl":  for Rockchip RK3188
"rockchip,rk3228-pinctrl":  for Rockchip RK3228
"rockchip,rk3288-pinctrl":  for Rockchip RK3288
+   "rockchip,rk3308-pinctrl":  for Rockchip RK3308
"rockchip,rk3328-pinctrl":  for Rockchip RK3328
"rockchip,rk3368-pinctrl":  for Rockchip RK3368
"rockchip,rk3399-pinctrl":  for Rockchip RK3399
-- 
2.17.1

[PATCH] pinctrl: rockchip: add rk3308 SoC support

[Jianqun Xu]

This patch do support pinctrl for RK3308 SoCs.

Signed-off-by: Jianqun Xu 
---
 .../bindings/pinctrl/rockchip,pinctrl.txt |   1 +
 drivers/pinctrl/pinctrl-rockchip.c| 420 ++
 2 files changed, 421 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt 
b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 0919db294c17..2113cfaa26e6 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -29,6 +29,7 @@ Required properties for iomux controller:
"rockchip,rk3188-pinctrl":  for Rockchip RK3188
"rockchip,rk3228-pinctrl":  for Rockchip RK3228
"rockchip,rk3288-pinctrl":  for Rockchip RK3288
+   "rockchip,rk3308-pinctrl":  for Rockchip RK3308
"rockchip,rk3328-pinctrl":  for Rockchip RK3328
"rockchip,rk3368-pinctrl":  for Rockchip RK3368
"rockchip,rk3399-pinctrl":  for Rockchip RK3399
diff --git a/drivers/pinctrl/pinctrl-rockchip.c 
b/drivers/pinctrl/pinctrl-rockchip.c
index dc0bbf198cbc..e91db155bd11 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -58,6 +58,7 @@ enum rockchip_pinctrl_type {
RK3128,
RK3188,
RK3288,
+   RK3308,
RK3368,
RK3399,
 };
@@ -656,6 +657,100 @@ static  struct rockchip_mux_recalced_data 
rk3128_mux_recalced_data[] = {
},
 };
 
+static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
+   {
+   .num = 1,
+   .pin = 14,
+   .reg = 0x28,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 15,
+   .reg = 0x2c,
+   .bit = 0,
+   .mask = 0x3
+   }, {
+   .num = 1,
+   .pin = 18,
+   .reg = 0x30,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 19,
+   .reg = 0x30,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 20,
+   .reg = 0x30,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 21,
+   .reg = 0x34,
+   .bit = 0,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 22,
+   .reg = 0x34,
+   .bit = 4,
+   .mask = 0xf
+   }, {
+   .num = 1,
+   .pin = 23,
+   .reg = 0x34,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 12,
+   .reg = 0x68,
+   .bit = 8,
+   .mask = 0xf
+   }, {
+   .num = 3,
+   .pin = 13,
+   .reg = 0x68,
+   .bit = 12,
+   .mask = 0xf
+   }, {
+   .num = 2,
+   .pin = 2,
+   .reg = 0x608,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 3,
+   .reg = 0x608,
+   .bit = 4,
+   .mask = 0x7
+   }, {
+   .num = 2,
+   .pin = 16,
+   .reg = 0x610,
+   .bit = 8,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 10,
+   .reg = 0x610,
+   .bit = 0,
+   .mask = 0x7
+   }, {
+   .num = 3,
+   .pin = 11,
+   .reg = 0x610,
+   .bit = 4,
+   .mask = 0x7
+   },
+};
+
 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
{
.num = 2,
@@ -982,6 +1077,192 @@ static struct rockchip_mux_route_data 
rk3288_mux_route_data[] = {
},
 };
 
+static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
+   {
+   /* rtc_clk */
+   .bank_num = 0,
+   .pin = 19,
+   .func = 1,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 0) | BIT(0),
+   }, {
+   /* uart2_rxm0 */
+   .bank_num = 1,
+   .pin = 22,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3),
+   }, {
+   /* uart2_rxm1 */
+   .bank_num = 4,
+   .pin = 26,
+   .func = 2,
+   .route_offset = 0x314,
+   .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
+   }, {
+   /* i2c3_sdam0 */
+   .bank_num = 0,
+   .pin 

[PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs

[Jianqun Xu]

This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
talk to NPU part inside SoC.

Signed-off-by: Jianqun Xu 
---
changes since v2:
- only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan

changes since v1:
- remove dfi and dmc

 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 +
 1 file changed, 22 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
new file mode 100644
index ..bb5ebf6608b9
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+
+#include "rk3399.dtsi"
+
+/ {
+   compatible = "rockchip,rk3399pro";
+};
+
+/* Default to enabled since AP talk to NPU part over pcie */
+_phy {
+   status = "okay";
+};
+
+/* Default to enabled since AP talk to NPU part over pcie */
+ {
+   ep-gpios = < RK_PB4 GPIO_ACTIVE_HIGH>;
+   num-lanes = <4>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_clkreqn_cpm>;
+   status = "okay";
+};
-- 
2.17.1

[PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs

[Jianqun Xu]

This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
include rk3399.dtsi. Also enable these nodes:
- pcie/pcie_phy
- sdhci/sdio/emmc/sdmmc

Signed-off-by: Jianqun Xu 
---
changes since v1:
- remove dfi and dmc

 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 74 +
 1 file changed, 74 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
new file mode 100644
index ..b6d433ffa67d
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+
+#include "rk3399.dtsi"
+
+/ {
+   compatible = "rockchip,rk3399pro";
+
+   xin32k: xin32k {
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "xin32k";
+   #clock-cells = <0>;
+   };
+};
+
+_phy {
+   status = "okay";
+};
+
+_phy {
+   status = "okay";
+};
+
+ {
+   ep-gpios = < RK_PB4 GPIO_ACTIVE_HIGH>;
+   num-lanes = <4>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_clkreqn_cpm>;
+   status = "okay";
+};
+
+ {
+   bus-width = <8>;
+   mmc-hs400-1_8v;
+   supports-emmc;
+   non-removable;
+   keep-power-in-suspend;
+   mmc-hs400-enhanced-strobe;
+   status = "okay";
+};
+
+ {
+   clock-frequency = <15000>;
+   clock-freq-min-max = <20 15000>;
+   supports-sdio;
+   bus-width = <4>;
+   disable-wp;
+   cap-sd-highspeed;
+   cap-sdio-irq;
+   keep-power-in-suspend;
+   mmc-pwrseq = <_pwrseq>;
+   non-removable;
+   num-slots = <1>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_bus4 _cmd _clk>;
+   sd-uhs-sdr104;
+   status = "okay";
+};
+
+ {
+   clock-frequency = <15000>;
+   clock-freq-min-max = <40 15000>;
+   supports-sd;
+   bus-width = <4>;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
+   disable-wp;
+   num-slots = <1>;
+   vqmmc-supply = <_sd>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_clk _cmd _cd _bus4>;
+   status = "okay";
+};
-- 
2.17.1

[PATCH 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs

[Jianqun Xu]

This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
include rk3399.dtsi. Also enable these nodes:
- dfi/dmc for ddr devfreq
- pcie/pcie_phy
- sdhci/sdio/emmc/sdmmc

Signed-off-by: Jianqun Xu 
---
 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 111 
 1 file changed, 111 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
new file mode 100644
index ..62f67f857c45
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+
+#include "rk3399.dtsi"
+
+/ {
+   compatible = "rockchip,rk3399pro";
+
+   xin32k: xin32k {
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "xin32k";
+   #clock-cells = <0>;
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   center-supply = <_log>;
+   upthreshold = <40>;
+   downdifferential = <20>;
+   system-status-freq = <
+   /*system status freq(KHz)*/
+   SYS_STATUS_NORMAL   80
+   SYS_STATUS_REBOOT   528000
+   SYS_STATUS_SUSPEND  20
+   SYS_STATUS_VIDEO_1080P  20
+   SYS_STATUS_VIDEO_4K 60
+   SYS_STATUS_VIDEO_4K_10B 80
+   SYS_STATUS_PERFORMANCE  80
+   SYS_STATUS_BOOST40
+   SYS_STATUS_DUALVIEW 60
+   SYS_STATUS_ISP  60
+   >;
+   vop-pn-msch-readlatency = <
+   /* plane_number  readlatency */
+   0   0
+   4   0x20
+   >;
+   vop-bw-dmc-freq = <
+   /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
+   0   762  20
+   763 1893 40
+   18943012 528000
+   3013980
+   >;
+   auto-min-freq = <20>;
+};
+
+_phy {
+   status = "okay";
+};
+
+_phy {
+   status = "okay";
+};
+
+ {
+   ep-gpios = < RK_PB4 GPIO_ACTIVE_HIGH>;
+   num-lanes = <4>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_clkreqn_cpm>;
+   status = "okay";
+};
+
+ {
+   bus-width = <8>;
+   mmc-hs400-1_8v;
+   supports-emmc;
+   non-removable;
+   keep-power-in-suspend;
+   mmc-hs400-enhanced-strobe;
+   status = "okay";
+};
+
+ {
+   clock-frequency = <15000>;
+   clock-freq-min-max = <20 15000>;
+   supports-sdio;
+   bus-width = <4>;
+   disable-wp;
+   cap-sd-highspeed;
+   cap-sdio-irq;
+   keep-power-in-suspend;
+   mmc-pwrseq = <_pwrseq>;
+   non-removable;
+   num-slots = <1>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_bus4 _cmd _clk>;
+   sd-uhs-sdr104;
+   status = "okay";
+};
+
+ {
+   clock-frequency = <15000>;
+   clock-freq-min-max = <40 15000>;
+   supports-sd;
+   bus-width = <4>;
+   cap-mmc-highspeed;
+   cap-sd-highspeed;
+   disable-wp;
+   num-slots = <1>;
+   vqmmc-supply = <_sd>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_clk _cmd _cd _bus4>;
+   status = "okay";
+};
-- 
2.17.1

[PATCH] ASoC: rockchip: add config for rockchip dmaengine pcm register

[Jianqun Xu]

This patch makes the rockchip i2s pcm configurable by adding
rockchip pcm config for devm_snd_dmaengine_pcm_register.

Signed-off-by: Jianqun Xu 
---
 sound/soc/rockchip/Makefile   |  3 ++-
 sound/soc/rockchip/rockchip_i2s.c |  3 ++-
 sound/soc/rockchip/rockchip_pcm.c | 45 +++
 sound/soc/rockchip/rockchip_pcm.h | 14 
 4 files changed, 63 insertions(+), 2 deletions(-)
 create mode 100644 sound/soc/rockchip/rockchip_pcm.c
 create mode 100644 sound/soc/rockchip/rockchip_pcm.h

diff --git a/sound/soc/rockchip/Makefile b/sound/soc/rockchip/Makefile
index 05b078e..65e814d 100644
--- a/sound/soc/rockchip/Makefile
+++ b/sound/soc/rockchip/Makefile
@@ -1,10 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0
 # ROCKCHIP Platform Support
 snd-soc-rockchip-i2s-objs := rockchip_i2s.o
+snd-soc-rockchip-pcm-objs := rockchip_pcm.o
 snd-soc-rockchip-pdm-objs := rockchip_pdm.o
 snd-soc-rockchip-spdif-objs := rockchip_spdif.o
 
-obj-$(CONFIG_SND_SOC_ROCKCHIP_I2S) += snd-soc-rockchip-i2s.o
+obj-$(CONFIG_SND_SOC_ROCKCHIP_I2S) += snd-soc-rockchip-i2s.o 
snd-soc-rockchip-pcm.o
 obj-$(CONFIG_SND_SOC_ROCKCHIP_PDM) += snd-soc-rockchip-pdm.o
 obj-$(CONFIG_SND_SOC_ROCKCHIP_SPDIF) += snd-soc-rockchip-spdif.o
 
diff --git a/sound/soc/rockchip/rockchip_i2s.c 
b/sound/soc/rockchip/rockchip_i2s.c
index 908211e..5e60181 100644
--- a/sound/soc/rockchip/rockchip_i2s.c
+++ b/sound/soc/rockchip/rockchip_i2s.c
@@ -22,6 +22,7 @@
 #include 
 
 #include "rockchip_i2s.h"
+#include "rockchip_pcm.h"
 
 #define DRV_NAME "rockchip-i2s"
 
@@ -667,7 +668,7 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
goto err_suspend;
}
 
-   ret = devm_snd_dmaengine_pcm_register(>dev, NULL, 0);
+   ret = rockchip_pcm_platform_register(>dev);
if (ret) {
dev_err(>dev, "Could not register PCM\n");
return ret;
diff --git a/sound/soc/rockchip/rockchip_pcm.c 
b/sound/soc/rockchip/rockchip_pcm.c
new file mode 100644
index 000..f775383
--- /dev/null
+++ b/sound/soc/rockchip/rockchip_pcm.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "rockchip_pcm.h"
+
+static const struct snd_pcm_hardware snd_rockchip_hardware = {
+   .info   = SNDRV_PCM_INFO_MMAP |
+ SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_PAUSE |
+ SNDRV_PCM_INFO_RESUME,
+   .period_bytes_min   = 32,
+   .period_bytes_max   = 8192,
+   .periods_min= 1,
+   .periods_max= 52,
+   .buffer_bytes_max   = 64 * 1024,
+   .fifo_size  = 32,
+};
+
+static const struct snd_dmaengine_pcm_config rk_dmaengine_pcm_config = {
+   .pcm_hardware = _rockchip_hardware,
+   .prealloc_buffer_size = 32 * 1024,
+};
+
+int rockchip_pcm_platform_register(struct device *dev)
+{
+   return devm_snd_dmaengine_pcm_register(dev, _dmaengine_pcm_config,
+   SND_DMAENGINE_PCM_FLAG_COMPAT);
+}
+EXPORT_SYMBOL_GPL(rockchip_pcm_platform_register);
+
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/rockchip/rockchip_pcm.h 
b/sound/soc/rockchip/rockchip_pcm.h
new file mode 100644
index 000..d6c3611
--- /dev/null
+++ b/sound/soc/rockchip/rockchip_pcm.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _ROCKCHIP_PCM_H
+#define _ROCKCHIP_PCM_H
+
+int rockchip_pcm_platform_register(struct device *dev);
+
+#endif
-- 
1.9.1

[PATCH] ASoC: rockchip: add config for rockchip dmaengine pcm register

[Jianqun Xu]

This patch makes the rockchip i2s pcm configurable by adding
rockchip pcm config for devm_snd_dmaengine_pcm_register.

Signed-off-by: Jianqun Xu 
---
 sound/soc/rockchip/Makefile   |  3 ++-
 sound/soc/rockchip/rockchip_i2s.c |  3 ++-
 sound/soc/rockchip/rockchip_pcm.c | 45 +++
 sound/soc/rockchip/rockchip_pcm.h | 14 
 4 files changed, 63 insertions(+), 2 deletions(-)
 create mode 100644 sound/soc/rockchip/rockchip_pcm.c
 create mode 100644 sound/soc/rockchip/rockchip_pcm.h

diff --git a/sound/soc/rockchip/Makefile b/sound/soc/rockchip/Makefile
index 05b078e..65e814d 100644
--- a/sound/soc/rockchip/Makefile
+++ b/sound/soc/rockchip/Makefile
@@ -1,10 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0
 # ROCKCHIP Platform Support
 snd-soc-rockchip-i2s-objs := rockchip_i2s.o
+snd-soc-rockchip-pcm-objs := rockchip_pcm.o
 snd-soc-rockchip-pdm-objs := rockchip_pdm.o
 snd-soc-rockchip-spdif-objs := rockchip_spdif.o
 
-obj-$(CONFIG_SND_SOC_ROCKCHIP_I2S) += snd-soc-rockchip-i2s.o
+obj-$(CONFIG_SND_SOC_ROCKCHIP_I2S) += snd-soc-rockchip-i2s.o 
snd-soc-rockchip-pcm.o
 obj-$(CONFIG_SND_SOC_ROCKCHIP_PDM) += snd-soc-rockchip-pdm.o
 obj-$(CONFIG_SND_SOC_ROCKCHIP_SPDIF) += snd-soc-rockchip-spdif.o
 
diff --git a/sound/soc/rockchip/rockchip_i2s.c 
b/sound/soc/rockchip/rockchip_i2s.c
index 908211e..5e60181 100644
--- a/sound/soc/rockchip/rockchip_i2s.c
+++ b/sound/soc/rockchip/rockchip_i2s.c
@@ -22,6 +22,7 @@
 #include 
 
 #include "rockchip_i2s.h"
+#include "rockchip_pcm.h"
 
 #define DRV_NAME "rockchip-i2s"
 
@@ -667,7 +668,7 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
goto err_suspend;
}
 
-   ret = devm_snd_dmaengine_pcm_register(>dev, NULL, 0);
+   ret = rockchip_pcm_platform_register(>dev);
if (ret) {
dev_err(>dev, "Could not register PCM\n");
return ret;
diff --git a/sound/soc/rockchip/rockchip_pcm.c 
b/sound/soc/rockchip/rockchip_pcm.c
new file mode 100644
index 000..f775383
--- /dev/null
+++ b/sound/soc/rockchip/rockchip_pcm.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "rockchip_pcm.h"
+
+static const struct snd_pcm_hardware snd_rockchip_hardware = {
+   .info   = SNDRV_PCM_INFO_MMAP |
+ SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_PAUSE |
+ SNDRV_PCM_INFO_RESUME,
+   .period_bytes_min   = 32,
+   .period_bytes_max   = 8192,
+   .periods_min= 1,
+   .periods_max= 52,
+   .buffer_bytes_max   = 64 * 1024,
+   .fifo_size  = 32,
+};
+
+static const struct snd_dmaengine_pcm_config rk_dmaengine_pcm_config = {
+   .pcm_hardware = _rockchip_hardware,
+   .prealloc_buffer_size = 32 * 1024,
+};
+
+int rockchip_pcm_platform_register(struct device *dev)
+{
+   return devm_snd_dmaengine_pcm_register(dev, _dmaengine_pcm_config,
+   SND_DMAENGINE_PCM_FLAG_COMPAT);
+}
+EXPORT_SYMBOL_GPL(rockchip_pcm_platform_register);
+
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/rockchip/rockchip_pcm.h 
b/sound/soc/rockchip/rockchip_pcm.h
new file mode 100644
index 000..d6c3611
--- /dev/null
+++ b/sound/soc/rockchip/rockchip_pcm.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _ROCKCHIP_PCM_H
+#define _ROCKCHIP_PCM_H
+
+int rockchip_pcm_platform_register(struct device *dev);
+
+#endif
-- 
1.9.1

[PATCH] arm64: dts: rockchip: include opp dtsi for rk3399 firefly

[Jianqun Xu]

Add opp tables for cpu cluster0 and cluster1 by including
rk3399-opp.dtsi.

Signed-off-by: Jianqun Xu <jay...@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts 
b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
index eed7e99..7fd4bfc 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
@@ -43,6 +43,7 @@
 /dts-v1/;
 #include 
 #include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
 
 / {
model = "Firefly-RK3399 Board";
-- 
1.9.1

[PATCH] arm64: dts: rockchip: include opp dtsi for rk3399 firefly

[Jianqun Xu]

Add opp tables for cpu cluster0 and cluster1 by including
rk3399-opp.dtsi.

Signed-off-by: Jianqun Xu 
---
 arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts 
b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
index eed7e99..7fd4bfc 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
@@ -43,6 +43,7 @@
 /dts-v1/;
 #include 
 #include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
 
 / {
model = "Firefly-RK3399 Board";
-- 
1.9.1

[PATCH v2 2/3] arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs

[Jianqun Xu]

I2S of RK3368 SoCs keep same as RK3066 SoCs found on Rockchip,
add nodes to support them.

Signed-off-by: Jianqun Xu <jay...@rock-chips.com>
---
changes since v1:
- fix compile error caused by dumplicate label 'i2s1'


 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 38 
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index c9be1b2..74fbcc2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -715,6 +715,30 @@
interrupts = ;
};
 
+   i2s_2ch: i2s-2ch@ff89 {
+   compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+   reg = <0x0 0xff89 0x0 0x1000>;
+   interrupts = ;
+   dmas = <_bus 6>, <_bus 7>;
+   dma-names = "tx", "rx";
+   clock-names = "i2s_clk", "i2s_hclk";
+   clocks = < SCLK_I2S_2CH>, < HCLK_I2S_2CH>;
+   status = "disabled";
+   };
+
+   i2s_8ch: i2s-8ch@ff898000 {
+   compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+   reg = <0x0 0xff898000 0x0 0x1000>;
+   interrupts = ;
+   dmas = <_bus 0>, <_bus 1>;
+   dma-names = "tx", "rx";
+   clock-names = "i2s_clk", "i2s_hclk";
+   clocks = < SCLK_I2S_8CH>, < HCLK_I2S_8CH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_8ch_bus>;
+   status = "disabled";
+   };
+
gic: interrupt-controller@ffb71000 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -917,6 +941,20 @@
};
};
 
+   i2s {
+   i2s_8ch_bus: i2s-8ch-bus {
+   rockchip,pins = <2 12 RK_FUNC_1 
_pull_none>,
+   <2 13 RK_FUNC_1 
_pull_none>,
+   <2 14 RK_FUNC_1 
_pull_none>,
+   <2 15 RK_FUNC_1 
_pull_none>,
+   <2 16 RK_FUNC_1 
_pull_none>,
+   <2 17 RK_FUNC_1 
_pull_none>,
+   <2 18 RK_FUNC_1 
_pull_none>,
+   <2 19 RK_FUNC_1 
_pull_none>,
+   <2 20 RK_FUNC_1 
_pull_none>;
+   };
+   };
+
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <3 8 RK_FUNC_2 _pull_none>;
-- 
1.9.1

[PATCH v2 2/3] arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs

[Jianqun Xu]

I2S of RK3368 SoCs keep same as RK3066 SoCs found on Rockchip,
add nodes to support them.

Signed-off-by: Jianqun Xu 
---
changes since v1:
- fix compile error caused by dumplicate label 'i2s1'


 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 38 
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index c9be1b2..74fbcc2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -715,6 +715,30 @@
interrupts = ;
};
 
+   i2s_2ch: i2s-2ch@ff89 {
+   compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+   reg = <0x0 0xff89 0x0 0x1000>;
+   interrupts = ;
+   dmas = <_bus 6>, <_bus 7>;
+   dma-names = "tx", "rx";
+   clock-names = "i2s_clk", "i2s_hclk";
+   clocks = < SCLK_I2S_2CH>, < HCLK_I2S_2CH>;
+   status = "disabled";
+   };
+
+   i2s_8ch: i2s-8ch@ff898000 {
+   compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+   reg = <0x0 0xff898000 0x0 0x1000>;
+   interrupts = ;
+   dmas = <_bus 0>, <_bus 1>;
+   dma-names = "tx", "rx";
+   clock-names = "i2s_clk", "i2s_hclk";
+   clocks = < SCLK_I2S_8CH>, < HCLK_I2S_8CH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_8ch_bus>;
+   status = "disabled";
+   };
+
gic: interrupt-controller@ffb71000 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -917,6 +941,20 @@
};
};
 
+   i2s {
+   i2s_8ch_bus: i2s-8ch-bus {
+   rockchip,pins = <2 12 RK_FUNC_1 
_pull_none>,
+   <2 13 RK_FUNC_1 
_pull_none>,
+   <2 14 RK_FUNC_1 
_pull_none>,
+   <2 15 RK_FUNC_1 
_pull_none>,
+   <2 16 RK_FUNC_1 
_pull_none>,
+   <2 17 RK_FUNC_1 
_pull_none>,
+   <2 18 RK_FUNC_1 
_pull_none>,
+   <2 19 RK_FUNC_1 
_pull_none>,
+   <2 20 RK_FUNC_1 
_pull_none>;
+   };
+   };
+
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <3 8 RK_FUNC_2 _pull_none>;
-- 
1.9.1

[PATCH v2 1/3] arm64: dts: rockchip: add amba node support for RK3368 SoCs

[Jianqun Xu]

There are two dmacs found on RK3368 SoCs, peripher dmac and bus dmac,
and the dmacs are same as previous SoCs' dmac.

Signed-off-by: Jianqun Xu <jay...@rock-chips.com>
---
changes since v1:
- none

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index a635adc..c9be1b2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -204,6 +204,37 @@
 <_b2>, <_b3>;
};
 
+   amba {
+   compatible = "simple-bus";
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   dmac_peri: dma-controller@ff25 {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0x0 0xff25 0x0 0x4000>;
+   interrupts = ,
+;
+   #dma-cells = <1>;
+   clocks = < ACLK_DMAC_PERI>;
+   clock-names = "apb_pclk";
+   arm,pl330-broken-no-flushp;
+   peripherals-req-type-burst;
+   };
+
+   dmac_bus: dma-controller@ff60 {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0x0 0xff60 0x0 0x4000>;
+   interrupts = ,
+;
+   #dma-cells = <1>;
+   clocks = < ACLK_DMAC_BUS>;
+   clock-names = "apb_pclk";
+   arm,pl330-broken-no-flushp;
+   peripherals-req-type-burst;
+   };
+   };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";
-- 
1.9.1

[PATCH 0/3] arm64: dts: rockchip: rk3368 add dmac and i2s nodes

[Jianqun Xu]

These patches add dmac, i2s nodes, and disable mailbox.

Jianqun Xu (3):
  arm64: dts: rockchip: add amba node support for RK3368 SoCs
  arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs
  arm64: dts: rockchip: disable mailbox of RK3368 SoCs defaultly

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 70 
 1 file changed, 70 insertions(+)

-- 
1.9.1

[PATCH 0/3] arm64: dts: rockchip: rk3368 add dmac and i2s nodes

[Jianqun Xu]

These patches add dmac, i2s nodes, and disable mailbox.

Jianqun Xu (3):
  arm64: dts: rockchip: add amba node support for RK3368 SoCs
  arm64: dts: rockchip: add i2s nodes support for RK3368 SoCs
  arm64: dts: rockchip: disable mailbox of RK3368 SoCs defaultly

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 70 
 1 file changed, 70 insertions(+)

-- 
1.9.1

[PATCH v2 1/3] arm64: dts: rockchip: add amba node support for RK3368 SoCs

[Jianqun Xu]

There are two dmacs found on RK3368 SoCs, peripher dmac and bus dmac,
and the dmacs are same as previous SoCs' dmac.

Signed-off-by: Jianqun Xu 
---
changes since v1:
- none

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index a635adc..c9be1b2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -204,6 +204,37 @@
 <_b2>, <_b3>;
};
 
+   amba {
+   compatible = "simple-bus";
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   dmac_peri: dma-controller@ff25 {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0x0 0xff25 0x0 0x4000>;
+   interrupts = ,
+;
+   #dma-cells = <1>;
+   clocks = < ACLK_DMAC_PERI>;
+   clock-names = "apb_pclk";
+   arm,pl330-broken-no-flushp;
+   peripherals-req-type-burst;
+   };
+
+   dmac_bus: dma-controller@ff60 {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0x0 0xff60 0x0 0x4000>;
+   interrupts = ,
+;
+   #dma-cells = <1>;
+   clocks = < ACLK_DMAC_BUS>;
+   clock-names = "apb_pclk";
+   arm,pl330-broken-no-flushp;
+   peripherals-req-type-burst;
+   };
+   };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";
-- 
1.9.1

[PATCH v2 3/3] arm64: dts: rockchip: disable mailbox of RK3368 SoCs defaultly

[Jianqun Xu]

Default to disable mailbox in rk3368 core dts file.

Signed-off-by: Jianqun Xu <jay...@rock-chips.com>
---
changes since v1:
- none

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 74fbcc2..eeb31f1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -662,6 +662,7 @@
clocks = < PCLK_MAILBOX>;
clock-names = "pclk_mailbox";
#mbox-cells = <1>;
+   status = "disabled";
};
 
pmugrf: syscon@ff738000 {
-- 
1.9.1

[PATCH v2 3/3] arm64: dts: rockchip: disable mailbox of RK3368 SoCs defaultly

[Jianqun Xu]

Default to disable mailbox in rk3368 core dts file.

Signed-off-by: Jianqun Xu 
---
changes since v1:
- none

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 74fbcc2..eeb31f1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -662,6 +662,7 @@
clocks = < PCLK_MAILBOX>;
clock-names = "pclk_mailbox";
#mbox-cells = <1>;
+   status = "disabled";
};
 
pmugrf: syscon@ff738000 {
-- 
1.9.1

[PATCH] arm64: dts: rockchip: rk3368 swap clust0 and clust1

[Jianqun Xu]

Before this patch, clust1 has little core0~3, clust0 has big core0~3
cpu_l | cpu0 |
cpu_l | cpu1 | clust1
cpu_l | cpu2 |
cpu_l | cpu3 |
--
cpu_b | cpu4 |
cpu_b | cpu5 | clust0
cpu_b | cpu6 |
cpu_b | cpu7 |

With this patch, clust0 will have little core0~3, clust1 will have big core0~3
cpu_l | cpu0 |
cpu_l | cpu1 | clust0
cpu_l | cpu2 |
cpu_l | cpu3 |
--
cpu_b | cpu4 |
cpu_b | cpu5 | clust1
cpu_b | cpu6 |
cpu_b | cpu7 |

It makes no other change, just keep same with other SoCs definations.

Signed-off-by: Jianqun Xu <jay...@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index a635adc..7b9d1e6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -79,31 +79,31 @@
cpu-map {
cluster0 {
core0 {
-   cpu = <_b0>;
+   cpu = <_l0>;
};
core1 {
-   cpu = <_b1>;
+   cpu = <_l1>;
};
core2 {
-   cpu = <_b2>;
+   cpu = <_l2>;
};
core3 {
-   cpu = <_b3>;
+   cpu = <_l3>;
};
};
 
cluster1 {
core0 {
-   cpu = <_l0>;
+   cpu = <_b0>;
};
core1 {
-   cpu = <_l1>;
+   cpu = <_b1>;
};
core2 {
-   cpu = <_l2>;
+   cpu = <_b2>;
};
core3 {
-   cpu = <_l3>;
+   cpu = <_b3>;
};
};
};
-- 
1.9.1

[PATCH] arm64: dts: rockchip: rk3368 swap clust0 and clust1

[Jianqun Xu]

Before this patch, clust1 has little core0~3, clust0 has big core0~3
cpu_l | cpu0 |
cpu_l | cpu1 | clust1
cpu_l | cpu2 |
cpu_l | cpu3 |
--
cpu_b | cpu4 |
cpu_b | cpu5 | clust0
cpu_b | cpu6 |
cpu_b | cpu7 |

With this patch, clust0 will have little core0~3, clust1 will have big core0~3
cpu_l | cpu0 |
cpu_l | cpu1 | clust0
cpu_l | cpu2 |
cpu_l | cpu3 |
--
cpu_b | cpu4 |
cpu_b | cpu5 | clust1
cpu_b | cpu6 |
cpu_b | cpu7 |

It makes no other change, just keep same with other SoCs definations.

Signed-off-by: Jianqun Xu 
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index a635adc..7b9d1e6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -79,31 +79,31 @@
cpu-map {
cluster0 {
core0 {
-   cpu = <_b0>;
+   cpu = <_l0>;
};
core1 {
-   cpu = <_b1>;
+   cpu = <_l1>;
};
core2 {
-   cpu = <_b2>;
+   cpu = <_l2>;
};
core3 {
-   cpu = <_b3>;
+   cpu = <_l3>;
};
};
 
cluster1 {
core0 {
-   cpu = <_l0>;
+   cpu = <_b0>;
};
core1 {
-   cpu = <_l1>;
+   cpu = <_b1>;
};
core2 {
-   cpu = <_l2>;
+   cpu = <_b2>;
};
core3 {
-   cpu = <_l3>;
+   cpu = <_b3>;
};
};
};
-- 
1.9.1

[PATCH 4/4] arm64: dts: rockchip: disable mailbox of RK3368 SoCs defaultly

[Jianqun Xu]

Default to disable mailbox in rk3368 core dts file.

Signed-off-by: Jianqun Xu <jay...@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 90f72c2..36aeed0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -662,6 +662,7 @@
clocks = < PCLK_MAILBOX>;
clock-names = "pclk_mailbox";
#mbox-cells = <1>;
+   status = "disabled";
};
 
pmugrf: syscon@ff738000 {
-- 
1.9.1