Re: [RESEND PATCH] rtc: rk808: rename rtc-rk808.c to rtc-rk8xx.c

[Kever Yang]

Hi Zhang Qing,

On 12/31/2015 10:14 PM, zhangqing wrote:

make rtc-rk8xx.c compatible for all pmic chips.
for pmic chips(rk808\rk807\rk816\rk818) in the future.

The commit message will be better like this:
Rename the file to rtc-rk8xx.c to compatible other Rockchip PMIC chips
like rk807/rk816/rk818 and other chips in the the future.

Also rename the variable, MACRO, function and etc. names in relate file.



Signed-off-by: zhangqing 

Prefer to use: Zhang Qing 

---
  drivers/mfd/rk808.c  |   2 +-
  drivers/rtc/Kconfig  |   8 +-
  drivers/rtc/Makefile |   2 +-
  drivers/rtc/{rtc-rk808.c => rtc-rk8xx.c} | 218 ++-
  4 files changed, 131 insertions(+), 99 deletions(-)
  rename drivers/rtc/{rtc-rk808.c => rtc-rk8xx.c} (64%)

diff --git a/drivers/mfd/rk808.c b/drivers/mfd/rk808.c
index 4b1e439..21da22b 100644
--- a/drivers/mfd/rk808.c
+++ b/drivers/mfd/rk808.c
@@ -77,7 +77,7 @@ static const struct mfd_cell rk808s[] = {
{ .name = "rk808-clkout", },
{ .name = "rk808-regulator", },
{
-   .name = "rk808-rtc",
+   .name = "rk8xx-rtc",
.num_resources = ARRAY_SIZE(rtc_resources),
.resources = _resources[0],
},
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 376322f..d669473d 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -325,15 +325,15 @@ config RTC_DRV_MAX77686
  This driver can also be built as a module. If so, the module
  will be called rtc-max77686.
  
-config RTC_DRV_RK808

-   tristate "Rockchip RK808 RTC"
+config RTC_DRV_RK8XX
+   tristate "Rockchip RK8XX RTC"
depends on MFD_RK808
help
  If you say yes here you will get support for the
- RTC of RK808 PMIC.
+ RTC of RK8XX PMIC.
  
  	  This driver can also be built as a module. If so, the module

- will be called rk808-rtc.
+ will be called rk8xx-rtc.
  
  config RTC_DRV_MAX77802

tristate "Maxim 77802 RTC"
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 62d61b2..5b1384a 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -120,7 +120,7 @@ obj-$(CONFIG_RTC_DRV_PUV3)  += rtc-puv3.o
  obj-$(CONFIG_RTC_DRV_PXA) += rtc-pxa.o
  obj-$(CONFIG_RTC_DRV_R9701)   += rtc-r9701.o
  obj-$(CONFIG_RTC_DRV_RC5T583) += rtc-rc5t583.o
-obj-$(CONFIG_RTC_DRV_RK808)+= rtc-rk808.o
+obj-$(CONFIG_RTC_DRV_RK8XX)+= rtc-rk8xx.o
  obj-$(CONFIG_RTC_DRV_RP5C01)  += rtc-rp5c01.o
  obj-$(CONFIG_RTC_DRV_RS5C313) += rtc-rs5c313.o
  obj-$(CONFIG_RTC_DRV_RS5C348) += rtc-rs5c348.o
diff --git a/drivers/rtc/rtc-rk808.c b/drivers/rtc/rtc-rk8xx.c
similarity index 64%
rename from drivers/rtc/rtc-rk808.c
rename to drivers/rtc/rtc-rk8xx.c
index 35c9aad..5d946bf 100644
--- a/drivers/rtc/rtc-rk808.c
+++ b/drivers/rtc/rtc-rk8xx.c
@@ -1,5 +1,5 @@
  /*
- * RTC driver for Rockchip RK808
+ * RTC driver for Rockchip RK8XX
   *
   * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   *
@@ -20,14 +20,33 @@
  #include 
  #include 
  #include 
-#include 
  #include 
  #include 
+#include 
+
+#define RK8XX_SECONDS_REG  0x00
+#define RK8XX_MINUTES_REG  0x01
+#define RK8XX_HOURS_REG0x02
+#define RK8XX_DAYS_REG 0x03
+#define RK8XX_MONTHS_REG   0x04
+#define RK8XX_YEARS_REG0x05
+#define RK8XX_WEEKS_REG0x06
+#define RK8XX_ALARM_SECONDS_REG0x08
+#define RK8XX_ALARM_MINUTES_REG0x09
+#define RK8XX_ALARM_HOURS_REG  0x0A
+#define RK8XX_ALARM_DAYS_REG   0x0B
+#define RK8XX_ALARM_MONTHS_REG 0x0C
+#define RK8XX_ALARM_YEARS_REG  0x0D
+#define RK8XX_RTC_CTRL_REG 0x10
+#define RK8XX_RTC_STATUS_REG   0x11
+#define RK8XX_RTC_INT_REG  0x12
+#define RK8XX_RTC_COMP_LSB_REG 0x13
+#define RK8XX_RTC_COMP_MSB_REG 0x14
  
  /* RTC_CTRL_REG bitfields */

  #define BIT_RTC_CTRL_REG_STOP_RTC_M   BIT(0)
  
-/* RK808 has a shadowed register for saving a "frozen" RTC time.

+/* RK8xx has a shadowed register for saving a "frozen" RTC time.
   * When user setting "GET_TIME" to 1, the time will save in this shadowed
   * register. If set "READSEL" to 1, user read rtc time register, actually
   * get the time of that moment. If we need the real time, clr this bit.
@@ -47,17 +66,25 @@
  
  /* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
  
-#define NUM_TIME_REGS	(RK808_WEEKS_REG - RK808_SECONDS_REG + 1)

-#define NUM_ALARM_REGS (RK808_ALARM_YEARS_REG - RK808_ALARM_SECONDS_REG + 1)
+#define 

Re: [PATCH v6 3/3] ARM: rockchip: fix the SMP code style

[Kever Yang]

Hi Caesar,

On 06/09/2015 05:49 PM, Caesar Wang wrote:

Use the below scripts to check:
scripts/checkpatch.pl -f --subject arch/arm/mach-rockchip/platsmp.c

Signed-off-by: Caesar Wang 

---

Changes in v6:
- fix the commnet Unified format.
Series-changes: 5
- Add the changelog.
Series-changes: 2
- Use the checkpatch.pl -f --subjective to check.

  arch/arm/mach-rockchip/platsmp.c | 14 --
  1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index d629206..30ccb82 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -100,7 +100,7 @@ static int pmu_set_power_domain(int pd, bool on)
ret = pmu_power_domain_is_on(pd);
if (ret < 0) {
pr_err("%s: could not read power domain state\n",
-__func__);
+  __func__);
return ret;
}
}
@@ -130,7 +130,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int 
cpu,
  
  	if (cpu >= ncores) {

pr_err("%s: cpu %d outside maximum number of cpus %d\n",
-   __func__, cpu, ncores);
+  __func__, cpu, ncores);
return -ENXIO;
}
  
@@ -140,7 +140,8 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,

return ret;
  
  	if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {

-   /* We communicate with the bootrom to active the cpus other
+   /*
+* We communicate with the bootrom to active the cpus other
 * than cpu0, after a blob of initialize code, they will
 * stay at wfe state, once they are actived, they will check
 * the mailbox:
@@ -149,11 +150,11 @@ static int __cpuinit rockchip_boot_secondary(unsigned int 
cpu,
 * The cpu0 need to wait the other cpus other than cpu0 entering
 * the wfe state.The wait time is affected by many aspects.
 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
-* */
+*/
mdelay(1); /* ensure the cpus other than cpu0 to startup */
  
  		writel(virt_to_phys(rockchip_secondary_startup),

-   sram_base_addr + 8);
+  sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4);
dsb_sev();
}
@@ -336,7 +337,7 @@ static int rockchip_cpu_kill(unsigned int cpu)
  static void rockchip_cpu_die(unsigned int cpu)
  {
v7_exit_coherency_flush(louis);
-   while(1)
+   while (1)
cpu_do_idle();
  }
  #endif
@@ -349,4 +350,5 @@ static struct smp_operations rockchip_smp_ops __initdata = {
.cpu_die= rockchip_cpu_die,
  #endif
  };
+
  CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", _smp_ops);

Reviewed-by: Kever Yang 

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Re: [PATCH v6 1/3] ARM: rockchip: fix the CPU soft reset

[Kever Yang]

c);
-   }
+   if (!IS_ERR(rstc) && !on)
+   reset_control_assert(rstc);
  
  	ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);

if (ret < 0) {
@@ -112,6 +105,12 @@ static int pmu_set_power_domain(int pd, bool on)
}
}
  
+	if (!IS_ERR(rstc)) {

+   if (on)
+   reset_control_deassert(rstc);
+   reset_control_put(rstc);
+   }
+
return 0;
  }
  
@@ -147,8 +146,12 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,

 * the mailbox:
 * sram_base_addr + 4: 0xdeadbeaf
 * sram_base_addr + 8: start address for pc
+* The cpu0 need to wait the other cpus other than cpu0 entering
+* the wfe state.The wait time is affected by many aspects.
+* (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
 * */
-   udelay(10);
+   mdelay(1); /* ensure the cpus other than cpu0 to startup */
+
writel(virt_to_phys(rockchip_secondary_startup),
        sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4);

Reviewed-by: Kever Yang 

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Re: [PATCH v6 2/3] ARM: rockchip: ensure CPU to enter WFI/WFE state

[Kever Yang]

Hi Caesar,

On 06/09/2015 05:49 PM, Caesar Wang wrote:

The patch can ensure that v7_exit_coherency_flush() in rockchip_cpu_die()
executed in time.
The mdelay(1) has enough time to fix the problem of CPU offlining.
That's a workaround way in rockchip hotplug code,
At least, we haven't a better way to solve it. Who know,
that maybe fixed by chip (hardware) in the future.

Signed-off-by: Caesar Wang 

---

Changes in v6:
- Fix the delay 1ms describing.
Series-changes: 5
- Fix the patch decription.
- Add the changelog.
Series-changes: 2
- As Kever points out, Fix the subject typo WFI/WFE.

  arch/arm/mach-rockchip/platsmp.c | 7 +++
  1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index b379cc8..d629206 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -322,6 +322,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int 
max_cpus)
  #ifdef CONFIG_HOTPLUG_CPU
  static int rockchip_cpu_kill(unsigned int cpu)
  {
+   /*
+* We need a delay here to ensure that the dying CPU can finish
+* executing v7_coherency_exit() and reach the WFI/WFE state
+* prior to having the power domain disabled.
+*/
+   mdelay(1);
+
pmu_set_power_domain(0 + cpu, false);
return 1;
  }

Reviewed-by: Kever Yang 

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Re: [PATCH v6 1/3] ARM: rockchip: fix the CPU soft reset

[Kever Yang]

(rstc);
  
  	ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);

if (ret  0) {
@@ -112,6 +105,12 @@ static int pmu_set_power_domain(int pd, bool on)
}
}
  
+	if (!IS_ERR(rstc)) {

+   if (on)
+   reset_control_deassert(rstc);
+   reset_control_put(rstc);
+   }
+
return 0;
  }
  
@@ -147,8 +146,12 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,

 * the mailbox:
 * sram_base_addr + 4: 0xdeadbeaf
 * sram_base_addr + 8: start address for pc
+* The cpu0 need to wait the other cpus other than cpu0 entering
+* the wfe state.The wait time is affected by many aspects.
+* (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
 * */
-   udelay(10);
+   mdelay(1); /* ensure the cpus other than cpu0 to startup */
+
writel(virt_to_phys(rockchip_secondary_startup),
sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4);

Reviewed-by: Kever Yang kever.y...@rock-chips.com

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Re: [PATCH v6 2/3] ARM: rockchip: ensure CPU to enter WFI/WFE state

[Kever Yang]

Hi Caesar,

On 06/09/2015 05:49 PM, Caesar Wang wrote:

The patch can ensure that v7_exit_coherency_flush() in rockchip_cpu_die()
executed in time.
The mdelay(1) has enough time to fix the problem of CPU offlining.
That's a workaround way in rockchip hotplug code,
At least, we haven't a better way to solve it. Who know,
that maybe fixed by chip (hardware) in the future.

Signed-off-by: Caesar Wang w...@rock-chips.com

---

Changes in v6:
- Fix the delay 1ms describing.
Series-changes: 5
- Fix the patch decription.
- Add the changelog.
Series-changes: 2
- As Kever points out, Fix the subject typo WFI/WFE.

  arch/arm/mach-rockchip/platsmp.c | 7 +++
  1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index b379cc8..d629206 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -322,6 +322,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int 
max_cpus)
  #ifdef CONFIG_HOTPLUG_CPU
  static int rockchip_cpu_kill(unsigned int cpu)
  {
+   /*
+* We need a delay here to ensure that the dying CPU can finish
+* executing v7_coherency_exit() and reach the WFI/WFE state
+* prior to having the power domain disabled.
+*/
+   mdelay(1);
+
pmu_set_power_domain(0 + cpu, false);
return 1;
  }

Reviewed-by: Kever Yang kever.y...@rock-chips.com

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Re: [PATCH v6 3/3] ARM: rockchip: fix the SMP code style

[Kever Yang]

Hi Caesar,

On 06/09/2015 05:49 PM, Caesar Wang wrote:

Use the below scripts to check:
scripts/checkpatch.pl -f --subject arch/arm/mach-rockchip/platsmp.c

Signed-off-by: Caesar Wang w...@rock-chips.com

---

Changes in v6:
- fix the commnet Unified format.
Series-changes: 5
- Add the changelog.
Series-changes: 2
- Use the checkpatch.pl -f --subjective to check.

  arch/arm/mach-rockchip/platsmp.c | 14 --
  1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index d629206..30ccb82 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -100,7 +100,7 @@ static int pmu_set_power_domain(int pd, bool on)
ret = pmu_power_domain_is_on(pd);
if (ret  0) {
pr_err(%s: could not read power domain state\n,
-__func__);
+  __func__);
return ret;
}
}
@@ -130,7 +130,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int 
cpu,
  
  	if (cpu = ncores) {

pr_err(%s: cpu %d outside maximum number of cpus %d\n,
-   __func__, cpu, ncores);
+  __func__, cpu, ncores);
return -ENXIO;
}
  
@@ -140,7 +140,8 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,

return ret;
  
  	if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {

-   /* We communicate with the bootrom to active the cpus other
+   /*
+* We communicate with the bootrom to active the cpus other
 * than cpu0, after a blob of initialize code, they will
 * stay at wfe state, once they are actived, they will check
 * the mailbox:
@@ -149,11 +150,11 @@ static int __cpuinit rockchip_boot_secondary(unsigned int 
cpu,
 * The cpu0 need to wait the other cpus other than cpu0 entering
 * the wfe state.The wait time is affected by many aspects.
 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
-* */
+*/
mdelay(1); /* ensure the cpus other than cpu0 to startup */
  
  		writel(virt_to_phys(rockchip_secondary_startup),

-   sram_base_addr + 8);
+  sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4);
dsb_sev();
}
@@ -336,7 +337,7 @@ static int rockchip_cpu_kill(unsigned int cpu)
  static void rockchip_cpu_die(unsigned int cpu)
  {
v7_exit_coherency_flush(louis);
-   while(1)
+   while (1)
cpu_do_idle();
  }
  #endif
@@ -349,4 +350,5 @@ static struct smp_operations rockchip_smp_ops __initdata = {
.cpu_die= rockchip_cpu_die,
  #endif
  };
+
  CPU_METHOD_OF_DECLARE(rk3066_smp, rockchip,rk3066-smp, rockchip_smp_ops);

Reviewed-by: Kever Yang kever.y...@rock-chips.com

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Re: [PATCH 2/3] ARM: rockchip: ensure CPU to enter WIF state

[Kever Yang]

Hi Caesar,

Subject typo WIF/WFI.

On 06/05/2015 12:47 PM, Caesar Wang wrote:

In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI state.

Signed-off-by: Caesar Wang 
---

  arch/arm/mach-rockchip/platsmp.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 1230d3d..978c357 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -316,6 +316,9 @@ static void __init rockchip_smp_prepare_cpus(unsigned int 
max_cpus)
  #ifdef CONFIG_HOTPLUG_CPU
  static int rockchip_cpu_kill(unsigned int cpu)
  {
+   /* ensure CPU can enter the WFI/WFE state */
+   mdelay(1);
+

Does it matter if core is not in WFI state when we want to power down it?

Thanks,
- Kever

pmu_set_power_domain(0 + cpu, false);
return 1;
  }


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Re: [PATCH 2/3] ARM: rockchip: ensure CPU to enter WIF state

[Kever Yang]

Hi Caesar,

Subject typo WIF/WFI.

On 06/05/2015 12:47 PM, Caesar Wang wrote:

In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI state.

Signed-off-by: Caesar Wang w...@rock-chips.com
---

  arch/arm/mach-rockchip/platsmp.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 1230d3d..978c357 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -316,6 +316,9 @@ static void __init rockchip_smp_prepare_cpus(unsigned int 
max_cpus)
  #ifdef CONFIG_HOTPLUG_CPU
  static int rockchip_cpu_kill(unsigned int cpu)
  {
+   /* ensure CPU can enter the WFI/WFE state */
+   mdelay(1);
+

Does it matter if core is not in WFI state when we want to power down it?

Thanks,
- Kever

pmu_set_power_domain(0 + cpu, false);
return 1;
  }


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Re: [PATCH v2] ASoC: max98090: add shutdown callback for max98090

[Kever Yang]

Hi Caesar,

On 04/08/2015 06:18 PM, Caesar Wang wrote:

To fix pop noise when shutdown,the pop noise during shutdown
is the pmic cutoff power of codec without any notice.

Signed-off-by: jay.xu 
Signed-off-by: zhengxing 
Signed-off-by: Caesar Wang 

Serien-cc: linux-kernel@vger.kernel.org
Serien-cc: devicet...@vger.kernel.org
Serien-cc: diand...@chromium.org

Typo? Should be "Series-cc" here I guess.

Thanks,
- Kever

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Re: [PATCH v2] ASoC: max98090: add shutdown callback for max98090

[Kever Yang]

Hi Caesar,

On 04/08/2015 06:18 PM, Caesar Wang wrote:

To fix pop noise when shutdown,the pop noise during shutdown
is the pmic cutoff power of codec without any notice.

Signed-off-by: jay.xu x...@rock-chips.com
Signed-off-by: zhengxing zhengx...@rock-chips.com
Signed-off-by: Caesar Wang w...@rock-chips.com

Serien-cc: linux-kernel@vger.kernel.org
Serien-cc: devicet...@vger.kernel.org
Serien-cc: diand...@chromium.org

Typo? Should be Series-cc here I guess.

Thanks,
- Kever

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Re: [PATCH V2] clockevents: rockchip: Add rockchip timer for rk3288

[Kever Yang]

Hi Daniel,

On 01/25/2015 05:42 PM, Daniel Lezcano wrote:

The rk3288 board uses the architected timers and these ones are shutdown when
the cpu is powered down. There is a need of a broadcast timer in this case to
ensure proper wakeup when the cpus are in sleep mode and a timer expires.

This driver provides the basic timer functionnality as a backup for the local
timers at sleep time.

The timer belongs to the alive subsystem. It includes two programmables 64 bits
timer channels but the driver only uses 32bits. It works with two operations
mode: free running and user defined count.

Programing sequence:

1. Timer initialization:
  * Disable the timer by writing '0' to the CONTROLREG register
  * Program the timer mode by writing the mode to the CONTROLREG register
  * Set the interrupt mask

2. Setting the count value:
  * Load the count value to the registers COUNT0 and COUNT1 (not used).

3. Enable the timer
  * Write '1' to the CONTROLREG register with the mode (free running or user)

Signed-off-by: Daniel Lezcano 
---
  .../bindings/timer/rockchip,rk3288-timer.txt   |  18 +++
  arch/arm/boot/dts/rk3288.dtsi  |   8 +
  arch/arm/mach-rockchip/Kconfig |   1 +
  drivers/clocksource/Kconfig|   4 +
  drivers/clocksource/Makefile   |   1 +
  drivers/clocksource/rockchip_timer.c   | 180 +
  6 files changed, 212 insertions(+)
  create mode 100644 
Documentation/devicetree/bindings/timer/rockchip,rk3288-timer.txt
  create mode 100644 drivers/clocksource/rockchip_timer.c

diff --git a/Documentation/devicetree/bindings/timer/rockchip,rk3288-timer.txt 
b/Documentation/devicetree/bindings/timer/rockchip,rk3288-timer.txt
new file mode 100644
index 000..87f0b00
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/rockchip,rk3288-timer.txt
@@ -0,0 +1,18 @@
+Rockchip rk3288 timer
+
+Required properties:
+- compatible: shall be "rockchip,rk3288-timer"
+- reg: base address of the timer register starting with TIMERS CONTROL register
+- interrupts: should contain the interrupts for Timer0
+- clocks : must contain an entry for each entry in clock-names
+- clock-names : must include the following entries:
+  "timer", "pclk"
+
+Example:
+   timer: timer@ff81 {
+   compatible = "rockchip,rk3288-timer";
+   reg = <0xff81 0x20>;
+   interrupts = ;
+   clocks = <>, < PCLK_TIMER>;
+   clock-names = "timer", "pclk";
+   };
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 2a878a3..0930140 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -149,6 +149,14 @@
clock-frequency = <2400>;
};
  
+	timer: timer@ff81 {

+   compatible = "rockchip,rk3288-timer";
+   reg = <0xff81 0x20>;
+   interrupts = ;
+   clocks = <>, < PCLK_TIMER>;
+   clock-names = "timer", "pclk";
+   };
+
sdmmc: dwmmc@ff0c {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <40 15000>;
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ac5803c..5078932 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -11,6 +11,7 @@ config ARCH_ROCKCHIP
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select DW_APB_TIMER_OF
+   select ROCKCHIP_TIMER
select ARM_GLOBAL_TIMER
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
help
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index fc01ec2..5c39de7 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -26,6 +26,10 @@ config DW_APB_TIMER_OF
select DW_APB_TIMER
select CLKSRC_OF
  
+config ROCKCHIP_TIMER

+   bool
+   select CLKSRC_OF
+
  config ARMADA_370_XP_TIMER
bool
select CLKSRC_OF
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 94d90b2..0ea1342 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CLKBLD_I8253)+= i8253.o
  obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
  obj-$(CONFIG_DW_APB_TIMER)+= dw_apb_timer.o
  obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
+obj-$(CONFIG_ROCKCHIP_TIMER)  += rockchip_timer.o
  obj-$(CONFIG_CLKSRC_NOMADIK_MTU)  += nomadik-mtu.o
  obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
  obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
diff --git a/drivers/clocksource/rockchip_timer.c 
b/drivers/clocksource/rockchip_timer.c
new file mode 100644
index 000..5ea290d
--- /dev/null
+++ b/drivers/clocksource/rockchip_timer.c
@@ -0,0 +1,180 @@
+/*
+ * Rockchip timer support
+ *
+ * Copyright (C) Daniel Lezcano 
+ *
+ * This program is free software; you can 

Re: [PATCH V2] clockevents: rockchip: Add rockchip timer for rk3288

[Kever Yang]

Hi Daniel,

On 01/25/2015 05:42 PM, Daniel Lezcano wrote:

The rk3288 board uses the architected timers and these ones are shutdown when
the cpu is powered down. There is a need of a broadcast timer in this case to
ensure proper wakeup when the cpus are in sleep mode and a timer expires.

This driver provides the basic timer functionnality as a backup for the local
timers at sleep time.

The timer belongs to the alive subsystem. It includes two programmables 64 bits
timer channels but the driver only uses 32bits. It works with two operations
mode: free running and user defined count.

Programing sequence:

1. Timer initialization:
  * Disable the timer by writing '0' to the CONTROLREG register
  * Program the timer mode by writing the mode to the CONTROLREG register
  * Set the interrupt mask

2. Setting the count value:
  * Load the count value to the registers COUNT0 and COUNT1 (not used).

3. Enable the timer
  * Write '1' to the CONTROLREG register with the mode (free running or user)

Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
  .../bindings/timer/rockchip,rk3288-timer.txt   |  18 +++
  arch/arm/boot/dts/rk3288.dtsi  |   8 +
  arch/arm/mach-rockchip/Kconfig |   1 +
  drivers/clocksource/Kconfig|   4 +
  drivers/clocksource/Makefile   |   1 +
  drivers/clocksource/rockchip_timer.c   | 180 +
  6 files changed, 212 insertions(+)
  create mode 100644 
Documentation/devicetree/bindings/timer/rockchip,rk3288-timer.txt
  create mode 100644 drivers/clocksource/rockchip_timer.c

diff --git a/Documentation/devicetree/bindings/timer/rockchip,rk3288-timer.txt 
b/Documentation/devicetree/bindings/timer/rockchip,rk3288-timer.txt
new file mode 100644
index 000..87f0b00
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/rockchip,rk3288-timer.txt
@@ -0,0 +1,18 @@
+Rockchip rk3288 timer
+
+Required properties:
+- compatible: shall be rockchip,rk3288-timer
+- reg: base address of the timer register starting with TIMERS CONTROL register
+- interrupts: should contain the interrupts for Timer0
+- clocks : must contain an entry for each entry in clock-names
+- clock-names : must include the following entries:
+  timer, pclk
+
+Example:
+   timer: timer@ff81 {
+   compatible = rockchip,rk3288-timer;
+   reg = 0xff81 0x20;
+   interrupts = GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH;
+   clocks = xin24m, cru PCLK_TIMER;
+   clock-names = timer, pclk;
+   };
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 2a878a3..0930140 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -149,6 +149,14 @@
clock-frequency = 2400;
};
  
+	timer: timer@ff81 {

+   compatible = rockchip,rk3288-timer;
+   reg = 0xff81 0x20;
+   interrupts = GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH;
+   clocks = xin24m, cru PCLK_TIMER;
+   clock-names = timer, pclk;
+   };
+
sdmmc: dwmmc@ff0c {
compatible = rockchip,rk3288-dw-mshc;
clock-freq-min-max = 40 15000;
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ac5803c..5078932 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -11,6 +11,7 @@ config ARCH_ROCKCHIP
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select DW_APB_TIMER_OF
+   select ROCKCHIP_TIMER
select ARM_GLOBAL_TIMER
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
help
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index fc01ec2..5c39de7 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -26,6 +26,10 @@ config DW_APB_TIMER_OF
select DW_APB_TIMER
select CLKSRC_OF
  
+config ROCKCHIP_TIMER

+   bool
+   select CLKSRC_OF
+
  config ARMADA_370_XP_TIMER
bool
select CLKSRC_OF
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 94d90b2..0ea1342 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CLKBLD_I8253)+= i8253.o
  obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
  obj-$(CONFIG_DW_APB_TIMER)+= dw_apb_timer.o
  obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
+obj-$(CONFIG_ROCKCHIP_TIMER)  += rockchip_timer.o
  obj-$(CONFIG_CLKSRC_NOMADIK_MTU)  += nomadik-mtu.o
  obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
  obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
diff --git a/drivers/clocksource/rockchip_timer.c 
b/drivers/clocksource/rockchip_timer.c
new file mode 100644
index 000..5ea290d
--- /dev/null
+++ b/drivers/clocksource/rockchip_timer.c
@@ -0,0 +1,180 @@
+/*
+ * Rockchip timer support
+ *
+ * Copyright 

Re: [PATCH v3] usb: dwc2: add bus suspend/resume for dwc2

[Kever Yang]

Hi Paul,

I think you need this patch to fix the problem:

usb: dwc2: resume root hub when device detect with suspend state
https://patchwork.kernel.org/patch/5325111/

Thanks,

- Kever
On 01/06/2015 09:23 AM, Paul Zimmerman wrote:

From: Kever Yang [mailto:kever.y...@rock-chips.com]
Sent: Wednesday, November 12, 2014 4:42 PM

On 11/13/2014 07:22 AM, Doug Anderson wrote:

Kever,

On Mon, Nov 10, 2014 at 5:09 AM, Kever Yang  wrote:

Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root hub enter suspend, we can make controller enter
low power state with PCGCTL register.

We also update the lx_state for hsotg state.

This patch has tested on rk3288 with suspend/resume.

Signed-off-by: Kever Yang 
Acked-by: Paul Zimmerman 
---

Changes in v3:
- remove CONFIG_PM macro for bus_suspend/resume
- add PCGCTL operation for no device connect case

Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode work

   drivers/usb/dwc2/hcd.c | 88 
+++---
   1 file changed, 77 insertions(+), 11 deletions(-)

I would certainly appreciate confirmation, but my inclination is to
NAK this change due to the fact that it regresses functionality.  I
haven't done any serious review of it, but I've been testing it and it
appears to break hotplug.

Said another way, I did this:

1. Without this patch, I booted with a USB stick in.  It was detected.
I unplugged it, waited 5 seconds, and then plugged it back in.  The
USB stick was redetcted.

2. With this patch, I did the same thing.  The USB not redected after
plugging it back in.

With this patch, the dwc2 hcd/root hub will be auto suspend after device
on port is disconnected, and it can't detect the device connect any more,
I think that's the problem.

I will figure out how to make dwc2 detect the device connect after auto
suspend,
or disable the auto suspend feature for the dwc2 hcd.

Kever,

This patch has made it into Linus' kernel as commit 0cf884e819e0, and
it breaks disconnect/connect on at least the Altera SOCFPGA platform.
I haven't been able to test it on any other platforms.

You need to submit a patch to either fix this, or to only enable this
feature for the Rock-chip platform. Otherwise the patch has to be
reverted.




--
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Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v3] usb: dwc2: add bus suspend/resume for dwc2

[Kever Yang]

Hi Paul,

I think you need this patch to fix the problem:

usb: dwc2: resume root hub when device detect with suspend state
https://patchwork.kernel.org/patch/5325111/

Thanks,

- Kever
On 01/06/2015 09:23 AM, Paul Zimmerman wrote:

From: Kever Yang [mailto:kever.y...@rock-chips.com]
Sent: Wednesday, November 12, 2014 4:42 PM

On 11/13/2014 07:22 AM, Doug Anderson wrote:

Kever,

On Mon, Nov 10, 2014 at 5:09 AM, Kever Yang kever.y...@rock-chips.com wrote:

Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root hub enter suspend, we can make controller enter
low power state with PCGCTL register.

We also update the lx_state for hsotg state.

This patch has tested on rk3288 with suspend/resume.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---

Changes in v3:
- remove CONFIG_PM macro for bus_suspend/resume
- add PCGCTL operation for no device connect case

Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode work

   drivers/usb/dwc2/hcd.c | 88 
+++---
   1 file changed, 77 insertions(+), 11 deletions(-)

I would certainly appreciate confirmation, but my inclination is to
NAK this change due to the fact that it regresses functionality.  I
haven't done any serious review of it, but I've been testing it and it
appears to break hotplug.

Said another way, I did this:

1. Without this patch, I booted with a USB stick in.  It was detected.
I unplugged it, waited 5 seconds, and then plugged it back in.  The
USB stick was redetcted.

2. With this patch, I did the same thing.  The USB not redected after
plugging it back in.

With this patch, the dwc2 hcd/root hub will be auto suspend after device
on port is disconnected, and it can't detect the device connect any more,
I think that's the problem.

I will figure out how to make dwc2 detect the device connect after auto
suspend,
or disable the auto suspend feature for the dwc2 hcd.

Kever,

This patch has made it into Linus' kernel as commit 0cf884e819e0, and
it breaks disconnect/connect on at least the Altera SOCFPGA platform.
I haven't been able to test it on any other platforms.

You need to submit a patch to either fix this, or to only enable this
feature for the Rock-chip platform. Otherwise the patch has to be
reverted.




--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH] phy: add Rockchip RK3288 USB2 PHY driver.

[Kever Yang]

Hi Roy,

Why you send two patches with different commit message but the same 
change,

you should use V2 for a new patch.

On 12/03/2014 09:46 PM, LiYunzhi wrote:

From: lyz 

You don't need the From for the patches from yourself.


Add a driver for the Rockchip SoC internal USB2.0 PHY.
This driver currently support RK3288.

Signed-off-by: lyz 

Remember to use you Full name here for From/Signed-off-by
or all the kind of signature.

---
  .../devicetree/bindings/phy/rockchip-usb-phy.txt   |  17 ++
The document should be in a separate patch, so please split this into 
two patches.

  drivers/phy/Kconfig|   7 +
  drivers/phy/Makefile   |   1 +
  drivers/phy/phy-rockchip-usb.c | 179 +
  4 files changed, 204 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
  create mode 100644 drivers/phy/phy-rockchip-usb.c

diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt 
b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
new file mode 100644
index 000..18ccc2f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -0,0 +1,17 @@
+ROCKCHIP USB2 PHY
+
+Required properties:
+ - compatible: rockchip,rk3288-usb-phy
+ - rockchip,grf : phandle to the syscon managing the "general
+   register files"
+ - #phy-cells: must be 1
+Refer to phy/phy-bindings.txt for the generic PHY binding
+properties
+
+Example:
+
+   usbphy: phy {
+   #phy-cells = <1>;
+   compatible = "rockchip,rk3288-usb-phy";
+   rockchip,grf = <>;
+   };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 2a436e6..54ab088 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -218,6 +218,13 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
  
+config PHY_ROCKCHIP_RK3288_USB2

+   tristate "Rockchip USB2 RK3288 PHY Driver"
+   depends on ARCH_ROCKCHIP && OF
+   select GENERIC_PHY
+   help
+ Enable this to support the Rockchip USB 2.0 PHY.
+
  config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index c4590fc..f4f2f79 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -25,6 +25,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += 
phy-exynos5250-usb2.o
  phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)+= phy-s5pv210-usb2.o
  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)  += phy-exynos5-usbdrd.o
  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)   += phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_ROCKCHIP_RK3288_USB2) += phy-rockchip-usb.o

Add this after 'CONFIG_PHY_QCOM_IPQ806X_SATA'.

  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)   += phy-qcom-ipq806x-sata.o
  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)  += phy-spear1310-miphy.o
  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)  += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
new file mode 100644
index 000..2586b76
--- /dev/null
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -0,0 +1,179 @@
+/*
+ * Rockchip usb PHY driver
+ *
+ * Copyright (C) 2014 Roy Li 
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14)
+
+#define SIDDQ_MSK  (1 << (13 + 16))
+#define SIDDQ_ON   (1 << 13)
+#define SIDDQ_OFF  (0 << 13)
+
+enum rk3288_phy_id {
+   RK3288_OTG,
+   RK3288_HOST0,
+   RK3288_HOST1,
+   RK3288_NUM_PHYS,
+};
+
+struct rockchip_usb_phy {
+   struct regmap *reg_base;
+   unsigned int reg_offset;
+   struct clk *clk;
+   struct phy *phy;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+  bool siddq)
+{
+   return regmap_write(phy->reg_base, phy->reg_offset,
+   SIDDQ_MSK | (siddq ? SIDDQ_ON : SIDDQ_OFF));
+}
+
+static int rockchip_usb_phy_power_off(struct phy *_phy)
+{
+   struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+   int ret = 0;
+
+   /* Power down usb phy analog blocks by set siddq 1*/
+   ret = rockchip_usb_phy_power(phy, 1);

Use a MACRO like ON/OFF instead of 1/0?
and then we don't need the comment anymore.

+   if (ret)
+   return ret;
+
+   

Re: [PATCH] phy: add Rockchip RK3288 USB2 PHY driver.

[Kever Yang]

Hi Roy,

Why you send two patches with different commit message but the same 
change,

you should use V2 for a new patch.

On 12/03/2014 09:46 PM, LiYunzhi wrote:

From: lyz l...@rock-chips.com

You don't need the From for the patches from yourself.


Add a driver for the Rockchip SoC internal USB2.0 PHY.
This driver currently support RK3288.

Signed-off-by: lyz l...@rock-chips.com

Remember to use you Full name here for From/Signed-off-by
or all the kind of signature.

---
  .../devicetree/bindings/phy/rockchip-usb-phy.txt   |  17 ++
The document should be in a separate patch, so please split this into 
two patches.

  drivers/phy/Kconfig|   7 +
  drivers/phy/Makefile   |   1 +
  drivers/phy/phy-rockchip-usb.c | 179 +
  4 files changed, 204 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
  create mode 100644 drivers/phy/phy-rockchip-usb.c

diff --git a/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt 
b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
new file mode 100644
index 000..18ccc2f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-usb-phy.txt
@@ -0,0 +1,17 @@
+ROCKCHIP USB2 PHY
+
+Required properties:
+ - compatible: rockchip,rk3288-usb-phy
+ - rockchip,grf : phandle to the syscon managing the general
+   register files
+ - #phy-cells: must be 1
+Refer to phy/phy-bindings.txt for the generic PHY binding
+properties
+
+Example:
+
+   usbphy: phy {
+   #phy-cells = 1;
+   compatible = rockchip,rk3288-usb-phy;
+   rockchip,grf = grf;
+   };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 2a436e6..54ab088 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -218,6 +218,13 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
  
+config PHY_ROCKCHIP_RK3288_USB2

+   tristate Rockchip USB2 RK3288 PHY Driver
+   depends on ARCH_ROCKCHIP  OF
+   select GENERIC_PHY
+   help
+ Enable this to support the Rockchip USB 2.0 PHY.
+
  config PHY_ST_SPEAR1310_MIPHY
tristate ST SPEAR1310-MIPHY driver
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index c4590fc..f4f2f79 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -25,6 +25,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += 
phy-exynos5250-usb2.o
  phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)+= phy-s5pv210-usb2.o
  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)  += phy-exynos5-usbdrd.o
  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)   += phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_ROCKCHIP_RK3288_USB2) += phy-rockchip-usb.o

Add this after 'CONFIG_PHY_QCOM_IPQ806X_SATA'.

  obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)   += phy-qcom-ipq806x-sata.o
  obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY)  += phy-spear1310-miphy.o
  obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)  += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c
new file mode 100644
index 000..2586b76
--- /dev/null
+++ b/drivers/phy/phy-rockchip-usb.c
@@ -0,0 +1,179 @@
+/*
+ * Rockchip usb PHY driver
+ *
+ * Copyright (C) 2014 Roy Li l...@rock-chips.com
+ * Copyright (C) 2014 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/mutex.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/phy/phy.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+#include linux/reset.h
+#include linux/regmap.h
+#include linux/mfd/syscon.h
+
+#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14)
+
+#define SIDDQ_MSK  (1  (13 + 16))
+#define SIDDQ_ON   (1  13)
+#define SIDDQ_OFF  (0  13)
+
+enum rk3288_phy_id {
+   RK3288_OTG,
+   RK3288_HOST0,
+   RK3288_HOST1,
+   RK3288_NUM_PHYS,
+};
+
+struct rockchip_usb_phy {
+   struct regmap *reg_base;
+   unsigned int reg_offset;
+   struct clk *clk;
+   struct phy *phy;
+};
+
+static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
+  bool siddq)
+{
+   return regmap_write(phy-reg_base, phy-reg_offset,
+   SIDDQ_MSK | (siddq ? SIDDQ_ON : SIDDQ_OFF));
+}
+
+static int rockchip_usb_phy_power_off(struct phy *_phy)
+{
+   struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
+   int ret = 0;
+
+   /* Power down 

Re: [PATCH 0/4] support GMAC driver for RK3288

[Kever Yang]

Hi Roger,

Please use the --in-reply-to option for patches other than 0/4
with the git send-email.

On 11/25/2014 05:07 PM, Roger Chen wrote:

Roger Chen (4):
   patch1: add driver for Rockchip RK3288 SoCs integrated GMAC
   patch2: modify CRU config for Rockchip RK3288 SoCs integrated GMAC
   patch3: dts: add gmac info for rk3288
   patch4: dts: enable gmac on RK3288 evb board

tested on rk3288 SDK board:
busybox ifconfig eth0 up
busybox ifconfig eth0 192.168.1.111
ping 192.168.1.1




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Re: [PATCH 0/2] Increase the maximum cpu frequency of rk3288

[Kever Yang]

Hi Chris,

On 11/25/2014 05:37 PM, Chris Zhong wrote:

The maximum cpu frequency of rk3288 can up to 1.8Ghz, but the vdd_cpu need set
to 1.4v. I've tested these patches on rk3288 evb board.

I'm not sure why you need this patch, I think we have a discuss
for the cpu operating point before.
In this case:
1. rk3288.dtsi is for all the rk3288 Soc based system, you may need
a separate opp table in rk3288-evb-rk808.dts;
2. 1.4V may beyond the supported voltage range too much,
and it's not a good idea to add it to rk3288.dtsi as a safe voltage.
3. Do you have a stress/heavy load test on evb with 1.4v at 1.8GHz?

- Kever



Chris Zhong (2):
   ARM: dts: rockchip: change the max voltage of cpu to 1.4v
   ARM: dts: rk3288: change the max clk of cpu to 1.8Ghz

  arch/arm/boot/dts/rk3288-evb-rk808.dts | 2 +-
  arch/arm/boot/dts/rk3288.dtsi  | 6 --
  2 files changed, 5 insertions(+), 3 deletions(-)




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Re: [PATCH 4/4] GMAC: dts: enable gmac on RK3288 evb board

[Kever Yang]

Hi Roger,

The subject should prefix:
Arm: dts: rockchip: enable ...

On 11/25/2014 05:09 PM, Roger Chen wrote:

enable gmac in rk3288-evb-rk808.dts

Signed-off-by: Roger Chen 
---
  arch/arm/boot/dts/rk3288-evb-rk808.dts |   22 ++
  1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts 
b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index d8c775e6..168b4fa 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -152,3 +152,25 @@
};
};
  };
+
+_gmac {
+   clock-frequency = <12500>;
+   clock-output-names = "ext_gmac";
+};
+
+ {
+   //pmu_regulator = "act_ldo5";
+   //pmu_enable_level = <1>; //1->HIGH, 0->LOW

remove these unused code.

+   power-gpio = < 6 GPIO_ACTIVE_HIGH>;
+   reset-gpio = < 7 GPIO_ACTIVE_LOW>;
+   //phyirq-gpio = < 2 GPIO_ACTIVE_LOW>;

same.

+   phy-mode = "rgmii";
+   clock_in_out = "input";
+   assigned-clocks = < SCLK_MAC>;
+   assigned-clock-parents = <_gmac>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pin>; /*_pin*/

same.

- Kever

+   tx_delay = <0x30>;
+   rx_delay = <0x10>;
+   status = "ok";
+};


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Re: [PATCH 3/4] GMAC: dts: add gmac info for rk3288

[Kever Yang]

Hi Roger,

The Subject should use below prefix:
ARM: dts: rockchip: add gmac info for rk3288

On 11/25/2014 05:08 PM, Roger Chen wrote:

add gmac info in rk3288.dtsi for GMAC driver

Signed-off-by: Roger Chen 
---
  arch/arm/boot/dts/rk3288.dtsi |   59 +
  1 file changed, 59 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 0f50d5d..949675d 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -137,6 +137,13 @@
#clock-cells = <0>;
};
  
+	ext_gmac: external-gmac-clock {

+   compatible = "fixed-clock";
+   clock-frequency = <12500>;
+   clock-output-names = "ext_gmac";
+   #clock-cells = <0>;
+   };
+

I'm not sure Heiko will happy with both add the new clock source and
gmac node in these patch.


timer {
compatible = "arm,armv7-timer";
interrupts = ,
@@ -490,6 +497,25 @@
reg = <0xff74 0x1000>;
};
  
+	gmac: eth@ff29 {

+   compatible = "rockchip,rk3288-gmac";
+   reg = <0xff29 0x1>;
+   interrupts = ;  /*irq=59*/
+   interrupt-names = "macirq";
+   rockchip,grf = <>;
+   clocks = < SCLK_MAC>, < SCLK_MAC_PLL>,
+   < SCLK_MAC_RX>, < SCLK_MAC_TX>,
+   < SCLK_MACREF>, < SCLK_MACREF_OUT>,
+   < ACLK_GMAC>, < PCLK_GMAC>;
+   clock-names = "stmmaceth", "clk_mac_pll",
+   "mac_clk_rx", "mac_clk_tx",
+   "clk_mac_ref", "clk_mac_refout",
+   "aclk_mac", "pclk_mac";
+   phy-mode = "rgmii";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pin /*_pin*/>;
+   };
+
The controller dts node should be sort by the base address, I'm sure 
this is in a

wrong place.

- Kever

cru: clock-controller@ff76 {
compatible = "rockchip,rk3288-cru";
reg = <0xff76 0x1000>;
@@ -1040,5 +1066,38 @@
rockchip,pins = <7 23 3 _pull_none>;
};
};
+
+   gmac {
+   rgmii_pin: rgmii-pins {
+   rockchip,pins = <3 30 3 _pull_none>,
+   <3 31 3 _pull_none>,
+   <3 26 3 _pull_none>,
+   <3 27 3 _pull_none>,
+   <3 28 3 _pull_none>,
+   <3 29 3 _pull_none>,
+   <3 24 3 _pull_none>,
+   <3 25 3 _pull_none>,
+   <4 0 3 _pull_none>,
+   <4 5 3 _pull_none>,
+   <4 6 3 _pull_none>,
+   <4 9 3 _pull_none>,
+   <4 4 3 _pull_none>,
+   <4 1 3 _pull_none>,
+   <4 3 3 _pull_none>;
+   };
+
+   rmii_pin: rmii-pins {
+   rockchip,pins = <3 30 3 _pull_none>,
+   <3 31 3 _pull_none>,
+   <3 28 3 _pull_none>,
+   <3 29 3 _pull_none>,
+   <4 0 3 _pull_none>,
+   <4 5 3 _pull_none>,
+   <4 4 3 _pull_none>,
+   <4 1 3 _pull_none>,
+   <4 2 3 _pull_none>,
+   <4 3 3 _pull_none>;
+   };
+   };
};
  };


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Re: [PATCH 2/4] GMAC: modify CRU config for Rockchip RK3288 SoCs integrated GMAC

[Kever Yang]

Hi  Roger,

This  patch should be split into two patch, one for clock ID definition,
one for mac related clocks update.

The Subject for clk-rk3288.c should use below prefix:
clk: rockchip: modify clock for mac ...

On 11/25/2014 05:08 PM, Roger Chen wrote:

modify CRU config for GMAC driver

Could you detail the reason for this patch in commit message?

Signed-off-by: Roger Chen 
---
  drivers/clk/rockchip/clk-rk3288.c  |   14 +++---
  include/dt-bindings/clock/rk3288-cru.h |4 
  2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 2327829..60237dc 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -187,7 +187,7 @@ PNAME(mux_uart2_p)  = { "uart2_src", "uart2_frac", "xin24m" 
};
  PNAME(mux_uart3_p)= { "uart3_src", "uart3_frac", "xin24m" };
  PNAME(mux_uart4_p)= { "uart4_src", "uart4_frac", "xin24m" };
  PNAME(mux_cif_out_p)  = { "cif_src", "xin24m" };
-PNAME(mux_macref_p)= { "mac_src", "ext_gmac" };
+PNAME(mux_mac_p)   = { "mac_pll_src", "ext_gmac" };
  PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
  PNAME(mux_edp_24m_p)  = { "ext_edp_24m", "xin24m" };
  PNAME(mux_tspout_p)   = { "cpll", "gpll", "npll", "xin27m" };
@@ -560,18 +560,18 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, 0,
RK3288_CLKSEL_CON(3), 8, 2, MFLAGS),
  
-	COMPOSITE(0, "mac_src", mux_pll_src_npll_cpll_gpll_p, 0,

+   COMPOSITE(SCLK_MAC_PLL, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(2), 5, GFLAGS),
-   MUX(0, "macref", mux_macref_p, 0,
+   MUX(SCLK_MAC, "mac_clk", mux_mac_p, 0,
RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
-   GATE(0, "sclk_macref_out", "macref", 0,
+   GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
RK3288_CLKGATE_CON(5), 3, GFLAGS),
-   GATE(SCLK_MACREF, "sclk_macref", "macref", 0,
+   GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
RK3288_CLKGATE_CON(5), 2, GFLAGS),
-   GATE(SCLK_MAC_RX, "sclk_mac_rx", "macref", 0,
+   GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
RK3288_CLKGATE_CON(5), 0, GFLAGS),
-   GATE(SCLK_MAC_TX, "sclk_mac_tx", "macref", 0,
+   GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
RK3288_CLKGATE_CON(5), 1, GFLAGS),
  
  	COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,

diff --git a/include/dt-bindings/clock/rk3288-cru.h 
b/include/dt-bindings/clock/rk3288-cru.h
index 100a08c..f9496f5 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -72,6 +72,10 @@
  #define SCLK_HEVC_CABAC   111
  #define SCLK_HEVC_CORE112
  
+#define SCLK_MAC_PLL		150

+#define SCLK_MAC   151
+#define SCLK_MACREF_OUT152
+
  #define DCLK_VOP0 190
  #define DCLK_VOP1 191
  


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Re: [PATCH 2/4] GMAC: modify CRU config for Rockchip RK3288 SoCs integrated GMAC

[Kever Yang]

Hi  Roger,

This  patch should be split into two patch, one for clock ID definition,
one for mac related clocks update.

The Subject for clk-rk3288.c should use below prefix:
clk: rockchip: modify clock for mac ...

On 11/25/2014 05:08 PM, Roger Chen wrote:

modify CRU config for GMAC driver

Could you detail the reason for this patch in commit message?

Signed-off-by: Roger Chen roger.c...@rock-chips.com
---
  drivers/clk/rockchip/clk-rk3288.c  |   14 +++---
  include/dt-bindings/clock/rk3288-cru.h |4 
  2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 2327829..60237dc 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -187,7 +187,7 @@ PNAME(mux_uart2_p)  = { uart2_src, uart2_frac, xin24m 
};
  PNAME(mux_uart3_p)= { uart3_src, uart3_frac, xin24m };
  PNAME(mux_uart4_p)= { uart4_src, uart4_frac, xin24m };
  PNAME(mux_cif_out_p)  = { cif_src, xin24m };
-PNAME(mux_macref_p)= { mac_src, ext_gmac };
+PNAME(mux_mac_p)   = { mac_pll_src, ext_gmac };
  PNAME(mux_hsadcout_p) = { hsadc_src, ext_hsadc };
  PNAME(mux_edp_24m_p)  = { ext_edp_24m, xin24m };
  PNAME(mux_tspout_p)   = { cpll, gpll, npll, xin27m };
@@ -560,18 +560,18 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
MUX(SCLK_UART4, sclk_uart4, mux_uart4_p, 0,
RK3288_CLKSEL_CON(3), 8, 2, MFLAGS),
  
-	COMPOSITE(0, mac_src, mux_pll_src_npll_cpll_gpll_p, 0,

+   COMPOSITE(SCLK_MAC_PLL, mac_pll_src, mux_pll_src_npll_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(2), 5, GFLAGS),
-   MUX(0, macref, mux_macref_p, 0,
+   MUX(SCLK_MAC, mac_clk, mux_mac_p, 0,
RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
-   GATE(0, sclk_macref_out, macref, 0,
+   GATE(SCLK_MACREF_OUT, sclk_macref_out, mac_clk, 0,
RK3288_CLKGATE_CON(5), 3, GFLAGS),
-   GATE(SCLK_MACREF, sclk_macref, macref, 0,
+   GATE(SCLK_MACREF, sclk_macref, mac_clk, 0,
RK3288_CLKGATE_CON(5), 2, GFLAGS),
-   GATE(SCLK_MAC_RX, sclk_mac_rx, macref, 0,
+   GATE(SCLK_MAC_RX, sclk_mac_rx, mac_clk, 0,
RK3288_CLKGATE_CON(5), 0, GFLAGS),
-   GATE(SCLK_MAC_TX, sclk_mac_tx, macref, 0,
+   GATE(SCLK_MAC_TX, sclk_mac_tx, mac_clk, 0,
RK3288_CLKGATE_CON(5), 1, GFLAGS),
  
  	COMPOSITE(0, hsadc_src, mux_pll_src_cpll_gpll_p, 0,

diff --git a/include/dt-bindings/clock/rk3288-cru.h 
b/include/dt-bindings/clock/rk3288-cru.h
index 100a08c..f9496f5 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -72,6 +72,10 @@
  #define SCLK_HEVC_CABAC   111
  #define SCLK_HEVC_CORE112
  
+#define SCLK_MAC_PLL		150

+#define SCLK_MAC   151
+#define SCLK_MACREF_OUT152
+
  #define DCLK_VOP0 190
  #define DCLK_VOP1 191
  


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Re: [PATCH 3/4] GMAC: dts: add gmac info for rk3288

[Kever Yang]

Hi Roger,

The Subject should use below prefix:
ARM: dts: rockchip: add gmac info for rk3288

On 11/25/2014 05:08 PM, Roger Chen wrote:

add gmac info in rk3288.dtsi for GMAC driver

Signed-off-by: Roger Chen roger.c...@rock-chips.com
---
  arch/arm/boot/dts/rk3288.dtsi |   59 +
  1 file changed, 59 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 0f50d5d..949675d 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -137,6 +137,13 @@
#clock-cells = 0;
};
  
+	ext_gmac: external-gmac-clock {

+   compatible = fixed-clock;
+   clock-frequency = 12500;
+   clock-output-names = ext_gmac;
+   #clock-cells = 0;
+   };
+

I'm not sure Heiko will happy with both add the new clock source and
gmac node in these patch.


timer {
compatible = arm,armv7-timer;
interrupts = GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 
IRQ_TYPE_LEVEL_HIGH),
@@ -490,6 +497,25 @@
reg = 0xff74 0x1000;
};
  
+	gmac: eth@ff29 {

+   compatible = rockchip,rk3288-gmac;
+   reg = 0xff29 0x1;
+   interrupts = GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH;  /*irq=59*/
+   interrupt-names = macirq;
+   rockchip,grf = grf;
+   clocks = cru SCLK_MAC, cru SCLK_MAC_PLL,
+   cru SCLK_MAC_RX, cru SCLK_MAC_TX,
+   cru SCLK_MACREF, cru SCLK_MACREF_OUT,
+   cru ACLK_GMAC, cru PCLK_GMAC;
+   clock-names = stmmaceth, clk_mac_pll,
+   mac_clk_rx, mac_clk_tx,
+   clk_mac_ref, clk_mac_refout,
+   aclk_mac, pclk_mac;
+   phy-mode = rgmii;
+   pinctrl-names = default;
+   pinctrl-0 = rgmii_pin /*rmii_pin*/;
+   };
+
The controller dts node should be sort by the base address, I'm sure 
this is in a

wrong place.

- Kever

cru: clock-controller@ff76 {
compatible = rockchip,rk3288-cru;
reg = 0xff76 0x1000;
@@ -1040,5 +1066,38 @@
rockchip,pins = 7 23 3 pcfg_pull_none;
};
};
+
+   gmac {
+   rgmii_pin: rgmii-pins {
+   rockchip,pins = 3 30 3 pcfg_pull_none,
+   3 31 3 pcfg_pull_none,
+   3 26 3 pcfg_pull_none,
+   3 27 3 pcfg_pull_none,
+   3 28 3 pcfg_pull_none,
+   3 29 3 pcfg_pull_none,
+   3 24 3 pcfg_pull_none,
+   3 25 3 pcfg_pull_none,
+   4 0 3 pcfg_pull_none,
+   4 5 3 pcfg_pull_none,
+   4 6 3 pcfg_pull_none,
+   4 9 3 pcfg_pull_none,
+   4 4 3 pcfg_pull_none,
+   4 1 3 pcfg_pull_none,
+   4 3 3 pcfg_pull_none;
+   };
+
+   rmii_pin: rmii-pins {
+   rockchip,pins = 3 30 3 pcfg_pull_none,
+   3 31 3 pcfg_pull_none,
+   3 28 3 pcfg_pull_none,
+   3 29 3 pcfg_pull_none,
+   4 0 3 pcfg_pull_none,
+   4 5 3 pcfg_pull_none,
+   4 4 3 pcfg_pull_none,
+   4 1 3 pcfg_pull_none,
+   4 2 3 pcfg_pull_none,
+   4 3 3 pcfg_pull_none;
+   };
+   };
};
  };


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Re: [PATCH 4/4] GMAC: dts: enable gmac on RK3288 evb board

[Kever Yang]

Hi Roger,

The subject should prefix:
Arm: dts: rockchip: enable ...

On 11/25/2014 05:09 PM, Roger Chen wrote:

enable gmac in rk3288-evb-rk808.dts

Signed-off-by: Roger Chen roger.c...@rock-chips.com
---
  arch/arm/boot/dts/rk3288-evb-rk808.dts |   22 ++
  1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts 
b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index d8c775e6..168b4fa 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -152,3 +152,25 @@
};
};
  };
+
+ext_gmac {
+   clock-frequency = 12500;
+   clock-output-names = ext_gmac;
+};
+
+gmac {
+   //pmu_regulator = act_ldo5;
+   //pmu_enable_level = 1; //1-HIGH, 0-LOW

remove these unused code.

+   power-gpio = gpio0 6 GPIO_ACTIVE_HIGH;
+   reset-gpio = gpio4 7 GPIO_ACTIVE_LOW;
+   //phyirq-gpio = gpio4 2 GPIO_ACTIVE_LOW;

same.

+   phy-mode = rgmii;
+   clock_in_out = input;
+   assigned-clocks = cru SCLK_MAC;
+   assigned-clock-parents = ext_gmac;
+   pinctrl-names = default;
+   pinctrl-0 = rgmii_pin; /*rmii_pin*/

same.

- Kever

+   tx_delay = 0x30;
+   rx_delay = 0x10;
+   status = ok;
+};


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Re: [PATCH 0/2] Increase the maximum cpu frequency of rk3288

[Kever Yang]

Hi Chris,

On 11/25/2014 05:37 PM, Chris Zhong wrote:

The maximum cpu frequency of rk3288 can up to 1.8Ghz, but the vdd_cpu need set
to 1.4v. I've tested these patches on rk3288 evb board.

I'm not sure why you need this patch, I think we have a discuss
for the cpu operating point before.
In this case:
1. rk3288.dtsi is for all the rk3288 Soc based system, you may need
a separate opp table in rk3288-evb-rk808.dts;
2. 1.4V may beyond the supported voltage range too much,
and it's not a good idea to add it to rk3288.dtsi as a safe voltage.
3. Do you have a stress/heavy load test on evb with 1.4v at 1.8GHz?

- Kever



Chris Zhong (2):
   ARM: dts: rockchip: change the max voltage of cpu to 1.4v
   ARM: dts: rk3288: change the max clk of cpu to 1.8Ghz

  arch/arm/boot/dts/rk3288-evb-rk808.dts | 2 +-
  arch/arm/boot/dts/rk3288.dtsi  | 6 --
  2 files changed, 5 insertions(+), 3 deletions(-)




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Re: [PATCH 0/4] support GMAC driver for RK3288

[Kever Yang]

Hi Roger,

Please use the --in-reply-to option for patches other than 0/4
with the git send-email.

On 11/25/2014 05:07 PM, Roger Chen wrote:

Roger Chen (4):
   patch1: add driver for Rockchip RK3288 SoCs integrated GMAC
   patch2: modify CRU config for Rockchip RK3288 SoCs integrated GMAC
   patch3: dts: add gmac info for rk3288
   patch4: dts: enable gmac on RK3288 evb board

tested on rk3288 SDK board:
busybox ifconfig eth0 up
busybox ifconfig eth0 192.168.1.111
ping 192.168.1.1




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Re: [PATCH v2 2/2] ASoC: rockchip: i2s: add support for grabbing output clock to codec

[Kever Yang]

Hi Jay,

On 11/19/2014 04:09 PM, Jianqun Xu wrote:

Patch is from Sonny Rao 

Here should be,

From: Sonny Rao 

- Kever

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Re: [PATCH v2 2/2] ASoC: rockchip: i2s: add support for grabbing output clock to codec

[Kever Yang]

Hi Jay,

On 11/19/2014 04:09 PM, Jianqun Xu wrote:

Patch is from Sonny Rao sonny...@chromium.org

Here should be,

From: Sonny Rao sonny...@chromium.org

- Kever

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[PATCH v2] usb: dwc2: resume root hub when device detect with suspend state

[Kever Yang]

After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.

This patch tested on rk3288.

Signed-off-by: Roy Li 
Signed-off-by: Kever Yang 
---

Changes in v2:
- add definition for hcd structure
- remove check for bus->root_hub

 drivers/usb/dwc2/hcd_intr.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index 551ba87..680206f 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -329,6 +329,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
 {
u32 hprt0;
u32 hprt0_modify;
+   struct usb_hcd *hcd = (struct usb_hcd *)hsotg->priv;
 
dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
 
@@ -354,6 +355,10 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
hsotg->flags.b.port_connect_status = 1;
hprt0_modify |= HPRT0_CONNDET;
 
+   /* resume root hub? */
+   if (hcd->state == HC_STATE_SUSPENDED)
+   usb_hcd_resume_root_hub(hcd);
+
/*
 * The Hub driver asserts a reset when it sees port connect
 * status change flag
-- 
1.9.1

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Re: [PATCH] usb: dwc2: resume root hub when device detect with suspend state

[Kever Yang]

Hi Julius,

On 11/18/2014 05:21 AM, Julius Werner wrote:

On Mon, Nov 17, 2014 at 5:14 AM, Kever Yang  wrote:

After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.

This patch tested on rk3288.

Signed-off-by: Roy Li 
Signed-off-by: Kever Yang 
---

  drivers/usb/dwc2/hcd_intr.c | 7 +++
  1 file changed, 7 insertions(+)

diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index 551ba87..c8299fd 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -355,6 +355,13 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
 hprt0_modify |= HPRT0_CONNDET;

 /*
+* Check if root hub is in suspend state
+* if root hub in suspend, resume it.
+*/
+   if ((bus->root_hub) && (hcd->state == HC_STATE_SUSPENDED))

What is bus->root_hub checking for? Is there any chance that this
could be NULL here?

I add bus->root_hub check because the _dwc2_hcd_start check this before it
call the usb_hcd_resume_root_hub.
I think we don't need this check for the root_hub must be there if we 
register

the HCD success, right?
I will remove this in next version.



+   usb_hcd_resume_root_hub(hcd);
+
+   /*
  * The Hub driver asserts a reset when it sees port connect
  * status change flag
  */
--
1.9.1

Seems sensible in general. Does this actually fix the problem Doug was
reporting?
Yes, this fix the problem Doug reported with my dwc2 hcd suspend/resume 
patch.


- Kever

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Re: [PATCH] usb: dwc2: resume root hub when device detect with suspend state

[Kever Yang]

This patch is no complete, Sorry for that, I will upload a new version 
tomorrow.


- Kever

On 11/17/2014 09:14 PM, Kever Yang wrote:

After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.

This patch tested on rk3288.

Signed-off-by: Roy Li 
Signed-off-by: Kever Yang 
---

  drivers/usb/dwc2/hcd_intr.c | 7 +++
  1 file changed, 7 insertions(+)

diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index 551ba87..c8299fd 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -355,6 +355,13 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
hprt0_modify |= HPRT0_CONNDET;
  
  		/*

+* Check if root hub is in suspend state
+* if root hub in suspend, resume it.
+*/
+   if ((bus->root_hub) && (hcd->state == HC_STATE_SUSPENDED))
+   usb_hcd_resume_root_hub(hcd);
+
+   /*
 * The Hub driver asserts a reset when it sees port connect
 * status change flag
 */


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[RFC PATCH 2/2] arm: dts: rockchip: select npll as parent of DCLK_VOP0

[Kever Yang]

The DCLK_VOP0 will change the parent clock's rate, we don't want
to change the PLLs rate other than npll. So we select the npll
as parent directly.

Signed-off-by: Kever Yang 
---

 arch/arm/boot/dts/rk3288.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index c3190f7..6ea6125 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -573,6 +573,8 @@
interrupts = ;
clocks = < ACLK_VOP0>, < DCLK_VOP0>, < HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+   assigned-clocks = < DCLK_VOP0>;
+   assigned-clock-parents = <3>;
resets = < SRST_LCDC0_AXI>, < SRST_LCDC0_AHB>, < 
SRST_LCDC0_DCLK>;
reset-names = "axi", "ahb", "dclk";
iommus = <_mmu>;
-- 
1.9.1

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[RFC PATCH 1/2] clk: rockchip: leave npll for VOP0 only

[Kever Yang]

We will need a pll to support all kinds of clock rate requirement
for HDMI(from DCLK_VOP0) which may change the rate at run time.

In order not to affect other clocks, remove the npll from the
parent list of other clocks and only DCLK_VOP0 can select npll
as parent.

Signed-off-by: Kever Yang 
---

 drivers/clk/rockchip/clk-rk3288.c | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index b4a74c2..6eb1407 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -174,7 +174,7 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
 PNAME(mux_aclk_cpu_src_p)  = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
 
 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
-PNAME(mux_pll_src_npll_cpll_gpll_p)= { "npll", "cpll", "gpll" };
+PNAME(mux_pll_src_npll_cpll_gpll_p)= { "dummy", "cpll", "gpll" };
 PNAME(mux_pll_src_cpll_gpll_npll_p)= { "cpll", "gpll", "npll" };
 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usbphy480m_src" };
 PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", 
"npll" };
@@ -392,24 +392,24 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 4, GFLAGS),
 
-   COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 
CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 1, GFLAGS),
-   COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 3, GFLAGS),
 
COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
RK3288_CLKGATE_CON(3), 12, GFLAGS),
-   COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 13, GFLAGS),
 
-   COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 14, GFLAGS),
-   COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 15, GFLAGS),
 
@@ -418,16 +418,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
RK3288_CLKGATE_CON(5), 11, GFLAGS),
 
-   COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 13, GFLAGS),
DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
 
-   COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", 
mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_p, 
0,
RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 14, GFLAGS),
-   COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", 
mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 15, GFLAGS),
 
@@ -443,7 +443,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
RK3288_CLKGATE_CON(5), 8, GFLAGS),
 
-   COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll

[RFC PATCH 0/2] clk: rockchip: leave npll for DCLK_VOP0(HDMI) only

[Kever Yang]

To support all kinds of frequency requirement for HDMI on rk3288,
we need a PLL that can change rate at run time.

There are some discussion before at [0], I think we can just leave
the npll for HDMI(DCLK_VOP0) used to make it simple.

Comments are welcome.

[0] https://lkml.org/lkml/2014/11/4/58


Kever Yang (2):
  clk: rockchip: leave npll for VOP0 only
  arm: dts: rockchip: select npll as parent of DCLK_VOP0

 arch/arm/boot/dts/rk3288.dtsi |  2 ++
 drivers/clk/rockchip/clk-rk3288.c | 24 
 2 files changed, 14 insertions(+), 12 deletions(-)

-- 
1.9.1

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Re: [PATCH v3] usb: dwc2: add bus suspend/resume for dwc2

[Kever Yang]

On 11/14/2014 11:55 PM, Alan Stern wrote:

On Thu, 13 Nov 2014, Julius Werner wrote:


Another thing might be that the port connect interrupt does not
correctly resume the root hub. I don't really know many details about
how that works, and it seems pretty complicated. But I can see that
all other HCDs seem to call usb_hcd_resume_root_hub() from their
interrupt handlers, which we don't. There's also a

That's how a root hub sends a wakeup request to the kernel.  The
controller issues an interrupt, and when the HCD's interrupt handler
sees that the root hub is suspended, it calls usb_hcd_resume_root_hub()
instead of trying to query the hardware (because in general you _can't_
query the hardware while it's in a low-power state).

Thanks Alan and Julius, just like what you have mentioned, the dwc2 miss the
usb_hcd_resume_root_hub() when root hub is suspended and device connect
detected.

I have send another patch for that, hope it did the right thing.

- Kever

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[PATCH] usb: dwc2: resume root hub when device detect with suspend state

[Kever Yang]

After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.

This patch tested on rk3288.

Signed-off-by: Roy Li 
Signed-off-by: Kever Yang 
---

 drivers/usb/dwc2/hcd_intr.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index 551ba87..c8299fd 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -355,6 +355,13 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
hprt0_modify |= HPRT0_CONNDET;
 
/*
+* Check if root hub is in suspend state
+* if root hub in suspend, resume it.
+*/
+   if ((bus->root_hub) && (hcd->state == HC_STATE_SUSPENDED))
+   usb_hcd_resume_root_hub(hcd);
+
+   /*
 * The Hub driver asserts a reset when it sees port connect
 * status change flag
 */
-- 
1.9.1

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[PATCH] usb: dwc2: resume root hub when device detect with suspend state

[Kever Yang]

After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.

This patch tested on rk3288.

Signed-off-by: Roy Li roy...@rock-chips.com
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 drivers/usb/dwc2/hcd_intr.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index 551ba87..c8299fd 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -355,6 +355,13 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
hprt0_modify |= HPRT0_CONNDET;
 
/*
+* Check if root hub is in suspend state
+* if root hub in suspend, resume it.
+*/
+   if ((bus-root_hub)  (hcd-state == HC_STATE_SUSPENDED))
+   usb_hcd_resume_root_hub(hcd);
+
+   /*
 * The Hub driver asserts a reset when it sees port connect
 * status change flag
 */
-- 
1.9.1

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Re: [PATCH v3] usb: dwc2: add bus suspend/resume for dwc2

[Kever Yang]

On 11/14/2014 11:55 PM, Alan Stern wrote:

On Thu, 13 Nov 2014, Julius Werner wrote:


Another thing might be that the port connect interrupt does not
correctly resume the root hub. I don't really know many details about
how that works, and it seems pretty complicated. But I can see that
all other HCDs seem to call usb_hcd_resume_root_hub() from their
interrupt handlers, which we don't. There's also a

That's how a root hub sends a wakeup request to the kernel.  The
controller issues an interrupt, and when the HCD's interrupt handler
sees that the root hub is suspended, it calls usb_hcd_resume_root_hub()
instead of trying to query the hardware (because in general you _can't_
query the hardware while it's in a low-power state).

Thanks Alan and Julius, just like what you have mentioned, the dwc2 miss the
usb_hcd_resume_root_hub() when root hub is suspended and device connect
detected.

I have send another patch for that, hope it did the right thing.

- Kever

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[RFC PATCH 0/2] clk: rockchip: leave npll for DCLK_VOP0(HDMI) only

[Kever Yang]

To support all kinds of frequency requirement for HDMI on rk3288,
we need a PLL that can change rate at run time.

There are some discussion before at [0], I think we can just leave
the npll for HDMI(DCLK_VOP0) used to make it simple.

Comments are welcome.

[0] https://lkml.org/lkml/2014/11/4/58


Kever Yang (2):
  clk: rockchip: leave npll for VOP0 only
  arm: dts: rockchip: select npll as parent of DCLK_VOP0

 arch/arm/boot/dts/rk3288.dtsi |  2 ++
 drivers/clk/rockchip/clk-rk3288.c | 24 
 2 files changed, 14 insertions(+), 12 deletions(-)

-- 
1.9.1

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[RFC PATCH 1/2] clk: rockchip: leave npll for VOP0 only

[Kever Yang]

We will need a pll to support all kinds of clock rate requirement
for HDMI(from DCLK_VOP0) which may change the rate at run time.

In order not to affect other clocks, remove the npll from the
parent list of other clocks and only DCLK_VOP0 can select npll
as parent.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 drivers/clk/rockchip/clk-rk3288.c | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index b4a74c2..6eb1407 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -174,7 +174,7 @@ PNAME(mux_ddrphy_p) = { dpll_ddr, gpll_ddr };
 PNAME(mux_aclk_cpu_src_p)  = { cpll_aclk_cpu, gpll_aclk_cpu };
 
 PNAME(mux_pll_src_cpll_gpll_p) = { cpll, gpll };
-PNAME(mux_pll_src_npll_cpll_gpll_p)= { npll, cpll, gpll };
+PNAME(mux_pll_src_npll_cpll_gpll_p)= { dummy, cpll, gpll };
 PNAME(mux_pll_src_cpll_gpll_npll_p)= { cpll, gpll, npll };
 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { cpll, gpll, usbphy480m_src };
 PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { cpll, gpll, usbphy480m_src, 
npll };
@@ -392,24 +392,24 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 4, GFLAGS),
 
-   COMPOSITE(DCLK_VOP0, dclk_vop0, mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(DCLK_VOP0, dclk_vop0, mux_pll_src_cpll_gpll_npll_p, 
CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 1, GFLAGS),
-   COMPOSITE(DCLK_VOP1, dclk_vop1, mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(DCLK_VOP1, dclk_vop1, mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 3, GFLAGS),
 
COMPOSITE_NODIV(SCLK_EDP_24M, sclk_edp_24m, mux_edp_24m_p, 0,
RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
RK3288_CLKGATE_CON(3), 12, GFLAGS),
-   COMPOSITE(SCLK_EDP, sclk_edp, mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(SCLK_EDP, sclk_edp, mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 13, GFLAGS),
 
-   COMPOSITE(SCLK_ISP, sclk_isp, mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(SCLK_ISP, sclk_isp, mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 14, GFLAGS),
-   COMPOSITE(SCLK_ISP_JPE, sclk_isp_jpe, mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(SCLK_ISP_JPE, sclk_isp_jpe, mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 15, GFLAGS),
 
@@ -418,16 +418,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
GATE(SCLK_HDMI_CEC, sclk_hdmi_cec, xin32k, 0,
RK3288_CLKGATE_CON(5), 11, GFLAGS),
 
-   COMPOSITE(ACLK_HEVC, aclk_hevc, mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(ACLK_HEVC, aclk_hevc, mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 13, GFLAGS),
DIV(HCLK_HEVC, hclk_hevc, aclk_hevc, 0,
RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
 
-   COMPOSITE(SCLK_HEVC_CABAC, sclk_hevc_cabac, 
mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(SCLK_HEVC_CABAC, sclk_hevc_cabac, mux_pll_src_cpll_gpll_p, 
0,
RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 14, GFLAGS),
-   COMPOSITE(SCLK_HEVC_CORE, sclk_hevc_core, 
mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE(SCLK_HEVC_CORE, sclk_hevc_core, mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 15, GFLAGS),
 
@@ -443,7 +443,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
RK3288_CLKGATE_CON(5), 8, GFLAGS),
 
-   COMPOSITE(SCLK_GPU, sclk_gpu, mux_pll_src_cpll_gll_usb_npll_p, 0,
+   COMPOSITE(SCLK_GPU, sclk_gpu, mux_pll_src_cpll_gpll_usb480m_p, 0,
RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(5), 7, GFLAGS),
 
@@ -489,7 +489,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
COMPOSITE(0, sclk_tspout, mux_tspout_p, 0,
RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(4), 11

[RFC PATCH 2/2] arm: dts: rockchip: select npll as parent of DCLK_VOP0

[Kever Yang]

The DCLK_VOP0 will change the parent clock's rate, we don't want
to change the PLLs rate other than npll. So we select the npll
as parent directly.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 arch/arm/boot/dts/rk3288.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index c3190f7..6ea6125 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -573,6 +573,8 @@
interrupts = GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH;
clocks = cru ACLK_VOP0, cru DCLK_VOP0, cru HCLK_VOP0;
clock-names = aclk_vop, dclk_vop, hclk_vop;
+   assigned-clocks = cru DCLK_VOP0;
+   assigned-clock-parents = 3;
resets = cru SRST_LCDC0_AXI, cru SRST_LCDC0_AHB, cru 
SRST_LCDC0_DCLK;
reset-names = axi, ahb, dclk;
iommus = vopb_mmu;
-- 
1.9.1

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Re: [PATCH] usb: dwc2: resume root hub when device detect with suspend state

[Kever Yang]

This patch is no complete, Sorry for that, I will upload a new version 
tomorrow.


- Kever

On 11/17/2014 09:14 PM, Kever Yang wrote:

After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.

This patch tested on rk3288.

Signed-off-by: Roy Li roy...@rock-chips.com
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

  drivers/usb/dwc2/hcd_intr.c | 7 +++
  1 file changed, 7 insertions(+)

diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index 551ba87..c8299fd 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -355,6 +355,13 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
hprt0_modify |= HPRT0_CONNDET;
  
  		/*

+* Check if root hub is in suspend state
+* if root hub in suspend, resume it.
+*/
+   if ((bus-root_hub)  (hcd-state == HC_STATE_SUSPENDED))
+   usb_hcd_resume_root_hub(hcd);
+
+   /*
 * The Hub driver asserts a reset when it sees port connect
 * status change flag
 */


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Re: [PATCH] usb: dwc2: resume root hub when device detect with suspend state

[Kever Yang]

Hi Julius,

On 11/18/2014 05:21 AM, Julius Werner wrote:

On Mon, Nov 17, 2014 at 5:14 AM, Kever Yang kever.y...@rock-chips.com wrote:

After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.

This patch tested on rk3288.

Signed-off-by: Roy Li roy...@rock-chips.com
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

  drivers/usb/dwc2/hcd_intr.c | 7 +++
  1 file changed, 7 insertions(+)

diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index 551ba87..c8299fd 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -355,6 +355,13 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
 hprt0_modify |= HPRT0_CONNDET;

 /*
+* Check if root hub is in suspend state
+* if root hub in suspend, resume it.
+*/
+   if ((bus-root_hub)  (hcd-state == HC_STATE_SUSPENDED))

What is bus-root_hub checking for? Is there any chance that this
could be NULL here?

I add bus-root_hub check because the _dwc2_hcd_start check this before it
call the usb_hcd_resume_root_hub.
I think we don't need this check for the root_hub must be there if we 
register

the HCD success, right?
I will remove this in next version.



+   usb_hcd_resume_root_hub(hcd);
+
+   /*
  * The Hub driver asserts a reset when it sees port connect
  * status change flag
  */
--
1.9.1

Seems sensible in general. Does this actually fix the problem Doug was
reporting?
Yes, this fix the problem Doug reported with my dwc2 hcd suspend/resume 
patch.


- Kever

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[PATCH v2] usb: dwc2: resume root hub when device detect with suspend state

[Kever Yang]

After we implement the bus_suspend/resume, auto suspend id enabled.
The root hub will be auto suspend if there is no device connected,
we need to resume the root hub when a device connect detect.

This patch tested on rk3288.

Signed-off-by: Roy Li roy...@rock-chips.com
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

Changes in v2:
- add definition for hcd structure
- remove check for bus-root_hub

 drivers/usb/dwc2/hcd_intr.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index 551ba87..680206f 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -329,6 +329,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
 {
u32 hprt0;
u32 hprt0_modify;
+   struct usb_hcd *hcd = (struct usb_hcd *)hsotg-priv;
 
dev_vdbg(hsotg-dev, --Port Interrupt--\n);
 
@@ -354,6 +355,10 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
hsotg-flags.b.port_connect_status = 1;
hprt0_modify |= HPRT0_CONNDET;
 
+   /* resume root hub? */
+   if (hcd-state == HC_STATE_SUSPENDED)
+   usb_hcd_resume_root_hub(hcd);
+
/*
 * The Hub driver asserts a reset when it sees port connect
 * status change flag
-- 
1.9.1

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Re: [PATCH 0/5] clk: rockchip: add full support for HDMI clock on rk3288

[Kever Yang]

Hi

On 11/14/2014 09:46 AM, Mike Turquette wrote:

Looking through the clock-tree there are a lot more components possibly
> >>using
> >>(or wanting to use) the npll: of course the VOPs, the edp, hdmi, isp,
> >>hevc,
> >>gpu, tsp uart0 and gmac. So I'm slightly uncomfortable with somehow
> >>reserving
> >>the npll for VOP0 alone.

I understand the concern for other module clocks which may use NPLL as
parent, we have to make sure all these clocks can get what they want even
if NPLL is not available for them. So, let's have a look at them(without 
NPLL):

with CPLL 400M and GPLL 594M,

GPU/HEVC/ISP/TSP can get 100/200/400 from CPLL, and ~300/600 from GPLL,
   and ~500 from usbphy480m, these should be enough for those modules.

DCLK_VOP1 for eDP/MIPI/LVDS, these clock can accept maybe more than 5%
margin, we can get enough frequency for them now, we can change the CPLL
to 800MHz for more option if it's needed one day.

GMAC can get 50M from CPLL, usually we use external clock for GMAC.

uart0 have frac divider, so we don't need to worry too much for it.




> >
> >It's true that I customized the usage of npll for VOP0 when we need some
> >very special frequency, but it doesn't means other modules can't use the
> >npll, it will always decided by clock core for module clocks that which
> >parent
> >is the best.

>
>We will just need to be very careful.  As I've mentioned in the past
>we'll need to think about what happens to other clocks that happen to
>be parented by NPLL whenever we change it.
>
>So if we do this:
>
>1. NPLL happens to be 500MHz.
>2. We set GPU to be 500MHz and it picks NPLL.
>3. We change NPLL to a different speed (like 600MHz).
>
>...I believe in this scenario the GPU would start running at 600MHz
>immediately.  We'd need to add special code to watch out for this and
>pick an alternate clock for the GPU (like the USB 480) before the NPLL
>change.  If NPLL later changes back to 500MHz and the GPU still wanted
>500MHz, we'd have to decide what to do.
>
>
>The summary is: it's pretty complicated

It's complicated if there are more than one clock share the PLL and
one of the clock wants to change the PLL output rate.

Most of module clocks can't be changed during they are work, and it
is better to route those clocks to a parent that would not change.

Some of PLLs should not be changed after system initialized and they
can be source for most of module clocks while some of PLLs have to
change for some special requirement like HDMI that we can know
the required frequency only when the device is plug in at run time.

To make it simple, we can use the NPLL exclusively for HDMI/VOP0,
just like what we do for APLL for cpu and DPLL for DDR, although what
I though was share NPLL with other clocks in most of time, maybe we
can use this case in the product like OTT BOX which will always have
HDMI pluged.

Maybe we can add an attribute for clock like NPLL in this way?
There is an owner children for NPLL(for example VOP0) which can change 
NPLL's rate,
and there it a fixed_rate attribute to describe if this clock is fixed 
or not.


If VOP0 is not enabled, NPLL output is unfixed, other children clock can
decide if they want to use a parent with unfixed output or another 
parent with

fixed output.

If VOP0 is enabled, then the NPLL's output has decide by the VOP0 and it 
become

a fixed output parent.


+Stephen Boyd & Tomeu Vizoso

Managing shared clocks is a subset of the general problems with clock
constraints. Maybe Stephen or Tomeu have some comment here?



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Re: [PATCH 0/5] clk: rockchip: add full support for HDMI clock on rk3288

[Kever Yang]

Hi

On 11/14/2014 09:46 AM, Mike Turquette wrote:

Looking through the clock-tree there are a lot more components possibly
 using
 (or wanting to use) the npll: of course the VOPs, the edp, hdmi, isp,
 hevc,
 gpu, tsp uart0 and gmac. So I'm slightly uncomfortable with somehow
 reserving
 the npll for VOP0 alone.

I understand the concern for other module clocks which may use NPLL as
parent, we have to make sure all these clocks can get what they want even
if NPLL is not available for them. So, let's have a look at them(without 
NPLL):

with CPLL 400M and GPLL 594M,

GPU/HEVC/ISP/TSP can get 100/200/400 from CPLL, and ~300/600 from GPLL,
   and ~500 from usbphy480m, these should be enough for those modules.

DCLK_VOP1 for eDP/MIPI/LVDS, these clock can accept maybe more than 5%
margin, we can get enough frequency for them now, we can change the CPLL
to 800MHz for more option if it's needed one day.

GMAC can get 50M from CPLL, usually we use external clock for GMAC.

uart0 have frac divider, so we don't need to worry too much for it.




 
 It's true that I customized the usage of npll for VOP0 when we need some
 very special frequency, but it doesn't means other modules can't use the
 npll, it will always decided by clock core for module clocks that which
 parent
 is the best.


We will just need to be very careful.  As I've mentioned in the past
we'll need to think about what happens to other clocks that happen to
be parented by NPLL whenever we change it.

So if we do this:

1. NPLL happens to be 500MHz.
2. We set GPU to be 500MHz and it picks NPLL.
3. We change NPLL to a different speed (like 600MHz).

...I believe in this scenario the GPU would start running at 600MHz
immediately.  We'd need to add special code to watch out for this and
pick an alternate clock for the GPU (like the USB 480) before the NPLL
change.  If NPLL later changes back to 500MHz and the GPU still wanted
500MHz, we'd have to decide what to do.


The summary is: it's pretty complicated

It's complicated if there are more than one clock share the PLL and
one of the clock wants to change the PLL output rate.

Most of module clocks can't be changed during they are work, and it
is better to route those clocks to a parent that would not change.

Some of PLLs should not be changed after system initialized and they
can be source for most of module clocks while some of PLLs have to
change for some special requirement like HDMI that we can know
the required frequency only when the device is plug in at run time.

To make it simple, we can use the NPLL exclusively for HDMI/VOP0,
just like what we do for APLL for cpu and DPLL for DDR, although what
I though was share NPLL with other clocks in most of time, maybe we
can use this case in the product like OTT BOX which will always have
HDMI pluged.

Maybe we can add an attribute for clock like NPLL in this way?
There is an owner children for NPLL(for example VOP0) which can change 
NPLL's rate,
and there it a fixed_rate attribute to describe if this clock is fixed 
or not.


If VOP0 is not enabled, NPLL output is unfixed, other children clock can
decide if they want to use a parent with unfixed output or another 
parent with

fixed output.

If VOP0 is enabled, then the NPLL's output has decide by the VOP0 and it 
become

a fixed output parent.


+Stephen Boyd  Tomeu Vizoso

Managing shared clocks is a subset of the general problems with clock
constraints. Maybe Stephen or Tomeu have some comment here?



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[RFC PATCH 2/2] dt-bindings: clk: add document for assigned-clock-force-rates usage

[Kever Yang]

This patch adds document for how to use the opetion property
assigned-clock-force-rates.

We may use this property to force update a clock setting.

Signed-off-by: Kever Yang 
---

 Documentation/devicetree/bindings/clock/clock-bindings.txt | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt 
b/Documentation/devicetree/bindings/clock/clock-bindings.txt
index 06fc6d5..fb5d3a5 100644
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -154,11 +154,14 @@ set to 0, or can be omitted if it is not followed by any 
non-zero entry.
 
 assigned-clocks = < 0>, < 2>;
 assigned-clock-parents = < 2>;
+assigned-clock-force-rates = <50>, <0>;
 assigned-clock-rates = <0>, <460800>;
 };
 
-In this example the < 2> clock is set as parent of clock < 0> and
-the < 2> clock is assigned a frequency value of 460800 Hz.
+In this example the < 2> clock is set as parent of clock < 0>,
+the < 0> clock is assigned a frequency value of 50 Hz and make
+sure the we get into assigned-clock-rates even if there is no rate change,
+and the < 2> clock is assigned a frequency value of 460800 Hz.
 
 Configuring a clock's parent and rate through the device node that consumes
 the clock can be done only for clocks that have a single user. Specifying
-- 
1.9.1

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[RFC PATCH 1/2] clk: add property for force to update clock setting

[Kever Yang]

Usually we assigned a clock to a default rate in dts,
there is a situation that the clock already initialized to the rate
we intend to set before kernel(hardware default or init in uboot etc).
For the PLLs we can get a rate from different PLL parameter configure,
we can't change the PLL parameter if the rate is not changed by now.

This patch adds a option property 'assigned-clock-force-rates'
to make sure we update all the setting even if we don't need to
update the clock rate.

Signed-off-by: Kever Yang 
---

 drivers/clk/clk-conf.c | 33 -
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
index aad4796..0c9df48 100644
--- a/drivers/clk/clk-conf.c
+++ b/drivers/clk/clk-conf.c
@@ -84,7 +84,7 @@ static int __set_clk_rates(struct device_node *node, bool 
clk_supplier)
struct clk *clk;
u32 rate;
 
-   of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) 
{
+   of_property_for_each_u32(node, "assigned-force-rates", prop, cur, rate) 
{
if (rate) {
rc = of_parse_phandle_with_args(node, "assigned-clocks",
"#clock-cells", index, );
@@ -104,7 +104,38 @@ static int __set_clk_rates(struct device_node *node, bool 
clk_supplier)
index, node->full_name);
return PTR_ERR(clk);
}
+   /* change the old rate to 0 to make sure we can get into
+* clk_change_rate */
+   clk->rate = 0;
+   rc = clk_set_rate(clk, rate);
+   if (rc < 0)
+   pr_err("clk: couldn't set %s clock rate: %d\n",
+  __clk_get_name(clk), rc);
+   clk_put(clk);
+   }
+   index++;
+   }
 
+   of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) 
{
+   if (rate) {
+   rc = of_parse_phandle_with_args(node, "assigned-clocks",
+   "#clock-cells", index, );
+   if (rc < 0) {
+   /* skip empty (null) phandles */
+   if (rc == -ENOENT)
+   continue;
+   else
+   return rc;
+   }
+   if (clkspec.np == node && !clk_supplier)
+   return 0;
+
+   clk = of_clk_get_by_clkspec();
+   if (IS_ERR(clk)) {
+   pr_warn("clk: couldn't get clock %d for %s\n",
+   index, node->full_name);
+   return PTR_ERR(clk);
+   }
rc = clk_set_rate(clk, rate);
if (rc < 0)
pr_err("clk: couldn't set %s clock rate: %d\n",
-- 
1.9.1

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[RFC PATCH 0/2] add dts property to force update a clock setting

[Kever Yang]

When we assgined a clock rate in dts, we may need to update
the clock setting like PLLs who can get the same output rate with
different parameter even if we don't need to change the rate.


Kever Yang (2):
  clk: add property for force to update clock setting
  dt-bindings: clk: add document for assigned-clock-force-rates usage

 .../devicetree/bindings/clock/clock-bindings.txt   |  7 +++--
 drivers/clk/clk-conf.c | 33 +-
 2 files changed, 37 insertions(+), 3 deletions(-)

-- 
1.9.1

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Re: [PATCH 0/5] clk: rockchip: add full support for HDMI clock on rk3288

[Kever Yang]

Hi Heiko,

On 11/07/2014 05:06 AM, Heiko Stübner wrote:

Hi Kever,

Am Dienstag, 4. November 2014, 15:52:34 schrieb Kever Yang:

we are going to make a clock usage solution for rk3288:
1. CPLL and GPLL always not change after assign init;
2. NPLL default as 500MHz, may used for most scene;
3. NPLL may be changed by VOP(HDMI) clock for some special
frequency requirement.

 I test it with rk3288 evb on top of Heiko's clk-for-next

In general I'm not really sure if allowing one component to arbitarily change
a shared clock wouldn't result in trouble.

At the moment only dclk_vop0 is included in your series, while the hdmi
controller can connect to both vop0 and vop1.
And as Doug mentioned the gpu also has the npll as one possible source.

I think the problem GPU HANGs with 480MHz clock from usbphy has
been fixed with my patch to gerrit:
https://chromium-review.googlesource.com/#/c/229554/


Looking through the clock-tree there are a lot more components possibly using
(or wanting to use) the npll: of course the VOPs, the edp, hdmi, isp, hevc,
gpu, tsp uart0 and gmac. So I'm slightly uncomfortable with somehow reserving
the npll for VOP0 alone.

It's true that I customized the usage of npll for VOP0 when we need some
very special frequency, but it doesn't means other modules can't use the
npll, it will always decided by clock core for module clocks that which 
parent

is the best.

I'll be very happy if there is a better solution for this situation, and any
suggestion is welcome.

- Kever


But I also don't see a different way to get these frequencies right now.


Heiko





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[PATCH] clk: rockchip: fix clock select order for usbphy480m_src

[Kever Yang]

According to rk3288 trm, the mux selector locate at bit[12:11]
of CRU_CLKSEL13_CON shows:
2'b00: select HOST0 USB pll clock (clk_otgphy1)
2'b01: select HOST1 USB pll clock (clk_otgphy2)
2'b10: select OTG USB pll clock   (clk_otgphy0)

The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3
- clk_otgphy0 -> USB PHY OTG
- clk_otgphy1 -> USB PHY host0
- clk_otgphy2 -> USB PHY host1

Signed-off-by: Kever Yang 
---

 drivers/clk/rockchip/clk-rk3288.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 157b60b..4d70518 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -195,8 +195,8 @@ PNAME(mux_hsadcout_p)   = { "hsadc_src", "ext_hsadc" };
 PNAME(mux_edp_24m_p)   = { "ext_edp_24m", "xin24m" };
 PNAME(mux_tspout_p)= { "cpll", "gpll", "npll", "xin27m" };
 
-PNAME(mux_usbphy480m_p)= { "sclk_otgphy0", "sclk_otgphy1",
-   "sclk_otgphy2" };
+PNAME(mux_usbphy480m_p)= { "sclk_otgphy1", "sclk_otgphy2",
+   "sclk_otgphy0" };
 PNAME(mux_hsicphy480m_p)   = { "cpll", "gpll", "usbphy480m_src" };
 PNAME(mux_hsicphy12m_p)= { "hsicphy12m_xin12m", 
"hsicphy12m_usbphy" };
 
-- 
1.9.1

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[PATCH] clk: rockchip: fix clock select order for usbphy480m_src

[Kever Yang]

According to rk3288 trm, the mux selector locate at bit[12:11]
of CRU_CLKSEL13_CON shows:
2'b00: select HOST0 USB pll clock (clk_otgphy1)
2'b01: select HOST1 USB pll clock (clk_otgphy2)
2'b10: select OTG USB pll clock   (clk_otgphy0)

The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3
- clk_otgphy0 - USB PHY OTG
- clk_otgphy1 - USB PHY host0
- clk_otgphy2 - USB PHY host1

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 drivers/clk/rockchip/clk-rk3288.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 157b60b..4d70518 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -195,8 +195,8 @@ PNAME(mux_hsadcout_p)   = { hsadc_src, ext_hsadc };
 PNAME(mux_edp_24m_p)   = { ext_edp_24m, xin24m };
 PNAME(mux_tspout_p)= { cpll, gpll, npll, xin27m };
 
-PNAME(mux_usbphy480m_p)= { sclk_otgphy0, sclk_otgphy1,
-   sclk_otgphy2 };
+PNAME(mux_usbphy480m_p)= { sclk_otgphy1, sclk_otgphy2,
+   sclk_otgphy0 };
 PNAME(mux_hsicphy480m_p)   = { cpll, gpll, usbphy480m_src };
 PNAME(mux_hsicphy12m_p)= { hsicphy12m_xin12m, 
hsicphy12m_usbphy };
 
-- 
1.9.1

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Re: [PATCH 0/5] clk: rockchip: add full support for HDMI clock on rk3288

[Kever Yang]

Hi Heiko,

On 11/07/2014 05:06 AM, Heiko Stübner wrote:

Hi Kever,

Am Dienstag, 4. November 2014, 15:52:34 schrieb Kever Yang:

we are going to make a clock usage solution for rk3288:
1. CPLL and GPLL always not change after assign init;
2. NPLL default as 500MHz, may used for most scene;
3. NPLL may be changed by VOP(HDMI) clock for some special
frequency requirement.

 I test it with rk3288 evb on top of Heiko's clk-for-next

In general I'm not really sure if allowing one component to arbitarily change
a shared clock wouldn't result in trouble.

At the moment only dclk_vop0 is included in your series, while the hdmi
controller can connect to both vop0 and vop1.
And as Doug mentioned the gpu also has the npll as one possible source.

I think the problem GPU HANGs with 480MHz clock from usbphy has
been fixed with my patch to gerrit:
https://chromium-review.googlesource.com/#/c/229554/


Looking through the clock-tree there are a lot more components possibly using
(or wanting to use) the npll: of course the VOPs, the edp, hdmi, isp, hevc,
gpu, tsp uart0 and gmac. So I'm slightly uncomfortable with somehow reserving
the npll for VOP0 alone.

It's true that I customized the usage of npll for VOP0 when we need some
very special frequency, but it doesn't means other modules can't use the
npll, it will always decided by clock core for module clocks that which 
parent

is the best.

I'll be very happy if there is a better solution for this situation, and any
suggestion is welcome.

- Kever


But I also don't see a different way to get these frequencies right now.


Heiko





--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at  http://www.tux.org/lkml/

[RFC PATCH 0/2] add dts property to force update a clock setting

[Kever Yang]

When we assgined a clock rate in dts, we may need to update
the clock setting like PLLs who can get the same output rate with
different parameter even if we don't need to change the rate.


Kever Yang (2):
  clk: add property for force to update clock setting
  dt-bindings: clk: add document for assigned-clock-force-rates usage

 .../devicetree/bindings/clock/clock-bindings.txt   |  7 +++--
 drivers/clk/clk-conf.c | 33 +-
 2 files changed, 37 insertions(+), 3 deletions(-)

-- 
1.9.1

--
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Please read the FAQ at  http://www.tux.org/lkml/

[RFC PATCH 1/2] clk: add property for force to update clock setting

[Kever Yang]

Usually we assigned a clock to a default rate in dts,
there is a situation that the clock already initialized to the rate
we intend to set before kernel(hardware default or init in uboot etc).
For the PLLs we can get a rate from different PLL parameter configure,
we can't change the PLL parameter if the rate is not changed by now.

This patch adds a option property 'assigned-clock-force-rates'
to make sure we update all the setting even if we don't need to
update the clock rate.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 drivers/clk/clk-conf.c | 33 -
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
index aad4796..0c9df48 100644
--- a/drivers/clk/clk-conf.c
+++ b/drivers/clk/clk-conf.c
@@ -84,7 +84,7 @@ static int __set_clk_rates(struct device_node *node, bool 
clk_supplier)
struct clk *clk;
u32 rate;
 
-   of_property_for_each_u32(node, assigned-clock-rates, prop, cur, rate) 
{
+   of_property_for_each_u32(node, assigned-force-rates, prop, cur, rate) 
{
if (rate) {
rc = of_parse_phandle_with_args(node, assigned-clocks,
#clock-cells, index, clkspec);
@@ -104,7 +104,38 @@ static int __set_clk_rates(struct device_node *node, bool 
clk_supplier)
index, node-full_name);
return PTR_ERR(clk);
}
+   /* change the old rate to 0 to make sure we can get into
+* clk_change_rate */
+   clk-rate = 0;
+   rc = clk_set_rate(clk, rate);
+   if (rc  0)
+   pr_err(clk: couldn't set %s clock rate: %d\n,
+  __clk_get_name(clk), rc);
+   clk_put(clk);
+   }
+   index++;
+   }
 
+   of_property_for_each_u32(node, assigned-clock-rates, prop, cur, rate) 
{
+   if (rate) {
+   rc = of_parse_phandle_with_args(node, assigned-clocks,
+   #clock-cells, index, clkspec);
+   if (rc  0) {
+   /* skip empty (null) phandles */
+   if (rc == -ENOENT)
+   continue;
+   else
+   return rc;
+   }
+   if (clkspec.np == node  !clk_supplier)
+   return 0;
+
+   clk = of_clk_get_by_clkspec(clkspec);
+   if (IS_ERR(clk)) {
+   pr_warn(clk: couldn't get clock %d for %s\n,
+   index, node-full_name);
+   return PTR_ERR(clk);
+   }
rc = clk_set_rate(clk, rate);
if (rc  0)
pr_err(clk: couldn't set %s clock rate: %d\n,
-- 
1.9.1

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[RFC PATCH 2/2] dt-bindings: clk: add document for assigned-clock-force-rates usage

[Kever Yang]

This patch adds document for how to use the opetion property
assigned-clock-force-rates.

We may use this property to force update a clock setting.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 Documentation/devicetree/bindings/clock/clock-bindings.txt | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt 
b/Documentation/devicetree/bindings/clock/clock-bindings.txt
index 06fc6d5..fb5d3a5 100644
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -154,11 +154,14 @@ set to 0, or can be omitted if it is not followed by any 
non-zero entry.
 
 assigned-clocks = clkcon 0, pll 2;
 assigned-clock-parents = pll 2;
+assigned-clock-force-rates = 50, 0;
 assigned-clock-rates = 0, 460800;
 };
 
-In this example the pll 2 clock is set as parent of clock clkcon 0 and
-the pll 2 clock is assigned a frequency value of 460800 Hz.
+In this example the pll 2 clock is set as parent of clock clkcon 0,
+the clkcon 0 clock is assigned a frequency value of 50 Hz and make
+sure the we get into assigned-clock-rates even if there is no rate change,
+and the pll 2 clock is assigned a frequency value of 460800 Hz.
 
 Configuring a clock's parent and rate through the device node that consumes
 the clock can be done only for clocks that have a single user. Specifying
-- 
1.9.1

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[PATCH 2/2] clk: rockchip: use the clock ID for usbphy480m_src

[Kever Yang]

Use the clock ID for usbphy480m_src so that we can find
this clock node in dts.

Signed-off-by: Kever Yang 
---

 drivers/clk/rockchip/clk-rk3288.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 74f8324..157b60b 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -586,7 +586,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
GATE(0, "jtag", "ext_jtag", 0,
RK3288_CLKGATE_CON(4), 14, GFLAGS),
 
-   COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0,
+   COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", 
mux_usbphy480m_p, 0,
RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
RK3288_CLKGATE_CON(5), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", 
mux_hsicphy480m_p, 0,
-- 
1.9.1

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[PATCH 1/2] clk: rockchip: add clock ID for usbphy480m_src

[Kever Yang]

There are 3 different parent clock from different usbphy,
all of them are fixed 480MHz, it is not able to auto select
by clock core to the 2nd and the 3rd parent.
For different use case for different board, we may need to
select different usbphy clock out as parent manually.

Add the clock ID for it so that we can use in dts.

Signed-off-by: Kever Yang 
---

 include/dt-bindings/clock/rk3288-cru.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/rk3288-cru.h 
b/include/dt-bindings/clock/rk3288-cru.h
index 100a08c..3dcc906 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -71,6 +71,7 @@
 #define SCLK_HDMI_CEC  110
 #define SCLK_HEVC_CABAC111
 #define SCLK_HEVC_CORE 112
+#define SCLK_USBPHY480M_SRC113
 
 #define DCLK_VOP0  190
 #define DCLK_VOP1  191
-- 
1.9.1

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[PATCH] clk: rockchip: fix clk_usbphy480m_gate bit location in register

[Kever Yang]

According to rk3288 trm, the clk_usbphy480m_gate is locate at
bit 14 of CRU_CLKGATE5_CON register.

Signed-off-by: Kever Yang 
---

 drivers/clk/rockchip/clk-rk3288.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 1a9d03c..74f8324 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -588,7 +588,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
 
COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0,
RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
-   RK3288_CLKGATE_CON(5), 15, GFLAGS),
+   RK3288_CLKGATE_CON(5), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", 
mux_hsicphy480m_p, 0,
RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
RK3288_CLKGATE_CON(3), 6, GFLAGS),
-- 
1.9.1

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Re: [PATCH] clk: rockchip: ensure HCLK_VIO2_H2P and PCLK_VIO2_H2P stay enabled

[Kever Yang]

Hi Dmitry,

On 11/13/2014 05:38 AM, Dmitry Torokhov wrote:

Currently there is no driver owning these clocks and they have to stay
up for the system to function properly, so let's mark them as
CLK_IGNORE_UNUSED.

Without this patch we have trouble with suspend/resume and we have
trouble turning the eDP back on if it ever idles off.

Signed-off-by: Doug Anderson 
Signed-off-by: Dmitry Torokhov 
---
  drivers/clk/rockchip/clk-rk3288.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 2327829..d79d52f 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -724,14 +724,14 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, 
GFLAGS),
GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, 
GFLAGS),
GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, 
GFLAGS),
-   GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 0, 
RK3288_CLKGATE_CON(16), 10, GFLAGS),
+   GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(16), 10, GFLAGS),
GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, 
RK3288_CLKGATE_CON(16), 4, GFLAGS),
GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, 
RK3288_CLKGATE_CON(16), 5, GFLAGS),
GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, 
RK3288_CLKGATE_CON(16), 6, GFLAGS),
GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, 
RK3288_CLKGATE_CON(16), 7, GFLAGS),
GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, 
RK3288_CLKGATE_CON(16), 8, GFLAGS),
GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, 
RK3288_CLKGATE_CON(16), 9, GFLAGS),
-   GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 0, 
RK3288_CLKGATE_CON(16), 11, GFLAGS),
+   GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(16), 11, GFLAGS),
  
  	/* aclk_vio0 gates */

GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, 
GFLAGS),
The H/PCLK_VIO2_H2P is some kind of bus clock for a ahb2apb bridge 
inside the VIO,
it should be on when some of VIO logic is working, but it is not easy to 
assign these
two clocks to module driver. I think it is reasonable to mark with 
CLK_IGNORE_UNUSED

tag so far.

Reviewed-by: Kever Yang 

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Re: [PATCH v3] usb: dwc2: add bus suspend/resume for dwc2

[Kever Yang]

Doug,

On 11/13/2014 07:22 AM, Doug Anderson wrote:

Kever,

On Mon, Nov 10, 2014 at 5:09 AM, Kever Yang  wrote:

Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root hub enter suspend, we can make controller enter
low power state with PCGCTL register.

We also update the lx_state for hsotg state.

This patch has tested on rk3288 with suspend/resume.

Signed-off-by: Kever Yang 
Acked-by: Paul Zimmerman 
---

Changes in v3:
- remove CONFIG_PM macro for bus_suspend/resume
- add PCGCTL operation for no device connect case

Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode work

  drivers/usb/dwc2/hcd.c | 88 +++---
  1 file changed, 77 insertions(+), 11 deletions(-)

I would certainly appreciate confirmation, but my inclination is to
NAK this change due to the fact that it regresses functionality.  I
haven't done any serious review of it, but I've been testing it and it
appears to break hotplug.

Said another way, I did this:

1. Without this patch, I booted with a USB stick in.  It was detected.
I unplugged it, waited 5 seconds, and then plugged it back in.  The
USB stick was redetcted.

2. With this patch, I did the same thing.  The USB not redected after
plugging it back in.

With this patch, the dwc2 hcd/root hub will be auto suspend after device
on port is disconnected, and it can't detect the device connect any more,
I think that's the problem.

I will figure out how to make dwc2 detect the device connect after auto 
suspend,

or disable the auto suspend feature for the dwc2 hcd.

- Kever

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Re: [PATCH v3] usb: dwc2: add bus suspend/resume for dwc2

[Kever Yang]

Doug,

On 11/13/2014 07:22 AM, Doug Anderson wrote:

Kever,

On Mon, Nov 10, 2014 at 5:09 AM, Kever Yang kever.y...@rock-chips.com wrote:

Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root hub enter suspend, we can make controller enter
low power state with PCGCTL register.

We also update the lx_state for hsotg state.

This patch has tested on rk3288 with suspend/resume.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---

Changes in v3:
- remove CONFIG_PM macro for bus_suspend/resume
- add PCGCTL operation for no device connect case

Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode work

  drivers/usb/dwc2/hcd.c | 88 +++---
  1 file changed, 77 insertions(+), 11 deletions(-)

I would certainly appreciate confirmation, but my inclination is to
NAK this change due to the fact that it regresses functionality.  I
haven't done any serious review of it, but I've been testing it and it
appears to break hotplug.

Said another way, I did this:

1. Without this patch, I booted with a USB stick in.  It was detected.
I unplugged it, waited 5 seconds, and then plugged it back in.  The
USB stick was redetcted.

2. With this patch, I did the same thing.  The USB not redected after
plugging it back in.

With this patch, the dwc2 hcd/root hub will be auto suspend after device
on port is disconnected, and it can't detect the device connect any more,
I think that's the problem.

I will figure out how to make dwc2 detect the device connect after auto 
suspend,

or disable the auto suspend feature for the dwc2 hcd.

- Kever

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Re: [PATCH] clk: rockchip: ensure HCLK_VIO2_H2P and PCLK_VIO2_H2P stay enabled

[Kever Yang]

Hi Dmitry,

On 11/13/2014 05:38 AM, Dmitry Torokhov wrote:

Currently there is no driver owning these clocks and they have to stay
up for the system to function properly, so let's mark them as
CLK_IGNORE_UNUSED.

Without this patch we have trouble with suspend/resume and we have
trouble turning the eDP back on if it ever idles off.

Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Dmitry Torokhov d...@chromium.org
---
  drivers/clk/rockchip/clk-rk3288.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 2327829..d79d52f 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -724,14 +724,14 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
GATE(HCLK_VIP, hclk_vip, hclk_vio, 0, RK3288_CLKGATE_CON(15), 15, 
GFLAGS),
GATE(HCLK_IEP, hclk_iep, hclk_vio, 0, RK3288_CLKGATE_CON(15), 3, 
GFLAGS),
GATE(HCLK_ISP, hclk_isp, hclk_vio, 0, RK3288_CLKGATE_CON(16), 1, 
GFLAGS),
-   GATE(HCLK_VIO2_H2P, hclk_vio2_h2p, hclk_vio, 0, 
RK3288_CLKGATE_CON(16), 10, GFLAGS),
+   GATE(HCLK_VIO2_H2P, hclk_vio2_h2p, hclk_vio, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(16), 10, GFLAGS),
GATE(PCLK_MIPI_DSI0, pclk_mipi_dsi0, hclk_vio, 0, 
RK3288_CLKGATE_CON(16), 4, GFLAGS),
GATE(PCLK_MIPI_DSI1, pclk_mipi_dsi1, hclk_vio, 0, 
RK3288_CLKGATE_CON(16), 5, GFLAGS),
GATE(PCLK_MIPI_CSI, pclk_mipi_csi, hclk_vio, 0, 
RK3288_CLKGATE_CON(16), 6, GFLAGS),
GATE(PCLK_LVDS_PHY, pclk_lvds_phy, hclk_vio, 0, 
RK3288_CLKGATE_CON(16), 7, GFLAGS),
GATE(PCLK_EDP_CTRL, pclk_edp_ctrl, hclk_vio, 0, 
RK3288_CLKGATE_CON(16), 8, GFLAGS),
GATE(PCLK_HDMI_CTRL, pclk_hdmi_ctrl, hclk_vio, 0, 
RK3288_CLKGATE_CON(16), 9, GFLAGS),
-   GATE(PCLK_VIO2_H2P, pclk_vio2_h2p, hclk_vio, 0, 
RK3288_CLKGATE_CON(16), 11, GFLAGS),
+   GATE(PCLK_VIO2_H2P, pclk_vio2_h2p, hclk_vio, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(16), 11, GFLAGS),
  
  	/* aclk_vio0 gates */

GATE(ACLK_VOP0, aclk_vop0, aclk_vio0, 0, RK3288_CLKGATE_CON(15), 5, 
GFLAGS),
The H/PCLK_VIO2_H2P is some kind of bus clock for a ahb2apb bridge 
inside the VIO,
it should be on when some of VIO logic is working, but it is not easy to 
assign these
two clocks to module driver. I think it is reasonable to mark with 
CLK_IGNORE_UNUSED

tag so far.

Reviewed-by: Kever Yang kever.y...@rock-chips.com

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[PATCH] clk: rockchip: fix clk_usbphy480m_gate bit location in register

[Kever Yang]

According to rk3288 trm, the clk_usbphy480m_gate is locate at
bit 14 of CRU_CLKGATE5_CON register.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 drivers/clk/rockchip/clk-rk3288.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 1a9d03c..74f8324 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -588,7 +588,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
 
COMPOSITE_NODIV(0, usbphy480m_src, mux_usbphy480m_p, 0,
RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
-   RK3288_CLKGATE_CON(5), 15, GFLAGS),
+   RK3288_CLKGATE_CON(5), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_HSICPHY480M, sclk_hsicphy480m, 
mux_hsicphy480m_p, 0,
RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
RK3288_CLKGATE_CON(3), 6, GFLAGS),
-- 
1.9.1

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[PATCH 1/2] clk: rockchip: add clock ID for usbphy480m_src

[Kever Yang]

There are 3 different parent clock from different usbphy,
all of them are fixed 480MHz, it is not able to auto select
by clock core to the 2nd and the 3rd parent.
For different use case for different board, we may need to
select different usbphy clock out as parent manually.

Add the clock ID for it so that we can use in dts.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 include/dt-bindings/clock/rk3288-cru.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/rk3288-cru.h 
b/include/dt-bindings/clock/rk3288-cru.h
index 100a08c..3dcc906 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -71,6 +71,7 @@
 #define SCLK_HDMI_CEC  110
 #define SCLK_HEVC_CABAC111
 #define SCLK_HEVC_CORE 112
+#define SCLK_USBPHY480M_SRC113
 
 #define DCLK_VOP0  190
 #define DCLK_VOP1  191
-- 
1.9.1

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[PATCH 2/2] clk: rockchip: use the clock ID for usbphy480m_src

[Kever Yang]

Use the clock ID for usbphy480m_src so that we can find
this clock node in dts.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 drivers/clk/rockchip/clk-rk3288.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 74f8324..157b60b 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -586,7 +586,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
GATE(0, jtag, ext_jtag, 0,
RK3288_CLKGATE_CON(4), 14, GFLAGS),
 
-   COMPOSITE_NODIV(0, usbphy480m_src, mux_usbphy480m_p, 0,
+   COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, usbphy480m_src, 
mux_usbphy480m_p, 0,
RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
RK3288_CLKGATE_CON(5), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_HSICPHY480M, sclk_hsicphy480m, 
mux_hsicphy480m_p, 0,
-- 
1.9.1

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[PATCH v3] usb: dwc2: add bus suspend/resume for dwc2

[Kever Yang]

Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root hub enter suspend, we can make controller enter
low power state with PCGCTL register.

We also update the lx_state for hsotg state.

This patch has tested on rk3288 with suspend/resume.

Signed-off-by: Kever Yang 
Acked-by: Paul Zimmerman 
---

Changes in v3:
- remove CONFIG_PM macro for bus_suspend/resume
- add PCGCTL operation for no device connect case

Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode work

 drivers/usb/dwc2/hcd.c | 88 +++---
 1 file changed, 77 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 0a0e6f0..7480078 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -1471,6 +1471,30 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, 
u16 windex)
}
 }
 
+static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
+{
+   u32 hprt0;
+
+   /* After clear the Stop PHY clock bit, we should wait for a moment
+* for PLL work stable with clock output.
+*/
+   writel(0, hsotg->regs + PCGCTL);
+   usleep_range(2000, 4000);
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   hprt0 |= HPRT0_RES;
+   writel(hprt0, hsotg->regs + HPRT0);
+   hprt0 &= ~HPRT0_SUSP;
+   /* according to USB2.0 Spec 7.1.7.7, the host must send the resume
+* signal for at least 20ms
+*/
+   usleep_range(2, 25000);
+
+   hprt0 &= ~HPRT0_RES;
+   writel(hprt0, hsotg->regs + HPRT0);
+   hsotg->lx_state = DWC2_L0;
+}
+
 /* Handles hub class-specific requests */
 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
u16 wvalue, u16 windex, char *buf, u16 wlength)
@@ -1516,17 +1540,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg 
*hsotg, u16 typereq,
case USB_PORT_FEAT_SUSPEND:
dev_dbg(hsotg->dev,
"ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
-   writel(0, hsotg->regs + PCGCTL);
-   usleep_range(2, 4);
-
-   hprt0 = dwc2_read_hprt0(hsotg);
-   hprt0 |= HPRT0_RES;
-   writel(hprt0, hsotg->regs + HPRT0);
-   hprt0 &= ~HPRT0_SUSP;
-   usleep_range(10, 15);
-
-   hprt0 &= ~HPRT0_RES;
-   writel(hprt0, hsotg->regs + HPRT0);
+   dwc2_port_resume(hsotg);
break;
 
case USB_PORT_FEAT_POWER:
@@ -2299,6 +2313,55 @@ static void _dwc2_hcd_stop(struct usb_hcd *hcd)
usleep_range(1000, 3000);
 }
 
+static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (!((hsotg->op_state == OTG_STATE_B_HOST) ||
+   (hsotg->op_state == OTG_STATE_A_HOST)))
+   return 0;
+
+   /* TODO: We get into suspend from 'on' state, maybe we need to do
+* something if we get here from DWC2_L1(LPM sleep) state one day.
+*/
+   if (hsotg->lx_state != DWC2_L0)
+   return 0;
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   if (hprt0 & HPRT0_CONNSTS) {
+   dwc2_port_suspend(hsotg, 1);
+   } else {
+   u32 pcgctl = readl(hsotg->regs + PCGCTL);
+
+   pcgctl |= PCGCTL_STOPPCLK;
+   writel(pcgctl, hsotg->regs + PCGCTL);
+   }
+
+   return 0;
+}
+
+static int _dwc2_hcd_resume(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (!((hsotg->op_state == OTG_STATE_B_HOST) ||
+   (hsotg->op_state == OTG_STATE_A_HOST)))
+   return 0;
+
+   if (hsotg->lx_state != DWC2_L2)
+   return 0;
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   if ((hprt0 & HPRT0_CONNSTS) && (hprt0 & HPRT0_SUSP))
+   dwc2_port_resume(hsotg);
+   else
+   writel(0, hsotg->regs + PCGCTL);
+
+   return 0;
+}
+
 /* Returns the current frame number */
 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
 {
@@ -2669,6 +2732,9 @@ static struct hc_driver dwc2_hc_driver = {
.hub_status_data = _dwc2_hcd_hub_status_data,
.hub_control = _dwc2_hcd_hub_control,
.clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
+
+   .bus_suspend = _dwc2_hcd_suspend,
+   .bus_resume = _dwc2_hcd_resume,
 };
 
 /*
-- 
1.9.1

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Re: [PATCH v2] usb: dwc2: add bus suspend/resume for dwc2

[Kever Yang]

Hi Julius,

On 11/07/2014 06:11 AM, Julius Werner wrote:

On Wed, Nov 5, 2014 at 5:30 PM, Kever Yang  wrote:

Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root hub enter suspend, we can make controller enter
low power state with PCGCTL register.

You say you do this, but I don't actually see you doing it (for the
not-connected case)?

Agree to add PCGCTL operation for the not-connected case.



We also update the lx_state for hsotg state.

This patch has tested on rk3288 with suspend/resume.

Signed-off-by: Kever Yang 
---

Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode work

  drivers/usb/dwc2/hcd.c | 78 +++---
  1 file changed, 67 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 0a0e6f0..01a415b 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -1471,6 +1471,30 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, 
u16 windex)
 }
  }

+static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
+{
+   u32 hprt0;
+
+   /* After clear the Stop PHY clock bit, we should wait for a moment
+* for PLL work stable with clock output.
+*/
+   writel(0, hsotg->regs + PCGCTL);
+   usleep_range(2000, 4000);
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   hprt0 |= HPRT0_RES;
+   writel(hprt0, hsotg->regs + HPRT0);
+   hprt0 &= ~HPRT0_SUSP;
+   /* according to USB2.0 Spec 7.1.7.7, the host must send the resume
+* signal for at least 20ms
+*/
+   usleep_range(2, 25000);
+
+   hprt0 &= ~HPRT0_RES;
+   writel(hprt0, hsotg->regs + HPRT0);
+   hsotg->lx_state = DWC2_L0;
+}
+
  /* Handles hub class-specific requests */
  static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
 u16 wvalue, u16 windex, char *buf, u16 wlength)
@@ -1516,17 +1540,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg 
*hsotg, u16 typereq,
 case USB_PORT_FEAT_SUSPEND:
 dev_dbg(hsotg->dev,
 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
-   writel(0, hsotg->regs + PCGCTL);
-   usleep_range(2, 4);
-
-   hprt0 = dwc2_read_hprt0(hsotg);
-   hprt0 |= HPRT0_RES;
-   writel(hprt0, hsotg->regs + HPRT0);
-   hprt0 &= ~HPRT0_SUSP;
-   usleep_range(10, 15);
-
-   hprt0 &= ~HPRT0_RES;
-   writel(hprt0, hsotg->regs + HPRT0);

I'm curious why this didn't change lx_state back to DWC2_L0 before...
Paul, do you know?


+   dwc2_port_resume(hsotg);
 break;

 case USB_PORT_FEAT_POWER:
@@ -2299,6 +2313,44 @@ static void _dwc2_hcd_stop(struct usb_hcd *hcd)
 usleep_range(1000, 3000);
  }

+static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (!((hsotg->op_state == OTG_STATE_B_HOST) ||
+   (hsotg->op_state == OTG_STATE_A_HOST)))
+   return 0;
+
+   if (hsotg->lx_state != DWC2_L0)

What if the port is in L1 state? I don't think the driver supports LPM
right now, but the DWC2_L1 enum is defined so it may one day in the
future. Let's maybe at least add a TODO.

Added



+   return 0;

In your original ChromiumOS version of this patch, you also set
PCGCTL_STOPPCLK here if the port was not connected. Is there a reason
that changed (does it not actually save power or something)?


+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   if (hprt0 & HPRT0_CONNSTS)
+   dwc2_port_suspend(hsotg, 1);

The contract for bus_suspend() is that it will suspend all ports not
yet suspended, keep track of those ports and then only resume those in
bus_resume() (compare, for example, how XHCI keeps track of that with
xhci_bus_state.bus_suspended in xhci_bus_suspend/resume()). So you
need something here to remember whether this function suspended the
port or whether it had already been suspended, and then only resume
the port in bus_resume() in the former case.

In fact, the dwc2 controller only support one port, so the hprt0
is the only one port we need to care.

Note that
dwc2_port_suspend() changes lx_state to DWC_L2 (at least in the
version I'm looking at right now), so you can't just rely on that
unless you explicitly set it back to something else here.


+
+   return 0;
+}
+
+static int _dwc2_hcd_resume(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (!((hsotg->op_state == OTG_STATE_B_HOST) ||
+   

Re: [PATCH v2] usb: dwc2: add bus suspend/resume for dwc2

[Kever Yang]

Hi Julius,

On 11/07/2014 06:11 AM, Julius Werner wrote:

On Wed, Nov 5, 2014 at 5:30 PM, Kever Yang kever.y...@rock-chips.com wrote:

Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root hub enter suspend, we can make controller enter
low power state with PCGCTL register.

You say you do this, but I don't actually see you doing it (for the
not-connected case)?

Agree to add PCGCTL operation for the not-connected case.



We also update the lx_state for hsotg state.

This patch has tested on rk3288 with suspend/resume.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode work

  drivers/usb/dwc2/hcd.c | 78 +++---
  1 file changed, 67 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 0a0e6f0..01a415b 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -1471,6 +1471,30 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, 
u16 windex)
 }
  }

+static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
+{
+   u32 hprt0;
+
+   /* After clear the Stop PHY clock bit, we should wait for a moment
+* for PLL work stable with clock output.
+*/
+   writel(0, hsotg-regs + PCGCTL);
+   usleep_range(2000, 4000);
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   hprt0 |= HPRT0_RES;
+   writel(hprt0, hsotg-regs + HPRT0);
+   hprt0 = ~HPRT0_SUSP;
+   /* according to USB2.0 Spec 7.1.7.7, the host must send the resume
+* signal for at least 20ms
+*/
+   usleep_range(2, 25000);
+
+   hprt0 = ~HPRT0_RES;
+   writel(hprt0, hsotg-regs + HPRT0);
+   hsotg-lx_state = DWC2_L0;
+}
+
  /* Handles hub class-specific requests */
  static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
 u16 wvalue, u16 windex, char *buf, u16 wlength)
@@ -1516,17 +1540,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg 
*hsotg, u16 typereq,
 case USB_PORT_FEAT_SUSPEND:
 dev_dbg(hsotg-dev,
 ClearPortFeature USB_PORT_FEAT_SUSPEND\n);
-   writel(0, hsotg-regs + PCGCTL);
-   usleep_range(2, 4);
-
-   hprt0 = dwc2_read_hprt0(hsotg);
-   hprt0 |= HPRT0_RES;
-   writel(hprt0, hsotg-regs + HPRT0);
-   hprt0 = ~HPRT0_SUSP;
-   usleep_range(10, 15);
-
-   hprt0 = ~HPRT0_RES;
-   writel(hprt0, hsotg-regs + HPRT0);

I'm curious why this didn't change lx_state back to DWC2_L0 before...
Paul, do you know?


+   dwc2_port_resume(hsotg);
 break;

 case USB_PORT_FEAT_POWER:
@@ -2299,6 +2313,44 @@ static void _dwc2_hcd_stop(struct usb_hcd *hcd)
 usleep_range(1000, 3000);
  }

+static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (!((hsotg-op_state == OTG_STATE_B_HOST) ||
+   (hsotg-op_state == OTG_STATE_A_HOST)))
+   return 0;
+
+   if (hsotg-lx_state != DWC2_L0)

What if the port is in L1 state? I don't think the driver supports LPM
right now, but the DWC2_L1 enum is defined so it may one day in the
future. Let's maybe at least add a TODO.

Added



+   return 0;

In your original ChromiumOS version of this patch, you also set
PCGCTL_STOPPCLK here if the port was not connected. Is there a reason
that changed (does it not actually save power or something)?


+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   if (hprt0  HPRT0_CONNSTS)
+   dwc2_port_suspend(hsotg, 1);

The contract for bus_suspend() is that it will suspend all ports not
yet suspended, keep track of those ports and then only resume those in
bus_resume() (compare, for example, how XHCI keeps track of that with
xhci_bus_state.bus_suspended in xhci_bus_suspend/resume()). So you
need something here to remember whether this function suspended the
port or whether it had already been suspended, and then only resume
the port in bus_resume() in the former case.

In fact, the dwc2 controller only support one port, so the hprt0
is the only one port we need to care.

Note that
dwc2_port_suspend() changes lx_state to DWC_L2 (at least in the
version I'm looking at right now), so you can't just rely on that
unless you explicitly set it back to something else here.


+
+   return 0;
+}
+
+static int _dwc2_hcd_resume(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (!((hsotg-op_state == OTG_STATE_B_HOST) ||
+   (hsotg-op_state

[PATCH v3] usb: dwc2: add bus suspend/resume for dwc2

[Kever Yang]

Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root hub enter suspend, we can make controller enter
low power state with PCGCTL register.

We also update the lx_state for hsotg state.

This patch has tested on rk3288 with suspend/resume.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
Acked-by: Paul Zimmerman pa...@synopsys.com
---

Changes in v3:
- remove CONFIG_PM macro for bus_suspend/resume
- add PCGCTL operation for no device connect case

Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode work

 drivers/usb/dwc2/hcd.c | 88 +++---
 1 file changed, 77 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 0a0e6f0..7480078 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -1471,6 +1471,30 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, 
u16 windex)
}
 }
 
+static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
+{
+   u32 hprt0;
+
+   /* After clear the Stop PHY clock bit, we should wait for a moment
+* for PLL work stable with clock output.
+*/
+   writel(0, hsotg-regs + PCGCTL);
+   usleep_range(2000, 4000);
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   hprt0 |= HPRT0_RES;
+   writel(hprt0, hsotg-regs + HPRT0);
+   hprt0 = ~HPRT0_SUSP;
+   /* according to USB2.0 Spec 7.1.7.7, the host must send the resume
+* signal for at least 20ms
+*/
+   usleep_range(2, 25000);
+
+   hprt0 = ~HPRT0_RES;
+   writel(hprt0, hsotg-regs + HPRT0);
+   hsotg-lx_state = DWC2_L0;
+}
+
 /* Handles hub class-specific requests */
 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
u16 wvalue, u16 windex, char *buf, u16 wlength)
@@ -1516,17 +1540,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg 
*hsotg, u16 typereq,
case USB_PORT_FEAT_SUSPEND:
dev_dbg(hsotg-dev,
ClearPortFeature USB_PORT_FEAT_SUSPEND\n);
-   writel(0, hsotg-regs + PCGCTL);
-   usleep_range(2, 4);
-
-   hprt0 = dwc2_read_hprt0(hsotg);
-   hprt0 |= HPRT0_RES;
-   writel(hprt0, hsotg-regs + HPRT0);
-   hprt0 = ~HPRT0_SUSP;
-   usleep_range(10, 15);
-
-   hprt0 = ~HPRT0_RES;
-   writel(hprt0, hsotg-regs + HPRT0);
+   dwc2_port_resume(hsotg);
break;
 
case USB_PORT_FEAT_POWER:
@@ -2299,6 +2313,55 @@ static void _dwc2_hcd_stop(struct usb_hcd *hcd)
usleep_range(1000, 3000);
 }
 
+static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (!((hsotg-op_state == OTG_STATE_B_HOST) ||
+   (hsotg-op_state == OTG_STATE_A_HOST)))
+   return 0;
+
+   /* TODO: We get into suspend from 'on' state, maybe we need to do
+* something if we get here from DWC2_L1(LPM sleep) state one day.
+*/
+   if (hsotg-lx_state != DWC2_L0)
+   return 0;
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   if (hprt0  HPRT0_CONNSTS) {
+   dwc2_port_suspend(hsotg, 1);
+   } else {
+   u32 pcgctl = readl(hsotg-regs + PCGCTL);
+
+   pcgctl |= PCGCTL_STOPPCLK;
+   writel(pcgctl, hsotg-regs + PCGCTL);
+   }
+
+   return 0;
+}
+
+static int _dwc2_hcd_resume(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (!((hsotg-op_state == OTG_STATE_B_HOST) ||
+   (hsotg-op_state == OTG_STATE_A_HOST)))
+   return 0;
+
+   if (hsotg-lx_state != DWC2_L2)
+   return 0;
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   if ((hprt0  HPRT0_CONNSTS)  (hprt0  HPRT0_SUSP))
+   dwc2_port_resume(hsotg);
+   else
+   writel(0, hsotg-regs + PCGCTL);
+
+   return 0;
+}
+
 /* Returns the current frame number */
 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
 {
@@ -2669,6 +2732,9 @@ static struct hc_driver dwc2_hc_driver = {
.hub_status_data = _dwc2_hcd_hub_status_data,
.hub_control = _dwc2_hcd_hub_control,
.clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
+
+   .bus_suspend = _dwc2_hcd_suspend,
+   .bus_resume = _dwc2_hcd_resume,
 };
 
 /*
-- 
1.9.1

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Re: [PATCH v8 1/3] power-domain: rockchip: add power domain drivers

[Kever Yang]

On 11/06/2014 02:22 PM, Caesar Wang wrote:

In order to meet high performance and low power requirements, a power
management unit is designed or saving power when RK3288 in low power mode.
The RK3288 PMU is dedicated for managing the power ot the whole chip.

Signed-off-by: Jack Dai
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang

---

Changes in v8:
 - This reconciles the v2 and v7 code so that we power domain have
 lists of clocks they toggle on and off during power transitions and
 independently from power domains clocks we attach clocks to devices
 comprising power domain and prepare them so they are turned on and off
 by runtime PM.

There are more changes like the new rockchip_pm_add_one_domain.


Changes in v7:
 - Delete unused variables



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Re: [PATCH v8 3/3] ARM: dts: add rk3288 power-domain node

[Kever Yang]

Hi Caesar,

On 11/06/2014 02:22 PM, Caesar Wang wrote:

Signed-off-by: Jack Dai 
Signed-off-by: jinkun.hong 
Signed-off-by: Caesar Wang 
pls detail the reason why you need to add all the clocks into 
power-controller node.

---

Changes in v8:
 - DTS go back to v2

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
 - Decomposition power-controller, changed to multiple controller
 (gpu-power-controller, hevc-power-controller)

Changes in v2:
 - make pd_vio clocks all one entry per line and alphabetize.
 - power: power-controller move back to pinctrl: pinctrl.

  arch/arm/boot/dts/rk3288.dtsi | 66 +++
  1 file changed, 66 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index cb18bb4..9cd269a 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -989,4 +989,70 @@
};
};
};
+
+   power: power-controller {
+   compatible = "rockchip,rk3288-power-controller";
+   #power-domain-cells = <1>;
+   rockchip,pmu = <>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   pd_gpu {
+   reg = ;
+   clocks = < ACLK_GPU>;
+   };
+
+   pd_hevc {
+   reg = ;
+   clocks = < ACLK_HEVC>,
+< SCLK_HEVC_CABAC>,
+< SCLK_HEVC_CORE>,
+< HCLK_HEVC>;
+   };
+
+   pd_vio {
+   reg = ;
+   clocks = < ACLK_IEP>,
+< ACLK_ISP>,
+< ACLK_RGA_NIU>,
+< ACLK_RGA>,
+< ACLK_VIO0_NIU>,
+< ACLK_VIO1_NIU>,
+< ACLK_VIP>,
+< ACLK_VOP0>,
+< ACLK_VOP1>,
+< DCLK_VOP0>,
+< DCLK_VOP1>,
+< HCLK_IEP>,
+< HCLK_ISP>,
+< HCLK_RGA>,
+< HCLK_VIO_AHB_ARBI>,
+< HCLK_VIO_NIU>,
+< HCLK_VIO2_H2P>,
+< HCLK_VIP>,
+< HCLK_VOP0>,
+< HCLK_VOP1>,
+< PCLK_EDP_CTRL>,
+< PCLK_HDMI_CTRL>,
+< PCLK_LVDS_PHY>,
+< PCLK_MIPI_CSI>,
+< PCLK_MIPI_DSI0>,
+< PCLK_MIPI_DSI1>,
+< PCLK_VIO2_H2P>,
+< SCLK_EDP_24M>,
+< SCLK_EDP>,
+< SCLK_HDMI_CEC>,
+< SCLK_HDMI_HDCP>,
+< SCLK_ISP_JPE>,
+< SCLK_ISP>,
+< SCLK_RGA>;
+   };
+
+   pd_video {
+   reg = ;
+   /* FIXME: add clocks */

remove the 'FIXME'.

+   clocks = < ACLK_VCODEC>,
+< HCLK_VCODEC>;
+   };
+   };
  };


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Re: [PATCH v8 3/3] ARM: dts: add rk3288 power-domain node

[Kever Yang]

Hi Caesar,

On 11/06/2014 02:22 PM, Caesar Wang wrote:

Signed-off-by: Jack Dai jack@rock-chips.com
Signed-off-by: jinkun.hong jinkun.h...@rock-chips.com
Signed-off-by: Caesar Wang caesar.w...@rock-chips.com
pls detail the reason why you need to add all the clocks into 
power-controller node.

---

Changes in v8:
 - DTS go back to v2

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
 - Decomposition power-controller, changed to multiple controller
 (gpu-power-controller, hevc-power-controller)

Changes in v2:
 - make pd_vio clocks all one entry per line and alphabetize.
 - power: power-controller move back to pinctrl: pinctrl.

  arch/arm/boot/dts/rk3288.dtsi | 66 +++
  1 file changed, 66 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index cb18bb4..9cd269a 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -989,4 +989,70 @@
};
};
};
+
+   power: power-controller {
+   compatible = rockchip,rk3288-power-controller;
+   #power-domain-cells = 1;
+   rockchip,pmu = pmu;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   pd_gpu {
+   reg = RK3288_PD_GPU;
+   clocks = cru ACLK_GPU;
+   };
+
+   pd_hevc {
+   reg = RK3288_PD_HEVC;
+   clocks = cru ACLK_HEVC,
+cru SCLK_HEVC_CABAC,
+cru SCLK_HEVC_CORE,
+cru HCLK_HEVC;
+   };
+
+   pd_vio {
+   reg = RK3288_PD_VIO;
+   clocks = cru ACLK_IEP,
+cru ACLK_ISP,
+cru ACLK_RGA_NIU,
+cru ACLK_RGA,
+cru ACLK_VIO0_NIU,
+cru ACLK_VIO1_NIU,
+cru ACLK_VIP,
+cru ACLK_VOP0,
+cru ACLK_VOP1,
+cru DCLK_VOP0,
+cru DCLK_VOP1,
+cru HCLK_IEP,
+cru HCLK_ISP,
+cru HCLK_RGA,
+cru HCLK_VIO_AHB_ARBI,
+cru HCLK_VIO_NIU,
+cru HCLK_VIO2_H2P,
+cru HCLK_VIP,
+cru HCLK_VOP0,
+cru HCLK_VOP1,
+cru PCLK_EDP_CTRL,
+cru PCLK_HDMI_CTRL,
+cru PCLK_LVDS_PHY,
+cru PCLK_MIPI_CSI,
+cru PCLK_MIPI_DSI0,
+cru PCLK_MIPI_DSI1,
+cru PCLK_VIO2_H2P,
+cru SCLK_EDP_24M,
+cru SCLK_EDP,
+cru SCLK_HDMI_CEC,
+cru SCLK_HDMI_HDCP,
+cru SCLK_ISP_JPE,
+cru SCLK_ISP,
+cru SCLK_RGA;
+   };
+
+   pd_video {
+   reg = RK3288_PD_VIDEO;
+   /* FIXME: add clocks */

remove the 'FIXME'.

+   clocks = cru ACLK_VCODEC,
+cru HCLK_VCODEC;
+   };
+   };
  };


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Re: [PATCH v8 1/3] power-domain: rockchip: add power domain drivers

[Kever Yang]

On 11/06/2014 02:22 PM, Caesar Wang wrote:

In order to meet high performance and low power requirements, a power
management unit is designed or saving power when RK3288 in low power mode.
The RK3288 PMU is dedicated for managing the power ot the whole chip.

Signed-off-by: Jack Daijack@rock-chips.com
Signed-off-by: jinkun.hongjinkun.h...@rock-chips.com
Signed-off-by: Caesar Wangcaesar.w...@rock-chips.com

---

Changes in v8:
 - This reconciles the v2 and v7 code so that we power domain have
 lists of clocks they toggle on and off during power transitions and
 independently from power domains clocks we attach clocks to devices
 comprising power domain and prepare them so they are turned on and off
 by runtime PM.

There are more changes like the new rockchip_pm_add_one_domain.


Changes in v7:
 - Delete unused variables



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[PATCH v2] usb: dwc2: add bus suspend/resume for dwc2

[Kever Yang]

Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root hub enter suspend, we can make controller enter
low power state with PCGCTL register.

We also update the lx_state for hsotg state.

This patch has tested on rk3288 with suspend/resume.

Signed-off-by: Kever Yang 
---

Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode work

 drivers/usb/dwc2/hcd.c | 78 +++---
 1 file changed, 67 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 0a0e6f0..01a415b 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -1471,6 +1471,30 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, 
u16 windex)
}
 }
 
+static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
+{
+   u32 hprt0;
+
+   /* After clear the Stop PHY clock bit, we should wait for a moment
+* for PLL work stable with clock output.
+*/
+   writel(0, hsotg->regs + PCGCTL);
+   usleep_range(2000, 4000);
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   hprt0 |= HPRT0_RES;
+   writel(hprt0, hsotg->regs + HPRT0);
+   hprt0 &= ~HPRT0_SUSP;
+   /* according to USB2.0 Spec 7.1.7.7, the host must send the resume
+* signal for at least 20ms
+*/
+   usleep_range(2, 25000);
+
+   hprt0 &= ~HPRT0_RES;
+   writel(hprt0, hsotg->regs + HPRT0);
+   hsotg->lx_state = DWC2_L0;
+}
+
 /* Handles hub class-specific requests */
 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
u16 wvalue, u16 windex, char *buf, u16 wlength)
@@ -1516,17 +1540,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg 
*hsotg, u16 typereq,
case USB_PORT_FEAT_SUSPEND:
dev_dbg(hsotg->dev,
"ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
-   writel(0, hsotg->regs + PCGCTL);
-   usleep_range(2, 4);
-
-   hprt0 = dwc2_read_hprt0(hsotg);
-   hprt0 |= HPRT0_RES;
-   writel(hprt0, hsotg->regs + HPRT0);
-   hprt0 &= ~HPRT0_SUSP;
-   usleep_range(10, 15);
-
-   hprt0 &= ~HPRT0_RES;
-   writel(hprt0, hsotg->regs + HPRT0);
+   dwc2_port_resume(hsotg);
break;
 
case USB_PORT_FEAT_POWER:
@@ -2299,6 +2313,44 @@ static void _dwc2_hcd_stop(struct usb_hcd *hcd)
usleep_range(1000, 3000);
 }
 
+static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (!((hsotg->op_state == OTG_STATE_B_HOST) ||
+   (hsotg->op_state == OTG_STATE_A_HOST)))
+   return 0;
+
+   if (hsotg->lx_state != DWC2_L0)
+   return 0;
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   if (hprt0 & HPRT0_CONNSTS)
+   dwc2_port_suspend(hsotg, 1);
+
+   return 0;
+}
+
+static int _dwc2_hcd_resume(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (!((hsotg->op_state == OTG_STATE_B_HOST) ||
+   (hsotg->op_state == OTG_STATE_A_HOST)))
+   return 0;
+
+   if (hsotg->lx_state != DWC2_L2)
+   return 0;
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   if ((hprt0 & HPRT0_CONNSTS) && (hprt0 & HPRT0_SUSP))
+   dwc2_port_resume(hsotg);
+
+   return 0;
+}
+
 /* Returns the current frame number */
 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
 {
@@ -2669,6 +2721,10 @@ static struct hc_driver dwc2_hc_driver = {
.hub_status_data = _dwc2_hcd_hub_status_data,
.hub_control = _dwc2_hcd_hub_control,
.clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
+#ifdef CONFIG_PM
+   .bus_suspend = _dwc2_hcd_suspend,
+   .bus_resume = _dwc2_hcd_resume,
+#endif
 };
 
 /*
-- 
1.9.1

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[PATCH v2] clk: rockchip: change hierarchy for some clocks

[Kever Yang]

There are some bus clock for multiple controllers with the same
function in rk3288: four usb controllers on hclk_usb_peri,
two nandc on hclk_emem and four dw_emmc controller on hclk_mem.
These bus clock has the same parent with the controllers,
they should be enabled if at least one of controllers
on that bus is enabled, and should be disabled if all the
controllers are disabled.

There is no existern way to describ this kind of dependency,
so maybe we can make the bus clock as a pseudo parent.

This patch change the hierarchy for these bus clocks, to met
the following bus hierarchy:
hclk_usb_peri is bus clock for
|- hclk_otg0,
|- hclk_host0,
|- hclk_host1,
|- hclk_hsic

hclk_emem is bus clock for
|- hclk_nandc0
|- hclk_nandc1

hclk_mem is bus clock for
|- hclk_sdmmc
|- hclk_sdio0
|- hclk_sdio1
|- hclk_emmc

Signed-off-by: Kever Yang 
---

Changes in v2:
- update the commit message

 drivers/clk/rockchip/clk-rk3288.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index baf8a89..d31bc45 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -652,21 +652,21 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
 
/* hclk_peri gates */
GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(6), 0, GFLAGS),
-   GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 4, GFLAGS),
-   GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, 
RK3288_CLKGATE_CON(7), 6, GFLAGS),
-   GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 7, GFLAGS),
-   GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, 
GFLAGS),
+   GATE(HCLK_OTG0, "hclk_otg0", "hclk_usb_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 4, GFLAGS),
+   GATE(HCLK_USBHOST0, "hclk_host0", "hclk_usb_peri", 0, 
RK3288_CLKGATE_CON(7), 6, GFLAGS),
+   GATE(HCLK_USBHOST1, "hclk_host1", "hclk_usb_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 7, GFLAGS),
+   GATE(HCLK_HSIC, "hclk_hsic", "hclk_usb_peri", 0, RK3288_CLKGATE_CON(7), 
8, GFLAGS),
GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 9, GFLAGS),
GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 10, GFLAGS),
GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 12, GFLAGS),
GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 13, GFLAGS),
-   GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 
14, GFLAGS),
-   GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 
15, GFLAGS),
+   GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_emem", 0, RK3288_CLKGATE_CON(7), 
14, GFLAGS),
+   GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_emem", 0, RK3288_CLKGATE_CON(7), 
15, GFLAGS),
GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, 
GFLAGS),
-   GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 
3, GFLAGS),
-   GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 
4, GFLAGS),
-   GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 
5, GFLAGS),
-   GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, 
GFLAGS),
+   GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_mem", 0, RK3288_CLKGATE_CON(8), 3, 
GFLAGS),
+   GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_mem", 0, RK3288_CLKGATE_CON(8), 4, 
GFLAGS),
+   GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_mem", 0, RK3288_CLKGATE_CON(8), 5, 
GFLAGS),
+   GATE(HCLK_EMMC, "hclk_emmc", "hclk_mem", 0, RK3288_CLKGATE_CON(8), 6, 
GFLAGS),
GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 
7, GFLAGS),
GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, 
GFLAGS),
 
-- 
1.9.1

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[PATCH v2] clk: rockchip: change hierarchy for some clocks

[Kever Yang]

There are some bus clock for multiple controllers with the same
function in rk3288: four usb controllers on hclk_usb_peri,
two nandc on hclk_emem and four dw_emmc controller on hclk_mem.
These bus clock has the same parent with the controllers,
they should be enabled if at least one of controllers
on that bus is enabled, and should be disabled if all the
controllers are disabled.

There is no existern way to describ this kind of dependency,
so maybe we can make the bus clock as a pseudo parent.

This patch change the hierarchy for these bus clocks, to met
the following bus hierarchy:
hclk_usb_peri is bus clock for
|- hclk_otg0,
|- hclk_host0,
|- hclk_host1,
|- hclk_hsic

hclk_emem is bus clock for
|- hclk_nandc0
|- hclk_nandc1

hclk_mem is bus clock for
|- hclk_sdmmc
|- hclk_sdio0
|- hclk_sdio1
|- hclk_emmc

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

Changes in v2:
- update the commit message

 drivers/clk/rockchip/clk-rk3288.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index baf8a89..d31bc45 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -652,21 +652,21 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
 
/* hclk_peri gates */
GATE(0, hclk_peri_matrix, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(6), 0, GFLAGS),
-   GATE(HCLK_OTG0, hclk_otg0, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 4, GFLAGS),
-   GATE(HCLK_USBHOST0, hclk_host0, hclk_peri, 0, 
RK3288_CLKGATE_CON(7), 6, GFLAGS),
-   GATE(HCLK_USBHOST1, hclk_host1, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 7, GFLAGS),
-   GATE(HCLK_HSIC, hclk_hsic, hclk_peri, 0, RK3288_CLKGATE_CON(7), 8, 
GFLAGS),
+   GATE(HCLK_OTG0, hclk_otg0, hclk_usb_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 4, GFLAGS),
+   GATE(HCLK_USBHOST0, hclk_host0, hclk_usb_peri, 0, 
RK3288_CLKGATE_CON(7), 6, GFLAGS),
+   GATE(HCLK_USBHOST1, hclk_host1, hclk_usb_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 7, GFLAGS),
+   GATE(HCLK_HSIC, hclk_hsic, hclk_usb_peri, 0, RK3288_CLKGATE_CON(7), 
8, GFLAGS),
GATE(0, hclk_usb_peri, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 9, GFLAGS),
GATE(0, hclk_peri_ahb_arbi, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 10, GFLAGS),
GATE(0, hclk_emem, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 12, GFLAGS),
GATE(0, hclk_mem, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 13, GFLAGS),
-   GATE(HCLK_NANDC0, hclk_nandc0, hclk_peri, 0, RK3288_CLKGATE_CON(7), 
14, GFLAGS),
-   GATE(HCLK_NANDC1, hclk_nandc1, hclk_peri, 0, RK3288_CLKGATE_CON(7), 
15, GFLAGS),
+   GATE(HCLK_NANDC0, hclk_nandc0, hclk_emem, 0, RK3288_CLKGATE_CON(7), 
14, GFLAGS),
+   GATE(HCLK_NANDC1, hclk_nandc1, hclk_emem, 0, RK3288_CLKGATE_CON(7), 
15, GFLAGS),
GATE(HCLK_TSP, hclk_tsp, hclk_peri, 0, RK3288_CLKGATE_CON(8), 8, 
GFLAGS),
-   GATE(HCLK_SDMMC, hclk_sdmmc, hclk_peri, 0, RK3288_CLKGATE_CON(8), 
3, GFLAGS),
-   GATE(HCLK_SDIO0, hclk_sdio0, hclk_peri, 0, RK3288_CLKGATE_CON(8), 
4, GFLAGS),
-   GATE(HCLK_SDIO1, hclk_sdio1, hclk_peri, 0, RK3288_CLKGATE_CON(8), 
5, GFLAGS),
-   GATE(HCLK_EMMC, hclk_emmc, hclk_peri, 0, RK3288_CLKGATE_CON(8), 6, 
GFLAGS),
+   GATE(HCLK_SDMMC, hclk_sdmmc, hclk_mem, 0, RK3288_CLKGATE_CON(8), 3, 
GFLAGS),
+   GATE(HCLK_SDIO0, hclk_sdio0, hclk_mem, 0, RK3288_CLKGATE_CON(8), 4, 
GFLAGS),
+   GATE(HCLK_SDIO1, hclk_sdio1, hclk_mem, 0, RK3288_CLKGATE_CON(8), 5, 
GFLAGS),
+   GATE(HCLK_EMMC, hclk_emmc, hclk_mem, 0, RK3288_CLKGATE_CON(8), 6, 
GFLAGS),
GATE(HCLK_HSADC, hclk_hsadc, hclk_peri, 0, RK3288_CLKGATE_CON(8), 
7, GFLAGS),
GATE(0, pmu_hclk_otg0, hclk_peri, 0, RK3288_CLKGATE_CON(7), 5, 
GFLAGS),
 
-- 
1.9.1

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[PATCH v2] usb: dwc2: add bus suspend/resume for dwc2

[Kever Yang]

Hcd controller needs bus_suspend/resume, dwc2 controller make
root hub generate suspend/resume signal with hprt0 register
when work in host mode.
After the root hub enter suspend, we can make controller enter
low power state with PCGCTL register.

We also update the lx_state for hsotg state.

This patch has tested on rk3288 with suspend/resume.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

Changes in v2:
- update commit message
- make dwc2 suspend/resume sourcecode work

 drivers/usb/dwc2/hcd.c | 78 +++---
 1 file changed, 67 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 0a0e6f0..01a415b 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -1471,6 +1471,30 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, 
u16 windex)
}
 }
 
+static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
+{
+   u32 hprt0;
+
+   /* After clear the Stop PHY clock bit, we should wait for a moment
+* for PLL work stable with clock output.
+*/
+   writel(0, hsotg-regs + PCGCTL);
+   usleep_range(2000, 4000);
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   hprt0 |= HPRT0_RES;
+   writel(hprt0, hsotg-regs + HPRT0);
+   hprt0 = ~HPRT0_SUSP;
+   /* according to USB2.0 Spec 7.1.7.7, the host must send the resume
+* signal for at least 20ms
+*/
+   usleep_range(2, 25000);
+
+   hprt0 = ~HPRT0_RES;
+   writel(hprt0, hsotg-regs + HPRT0);
+   hsotg-lx_state = DWC2_L0;
+}
+
 /* Handles hub class-specific requests */
 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
u16 wvalue, u16 windex, char *buf, u16 wlength)
@@ -1516,17 +1540,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg 
*hsotg, u16 typereq,
case USB_PORT_FEAT_SUSPEND:
dev_dbg(hsotg-dev,
ClearPortFeature USB_PORT_FEAT_SUSPEND\n);
-   writel(0, hsotg-regs + PCGCTL);
-   usleep_range(2, 4);
-
-   hprt0 = dwc2_read_hprt0(hsotg);
-   hprt0 |= HPRT0_RES;
-   writel(hprt0, hsotg-regs + HPRT0);
-   hprt0 = ~HPRT0_SUSP;
-   usleep_range(10, 15);
-
-   hprt0 = ~HPRT0_RES;
-   writel(hprt0, hsotg-regs + HPRT0);
+   dwc2_port_resume(hsotg);
break;
 
case USB_PORT_FEAT_POWER:
@@ -2299,6 +2313,44 @@ static void _dwc2_hcd_stop(struct usb_hcd *hcd)
usleep_range(1000, 3000);
 }
 
+static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (!((hsotg-op_state == OTG_STATE_B_HOST) ||
+   (hsotg-op_state == OTG_STATE_A_HOST)))
+   return 0;
+
+   if (hsotg-lx_state != DWC2_L0)
+   return 0;
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   if (hprt0  HPRT0_CONNSTS)
+   dwc2_port_suspend(hsotg, 1);
+
+   return 0;
+}
+
+static int _dwc2_hcd_resume(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (!((hsotg-op_state == OTG_STATE_B_HOST) ||
+   (hsotg-op_state == OTG_STATE_A_HOST)))
+   return 0;
+
+   if (hsotg-lx_state != DWC2_L2)
+   return 0;
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   if ((hprt0  HPRT0_CONNSTS)  (hprt0  HPRT0_SUSP))
+   dwc2_port_resume(hsotg);
+
+   return 0;
+}
+
 /* Returns the current frame number */
 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
 {
@@ -2669,6 +2721,10 @@ static struct hc_driver dwc2_hc_driver = {
.hub_status_data = _dwc2_hcd_hub_status_data,
.hub_control = _dwc2_hcd_hub_control,
.clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
+#ifdef CONFIG_PM
+   .bus_suspend = _dwc2_hcd_suspend,
+   .bus_resume = _dwc2_hcd_resume,
+#endif
 };
 
 /*
-- 
1.9.1

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Re: [PATCH] clk: rockchip: change hierarchy for some clocks

[Kever Yang]

Hi Doug,

On 11/05/2014 05:32 AM, Doug Anderson wrote:

Kever

On Fri, Oct 31, 2014 at 2:29 AM, Kever Yang  wrote:

This patch change the hierarchy for some clocks, to met the following
bus hierarchy:
hclk_usb_peri is bus clock for
|- hclk_otg0,
|- hclk_host0,
|- hclk_host1,
|- hclk_hsic

hclk_emem is bus clock for
|- hclk_nandc0
|- hclk_nandc1

hclk_mem is bus clock for
|- hclk_sdmmc
|- hclk_sdio0
|- hclk_sdio1
|- hclk_emmc

So as I understand it the "parent" clocks aren't really parents but
are actually peer clocks.  That is if "hclk_usb_peri" is gated
"hclk_otg0" continues to run.  ...but the OTG periperhal is useless
without "hclk_usb_peri" also being enabled.

Correct.


There doesn't seem to be any real downside to modeling thing as you
have done it, though it's not quite a true representation of the
world.  A slightly more true representation would be to make it so
that whenever "hclk_otg0" is enabled/disabled that it makes an
enable/disable call to "hclk_usb_peri".  I think you'd have to
subclass the gate clock and patch your stuff in the "enable" function.

I'm personally OK with things landing as you've described it (I can
see no downside), but it seems like this at least deserves a comment
(either in the code or the commit message).

I will update the commit message in new version, I describe it
in a private mail ask for how to handle this kind of clock, but not
in this patch, I will add it.


If Mike T. thinks that we should use a more truthful model or if
there's some better way to express this, you should of course listen
to him and not to me.

Sure, I'm always looks for a better way for these kind of clocks,
there are many other clocks like *_arbi and *_niu still on rk3288
are not handled by any module which we have to use
CLK_IGNORE_UNUSED tag when disable unused init.

- Kever
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[PATCH v5] clk: rockchip: disable unused clocks

[Kever Yang]

The rockchip clock driver use CLK_IGNORE_UNUSED flag to make sure
all the clocks are available like default power on state.
We have implement the clock manage in most of rockchip drivers,
it is time to remove it for power save.
Instead we add CLK_IGNORE_UNUSED for some clock nodes which should
be on during boot or no module driver in kernel will initialize it.

Signed-off-by: Kever Yang 
Reviewed-by: Doug Anderson 
Tested-by: Doug Anderson 
---

Changes in v5:
- take CLK_IGNORE_UNUSED tag out of EMMC and UART2
- take CLK_IGNORE_UNUSED tag out of pclk_publ*, pclk_ddrupctl*
- add Doug's Reviewed-by and Tested-by

Changes in v4:
- add CLK_IGNORE_UNUSED tag for all the niu/arbi/matrix clock

Changes in v3:
- get CLK_DIVIDER_READ_ONLY tag back fro armcores
- add CLK_IGNORE_UNUSED tag for cs_dbg, pclk_dgb_pre and pclk_rkpwm

Changes in v2:
- get some clock ID back
- add CLK_IGNORE_UNUSED tag for aclk_strc and aclk_core in clk-rk3188.c
- add CLK_IGNORE_UNUSED tag for rk3288 dwc2

 drivers/clk/rockchip/clk-rk3188.c |  40 ++--
 drivers/clk/rockchip/clk-rk3288.c | 132 +++---
 drivers/clk/rockchip/clk.c|   9 ---
 3 files changed, 86 insertions(+), 95 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3188.c 
b/drivers/clk/rockchip/clk-rk3188.c
index beed49c..1800cfe 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -257,9 +257,9 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
RK2928_CLKGATE_CON(3), 12, GFLAGS),
 
-   GATE(0, "gpll_ddr", "gpll", 0,
+   GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 7, GFLAGS),
-   COMPOSITE(0, "ddrphy", mux_ddrphy_p, 0,
+   COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | 
CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
 
@@ -270,10 +270,10 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
RK2928_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,
RK2928_CLKGATE_CON(0), 5, GFLAGS),
-   GATE(0, "hclk_cpu", "hclk_cpu_pre", 0,
+   GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 4, GFLAGS),
 
-   COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 0,
+   COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 
CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 0, GFLAGS),
COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
@@ -304,9 +304,9 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
 * the 480m are generated inside the usb block from these clocks,
 * but they are also a source for the hsicphy clock.
 */
-   GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
+   GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 5, GFLAGS),
-   GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
+   GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 6, GFLAGS),
 
COMPOSITE(0, "mac_src", mux_mac_p, 0,
@@ -399,8 +399,8 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
 
/* aclk_cpu gates */
GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, 
GFLAGS),
-   GATE(0, "aclk_intmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 12, 
GFLAGS),
-   GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 10, 
GFLAGS),
+   GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 12, GFLAGS),
+   GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 10, GFLAGS),
 
/* hclk_cpu gates */
GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, 
GFLAGS),
@@ -416,8 +416,8 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, 
GFLAGS),
 
/* hclk_peri gates */
-   GATE(0, "hclk_peri_axi_matrix", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 
0, GFLAGS),
-   GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK2928_CL

[PATCH v5] clk: rockchip: disable unused clocks

[Kever Yang]

The rockchip clock driver use CLK_IGNORE_UNUSED flag to make sure
all the clocks are available like default power on state.
We have implement the clock manage in most of rockchip drivers,
it is time to remove it for power save.
Instead we add CLK_IGNORE_UNUSED for some clock nodes which should
be on during boot or no module driver in kernel will initialize it.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
---

Changes in v5:
- take CLK_IGNORE_UNUSED tag out of EMMC and UART2
- take CLK_IGNORE_UNUSED tag out of pclk_publ*, pclk_ddrupctl*
- add Doug's Reviewed-by and Tested-by

Changes in v4:
- add CLK_IGNORE_UNUSED tag for all the niu/arbi/matrix clock

Changes in v3:
- get CLK_DIVIDER_READ_ONLY tag back fro armcores
- add CLK_IGNORE_UNUSED tag for cs_dbg, pclk_dgb_pre and pclk_rkpwm

Changes in v2:
- get some clock ID back
- add CLK_IGNORE_UNUSED tag for aclk_strc and aclk_core in clk-rk3188.c
- add CLK_IGNORE_UNUSED tag for rk3288 dwc2

 drivers/clk/rockchip/clk-rk3188.c |  40 ++--
 drivers/clk/rockchip/clk-rk3288.c | 132 +++---
 drivers/clk/rockchip/clk.c|   9 ---
 3 files changed, 86 insertions(+), 95 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3188.c 
b/drivers/clk/rockchip/clk-rk3188.c
index beed49c..1800cfe 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -257,9 +257,9 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
GATE(0, hclk_vdpu, aclk_vdpu, 0,
RK2928_CLKGATE_CON(3), 12, GFLAGS),
 
-   GATE(0, gpll_ddr, gpll, 0,
+   GATE(0, gpll_ddr, gpll, CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 7, GFLAGS),
-   COMPOSITE(0, ddrphy, mux_ddrphy_p, 0,
+   COMPOSITE(0, ddrphy, mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | 
CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
 
@@ -270,10 +270,10 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
RK2928_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, pclk_cpu, pclk_cpu_pre, 0,
RK2928_CLKGATE_CON(0), 5, GFLAGS),
-   GATE(0, hclk_cpu, hclk_cpu_pre, 0,
+   GATE(0, hclk_cpu, hclk_cpu_pre, CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 4, GFLAGS),
 
-   COMPOSITE(0, aclk_lcdc0_pre, mux_pll_src_cpll_gpll_p, 0,
+   COMPOSITE(0, aclk_lcdc0_pre, mux_pll_src_cpll_gpll_p, 
CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 0, GFLAGS),
COMPOSITE(0, aclk_lcdc1_pre, mux_pll_src_cpll_gpll_p, 0,
@@ -304,9 +304,9 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
 * the 480m are generated inside the usb block from these clocks,
 * but they are also a source for the hsicphy clock.
 */
-   GATE(SCLK_OTGPHY0, sclk_otgphy0, usb480m, 0,
+   GATE(SCLK_OTGPHY0, sclk_otgphy0, usb480m, CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 5, GFLAGS),
-   GATE(SCLK_OTGPHY1, sclk_otgphy1, usb480m, 0,
+   GATE(SCLK_OTGPHY1, sclk_otgphy1, usb480m, CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 6, GFLAGS),
 
COMPOSITE(0, mac_src, mux_mac_p, 0,
@@ -399,8 +399,8 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
 
/* aclk_cpu gates */
GATE(ACLK_DMA1, aclk_dma1, aclk_cpu, 0, RK2928_CLKGATE_CON(5), 0, 
GFLAGS),
-   GATE(0, aclk_intmem, aclk_cpu, 0, RK2928_CLKGATE_CON(4), 12, 
GFLAGS),
-   GATE(0, aclk_strc_sys, aclk_cpu, 0, RK2928_CLKGATE_CON(4), 10, 
GFLAGS),
+   GATE(0, aclk_intmem, aclk_cpu, CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 12, GFLAGS),
+   GATE(0, aclk_strc_sys, aclk_cpu, CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 10, GFLAGS),
 
/* hclk_cpu gates */
GATE(HCLK_ROM, hclk_rom, hclk_cpu, 0, RK2928_CLKGATE_CON(5), 6, 
GFLAGS),
@@ -416,8 +416,8 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
GATE(HCLK_RGA, hclk_rga, hclk_cpu, 0, RK2928_CLKGATE_CON(6), 10, 
GFLAGS),
 
/* hclk_peri gates */
-   GATE(0, hclk_peri_axi_matrix, hclk_peri, 0, RK2928_CLKGATE_CON(4), 
0, GFLAGS),
-   GATE(0, hclk_peri_ahb_arbi, hclk_peri, 0, RK2928_CLKGATE_CON(4), 6, 
GFLAGS),
+   GATE(0, hclk_peri_axi_matrix, hclk_peri, CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 0, GFLAGS),
+   GATE(0, hclk_peri_ahb_arbi, hclk_peri, CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 6, GFLAGS),
GATE(0, hclk_emem_peri, hclk_peri, 0, RK2928_CLKGATE_CON(4), 7, 
GFLAGS),
GATE(HCLK_EMAC, hclk_emac, hclk_peri, 0, RK2928_CLKGATE_CON(7), 0, 
GFLAGS),
GATE(HCLK_NANDC0, hclk_nandc0, hclk_peri, 0

Re: [PATCH] clk: rockchip: change hierarchy for some clocks

[Kever Yang]

Hi Doug,

On 11/05/2014 05:32 AM, Doug Anderson wrote:

Kever

On Fri, Oct 31, 2014 at 2:29 AM, Kever Yang kever.y...@rock-chips.com wrote:

This patch change the hierarchy for some clocks, to met the following
bus hierarchy:
hclk_usb_peri is bus clock for
|- hclk_otg0,
|- hclk_host0,
|- hclk_host1,
|- hclk_hsic

hclk_emem is bus clock for
|- hclk_nandc0
|- hclk_nandc1

hclk_mem is bus clock for
|- hclk_sdmmc
|- hclk_sdio0
|- hclk_sdio1
|- hclk_emmc

So as I understand it the parent clocks aren't really parents but
are actually peer clocks.  That is if hclk_usb_peri is gated
hclk_otg0 continues to run.  ...but the OTG periperhal is useless
without hclk_usb_peri also being enabled.

Correct.


There doesn't seem to be any real downside to modeling thing as you
have done it, though it's not quite a true representation of the
world.  A slightly more true representation would be to make it so
that whenever hclk_otg0 is enabled/disabled that it makes an
enable/disable call to hclk_usb_peri.  I think you'd have to
subclass the gate clock and patch your stuff in the enable function.

I'm personally OK with things landing as you've described it (I can
see no downside), but it seems like this at least deserves a comment
(either in the code or the commit message).

I will update the commit message in new version, I describe it
in a private mail ask for how to handle this kind of clock, but not
in this patch, I will add it.


If Mike T. thinks that we should use a more truthful model or if
there's some better way to express this, you should of course listen
to him and not to me.

Sure, I'm always looks for a better way for these kind of clocks,
there are many other clocks like *_arbi and *_niu still on rk3288
are not handled by any module which we have to use
CLK_IGNORE_UNUSED tag when disable unused init.

- Kever
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[PATCH 5/5] clk: rockchip: change DCLK_VOP0 to use new COMPOSITE_DIVOPS

[Kever Yang]

The HDMI clock is actually provide by DCLK_VOP0, so we need this
patch to handle the HDMI clock correctly

Signed-off-by: Kever Yang 
---

 drivers/clk/rockchip/clk-rk3288.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 0151140..073a719 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -396,8 +396,10 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 4, GFLAGS),
 
-   COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE_DIVOPS(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p,
+   (CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT),
RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
+   _vop_ops,
RK3288_CLKGATE_CON(3), 1, GFLAGS),
COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
-- 
1.9.1

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[PATCH 0/5] clk: rockchip: add full support for HDMI clock on rk3288

[Kever Yang]

we are going to make a clock usage solution for rk3288:
1. CPLL and GPLL always not change after assign init;
2. NPLL default as 500MHz, may used for most scene;
3. NPLL may be changed by VOP(HDMI) clock for some special
   frequency requirement.

I test it with rk3288 evb on top of Heiko's clk-for-next


Kever Yang (5):
  clk: rockchip: add some clock rate into rate table for rk3288
  clk: divider: make clk_divider_recalc/set_rate available
  clk: rockchip: introduce the div_ops handling for composite branches
  clk: rockchip: add the vop_determine_rate for vop dclock
  clk: rockchip: change DCLK_VOP0 to use new COMPOSITE_DIVOPS

 drivers/clk/clk-divider.c |  4 +--
 drivers/clk/rockchip/clk-rk3288.c | 76 ++-
 drivers/clk/rockchip/clk.c| 13 ---
 drivers/clk/rockchip/clk.h| 24 +
 include/linux/clk-provider.h  |  4 +++
 5 files changed, 114 insertions(+), 7 deletions(-)

-- 
1.9.1

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[PATCH 2/5] clk: divider: make clk_divider_recalc/set_rate available

[Kever Yang]

This patch makes these two function available for other file,
which may help to make costom usage of clock divider type.

Signed-off-by: Kever Yang 
---

 drivers/clk/clk-divider.c| 4 ++--
 include/linux/clk-provider.h | 4 
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 18a9de2..f3f55a8 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -109,7 +109,7 @@ static unsigned int _get_val(struct clk_divider *divider, 
unsigned int div)
return div - 1;
 }
 
-static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
+unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
 {
struct clk_divider *divider = to_clk_divider(hw);
@@ -318,7 +318,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, 
unsigned long rate,
return DIV_ROUND_UP(*prate, div);
 }
 
-static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
 {
struct clk_divider *divider = to_clk_divider(hw);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index be21af1..7947fe9 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -555,6 +555,10 @@ struct clk *__clk_lookup(const char *name);
 long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
  unsigned long *best_parent_rate,
  struct clk **best_parent_p);
+unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate);
+int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long parent_rate);
 
 /*
  * FIXME clock api without lock protection
-- 
1.9.1

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[PATCH 4/5] clk: rockchip: add the vop_determine_rate for vop dclock

[Kever Yang]

Rk3288 has 5 PLLs(APLL, DPLL, CPLL, GPLL, NPLL),
APLL is for CPU clock only and DPLL is for DRAM clock only,
and other 3 PLls used for all other peripherals.
We have to make a total solution for how to campatible all
kinds of clock requirement by on chip peripheral controllers.

Some controllers like I2S and HDMI need accurate frequency while
others controllers accept clock rate with margin.

According to our experience on rk3288, we prefer to use CPLL and GPLL fixed
at 400MHz and 594MHz for general use for most peripheral.

The fraction divider should be enough for I2S controller.

The HDMI is the most diffical one if we have to support all the
resolution requirement for frequency. Most people use 720p and
1080 i/p resolution with 74.25MHz/148.5MHz, which can get clock
rate from 594MHz(maybe from GPLL). some other resolution like
640*480 will use 25.175MHz, which is hard to get from general
used PLLs.

So it is better to make HDMI controller has the right to change
the PLL frequency and get the clock rate it wants.

We set NPLL to 500MHz as default, if HDMI can get what it need
from existent clock provider, then change its divider and switch
to that parent; if not, we have to change the NPLL's output
and always make CPLL not change.

This patch add vop_determinate_rate as a div_ops to handle
the HDMI clock things.

Signed-off-by: Kever Yang 
---

 drivers/clk/rockchip/clk-rk3288.c | 69 +++
 1 file changed, 69 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 48412e9..0151140 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -14,6 +14,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -25,6 +26,7 @@
 enum rk3288_plls {
apll, dpll, cpll, gpll, npll,
 };
+const struct clk_ops dclk_vop_ops;
 
 struct rockchip_pll_rate_table rk3288_pll_rates[] = {
RK3066_PLL_RATE(220800, 1, 92, 1),
@@ -766,6 +768,73 @@ static const char *rk3288_critical_clocks[] __initconst = {
"aclk_peri",
"hclk_peri",
 };
+#define DCLK_VOP_PARENT_NPLL 2
+
+long dclk_vop_determine_rate(struct clk_hw *hw, unsigned long rate,
+   unsigned long *best_parent_rate,
+   struct clk **best_parent_p)
+{
+   struct clk *clk = hw->clk, *parent;
+   unsigned long parent_rate, best = 0;
+   int num_parents = clk->num_parents;
+   int i;
+
+   /*
+* check if one of the generic plls can provide a cleanly dividable
+* rate without changing them.
+*/
+   for (i = 0; i < (num_parents - 1); i++) {
+   parent = clk_get_parent_by_index(clk, i);
+   parent_rate = __clk_get_rate(parent);
+   if (parent_rate % rate == 0) {
+   *best_parent_p = parent;
+   *best_parent_rate = parent_rate;
+   return rate;
+   }
+   }
+
+   /* take the npll and set its rate to something suitable */
+   for (i = 0; rk3288_pll_rates[i].rate != 0; i++) {
+   if (rk3288_pll_rates[i].rate % rate == 0) {
+   *best_parent_p = clk_get_parent_by_index(clk,
+   DCLK_VOP_PARENT_NPLL);
+   *best_parent_rate = rk3288_pll_rates[i].rate;
+   return rk3288_pll_rates[i].rate;
+   }
+   }
+
+   /*
+* We were not able to find a matching rate, so falling back
+* to finding the fastest rate < rate.
+* We allow the npll to change its rate while the other plls
+* are not allowed to change.
+*/
+   for (i = 0; i < num_parents; i++) {
+   parent = clk_get_parent_by_index(clk, i);
+   if (!parent)
+   continue;
+
+   if (i == DCLK_VOP_PARENT_NPLL)
+   parent_rate = __clk_round_rate(parent, rate);
+   else
+   parent_rate = __clk_get_rate(parent);
+   if (parent_rate <= rate && parent_rate > best) {
+   int div = DIV_ROUND_UP(parent_rate, rate);
+   *best_parent_p = parent;
+   *best_parent_rate = parent_rate;
+   best = DIV_ROUND_UP(parent_rate, div);
+   }
+   }
+
+   return best;
+}
+
+
+const struct clk_ops dclk_vop_ops = {
+   .recalc_rate = clk_divider_recalc_rate,
+   .set_rate = clk_divider_set_rate,
+   .determine_rate = dclk_vop_determine_rate,
+};
 
 static void __init rk3288_clk_init(struct device_node *np)
 {
-- 
1.9.1

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[PATCH 1/5] clk: rockchip: add some clock rate into rate table for rk3288

[Kever Yang]

We are going to support all the HDMI resolutions which need a bunch
of accurate clock rates. This patch makes the pll rate table can
provide all the option clock rate that HDMI controller may needed.

Here's what HDMI needs:
resolutions Pixel clock(Mhz)
1920x1080p 60/50148.5
1920x1080i 100/120  148.5
1920x1080i 60/5074.25
1280x720p 60/50/30/25   74.25
720x576p 50 27
720x480p 60 27
1440x480i 6027
1440x576i 5027
1680x1050 60146.25
1280x1024 60108
1280x960 60 108
1440x900 60 106.5
1280x800 60 83.5
1024x768 60 65
800x600 60  40
800x600 56  36
640x480 60  25.175

Signed-off-by: Kever Yang 
---

 drivers/clk/rockchip/clk-rk3288.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 279a662..48412e9 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -73,6 +73,7 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
RK3066_PLL_RATE(112800, 1, 47, 1),
RK3066_PLL_RATE(110400, 1, 46, 1),
RK3066_PLL_RATE(100800, 1, 84, 2),
+   RK3066_PLL_RATE(100700, 12, 1007, 2),
RK3066_PLL_RATE( 91200, 1, 76, 2),
RK3066_PLL_RATE( 89100, 8, 594, 2),
RK3066_PLL_RATE( 88800, 1, 74, 2),
@@ -84,6 +85,7 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
RK3066_PLL_RATE( 69600, 1, 58, 2),
RK3066_PLL_RATE( 6, 1, 50, 2),
RK3066_PLL_RATE_BWADJ(59400, 1, 198, 8, 1),
+   RK3066_PLL_RATE( 58500, 4, 195, 2),
RK3066_PLL_RATE( 55200, 1, 46, 2),
RK3066_PLL_RATE( 50400, 1, 84, 4),
RK3066_PLL_RATE( 5, 3, 125, 2),
@@ -97,6 +99,7 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
RK3066_PLL_RATE( 29700, 2, 198, 8),
RK3066_PLL_RATE( 25200, 1, 84, 8),
RK3066_PLL_RATE( 21600, 1, 72, 8),
+   RK3066_PLL_RATE( 16700, 3, 167, 8),
RK3066_PLL_RATE( 14850, 2, 99, 8),
RK3066_PLL_RATE( 12600, 1, 84, 16),
RK3066_PLL_RATE(  4800, 1, 64, 32),
-- 
1.9.1

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[PATCH 3/5] clk: rockchip: introduce the div_ops handling for composite branches

[Kever Yang]

Rockchip Socs have a lot of clock node registered as composite
branch which include mux, divider and gate, most of them use
the same ops handling callback, we still need special ops
handling for some special clock node and this patch make it
possible.

Signed-off-by: Kever Yang 
---

 drivers/clk/rockchip/clk.c | 13 +
 drivers/clk/rockchip/clk.h | 24 
 2 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 1e68bff..0917c2b 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -42,6 +42,7 @@ static struct clk *rockchip_clk_register_branch(const char 
*name,
const char **parent_names, u8 num_parents, void __iomem *base,
int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
u8 div_shift, u8 div_width, u8 div_flags,
+   const struct clk_ops *divops,
struct clk_div_table *div_table, int gate_offset,
u8 gate_shift, u8 gate_flags, unsigned long flags,
spinlock_t *lock)
@@ -90,9 +91,12 @@ static struct clk *rockchip_clk_register_branch(const char 
*name,
div->width = div_width;
div->lock = lock;
div->table = div_table;
-   div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
-   ? _divider_ro_ops
-   : _divider_ops;
+   if (divops)
+   div_ops = divops;
+   else if (div_flags & CLK_DIVIDER_READ_ONLY)
+   div_ops = _divider_ro_ops;
+   else
+   div_ops = _divider_ops;
}
 
clk = clk_register_composite(NULL, name, parent_names, num_parents,
@@ -275,7 +279,8 @@ void __init rockchip_clk_register_branches(
reg_base, list->muxdiv_offset, list->mux_shift,
list->mux_width, list->mux_flags,
list->div_shift, list->div_width,
-   list->div_flags, list->div_table,
+   list->div_flags,
+   list->div_ops, list->div_table,
list->gate_offset, list->gate_shift,
list->gate_flags, flags, _lock);
break;
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 6baf665..2cf263b 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -185,6 +185,7 @@ struct rockchip_clk_branch {
u8  div_shift;
u8  div_width;
u8  div_flags;
+   const struct clk_ops*div_ops;
struct clk_div_table*div_table;
int gate_offset;
u8  gate_shift;
@@ -212,6 +213,29 @@ struct rockchip_clk_branch {
.gate_flags = gf,   \
}
 
+#define COMPOSITE_DIVOPS(_id, cname, pnames, f, mo, ms, mw, mf, \
+   ds, dw, df, dops, go, gs, gf)   \
+   {   \
+   .id = _id,  \
+   .branch_type= branch_composite, \
+   .name   = cname,\
+   .parent_names   = pnames,   \
+   .num_parents= ARRAY_SIZE(pnames),   \
+   .flags  = f,\
+   .muxdiv_offset  = mo,   \
+   .mux_shift  = ms,   \
+   .mux_width  = mw,   \
+   .mux_flags  = mf,   \
+   .div_shift  = ds,   \
+   .div_width  = dw,   \
+   .div_flags  = df,   \
+   .div_ops= dops, \
+   .gate_offset= go,   \
+   .gate_shift = gs,   \
+   .gate_flags = gf,   \
+   }
+
+
 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df,  \
go, gs, gf) \
{   \
-- 
1.9.1

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[PATCH 1/5] clk: rockchip: add some clock rate into rate table for rk3288

[Kever Yang]

We are going to support all the HDMI resolutions which need a bunch
of accurate clock rates. This patch makes the pll rate table can
provide all the option clock rate that HDMI controller may needed.

Here's what HDMI needs:
resolutions Pixel clock(Mhz)
1920x1080p 60/50148.5
1920x1080i 100/120  148.5
1920x1080i 60/5074.25
1280x720p 60/50/30/25   74.25
720x576p 50 27
720x480p 60 27
1440x480i 6027
1440x576i 5027
1680x1050 60146.25
1280x1024 60108
1280x960 60 108
1440x900 60 106.5
1280x800 60 83.5
1024x768 60 65
800x600 60  40
800x600 56  36
640x480 60  25.175

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 drivers/clk/rockchip/clk-rk3288.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 279a662..48412e9 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -73,6 +73,7 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
RK3066_PLL_RATE(112800, 1, 47, 1),
RK3066_PLL_RATE(110400, 1, 46, 1),
RK3066_PLL_RATE(100800, 1, 84, 2),
+   RK3066_PLL_RATE(100700, 12, 1007, 2),
RK3066_PLL_RATE( 91200, 1, 76, 2),
RK3066_PLL_RATE( 89100, 8, 594, 2),
RK3066_PLL_RATE( 88800, 1, 74, 2),
@@ -84,6 +85,7 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
RK3066_PLL_RATE( 69600, 1, 58, 2),
RK3066_PLL_RATE( 6, 1, 50, 2),
RK3066_PLL_RATE_BWADJ(59400, 1, 198, 8, 1),
+   RK3066_PLL_RATE( 58500, 4, 195, 2),
RK3066_PLL_RATE( 55200, 1, 46, 2),
RK3066_PLL_RATE( 50400, 1, 84, 4),
RK3066_PLL_RATE( 5, 3, 125, 2),
@@ -97,6 +99,7 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
RK3066_PLL_RATE( 29700, 2, 198, 8),
RK3066_PLL_RATE( 25200, 1, 84, 8),
RK3066_PLL_RATE( 21600, 1, 72, 8),
+   RK3066_PLL_RATE( 16700, 3, 167, 8),
RK3066_PLL_RATE( 14850, 2, 99, 8),
RK3066_PLL_RATE( 12600, 1, 84, 16),
RK3066_PLL_RATE(  4800, 1, 64, 32),
-- 
1.9.1

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[PATCH 3/5] clk: rockchip: introduce the div_ops handling for composite branches

[Kever Yang]

Rockchip Socs have a lot of clock node registered as composite
branch which include mux, divider and gate, most of them use
the same ops handling callback, we still need special ops
handling for some special clock node and this patch make it
possible.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 drivers/clk/rockchip/clk.c | 13 +
 drivers/clk/rockchip/clk.h | 24 
 2 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 1e68bff..0917c2b 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -42,6 +42,7 @@ static struct clk *rockchip_clk_register_branch(const char 
*name,
const char **parent_names, u8 num_parents, void __iomem *base,
int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
u8 div_shift, u8 div_width, u8 div_flags,
+   const struct clk_ops *divops,
struct clk_div_table *div_table, int gate_offset,
u8 gate_shift, u8 gate_flags, unsigned long flags,
spinlock_t *lock)
@@ -90,9 +91,12 @@ static struct clk *rockchip_clk_register_branch(const char 
*name,
div-width = div_width;
div-lock = lock;
div-table = div_table;
-   div_ops = (div_flags  CLK_DIVIDER_READ_ONLY)
-   ? clk_divider_ro_ops
-   : clk_divider_ops;
+   if (divops)
+   div_ops = divops;
+   else if (div_flags  CLK_DIVIDER_READ_ONLY)
+   div_ops = clk_divider_ro_ops;
+   else
+   div_ops = clk_divider_ops;
}
 
clk = clk_register_composite(NULL, name, parent_names, num_parents,
@@ -275,7 +279,8 @@ void __init rockchip_clk_register_branches(
reg_base, list-muxdiv_offset, list-mux_shift,
list-mux_width, list-mux_flags,
list-div_shift, list-div_width,
-   list-div_flags, list-div_table,
+   list-div_flags,
+   list-div_ops, list-div_table,
list-gate_offset, list-gate_shift,
list-gate_flags, flags, clk_lock);
break;
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 6baf665..2cf263b 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -185,6 +185,7 @@ struct rockchip_clk_branch {
u8  div_shift;
u8  div_width;
u8  div_flags;
+   const struct clk_ops*div_ops;
struct clk_div_table*div_table;
int gate_offset;
u8  gate_shift;
@@ -212,6 +213,29 @@ struct rockchip_clk_branch {
.gate_flags = gf,   \
}
 
+#define COMPOSITE_DIVOPS(_id, cname, pnames, f, mo, ms, mw, mf, \
+   ds, dw, df, dops, go, gs, gf)   \
+   {   \
+   .id = _id,  \
+   .branch_type= branch_composite, \
+   .name   = cname,\
+   .parent_names   = pnames,   \
+   .num_parents= ARRAY_SIZE(pnames),   \
+   .flags  = f,\
+   .muxdiv_offset  = mo,   \
+   .mux_shift  = ms,   \
+   .mux_width  = mw,   \
+   .mux_flags  = mf,   \
+   .div_shift  = ds,   \
+   .div_width  = dw,   \
+   .div_flags  = df,   \
+   .div_ops= dops, \
+   .gate_offset= go,   \
+   .gate_shift = gs,   \
+   .gate_flags = gf,   \
+   }
+
+
 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df,  \
go, gs, gf) \
{   \
-- 
1.9.1

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[PATCH 4/5] clk: rockchip: add the vop_determine_rate for vop dclock

[Kever Yang]

Rk3288 has 5 PLLs(APLL, DPLL, CPLL, GPLL, NPLL),
APLL is for CPU clock only and DPLL is for DRAM clock only,
and other 3 PLls used for all other peripherals.
We have to make a total solution for how to campatible all
kinds of clock requirement by on chip peripheral controllers.

Some controllers like I2S and HDMI need accurate frequency while
others controllers accept clock rate with margin.

According to our experience on rk3288, we prefer to use CPLL and GPLL fixed
at 400MHz and 594MHz for general use for most peripheral.

The fraction divider should be enough for I2S controller.

The HDMI is the most diffical one if we have to support all the
resolution requirement for frequency. Most people use 720p and
1080 i/p resolution with 74.25MHz/148.5MHz, which can get clock
rate from 594MHz(maybe from GPLL). some other resolution like
640*480 will use 25.175MHz, which is hard to get from general
used PLLs.

So it is better to make HDMI controller has the right to change
the PLL frequency and get the clock rate it wants.

We set NPLL to 500MHz as default, if HDMI can get what it need
from existent clock provider, then change its divider and switch
to that parent; if not, we have to change the NPLL's output
and always make CPLLGPLL not change.

This patch add vop_determinate_rate as a div_ops to handle
the HDMI clock things.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 drivers/clk/rockchip/clk-rk3288.c | 69 +++
 1 file changed, 69 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 48412e9..0151140 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -14,6 +14,7 @@
  */
 
 #include linux/clk-provider.h
+#include linux/clk-private.h
 #include linux/of.h
 #include linux/of_address.h
 #include dt-bindings/clock/rk3288-cru.h
@@ -25,6 +26,7 @@
 enum rk3288_plls {
apll, dpll, cpll, gpll, npll,
 };
+const struct clk_ops dclk_vop_ops;
 
 struct rockchip_pll_rate_table rk3288_pll_rates[] = {
RK3066_PLL_RATE(220800, 1, 92, 1),
@@ -766,6 +768,73 @@ static const char *rk3288_critical_clocks[] __initconst = {
aclk_peri,
hclk_peri,
 };
+#define DCLK_VOP_PARENT_NPLL 2
+
+long dclk_vop_determine_rate(struct clk_hw *hw, unsigned long rate,
+   unsigned long *best_parent_rate,
+   struct clk **best_parent_p)
+{
+   struct clk *clk = hw-clk, *parent;
+   unsigned long parent_rate, best = 0;
+   int num_parents = clk-num_parents;
+   int i;
+
+   /*
+* check if one of the generic plls can provide a cleanly dividable
+* rate without changing them.
+*/
+   for (i = 0; i  (num_parents - 1); i++) {
+   parent = clk_get_parent_by_index(clk, i);
+   parent_rate = __clk_get_rate(parent);
+   if (parent_rate % rate == 0) {
+   *best_parent_p = parent;
+   *best_parent_rate = parent_rate;
+   return rate;
+   }
+   }
+
+   /* take the npll and set its rate to something suitable */
+   for (i = 0; rk3288_pll_rates[i].rate != 0; i++) {
+   if (rk3288_pll_rates[i].rate % rate == 0) {
+   *best_parent_p = clk_get_parent_by_index(clk,
+   DCLK_VOP_PARENT_NPLL);
+   *best_parent_rate = rk3288_pll_rates[i].rate;
+   return rk3288_pll_rates[i].rate;
+   }
+   }
+
+   /*
+* We were not able to find a matching rate, so falling back
+* to finding the fastest rate  rate.
+* We allow the npll to change its rate while the other plls
+* are not allowed to change.
+*/
+   for (i = 0; i  num_parents; i++) {
+   parent = clk_get_parent_by_index(clk, i);
+   if (!parent)
+   continue;
+
+   if (i == DCLK_VOP_PARENT_NPLL)
+   parent_rate = __clk_round_rate(parent, rate);
+   else
+   parent_rate = __clk_get_rate(parent);
+   if (parent_rate = rate  parent_rate  best) {
+   int div = DIV_ROUND_UP(parent_rate, rate);
+   *best_parent_p = parent;
+   *best_parent_rate = parent_rate;
+   best = DIV_ROUND_UP(parent_rate, div);
+   }
+   }
+
+   return best;
+}
+
+
+const struct clk_ops dclk_vop_ops = {
+   .recalc_rate = clk_divider_recalc_rate,
+   .set_rate = clk_divider_set_rate,
+   .determine_rate = dclk_vop_determine_rate,
+};
 
 static void __init rk3288_clk_init(struct device_node *np)
 {
-- 
1.9.1

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[PATCH 0/5] clk: rockchip: add full support for HDMI clock on rk3288

[Kever Yang]

we are going to make a clock usage solution for rk3288:
1. CPLL and GPLL always not change after assign init;
2. NPLL default as 500MHz, may used for most scene;
3. NPLL may be changed by VOP(HDMI) clock for some special
   frequency requirement.

I test it with rk3288 evb on top of Heiko's clk-for-next


Kever Yang (5):
  clk: rockchip: add some clock rate into rate table for rk3288
  clk: divider: make clk_divider_recalc/set_rate available
  clk: rockchip: introduce the div_ops handling for composite branches
  clk: rockchip: add the vop_determine_rate for vop dclock
  clk: rockchip: change DCLK_VOP0 to use new COMPOSITE_DIVOPS

 drivers/clk/clk-divider.c |  4 +--
 drivers/clk/rockchip/clk-rk3288.c | 76 ++-
 drivers/clk/rockchip/clk.c| 13 ---
 drivers/clk/rockchip/clk.h| 24 +
 include/linux/clk-provider.h  |  4 +++
 5 files changed, 114 insertions(+), 7 deletions(-)

-- 
1.9.1

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[PATCH 5/5] clk: rockchip: change DCLK_VOP0 to use new COMPOSITE_DIVOPS

[Kever Yang]

The HDMI clock is actually provide by DCLK_VOP0, so we need this
patch to handle the HDMI clock correctly

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 drivers/clk/rockchip/clk-rk3288.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 0151140..073a719 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -396,8 +396,10 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 4, GFLAGS),
 
-   COMPOSITE(DCLK_VOP0, dclk_vop0, mux_pll_src_cpll_gpll_npll_p, 0,
+   COMPOSITE_DIVOPS(DCLK_VOP0, dclk_vop0, mux_pll_src_cpll_gpll_npll_p,
+   (CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT),
RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
+   dclk_vop_ops,
RK3288_CLKGATE_CON(3), 1, GFLAGS),
COMPOSITE(DCLK_VOP1, dclk_vop1, mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
-- 
1.9.1

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[PATCH 2/5] clk: divider: make clk_divider_recalc/set_rate available

[Kever Yang]

This patch makes these two function available for other file,
which may help to make costom usage of clock divider type.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 drivers/clk/clk-divider.c| 4 ++--
 include/linux/clk-provider.h | 4 
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 18a9de2..f3f55a8 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -109,7 +109,7 @@ static unsigned int _get_val(struct clk_divider *divider, 
unsigned int div)
return div - 1;
 }
 
-static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
+unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
 {
struct clk_divider *divider = to_clk_divider(hw);
@@ -318,7 +318,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, 
unsigned long rate,
return DIV_ROUND_UP(*prate, div);
 }
 
-static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
 {
struct clk_divider *divider = to_clk_divider(hw);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index be21af1..7947fe9 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -555,6 +555,10 @@ struct clk *__clk_lookup(const char *name);
 long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
  unsigned long *best_parent_rate,
  struct clk **best_parent_p);
+unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate);
+int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long parent_rate);
 
 /*
  * FIXME clock api without lock protection
-- 
1.9.1

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[PATCH v4] clk: rockchip: disable unused clocks

[Kever Yang]

The rockchip clock driver use CLK_IGNORE_UNUSED flag to make sure
all the clocks are available like default power on state.
We have implement the clock manage in most of rockchip drivers,
it is time to remove it for power save.
Instead we add CLK_IGNORE_UNUSED for some clock nodes which should
be on during boot or no module driver in kernel will initialize it.

Signed-off-by: Kever Yang 
---

Changes in v4:
- add CLK_IGNORE_UNUSED tag for all the niu/arbi/matrix clock

Changes in v3:
- get CLK_DIVIDER_READ_ONLY tag back fro armcores
- add CLK_IGNORE_UNUSED tag for cs_dbg, pclk_dgb_pre and pclk_rkpwm

Changes in v2:
- get some clock ID back
- add CLK_IGNORE_UNUSED tag for aclk_strc and aclk_core in clk-rk3188.c
- add CLK_IGNORE_UNUSED tag for rk3288 dwc2

 drivers/clk/rockchip/clk-rk3188.c |  40 +--
 drivers/clk/rockchip/clk-rk3288.c | 146 +++---
 drivers/clk/rockchip/clk.c|   9 ---
 3 files changed, 93 insertions(+), 102 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3188.c 
b/drivers/clk/rockchip/clk-rk3188.c
index beed49c..1800cfe 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -257,9 +257,9 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
RK2928_CLKGATE_CON(3), 12, GFLAGS),
 
-   GATE(0, "gpll_ddr", "gpll", 0,
+   GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 7, GFLAGS),
-   COMPOSITE(0, "ddrphy", mux_ddrphy_p, 0,
+   COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | 
CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
 
@@ -270,10 +270,10 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
RK2928_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,
RK2928_CLKGATE_CON(0), 5, GFLAGS),
-   GATE(0, "hclk_cpu", "hclk_cpu_pre", 0,
+   GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 4, GFLAGS),
 
-   COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 0,
+   COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 
CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 0, GFLAGS),
COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
@@ -304,9 +304,9 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
 * the 480m are generated inside the usb block from these clocks,
 * but they are also a source for the hsicphy clock.
 */
-   GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
+   GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 5, GFLAGS),
-   GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
+   GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 6, GFLAGS),
 
COMPOSITE(0, "mac_src", mux_mac_p, 0,
@@ -399,8 +399,8 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
 
/* aclk_cpu gates */
GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, 
GFLAGS),
-   GATE(0, "aclk_intmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 12, 
GFLAGS),
-   GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 10, 
GFLAGS),
+   GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 12, GFLAGS),
+   GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 10, GFLAGS),
 
/* hclk_cpu gates */
GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, 
GFLAGS),
@@ -416,8 +416,8 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, 
GFLAGS),
 
/* hclk_peri gates */
-   GATE(0, "hclk_peri_axi_matrix", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 
0, GFLAGS),
-   GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 6, 
GFLAGS),
+   GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 0, GFLAGS),
+   GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK

[PATCH v4] clk: rockchip: disable unused clocks

[Kever Yang]

The rockchip clock driver use CLK_IGNORE_UNUSED flag to make sure
all the clocks are available like default power on state.
We have implement the clock manage in most of rockchip drivers,
it is time to remove it for power save.
Instead we add CLK_IGNORE_UNUSED for some clock nodes which should
be on during boot or no module driver in kernel will initialize it.

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

Changes in v4:
- add CLK_IGNORE_UNUSED tag for all the niu/arbi/matrix clock

Changes in v3:
- get CLK_DIVIDER_READ_ONLY tag back fro armcores
- add CLK_IGNORE_UNUSED tag for cs_dbg, pclk_dgb_pre and pclk_rkpwm

Changes in v2:
- get some clock ID back
- add CLK_IGNORE_UNUSED tag for aclk_strc and aclk_core in clk-rk3188.c
- add CLK_IGNORE_UNUSED tag for rk3288 dwc2

 drivers/clk/rockchip/clk-rk3188.c |  40 +--
 drivers/clk/rockchip/clk-rk3288.c | 146 +++---
 drivers/clk/rockchip/clk.c|   9 ---
 3 files changed, 93 insertions(+), 102 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3188.c 
b/drivers/clk/rockchip/clk-rk3188.c
index beed49c..1800cfe 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -257,9 +257,9 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
GATE(0, hclk_vdpu, aclk_vdpu, 0,
RK2928_CLKGATE_CON(3), 12, GFLAGS),
 
-   GATE(0, gpll_ddr, gpll, 0,
+   GATE(0, gpll_ddr, gpll, CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 7, GFLAGS),
-   COMPOSITE(0, ddrphy, mux_ddrphy_p, 0,
+   COMPOSITE(0, ddrphy, mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | 
CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
 
@@ -270,10 +270,10 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
RK2928_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, pclk_cpu, pclk_cpu_pre, 0,
RK2928_CLKGATE_CON(0), 5, GFLAGS),
-   GATE(0, hclk_cpu, hclk_cpu_pre, 0,
+   GATE(0, hclk_cpu, hclk_cpu_pre, CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 4, GFLAGS),
 
-   COMPOSITE(0, aclk_lcdc0_pre, mux_pll_src_cpll_gpll_p, 0,
+   COMPOSITE(0, aclk_lcdc0_pre, mux_pll_src_cpll_gpll_p, 
CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 0, GFLAGS),
COMPOSITE(0, aclk_lcdc1_pre, mux_pll_src_cpll_gpll_p, 0,
@@ -304,9 +304,9 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
 * the 480m are generated inside the usb block from these clocks,
 * but they are also a source for the hsicphy clock.
 */
-   GATE(SCLK_OTGPHY0, sclk_otgphy0, usb480m, 0,
+   GATE(SCLK_OTGPHY0, sclk_otgphy0, usb480m, CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 5, GFLAGS),
-   GATE(SCLK_OTGPHY1, sclk_otgphy1, usb480m, 0,
+   GATE(SCLK_OTGPHY1, sclk_otgphy1, usb480m, CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 6, GFLAGS),
 
COMPOSITE(0, mac_src, mux_mac_p, 0,
@@ -399,8 +399,8 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
 
/* aclk_cpu gates */
GATE(ACLK_DMA1, aclk_dma1, aclk_cpu, 0, RK2928_CLKGATE_CON(5), 0, 
GFLAGS),
-   GATE(0, aclk_intmem, aclk_cpu, 0, RK2928_CLKGATE_CON(4), 12, 
GFLAGS),
-   GATE(0, aclk_strc_sys, aclk_cpu, 0, RK2928_CLKGATE_CON(4), 10, 
GFLAGS),
+   GATE(0, aclk_intmem, aclk_cpu, CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 12, GFLAGS),
+   GATE(0, aclk_strc_sys, aclk_cpu, CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 10, GFLAGS),
 
/* hclk_cpu gates */
GATE(HCLK_ROM, hclk_rom, hclk_cpu, 0, RK2928_CLKGATE_CON(5), 6, 
GFLAGS),
@@ -416,8 +416,8 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
GATE(HCLK_RGA, hclk_rga, hclk_cpu, 0, RK2928_CLKGATE_CON(6), 10, 
GFLAGS),
 
/* hclk_peri gates */
-   GATE(0, hclk_peri_axi_matrix, hclk_peri, 0, RK2928_CLKGATE_CON(4), 
0, GFLAGS),
-   GATE(0, hclk_peri_ahb_arbi, hclk_peri, 0, RK2928_CLKGATE_CON(4), 6, 
GFLAGS),
+   GATE(0, hclk_peri_axi_matrix, hclk_peri, CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 0, GFLAGS),
+   GATE(0, hclk_peri_ahb_arbi, hclk_peri, CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 6, GFLAGS),
GATE(0, hclk_emem_peri, hclk_peri, 0, RK2928_CLKGATE_CON(4), 7, 
GFLAGS),
GATE(HCLK_EMAC, hclk_emac, hclk_peri, 0, RK2928_CLKGATE_CON(7), 0, 
GFLAGS),
GATE(HCLK_NANDC0, hclk_nandc0, hclk_peri, 0, RK2928_CLKGATE_CON(5), 
9, GFLAGS),
@@ -457,23 +457,23 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
GATE(0, pclk_ddrupctl, pclk_cpu, 0, RK2928_CLKGATE_CON(5), 7, 
GFLAGS),
GATE(0, pclk_ddrpubl, pclk_cpu, 0, RK2928_CLKGATE_CON(9), 6

[PATCH] usb: dwc2: add bus suspend/resume for dwc2

[Kever Yang]

This patch adds suspend/resume for dwc2 hcd controller.

Signed-off-by: Kever Yang 
---

 drivers/usb/dwc2/hcd.c | 74 ++
 1 file changed, 63 insertions(+), 11 deletions(-)

diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index fa49c72..df68449 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -1473,6 +1473,29 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, 
u16 windex)
}
 }
 
+static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
+{
+   u32 hprt0;
+
+   /* After clear the Stop PHY clock bit, we should wait for a moment
+* for PLL work stable with clock output.
+*/
+   writel(0, hsotg->regs + PCGCTL);
+   usleep_range(2000, 4000);
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   hprt0 |= HPRT0_RES;
+   writel(hprt0, hsotg->regs + HPRT0);
+   hprt0 &= ~HPRT0_SUSP;
+   /* according to USB2.0 Spec 7.1.7.7, the host most send the resume
+* signal for at least 20ms
+*/
+   usleep_range(2, 25000);
+
+   hprt0 &= ~HPRT0_RES;
+   writel(hprt0, hsotg->regs + HPRT0);
+}
+
 /* Handles hub class-specific requests */
 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
u16 wvalue, u16 windex, char *buf, u16 wlength)
@@ -1518,17 +1541,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg 
*hsotg, u16 typereq,
case USB_PORT_FEAT_SUSPEND:
dev_dbg(hsotg->dev,
"ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
-   writel(0, hsotg->regs + PCGCTL);
-   usleep_range(2, 4);
-
-   hprt0 = dwc2_read_hprt0(hsotg);
-   hprt0 |= HPRT0_RES;
-   writel(hprt0, hsotg->regs + HPRT0);
-   hprt0 &= ~HPRT0_SUSP;
-   usleep_range(10, 15);
-
-   hprt0 &= ~HPRT0_RES;
-   writel(hprt0, hsotg->regs + HPRT0);
+   dwc2_port_resume(hsotg);
break;
 
case USB_PORT_FEAT_POWER:
@@ -2301,6 +2314,42 @@ static void _dwc2_hcd_stop(struct usb_hcd *hcd)
usleep_range(1000, 3000);
 }
 
+static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (hsotg->op_state != OTG_STATE_B_HOST)
+   return 0;
+
+   if (hsotg->lx_state != DWC2_L0)
+   return 0;
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   if (hprt0 & HPRT0_CONNSTS)
+   dwc2_port_suspend(hsotg, 1);
+
+   return 0;
+}
+
+static int _dwc2_hcd_resume(struct usb_hcd *hcd)
+{
+   struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
+   u32 hprt0;
+
+   if (hsotg->op_state != OTG_STATE_B_HOST)
+   return 0;
+
+   if (hsotg->lx_state != DWC2_L2)
+   return 0;
+
+   hprt0 = dwc2_read_hprt0(hsotg);
+   if ((hprt0 | HPRT0_CONNSTS) && (hprt0 | HPRT0_SUSP))
+   dwc2_port_resume(hsotg);
+
+   return 0;
+}
+
 /* Returns the current frame number */
 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
 {
@@ -2671,6 +2720,9 @@ static struct hc_driver dwc2_hc_driver = {
.hub_status_data = _dwc2_hcd_hub_status_data,
.hub_control = _dwc2_hcd_hub_control,
.clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
+
+   .bus_suspend = _dwc2_hcd_suspend,
+   .bus_resume = _dwc2_hcd_resume,
 };
 
 /*
-- 
1.9.1

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[PATCH] clk: rockchip: change hierarchy for some clocks

[Kever Yang]

This patch change the hierarchy for some clocks, to met the following
bus hierarchy:
hclk_usb_peri is bus clock for
|- hclk_otg0,
|- hclk_host0,
|- hclk_host1,
|- hclk_hsic

hclk_emem is bus clock for
|- hclk_nandc0
|- hclk_nandc1

hclk_mem is bus clock for
|- hclk_sdmmc
|- hclk_sdio0
|- hclk_sdio1
|- hclk_emmc

Signed-off-by: Kever Yang 
---

 drivers/clk/rockchip/clk-rk3288.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 7a0741d..e1106ad 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -652,21 +652,21 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
 
/* hclk_peri gates */
GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(6), 0, GFLAGS),
-   GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 4, GFLAGS),
-   GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, 
RK3288_CLKGATE_CON(7), 6, GFLAGS),
-   GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 7, GFLAGS),
-   GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, 
GFLAGS),
+   GATE(HCLK_OTG0, "hclk_otg0", "hclk_usb_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 4, GFLAGS),
+   GATE(HCLK_USBHOST0, "hclk_host0", "hclk_usb_peri", 0, 
RK3288_CLKGATE_CON(7), 6, GFLAGS),
+   GATE(HCLK_USBHOST1, "hclk_host1", "hclk_usb_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 7, GFLAGS),
+   GATE(HCLK_HSIC, "hclk_hsic", "hclk_usb_peri", 0, RK3288_CLKGATE_CON(7), 
8, GFLAGS),
GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 9, GFLAGS),
GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 10, GFLAGS),
GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 12, GFLAGS),
GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 13, GFLAGS),
-   GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 
14, GFLAGS),
-   GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 
15, GFLAGS),
+   GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_emem", 0, RK3288_CLKGATE_CON(7), 
14, GFLAGS),
+   GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_emem", 0, RK3288_CLKGATE_CON(7), 
15, GFLAGS),
GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, 
GFLAGS),
-   GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 
3, GFLAGS),
-   GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 
4, GFLAGS),
-   GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 
5, GFLAGS),
-   GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, 
GFLAGS),
+   GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_mem", 0, RK3288_CLKGATE_CON(8), 3, 
GFLAGS),
+   GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_mem", 0, RK3288_CLKGATE_CON(8), 4, 
GFLAGS),
+   GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_mem", 0, RK3288_CLKGATE_CON(8), 5, 
GFLAGS),
+   GATE(HCLK_EMMC, "hclk_emmc", "hclk_mem", 0, RK3288_CLKGATE_CON(8), 6, 
GFLAGS),
GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 
7, GFLAGS),
GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, 
GFLAGS),
 
-- 
1.9.1

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[PATCH] clk: rockchip: change hierarchy for some clocks

[Kever Yang]

This patch change the hierarchy for some clocks, to met the following
bus hierarchy:
hclk_usb_peri is bus clock for
|- hclk_otg0,
|- hclk_host0,
|- hclk_host1,
|- hclk_hsic

hclk_emem is bus clock for
|- hclk_nandc0
|- hclk_nandc1

hclk_mem is bus clock for
|- hclk_sdmmc
|- hclk_sdio0
|- hclk_sdio1
|- hclk_emmc

Signed-off-by: Kever Yang kever.y...@rock-chips.com
---

 drivers/clk/rockchip/clk-rk3288.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c 
b/drivers/clk/rockchip/clk-rk3288.c
index 7a0741d..e1106ad 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -652,21 +652,21 @@ static struct rockchip_clk_branch rk3288_clk_branches[] 
__initdata = {
 
/* hclk_peri gates */
GATE(0, hclk_peri_matrix, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(6), 0, GFLAGS),
-   GATE(HCLK_OTG0, hclk_otg0, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 4, GFLAGS),
-   GATE(HCLK_USBHOST0, hclk_host0, hclk_peri, 0, 
RK3288_CLKGATE_CON(7), 6, GFLAGS),
-   GATE(HCLK_USBHOST1, hclk_host1, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 7, GFLAGS),
-   GATE(HCLK_HSIC, hclk_hsic, hclk_peri, 0, RK3288_CLKGATE_CON(7), 8, 
GFLAGS),
+   GATE(HCLK_OTG0, hclk_otg0, hclk_usb_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 4, GFLAGS),
+   GATE(HCLK_USBHOST0, hclk_host0, hclk_usb_peri, 0, 
RK3288_CLKGATE_CON(7), 6, GFLAGS),
+   GATE(HCLK_USBHOST1, hclk_host1, hclk_usb_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 7, GFLAGS),
+   GATE(HCLK_HSIC, hclk_hsic, hclk_usb_peri, 0, RK3288_CLKGATE_CON(7), 
8, GFLAGS),
GATE(0, hclk_usb_peri, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 9, GFLAGS),
GATE(0, hclk_peri_ahb_arbi, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 10, GFLAGS),
GATE(0, hclk_emem, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 12, GFLAGS),
GATE(0, hclk_mem, hclk_peri, CLK_IGNORE_UNUSED, 
RK3288_CLKGATE_CON(7), 13, GFLAGS),
-   GATE(HCLK_NANDC0, hclk_nandc0, hclk_peri, 0, RK3288_CLKGATE_CON(7), 
14, GFLAGS),
-   GATE(HCLK_NANDC1, hclk_nandc1, hclk_peri, 0, RK3288_CLKGATE_CON(7), 
15, GFLAGS),
+   GATE(HCLK_NANDC0, hclk_nandc0, hclk_emem, 0, RK3288_CLKGATE_CON(7), 
14, GFLAGS),
+   GATE(HCLK_NANDC1, hclk_nandc1, hclk_emem, 0, RK3288_CLKGATE_CON(7), 
15, GFLAGS),
GATE(HCLK_TSP, hclk_tsp, hclk_peri, 0, RK3288_CLKGATE_CON(8), 8, 
GFLAGS),
-   GATE(HCLK_SDMMC, hclk_sdmmc, hclk_peri, 0, RK3288_CLKGATE_CON(8), 
3, GFLAGS),
-   GATE(HCLK_SDIO0, hclk_sdio0, hclk_peri, 0, RK3288_CLKGATE_CON(8), 
4, GFLAGS),
-   GATE(HCLK_SDIO1, hclk_sdio1, hclk_peri, 0, RK3288_CLKGATE_CON(8), 
5, GFLAGS),
-   GATE(HCLK_EMMC, hclk_emmc, hclk_peri, 0, RK3288_CLKGATE_CON(8), 6, 
GFLAGS),
+   GATE(HCLK_SDMMC, hclk_sdmmc, hclk_mem, 0, RK3288_CLKGATE_CON(8), 3, 
GFLAGS),
+   GATE(HCLK_SDIO0, hclk_sdio0, hclk_mem, 0, RK3288_CLKGATE_CON(8), 4, 
GFLAGS),
+   GATE(HCLK_SDIO1, hclk_sdio1, hclk_mem, 0, RK3288_CLKGATE_CON(8), 5, 
GFLAGS),
+   GATE(HCLK_EMMC, hclk_emmc, hclk_mem, 0, RK3288_CLKGATE_CON(8), 6, 
GFLAGS),
GATE(HCLK_HSADC, hclk_hsadc, hclk_peri, 0, RK3288_CLKGATE_CON(8), 
7, GFLAGS),
GATE(0, pmu_hclk_otg0, hclk_peri, 0, RK3288_CLKGATE_CON(7), 5, 
GFLAGS),
 
-- 
1.9.1

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