[PATCH v5 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
v5:
* Fix copy/paste error when killing qcom_ipq806x_sata_delay_us
v4:
* removed qcom_ipq806x_sata_delay_us as it was only used one
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so phy_provider_register is last
v2:
* dropped unused dev pointer in struct qcom_ipq806x_sata_phy
* remove unnecessary reg initializaiton
* Removed unneeded error message
* Added remove function to disable the clock
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 206
3 files changed, 214 insertions(+)
create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..b7b6bce 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,11 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_QCOM_IPQ806X_SATA
+ tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
+ depends on ARCH_QCOM
+ depends on HAS_IOMEM
+ depends on OF
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d950317 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
b/drivers/phy/phy-qcom-ipq806x-sata.c
new file mode 100644
index 000..0716aa2
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct qcom_ipq806x_sata_phy {
+ void __iomem *mmio;
+ struct clk *cfg_clk;
+};
+
+#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
+
+#define SATA_PHY_P0_PARAM0 0x200
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+
+#define SATA_PHY_P0_PARAM1 0x204
+#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+
+#define SATA_PHY_P0_PARAM2 0x208
+#define SATA_PHY_P0_PARAM2_RX_EQ(x)__set(x, 20, 18)
+#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
+
+#define SATA_PHY_P0_PARAM3 0x20C
+#define SATA_PHY_SSC_EN0x8
+#define SATA_PHY_P0_PARAM4 0x210
+#define SATA_PHY_REF_SSP_EN0x2
+#define SATA_PHY_RESET 0x1
+
+static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
+{
+ struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
+ u32 reg;
+
+ /* Setting SSC_EN to 1 */
+ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3);
+ reg = reg | SATA_PHY_SSC_EN;
+ writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
+
+ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) &
+ ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK);
+ reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf);
+ writel_relaxed(reg, phy->mmio
[PATCH v4 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
v4:
* removed qcom_ipq806x_sata_delay_us as it was only used one
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so phy_provider_register is last
v2:
* dropped unused dev pointer in struct qcom_ipq806x_sata_phy
* remove unnecessary reg initializaiton
* Removed unneeded error message
* Added remove function to disable the clock
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 206
3 files changed, 214 insertions(+)
create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..b7b6bce 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,11 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_QCOM_IPQ806X_SATA
+ tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
+ depends on ARCH_QCOM
+ depends on HAS_IOMEM
+ depends on OF
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d950317 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
b/drivers/phy/phy-qcom-ipq806x-sata.c
new file mode 100644
index 000..f58ab6d
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct qcom_ipq806x_sata_phy {
+ void __iomem *mmio;
+ struct clk *cfg_clk;
+};
+
+#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
+
+#define SATA_PHY_P0_PARAM0 0x200
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+
+#define SATA_PHY_P0_PARAM1 0x204
+#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+
+#define SATA_PHY_P0_PARAM2 0x208
+#define SATA_PHY_P0_PARAM2_RX_EQ(x)__set(x, 20, 18)
+#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
+
+#define SATA_PHY_P0_PARAM3 0x20C
+#define SATA_PHY_SSC_EN0x8
+#define SATA_PHY_P0_PARAM4 0x210
+#define SATA_PHY_REF_SSP_EN0x2
+#define SATA_PHY_RESET 0x1
+
+static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
+{
+ struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
+ u32 reg;
+
+ /* Setting SSC_EN to 1 */
+ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3);
+ reg = reg | SATA_PHY_SSC_EN;
+ writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
+
+ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) &
+ ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK);
+ reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf);
+ writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0);
+
+ reg = readl_re
Re: [PATCH v2 2/3] ata: Add Qualcomm ARM SoC AHCI SATA host controller driver
On Jun 17, 2014, at 7:25 AM, Bartlomiej Zolnierkiewicz
wrote:
>
> Hi,
>
> On Friday, June 13, 2014 11:16:03 AM Kumar Gala wrote:
>> Add support for the Qualcomm AHCI SATA controller that exists on several
>> SoC and specifically the IPQ806x family of chips. The IPQ806x SATA support
>> requires the associated IPQ806x SATA PHY Driver to be enabled as well.
>>
>> Signed-off-by: Kumar Gala
>> ---
>> v2:
>> * Fixed MODULE_LICENSE to be GPL v2
>>
>> drivers/ata/Kconfig | 10 ++
>> drivers/ata/Makefile| 1 +
>> drivers/ata/ahci_qcom.c | 86
>> +
>> 3 files changed, 97 insertions(+)
>> create mode 100644 drivers/ata/ahci_qcom.c
>>
>> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
>> index 7671dba..aa88648 100644
>> --- a/drivers/ata/Kconfig
>> +++ b/drivers/ata/Kconfig
>> @@ -132,6 +132,16 @@ config AHCI_MVEBU
>>
>>If unsure, say N.
>>
>> +config AHCI_QCOM
>> +tristate "Qualcomm AHCI SATA support"
>> +depends on ARCH_QCOM
>> +help
>> + This option enables support for AHCI SATA controller
>> + integrated into Qualcomm ARM SoC chipsets. For more
>> + information please refer to http://www.qualcomm.com/chipsets.
>> +
>> + If unsure, say N.
>> +
>> config AHCI_SUNXI
>> tristate "Allwinner sunxi AHCI SATA support"
>> depends on ARCH_SUNXI
>> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
>> index 5a02aee..15401e9 100644
>> --- a/drivers/ata/Makefile
>> +++ b/drivers/ata/Makefile
>> @@ -13,6 +13,7 @@ obj-$(CONFIG_SATA_HIGHBANK)+= sata_highbank.o
>> libahci.o
>> obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
>> obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o
>> libahci_platform.o
>> obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
>> +obj-$(CONFIG_AHCI_QCOM) += ahci_qcom.o libahci.o
>> libahci_platform.o
>> obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
>> obj-$(CONFIG_AHCI_ST)+= ahci_st.o libahci.o
>> libahci_platform.o
>> obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o libahci.o libahci_platform.o
>> diff --git a/drivers/ata/ahci_qcom.c b/drivers/ata/ahci_qcom.c
>> new file mode 100644
>> index 000..bfb7a77
>> --- /dev/null
>> +++ b/drivers/ata/ahci_qcom.c
>> @@ -0,0 +1,86 @@
>> +/*
>> + * Qualcomm ARM SoC AHCI SATA platform driver
>> + *
>> + * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
>> + *
>> + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include "ahci.h"
>> +
>> +static const struct ata_port_info qcom_ahci_port_info = {
>> +.flags = AHCI_FLAG_COMMON,
>> +.pio_mask = ATA_PIO4,
>> +.udma_mask = ATA_UDMA6,
>> +.port_ops = _platform_ops,
>> +};
>> +
>> +static int qcom_ahci_probe(struct platform_device *pdev)
>> +{
>> +struct ahci_host_priv *hpriv;
>> +struct clk *rxoob_clk;
>> +int rc;
>> +
>> +hpriv = ahci_platform_get_resources(pdev);
>> +if (IS_ERR(hpriv))
>> +return PTR_ERR(hpriv);
>> +
>> +/* Try and set the rxoob clk to 100Mhz */
>> +rxoob_clk = of_clk_get_by_name(pdev->dev.of_node, "rxoob");
>> +if (IS_ERR(rxoob_clk))
>> +return PTR_ERR(rxoob_clk);
>> +
>> +rc = clk_set_rate(rxoob_clk, 1);
>
> Shouldn't the clk_prepare_enable() be called first?
I don’t believe there is any requirement for clk_prepare_enable to be called
first.
>
>> +if (rc)
>> +return rc;
>
> of_clk_get_by_name() gets an extra reference on the clock so clk_pu
[PATCH v4 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
v4:
* removed qcom_ipq806x_sata_delay_us as it was only used one
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so phy_provider_register is last
v2:
* dropped unused dev pointer in struct qcom_ipq806x_sata_phy
* remove unnecessary reg initializaiton
* Removed unneeded error message
* Added remove function to disable the clock
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 206
3 files changed, 214 insertions(+)
create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..b7b6bce 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,11 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_QCOM_IPQ806X_SATA
+ tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
+ depends on ARCH_QCOM
+ depends on HAS_IOMEM
+ depends on OF
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d950317 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
b/drivers/phy/phy-qcom-ipq806x-sata.c
new file mode 100644
index 000..f58ab6d
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct qcom_ipq806x_sata_phy {
+ void __iomem *mmio;
+ struct clk *cfg_clk;
+};
+
+#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
+
+#define SATA_PHY_P0_PARAM0 0x200
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+
+#define SATA_PHY_P0_PARAM1 0x204
+#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+
+#define SATA_PHY_P0_PARAM2 0x208
+#define SATA_PHY_P0_PARAM2_RX_EQ(x)__set(x, 20, 18)
+#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
+
+#define SATA_PHY_P0_PARAM3 0x20C
+#define SATA_PHY_SSC_EN0x8
+#define SATA_PHY_P0_PARAM4 0x210
+#define SATA_PHY_REF_SSP_EN0x2
+#define SATA_PHY_RESET 0x1
+
+static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
+{
+ struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
+ u32 reg;
+
+ /* Setting SSC_EN to 1 */
+ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3);
+ reg = reg | SATA_PHY_SSC_EN;
+ writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
+
+ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) &
+ ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK);
+ reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf);
+ writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0);
+
+ reg = readl_re
[PATCH v4 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v4:
* removed qcom_ipq806x_sata_delay_us as it was only used one
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so phy_provider_register is last
v2:
* dropped unused dev pointer in struct qcom_ipq806x_sata_phy
* remove unnecessary reg initializaiton
* Removed unneeded error message
* Added remove function to disable the clock
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 206
3 files changed, 214 insertions(+)
create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..b7b6bce 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,11 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_QCOM_IPQ806X_SATA
+ tristate Qualcomm IPQ806x SATA SerDes/PHY driver
+ depends on ARCH_QCOM
+ depends on HAS_IOMEM
+ depends on OF
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d950317 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
b/drivers/phy/phy-qcom-ipq806x-sata.c
new file mode 100644
index 000..f58ab6d
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/time.h
+#include linux/delay.h
+#include linux/clk.h
+#include linux/slab.h
+#include linux/platform_device.h
+#include linux/phy/phy.h
+
+struct qcom_ipq806x_sata_phy {
+ void __iomem *mmio;
+ struct clk *cfg_clk;
+};
+
+#define __set(v, a, b) (((v) (b)) GENMASK(a, b))
+
+#define SATA_PHY_P0_PARAM0 0x200
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+
+#define SATA_PHY_P0_PARAM1 0x204
+#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+
+#define SATA_PHY_P0_PARAM2 0x208
+#define SATA_PHY_P0_PARAM2_RX_EQ(x)__set(x, 20, 18)
+#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
+
+#define SATA_PHY_P0_PARAM3 0x20C
+#define SATA_PHY_SSC_EN0x8
+#define SATA_PHY_P0_PARAM4 0x210
+#define SATA_PHY_REF_SSP_EN0x2
+#define SATA_PHY_RESET 0x1
+
+static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
+{
+ struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
+ u32 reg;
+
+ /* Setting SSC_EN to 1 */
+ reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM3);
+ reg = reg | SATA_PHY_SSC_EN;
+ writel_relaxed(reg, phy-mmio + SATA_PHY_P0_PARAM3);
+
+ reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM0)
+ ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK);
+ reg
Re: [PATCH v2 2/3] ata: Add Qualcomm ARM SoC AHCI SATA host controller driver
On Jun 17, 2014, at 7:25 AM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
Hi,
On Friday, June 13, 2014 11:16:03 AM Kumar Gala wrote:
Add support for the Qualcomm AHCI SATA controller that exists on several
SoC and specifically the IPQ806x family of chips. The IPQ806x SATA support
requires the associated IPQ806x SATA PHY Driver to be enabled as well.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v2:
* Fixed MODULE_LICENSE to be GPL v2
drivers/ata/Kconfig | 10 ++
drivers/ata/Makefile| 1 +
drivers/ata/ahci_qcom.c | 86
+
3 files changed, 97 insertions(+)
create mode 100644 drivers/ata/ahci_qcom.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 7671dba..aa88648 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -132,6 +132,16 @@ config AHCI_MVEBU
If unsure, say N.
+config AHCI_QCOM
+tristate Qualcomm AHCI SATA support
+depends on ARCH_QCOM
+help
+ This option enables support for AHCI SATA controller
+ integrated into Qualcomm ARM SoC chipsets. For more
+ information please refer to http://www.qualcomm.com/chipsets.
+
+ If unsure, say N.
+
config AHCI_SUNXI
tristate Allwinner sunxi AHCI SATA support
depends on ARCH_SUNXI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 5a02aee..15401e9 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SATA_HIGHBANK)+= sata_highbank.o
libahci.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o
libahci_platform.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_QCOM) += ahci_qcom.o libahci.o
libahci_platform.o
obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_ST)+= ahci_st.o libahci.o
libahci_platform.o
obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_qcom.c b/drivers/ata/ahci_qcom.c
new file mode 100644
index 000..bfb7a77
--- /dev/null
+++ b/drivers/ata/ahci_qcom.c
@@ -0,0 +1,86 @@
+/*
+ * Qualcomm ARM SoC AHCI SATA platform driver
+ *
+ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
+ *
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/pm.h
+#include linux/device.h
+#include linux/platform_device.h
+#include linux/libata.h
+#include linux/ahci_platform.h
+#include ahci.h
+
+static const struct ata_port_info qcom_ahci_port_info = {
+.flags = AHCI_FLAG_COMMON,
+.pio_mask = ATA_PIO4,
+.udma_mask = ATA_UDMA6,
+.port_ops = ahci_platform_ops,
+};
+
+static int qcom_ahci_probe(struct platform_device *pdev)
+{
+struct ahci_host_priv *hpriv;
+struct clk *rxoob_clk;
+int rc;
+
+hpriv = ahci_platform_get_resources(pdev);
+if (IS_ERR(hpriv))
+return PTR_ERR(hpriv);
+
+/* Try and set the rxoob clk to 100Mhz */
+rxoob_clk = of_clk_get_by_name(pdev-dev.of_node, rxoob);
+if (IS_ERR(rxoob_clk))
+return PTR_ERR(rxoob_clk);
+
+rc = clk_set_rate(rxoob_clk, 1);
Shouldn't the clk_prepare_enable() be called first?
I don’t believe there is any requirement for clk_prepare_enable to be called
first.
+if (rc)
+return rc;
of_clk_get_by_name() gets an extra reference on the clock so clk_put()
should be called on failure.
will fix.
+rc = ahci_platform_enable_resources(hpriv);
+if (rc)
+return rc;
+
+rc = ahci_platform_init_host(pdev, hpriv, qcom_ahci_port_info, 0, 0);
+if (rc)
+goto disable_resources;
+
+return 0;
+disable_resources:
+ahci_platform_disable_resources(hpriv);
+return rc;
+}
+
+static const struct of_device_id qcom_ahci_of_match[] = {
+{ .compatible = qcom,msm-ahci, },
+{},
+};
+MODULE_DEVICE_TABLE(of, qcom_ahci_of_match);
+
+static struct platform_driver qcom_ahci_driver = {
+.probe = qcom_ahci_probe,
+.remove = ata_platform_remove_one,
+.driver = {
+.name = qcom_ahci_qcom,
+.owner = THIS_MODULE,
+.of_match_table = qcom_ahci_of_match
[PATCH v4 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v4:
* removed qcom_ipq806x_sata_delay_us as it was only used one
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so phy_provider_register is last
v2:
* dropped unused dev pointer in struct qcom_ipq806x_sata_phy
* remove unnecessary reg initializaiton
* Removed unneeded error message
* Added remove function to disable the clock
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 206
3 files changed, 214 insertions(+)
create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..b7b6bce 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,11 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_QCOM_IPQ806X_SATA
+ tristate Qualcomm IPQ806x SATA SerDes/PHY driver
+ depends on ARCH_QCOM
+ depends on HAS_IOMEM
+ depends on OF
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d950317 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
b/drivers/phy/phy-qcom-ipq806x-sata.c
new file mode 100644
index 000..f58ab6d
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/time.h
+#include linux/delay.h
+#include linux/clk.h
+#include linux/slab.h
+#include linux/platform_device.h
+#include linux/phy/phy.h
+
+struct qcom_ipq806x_sata_phy {
+ void __iomem *mmio;
+ struct clk *cfg_clk;
+};
+
+#define __set(v, a, b) (((v) (b)) GENMASK(a, b))
+
+#define SATA_PHY_P0_PARAM0 0x200
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+
+#define SATA_PHY_P0_PARAM1 0x204
+#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+
+#define SATA_PHY_P0_PARAM2 0x208
+#define SATA_PHY_P0_PARAM2_RX_EQ(x)__set(x, 20, 18)
+#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
+
+#define SATA_PHY_P0_PARAM3 0x20C
+#define SATA_PHY_SSC_EN0x8
+#define SATA_PHY_P0_PARAM4 0x210
+#define SATA_PHY_REF_SSP_EN0x2
+#define SATA_PHY_RESET 0x1
+
+static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
+{
+ struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
+ u32 reg;
+
+ /* Setting SSC_EN to 1 */
+ reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM3);
+ reg = reg | SATA_PHY_SSC_EN;
+ writel_relaxed(reg, phy-mmio + SATA_PHY_P0_PARAM3);
+
+ reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM0)
+ ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK);
+ reg
[PATCH v5 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v5:
* Fix copy/paste error when killing qcom_ipq806x_sata_delay_us
v4:
* removed qcom_ipq806x_sata_delay_us as it was only used one
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so phy_provider_register is last
v2:
* dropped unused dev pointer in struct qcom_ipq806x_sata_phy
* remove unnecessary reg initializaiton
* Removed unneeded error message
* Added remove function to disable the clock
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 206
3 files changed, 214 insertions(+)
create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..b7b6bce 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,11 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_QCOM_IPQ806X_SATA
+ tristate Qualcomm IPQ806x SATA SerDes/PHY driver
+ depends on ARCH_QCOM
+ depends on HAS_IOMEM
+ depends on OF
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d950317 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
b/drivers/phy/phy-qcom-ipq806x-sata.c
new file mode 100644
index 000..0716aa2
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/time.h
+#include linux/delay.h
+#include linux/clk.h
+#include linux/slab.h
+#include linux/platform_device.h
+#include linux/phy/phy.h
+
+struct qcom_ipq806x_sata_phy {
+ void __iomem *mmio;
+ struct clk *cfg_clk;
+};
+
+#define __set(v, a, b) (((v) (b)) GENMASK(a, b))
+
+#define SATA_PHY_P0_PARAM0 0x200
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+
+#define SATA_PHY_P0_PARAM1 0x204
+#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+
+#define SATA_PHY_P0_PARAM2 0x208
+#define SATA_PHY_P0_PARAM2_RX_EQ(x)__set(x, 20, 18)
+#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
+
+#define SATA_PHY_P0_PARAM3 0x20C
+#define SATA_PHY_SSC_EN0x8
+#define SATA_PHY_P0_PARAM4 0x210
+#define SATA_PHY_REF_SSP_EN0x2
+#define SATA_PHY_RESET 0x1
+
+static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
+{
+ struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
+ u32 reg;
+
+ /* Setting SSC_EN to 1 */
+ reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM3);
+ reg = reg | SATA_PHY_SSC_EN;
+ writel_relaxed(reg, phy-mmio + SATA_PHY_P0_PARAM3);
+
+ reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM0)
+ ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK
[PATCH v3 2/3] ata: Add Qualcomm ARM SoC AHCI SATA host controller driver
Add support for the Qualcomm AHCI SATA controller that exists on several
SoC and specifically the IPQ806x family of chips. The IPQ806x SATA support
requires the associated IPQ806x SATA PHY Driver to be enabled as well.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v3:
* Added comment about suspend/resume not supported
* Fixup ahci_platform_init_host for upstream change to interface
* cleanup error handling of rxoob clk, moved to devm_clk_get/put
v2:
* Fixed MODULE_LICENSE to be GPL v2
drivers/ata/Kconfig | 10 ++
drivers/ata/Makefile| 1 +
drivers/ata/ahci_qcom.c | 90 +
3 files changed, 101 insertions(+)
create mode 100644 drivers/ata/ahci_qcom.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 7671dba..aa88648 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -132,6 +132,16 @@ config AHCI_MVEBU
If unsure, say N.
+config AHCI_QCOM
+ tristate Qualcomm AHCI SATA support
+ depends on ARCH_QCOM
+ help
+ This option enables support for AHCI SATA controller
+ integrated into Qualcomm ARM SoC chipsets. For more
+ information please refer to http://www.qualcomm.com/chipsets.
+
+ If unsure, say N.
+
config AHCI_SUNXI
tristate Allwinner sunxi AHCI SATA support
depends on ARCH_SUNXI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 5a02aee..15401e9 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_QCOM)+= ahci_qcom.o libahci.o
libahci_platform.o
obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_qcom.c b/drivers/ata/ahci_qcom.c
new file mode 100644
index 000..412e878
--- /dev/null
+++ b/drivers/ata/ahci_qcom.c
@@ -0,0 +1,90 @@
+/*
+ * Qualcomm ARM SoC AHCI SATA platform driver
+ *
+ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
+ *
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/pm.h
+#include linux/device.h
+#include linux/platform_device.h
+#include linux/libata.h
+#include linux/ahci_platform.h
+#include ahci.h
+
+static const struct ata_port_info qcom_ahci_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = ahci_platform_ops,
+};
+
+static int qcom_ahci_probe(struct platform_device *pdev)
+{
+ struct ahci_host_priv *hpriv;
+ struct clk *rxoob_clk;
+ int rc;
+
+ hpriv = ahci_platform_get_resources(pdev);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
+
+ /* Try and set the rxoob clk to 100Mhz */
+ rxoob_clk = devm_clk_get(pdev-dev, rxoob);
+ if (IS_ERR(rxoob_clk))
+ return PTR_ERR(rxoob_clk);
+
+ rc = clk_set_rate(rxoob_clk, 1);
+ if (rc)
+ return rc;
+
+ devm_clk_put(pdev-dev, rxoob_clk);
+
+ rc = ahci_platform_enable_resources(hpriv);
+ if (rc)
+ return rc;
+
+ rc = ahci_platform_init_host(pdev, hpriv, qcom_ahci_port_info,
+0, 0, 0);
+ if (rc)
+ goto disable_resources;
+
+ return 0;
+disable_resources:
+ ahci_platform_disable_resources(hpriv);
+ return rc;
+}
+
+static const struct of_device_id qcom_ahci_of_match[] = {
+ { .compatible = qcom,msm-ahci, },
+ {},
+};
+MODULE_DEVICE_TABLE(of, qcom_ahci_of_match);
+
+static struct platform_driver qcom_ahci_driver = {
+ .probe = qcom_ahci_probe,
+ .remove = ata_platform_remove_one,
+ .driver = {
+ .name = qcom_ahci_qcom,
+ .owner = THIS_MODULE,
+ .of_match_table = qcom_ahci_of_match,
+ },
+ /* suspend/resume not currently supported */
+};
+module_platform_driver(qcom_ahci_driver);
+
+MODULE_DESCRIPTION(Qualcomm AHCI SATA platform driver
Re: [PATCH] tty: serial: msm: Fix section mismatch warning
On Jun 3, 2014, at 4:17 PM, Olof Johansson o...@lixom.net wrote: On Tue, Jun 3, 2014 at 2:14 PM, Greg KH gre...@linuxfoundation.org wrote: On Tue, Jun 03, 2014 at 02:04:43PM -0700, Olof Johansson wrote: On Tue, Jun 3, 2014 at 1:33 PM, Greg KH gre...@linuxfoundation.org wrote: On Tue, Jun 03, 2014 at 03:13:22PM -0500, Kumar Gala wrote: WARNING: drivers/tty/built-in.o(.data+0x3544): Section mismatch in reference from the variable msm_platform_driver to the function .init.text:msm_serial_probe() The variable msm_platform_driver references the function __init msm_serial_probe() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Where is this mismatch showing up at? 3.15-rc8, 3.16-rc1? Somewhere older or else? Linus' next branch, it was merged through arm-soc. I didn't notice it in time to fix it before we sent to Linus. :( Ok, do you want to take this patch then? I don't mind taking it through my tree, but it will have to wait until after 3.16-rc1 is out. It's up to you. I've got a handful of fixes we're queueing for the second batch of merges, and I can add it to there. -Olof Olof, Reminder to queue this up for fixes for 3.16 - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
On Jun 16, 2014, at 5:04 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Friday 13 June 2014 12:48 AM, Kumar Gala wrote:
>> Add a PHY driver for uses with AHCI based SATA controller driver on the
>> IPQ806x family of SoCs.
>>
>> Signed-off-by: Kumar Gala
>> ---
>> drivers/phy/Kconfig | 6 ++
>> drivers/phy/Makefile| 1 +
>> drivers/phy/phy-qcom-ipq806x-sata.c | 204
>>
>> 3 files changed, 211 insertions(+)
>> create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 16a2f06..52bfb93 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -178,4 +178,10 @@ config PHY_XGENE
>> help
>>This option enables support for APM X-Gene SoC multi-purpose PHY.
>>
>> +config PHY_QCOM_IPQ806X_SATA
>> +tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
>> +depends on ARCH_QCOM
>> +depends on OF
> depends on HAS_IOMEM?
will add
>> +select GENERIC_PHY
>> +
>> endmenu
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index b4f1d57..d950317 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
>> phy-exynos4x12-usb2.o
>> phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)+= phy-exynos5250-usb2.o
>> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
>> obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
>> +obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
>> diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
>> b/drivers/phy/phy-qcom-ipq806x-sata.c
>> new file mode 100644
>> index 000..fc57340
>> --- /dev/null
>> +++ b/drivers/phy/phy-qcom-ipq806x-sata.c
>> @@ -0,0 +1,204 @@
>> +/*
>> + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 and
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +struct qcom_ipq806x_sata_phy {
>> +struct device *dev;
>
> dev is not used anywhere. remove it.
already done in v2
>> +void __iomem *mmio;
>> +struct clk *cfg_clk;
>> +};
>> +
>> +#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
>> +
>> +#define SATA_PHY_P0_PARAM0 0x200
>> +#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x)__set(x, 17, 12)
>> +#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
>> +#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x)__set(x, 11, 6)
>> +#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
>> +#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x)__set(x, 5, 0)
>> +#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
>> +
>> +#define SATA_PHY_P0_PARAM1 0x204
>> +#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x)__set(x, 31, 21)
>> +#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
>> +#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASKGENMASK(20, 14)
>> +#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
>> +#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASKGENMASK(13, 7)
>> +#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
>> +#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASKGENMASK(6, 0)
>> +
>> +#define SATA_PHY_P0_PARAM2 0x208
>> +#define SATA_PHY_P0_PARAM2_RX_EQ(x) __set(x, 20, 18)
>> +#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
>> +
>> +#define SATA_PHY_P0_PARAM3 0x20C
>> +#define SATA_PHY_SSC_EN 0x8
>> +#define SATA_PHY_P0_PARAM4 0x210
>> +#define SATA_PHY_REF_SSP_EN 0x2
>> +#define SATA_PHY_RESET 0x1
>> +
>> +static inline void qcom_ipq806x_sata_d
[PATCH v3 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so phy_provider_register is last
v2:
* dropped unused dev pointer in struct qcom_ipq806x_sata_phy
* remove unnecessary reg initializaiton
* Removed unneeded error message
* Added remove function to disable the clock
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 211
3 files changed, 219 insertions(+)
create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..b7b6bce 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,11 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_QCOM_IPQ806X_SATA
+ tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
+ depends on ARCH_QCOM
+ depends on HAS_IOMEM
+ depends on OF
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d950317 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
b/drivers/phy/phy-qcom-ipq806x-sata.c
new file mode 100644
index 000..e931aee
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct qcom_ipq806x_sata_phy {
+ void __iomem *mmio;
+ struct clk *cfg_clk;
+};
+
+#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
+
+#define SATA_PHY_P0_PARAM0 0x200
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+
+#define SATA_PHY_P0_PARAM1 0x204
+#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+
+#define SATA_PHY_P0_PARAM2 0x208
+#define SATA_PHY_P0_PARAM2_RX_EQ(x)__set(x, 20, 18)
+#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
+
+#define SATA_PHY_P0_PARAM3 0x20C
+#define SATA_PHY_SSC_EN0x8
+#define SATA_PHY_P0_PARAM4 0x210
+#define SATA_PHY_REF_SSP_EN0x2
+#define SATA_PHY_RESET 0x1
+
+static inline void qcom_ipq806x_sata_delay_us(unsigned int delay)
+{
+ /* sleep for max. 50us more to combine processor wakeups */
+ usleep_range(delay, delay + 50);
+}
+
+static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
+{
+ struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
+ u32 reg;
+
+ /* Setting SSC_EN to 1 */
+ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3);
+ reg = reg | SATA_PHY_SSC_EN;
+ writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
+
+ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) &
+ ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK);
+ reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf)
[PATCH v3 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so phy_provider_register is last
v2:
* dropped unused dev pointer in struct qcom_ipq806x_sata_phy
* remove unnecessary reg initializaiton
* Removed unneeded error message
* Added remove function to disable the clock
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 211
3 files changed, 219 insertions(+)
create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..b7b6bce 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,11 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_QCOM_IPQ806X_SATA
+ tristate Qualcomm IPQ806x SATA SerDes/PHY driver
+ depends on ARCH_QCOM
+ depends on HAS_IOMEM
+ depends on OF
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d950317 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
b/drivers/phy/phy-qcom-ipq806x-sata.c
new file mode 100644
index 000..e931aee
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/time.h
+#include linux/delay.h
+#include linux/clk.h
+#include linux/slab.h
+#include linux/platform_device.h
+#include linux/phy/phy.h
+
+struct qcom_ipq806x_sata_phy {
+ void __iomem *mmio;
+ struct clk *cfg_clk;
+};
+
+#define __set(v, a, b) (((v) (b)) GENMASK(a, b))
+
+#define SATA_PHY_P0_PARAM0 0x200
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+
+#define SATA_PHY_P0_PARAM1 0x204
+#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+
+#define SATA_PHY_P0_PARAM2 0x208
+#define SATA_PHY_P0_PARAM2_RX_EQ(x)__set(x, 20, 18)
+#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
+
+#define SATA_PHY_P0_PARAM3 0x20C
+#define SATA_PHY_SSC_EN0x8
+#define SATA_PHY_P0_PARAM4 0x210
+#define SATA_PHY_REF_SSP_EN0x2
+#define SATA_PHY_RESET 0x1
+
+static inline void qcom_ipq806x_sata_delay_us(unsigned int delay)
+{
+ /* sleep for max. 50us more to combine processor wakeups */
+ usleep_range(delay, delay + 50);
+}
+
+static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
+{
+ struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
+ u32 reg;
+
+ /* Setting SSC_EN to 1 */
+ reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM3);
+ reg = reg | SATA_PHY_SSC_EN;
+ writel_relaxed(reg, phy-mmio + SATA_PHY_P0_PARAM3);
+
+ reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM0)
+ ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK
Re: [PATCH 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
On Jun 16, 2014, at 5:04 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
Hi,
On Friday 13 June 2014 12:48 AM, Kumar Gala wrote:
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/phy/Kconfig | 6 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 204
3 files changed, 211 insertions(+)
create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..52bfb93 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,10 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_QCOM_IPQ806X_SATA
+tristate Qualcomm IPQ806x SATA SerDes/PHY driver
+depends on ARCH_QCOM
+depends on OF
depends on HAS_IOMEM?
will add
+select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d950317 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)+= phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
b/drivers/phy/phy-qcom-ipq806x-sata.c
new file mode 100644
index 000..fc57340
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/time.h
+#include linux/delay.h
+#include linux/clk.h
+#include linux/slab.h
+#include linux/platform_device.h
+#include linux/phy/phy.h
+
+struct qcom_ipq806x_sata_phy {
+struct device *dev;
dev is not used anywhere. remove it.
already done in v2
+void __iomem *mmio;
+struct clk *cfg_clk;
+};
+
+#define __set(v, a, b) (((v) (b)) GENMASK(a, b))
+
+#define SATA_PHY_P0_PARAM0 0x200
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x)__set(x, 17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x)__set(x, 11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x)__set(x, 5, 0)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+
+#define SATA_PHY_P0_PARAM1 0x204
+#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x)__set(x, 31, 21)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASKGENMASK(20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASKGENMASK(13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASKGENMASK(6, 0)
+
+#define SATA_PHY_P0_PARAM2 0x208
+#define SATA_PHY_P0_PARAM2_RX_EQ(x) __set(x, 20, 18)
+#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
+
+#define SATA_PHY_P0_PARAM3 0x20C
+#define SATA_PHY_SSC_EN 0x8
+#define SATA_PHY_P0_PARAM4 0x210
+#define SATA_PHY_REF_SSP_EN 0x2
+#define SATA_PHY_RESET 0x1
+
+static inline void qcom_ipq806x_sata_delay_us(unsigned int delay)
+{
+/* sleep for max. 50us more to combine processor wakeups */
+usleep_range(delay, delay + 50);
+}
+
+static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
+{
+struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
+u32 reg = 0;
+
+/* Setting SSC_EN to 1 */
+reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM3);
Why readl_relaxed?
because there is no need for readl’s memory barriers here.
+reg = reg | SATA_PHY_SSC_EN;
+writel_relaxed(reg, phy-mmio + SATA_PHY_P0_PARAM3);
+
+reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM0)
+~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK
Re: [Patch v2 3/3] spi: qup: Add support for v1.1.1
On Jun 12, 2014, at 2:34 PM, Andy Gross wrote: > This patch adds support for v1.1.1 of the SPI QUP controller. > > Signed-off-by: Andy Gross > --- > .../devicetree/bindings/spi/qcom,spi-qup.txt |6 +++- > drivers/spi/spi-qup.c | 36 > 2 files changed, 27 insertions(+), 15 deletions(-) > > diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt > b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt > index bee6ff2..e2c88df 100644 > --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt > +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt > @@ -7,7 +7,11 @@ SPI in master mode supports up to 50MHz, up to four chip > selects, programmable > data path from 4 bits to 32 bits and numerous protocol variants. > > Required properties: > -- compatible: Should contain "qcom,spi-qup-v2.1.1" or > "qcom,spi-qup-v2.2.1" > +- compatible: Should contain: > + "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064. > + "qcom,spi-qup-v2.1.1" for 8974 and later > + "qcom,spi-qup-v2.2.1" for 8974 v2 and later. > + We should probably try to be a bit more clear about ipq/apq/msm here. > - reg:Should contain base register location and length > - interrupts: Interrupt number used by this controller - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
v2:
* dropped unused dev pointer in struct qcom_ipq806x_sata_phy
* remove unnecessary reg initializaiton
* Removed unneeded error message
* Added remove function to disable the clock
drivers/phy/Kconfig | 6 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 210
3 files changed, 217 insertions(+)
create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..52bfb93 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,10 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_QCOM_IPQ806X_SATA
+ tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
+ depends on ARCH_QCOM
+ depends on OF
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d950317 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
b/drivers/phy/phy-qcom-ipq806x-sata.c
new file mode 100644
index 000..f22b9a2
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct qcom_ipq806x_sata_phy {
+ void __iomem *mmio;
+ struct clk *cfg_clk;
+};
+
+#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
+
+#define SATA_PHY_P0_PARAM0 0x200
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+
+#define SATA_PHY_P0_PARAM1 0x204
+#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+
+#define SATA_PHY_P0_PARAM2 0x208
+#define SATA_PHY_P0_PARAM2_RX_EQ(x)__set(x, 20, 18)
+#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
+
+#define SATA_PHY_P0_PARAM3 0x20C
+#define SATA_PHY_SSC_EN0x8
+#define SATA_PHY_P0_PARAM4 0x210
+#define SATA_PHY_REF_SSP_EN0x2
+#define SATA_PHY_RESET 0x1
+
+static inline void qcom_ipq806x_sata_delay_us(unsigned int delay)
+{
+ /* sleep for max. 50us more to combine processor wakeups */
+ usleep_range(delay, delay + 50);
+}
+
+static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
+{
+ struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
+ u32 reg;
+
+ /* Setting SSC_EN to 1 */
+ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3);
+ reg = reg | SATA_PHY_SSC_EN;
+ writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
+
+ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) &
+ ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK);
+ reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf);
+ writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0);
+
+ reg = readl_re
[PATCH v2 2/3] ata: Add Qualcomm ARM SoC AHCI SATA host controller driver
Add support for the Qualcomm AHCI SATA controller that exists on several
SoC and specifically the IPQ806x family of chips. The IPQ806x SATA support
requires the associated IPQ806x SATA PHY Driver to be enabled as well.
Signed-off-by: Kumar Gala
---
v2:
* Fixed MODULE_LICENSE to be GPL v2
drivers/ata/Kconfig | 10 ++
drivers/ata/Makefile| 1 +
drivers/ata/ahci_qcom.c | 86 +
3 files changed, 97 insertions(+)
create mode 100644 drivers/ata/ahci_qcom.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 7671dba..aa88648 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -132,6 +132,16 @@ config AHCI_MVEBU
If unsure, say N.
+config AHCI_QCOM
+ tristate "Qualcomm AHCI SATA support"
+ depends on ARCH_QCOM
+ help
+ This option enables support for AHCI SATA controller
+ integrated into Qualcomm ARM SoC chipsets. For more
+ information please refer to http://www.qualcomm.com/chipsets.
+
+ If unsure, say N.
+
config AHCI_SUNXI
tristate "Allwinner sunxi AHCI SATA support"
depends on ARCH_SUNXI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 5a02aee..15401e9 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_QCOM)+= ahci_qcom.o libahci.o
libahci_platform.o
obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_qcom.c b/drivers/ata/ahci_qcom.c
new file mode 100644
index 000..bfb7a77
--- /dev/null
+++ b/drivers/ata/ahci_qcom.c
@@ -0,0 +1,86 @@
+/*
+ * Qualcomm ARM SoC AHCI SATA platform driver
+ *
+ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
+ *
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "ahci.h"
+
+static const struct ata_port_info qcom_ahci_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = _platform_ops,
+};
+
+static int qcom_ahci_probe(struct platform_device *pdev)
+{
+ struct ahci_host_priv *hpriv;
+ struct clk *rxoob_clk;
+ int rc;
+
+ hpriv = ahci_platform_get_resources(pdev);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
+
+ /* Try and set the rxoob clk to 100Mhz */
+ rxoob_clk = of_clk_get_by_name(pdev->dev.of_node, "rxoob");
+ if (IS_ERR(rxoob_clk))
+ return PTR_ERR(rxoob_clk);
+
+ rc = clk_set_rate(rxoob_clk, 1);
+ if (rc)
+ return rc;
+
+ rc = ahci_platform_enable_resources(hpriv);
+ if (rc)
+ return rc;
+
+ rc = ahci_platform_init_host(pdev, hpriv, _ahci_port_info, 0, 0);
+ if (rc)
+ goto disable_resources;
+
+ return 0;
+disable_resources:
+ ahci_platform_disable_resources(hpriv);
+ return rc;
+}
+
+static const struct of_device_id qcom_ahci_of_match[] = {
+ { .compatible = "qcom,msm-ahci", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, qcom_ahci_of_match);
+
+static struct platform_driver qcom_ahci_driver = {
+ .probe = qcom_ahci_probe,
+ .remove = ata_platform_remove_one,
+ .driver = {
+ .name = "qcom_ahci_qcom",
+ .owner = THIS_MODULE,
+ .of_match_table = qcom_ahci_of_match,
+ },
+};
+module_platform_driver(qcom_ahci_driver);
+
+MODULE_DESCRIPTION("Qualcomm AHCI SATA platform driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("ahci:qcom");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
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Re: [PATCH 2/3] ata: Add Qualcomm ARM SoC AHCI SATA host controller driver
On Jun 13, 2014, at 9:38 AM, Stanimir Varbanov wrote:
> Hi Kumar,
>
>> +
>> +static struct platform_driver qcom_ahci_driver = {
>> +.probe = qcom_ahci_probe,
>> +.remove = ata_platform_remove_one,
>> +.driver = {
>> +.name = "qcom_ahci_qcom",
>> +.owner = THIS_MODULE,
>> +.of_match_table = qcom_ahci_of_match,
>> +},
>> +};
>> +module_platform_driver(qcom_ahci_driver);
>> +
>> +MODULE_DESCRIPTION("Qualcomm AHCI SATA platform driver");
>> +MODULE_LICENSE("GPL");
>
> "GPL v2" ? Or only GPL is intentional?
should be v2, will fix
>
>> +MODULE_ALIAS("ahci:qcom");
>>
>
> missing MODULE_AUTHOR
>
> --
> regards,
> Stan
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
- k
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 2/3] ata: Add Qualcomm ARM SoC AHCI SATA host controller driver
On Jun 13, 2014, at 9:38 AM, Stanimir Varbanov svarba...@mm-sol.com wrote:
Hi Kumar,
+
+static struct platform_driver qcom_ahci_driver = {
+.probe = qcom_ahci_probe,
+.remove = ata_platform_remove_one,
+.driver = {
+.name = qcom_ahci_qcom,
+.owner = THIS_MODULE,
+.of_match_table = qcom_ahci_of_match,
+},
+};
+module_platform_driver(qcom_ahci_driver);
+
+MODULE_DESCRIPTION(Qualcomm AHCI SATA platform driver);
+MODULE_LICENSE(GPL);
GPL v2 ? Or only GPL is intentional?
should be v2, will fix
+MODULE_ALIAS(ahci:qcom);
missing MODULE_AUTHOR
--
regards,
Stan
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- k
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 2/3] ata: Add Qualcomm ARM SoC AHCI SATA host controller driver
Add support for the Qualcomm AHCI SATA controller that exists on several
SoC and specifically the IPQ806x family of chips. The IPQ806x SATA support
requires the associated IPQ806x SATA PHY Driver to be enabled as well.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v2:
* Fixed MODULE_LICENSE to be GPL v2
drivers/ata/Kconfig | 10 ++
drivers/ata/Makefile| 1 +
drivers/ata/ahci_qcom.c | 86 +
3 files changed, 97 insertions(+)
create mode 100644 drivers/ata/ahci_qcom.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 7671dba..aa88648 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -132,6 +132,16 @@ config AHCI_MVEBU
If unsure, say N.
+config AHCI_QCOM
+ tristate Qualcomm AHCI SATA support
+ depends on ARCH_QCOM
+ help
+ This option enables support for AHCI SATA controller
+ integrated into Qualcomm ARM SoC chipsets. For more
+ information please refer to http://www.qualcomm.com/chipsets.
+
+ If unsure, say N.
+
config AHCI_SUNXI
tristate Allwinner sunxi AHCI SATA support
depends on ARCH_SUNXI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 5a02aee..15401e9 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_QCOM)+= ahci_qcom.o libahci.o
libahci_platform.o
obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_qcom.c b/drivers/ata/ahci_qcom.c
new file mode 100644
index 000..bfb7a77
--- /dev/null
+++ b/drivers/ata/ahci_qcom.c
@@ -0,0 +1,86 @@
+/*
+ * Qualcomm ARM SoC AHCI SATA platform driver
+ *
+ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
+ *
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/pm.h
+#include linux/device.h
+#include linux/platform_device.h
+#include linux/libata.h
+#include linux/ahci_platform.h
+#include ahci.h
+
+static const struct ata_port_info qcom_ahci_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = ahci_platform_ops,
+};
+
+static int qcom_ahci_probe(struct platform_device *pdev)
+{
+ struct ahci_host_priv *hpriv;
+ struct clk *rxoob_clk;
+ int rc;
+
+ hpriv = ahci_platform_get_resources(pdev);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
+
+ /* Try and set the rxoob clk to 100Mhz */
+ rxoob_clk = of_clk_get_by_name(pdev-dev.of_node, rxoob);
+ if (IS_ERR(rxoob_clk))
+ return PTR_ERR(rxoob_clk);
+
+ rc = clk_set_rate(rxoob_clk, 1);
+ if (rc)
+ return rc;
+
+ rc = ahci_platform_enable_resources(hpriv);
+ if (rc)
+ return rc;
+
+ rc = ahci_platform_init_host(pdev, hpriv, qcom_ahci_port_info, 0, 0);
+ if (rc)
+ goto disable_resources;
+
+ return 0;
+disable_resources:
+ ahci_platform_disable_resources(hpriv);
+ return rc;
+}
+
+static const struct of_device_id qcom_ahci_of_match[] = {
+ { .compatible = qcom,msm-ahci, },
+ {},
+};
+MODULE_DEVICE_TABLE(of, qcom_ahci_of_match);
+
+static struct platform_driver qcom_ahci_driver = {
+ .probe = qcom_ahci_probe,
+ .remove = ata_platform_remove_one,
+ .driver = {
+ .name = qcom_ahci_qcom,
+ .owner = THIS_MODULE,
+ .of_match_table = qcom_ahci_of_match,
+ },
+};
+module_platform_driver(qcom_ahci_driver);
+
+MODULE_DESCRIPTION(Qualcomm AHCI SATA platform driver);
+MODULE_LICENSE(GPL v2);
+MODULE_ALIAS(ahci:qcom);
--
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hosted by The Linux Foundation
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[PATCH v2 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v2:
* dropped unused dev pointer in struct qcom_ipq806x_sata_phy
* remove unnecessary reg initializaiton
* Removed unneeded error message
* Added remove function to disable the clock
drivers/phy/Kconfig | 6 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 210
3 files changed, 217 insertions(+)
create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..52bfb93 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,10 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_QCOM_IPQ806X_SATA
+ tristate Qualcomm IPQ806x SATA SerDes/PHY driver
+ depends on ARCH_QCOM
+ depends on OF
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d950317 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
b/drivers/phy/phy-qcom-ipq806x-sata.c
new file mode 100644
index 000..f22b9a2
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/time.h
+#include linux/delay.h
+#include linux/clk.h
+#include linux/slab.h
+#include linux/platform_device.h
+#include linux/phy/phy.h
+
+struct qcom_ipq806x_sata_phy {
+ void __iomem *mmio;
+ struct clk *cfg_clk;
+};
+
+#define __set(v, a, b) (((v) (b)) GENMASK(a, b))
+
+#define SATA_PHY_P0_PARAM0 0x200
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+
+#define SATA_PHY_P0_PARAM1 0x204
+#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+
+#define SATA_PHY_P0_PARAM2 0x208
+#define SATA_PHY_P0_PARAM2_RX_EQ(x)__set(x, 20, 18)
+#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
+
+#define SATA_PHY_P0_PARAM3 0x20C
+#define SATA_PHY_SSC_EN0x8
+#define SATA_PHY_P0_PARAM4 0x210
+#define SATA_PHY_REF_SSP_EN0x2
+#define SATA_PHY_RESET 0x1
+
+static inline void qcom_ipq806x_sata_delay_us(unsigned int delay)
+{
+ /* sleep for max. 50us more to combine processor wakeups */
+ usleep_range(delay, delay + 50);
+}
+
+static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
+{
+ struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
+ u32 reg;
+
+ /* Setting SSC_EN to 1 */
+ reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM3);
+ reg = reg | SATA_PHY_SSC_EN;
+ writel_relaxed(reg, phy-mmio + SATA_PHY_P0_PARAM3);
+
+ reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM0)
+ ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK);
+ reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3
Re: [Patch v2 3/3] spi: qup: Add support for v1.1.1
On Jun 12, 2014, at 2:34 PM, Andy Gross agr...@codeaurora.org wrote: This patch adds support for v1.1.1 of the SPI QUP controller. Signed-off-by: Andy Gross agr...@codeaurora.org --- .../devicetree/bindings/spi/qcom,spi-qup.txt |6 +++- drivers/spi/spi-qup.c | 36 2 files changed, 27 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt index bee6ff2..e2c88df 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt @@ -7,7 +7,11 @@ SPI in master mode supports up to 50MHz, up to four chip selects, programmable data path from 4 bits to 32 bits and numerous protocol variants. Required properties: -- compatible: Should contain qcom,spi-qup-v2.1.1 or qcom,spi-qup-v2.2.1 +- compatible: Should contain: + qcom,spi-qup-v1.1.1 for 8660, 8960 and 8064. + qcom,spi-qup-v2.1.1 for 8974 and later + qcom,spi-qup-v2.2.1 for 8974 v2 and later. + We should probably try to be a bit more clear about ipq/apq/msm here. - reg:Should contain base register location and length - interrupts: Interrupt number used by this controller - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 2/3] ata: Add Qualcomm ARM SoC AHCI SATA host controller driver
On Jun 12, 2014, at 2:50 PM, Stephen Boyd wrote:
> On 06/12/14 12:13, Kumar Gala wrote:
>> +static int qcom_ahci_probe(struct platform_device *pdev)
>> +{
>> +struct ahci_host_priv *hpriv;
>> +struct clk *rxoob_clk;
>> +int rc;
>> +
>> +hpriv = ahci_platform_get_resources(pdev);
>> +if (IS_ERR(hpriv))
>> +return PTR_ERR(hpriv);
>> +
>> +/* Try and set the rxoob clk to 100Mhz */
>> +rxoob_clk = of_clk_get_by_name(pdev->dev.of_node, "rxoob");
>
> Any reason we can't use devm_clk_get() here?
Was trying to avoid the ref cnt of devm_clk_get() as the clk’s are actually
handled in ahci_platform_get_resources/ahci_platform_enable_resources
- k
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
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[PATCH 2/2] phy: qcom: Add device tree bindings information
Add binding spec for Qualcomm SoC PHYs, starting with the SATA PHY on
the IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
Documentation/devicetree/bindings/phy/qcom-phy.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom-phy.txt
b/Documentation/devicetree/bindings/phy/qcom-phy.txt
new file mode 100644
index 000..76bfbd0
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-phy.txt
@@ -0,0 +1,23 @@
+Qualcomm IPQ806x SATA PHY Controller
+
+
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "qcom,ipq806x-sata-phy"
+- reg: offset and length of the SATA PHY register set;
+- #phy-cells: must be zero
+- clocks: must be exactly one entry
+- clock-names: must be "cfg"
+
+Example:
+ sata_phy: sata-phy@1b40 {
+ compatible = "qcom,ipq806x-sata-phy";
+ reg = <0x1b40 0x200>;
+
+ clocks = < SATA_PHY_CFG_CLK>;
+ clock-names = "cfg";
+
+ #phy-cells = <0>;
+ };
--
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hosted by The Linux Foundation
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[PATCH 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
drivers/phy/Kconfig | 6 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 204
3 files changed, 211 insertions(+)
create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..52bfb93 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,10 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_QCOM_IPQ806X_SATA
+ tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
+ depends on ARCH_QCOM
+ depends on OF
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d950317 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
b/drivers/phy/phy-qcom-ipq806x-sata.c
new file mode 100644
index 000..fc57340
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct qcom_ipq806x_sata_phy {
+ struct device *dev;
+ void __iomem *mmio;
+ struct clk *cfg_clk;
+};
+
+#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
+
+#define SATA_PHY_P0_PARAM0 0x200
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+
+#define SATA_PHY_P0_PARAM1 0x204
+#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+
+#define SATA_PHY_P0_PARAM2 0x208
+#define SATA_PHY_P0_PARAM2_RX_EQ(x)__set(x, 20, 18)
+#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
+
+#define SATA_PHY_P0_PARAM3 0x20C
+#define SATA_PHY_SSC_EN0x8
+#define SATA_PHY_P0_PARAM4 0x210
+#define SATA_PHY_REF_SSP_EN0x2
+#define SATA_PHY_RESET 0x1
+
+static inline void qcom_ipq806x_sata_delay_us(unsigned int delay)
+{
+ /* sleep for max. 50us more to combine processor wakeups */
+ usleep_range(delay, delay + 50);
+}
+
+static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
+{
+ struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
+ u32 reg = 0;
+
+ /* Setting SSC_EN to 1 */
+ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3);
+ reg = reg | SATA_PHY_SSC_EN;
+ writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
+
+ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) &
+ ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK);
+ reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf);
+ writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0);
+
+ reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) &
+ ~(SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK |
+ S
[PATCH 2/3] ata: Add Qualcomm ARM SoC AHCI SATA host controller driver
Add support for the Qualcomm AHCI SATA controller that exists on several
SoC and specifically the IPQ806x family of chips. The IPQ806x SATA support
requires the associated IPQ806x SATA PHY Driver to be enabled as well.
Signed-off-by: Kumar Gala
---
drivers/ata/Kconfig | 10 ++
drivers/ata/Makefile| 1 +
drivers/ata/ahci_qcom.c | 86 +
3 files changed, 97 insertions(+)
create mode 100644 drivers/ata/ahci_qcom.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 7671dba..aa88648 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -132,6 +132,16 @@ config AHCI_MVEBU
If unsure, say N.
+config AHCI_QCOM
+ tristate "Qualcomm AHCI SATA support"
+ depends on ARCH_QCOM
+ help
+ This option enables support for AHCI SATA controller
+ integrated into Qualcomm ARM SoC chipsets. For more
+ information please refer to http://www.qualcomm.com/chipsets.
+
+ If unsure, say N.
+
config AHCI_SUNXI
tristate "Allwinner sunxi AHCI SATA support"
depends on ARCH_SUNXI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 5a02aee..15401e9 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_QCOM)+= ahci_qcom.o libahci.o
libahci_platform.o
obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_qcom.c b/drivers/ata/ahci_qcom.c
new file mode 100644
index 000..7a4fd30
--- /dev/null
+++ b/drivers/ata/ahci_qcom.c
@@ -0,0 +1,86 @@
+/*
+ * Qualcomm ARM SoC AHCI SATA platform driver
+ *
+ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
+ *
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "ahci.h"
+
+static const struct ata_port_info qcom_ahci_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = _platform_ops,
+};
+
+static int qcom_ahci_probe(struct platform_device *pdev)
+{
+ struct ahci_host_priv *hpriv;
+ struct clk *rxoob_clk;
+ int rc;
+
+ hpriv = ahci_platform_get_resources(pdev);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
+
+ /* Try and set the rxoob clk to 100Mhz */
+ rxoob_clk = of_clk_get_by_name(pdev->dev.of_node, "rxoob");
+ if (IS_ERR(rxoob_clk))
+ return PTR_ERR(rxoob_clk);
+
+ rc = clk_set_rate(rxoob_clk, 1);
+ if (rc)
+ return rc;
+
+ rc = ahci_platform_enable_resources(hpriv);
+ if (rc)
+ return rc;
+
+ rc = ahci_platform_init_host(pdev, hpriv, _ahci_port_info, 0, 0);
+ if (rc)
+ goto disable_resources;
+
+ return 0;
+disable_resources:
+ ahci_platform_disable_resources(hpriv);
+ return rc;
+}
+
+static const struct of_device_id qcom_ahci_of_match[] = {
+ { .compatible = "qcom,msm-ahci", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, qcom_ahci_of_match);
+
+static struct platform_driver qcom_ahci_driver = {
+ .probe = qcom_ahci_probe,
+ .remove = ata_platform_remove_one,
+ .driver = {
+ .name = "qcom_ahci_qcom",
+ .owner = THIS_MODULE,
+ .of_match_table = qcom_ahci_of_match,
+ },
+};
+module_platform_driver(qcom_ahci_driver);
+
+MODULE_DESCRIPTION("Qualcomm AHCI SATA platform driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("ahci:qcom");
--
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[PATCH 1/3] ahci-platform: Bump max number of clocks to 5
Qualcomm IPQ806x SoCs with SATA controllers need 5 clocks to be enabled.
Signed-off-by: Kumar Gala
---
drivers/ata/ahci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 05882e4..001aa99 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -53,7 +53,7 @@
enum {
AHCI_MAX_PORTS = 32,
- AHCI_MAX_CLKS = 3,
+ AHCI_MAX_CLKS = 5,
AHCI_MAX_SG = 168, /* hardware max is 64K */
AHCI_DMA_BOUNDARY = 0x,
AHCI_MAX_CMDS = 32,
--
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[PATCH 3/3] ata: qcom: Add device tree bindings information
Add device tree binding for Qualcomm AHCI SATA controller and specifically
the sata controller on the IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
.../devicetree/bindings/ata/qcom-sata.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/qcom-sata.txt
diff --git a/Documentation/devicetree/bindings/ata/qcom-sata.txt
b/Documentation/devicetree/bindings/ata/qcom-sata.txt
new file mode 100644
index 000..5e74e41
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/qcom-sata.txt
@@ -0,0 +1,40 @@
+* Qualcomm AHCI SATA Controller
+
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+Each SATA controller should have its own node.
+
+Required properties:
+- compatible : compatible list, contains "qcom,msm-ahci"
+- interrupts :
+- reg :
+- phys : Must contain exactly one entry as specified
+ in phy-bindings.txt
+- phy-names: Must be "sata-phy"
+
+Required properties for "qcom,ipq806x-ahci" compatible:
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names : Shall be:
+ "slave_iface" - Fabric port AHB clock for SATA
+ "iface" - AHB clock
+ "core" - core clock
+ "rxoob" - RX out-of-band clock
+ "pmalive" - Power Module Alive clock
+
+Example:
+ sata@2900 {
+ compatible = "qcom,ipq806x-ahci", "qcom,msm-ahci";
+ reg = <0x2900 0x180>;
+
+ interrupts = <0 209 0x0>;
+
+ clocks = < SFAB_SATA_S_H_CLK>,
+< SATA_H_CLK>,
+< SATA_A_CLK>,
+< SATA_RXOOB_CLK>,
+< SATA_PMALIVE_CLK>;
+ clock-names = "slave_iface", "iface", "core",
+ "rxoob", "pmalive";
+
+ phys = <_phy>;
+ phy-names = "sata-phy";
+ };
--
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[PATCH 1/3] ahci-platform: Bump max number of clocks to 5
Qualcomm IPQ806x SoCs with SATA controllers need 5 clocks to be enabled.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/ata/ahci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 05882e4..001aa99 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -53,7 +53,7 @@
enum {
AHCI_MAX_PORTS = 32,
- AHCI_MAX_CLKS = 3,
+ AHCI_MAX_CLKS = 5,
AHCI_MAX_SG = 168, /* hardware max is 64K */
AHCI_DMA_BOUNDARY = 0x,
AHCI_MAX_CMDS = 32,
--
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[PATCH 3/3] ata: qcom: Add device tree bindings information
Add device tree binding for Qualcomm AHCI SATA controller and specifically
the sata controller on the IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
.../devicetree/bindings/ata/qcom-sata.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/qcom-sata.txt
diff --git a/Documentation/devicetree/bindings/ata/qcom-sata.txt
b/Documentation/devicetree/bindings/ata/qcom-sata.txt
new file mode 100644
index 000..5e74e41
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/qcom-sata.txt
@@ -0,0 +1,40 @@
+* Qualcomm AHCI SATA Controller
+
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+Each SATA controller should have its own node.
+
+Required properties:
+- compatible : compatible list, contains qcom,msm-ahci
+- interrupts : interrupt mapping for SATA IRQ
+- reg : registers mapping
+- phys : Must contain exactly one entry as specified
+ in phy-bindings.txt
+- phy-names: Must be sata-phy
+
+Required properties for qcom,ipq806x-ahci compatible:
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names : Shall be:
+ slave_iface - Fabric port AHB clock for SATA
+ iface - AHB clock
+ core - core clock
+ rxoob - RX out-of-band clock
+ pmalive - Power Module Alive clock
+
+Example:
+ sata@2900 {
+ compatible = qcom,ipq806x-ahci, qcom,msm-ahci;
+ reg = 0x2900 0x180;
+
+ interrupts = 0 209 0x0;
+
+ clocks = gcc SFAB_SATA_S_H_CLK,
+gcc SATA_H_CLK,
+gcc SATA_A_CLK,
+gcc SATA_RXOOB_CLK,
+gcc SATA_PMALIVE_CLK;
+ clock-names = slave_iface, iface, core,
+ rxoob, pmalive;
+
+ phys = sata_phy;
+ phy-names = sata-phy;
+ };
--
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[PATCH 2/3] ata: Add Qualcomm ARM SoC AHCI SATA host controller driver
Add support for the Qualcomm AHCI SATA controller that exists on several
SoC and specifically the IPQ806x family of chips. The IPQ806x SATA support
requires the associated IPQ806x SATA PHY Driver to be enabled as well.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/ata/Kconfig | 10 ++
drivers/ata/Makefile| 1 +
drivers/ata/ahci_qcom.c | 86 +
3 files changed, 97 insertions(+)
create mode 100644 drivers/ata/ahci_qcom.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 7671dba..aa88648 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -132,6 +132,16 @@ config AHCI_MVEBU
If unsure, say N.
+config AHCI_QCOM
+ tristate Qualcomm AHCI SATA support
+ depends on ARCH_QCOM
+ help
+ This option enables support for AHCI SATA controller
+ integrated into Qualcomm ARM SoC chipsets. For more
+ information please refer to http://www.qualcomm.com/chipsets.
+
+ If unsure, say N.
+
config AHCI_SUNXI
tristate Allwinner sunxi AHCI SATA support
depends on ARCH_SUNXI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 5a02aee..15401e9 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_QCOM)+= ahci_qcom.o libahci.o
libahci_platform.o
obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_qcom.c b/drivers/ata/ahci_qcom.c
new file mode 100644
index 000..7a4fd30
--- /dev/null
+++ b/drivers/ata/ahci_qcom.c
@@ -0,0 +1,86 @@
+/*
+ * Qualcomm ARM SoC AHCI SATA platform driver
+ *
+ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
+ *
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/pm.h
+#include linux/device.h
+#include linux/platform_device.h
+#include linux/libata.h
+#include linux/ahci_platform.h
+#include ahci.h
+
+static const struct ata_port_info qcom_ahci_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = ahci_platform_ops,
+};
+
+static int qcom_ahci_probe(struct platform_device *pdev)
+{
+ struct ahci_host_priv *hpriv;
+ struct clk *rxoob_clk;
+ int rc;
+
+ hpriv = ahci_platform_get_resources(pdev);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
+
+ /* Try and set the rxoob clk to 100Mhz */
+ rxoob_clk = of_clk_get_by_name(pdev-dev.of_node, rxoob);
+ if (IS_ERR(rxoob_clk))
+ return PTR_ERR(rxoob_clk);
+
+ rc = clk_set_rate(rxoob_clk, 1);
+ if (rc)
+ return rc;
+
+ rc = ahci_platform_enable_resources(hpriv);
+ if (rc)
+ return rc;
+
+ rc = ahci_platform_init_host(pdev, hpriv, qcom_ahci_port_info, 0, 0);
+ if (rc)
+ goto disable_resources;
+
+ return 0;
+disable_resources:
+ ahci_platform_disable_resources(hpriv);
+ return rc;
+}
+
+static const struct of_device_id qcom_ahci_of_match[] = {
+ { .compatible = qcom,msm-ahci, },
+ {},
+};
+MODULE_DEVICE_TABLE(of, qcom_ahci_of_match);
+
+static struct platform_driver qcom_ahci_driver = {
+ .probe = qcom_ahci_probe,
+ .remove = ata_platform_remove_one,
+ .driver = {
+ .name = qcom_ahci_qcom,
+ .owner = THIS_MODULE,
+ .of_match_table = qcom_ahci_of_match,
+ },
+};
+module_platform_driver(qcom_ahci_driver);
+
+MODULE_DESCRIPTION(Qualcomm AHCI SATA platform driver);
+MODULE_LICENSE(GPL);
+MODULE_ALIAS(ahci:qcom);
--
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Please
[PATCH 1/2] phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/phy/Kconfig | 6 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 204
3 files changed, 211 insertions(+)
create mode 100644 drivers/phy/phy-qcom-ipq806x-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 16a2f06..52bfb93 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -178,4 +178,10 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_QCOM_IPQ806X_SATA
+ tristate Qualcomm IPQ806x SATA SerDes/PHY driver
+ depends on ARCH_QCOM
+ depends on OF
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4f1d57..d950317 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -20,3 +20,4 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) +=
phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA)+= phy-qcom-ipq806x-sata.o
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c
b/drivers/phy/phy-qcom-ipq806x-sata.c
new file mode 100644
index 000..fc57340
--- /dev/null
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/time.h
+#include linux/delay.h
+#include linux/clk.h
+#include linux/slab.h
+#include linux/platform_device.h
+#include linux/phy/phy.h
+
+struct qcom_ipq806x_sata_phy {
+ struct device *dev;
+ void __iomem *mmio;
+ struct clk *cfg_clk;
+};
+
+#define __set(v, a, b) (((v) (b)) GENMASK(a, b))
+
+#define SATA_PHY_P0_PARAM0 0x200
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
+#define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+
+#define SATA_PHY_P0_PARAM1 0x204
+#define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
+#define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+
+#define SATA_PHY_P0_PARAM2 0x208
+#define SATA_PHY_P0_PARAM2_RX_EQ(x)__set(x, 20, 18)
+#define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
+
+#define SATA_PHY_P0_PARAM3 0x20C
+#define SATA_PHY_SSC_EN0x8
+#define SATA_PHY_P0_PARAM4 0x210
+#define SATA_PHY_REF_SSP_EN0x2
+#define SATA_PHY_RESET 0x1
+
+static inline void qcom_ipq806x_sata_delay_us(unsigned int delay)
+{
+ /* sleep for max. 50us more to combine processor wakeups */
+ usleep_range(delay, delay + 50);
+}
+
+static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
+{
+ struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
+ u32 reg = 0;
+
+ /* Setting SSC_EN to 1 */
+ reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM3);
+ reg = reg | SATA_PHY_SSC_EN;
+ writel_relaxed(reg, phy-mmio + SATA_PHY_P0_PARAM3);
+
+ reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM0)
+ ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK |
+ SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK);
+ reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf);
+ writel_relaxed(reg, phy-mmio + SATA_PHY_P0_PARAM0);
+
+ reg = readl_relaxed(phy-mmio + SATA_PHY_P0_PARAM1
[PATCH 2/2] phy: qcom: Add device tree bindings information
Add binding spec for Qualcomm SoC PHYs, starting with the SATA PHY on
the IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
Documentation/devicetree/bindings/phy/qcom-phy.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom-phy.txt
b/Documentation/devicetree/bindings/phy/qcom-phy.txt
new file mode 100644
index 000..76bfbd0
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-phy.txt
@@ -0,0 +1,23 @@
+Qualcomm IPQ806x SATA PHY Controller
+
+
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible list, contains qcom,ipq806x-sata-phy
+- reg: offset and length of the SATA PHY register set;
+- #phy-cells: must be zero
+- clocks: must be exactly one entry
+- clock-names: must be cfg
+
+Example:
+ sata_phy: sata-phy@1b40 {
+ compatible = qcom,ipq806x-sata-phy;
+ reg = 0x1b40 0x200;
+
+ clocks = gcc SATA_PHY_CFG_CLK;
+ clock-names = cfg;
+
+ #phy-cells = 0;
+ };
--
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Re: [PATCH 2/3] ata: Add Qualcomm ARM SoC AHCI SATA host controller driver
On Jun 12, 2014, at 2:50 PM, Stephen Boyd sb...@codeaurora.org wrote:
On 06/12/14 12:13, Kumar Gala wrote:
+static int qcom_ahci_probe(struct platform_device *pdev)
+{
+struct ahci_host_priv *hpriv;
+struct clk *rxoob_clk;
+int rc;
+
+hpriv = ahci_platform_get_resources(pdev);
+if (IS_ERR(hpriv))
+return PTR_ERR(hpriv);
+
+/* Try and set the rxoob clk to 100Mhz */
+rxoob_clk = of_clk_get_by_name(pdev-dev.of_node, rxoob);
Any reason we can't use devm_clk_get() here?
Was trying to avoid the ref cnt of devm_clk_get() as the clk’s are actually
handled in ahci_platform_get_resources/ahci_platform_enable_resources
- k
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Re: [PATCH] mmc: sdhci-msm: Fix fallout from sdhci refactoring
On Jun 10, 2014, at 1:27 PM, Stephen Boyd wrote: > The sdhci core was refactored recently and some of those > refactorings required changes in every sdhci platform driver. > Those updates happened around the same time as when the msm > driver was merged so the refactorings missed the msm driver. > Hook in the basic library functions so that we can boot apq8074 > dragonboards again instead of crashing when we try to jump to > NULL function pointers. > > Reported-by: Kevin Hilman > Cc: Georgi Djakov > Cc: Russell King > Signed-off-by: Stephen Boyd > --- > > Patch based on next-20140610 > > drivers/mmc/host/sdhci-msm.c | 4 > 1 file changed, 4 insertions(+) Acked-by: Kumar Gala Feel free to pick up this version of the patch and ignore mine. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] mmc: sdhci-msm: Fix crash due to missing ops functions
Recent changes in sdhci core need to get reflected in sdhci_msm_ops otherwise
we ended up dereferencing null pointers in the ops struct and crash.
Signed-off-by: Kumar Gala
---
drivers/mmc/host/sdhci-msm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index acb0e9e..0d6cee0 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -467,7 +467,11 @@ static const struct of_device_id sdhci_msm_dt_match[] = {
MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
static struct sdhci_ops sdhci_msm_ops = {
+ .set_clock = sdhci_set_clock,
+ .set_bus_width = sdhci_set_bus_width,
.platform_execute_tuning = sdhci_msm_execute_tuning,
+ .reset = sdhci_reset,
+ .set_uhs_signaling = sdhci_set_uhs_signaling,
};
static int sdhci_msm_probe(struct platform_device *pdev)
--
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[PATCH] mmc: sdhci-msm: Fix crash due to missing ops functions
Recent changes in sdhci core need to get reflected in sdhci_msm_ops otherwise
we ended up dereferencing null pointers in the ops struct and crash.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/mmc/host/sdhci-msm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index acb0e9e..0d6cee0 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -467,7 +467,11 @@ static const struct of_device_id sdhci_msm_dt_match[] = {
MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
static struct sdhci_ops sdhci_msm_ops = {
+ .set_clock = sdhci_set_clock,
+ .set_bus_width = sdhci_set_bus_width,
.platform_execute_tuning = sdhci_msm_execute_tuning,
+ .reset = sdhci_reset,
+ .set_uhs_signaling = sdhci_set_uhs_signaling,
};
static int sdhci_msm_probe(struct platform_device *pdev)
--
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Re: [PATCH] mmc: sdhci-msm: Fix fallout from sdhci refactoring
On Jun 10, 2014, at 1:27 PM, Stephen Boyd sb...@codeaurora.org wrote: The sdhci core was refactored recently and some of those refactorings required changes in every sdhci platform driver. Those updates happened around the same time as when the msm driver was merged so the refactorings missed the msm driver. Hook in the basic library functions so that we can boot apq8074 dragonboards again instead of crashing when we try to jump to NULL function pointers. Reported-by: Kevin Hilman khil...@linaro.org Cc: Georgi Djakov gdja...@mm-sol.com Cc: Russell King rmk+ker...@arm.linux.org.uk Signed-off-by: Stephen Boyd sb...@codeaurora.org --- Patch based on next-20140610 drivers/mmc/host/sdhci-msm.c | 4 1 file changed, 4 insertions(+) Acked-by: Kumar Gala ga...@codeaurora.org Feel free to pick up this version of the patch and ignore mine. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] tty: serial: msm: Fix section mismatch warning
WARNING: drivers/tty/built-in.o(.data+0x3544): Section mismatch in
reference from the variable msm_platform_driver to the function
.init.text:msm_serial_probe()
The variable msm_platform_driver references
the function __init msm_serial_probe()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
Signed-off-by: Kumar Gala
---
drivers/tty/serial/msm_serial.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 778e376..24f3cdc 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -991,7 +991,7 @@ static const struct of_device_id msm_uartdm_table[] = {
{ }
};
-static int __init msm_serial_probe(struct platform_device *pdev)
+static int msm_serial_probe(struct platform_device *pdev)
{
struct msm_port *msm_port;
struct resource *resource;
--
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[PATCH] tty: serial: msm: Fix section mismatch warning
WARNING: drivers/tty/built-in.o(.data+0x3544): Section mismatch in
reference from the variable msm_platform_driver to the function
.init.text:msm_serial_probe()
The variable msm_platform_driver references
the function __init msm_serial_probe()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/tty/serial/msm_serial.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 778e376..24f3cdc 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -991,7 +991,7 @@ static const struct of_device_id msm_uartdm_table[] = {
{ }
};
-static int __init msm_serial_probe(struct platform_device *pdev)
+static int msm_serial_probe(struct platform_device *pdev)
{
struct msm_port *msm_port;
struct resource *resource;
--
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Re: [PATCH 1/2] pci: Add IORESOURCE_BIT entry for PCIe ECAM resources.
On Jun 2, 2014, at 2:15 PM, Arnd Bergmann wrote: > On Monday 02 June 2014 13:09:08 Kumar Gala wrote: >>> However, what do we do with the 2 cases that exist in upstream that >>>> are using ranges for cfg space? >>> >>> Ignore them in the core code? Make the specific host controller handle >>> them I would think. >> >> I just meant, should we ‘break’ their DTs and move them from using ranges to >> reg? > > dw-pcie is used on a lot of systems, I think we should make the common > part of that driver always handle config space in a common way, and > move out the part that parses the ranges property into the individual > soc-specific glue drivers that want to keep optional backwards compatibility > with existing dtbs. > > Which one is the other driver? > > Arnd Its imx6 and exynos, havent looked to see if dw-pcie is handling the parsing or not for them. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 3/4] ARM: dts: qcom: Add APQ8084 Global Clock Controller DT node
On May 31, 2014, at 10:45 AM, Georgi Djakov wrote: > This patch adds the necessary node to probe the global clock > controller on APQ8084 platforms. > > Signed-off-by: Georgi Djakov > --- > arch/arm/boot/dts/qcom-apq8084.dtsi | 10 ++ > 1 file changed, 10 insertions(+) Can you split the 2 DT patches into their own patchset since they will go via the qcom/arm-soc tree and not Mike’s clk tree. thanks - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/2] pci: Add IORESOURCE_BIT entry for PCIe ECAM resources.
On Jun 2, 2014, at 11:23 AM, Grant Likely wrote: > On Mon, 2 Jun 2014 10:40:30 -0500, Kumar Gala wrote: >> >> On Jun 2, 2014, at 10:09 AM, Grant Likely wrote: >> >>> On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann wrote: >>>> On Saturday 31 May 2014 01:36:40 Liviu Dudau wrote: >>>>> We would like to be able to describe PCIe ECAM resources as >>>>> IORESOURCE_MEM blocks while distinguish them from standard >>>>> memory resources. Add an IORESOURCE_BIT entry for this case. >>>>> >>>>> Signed-off-by: Liviu Dudau >>>> >>>> I still don't see any value in this at all. What is the advantage >>>> of doing this opposed to just having a standardized 'reg' property >>>> for a particular compatible string? >>> >>> I'm inclined to agree. It doesn't seem appropriate to put config space >>> in ranges, and the host controller binding is responsible for >>> identifying how config space is memory mapped. >>> >>> g. >> >> I don’t agree when it comes to ECAM, but we can drop this for now >> until someone really does that. > > Okay, humor me then. What would a ranges property look like for ECAM? Do > you have an example? I believe there would need to be a separate entry > for each and every PCI device on the bus to get the config spaces to be > contiguous. The definition of ECAM is a 256M linear region with each 4k being a different bus/dev/func. So the ranges would look something like: ranges = <0x 0 0x 0x0ff0 0 0x1000> /* configuration space */ The reason I think allow an ECAM makes sense in ranges is because it allows for a direct IO read/write to CFG space (w/o any mapping) similar to what one would do for MEM space or IO. > However, what do we do with the 2 cases that exist in upstream that >> are using ranges for cfg space? > > Ignore them in the core code? Make the specific host controller handle > them I would think. I just meant, should we ‘break’ their DTs and move them from using ranges to reg? - k > -- > To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/2] pci: Add IORESOURCE_BIT entry for PCIe ECAM resources.
On Jun 2, 2014, at 10:09 AM, Grant Likely wrote: > On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann wrote: >> On Saturday 31 May 2014 01:36:40 Liviu Dudau wrote: >>> We would like to be able to describe PCIe ECAM resources as >>> IORESOURCE_MEM blocks while distinguish them from standard >>> memory resources. Add an IORESOURCE_BIT entry for this case. >>> >>> Signed-off-by: Liviu Dudau >> >> I still don't see any value in this at all. What is the advantage >> of doing this opposed to just having a standardized 'reg' property >> for a particular compatible string? > > I'm inclined to agree. It doesn't seem appropriate to put config space > in ranges, and the host controller binding is responsible for > identifying how config space is memory mapped. > > g. I don’t agree when it comes to ECAM, but we can drop this for now until someone really does that. However, what do we do with the 2 cases that exist in upstream that are using ranges for cfg space? - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/2] pci: Add IORESOURCE_BIT entry for PCIe ECAM resources.
On Jun 2, 2014, at 10:09 AM, Grant Likely grant.lik...@linaro.org wrote: On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann a...@arndb.de wrote: On Saturday 31 May 2014 01:36:40 Liviu Dudau wrote: We would like to be able to describe PCIe ECAM resources as IORESOURCE_MEM blocks while distinguish them from standard memory resources. Add an IORESOURCE_BIT entry for this case. Signed-off-by: Liviu Dudau liviu.du...@arm.com I still don't see any value in this at all. What is the advantage of doing this opposed to just having a standardized 'reg' property for a particular compatible string? I'm inclined to agree. It doesn't seem appropriate to put config space in ranges, and the host controller binding is responsible for identifying how config space is memory mapped. g. I don’t agree when it comes to ECAM, but we can drop this for now until someone really does that. However, what do we do with the 2 cases that exist in upstream that are using ranges for cfg space? - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/2] pci: Add IORESOURCE_BIT entry for PCIe ECAM resources.
On Jun 2, 2014, at 11:23 AM, Grant Likely grant.lik...@linaro.org wrote: On Mon, 2 Jun 2014 10:40:30 -0500, Kumar Gala ga...@codeaurora.org wrote: On Jun 2, 2014, at 10:09 AM, Grant Likely grant.lik...@linaro.org wrote: On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann a...@arndb.de wrote: On Saturday 31 May 2014 01:36:40 Liviu Dudau wrote: We would like to be able to describe PCIe ECAM resources as IORESOURCE_MEM blocks while distinguish them from standard memory resources. Add an IORESOURCE_BIT entry for this case. Signed-off-by: Liviu Dudau liviu.du...@arm.com I still don't see any value in this at all. What is the advantage of doing this opposed to just having a standardized 'reg' property for a particular compatible string? I'm inclined to agree. It doesn't seem appropriate to put config space in ranges, and the host controller binding is responsible for identifying how config space is memory mapped. g. I don’t agree when it comes to ECAM, but we can drop this for now until someone really does that. Okay, humor me then. What would a ranges property look like for ECAM? Do you have an example? I believe there would need to be a separate entry for each and every PCI device on the bus to get the config spaces to be contiguous. The definition of ECAM is a 256M linear region with each 4k being a different bus/dev/func. So the ranges would look something like: ranges = 0x 0 0x 0x0ff0 0 0x1000 /* configuration space */ The reason I think allow an ECAM makes sense in ranges is because it allows for a direct IO read/write to CFG space (w/o any mapping) similar to what one would do for MEM space or IO. However, what do we do with the 2 cases that exist in upstream that are using ranges for cfg space? Ignore them in the core code? Make the specific host controller handle them I would think. I just meant, should we ‘break’ their DTs and move them from using ranges to reg? - k -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 3/4] ARM: dts: qcom: Add APQ8084 Global Clock Controller DT node
On May 31, 2014, at 10:45 AM, Georgi Djakov gdja...@mm-sol.com wrote: This patch adds the necessary node to probe the global clock controller on APQ8084 platforms. Signed-off-by: Georgi Djakov gdja...@mm-sol.com --- arch/arm/boot/dts/qcom-apq8084.dtsi | 10 ++ 1 file changed, 10 insertions(+) Can you split the 2 DT patches into their own patchset since they will go via the qcom/arm-soc tree and not Mike’s clk tree. thanks - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/2] pci: Add IORESOURCE_BIT entry for PCIe ECAM resources.
On Jun 2, 2014, at 2:15 PM, Arnd Bergmann a...@arndb.de wrote: On Monday 02 June 2014 13:09:08 Kumar Gala wrote: However, what do we do with the 2 cases that exist in upstream that are using ranges for cfg space? Ignore them in the core code? Make the specific host controller handle them I would think. I just meant, should we ‘break’ their DTs and move them from using ranges to reg? dw-pcie is used on a lot of systems, I think we should make the common part of that driver always handle config space in a common way, and move out the part that parses the ranges property into the individual soc-specific glue drivers that want to keep optional backwards compatibility with existing dtbs. Which one is the other driver? Arnd Its imx6 and exynos, havent looked to see if dw-pcie is handling the parsing or not for them. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] of: treat PCI config space as IORESOURCE_MEM type
On May 29, 2014, at 8:41 PM, Liviu Dudau wrote:
> On Thu, May 29, 2014 at 07:29:31PM -0600, Bjorn Helgaas wrote:
>> On Thu, May 29, 2014 at 6:56 PM, Liviu Dudau wrote:
>>> On Thu, May 29, 2014 at 03:51:28PM -0500, Kumar Gala wrote:
>>>>
>>>> On May 29, 2014, at 3:44 PM, Rob Herring wrote:
>>>>
>>>>> On Thu, May 29, 2014 at 11:03 AM, Kumar Gala wrote:
>>>>>> If we have a PCI config space specified in something like a ranges
>>>>>> property we should treat it as memory type resource.
>>>>>
>>>>> Config space should not be in ranges[1]. We have some cases that are,
>>>>> but we don't want new ones.
>>>>
>>>> For the cases we have I agree, however an ECAM based cfg seems completely
>>>> legit.
>>>>
>>>>>> Signed-off-by: Kumar Gala
>>>>>> ---
>>>>>> drivers/of/address.c | 3 +++
>>>>>> 1 file changed, 3 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/of/address.c b/drivers/of/address.c
>>>>>> index cb4242a..4e7ee59 100644
>>>>>> --- a/drivers/of/address.c
>>>>>> +++ b/drivers/of/address.c
>>>>>> @@ -122,6 +122,9 @@ static unsigned int of_bus_pci_get_flags(const
>>>>>> __be32 *addr)
>>>>>> u32 w = be32_to_cpup(addr);
>>>>>>
>>>>>> switch((w >> 24) & 0x03) {
>>>>>> + case 0x00: /* cfg space */
>>>>>> + flags |= IORESOURCE_MEM;
>>>>>> + break;
>>>>>
>>>>> How would you then distinguish actual memory ranges?
>>>>
>>>> One assumes you are still looking at pci_space as part of of_pci_range
>>>
>>> That doesn't happen when you start scanning the bus. The existing code will
>>> use the IORESOURCE_MEM for allocating memory space for devices, which is
>>> not what you want. Did you test your patch on any PCI system? I'm pretty
>>> sure that with my patch series that tries to make a generic framework for
>>> host controllers this will fail.
>>>
>>> We really need a IORESOURCE_CFG flag for this space.
>>
>> Maybe, but I'm not convinced yet. The existing IORESOURCE_TYPE_BITS
>> types are for things that are mutually exclusive address spaces. I
>> think this discussion is about ECAM, where the CPU side is definitely
>> in the same address space (IORESOURCE_MEM) as RAM, APICs, host bridge
>> apertures, device MMIO, etc. The ECAM area must appear in the
>> iomem_resource tree so we avoid it when allocating other areas.
>
> Agree, I'm only concerned that if this ECAM config space gets added to
> the list of pci_host_bridge windows it will be indistinguishable from
> IORESOURCE_MEM resources and pci_create_root_bus() will add it to the
> bus and allow devices present on that bus to be assigned addresses from
> that range. Which might not be what one wants for certain BARs.
>
> I've had an aborted attempt to parse ECAM ranges in one version of my
> series (granted, I was trying to hack the IORESOURCE_TYPE_BITS as well)
> and things got horribly wrong quickly. I could give this patch a go with
> my series tomorrow when I'm in the office and report back.
We need to fix the parsing code to be smarter about this case.
- k
--
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Re: [PATCH] of: treat PCI config space as IORESOURCE_MEM type
On May 30, 2014, at 3:37 PM, Jason Gunthorpe wrote: > On Fri, May 30, 2014 at 02:41:17AM +0100, Liviu Dudau wrote: > >> Agree, I'm only concerned that if this ECAM config space gets added to >> the list of pci_host_bridge windows it will be indistinguishable from >> IORESOURCE_MEM resources and pci_create_root_bus() will add it to the >> bus and allow devices present on that bus to be assigned addresses from >> that range. Which might not be what one wants for certain BARs. > > I wouldn't worry about supporting config in ranges. ECAM is the > logical use for config ranges, but it isn't specified and probably > will never be. > > Will's driver the is the only driver I've seen to support ECAM and it > didn't use ranges. I expect with 64-bit parts we will see more use of ECAM, I think the reason its not used much is because of the address space it chews up, but that becomes less of an issue with LPAE or 64-bit parts with larger physical address spaces. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: qcom: Enable GSBI driver in defconfig
On May 30, 2014, at 12:28 PM, Stephen Boyd wrote: > On 05/29/14 09:26, Kumar Gala wrote: >> Signed-off-by: Kumar Gala >> --- >> arch/arm/configs/qcom_defconfig | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm/configs/qcom_defconfig >> b/arch/arm/configs/qcom_defconfig >> index bfed753..42ebd72 100644 >> --- a/arch/arm/configs/qcom_defconfig >> +++ b/arch/arm/configs/qcom_defconfig >> @@ -131,6 +131,7 @@ CONFIG_RTC_CLASS=y >> CONFIG_DMADEVICES=y >> CONFIG_QCOM_BAM_DMA=y >> CONFIG_STAGING=y >> +CONFIG_QCOM_GSBI=y >> CONFIG_COMMON_CLK_QCOM=y >> CONFIG_MSM_GCC_8660=y >> CONFIG_MSM_MMCC_8960=y > > It would be good to do this in the multi-platform defconfig as well. > Otherwise users of that defconfig (i.e. khilman's boot tester) will > start failing to boot once the DT changes land. > > — Will do after 3.16-rc1, as nothing Kevin is booting uses the GSBI. Trying to decide if we should have some Kconfig dependency here. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom SoC changes for v3.16-2
The following changes since commit 87cfb00d666cca3abf36f755279cde1b27b9c377: ARM: qcom: Select PINCTRL by default for ARCH_QCOM (2014-05-22 11:50:42 -0500) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-soc-for-3.16-2 for you to fetch changes up to 2f528dd3b30c4351c0ece73b8bdc39753c02003b: ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084 (2014-05-29 11:14:28 -0500) Qualcomm ARM Based SoC Updates for v3.16-2 * Updated Kconfig DEBUG_QCOM_UARTDM help to include APQ8084 info Georgi Djakov (1): ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084 arch/arm/Kconfig.debug | 1 + 1 file changed, 1 insertion(+) -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom defconfig changes for v3.16-2
The following changes since commit f604759ec025e21d0c29a6d0addd53bbc60eb12e: ARM: config: Update msm_defconfig (2014-05-22 11:18:56 -0500) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-defconfig-for-3.16-2 for you to fetch changes up to 15ce39ade232bdac9fb788c66da9bcc7eb1a46a9: ARM: qcom: Enable GSBI driver in defconfig (2014-05-29 11:27:03 -0500) Qualcomm ARM Based defconfig Updates for v3.16-2 * Enable qcom GSBI driver Kumar Gala (1): ARM: qcom: Enable GSBI driver in defconfig arch/arm/configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom driver changes for v3.16-2
The following changes since commit 5d144e36b7c51612922fa05d37ff3a869261cc82: soc: qcom: Add GSBI driver (2014-05-23 11:38:04 -0500) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-drivers-for-3.16-2 for you to fetch changes up to 31964ffebbb958c6cf289c7c12edd7530d6221b9: tty: serial: msm: Remove direct access to GSBI (2014-05-29 11:06:20 -0500) Qualcomm ARM Based driver Updates for v3.16-2 * Updated MSM uart driver to not access GSBI control registers Andy Gross (1): tty: serial: msm: Remove direct access to GSBI drivers/tty/serial/msm_serial.c | 48 ++--- drivers/tty/serial/msm_serial.h | 5 - 2 files changed, 2 insertions(+), 51 deletions(-) -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom DT changes for v3.16-2
The following changes since commit 08f9234ad6b0b8bc51046346eabf5b92e631e62a: soc: qcom: Add device tree binding for GSBI (2014-05-23 11:38:53 -0500) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-dt-for-3.16-2 for you to fetch changes up to f46d23f6f3676720de2a3f195413a5e69f202238: ARM: dts: qcom: Add APQ8084-MTP board support (2014-05-29 11:16:45 -0500) Qualcomm ARM Based Device Tree Updates for v3.16-2 * Updated MSM8660/MSM8960/MSM8974 dts for various updates or conformitity to binding specs * Added APQ8064 SoC and IFC6410 board device tree support * Added APQ8084 SoC and APQ8084-MTP board device tree support Georgi Djakov (2): ARM: dts: qcom: Add APQ8084 SoC support ARM: dts: qcom: Add APQ8084-MTP board support Kumar Gala (4): ARM: dts: qcom: Update msm8974/apq8074 device trees ARM: dts: qcom: Update msm8960 device trees ARM: dts: qcom: Update msm8660 device trees ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410 board device trees arch/arm/boot/dts/Makefile | 9 +- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 16 +++ arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 1 + arch/arm/boot/dts/qcom-apq8064.dtsi| 170 +++ arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 28 +++- arch/arm/boot/dts/qcom-apq8084-mtp.dts | 6 + arch/arm/boot/dts/qcom-apq8084.dtsi| 179 + arch/arm/boot/dts/qcom-msm8660-surf.dts| 10 ++ arch/arm/boot/dts/qcom-msm8660.dtsi| 115 +--- arch/arm/boot/dts/qcom-msm8960-cdp.dts | 10 ++ arch/arm/boot/dts/qcom-msm8960.dtsi| 176 +--- arch/arm/boot/dts/qcom-msm8974.dtsi| 49 +++ arch/arm/mach-qcom/board.c | 4 +- 13 files changed, 612 insertions(+), 161 deletions(-) create mode 100644 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts create mode 100644 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi create mode 100644 arch/arm/boot/dts/qcom-apq8064.dtsi create mode 100644 arch/arm/boot/dts/qcom-apq8084-mtp.dts create mode 100644 arch/arm/boot/dts/qcom-apq8084.dtsi -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom DT changes for v3.16-2
The following changes since commit 08f9234ad6b0b8bc51046346eabf5b92e631e62a: soc: qcom: Add device tree binding for GSBI (2014-05-23 11:38:53 -0500) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-dt-for-3.16-2 for you to fetch changes up to f46d23f6f3676720de2a3f195413a5e69f202238: ARM: dts: qcom: Add APQ8084-MTP board support (2014-05-29 11:16:45 -0500) Qualcomm ARM Based Device Tree Updates for v3.16-2 * Updated MSM8660/MSM8960/MSM8974 dts for various updates or conformitity to binding specs * Added APQ8064 SoC and IFC6410 board device tree support * Added APQ8084 SoC and APQ8084-MTP board device tree support Georgi Djakov (2): ARM: dts: qcom: Add APQ8084 SoC support ARM: dts: qcom: Add APQ8084-MTP board support Kumar Gala (4): ARM: dts: qcom: Update msm8974/apq8074 device trees ARM: dts: qcom: Update msm8960 device trees ARM: dts: qcom: Update msm8660 device trees ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410 board device trees arch/arm/boot/dts/Makefile | 9 +- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 16 +++ arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 1 + arch/arm/boot/dts/qcom-apq8064.dtsi| 170 +++ arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 28 +++- arch/arm/boot/dts/qcom-apq8084-mtp.dts | 6 + arch/arm/boot/dts/qcom-apq8084.dtsi| 179 + arch/arm/boot/dts/qcom-msm8660-surf.dts| 10 ++ arch/arm/boot/dts/qcom-msm8660.dtsi| 115 +--- arch/arm/boot/dts/qcom-msm8960-cdp.dts | 10 ++ arch/arm/boot/dts/qcom-msm8960.dtsi| 176 +--- arch/arm/boot/dts/qcom-msm8974.dtsi| 49 +++ arch/arm/mach-qcom/board.c | 4 +- 13 files changed, 612 insertions(+), 161 deletions(-) create mode 100644 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts create mode 100644 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi create mode 100644 arch/arm/boot/dts/qcom-apq8064.dtsi create mode 100644 arch/arm/boot/dts/qcom-apq8084-mtp.dts create mode 100644 arch/arm/boot/dts/qcom-apq8084.dtsi -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom driver changes for v3.16-2
The following changes since commit 5d144e36b7c51612922fa05d37ff3a869261cc82: soc: qcom: Add GSBI driver (2014-05-23 11:38:04 -0500) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-drivers-for-3.16-2 for you to fetch changes up to 31964ffebbb958c6cf289c7c12edd7530d6221b9: tty: serial: msm: Remove direct access to GSBI (2014-05-29 11:06:20 -0500) Qualcomm ARM Based driver Updates for v3.16-2 * Updated MSM uart driver to not access GSBI control registers Andy Gross (1): tty: serial: msm: Remove direct access to GSBI drivers/tty/serial/msm_serial.c | 48 ++--- drivers/tty/serial/msm_serial.h | 5 - 2 files changed, 2 insertions(+), 51 deletions(-) -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom defconfig changes for v3.16-2
The following changes since commit f604759ec025e21d0c29a6d0addd53bbc60eb12e: ARM: config: Update msm_defconfig (2014-05-22 11:18:56 -0500) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-defconfig-for-3.16-2 for you to fetch changes up to 15ce39ade232bdac9fb788c66da9bcc7eb1a46a9: ARM: qcom: Enable GSBI driver in defconfig (2014-05-29 11:27:03 -0500) Qualcomm ARM Based defconfig Updates for v3.16-2 * Enable qcom GSBI driver Kumar Gala (1): ARM: qcom: Enable GSBI driver in defconfig arch/arm/configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[GIT PULL] qcom SoC changes for v3.16-2
The following changes since commit 87cfb00d666cca3abf36f755279cde1b27b9c377: ARM: qcom: Select PINCTRL by default for ARCH_QCOM (2014-05-22 11:50:42 -0500) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-soc-for-3.16-2 for you to fetch changes up to 2f528dd3b30c4351c0ece73b8bdc39753c02003b: ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084 (2014-05-29 11:14:28 -0500) Qualcomm ARM Based SoC Updates for v3.16-2 * Updated Kconfig DEBUG_QCOM_UARTDM help to include APQ8084 info Georgi Djakov (1): ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084 arch/arm/Kconfig.debug | 1 + 1 file changed, 1 insertion(+) -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: qcom: Enable GSBI driver in defconfig
On May 30, 2014, at 12:28 PM, Stephen Boyd sb...@codeaurora.org wrote: On 05/29/14 09:26, Kumar Gala wrote: Signed-off-by: Kumar Gala ga...@codeaurora.org --- arch/arm/configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index bfed753..42ebd72 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -131,6 +131,7 @@ CONFIG_RTC_CLASS=y CONFIG_DMADEVICES=y CONFIG_QCOM_BAM_DMA=y CONFIG_STAGING=y +CONFIG_QCOM_GSBI=y CONFIG_COMMON_CLK_QCOM=y CONFIG_MSM_GCC_8660=y CONFIG_MSM_MMCC_8960=y It would be good to do this in the multi-platform defconfig as well. Otherwise users of that defconfig (i.e. khilman's boot tester) will start failing to boot once the DT changes land. — Will do after 3.16-rc1, as nothing Kevin is booting uses the GSBI. Trying to decide if we should have some Kconfig dependency here. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] of: treat PCI config space as IORESOURCE_MEM type
On May 30, 2014, at 3:37 PM, Jason Gunthorpe jguntho...@obsidianresearch.com wrote: On Fri, May 30, 2014 at 02:41:17AM +0100, Liviu Dudau wrote: Agree, I'm only concerned that if this ECAM config space gets added to the list of pci_host_bridge windows it will be indistinguishable from IORESOURCE_MEM resources and pci_create_root_bus() will add it to the bus and allow devices present on that bus to be assigned addresses from that range. Which might not be what one wants for certain BARs. I wouldn't worry about supporting config in ranges. ECAM is the logical use for config ranges, but it isn't specified and probably will never be. Will's driver the is the only driver I've seen to support ECAM and it didn't use ranges. I expect with 64-bit parts we will see more use of ECAM, I think the reason its not used much is because of the address space it chews up, but that becomes less of an issue with LPAE or 64-bit parts with larger physical address spaces. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] of: treat PCI config space as IORESOURCE_MEM type
On May 29, 2014, at 8:41 PM, Liviu Dudau li...@dudau.co.uk wrote:
On Thu, May 29, 2014 at 07:29:31PM -0600, Bjorn Helgaas wrote:
On Thu, May 29, 2014 at 6:56 PM, Liviu Dudau li...@dudau.co.uk wrote:
On Thu, May 29, 2014 at 03:51:28PM -0500, Kumar Gala wrote:
On May 29, 2014, at 3:44 PM, Rob Herring robherri...@gmail.com wrote:
On Thu, May 29, 2014 at 11:03 AM, Kumar Gala ga...@codeaurora.org wrote:
If we have a PCI config space specified in something like a ranges
property we should treat it as memory type resource.
Config space should not be in ranges[1]. We have some cases that are,
but we don't want new ones.
For the cases we have I agree, however an ECAM based cfg seems completely
legit.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/of/address.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index cb4242a..4e7ee59 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -122,6 +122,9 @@ static unsigned int of_bus_pci_get_flags(const
__be32 *addr)
u32 w = be32_to_cpup(addr);
switch((w 24) 0x03) {
+ case 0x00: /* cfg space */
+ flags |= IORESOURCE_MEM;
+ break;
How would you then distinguish actual memory ranges?
One assumes you are still looking at pci_space as part of of_pci_range
That doesn't happen when you start scanning the bus. The existing code will
use the IORESOURCE_MEM for allocating memory space for devices, which is
not what you want. Did you test your patch on any PCI system? I'm pretty
sure that with my patch series that tries to make a generic framework for
host controllers this will fail.
We really need a IORESOURCE_CFG flag for this space.
Maybe, but I'm not convinced yet. The existing IORESOURCE_TYPE_BITS
types are for things that are mutually exclusive address spaces. I
think this discussion is about ECAM, where the CPU side is definitely
in the same address space (IORESOURCE_MEM) as RAM, APICs, host bridge
apertures, device MMIO, etc. The ECAM area must appear in the
iomem_resource tree so we avoid it when allocating other areas.
Agree, I'm only concerned that if this ECAM config space gets added to
the list of pci_host_bridge windows it will be indistinguishable from
IORESOURCE_MEM resources and pci_create_root_bus() will add it to the
bus and allow devices present on that bus to be assigned addresses from
that range. Which might not be what one wants for certain BARs.
I've had an aborted attempt to parse ECAM ranges in one version of my
series (granted, I was trying to hack the IORESOURCE_TYPE_BITS as well)
and things got horribly wrong quickly. I could give this patch a go with
my series tomorrow when I'm in the office and report back.
We need to fix the parsing code to be smarter about this case.
- k
--
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Re: [PATCH] of: treat PCI config space as IORESOURCE_MEM type
On May 29, 2014, at 3:44 PM, Rob Herring wrote:
> On Thu, May 29, 2014 at 11:03 AM, Kumar Gala wrote:
>> If we have a PCI config space specified in something like a ranges
>> property we should treat it as memory type resource.
>
> Config space should not be in ranges[1]. We have some cases that are,
> but we don't want new ones.
For the cases we have I agree, however an ECAM based cfg seems completely legit.
>> Signed-off-by: Kumar Gala
>> ---
>> drivers/of/address.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/of/address.c b/drivers/of/address.c
>> index cb4242a..4e7ee59 100644
>> --- a/drivers/of/address.c
>> +++ b/drivers/of/address.c
>> @@ -122,6 +122,9 @@ static unsigned int of_bus_pci_get_flags(const __be32
>> *addr)
>>u32 w = be32_to_cpup(addr);
>>
>>switch((w >> 24) & 0x03) {
>> + case 0x00: /* cfg space */
>> + flags |= IORESOURCE_MEM;
>> + break;
>
> How would you then distinguish actual memory ranges?
One assumes you are still looking at pci_space as part of of_pci_range
>
> Rob
>
> [1] http://www.spinics.net/lists/linux-pci/msg30585.html
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
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> More majordomo info at http://vger.kernel.org/majordomo-info.html
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
On May 29, 2014, at 11:30 AM, Jason Gunthorpe wrote: > On Thu, May 29, 2014 at 11:03:36AM -0500, Kumar Gala wrote: > >> Just because the kernel doesn’t handle this is NO reason to change >> the way the DT works. > > The OF specs do not specify how to process a config type ranges entry, > and we all mutually agreed that the only sane interpretation for such > a thing would be to describe an ECAM memory space so generic code > could potentially make use of it. > > Since designware is not ECAM it should not use config ranges. > > This has come up multiple times now, and the above is the consensus. > > Jason Well the designware controller does support ECAM, just that the current in kernel users don’t do cfg space that way. So do we continue to support the current users that use a cfg range for a non-ECAM space? Or break their DT and convert them to using regs? - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/3] mfd: devicetree: bindings: Add Qualcomm RPM DT binding
On May 29, 2014, at 11:19 AM, Srinivas Kandagatla
wrote:
>> += SUBDEVICES
>> +
>> +The RPM exposes resources to its subnodes. The below bindings specify the
>> set
>> +of valid subnodes that can operate on these resources.
>
> Why should these devices be on sub nodes?
>
> Any reason not to implement it like this,
>
> rpm: rpm@108000 {
> compatible = "qcom,rpm-msm8960";
> reg = <0x108000 0x1000 0x2011008 0x4>;
>
> interrupts = <0 19 0>, <0 21 0>, <0 22 0>;
> interrupt-names = "ack", "err", "wakeup";
> };
>
> pm8921_s1: pm8921-s1 {
> compatible = "qcom,rpm-pm8921-smps";
>
> regulator-min-microvolt = <1225000>;
> regulator-max-microvolt = <1225000>;
> regulator-always-on;
>
> qcom,rpm = < QCOM_RPM_PM8921_S1>;
> qcom,switch-mode-frequency = <320>;
> qcom,hpm-threshold = <10>;
> };
>
> This would simplify the driver code too and handle the interface neatly then
> depending on device hierarchy.
> rpm would be a interface library to the clients. Makes the drivers more
> independent, and re-usable if we do this way.
>
> ??
One reason to go with sub nodes is it creates a proper driver ordering
dependency as I assume rpm driver will end up calling of_platform_populate for
the sub nodes at the point that the RPM driver is ready. We could do this with
deferred probe but doing it explicitly is better in my opinion as it limits the
amount of time between when RPM is ready vs when the children can start doing
things
- k
--
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[PATCH] ARM: qcom: Enable GSBI driver in defconfig
Signed-off-by: Kumar Gala --- arch/arm/configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index bfed753..42ebd72 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -131,6 +131,7 @@ CONFIG_RTC_CLASS=y CONFIG_DMADEVICES=y CONFIG_QCOM_BAM_DMA=y CONFIG_STAGING=y +CONFIG_QCOM_GSBI=y CONFIG_COMMON_CLK_QCOM=y CONFIG_MSM_GCC_8660=y CONFIG_MSM_MMCC_8960=y -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [Patch v2 4/4] tty: serial: msm: Remove direct access to GSBI
On May 29, 2014, at 10:14 AM, Kumar Gala wrote: > > On Apr 24, 2014, at 11:31 AM, Andy Gross wrote: > >> This patch removes direct access of the GSBI registers. GSBI configuration >> should be done through the GSBI driver directly. >> >> Signed-off-by: Andy Gross >> --- >> drivers/tty/serial/msm_serial.c | 48 >> ++- >> drivers/tty/serial/msm_serial.h |5 >> 2 files changed, 2 insertions(+), 51 deletions(-) > > Greg, > > Any update on pulling this is for next? > > - k I’ll send it via arm-soc as the related patches are going via that path. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] of: treat PCI config space as IORESOURCE_MEM type
If we have a PCI config space specified in something like a ranges
property we should treat it as memory type resource.
Signed-off-by: Kumar Gala
---
drivers/of/address.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index cb4242a..4e7ee59 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -122,6 +122,9 @@ static unsigned int of_bus_pci_get_flags(const __be32 *addr)
u32 w = be32_to_cpup(addr);
switch((w >> 24) & 0x03) {
+ case 0x00: /* cfg space */
+ flags |= IORESOURCE_MEM;
+ break;
case 0x01:
flags |= IORESOURCE_IO;
break;
--
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Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
On May 29, 2014, at 10:18 AM, Liviu Dudau wrote: > On Thu, May 29, 2014 at 10:03:54AM -0500, Kumar Gala wrote: >> >> On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I wrote: >> >>> The configuration address space has so far been specified in *ranges*, >>> however it should be specified in *reg* making it a platform MEM resource. >>> Hence used 'platform_get_resource_*' API to get configuration address >>> space in the designware driver. >>> >>> Cc: Jason Gunthorpe >>> Cc: Bjorn Helgaas >>> Cc: Mohit Kumar >>> Cc: Jingoo Han >>> Cc: Marek Vasut >>> Cc: Arnd Bergmann >>> Signed-off-by: Kishon Vijay Abraham I >>> --- >>> .../devicetree/bindings/pci/designware-pcie.txt|1 + >>> drivers/pci/host/pcie-designware.c | 17 +++-- >>> 2 files changed, 16 insertions(+), 2 deletions(-) >> >> Why should the cfg space be defined in *reg* instead of ranges? > > Because what you end up using is a struct resource to represent the cfg space > and > the conversion between ranges and resources breaks down for CFG space (we > don't > have a flag in the resource flags to say this is CFG resource). Specifying it > as a *reg* property makes it a MEM resource and no special casing is needed. > > Best regards, > Liviu Just because the kernel doesn’t handle this is NO reason to change the way the DT works. We are probably better of changing of_bus_pci_get_flags() to set IORESOURCE_MEM for cfg type. Will send a patch for this. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: dts: qcom: Update msm8660 device trees
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8660-surf.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Add GSBI node and configuration of GSBI controller
Signed-off-by: Kumar Gala
---
v2:
* Added GSBI node
arch/arm/boot/dts/qcom-msm8660-surf.dts | 10 +++
arch/arm/boot/dts/qcom-msm8660.dtsi | 115 +++-
2 files changed, 78 insertions(+), 47 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts
b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 169bad9..45180ad 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -3,4 +3,14 @@
/ {
model = "Qualcomm MSM8660 SURF";
compatible = "qcom,msm8660-surf", "qcom,msm8660";
+
+ soc {
+ gsbi@19c0 {
+ status = "ok";
+ qcom,mode = ;
+ serial@19c4 {
+ status = "ok";
+ };
+ };
+ };
};
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi
b/arch/arm/boot/dts/qcom-msm8660.dtsi
index c52a9e9..53837aaa2f 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -3,6 +3,7 @@
/include/ "skeleton.dtsi"
#include
+#include
/ {
model = "Qualcomm MSM8660";
@@ -12,16 +13,18 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "qcom,scorpion";
- enable-method = "qcom,gcc-msm8660";
cpu@0 {
+ compatible = "qcom,scorpion";
+ enable-method = "qcom,gcc-msm8660";
device_type = "cpu";
reg = <0>;
next-level-cache = <>;
};
cpu@1 {
+ compatible = "qcom,scorpion";
+ enable-method = "qcom,gcc-msm8660";
device_type = "cpu";
reg = <1>;
next-level-cache = <>;
@@ -33,55 +36,73 @@
};
};
- intc: interrupt-controller@208 {
- compatible = "qcom,msm-8660-qgic";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = < 0x0208 0x1000 >,
- < 0x02081000 0x1000 >;
- };
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "simple-bus";
- timer@200 {
- compatible = "qcom,scss-timer", "qcom,msm-timer";
- interrupts = <1 0 0x301>,
-<1 1 0x301>,
-<1 2 0x301>;
- reg = <0x0200 0x100>;
- clock-frequency = <2700>,
- <32768>;
- cpu-offset = <0x4>;
- };
+ intc: interrupt-controller@208 {
+ compatible = "qcom,msm-8660-qgic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = < 0x0208 0x1000 >,
+ < 0x02081000 0x1000 >;
+ };
- msmgpio: gpio@80 {
- compatible = "qcom,msm-gpio";
- reg = <0x0080 0x4000>;
- gpio-controller;
- #gpio-cells = <2>;
- ngpio = <173>;
- interrupts = <0 16 0x4>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
+ timer@200 {
+ compatible = "qcom,scss-timer", "qcom,msm-timer";
+ interrupts = <1 0 0x301>,
+<1 1 0x301>,
+<1 2 0x301>;
+ reg = <0x0200 0x100>;
+ clock-frequency = <2700>,
+ <32768>;
+ cpu-offset = <0x4>;
+ };
- gcc: clock-controller@90 {
- compatible = "qcom,gcc-msm8660";
- #clock-cells = <1>;
- #reset-cells = <1>;
- reg = <0x90 0x4000>;
- };
+ msmgpio: gpio@80 {
+ compati
[PATCH v2] ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410 board device trees
Add basic APQ8064 SoC include device tree and support for basic booting on
the IFC6410 board. Also, keep dtb build list and qcom_dt_match in sorted
order.
Signed-off-by: Kumar Gala
---
v2:
* Fix gsbi controller reg address
arch/arm/boot/dts/Makefile | 8 +-
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 16 +++
arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 1 +
arch/arm/boot/dts/qcom-apq8064.dtsi| 170 +
arch/arm/mach-qcom/board.c | 3 +-
5 files changed, 194 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
create mode 100644 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
create mode 100644 arch/arm/boot/dts/qcom-apq8064.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 35c146f..c58624f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -291,9 +291,11 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
-dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
- qcom-msm8960-cdp.dtb \
- qcom-apq8074-dragonboard.dtb
+dtb-$(CONFIG_ARCH_QCOM) += \
+ qcom-apq8064-ifc6410.dtb \
+ qcom-apq8074-dragonboard.dtb \
+ qcom-msm8660-surf.dtb \
+ qcom-msm8960-cdp.dtb
dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
ste-hrefprev60-stuib.dtb \
ste-hrefprev60-tvk.dtb \
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
new file mode 100644
index 000..7c2441d
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -0,0 +1,16 @@
+#include "qcom-apq8064-v2.0.dtsi"
+
+/ {
+ model = "Qualcomm APQ8064/IFC6410";
+ compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
+
+ soc {
+ gsbi@1660 {
+ status = "ok";
+ qcom,mode = ;
+ serial@1664 {
+ status = "ok";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
new file mode 100644
index 000..935c394
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
@@ -0,0 +1 @@
+#include "qcom-apq8064.dtsi"
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
new file mode 100644
index 000..92bf793
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -0,0 +1,170 @@
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include
+#include
+
+/ {
+ model = "Qualcomm APQ8064";
+ compatible = "qcom,apq8064";
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <>;
+ qcom,acc = <>;
+ qcom,saw = <>;
+ };
+
+ cpu@1 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <>;
+ qcom,acc = <>;
+ qcom,saw = <>;
+ };
+
+ cpu@2 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
+ device_type = "cpu";
+ reg = <2>;
+ next-level-cache = <>;
+ qcom,acc = <>;
+ qcom,saw = <>;
+ };
+
+ cpu@3 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
+ device_type = "cpu";
+ reg = <3>;
+ next-level-cache = <>;
+ qcom,acc = <>;
+ qcom,saw = <>;
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ cpu-pmu {
+ compatible = "qcom,krait-pmu";
+ interrupts = <1 10 0x304>;
+ };
+
+ soc: soc {
+
[PATCH v2] ARM: dts: qcom: Update msm8960 device trees
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8960-cdp.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
binding spec
* Add GSBI node and configuration of GSBI controller
Signed-off-by: Kumar Gala
---
v2:
* Added GSBI node
arch/arm/boot/dts/qcom-msm8960-cdp.dts | 10 ++
arch/arm/boot/dts/qcom-msm8960.dtsi| 176 ++---
2 files changed, 108 insertions(+), 78 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index a58fb88..8f75cc4 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -3,4 +3,14 @@
/ {
model = "Qualcomm MSM8960 CDP";
compatible = "qcom,msm8960-cdp", "qcom,msm8960";
+
+ soc {
+ gsbi@1640 {
+ status = "ok";
+ qcom,mode = ;
+ serial@1644 {
+ status = "ok";
+ };
+ };
+ };
};
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi
b/arch/arm/boot/dts/qcom-msm8960.dtsi
index 997b7b9..5303e53 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -3,6 +3,7 @@
/include/ "skeleton.dtsi"
#include
+#include
/ {
model = "Qualcomm MSM8960";
@@ -13,10 +14,10 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <1 14 0x304>;
- compatible = "qcom,krait";
- enable-method = "qcom,kpss-acc-v1";
cpu@0 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <0>;
next-level-cache = <>;
@@ -25,6 +26,8 @@
};
cpu@1 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <1>;
next-level-cache = <>;
@@ -35,7 +38,6 @@
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
- interrupts = <0 2 0x4>;
};
};
@@ -45,91 +47,109 @@
qcom,no-pc-write;
};
- intc: interrupt-controller@200 {
- compatible = "qcom,msm-qgic2";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = < 0x0200 0x1000 >,
- < 0x02002000 0x1000 >;
- };
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@200 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x0200 0x1000>,
+ <0x02002000 0x1000>;
+ };
- timer@200a000 {
- compatible = "qcom,kpss-timer", "qcom,msm-timer";
- interrupts = <1 1 0x301>,
-<1 2 0x301>,
-<1 3 0x301>;
- reg = <0x0200a000 0x100>;
- clock-frequency = <2700>,
- <32768>;
- cpu-offset = <0x8>;
- };
+ timer@200a000 {
+ compatible = "qcom,kpss-timer", "qcom,msm-timer";
+ interrupts = <1 1 0x301>,
+<1 2 0x301>,
+<1 3 0x301>;
+ reg = <0x0200a000 0x100>;
+ clock-frequency = <2700>,
+ <32768>;
+ cpu-offset = <0x8>;
+ };
- msmgpio: gpio@80 {
- compatible = "qcom,msm-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- ngpio = <150>;
- interrupts = <0 16 0x4>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
Re: [Patch v2 4/4] tty: serial: msm: Remove direct access to GSBI
On Apr 24, 2014, at 11:31 AM, Andy Gross wrote:
> This patch removes direct access of the GSBI registers. GSBI configuration
> should be done through the GSBI driver directly.
>
> Signed-off-by: Andy Gross
> ---
> drivers/tty/serial/msm_serial.c | 48 ++-
> drivers/tty/serial/msm_serial.h |5
> 2 files changed, 2 insertions(+), 51 deletions(-)
Greg,
Any update on pulling this is for next?
- k
>
> diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
> index b5d779c..8901114 100644
> --- a/drivers/tty/serial/msm_serial.c
> +++ b/drivers/tty/serial/msm_serial.c
> @@ -45,7 +45,6 @@ struct msm_port {
> struct clk *clk;
> struct clk *pclk;
> unsigned intimr;
> - void __iomem*gsbi_base;
> int is_uartdm;
> unsigned intold_snap_state;
> };
> @@ -586,9 +585,7 @@ static const char *msm_type(struct uart_port *port)
> static void msm_release_port(struct uart_port *port)
> {
> struct platform_device *pdev = to_platform_device(port->dev);
> - struct msm_port *msm_port = UART_TO_MSM(port);
> struct resource *uart_resource;
> - struct resource *gsbi_resource;
> resource_size_t size;
>
> uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> @@ -599,28 +596,12 @@ static void msm_release_port(struct uart_port *port)
> release_mem_region(port->mapbase, size);
> iounmap(port->membase);
> port->membase = NULL;
> -
> - if (msm_port->gsbi_base) {
> - writel_relaxed(GSBI_PROTOCOL_IDLE,
> - msm_port->gsbi_base + GSBI_CONTROL);
> -
> - gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> - if (unlikely(!gsbi_resource))
> - return;
> -
> - size = resource_size(gsbi_resource);
> - release_mem_region(gsbi_resource->start, size);
> - iounmap(msm_port->gsbi_base);
> - msm_port->gsbi_base = NULL;
> - }
> }
>
> static int msm_request_port(struct uart_port *port)
> {
> - struct msm_port *msm_port = UART_TO_MSM(port);
> struct platform_device *pdev = to_platform_device(port->dev);
> struct resource *uart_resource;
> - struct resource *gsbi_resource;
> resource_size_t size;
> int ret;
>
> @@ -639,30 +620,8 @@ static int msm_request_port(struct uart_port *port)
> goto fail_release_port;
> }
>
> - gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> - /* Is this a GSBI-based port? */
> - if (gsbi_resource) {
> - size = resource_size(gsbi_resource);
> -
> - if (!request_mem_region(gsbi_resource->start, size,
> - "msm_serial")) {
> - ret = -EBUSY;
> - goto fail_release_port_membase;
> - }
> -
> - msm_port->gsbi_base = ioremap(gsbi_resource->start, size);
> - if (!msm_port->gsbi_base) {
> - ret = -EBUSY;
> - goto fail_release_gsbi;
> - }
> - }
> -
> return 0;
>
> -fail_release_gsbi:
> - release_mem_region(gsbi_resource->start, size);
> -fail_release_port_membase:
> - iounmap(port->membase);
> fail_release_port:
> release_mem_region(port->mapbase, size);
> return ret;
> @@ -670,7 +629,6 @@ fail_release_port:
>
> static void msm_config_port(struct uart_port *port, int flags)
> {
> - struct msm_port *msm_port = UART_TO_MSM(port);
> int ret;
> if (flags & UART_CONFIG_TYPE) {
> port->type = PORT_MSM;
> @@ -678,9 +636,6 @@ static void msm_config_port(struct uart_port *port, int
> flags)
> if (ret)
> return;
> }
> - if (msm_port->gsbi_base)
> - writel_relaxed(GSBI_PROTOCOL_UART,
> - msm_port->gsbi_base + GSBI_CONTROL);
> }
>
> static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
> @@ -976,6 +931,7 @@ static struct of_device_id msm_match_table[] = {
>
> static struct platform_driver msm_platform_driver = {
> .remove = msm_serial_remove,
> + .probe = msm_serial_probe,
> .driver = {
> .name = "msm_serial",
> .owner = THIS_MODULE,
> @@ -991,7 +947,7 @@ static int __init msm_serial_init(void)
> if (unlikely(ret))
> return ret;
>
> - ret = platform_driver_probe(_platform_driver, msm_serial_probe);
> + ret = platform_driver_register(_platform_driver);
> if (unlikely(ret))
> uart_unregister_driver(_uart_driver);
>
> diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h
> index 469fda5..a77cc76 100644
> --- a/drivers/tty/serial/msm_serial.h
> +++ b/drivers/tty/serial/msm_serial.h
> @@ -108,11
Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I wrote: > The configuration address space has so far been specified in *ranges*, > however it should be specified in *reg* making it a platform MEM resource. > Hence used 'platform_get_resource_*' API to get configuration address > space in the designware driver. > > Cc: Jason Gunthorpe > Cc: Bjorn Helgaas > Cc: Mohit Kumar > Cc: Jingoo Han > Cc: Marek Vasut > Cc: Arnd Bergmann > Signed-off-by: Kishon Vijay Abraham I > --- > .../devicetree/bindings/pci/designware-pcie.txt|1 + > drivers/pci/host/pcie-designware.c | 17 +++-- > 2 files changed, 16 insertions(+), 2 deletions(-) Why should the cfg space be defined in *reg* instead of ranges? - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote: The configuration address space has so far been specified in *ranges*, however it should be specified in *reg* making it a platform MEM resource. Hence used 'platform_get_resource_*' API to get configuration address space in the designware driver. Cc: Jason Gunthorpe jguntho...@obsidianresearch.com Cc: Bjorn Helgaas bhelg...@google.com Cc: Mohit Kumar mohit.ku...@st.com Cc: Jingoo Han jg1@samsung.com Cc: Marek Vasut ma...@denx.de Cc: Arnd Bergmann a...@arndb.de Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- .../devicetree/bindings/pci/designware-pcie.txt|1 + drivers/pci/host/pcie-designware.c | 17 +++-- 2 files changed, 16 insertions(+), 2 deletions(-) Why should the cfg space be defined in *reg* instead of ranges? - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [Patch v2 4/4] tty: serial: msm: Remove direct access to GSBI
On Apr 24, 2014, at 11:31 AM, Andy Gross agr...@codeaurora.org wrote:
This patch removes direct access of the GSBI registers. GSBI configuration
should be done through the GSBI driver directly.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/tty/serial/msm_serial.c | 48 ++-
drivers/tty/serial/msm_serial.h |5
2 files changed, 2 insertions(+), 51 deletions(-)
Greg,
Any update on pulling this is for next?
- k
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index b5d779c..8901114 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -45,7 +45,6 @@ struct msm_port {
struct clk *clk;
struct clk *pclk;
unsigned intimr;
- void __iomem*gsbi_base;
int is_uartdm;
unsigned intold_snap_state;
};
@@ -586,9 +585,7 @@ static const char *msm_type(struct uart_port *port)
static void msm_release_port(struct uart_port *port)
{
struct platform_device *pdev = to_platform_device(port-dev);
- struct msm_port *msm_port = UART_TO_MSM(port);
struct resource *uart_resource;
- struct resource *gsbi_resource;
resource_size_t size;
uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -599,28 +596,12 @@ static void msm_release_port(struct uart_port *port)
release_mem_region(port-mapbase, size);
iounmap(port-membase);
port-membase = NULL;
-
- if (msm_port-gsbi_base) {
- writel_relaxed(GSBI_PROTOCOL_IDLE,
- msm_port-gsbi_base + GSBI_CONTROL);
-
- gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- if (unlikely(!gsbi_resource))
- return;
-
- size = resource_size(gsbi_resource);
- release_mem_region(gsbi_resource-start, size);
- iounmap(msm_port-gsbi_base);
- msm_port-gsbi_base = NULL;
- }
}
static int msm_request_port(struct uart_port *port)
{
- struct msm_port *msm_port = UART_TO_MSM(port);
struct platform_device *pdev = to_platform_device(port-dev);
struct resource *uart_resource;
- struct resource *gsbi_resource;
resource_size_t size;
int ret;
@@ -639,30 +620,8 @@ static int msm_request_port(struct uart_port *port)
goto fail_release_port;
}
- gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- /* Is this a GSBI-based port? */
- if (gsbi_resource) {
- size = resource_size(gsbi_resource);
-
- if (!request_mem_region(gsbi_resource-start, size,
- msm_serial)) {
- ret = -EBUSY;
- goto fail_release_port_membase;
- }
-
- msm_port-gsbi_base = ioremap(gsbi_resource-start, size);
- if (!msm_port-gsbi_base) {
- ret = -EBUSY;
- goto fail_release_gsbi;
- }
- }
-
return 0;
-fail_release_gsbi:
- release_mem_region(gsbi_resource-start, size);
-fail_release_port_membase:
- iounmap(port-membase);
fail_release_port:
release_mem_region(port-mapbase, size);
return ret;
@@ -670,7 +629,6 @@ fail_release_port:
static void msm_config_port(struct uart_port *port, int flags)
{
- struct msm_port *msm_port = UART_TO_MSM(port);
int ret;
if (flags UART_CONFIG_TYPE) {
port-type = PORT_MSM;
@@ -678,9 +636,6 @@ static void msm_config_port(struct uart_port *port, int
flags)
if (ret)
return;
}
- if (msm_port-gsbi_base)
- writel_relaxed(GSBI_PROTOCOL_UART,
- msm_port-gsbi_base + GSBI_CONTROL);
}
static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
@@ -976,6 +931,7 @@ static struct of_device_id msm_match_table[] = {
static struct platform_driver msm_platform_driver = {
.remove = msm_serial_remove,
+ .probe = msm_serial_probe,
.driver = {
.name = msm_serial,
.owner = THIS_MODULE,
@@ -991,7 +947,7 @@ static int __init msm_serial_init(void)
if (unlikely(ret))
return ret;
- ret = platform_driver_probe(msm_platform_driver, msm_serial_probe);
+ ret = platform_driver_register(msm_platform_driver);
if (unlikely(ret))
uart_unregister_driver(msm_uart_driver);
diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h
index 469fda5..a77cc76 100644
--- a/drivers/tty/serial/msm_serial.h
+++ b/drivers/tty/serial/msm_serial.h
@@ -108,11 +108,6 @@
#define UART_ISR 0x0014
#define UART_ISR_TX_READY (1 7)
-#define
[PATCH v2] ARM: dts: qcom: Update msm8960 device trees
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8960-cdp.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
binding spec
* Add GSBI node and configuration of GSBI controller
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v2:
* Added GSBI node
arch/arm/boot/dts/qcom-msm8960-cdp.dts | 10 ++
arch/arm/boot/dts/qcom-msm8960.dtsi| 176 ++---
2 files changed, 108 insertions(+), 78 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index a58fb88..8f75cc4 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -3,4 +3,14 @@
/ {
model = Qualcomm MSM8960 CDP;
compatible = qcom,msm8960-cdp, qcom,msm8960;
+
+ soc {
+ gsbi@1640 {
+ status = ok;
+ qcom,mode = GSBI_PROT_I2C_UART;
+ serial@1644 {
+ status = ok;
+ };
+ };
+ };
};
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi
b/arch/arm/boot/dts/qcom-msm8960.dtsi
index 997b7b9..5303e53 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -3,6 +3,7 @@
/include/ skeleton.dtsi
#include dt-bindings/clock/qcom,gcc-msm8960.h
+#include dt-bindings/soc/qcom,gsbi.h
/ {
model = Qualcomm MSM8960;
@@ -13,10 +14,10 @@
#address-cells = 1;
#size-cells = 0;
interrupts = 1 14 0x304;
- compatible = qcom,krait;
- enable-method = qcom,kpss-acc-v1;
cpu@0 {
+ compatible = qcom,krait;
+ enable-method = qcom,kpss-acc-v1;
device_type = cpu;
reg = 0;
next-level-cache = L2;
@@ -25,6 +26,8 @@
};
cpu@1 {
+ compatible = qcom,krait;
+ enable-method = qcom,kpss-acc-v1;
device_type = cpu;
reg = 1;
next-level-cache = L2;
@@ -35,7 +38,6 @@
L2: l2-cache {
compatible = cache;
cache-level = 2;
- interrupts = 0 2 0x4;
};
};
@@ -45,91 +47,109 @@
qcom,no-pc-write;
};
- intc: interrupt-controller@200 {
- compatible = qcom,msm-qgic2;
- interrupt-controller;
- #interrupt-cells = 3;
- reg = 0x0200 0x1000 ,
- 0x02002000 0x1000 ;
- };
+ soc: soc {
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ compatible = simple-bus;
+
+ intc: interrupt-controller@200 {
+ compatible = qcom,msm-qgic2;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x0200 0x1000,
+ 0x02002000 0x1000;
+ };
- timer@200a000 {
- compatible = qcom,kpss-timer, qcom,msm-timer;
- interrupts = 1 1 0x301,
-1 2 0x301,
-1 3 0x301;
- reg = 0x0200a000 0x100;
- clock-frequency = 2700,
- 32768;
- cpu-offset = 0x8;
- };
+ timer@200a000 {
+ compatible = qcom,kpss-timer, qcom,msm-timer;
+ interrupts = 1 1 0x301,
+1 2 0x301,
+1 3 0x301;
+ reg = 0x0200a000 0x100;
+ clock-frequency = 2700,
+ 32768;
+ cpu-offset = 0x8;
+ };
- msmgpio: gpio@80 {
- compatible = qcom,msm-gpio;
- gpio-controller;
- #gpio-cells = 2;
- ngpio = 150;
- interrupts = 0 16 0x4;
- interrupt-controller;
- #interrupt-cells = 2;
- reg = 0x80 0x4000;
- };
+ msmgpio: gpio@80 {
+ compatible = qcom,msm-gpio;
+ gpio-controller;
+ #gpio-cells = 2;
+ ngpio = 150;
+ interrupts = 0 16 0x4;
+ interrupt-controller;
+ #interrupt-cells = 2;
+ reg = 0x80 0x4000
[PATCH] ARM: dts: qcom: Update msm8660 device trees
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8660-surf.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Add GSBI node and configuration of GSBI controller
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v2:
* Added GSBI node
arch/arm/boot/dts/qcom-msm8660-surf.dts | 10 +++
arch/arm/boot/dts/qcom-msm8660.dtsi | 115 +++-
2 files changed, 78 insertions(+), 47 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts
b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 169bad9..45180ad 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -3,4 +3,14 @@
/ {
model = Qualcomm MSM8660 SURF;
compatible = qcom,msm8660-surf, qcom,msm8660;
+
+ soc {
+ gsbi@19c0 {
+ status = ok;
+ qcom,mode = GSBI_PROT_I2C_UART;
+ serial@19c4 {
+ status = ok;
+ };
+ };
+ };
};
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi
b/arch/arm/boot/dts/qcom-msm8660.dtsi
index c52a9e9..53837aaa2f 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -3,6 +3,7 @@
/include/ skeleton.dtsi
#include dt-bindings/clock/qcom,gcc-msm8660.h
+#include dt-bindings/soc/qcom,gsbi.h
/ {
model = Qualcomm MSM8660;
@@ -12,16 +13,18 @@
cpus {
#address-cells = 1;
#size-cells = 0;
- compatible = qcom,scorpion;
- enable-method = qcom,gcc-msm8660;
cpu@0 {
+ compatible = qcom,scorpion;
+ enable-method = qcom,gcc-msm8660;
device_type = cpu;
reg = 0;
next-level-cache = L2;
};
cpu@1 {
+ compatible = qcom,scorpion;
+ enable-method = qcom,gcc-msm8660;
device_type = cpu;
reg = 1;
next-level-cache = L2;
@@ -33,55 +36,73 @@
};
};
- intc: interrupt-controller@208 {
- compatible = qcom,msm-8660-qgic;
- interrupt-controller;
- #interrupt-cells = 3;
- reg = 0x0208 0x1000 ,
- 0x02081000 0x1000 ;
- };
+ soc: soc {
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ compatible = simple-bus;
- timer@200 {
- compatible = qcom,scss-timer, qcom,msm-timer;
- interrupts = 1 0 0x301,
-1 1 0x301,
-1 2 0x301;
- reg = 0x0200 0x100;
- clock-frequency = 2700,
- 32768;
- cpu-offset = 0x4;
- };
+ intc: interrupt-controller@208 {
+ compatible = qcom,msm-8660-qgic;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x0208 0x1000 ,
+ 0x02081000 0x1000 ;
+ };
- msmgpio: gpio@80 {
- compatible = qcom,msm-gpio;
- reg = 0x0080 0x4000;
- gpio-controller;
- #gpio-cells = 2;
- ngpio = 173;
- interrupts = 0 16 0x4;
- interrupt-controller;
- #interrupt-cells = 2;
- };
+ timer@200 {
+ compatible = qcom,scss-timer, qcom,msm-timer;
+ interrupts = 1 0 0x301,
+1 1 0x301,
+1 2 0x301;
+ reg = 0x0200 0x100;
+ clock-frequency = 2700,
+ 32768;
+ cpu-offset = 0x4;
+ };
- gcc: clock-controller@90 {
- compatible = qcom,gcc-msm8660;
- #clock-cells = 1;
- #reset-cells = 1;
- reg = 0x90 0x4000;
- };
+ msmgpio: gpio@80 {
+ compatible = qcom,msm-gpio;
+ reg = 0x0080 0x4000;
+ gpio-controller;
+ #gpio-cells = 2;
+ ngpio = 173;
+ interrupts = 0 16 0x4;
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
- serial@19c4 {
- compatible = qcom,msm-uartdm-v1.3, qcom,msm-uartdm;
- reg
[PATCH v2] ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410 board device trees
Add basic APQ8064 SoC include device tree and support for basic booting on
the IFC6410 board. Also, keep dtb build list and qcom_dt_match in sorted
order.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v2:
* Fix gsbi controller reg address
arch/arm/boot/dts/Makefile | 8 +-
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 16 +++
arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 1 +
arch/arm/boot/dts/qcom-apq8064.dtsi| 170 +
arch/arm/mach-qcom/board.c | 3 +-
5 files changed, 194 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
create mode 100644 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
create mode 100644 arch/arm/boot/dts/qcom-apq8064.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 35c146f..c58624f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -291,9 +291,11 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
-dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
- qcom-msm8960-cdp.dtb \
- qcom-apq8074-dragonboard.dtb
+dtb-$(CONFIG_ARCH_QCOM) += \
+ qcom-apq8064-ifc6410.dtb \
+ qcom-apq8074-dragonboard.dtb \
+ qcom-msm8660-surf.dtb \
+ qcom-msm8960-cdp.dtb
dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
ste-hrefprev60-stuib.dtb \
ste-hrefprev60-tvk.dtb \
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
new file mode 100644
index 000..7c2441d
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -0,0 +1,16 @@
+#include qcom-apq8064-v2.0.dtsi
+
+/ {
+ model = Qualcomm APQ8064/IFC6410;
+ compatible = qcom,apq8064-ifc6410, qcom,apq8064;
+
+ soc {
+ gsbi@1660 {
+ status = ok;
+ qcom,mode = GSBI_PROT_I2C_UART;
+ serial@1664 {
+ status = ok;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
new file mode 100644
index 000..935c394
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
@@ -0,0 +1 @@
+#include qcom-apq8064.dtsi
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
new file mode 100644
index 000..92bf793
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -0,0 +1,170 @@
+/dts-v1/;
+
+#include skeleton.dtsi
+#include dt-bindings/clock/qcom,gcc-msm8960.h
+#include dt-bindings/soc/qcom,gsbi.h
+
+/ {
+ model = Qualcomm APQ8064;
+ compatible = qcom,apq8064;
+ interrupt-parent = intc;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ compatible = qcom,krait;
+ enable-method = qcom,kpss-acc-v1;
+ device_type = cpu;
+ reg = 0;
+ next-level-cache = L2;
+ qcom,acc = acc0;
+ qcom,saw = saw0;
+ };
+
+ cpu@1 {
+ compatible = qcom,krait;
+ enable-method = qcom,kpss-acc-v1;
+ device_type = cpu;
+ reg = 1;
+ next-level-cache = L2;
+ qcom,acc = acc1;
+ qcom,saw = saw1;
+ };
+
+ cpu@2 {
+ compatible = qcom,krait;
+ enable-method = qcom,kpss-acc-v1;
+ device_type = cpu;
+ reg = 2;
+ next-level-cache = L2;
+ qcom,acc = acc2;
+ qcom,saw = saw2;
+ };
+
+ cpu@3 {
+ compatible = qcom,krait;
+ enable-method = qcom,kpss-acc-v1;
+ device_type = cpu;
+ reg = 3;
+ next-level-cache = L2;
+ qcom,acc = acc3;
+ qcom,saw = saw3;
+ };
+
+ L2: l2-cache {
+ compatible = cache;
+ cache-level = 2;
+ };
+ };
+
+ cpu-pmu {
+ compatible = qcom,krait-pmu;
+ interrupts = 1 10 0x304;
+ };
+
+ soc: soc {
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ compatible = simple-bus;
+
+ intc: interrupt-controller@200 {
+ compatible = qcom,msm-qgic2;
+ interrupt-controller
[PATCH] of: treat PCI config space as IORESOURCE_MEM type
If we have a PCI config space specified in something like a ranges
property we should treat it as memory type resource.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/of/address.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index cb4242a..4e7ee59 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -122,6 +122,9 @@ static unsigned int of_bus_pci_get_flags(const __be32 *addr)
u32 w = be32_to_cpup(addr);
switch((w 24) 0x03) {
+ case 0x00: /* cfg space */
+ flags |= IORESOURCE_MEM;
+ break;
case 0x01:
flags |= IORESOURCE_IO;
break;
--
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Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
On May 29, 2014, at 10:18 AM, Liviu Dudau li...@dudau.co.uk wrote: On Thu, May 29, 2014 at 10:03:54AM -0500, Kumar Gala wrote: On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote: The configuration address space has so far been specified in *ranges*, however it should be specified in *reg* making it a platform MEM resource. Hence used 'platform_get_resource_*' API to get configuration address space in the designware driver. Cc: Jason Gunthorpe jguntho...@obsidianresearch.com Cc: Bjorn Helgaas bhelg...@google.com Cc: Mohit Kumar mohit.ku...@st.com Cc: Jingoo Han jg1@samsung.com Cc: Marek Vasut ma...@denx.de Cc: Arnd Bergmann a...@arndb.de Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- .../devicetree/bindings/pci/designware-pcie.txt|1 + drivers/pci/host/pcie-designware.c | 17 +++-- 2 files changed, 16 insertions(+), 2 deletions(-) Why should the cfg space be defined in *reg* instead of ranges? Because what you end up using is a struct resource to represent the cfg space and the conversion between ranges and resources breaks down for CFG space (we don't have a flag in the resource flags to say this is CFG resource). Specifying it as a *reg* property makes it a MEM resource and no special casing is needed. Best regards, Liviu Just because the kernel doesn’t handle this is NO reason to change the way the DT works. We are probably better of changing of_bus_pci_get_flags() to set IORESOURCE_MEM for cfg type. Will send a patch for this. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [Patch v2 4/4] tty: serial: msm: Remove direct access to GSBI
On May 29, 2014, at 10:14 AM, Kumar Gala ga...@codeaurora.org wrote: On Apr 24, 2014, at 11:31 AM, Andy Gross agr...@codeaurora.org wrote: This patch removes direct access of the GSBI registers. GSBI configuration should be done through the GSBI driver directly. Signed-off-by: Andy Gross agr...@codeaurora.org --- drivers/tty/serial/msm_serial.c | 48 ++- drivers/tty/serial/msm_serial.h |5 2 files changed, 2 insertions(+), 51 deletions(-) Greg, Any update on pulling this is for next? - k I’ll send it via arm-soc as the related patches are going via that path. - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: qcom: Enable GSBI driver in defconfig
Signed-off-by: Kumar Gala ga...@codeaurora.org --- arch/arm/configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index bfed753..42ebd72 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -131,6 +131,7 @@ CONFIG_RTC_CLASS=y CONFIG_DMADEVICES=y CONFIG_QCOM_BAM_DMA=y CONFIG_STAGING=y +CONFIG_QCOM_GSBI=y CONFIG_COMMON_CLK_QCOM=y CONFIG_MSM_GCC_8660=y CONFIG_MSM_MMCC_8960=y -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/3] mfd: devicetree: bindings: Add Qualcomm RPM DT binding
On May 29, 2014, at 11:19 AM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
+= SUBDEVICES
+
+The RPM exposes resources to its subnodes. The below bindings specify the
set
+of valid subnodes that can operate on these resources.
Why should these devices be on sub nodes?
Any reason not to implement it like this,
rpm: rpm@108000 {
compatible = qcom,rpm-msm8960;
reg = 0x108000 0x1000 0x2011008 0x4;
interrupts = 0 19 0, 0 21 0, 0 22 0;
interrupt-names = ack, err, wakeup;
};
pm8921_s1: pm8921-s1 {
compatible = qcom,rpm-pm8921-smps;
regulator-min-microvolt = 1225000;
regulator-max-microvolt = 1225000;
regulator-always-on;
qcom,rpm = rpm QCOM_RPM_PM8921_S1;
qcom,switch-mode-frequency = 320;
qcom,hpm-threshold = 10;
};
This would simplify the driver code too and handle the interface neatly then
depending on device hierarchy.
rpm would be a interface library to the clients. Makes the drivers more
independent, and re-usable if we do this way.
??
One reason to go with sub nodes is it creates a proper driver ordering
dependency as I assume rpm driver will end up calling of_platform_populate for
the sub nodes at the point that the RPM driver is ready. We could do this with
deferred probe but doing it explicitly is better in my opinion as it limits the
amount of time between when RPM is ready vs when the children can start doing
things
- k
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Re: [PATCH v2 03/18] PCI: designware: Configuration space should be specified in 'reg'
On May 29, 2014, at 11:30 AM, Jason Gunthorpe jguntho...@obsidianresearch.com wrote: On Thu, May 29, 2014 at 11:03:36AM -0500, Kumar Gala wrote: Just because the kernel doesn’t handle this is NO reason to change the way the DT works. The OF specs do not specify how to process a config type ranges entry, and we all mutually agreed that the only sane interpretation for such a thing would be to describe an ECAM memory space so generic code could potentially make use of it. Since designware is not ECAM it should not use config ranges. This has come up multiple times now, and the above is the consensus. Jason Well the designware controller does support ECAM, just that the current in kernel users don’t do cfg space that way. So do we continue to support the current users that use a cfg range for a non-ECAM space? Or break their DT and convert them to using regs? - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] of: treat PCI config space as IORESOURCE_MEM type
On May 29, 2014, at 3:44 PM, Rob Herring robherri...@gmail.com wrote:
On Thu, May 29, 2014 at 11:03 AM, Kumar Gala ga...@codeaurora.org wrote:
If we have a PCI config space specified in something like a ranges
property we should treat it as memory type resource.
Config space should not be in ranges[1]. We have some cases that are,
but we don't want new ones.
For the cases we have I agree, however an ECAM based cfg seems completely legit.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/of/address.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index cb4242a..4e7ee59 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -122,6 +122,9 @@ static unsigned int of_bus_pci_get_flags(const __be32
*addr)
u32 w = be32_to_cpup(addr);
switch((w 24) 0x03) {
+ case 0x00: /* cfg space */
+ flags |= IORESOURCE_MEM;
+ break;
How would you then distinguish actual memory ranges?
One assumes you are still looking at pci_space as part of of_pci_range
Rob
[1] http://www.spinics.net/lists/linux-pci/msg30585.html
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Re: [PATCH] ARM: dts: qcom: Update msm8960 device trees
On May 28, 2014, at 3:09 PM, Josh Cartwright wrote:
> On Wed, May 28, 2014 at 01:27:23PM -0500, Kumar Gala wrote:
>> * Move SoC peripherals into an SoC container node
>> * Move serial enabling into board file (qcom-msm8960-cdp.dts)
>> * Cleanup cpu node to match binding spec, enable-method and compatible
>> should be per cpu, not part of the container
>> * Drop interrupts property from l2-cache node as its not part of the
>> binding spec
>>
>> Signed-off-by: Kumar Gala
>> ---
>> arch/arm/boot/dts/qcom-msm8960-cdp.dts | 6 ++
>> arch/arm/boot/dts/qcom-msm8960.dtsi| 165
>> +
>> 2 files changed, 93 insertions(+), 78 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
>> b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
>> index a58fb88..8e77ed7 100644
>> --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
>> +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
>> @@ -3,4 +3,10 @@
>> / {
>> model = "Qualcomm MSM8960 CDP";
>> compatible = "qcom,msm8960-cdp", "qcom,msm8960";
>> +
>> +soc {
>> +serial@1644 {
>> +status = "ok";
>> +};
>> +};
>> };
>
> Is now the time put these serial nodes under a GSBI parent node?
Yeah, I’ll make the change to the 8960 & 8660 dts
- k
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[PATCH v2] ARM: dts: qcom: Update msm8974/apq8074 device trees
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-apq8074-dragonboard.dts)
* Move spi pinctrl into board file
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
binding spec
* Move timer node out of SoC container
Signed-off-by: Kumar Gala
---
v2:
* Move timer node out of SoC container
arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 28 ++-
arch/arm/boot/dts/qcom-msm8974.dtsi| 49 ++
2 files changed, 45 insertions(+), 32 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index 92320c4..b4dfb01 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -4,7 +4,11 @@
model = "Qualcomm APQ8074 Dragonboard";
compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
- soc: soc {
+ soc {
+ serial@f991e000 {
+ status = "ok";
+ };
+
sdhci@f9824900 {
bus-width = <8>;
non-removable;
@@ -15,5 +19,27 @@
cd-gpios = < 62 0x1>;
bus-width = <4>;
};
+
+
+ pinctrl@fd51 {
+ spi8_default: spi8_default {
+ mosi {
+ pins = "gpio45";
+ function = "blsp_spi8";
+ };
+ miso {
+ pins = "gpio46";
+ function = "blsp_spi8";
+ };
+ cs {
+ pins = "gpio47";
+ function = "blsp_spi8";
+ };
+ clk {
+ pins = "gpio48";
+ function = "blsp_spi8";
+ };
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index c530a33..69dca2a 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -13,10 +13,10 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <1 9 0xf04>;
- compatible = "qcom,krait";
- enable-method = "qcom,kpss-acc-v2";
cpu@0 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <0>;
next-level-cache = <>;
@@ -24,6 +24,8 @@
};
cpu@1 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <1>;
next-level-cache = <>;
@@ -31,6 +33,8 @@
};
cpu@2 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <2>;
next-level-cache = <>;
@@ -38,6 +42,8 @@
};
cpu@3 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <3>;
next-level-cache = <>;
@@ -47,7 +53,6 @@
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
- interrupts = <0 2 0x4>;
qcom,saw = <_l2>;
};
};
@@ -57,6 +62,15 @@
interrupts = <1 7 0xf04>;
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 2 0xf08>,
+<1 3 0xf08>,
+<1 4 0xf08>,
+<1 1 0xf08>;
+ clock-frequency = <1920>;
+
[PATCH] ARM: dts: qcom: Update msm8974/apq8074 device trees
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-apq8074-dragonboard.dts)
* Move spi pinctrl into board file
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
binding spec
Signed-off-by: Kumar Gala
---
arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 28 ++-
arch/arm/boot/dts/qcom-msm8974.dtsi| 31 --
2 files changed, 36 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index 92320c4..b4dfb01 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -4,7 +4,11 @@
model = "Qualcomm APQ8074 Dragonboard";
compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
- soc: soc {
+ soc {
+ serial@f991e000 {
+ status = "ok";
+ };
+
sdhci@f9824900 {
bus-width = <8>;
non-removable;
@@ -15,5 +19,27 @@
cd-gpios = < 62 0x1>;
bus-width = <4>;
};
+
+
+ pinctrl@fd51 {
+ spi8_default: spi8_default {
+ mosi {
+ pins = "gpio45";
+ function = "blsp_spi8";
+ };
+ miso {
+ pins = "gpio46";
+ function = "blsp_spi8";
+ };
+ cs {
+ pins = "gpio47";
+ function = "blsp_spi8";
+ };
+ clk {
+ pins = "gpio48";
+ function = "blsp_spi8";
+ };
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/boot/dts/qcom-msm8974.dtsi
index c530a33..b0716c1 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -13,10 +13,10 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <1 9 0xf04>;
- compatible = "qcom,krait";
- enable-method = "qcom,kpss-acc-v2";
cpu@0 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <0>;
next-level-cache = <>;
@@ -24,6 +24,8 @@
};
cpu@1 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <1>;
next-level-cache = <>;
@@ -31,6 +33,8 @@
};
cpu@2 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <2>;
next-level-cache = <>;
@@ -38,6 +42,8 @@
};
cpu@3 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <3>;
next-level-cache = <>;
@@ -47,7 +53,6 @@
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
- interrupts = <0 2 0x4>;
qcom,saw = <_l2>;
};
};
@@ -190,6 +195,7 @@
interrupts = <0 108 0x0>;
clocks = < GCC_BLSP1_UART2_APPS_CLK>, <
GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ status = "disabled";
};
sdhci@f9824900 {
@@ -229,25 +235,6 @@
interrupt-controller;
#interrupt-cells = <2>;
[PATCH] ARM: dts: qcom: Update msm8960 device trees
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8960-cdp.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
binding spec
Signed-off-by: Kumar Gala
---
arch/arm/boot/dts/qcom-msm8960-cdp.dts | 6 ++
arch/arm/boot/dts/qcom-msm8960.dtsi| 165 +
2 files changed, 93 insertions(+), 78 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index a58fb88..8e77ed7 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -3,4 +3,10 @@
/ {
model = "Qualcomm MSM8960 CDP";
compatible = "qcom,msm8960-cdp", "qcom,msm8960";
+
+ soc {
+ serial@1644 {
+ status = "ok";
+ };
+ };
};
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi
b/arch/arm/boot/dts/qcom-msm8960.dtsi
index 997b7b9..c38e54c 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -13,10 +13,10 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <1 14 0x304>;
- compatible = "qcom,krait";
- enable-method = "qcom,kpss-acc-v1";
cpu@0 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <0>;
next-level-cache = <>;
@@ -25,6 +25,8 @@
};
cpu@1 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <1>;
next-level-cache = <>;
@@ -35,7 +37,6 @@
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
- interrupts = <0 2 0x4>;
};
};
@@ -45,91 +46,99 @@
qcom,no-pc-write;
};
- intc: interrupt-controller@200 {
- compatible = "qcom,msm-qgic2";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = < 0x0200 0x1000 >,
- < 0x02002000 0x1000 >;
- };
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@200 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x0200 0x1000>,
+ <0x02002000 0x1000>;
+ };
- timer@200a000 {
- compatible = "qcom,kpss-timer", "qcom,msm-timer";
- interrupts = <1 1 0x301>,
-<1 2 0x301>,
-<1 3 0x301>;
- reg = <0x0200a000 0x100>;
- clock-frequency = <2700>,
- <32768>;
- cpu-offset = <0x8>;
- };
+ timer@200a000 {
+ compatible = "qcom,kpss-timer", "qcom,msm-timer";
+ interrupts = <1 1 0x301>,
+<1 2 0x301>,
+<1 3 0x301>;
+ reg = <0x0200a000 0x100>;
+ clock-frequency = <2700>,
+ <32768>;
+ cpu-offset = <0x8>;
+ };
- msmgpio: gpio@80 {
- compatible = "qcom,msm-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- ngpio = <150>;
- interrupts = <0 16 0x4>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x80 0x4000>;
- };
+ msmgpio: gpio@80 {
+ compatible = "qcom,msm-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpio = <150>;
+ interrupts = <0 16 0x4>;
+
[PATCH] ARM: dts: qcom: Update msm8660 device trees
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8660-surf.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
Signed-off-by: Kumar Gala
---
arch/arm/boot/dts/qcom-msm8660-surf.dts | 6 ++
arch/arm/boot/dts/qcom-msm8660.dtsi | 104 +---
2 files changed, 63 insertions(+), 47 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts
b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 169bad9..13f5a78 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -3,4 +3,10 @@
/ {
model = "Qualcomm MSM8660 SURF";
compatible = "qcom,msm8660-surf", "qcom,msm8660";
+
+ soc {
+ serial@19c4 {
+ status = "ok";
+ };
+ };
};
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi
b/arch/arm/boot/dts/qcom-msm8660.dtsi
index c52a9e9..41bc38b 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -12,16 +12,18 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "qcom,scorpion";
- enable-method = "qcom,gcc-msm8660";
cpu@0 {
+ compatible = "qcom,scorpion";
+ enable-method = "qcom,gcc-msm8660";
device_type = "cpu";
reg = <0>;
next-level-cache = <>;
};
cpu@1 {
+ compatible = "qcom,scorpion";
+ enable-method = "qcom,gcc-msm8660";
device_type = "cpu";
reg = <1>;
next-level-cache = <>;
@@ -33,55 +35,63 @@
};
};
- intc: interrupt-controller@208 {
- compatible = "qcom,msm-8660-qgic";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = < 0x0208 0x1000 >,
- < 0x02081000 0x1000 >;
- };
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "simple-bus";
- timer@200 {
- compatible = "qcom,scss-timer", "qcom,msm-timer";
- interrupts = <1 0 0x301>,
-<1 1 0x301>,
-<1 2 0x301>;
- reg = <0x0200 0x100>;
- clock-frequency = <2700>,
- <32768>;
- cpu-offset = <0x4>;
- };
+ intc: interrupt-controller@208 {
+ compatible = "qcom,msm-8660-qgic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = < 0x0208 0x1000 >,
+ < 0x02081000 0x1000 >;
+ };
- msmgpio: gpio@80 {
- compatible = "qcom,msm-gpio";
- reg = <0x0080 0x4000>;
- gpio-controller;
- #gpio-cells = <2>;
- ngpio = <173>;
- interrupts = <0 16 0x4>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
+ timer@200 {
+ compatible = "qcom,scss-timer", "qcom,msm-timer";
+ interrupts = <1 0 0x301>,
+<1 1 0x301>,
+<1 2 0x301>;
+ reg = <0x0200 0x100>;
+ clock-frequency = <2700>,
+ <32768>;
+ cpu-offset = <0x4>;
+ };
- gcc: clock-controller@90 {
- compatible = "qcom,gcc-msm8660";
- #clock-cells = <1>;
- #reset-cells = <1>;
- reg = <0x90 0x4000>;
- };
+ msmgpio: gpio@80 {
+ compatible = "qcom,msm-gpio";
+ reg = <0x0080 0x4000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpio = <173>;
+ interrupts = <0 16 0x4>;
+ interrupt-controller;
+ #interrupt-cells = &
[PATCH v3] ARM: qcom: Add initial APQ8064 SoC and IFC6410 board device trees
Add basic APQ8064 SoC include device tree and support for basic booting on
the IFC6410 board. Also, keep dtb build list and qcom_dt_match in sorted
order.
Signed-off-by: Kumar Gala
---
v3:
* Cleanup cpu node to have compatible & enable-method per node and
not in the container
* Dropped l2-cache interrupt prop as its not part of any binding
* Cleanup reg whitespace
v2:
* created a v2.0 apq8064.dtsi to handle differences in Si rev in future
* changed /include/ to #include
* added PMU node
* dropped interrupts from cpus node, not currently part of binding
arch/arm/boot/dts/Makefile | 8 +-
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 16 +++
arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 1 +
arch/arm/boot/dts/qcom-apq8064.dtsi| 170 +
arch/arm/mach-qcom/board.c | 3 +-
5 files changed, 194 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
create mode 100644 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
create mode 100644 arch/arm/boot/dts/qcom-apq8064.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 35c146f..c58624f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -291,9 +291,11 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
-dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
- qcom-msm8960-cdp.dtb \
- qcom-apq8074-dragonboard.dtb
+dtb-$(CONFIG_ARCH_QCOM) += \
+ qcom-apq8064-ifc6410.dtb \
+ qcom-apq8074-dragonboard.dtb \
+ qcom-msm8660-surf.dtb \
+ qcom-msm8960-cdp.dtb
dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
ste-hrefprev60-stuib.dtb \
ste-hrefprev60-tvk.dtb \
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
new file mode 100644
index 000..7c2441d
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -0,0 +1,16 @@
+#include "qcom-apq8064-v2.0.dtsi"
+
+/ {
+ model = "Qualcomm APQ8064/IFC6410";
+ compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
+
+ soc {
+ gsbi@1660 {
+ status = "ok";
+ qcom,mode = ;
+ serial@1664 {
+ status = "ok";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
new file mode 100644
index 000..935c394
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
@@ -0,0 +1 @@
+#include "qcom-apq8064.dtsi"
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
new file mode 100644
index 000..e8a3423
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -0,0 +1,170 @@
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include
+#include
+
+/ {
+ model = "Qualcomm APQ8064";
+ compatible = "qcom,apq8064";
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <>;
+ qcom,acc = <>;
+ qcom,saw = <>;
+ };
+
+ cpu@1 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <>;
+ qcom,acc = <>;
+ qcom,saw = <>;
+ };
+
+ cpu@2 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
+ device_type = "cpu";
+ reg = <2>;
+ next-level-cache = <>;
+ qcom,acc = <>;
+ qcom,saw = <>;
+ };
+
+ cpu@3 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
+ device_type = "cpu";
+ reg = <3>;
+ next-level-cache = <>;
+ qcom,acc = <>;
+ qcom,saw = <>;
+
Re: [PATCH 0/3] Qualcomm Resource Power Manager driver
On May 28, 2014, at 11:59 AM, Bjorn Andersson wrote: > On Wed, May 28, 2014 at 9:23 AM, Kumar Gala wrote: >> >> On May 27, 2014, at 12:28 PM, Bjorn Andersson >> wrote: >> >>> This series adds a regulator driver for the Resource Power Manager found in >>> Qualcomm 8660, 8960 and 8064 based devices. >>> >>> The RPM driver exposes resources to its child devices, that can be accessed >>> to >>> implement drivers for the regulators, clocks and bus frequency control >>> that's >>> owned by the RPM in these devices. >> >> Rather than adding yet another mfd driver, how about we put this in >> drivers/soc/qcom as a much better location for the low level rpm code. Some >> code already merged in arm-soc for creation of drivers/soc/qcom/ > > Hi Kumar, > > I do see rpm as somewhat equivalent to a pmic and that was why I > followed suite and put it in mfd, but I can of course move it if you > prefer. > > > Lately I've been working on rpm, rpm-smd, smem, smd, smsm, smp2p > patches for mainline. > It could be argued that smd is a bus and should go in drivers/bus, but > for the rest I fear that we just created drivers/soc/qcom as another > dumping ground for things; a "Qualcomm specific drivers/mfd". > > But maybe that is the purpose of it ;) It is the purpose so that as we see common patterns between either drivers/soc/ we can refactor in the future. However, we need to all a little time for those patterns to emerge rather than shoe horning in drivers into places that don’t make sense. > > If I move the rpm driver, are there any conclusion to where I should > move the dt binding documentation? devicetree/bindings/soc/qcom include/dt-bindings/soc > > Regards, > Bjorn - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/3] mfd: devicetree: bindings: Add Qualcomm RPM DT binding
On May 27, 2014, at 12:28 PM, Bjorn Andersson wrote: > Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660, 8960 > and 8064 based devices. The binding currently describes the rpm itself and the > regulator subnodes. > > Signed-off-by: Bjorn Andersson > --- > Documentation/devicetree/bindings/mfd/qcom,rpm.txt | 284 + > include/dt-bindings/mfd/qcom_rpm.h | 142 +++ > 2 files changed, 426 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mfd/qcom,rpm.txt > create mode 100644 include/dt-bindings/mfd/qcom_rpm.h > > diff --git a/Documentation/devicetree/bindings/mfd/qcom,rpm.txt > b/Documentation/devicetree/bindings/mfd/qcom,rpm.txt > new file mode 100644 > index 000..3908a5d > --- /dev/null > +++ b/Documentation/devicetree/bindings/mfd/qcom,rpm.txt > @@ -0,0 +1,284 @@ > +Qualcomm Resource Power Manager (RPM) > + > +This driver is used to interface with the Resource Power Manager (RPM) found > in > +various Qualcomm platforms. The RPM allows each component in the system to > vote > +for state of the system resources, such as clocks, regulators and bus > +frequencies. > + > +- compatible: > + Usage: required > + Value type: > + Definition: must be one of: > + "qcom,rpm-apq8064" > + "qcom,rpm-msm8660" > + "qcom,rpm-msm8960" > + > +- reg: > + Usage: required > + Value type: > + Definition: two entries specifying the RPM's message ram and ipc > register > + > +- reg-names: > + Usage: required > + Value type: > + Definition: must contain the following, in order: > + "msg_ram" > + “ipc" If order maters, it should be on reg not reg-names. If order doesn’t mater than this should say the names should match the reg > + > +- interrupts: > + Usage: required > + Value type: > + Definition: three entries specifying the RPM's: > + 1. acknowledgement interrupt > + 2. error interrupt > + 3. wakeup interrupt > + > +- interrupt-names: > + Usage: required > + Value type: > + Definition: must be the three strings "ack", "err" and "wakeup", in > order again, if order maters it should be with the interrupts prop, not the name. > + > +- #address-cells: > + Usage: required > + Value type: > + Definition: must be 1 > + > +- #size-cells: > + Usage: required > + Value type: > + Definition: must be 0 > + > + > += SUBDEVICES > + > +The RPM exposes resources to its subnodes. The below bindings specify the set > +of valid subnodes that can operate on these resources. > + > +== Switch-mode Power Supply regulator > + > +- compatible: > + Usage: required > + Value type: > + Definition: must be one of: > + "qcom,rpm-pm8058-smps" > + "qcom,rpm-pm8901-ftsmps" > + "qcom,rpm-pm8921-smps" > + "qcom,rpm-pm8921-ftsmps" > + > +- reg: > + Usage: required > + Value type: > + Definition: resource as defined in Can we provide a bit more description about what “namespace” this reg is work in. > + > +- qcom,switch-mode-frequency: > + Usage: required > + Value type: > + Definition: Frequency (Hz) of the switch-mode power supply; > + must be one of: > + 1920, 960, 640, 480, 384, 320, > + 274, 240, 213, 192, 175, 160, > + 148, 137, 128, 120 > + > +- qcom,hpm-threshold: > + Usage: optional > + Value type: > + Definition: indicates the breaking point at which the regulator should > + switch to high power mode in what units? > + > +- qcom,load-bias: > + Usage: optional > + Value type: > + Definition: specifies a base load on the specific regulator in what units? > + > +- qcom,boot-load: > + Usage: optional > + Value type: > + Definition: specifies the configured load on boot for the specific > + regulator in what units? > + > +- qcom,force-mode-none: > + Usage: optional (default if no other qcom,force-mode is specified) > + Value type: > + Defintion: indicates that the regulator should not be forced to any > +particular mode > + > +- qcom,force-mode-lpm: > + Usage: optional > + Value type: > + Definition: indicates that the regulator should be forced to operate in > + low-power-mode > + > +- qcom,force-mode-auto: > + Usage: optional (only available for 8960/8064) > + Value type: > + Definition: indicates that the regulator should be automatically pick > + operating mode > + > +- qcom,force-mode-hpm: > + Usage: optional (only available for 8960/8064) > + Value type: > + Definition: indicates that the regulator should be forced to operate in > +
Re: [PATCH 0/3] Qualcomm Resource Power Manager driver
On May 27, 2014, at 12:28 PM, Bjorn Andersson wrote: > This series adds a regulator driver for the Resource Power Manager found in > Qualcomm 8660, 8960 and 8064 based devices. > > The RPM driver exposes resources to its child devices, that can be accessed to > implement drivers for the regulators, clocks and bus frequency control that's > owned by the RPM in these devices. Rather than adding yet another mfd driver, how about we put this in drivers/soc/qcom as a much better location for the low level rpm code. Some code already merged in arm-soc for creation of drivers/soc/qcom/ > > Bjorn Andersson (3): > mfd: devicetree: bindings: Add Qualcomm RPM DT binding > mfd: qcom-rpm: Driver for the Qualcomm RPM > regulator: qcom-rpm: Regulator driver for the Qualcomm RPM > > Documentation/devicetree/bindings/mfd/qcom,rpm.txt | 283 +++ > drivers/mfd/Kconfig| 15 + > drivers/mfd/Makefile | 1 + > drivers/mfd/qcom_rpm.c | 554 ++ > drivers/regulator/Kconfig | 12 + > drivers/regulator/Makefile | 1 + > drivers/regulator/qcom_rpm-regulator.c | 852 + > include/dt-bindings/mfd/qcom_rpm.h | 148 > include/linux/mfd/qcom_rpm.h | 13 + > 9 files changed, 1879 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mfd/qcom,rpm.txt > create mode 100644 drivers/mfd/qcom_rpm.c > create mode 100644 drivers/regulator/qcom_rpm-regulator.c > create mode 100644 include/dt-bindings/mfd/qcom_rpm.h > create mode 100644 include/linux/mfd/qcom_rpm.h - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: dts: qcom: Update msm8960 device trees
On May 28, 2014, at 3:09 PM, Josh Cartwright jo...@codeaurora.org wrote:
On Wed, May 28, 2014 at 01:27:23PM -0500, Kumar Gala wrote:
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8960-cdp.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
binding spec
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8960-cdp.dts | 6 ++
arch/arm/boot/dts/qcom-msm8960.dtsi| 165
+
2 files changed, 93 insertions(+), 78 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index a58fb88..8e77ed7 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -3,4 +3,10 @@
/ {
model = Qualcomm MSM8960 CDP;
compatible = qcom,msm8960-cdp, qcom,msm8960;
+
+soc {
+serial@1644 {
+status = ok;
+};
+};
};
Is now the time put these serial nodes under a GSBI parent node?
Yeah, I’ll make the change to the 8960 8660 dts
- k
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Qualcomm Resource Power Manager driver
On May 27, 2014, at 12:28 PM, Bjorn Andersson bjorn.anders...@sonymobile.com wrote: This series adds a regulator driver for the Resource Power Manager found in Qualcomm 8660, 8960 and 8064 based devices. The RPM driver exposes resources to its child devices, that can be accessed to implement drivers for the regulators, clocks and bus frequency control that's owned by the RPM in these devices. Rather than adding yet another mfd driver, how about we put this in drivers/soc/qcom as a much better location for the low level rpm code. Some code already merged in arm-soc for creation of drivers/soc/qcom/ Bjorn Andersson (3): mfd: devicetree: bindings: Add Qualcomm RPM DT binding mfd: qcom-rpm: Driver for the Qualcomm RPM regulator: qcom-rpm: Regulator driver for the Qualcomm RPM Documentation/devicetree/bindings/mfd/qcom,rpm.txt | 283 +++ drivers/mfd/Kconfig| 15 + drivers/mfd/Makefile | 1 + drivers/mfd/qcom_rpm.c | 554 ++ drivers/regulator/Kconfig | 12 + drivers/regulator/Makefile | 1 + drivers/regulator/qcom_rpm-regulator.c | 852 + include/dt-bindings/mfd/qcom_rpm.h | 148 include/linux/mfd/qcom_rpm.h | 13 + 9 files changed, 1879 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/qcom,rpm.txt create mode 100644 drivers/mfd/qcom_rpm.c create mode 100644 drivers/regulator/qcom_rpm-regulator.c create mode 100644 include/dt-bindings/mfd/qcom_rpm.h create mode 100644 include/linux/mfd/qcom_rpm.h - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/3] mfd: devicetree: bindings: Add Qualcomm RPM DT binding
On May 27, 2014, at 12:28 PM, Bjorn Andersson bjorn.anders...@sonymobile.com wrote: Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660, 8960 and 8064 based devices. The binding currently describes the rpm itself and the regulator subnodes. Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com --- Documentation/devicetree/bindings/mfd/qcom,rpm.txt | 284 + include/dt-bindings/mfd/qcom_rpm.h | 142 +++ 2 files changed, 426 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/qcom,rpm.txt create mode 100644 include/dt-bindings/mfd/qcom_rpm.h diff --git a/Documentation/devicetree/bindings/mfd/qcom,rpm.txt b/Documentation/devicetree/bindings/mfd/qcom,rpm.txt new file mode 100644 index 000..3908a5d --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/qcom,rpm.txt @@ -0,0 +1,284 @@ +Qualcomm Resource Power Manager (RPM) + +This driver is used to interface with the Resource Power Manager (RPM) found in +various Qualcomm platforms. The RPM allows each component in the system to vote +for state of the system resources, such as clocks, regulators and bus +frequencies. + +- compatible: + Usage: required + Value type: string + Definition: must be one of: + qcom,rpm-apq8064 + qcom,rpm-msm8660 + qcom,rpm-msm8960 + +- reg: + Usage: required + Value type: prop-encoded-array + Definition: two entries specifying the RPM's message ram and ipc register + +- reg-names: + Usage: required + Value type: string-array + Definition: must contain the following, in order: + msg_ram + “ipc If order maters, it should be on reg not reg-names. If order doesn’t mater than this should say the names should match the reg + +- interrupts: + Usage: required + Value type: prop-encoded-array + Definition: three entries specifying the RPM's: + 1. acknowledgement interrupt + 2. error interrupt + 3. wakeup interrupt + +- interrupt-names: + Usage: required + Value type: string-array + Definition: must be the three strings ack, err and wakeup, in order again, if order maters it should be with the interrupts prop, not the name. + +- #address-cells: + Usage: required + Value type: u32 + Definition: must be 1 + +- #size-cells: + Usage: required + Value type: u32 + Definition: must be 0 + + += SUBDEVICES + +The RPM exposes resources to its subnodes. The below bindings specify the set +of valid subnodes that can operate on these resources. + +== Switch-mode Power Supply regulator + +- compatible: + Usage: required + Value type: string + Definition: must be one of: + qcom,rpm-pm8058-smps + qcom,rpm-pm8901-ftsmps + qcom,rpm-pm8921-smps + qcom,rpm-pm8921-ftsmps + +- reg: + Usage: required + Value type: u32 + Definition: resource as defined in dt-bindings/mfd/qcom_rpm.h Can we provide a bit more description about what “namespace” this reg is work in. + +- qcom,switch-mode-frequency: + Usage: required + Value type: u32 + Definition: Frequency (Hz) of the switch-mode power supply; + must be one of: + 1920, 960, 640, 480, 384, 320, + 274, 240, 213, 192, 175, 160, + 148, 137, 128, 120 + +- qcom,hpm-threshold: + Usage: optional + Value type: u32 + Definition: indicates the breaking point at which the regulator should + switch to high power mode in what units? + +- qcom,load-bias: + Usage: optional + Value type: u32 + Definition: specifies a base load on the specific regulator in what units? + +- qcom,boot-load: + Usage: optional + Value type: u32 + Definition: specifies the configured load on boot for the specific + regulator in what units? + +- qcom,force-mode-none: + Usage: optional (default if no other qcom,force-mode is specified) + Value type: empty + Defintion: indicates that the regulator should not be forced to any +particular mode + +- qcom,force-mode-lpm: + Usage: optional + Value type: empty + Definition: indicates that the regulator should be forced to operate in + low-power-mode + +- qcom,force-mode-auto: + Usage: optional (only available for 8960/8064) + Value type: empty + Definition: indicates that the regulator should be automatically pick + operating mode + +- qcom,force-mode-hpm: + Usage: optional (only available for 8960/8064) + Value type: empty + Definition: indicates that the regulator
Re: [PATCH 0/3] Qualcomm Resource Power Manager driver
On May 28, 2014, at 11:59 AM, Bjorn Andersson bj...@kryo.se wrote: On Wed, May 28, 2014 at 9:23 AM, Kumar Gala ga...@codeaurora.org wrote: On May 27, 2014, at 12:28 PM, Bjorn Andersson bjorn.anders...@sonymobile.com wrote: This series adds a regulator driver for the Resource Power Manager found in Qualcomm 8660, 8960 and 8064 based devices. The RPM driver exposes resources to its child devices, that can be accessed to implement drivers for the regulators, clocks and bus frequency control that's owned by the RPM in these devices. Rather than adding yet another mfd driver, how about we put this in drivers/soc/qcom as a much better location for the low level rpm code. Some code already merged in arm-soc for creation of drivers/soc/qcom/ Hi Kumar, I do see rpm as somewhat equivalent to a pmic and that was why I followed suite and put it in mfd, but I can of course move it if you prefer. Lately I've been working on rpm, rpm-smd, smem, smd, smsm, smp2p patches for mainline. It could be argued that smd is a bus and should go in drivers/bus, but for the rest I fear that we just created drivers/soc/qcom as another dumping ground for things; a Qualcomm specific drivers/mfd. But maybe that is the purpose of it ;) It is the purpose so that as we see common patterns between either drivers/soc/VENDOR we can refactor in the future. However, we need to all a little time for those patterns to emerge rather than shoe horning in drivers into places that don’t make sense. If I move the rpm driver, are there any conclusion to where I should move the dt binding documentation? devicetree/bindings/soc/qcom include/dt-bindings/soc Regards, Bjorn - k -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3] ARM: qcom: Add initial APQ8064 SoC and IFC6410 board device trees
Add basic APQ8064 SoC include device tree and support for basic booting on
the IFC6410 board. Also, keep dtb build list and qcom_dt_match in sorted
order.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v3:
* Cleanup cpu node to have compatible enable-method per node and
not in the container
* Dropped l2-cache interrupt prop as its not part of any binding
* Cleanup reg whitespace
v2:
* created a v2.0 apq8064.dtsi to handle differences in Si rev in future
* changed /include/ to #include
* added PMU node
* dropped interrupts from cpus node, not currently part of binding
arch/arm/boot/dts/Makefile | 8 +-
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 16 +++
arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 1 +
arch/arm/boot/dts/qcom-apq8064.dtsi| 170 +
arch/arm/mach-qcom/board.c | 3 +-
5 files changed, 194 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
create mode 100644 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
create mode 100644 arch/arm/boot/dts/qcom-apq8064.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 35c146f..c58624f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -291,9 +291,11 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
-dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
- qcom-msm8960-cdp.dtb \
- qcom-apq8074-dragonboard.dtb
+dtb-$(CONFIG_ARCH_QCOM) += \
+ qcom-apq8064-ifc6410.dtb \
+ qcom-apq8074-dragonboard.dtb \
+ qcom-msm8660-surf.dtb \
+ qcom-msm8960-cdp.dtb
dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
ste-hrefprev60-stuib.dtb \
ste-hrefprev60-tvk.dtb \
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
new file mode 100644
index 000..7c2441d
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -0,0 +1,16 @@
+#include qcom-apq8064-v2.0.dtsi
+
+/ {
+ model = Qualcomm APQ8064/IFC6410;
+ compatible = qcom,apq8064-ifc6410, qcom,apq8064;
+
+ soc {
+ gsbi@1660 {
+ status = ok;
+ qcom,mode = GSBI_PROT_I2C_UART;
+ serial@1664 {
+ status = ok;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
new file mode 100644
index 000..935c394
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
@@ -0,0 +1 @@
+#include qcom-apq8064.dtsi
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
new file mode 100644
index 000..e8a3423
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -0,0 +1,170 @@
+/dts-v1/;
+
+#include skeleton.dtsi
+#include dt-bindings/clock/qcom,gcc-msm8960.h
+#include dt-bindings/soc/qcom,gsbi.h
+
+/ {
+ model = Qualcomm APQ8064;
+ compatible = qcom,apq8064;
+ interrupt-parent = intc;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ compatible = qcom,krait;
+ enable-method = qcom,kpss-acc-v1;
+ device_type = cpu;
+ reg = 0;
+ next-level-cache = L2;
+ qcom,acc = acc0;
+ qcom,saw = saw0;
+ };
+
+ cpu@1 {
+ compatible = qcom,krait;
+ enable-method = qcom,kpss-acc-v1;
+ device_type = cpu;
+ reg = 1;
+ next-level-cache = L2;
+ qcom,acc = acc1;
+ qcom,saw = saw1;
+ };
+
+ cpu@2 {
+ compatible = qcom,krait;
+ enable-method = qcom,kpss-acc-v1;
+ device_type = cpu;
+ reg = 2;
+ next-level-cache = L2;
+ qcom,acc = acc2;
+ qcom,saw = saw2;
+ };
+
+ cpu@3 {
+ compatible = qcom,krait;
+ enable-method = qcom,kpss-acc-v1;
+ device_type = cpu;
+ reg = 3;
+ next-level-cache = L2;
+ qcom,acc = acc3;
+ qcom,saw = saw3;
+ };
+
+ L2: l2-cache {
+ compatible = cache;
+ cache-level = 2;
+ };
+ };
+
+ cpu-pmu {
+ compatible = qcom,krait-pmu;
+ interrupts = 1 10 0x304
