[PATCH v2 2/2] media: i2c: imx219: Balance runtime PM use-count
Move incrementing/decrementing runtime PM count to
imx219_start_streaming()/imx219_stop_streaming() functions respectively.
This fixes an issue of unbalanced runtime PM count in resume callback
error path where streaming is stopped and runtime PM count is left
unbalanced.
Fixes: 1283b3b8f82b9 ("media: i2c: Add driver for Sony IMX219 sensor")
Reported-by: Pavel Machek
Signed-off-by: Lad Prabhakar
---
drivers/media/i2c/imx219.c | 32 +---
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
index 82756cbfbaac..49ba39418360 100644
--- a/drivers/media/i2c/imx219.c
+++ b/drivers/media/i2c/imx219.c
@@ -1035,37 +1035,47 @@ static int imx219_start_streaming(struct imx219 *imx219)
const struct imx219_reg_list *reg_list;
int ret;
+ ret = pm_runtime_get_sync(&client->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(&client->dev);
+ return ret;
+ }
+
/* Apply default values of current mode */
reg_list = &imx219->mode->reg_list;
ret = imx219_write_regs(imx219, reg_list->regs, reg_list->num_of_regs);
if (ret) {
dev_err(&client->dev, "%s failed to set mode\n", __func__);
- return ret;
+ goto err_rpm_put;
}
ret = imx219_set_framefmt(imx219);
if (ret) {
dev_err(&client->dev, "%s failed to set frame format: %d\n",
__func__, ret);
- return ret;
+ goto err_rpm_put;
}
/* Apply customized values from user */
ret = __v4l2_ctrl_handler_setup(imx219->sd.ctrl_handler);
if (ret)
- return ret;
+ goto err_rpm_put;
/* set stream on register */
ret = imx219_write_reg(imx219, IMX219_REG_MODE_SELECT,
IMX219_REG_VALUE_08BIT, IMX219_MODE_STREAMING);
if (ret)
- return ret;
+ goto err_rpm_put;
/* vflip and hflip cannot change during streaming */
__v4l2_ctrl_grab(imx219->vflip, true);
__v4l2_ctrl_grab(imx219->hflip, true);
return 0;
+
+err_rpm_put:
+ pm_runtime_put(&client->dev);
+ return ret;
}
static void imx219_stop_streaming(struct imx219 *imx219)
@@ -1081,12 +1091,13 @@ static void imx219_stop_streaming(struct imx219 *imx219)
__v4l2_ctrl_grab(imx219->vflip, false);
__v4l2_ctrl_grab(imx219->hflip, false);
+
+ pm_runtime_put(&client->dev);
}
static int imx219_set_stream(struct v4l2_subdev *sd, int enable)
{
struct imx219 *imx219 = to_imx219(sd);
- struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret = 0;
mutex_lock(&imx219->mutex);
@@ -1096,22 +1107,15 @@ static int imx219_set_stream(struct v4l2_subdev *sd,
int enable)
}
if (enable) {
- ret = pm_runtime_get_sync(&client->dev);
- if (ret < 0) {
- pm_runtime_put_noidle(&client->dev);
- goto err_unlock;
- }
-
/*
* Apply default & customized values
* and then start streaming.
*/
ret = imx219_start_streaming(imx219);
if (ret)
- goto err_rpm_put;
+ goto err_unlock;
} else {
imx219_stop_streaming(imx219);
- pm_runtime_put(&client->dev);
}
imx219->streaming = enable;
@@ -1120,8 +1124,6 @@ static int imx219_set_stream(struct v4l2_subdev *sd, int
enable)
return ret;
-err_rpm_put:
- pm_runtime_put(&client->dev);
err_unlock:
mutex_unlock(&imx219->mutex);
--
2.17.1
[PATCH v2 0/2] media: i2c: imx219: Trivial Fixes
Hi All, This patch series fixes trivial issues found in imx219 driver. Cheers, Prabhakar Changes for v2: * Dropped serialization patch * Moved locking/unlocking of controls to imx219_start/imx219_stop as suggested by Laurent. * Moved incrementing/decrementing to imx219_start/imx219_stop as suggested by Laurent. Lad Prabhakar (2): media: i2c: imx219: Move out locking/unlocking of vflip and hflip controls from imx219_set_stream media: i2c: imx219: Balance runtime PM use-count drivers/media/i2c/imx219.c | 49 ++ 1 file changed, 29 insertions(+), 20 deletions(-) -- 2.17.1
[PATCH v2 1/2] media: i2c: imx219: Move out locking/unlocking of vflip and hflip controls from imx219_set_stream
Move out locking/unlocking of vflip and hflip controls from
imx219_set_stream() to the imx219_start_streaming()/
imx219_stop_streaming() respectively.
This fixes an issue in resume callback error path where streaming is
stopped and the controls are left in locked state.
Fixes: 1283b3b8f82b9 ("media: i2c: Add driver for Sony IMX219 sensor")
Reported-by: Pavel Machek
Signed-off-by: Lad Prabhakar
---
drivers/media/i2c/imx219.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
index 6e3382b85a90..82756cbfbaac 100644
--- a/drivers/media/i2c/imx219.c
+++ b/drivers/media/i2c/imx219.c
@@ -1056,8 +1056,16 @@ static int imx219_start_streaming(struct imx219 *imx219)
return ret;
/* set stream on register */
- return imx219_write_reg(imx219, IMX219_REG_MODE_SELECT,
- IMX219_REG_VALUE_08BIT, IMX219_MODE_STREAMING);
+ ret = imx219_write_reg(imx219, IMX219_REG_MODE_SELECT,
+ IMX219_REG_VALUE_08BIT, IMX219_MODE_STREAMING);
+ if (ret)
+ return ret;
+
+ /* vflip and hflip cannot change during streaming */
+ __v4l2_ctrl_grab(imx219->vflip, true);
+ __v4l2_ctrl_grab(imx219->hflip, true);
+
+ return 0;
}
static void imx219_stop_streaming(struct imx219 *imx219)
@@ -1070,6 +1078,9 @@ static void imx219_stop_streaming(struct imx219 *imx219)
IMX219_REG_VALUE_08BIT, IMX219_MODE_STANDBY);
if (ret)
dev_err(&client->dev, "%s failed to set stream\n", __func__);
+
+ __v4l2_ctrl_grab(imx219->vflip, false);
+ __v4l2_ctrl_grab(imx219->hflip, false);
}
static int imx219_set_stream(struct v4l2_subdev *sd, int enable)
@@ -1105,10 +1116,6 @@ static int imx219_set_stream(struct v4l2_subdev *sd, int
enable)
imx219->streaming = enable;
- /* vflip and hflip cannot change during streaming */
- __v4l2_ctrl_grab(imx219->vflip, enable);
- __v4l2_ctrl_grab(imx219->hflip, enable);
-
mutex_unlock(&imx219->mutex);
return ret;
--
2.17.1
Re: [PATCH 1/3] media: i2c: imx219: Enable vflip and hflip controls on stream stop
Hi Laurent,
Thank you for the review.
On Wed, Mar 10, 2021 at 12:45 PM Laurent Pinchart
wrote:
>
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Wed, Mar 10, 2021 at 12:20:12PM +0000, Lad Prabhakar wrote:
> > Enable vflip and hflip controls in resume error path when streaming
> > is stopped.
> >
> > Fixes: 1283b3b8f82b9 ("media: i2c: Add driver for Sony IMX219 sensor")
> > Reported-by: Pavel Machek
> > Signed-off-by: Lad Prabhakar
> > ---
> > drivers/media/i2c/imx219.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
> > index 6e3382b85a90..f0cf1985a4dc 100644
> > --- a/drivers/media/i2c/imx219.c
> > +++ b/drivers/media/i2c/imx219.c
> > @@ -1195,6 +1195,8 @@ static int __maybe_unused imx219_resume(struct device
> > *dev)
> > error:
> > imx219_stop_streaming(imx219);
> > imx219->streaming = false;
> > + __v4l2_ctrl_grab(imx219->vflip, false);
> > + __v4l2_ctrl_grab(imx219->hflip, false);
>
> It's not very nice to do this manually in imx219_resume(). Shouldn't we
> move the __v4l2_ctrl_grab() calls from imx219_set_stream() to
> imx219_start_streaming() and imx219_stop_streaming() instead ?
>
Agreed, moved to respective functions.
Cheers,
Prabhakar
> >
> > return ret;
> > }
>
> --
> Regards,
>
> Laurent Pinchart
Re: [PATCH 3/3] media: i2c: imx219: Balance runtime PM use-count in resume callback
Hi Laurent,
Thank you for the review.
On Wed, Mar 10, 2021 at 12:49 PM Laurent Pinchart
wrote:
>
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Wed, Mar 10, 2021 at 12:20:14PM +0000, Lad Prabhakar wrote:
> > The runtime PM use-count gets incremented in imx219_set_stream() call
> > when streaming is started this needs to be balanced by calling
> > pm_runtime_put() upon failure to start stream in resume callback.
> >
> > Fixes: 1283b3b8f82b9 ("media: i2c: Add driver for Sony IMX219 sensor")
> > Reported-by: Pavel Machek
> > Signed-off-by: Lad Prabhakar
> > ---
> > drivers/media/i2c/imx219.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
> > index 87c021de1460..afffc85cd265 100644
> > --- a/drivers/media/i2c/imx219.c
> > +++ b/drivers/media/i2c/imx219.c
> > @@ -1184,6 +1184,7 @@ static int __maybe_unused imx219_resume(struct device
> > *dev)
> > {
> > struct v4l2_subdev *sd = dev_get_drvdata(dev);
> > struct imx219 *imx219 = to_imx219(sd);
> > + struct i2c_client *client;
> > int ret;
> >
> > mutex_lock(&imx219->mutex);
> > @@ -1197,7 +1198,9 @@ static int __maybe_unused imx219_resume(struct device
> > *dev)
> > return 0;
> >
> > error:
> > + client = v4l2_get_subdevdata(&imx219->sd);
> > imx219_stop_streaming(imx219);
> > + pm_runtime_put(&client->dev);
> > imx219->streaming = false;
> > __v4l2_ctrl_grab(imx219->vflip, false);
> > __v4l2_ctrl_grab(imx219->hflip, false);
>
> Similarly to the __v4l2_ctrl_grab(), it could be better to move
> pm_runtime_put() to imx219_stop_streaming().
>
Agreed, moved this to imx219_stop_streaming().
Cheers,
Prabhakar
> --
> Regards,
>
> Laurent Pinchart
Re: [PATCH 2/3] media: i2c: imx219: Serialize during stream start/stop
Hi Laurent,
On Wed, Mar 10, 2021 at 12:54 PM Laurent Pinchart
wrote:
>
> Hi Prabhakar,
>
> On Wed, Mar 10, 2021 at 12:46:39PM +, Lad, Prabhakar wrote:
> > On Wed, Mar 10, 2021 at 12:40 PM Laurent Pinchart wrote:
> > > On Wed, Mar 10, 2021 at 12:20:13PM +, Lad Prabhakar wrote:
> > > > Serialize during stream start/stop in suspend/resume callbacks.
> > >
> > > Could you please explain why this is needed ?
> > >
> > The streaming variable in this driver has serialized access, but this
> > wasn't taken care during suspend/resume callbacks.
>
> But nothing that touches the streaming variable can run concurrently to
> suspend/resume, isn't it ?
>
You are right, we could drop this patch.
> I'm actually even quite dubious about the need to start and stop
> streaming during resume and suspend, the driver using the subdev should
> start/stop the whole video pipeline at suspend/resume time.
>
I see, do we have any documentation on how bridge/subdevs should
behave on suspend/resume ?
I did have a quick look at the omp3isp bridge driver and it does
start/stop on resume/suspend callbacks.
Cheers,
Prabhakar
> > > > Signed-off-by: Lad Prabhakar
> > > > ---
> > > > drivers/media/i2c/imx219.c | 5 +
> > > > 1 file changed, 5 insertions(+)
> > > >
> > > > diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
> > > > index f0cf1985a4dc..87c021de1460 100644
> > > > --- a/drivers/media/i2c/imx219.c
> > > > +++ b/drivers/media/i2c/imx219.c
> > > > @@ -1172,8 +1172,10 @@ static int __maybe_unused imx219_suspend(struct
> > > > device *dev)
> > > > struct v4l2_subdev *sd = dev_get_drvdata(dev);
> > > > struct imx219 *imx219 = to_imx219(sd);
> > > >
> > > > + mutex_lock(&imx219->mutex);
> > > > if (imx219->streaming)
> > > > imx219_stop_streaming(imx219);
> > > > + mutex_unlock(&imx219->mutex);
> > > >
> > > > return 0;
> > > > }
> > > > @@ -1184,11 +1186,13 @@ static int __maybe_unused imx219_resume(struct
> > > > device *dev)
> > > > struct imx219 *imx219 = to_imx219(sd);
> > > > int ret;
> > > >
> > > > + mutex_lock(&imx219->mutex);
> > > > if (imx219->streaming) {
> > > > ret = imx219_start_streaming(imx219);
> > > > if (ret)
> > > > goto error;
> > > > }
> > > > + mutex_unlock(&imx219->mutex);
> > > >
> > > > return 0;
> > > >
> > > > @@ -1197,6 +1201,7 @@ static int __maybe_unused imx219_resume(struct
> > > > device *dev)
> > > > imx219->streaming = false;
> > > > __v4l2_ctrl_grab(imx219->vflip, false);
> > > > __v4l2_ctrl_grab(imx219->hflip, false);
> > > > + mutex_unlock(&imx219->mutex);
> > > >
> > > > return ret;
> > > > }
>
> --
> Regards,
>
> Laurent Pinchart
Re: [PATCH 2/3] media: i2c: imx219: Serialize during stream start/stop
Hi Laurent,
Thank you for the review.
On Wed, Mar 10, 2021 at 12:40 PM Laurent Pinchart
wrote:
>
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Wed, Mar 10, 2021 at 12:20:13PM +0000, Lad Prabhakar wrote:
> > Serialize during stream start/stop in suspend/resume callbacks.
>
> Could you please explain why this is needed ?
>
The streaming variable in this driver has serialized access, but this
wasn't taken care during suspend/resume callbacks.
Cheers,
Prabhakar
> > Signed-off-by: Lad Prabhakar
> > ---
> > drivers/media/i2c/imx219.c | 5 +
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
> > index f0cf1985a4dc..87c021de1460 100644
> > --- a/drivers/media/i2c/imx219.c
> > +++ b/drivers/media/i2c/imx219.c
> > @@ -1172,8 +1172,10 @@ static int __maybe_unused imx219_suspend(struct
> > device *dev)
> > struct v4l2_subdev *sd = dev_get_drvdata(dev);
> > struct imx219 *imx219 = to_imx219(sd);
> >
> > + mutex_lock(&imx219->mutex);
> > if (imx219->streaming)
> > imx219_stop_streaming(imx219);
> > + mutex_unlock(&imx219->mutex);
> >
> > return 0;
> > }
> > @@ -1184,11 +1186,13 @@ static int __maybe_unused imx219_resume(struct
> > device *dev)
> > struct imx219 *imx219 = to_imx219(sd);
> > int ret;
> >
> > + mutex_lock(&imx219->mutex);
> > if (imx219->streaming) {
> > ret = imx219_start_streaming(imx219);
> > if (ret)
> > goto error;
> > }
> > + mutex_unlock(&imx219->mutex);
> >
> > return 0;
> >
> > @@ -1197,6 +1201,7 @@ static int __maybe_unused imx219_resume(struct device
> > *dev)
> > imx219->streaming = false;
> > __v4l2_ctrl_grab(imx219->vflip, false);
> > __v4l2_ctrl_grab(imx219->hflip, false);
> > + mutex_unlock(&imx219->mutex);
> >
> > return ret;
> > }
>
> --
> Regards,
>
> Laurent Pinchart
[PATCH 3/3] media: i2c: imx219: Balance runtime PM use-count in resume callback
The runtime PM use-count gets incremented in imx219_set_stream() call
when streaming is started this needs to be balanced by calling
pm_runtime_put() upon failure to start stream in resume callback.
Fixes: 1283b3b8f82b9 ("media: i2c: Add driver for Sony IMX219 sensor")
Reported-by: Pavel Machek
Signed-off-by: Lad Prabhakar
---
drivers/media/i2c/imx219.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
index 87c021de1460..afffc85cd265 100644
--- a/drivers/media/i2c/imx219.c
+++ b/drivers/media/i2c/imx219.c
@@ -1184,6 +1184,7 @@ static int __maybe_unused imx219_resume(struct device
*dev)
{
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx219 *imx219 = to_imx219(sd);
+ struct i2c_client *client;
int ret;
mutex_lock(&imx219->mutex);
@@ -1197,7 +1198,9 @@ static int __maybe_unused imx219_resume(struct device
*dev)
return 0;
error:
+ client = v4l2_get_subdevdata(&imx219->sd);
imx219_stop_streaming(imx219);
+ pm_runtime_put(&client->dev);
imx219->streaming = false;
__v4l2_ctrl_grab(imx219->vflip, false);
__v4l2_ctrl_grab(imx219->hflip, false);
--
2.17.1
[PATCH 2/3] media: i2c: imx219: Serialize during stream start/stop
Serialize during stream start/stop in suspend/resume callbacks.
Signed-off-by: Lad Prabhakar
---
drivers/media/i2c/imx219.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
index f0cf1985a4dc..87c021de1460 100644
--- a/drivers/media/i2c/imx219.c
+++ b/drivers/media/i2c/imx219.c
@@ -1172,8 +1172,10 @@ static int __maybe_unused imx219_suspend(struct device
*dev)
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx219 *imx219 = to_imx219(sd);
+ mutex_lock(&imx219->mutex);
if (imx219->streaming)
imx219_stop_streaming(imx219);
+ mutex_unlock(&imx219->mutex);
return 0;
}
@@ -1184,11 +1186,13 @@ static int __maybe_unused imx219_resume(struct device
*dev)
struct imx219 *imx219 = to_imx219(sd);
int ret;
+ mutex_lock(&imx219->mutex);
if (imx219->streaming) {
ret = imx219_start_streaming(imx219);
if (ret)
goto error;
}
+ mutex_unlock(&imx219->mutex);
return 0;
@@ -1197,6 +1201,7 @@ static int __maybe_unused imx219_resume(struct device
*dev)
imx219->streaming = false;
__v4l2_ctrl_grab(imx219->vflip, false);
__v4l2_ctrl_grab(imx219->hflip, false);
+ mutex_unlock(&imx219->mutex);
return ret;
}
--
2.17.1
[PATCH 0/3] media: i2c: imx219: Trivial Fixes
Hi All, This patch series fixes trivial issues found in imx219 driver. Cheers, Prabhakar Lad Prabhakar (3): media: i2c: imx219: Enable vflip and hflip controls on stream stop media: i2c: imx219: Serialize during stream start/stop media: i2c: imx219: Balance runtime PM use-count in resume callback drivers/media/i2c/imx219.c | 10 ++ 1 file changed, 10 insertions(+) -- 2.17.1
[PATCH 1/3] media: i2c: imx219: Enable vflip and hflip controls on stream stop
Enable vflip and hflip controls in resume error path when streaming
is stopped.
Fixes: 1283b3b8f82b9 ("media: i2c: Add driver for Sony IMX219 sensor")
Reported-by: Pavel Machek
Signed-off-by: Lad Prabhakar
---
drivers/media/i2c/imx219.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
index 6e3382b85a90..f0cf1985a4dc 100644
--- a/drivers/media/i2c/imx219.c
+++ b/drivers/media/i2c/imx219.c
@@ -1195,6 +1195,8 @@ static int __maybe_unused imx219_resume(struct device
*dev)
error:
imx219_stop_streaming(imx219);
imx219->streaming = false;
+ __v4l2_ctrl_grab(imx219->vflip, false);
+ __v4l2_ctrl_grab(imx219->hflip, false);
return ret;
}
--
2.17.1
Re: [PATCH] include: media: davinci: Fixed up few trivial spellings in the file isif.h
Hi Bhaskar,
Thank you for the patch.
On Fri, Feb 5, 2021 at 9:21 AM Bhaskar Chowdhury wrote:
>
>
>
> Several spelling fixes throughout the file.
>
> Signed-off-by: Bhaskar Chowdhury
> ---
> include/media/davinci/isif.h | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
Acked-by: Lad Prabhakar
Cheers,
Prabhakar
> diff --git a/include/media/davinci/isif.h b/include/media/davinci/isif.h
> index e66589c4022d..8369acd26e7e 100644
> --- a/include/media/davinci/isif.h
> +++ b/include/media/davinci/isif.h
> @@ -177,7 +177,7 @@ struct isif_black_clamp {
> * 1 - clamp value calculated separately for all colors
> */
> __u8 bc_mode_color;
> - /* Vrtical start position for bc subtraction */
> + /* Vertical start position for bc subtraction */
> __u16 vert_start_sub;
> /* Black clamp for horizontal direction */
> struct isif_horz_bclamp horz;
> @@ -193,7 +193,7 @@ struct isif_color_space_conv {
> /* Enable color space conversion */
> __u8 en;
> /*
> -* csc coeffient table. S8Q5, M00 at index 0, M01 at index 1, and
> +* csc coefficient table. S8Q5, M00 at index 0, M01 at index 1, and
> * so forth
> */
> struct isif_float_8 coeff[ISIF_CSC_NUM_COEFF];
> @@ -340,7 +340,7 @@ struct isif_data_formatter {
> };
>
> struct isif_df_csc {
> - /* Color Space Conversion confguration, 0 - csc, 1 - df */
> + /* Color Space Conversion configuration, 0 - csc, 1 - df */
> __u8 df_or_csc;
> /* csc configuration valid if df_or_csc is 0 */
> struct isif_color_space_conv csc;
> @@ -406,7 +406,7 @@ struct isif_config_params_raw {
> struct isif_linearize linearize;
> /* Data formatter or CSC */
> struct isif_df_csc df_csc;
> - /* Defect Pixel Correction (DFC) confguration */
> + /* Defect Pixel Correction (DFC) configuration */
> struct isif_dfc dfc;
> /* Black/Digital Clamp configuration */
> struct isif_black_clamp bclamp;
> --
> 2.30.0
>
Re: [PATCH] media: i2c/Kconfig: Select FWNODE for OV772x sensor
On Wed, Jan 20, 2021 at 11:09 AM Kieran Bingham
wrote:
>
> On 20/01/2021 10:36, Sakari Ailus wrote:
> > On Wed, Jan 20, 2021 at 10:17:14AM +, Kieran Bingham wrote:
> >> Hi Lad,
> >>
> >> On 20/01/2021 09:01, Lad Prabhakar wrote:
> >>> Fix OV772x build breakage by selecting V4L2_FWNODE config:
> >>>
> >>> ia64-linux-ld: drivers/media/i2c/ov772x.o: in function `ov772x_probe':
> >>> ov772x.c:(.text+0x1ee2): undefined reference to
> >>> `v4l2_fwnode_endpoint_alloc_parse'
> >>> ia64-linux-ld: ov772x.c:(.text+0x1f12): undefined reference to
> >>> `v4l2_fwnode_endpoint_free'
> >>> ia64-linux-ld: ov772x.c:(.text+0x2212): undefined reference to
> >>> `v4l2_fwnode_endpoint_alloc_parse'
> >>>
> >>> Fixes: 8a10b4e3601e ("media: i2c: ov772x: Parse endpoint properties")
> >>> Reported-by: kernel test robot
> >>> Signed-off-by: Lad Prabhakar
> >>
> >> I see this driver uses subdev API too.
> >>
> >> Should the driver also select VIDEO_V4L2_SUBDEV_API?
> >
> > Yes, it should. Another patch? This one fixes a compilation problem.
>
> Yes, it's probably another patch, because indeed this is a specific fix.
>
> I wonder if that means the builders haven't been able to construct a
> combination without VIDEO_V4L2_SUBDEV_API...
>
Thats because v4l2-subdev.o is built irrespective of
VIDEO_V4L2_SUBDEV_API enabled/disabled and there are empty fillers in
v4l2-subdev.c when VIDEO_V4L2_SUBDEV_API is disabled.
Cheers,
Prabhakar
> --
> Kieran
>
>
> >> Or is that covered sufficiently already on any platforms that would use
> >> the driver?
> >>
> >> Reviewed-by: Kieran Bingham
> >>
> >>> ---
> >>> drivers/media/i2c/Kconfig | 1 +
> >>> 1 file changed, 1 insertion(+)
> >>>
> >>> diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
> >>> index eddb10220953..bb1b5a340431 100644
> >>> --- a/drivers/media/i2c/Kconfig
> >>> +++ b/drivers/media/i2c/Kconfig
> >>> @@ -1013,6 +1013,7 @@ config VIDEO_OV772X
> >>> tristate "OmniVision OV772x sensor support"
> >>> depends on I2C && VIDEO_V4L2
> >>> select REGMAP_SCCB
> >>> + select V4L2_FWNODE
> >>> help
> >>> This is a Video4Linux2 sensor driver for the OmniVision
> >>> OV772x camera.
> >>>
> >>
> >
>
Re: [PATCH] media: i2c/Kconfig: Select FWNODE for OV772x sensor
Hi Sakari and Kieran,
On Wed, Jan 20, 2021 at 10:36 AM Sakari Ailus
wrote:
>
> On Wed, Jan 20, 2021 at 10:17:14AM +, Kieran Bingham wrote:
> > Hi Lad,
> >
> > On 20/01/2021 09:01, Lad Prabhakar wrote:
> > > Fix OV772x build breakage by selecting V4L2_FWNODE config:
> > >
> > > ia64-linux-ld: drivers/media/i2c/ov772x.o: in function `ov772x_probe':
> > > ov772x.c:(.text+0x1ee2): undefined reference to
> > > `v4l2_fwnode_endpoint_alloc_parse'
> > > ia64-linux-ld: ov772x.c:(.text+0x1f12): undefined reference to
> > > `v4l2_fwnode_endpoint_free'
> > > ia64-linux-ld: ov772x.c:(.text+0x2212): undefined reference to
> > > `v4l2_fwnode_endpoint_alloc_parse'
> > >
> > > Fixes: 8a10b4e3601e ("media: i2c: ov772x: Parse endpoint properties")
> > > Reported-by: kernel test robot
> > > Signed-off-by: Lad Prabhakar
> >
> > I see this driver uses subdev API too.
> >
> > Should the driver also select VIDEO_V4L2_SUBDEV_API?
>
> Yes, it should. Another patch? This one fixes a compilation problem.
>
Do agree, I will post an incremental patch on top of this.
Cheers,
Prabhakar
> >
> > Or is that covered sufficiently already on any platforms that would use
> > the driver?
> >
> > Reviewed-by: Kieran Bingham
> >
> > > ---
> > > drivers/media/i2c/Kconfig | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
> > > index eddb10220953..bb1b5a340431 100644
> > > --- a/drivers/media/i2c/Kconfig
> > > +++ b/drivers/media/i2c/Kconfig
> > > @@ -1013,6 +1013,7 @@ config VIDEO_OV772X
> > > tristate "OmniVision OV772x sensor support"
> > > depends on I2C && VIDEO_V4L2
> > > select REGMAP_SCCB
> > > + select V4L2_FWNODE
> > > help
> > > This is a Video4Linux2 sensor driver for the OmniVision
> > > OV772x camera.
> > >
> >
>
> --
> Sakari Ailus
[PATCH] media: i2c/Kconfig: Select FWNODE for OV772x sensor
Fix OV772x build breakage by selecting V4L2_FWNODE config:
ia64-linux-ld: drivers/media/i2c/ov772x.o: in function `ov772x_probe':
ov772x.c:(.text+0x1ee2): undefined reference to
`v4l2_fwnode_endpoint_alloc_parse'
ia64-linux-ld: ov772x.c:(.text+0x1f12): undefined reference to
`v4l2_fwnode_endpoint_free'
ia64-linux-ld: ov772x.c:(.text+0x2212): undefined reference to
`v4l2_fwnode_endpoint_alloc_parse'
Fixes: 8a10b4e3601e ("media: i2c: ov772x: Parse endpoint properties")
Reported-by: kernel test robot
Signed-off-by: Lad Prabhakar
---
drivers/media/i2c/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index eddb10220953..bb1b5a340431 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -1013,6 +1013,7 @@ config VIDEO_OV772X
tristate "OmniVision OV772x sensor support"
depends on I2C && VIDEO_V4L2
select REGMAP_SCCB
+ select V4L2_FWNODE
help
This is a Video4Linux2 sensor driver for the OmniVision
OV772x camera.
--
2.17.1
[PATCH] spi: rpc-if: Gaurd .pm assignment with CONFIG_PM_SLEEP #ifdef check
With CONFIG_PM_SLEEP disabled the rpcif_spi_pm_ops variable is still
referenced and thus increasing the size of kernel.
Fix this issue by adding CONFIG_PM_SLEEP #ifdef check around the .pm
assignment (image size is critical on RZ/A SoC's where the SRAM sizes
range 4~5 MiB).
Fixes: 9584fc95cadc0 ("spi: rpc-if: Remove CONFIG_PM_SLEEP ifdefery")
Reported-by: Geert Uytterhoeven
Suggested-by: Pavel Machek
Signed-off-by: Lad Prabhakar
---
drivers/spi/spi-rpc-if.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/spi/spi-rpc-if.c b/drivers/spi/spi-rpc-if.c
index c313dbe6185c..c53138ce0030 100644
--- a/drivers/spi/spi-rpc-if.c
+++ b/drivers/spi/spi-rpc-if.c
@@ -197,7 +197,9 @@ static struct platform_driver rpcif_spi_driver = {
.remove = rpcif_spi_remove,
.driver = {
.name = "rpc-if-spi",
+#ifdef CONFIG_PM_SLEEP
.pm = &rpcif_spi_pm_ops,
+#endif
},
};
module_platform_driver(rpcif_spi_driver);
--
2.17.1
Re: [PATCH 2/2] spi: rpc-if: Remove CONFIG_PM_SLEEP ifdefery
Hi Geert,
Thank you for the review.
On Mon, Jan 4, 2021 at 12:34 PM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Wed, Dec 30, 2020 at 4:00 PM Lad Prabhakar
> wrote:
> > Use __maybe_unused for the suspend()/resume() hooks and get rid of
> > the CONFIG_PM_SLEEP ifdefery to improve the code.
> >
> > Suggested-by: Pavel Machek
> > Signed-off-by: Lad Prabhakar
>
> Thanks for your patch!
>
> > --- a/drivers/spi/spi-rpc-if.c
> > +++ b/drivers/spi/spi-rpc-if.c
> > @@ -176,15 +176,14 @@ static int rpcif_spi_remove(struct platform_device
> > *pdev)
> > return 0;
> > }
> >
> > -#ifdef CONFIG_PM_SLEEP
> > -static int rpcif_spi_suspend(struct device *dev)
> > +static int __maybe_unused rpcif_spi_suspend(struct device *dev)
> > {
> > struct spi_controller *ctlr = dev_get_drvdata(dev);
> >
> > return spi_controller_suspend(ctlr);
> > }
> >
> > -static int rpcif_spi_resume(struct device *dev)
> > +static int __maybe_unused rpcif_spi_resume(struct device *dev)
> > {
> > struct spi_controller *ctlr = dev_get_drvdata(dev);
> >
> > @@ -192,17 +191,13 @@ static int rpcif_spi_resume(struct device *dev)
> > }
> >
> > static SIMPLE_DEV_PM_OPS(rpcif_spi_pm_ops, rpcif_spi_suspend,
> > rpcif_spi_resume);
> > -#define DEV_PM_OPS (&rpcif_spi_pm_ops)
> > -#else
> > -#define DEV_PM_OPS NULL
> > -#endif
> >
> > static struct platform_driver rpcif_spi_driver = {
> > .probe = rpcif_spi_probe,
> > .remove = rpcif_spi_remove,
> > .driver = {
> > .name = "rpc-if-spi",
> > - .pm = DEV_PM_OPS,
> > + .pm = &rpcif_spi_pm_ops,
>
> You're aware rpcif_spi_pm_ops is now always referenced and thus emitted,
> increasing kernel size by 92 bytes if CONFIG_PM_SLEEP=n?
> This may matter for RZ/A SoCs running from internal SRAM.
>
Hmm didn't realise this would be an issue on RZ/A.
Mark, could you please drop this patch from your branch.
Cheers,
Prabhakar
> > },
> > };
> > module_platform_driver(rpcif_spi_driver);
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
Re: [PATCH] can: rcar: Update help description for CAN_RCAR_CANFD config
Hi Geert,
Thank you for the review.
On Mon, Jan 4, 2021 at 10:51 AM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Thu, Dec 31, 2020 at 5:00 PM Lad Prabhakar
> wrote:
> > The rcar_canfd driver supports R-Car Gen3 and RZ/G2 SoC's, update the
> > description to reflect this.
> >
> > Signed-off-by: Lad Prabhakar
>
> Reviewed-by: Geert Uytterhoeven
>
> > --- a/drivers/net/can/rcar/Kconfig
> > +++ b/drivers/net/can/rcar/Kconfig
> > @@ -10,13 +10,13 @@ config CAN_RCAR
> > be called rcar_can.
> >
> > config CAN_RCAR_CANFD
> > - tristate "Renesas R-Car CAN FD controller"
> > + tristate "Renesas R-Car Gen3 and RZ/G2 CAN FD controller"
> > depends on ARCH_RENESAS || ARM
>
> Not introduced by this patch, but the "|| ARM" looks strange to me.
> Is this meant for compile-testing? Doesn't the driver compile on all
> platforms (it does on m68k), so "|| COMPILE_TEST" is not appropriate?
> Is the CAN FD controller present on some Renesas arm32 SoCs (but
> not yet supported by this driver)?
>
Good catch. "|| ARM" was probably copied from CAN_RCAR config and I
can confirm CAN-FD controller doesn't exist on R-Car Gen2 and RZ/G2
32bit SoC's (but with a bit of google search RZ/A2M supports CAN-FD I
am not sure if its the same controller tough), but said that there
shouldn't be any harm in replacing "|| ARM" with "|| COMPILE_TEST"
for both CAN_RCAR_CAN{FD}. What are your thoughts?
Cheers,
Prabhakar
> > help
> > Say Y here if you want to use CAN FD controller found on
> > - Renesas R-Car SoCs. The driver puts the controller in CAN FD only
> > - mode, which can interoperate with CAN2.0 nodes but does not
> > support
> > - dedicated CAN 2.0 mode.
> > + Renesas R-Car Gen3 and RZ/G2 SoCs. The driver puts the
> > + controller in CAN FD only mode, which can interoperate with
> > + CAN2.0 nodes but does not support dedicated CAN 2.0 mode.
> >
> > To compile this driver as a module, choose M here: the module will
> > be called rcar_canfd.
>
> Gr{oetje,eeting}s,
>
> Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
[PATCH v2] gpio: Kconfig: Update help description for GPIO_RCAR config
The gpio-rcar driver also supports RZ/G SoC's, update the description to reflect this. Signed-off-by: Lad Prabhakar --- v1->v2 * Dropped SoC version numbers --- drivers/gpio/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index c70f46e80a3b..62ae296251eb 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -486,11 +486,11 @@ config GPIO_PXA Say yes here to support the PXA GPIO device config GPIO_RCAR - tristate "Renesas R-Car GPIO" + tristate "Renesas R-Car and RZ/G GPIO support" depends on ARCH_RENESAS || COMPILE_TEST select GPIOLIB_IRQCHIP help - Say yes here to support GPIO on Renesas R-Car SoCs. + Say yes here to support GPIO on Renesas R-Car or RZ/G SoCs. config GPIO_RDA bool "RDA Micro GPIO controller support" -- 2.17.1
[PATCH v2] can: rcar: Update help description for CAN_RCAR config
The rcar_can driver also supports RZ/G SoC's, update the description to reflect this. Signed-off-by: Lad Prabhakar --- v1->v2 * Dropped SoC version numbers. --- drivers/net/can/rcar/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/can/rcar/Kconfig b/drivers/net/can/rcar/Kconfig index 5cb0892978ca..ec6e3339d048 100644 --- a/drivers/net/can/rcar/Kconfig +++ b/drivers/net/can/rcar/Kconfig @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 config CAN_RCAR - tristate "Renesas R-Car CAN controller" + tristate "Renesas R-Car and RZ/G CAN controller" depends on ARCH_RENESAS || ARM help Say Y here if you want to use CAN controller found on Renesas R-Car - SoCs. + or RZ/G SoCs. To compile this driver as a module, choose M here: the module will be called rcar_can. -- 2.17.1
[PATCH] can: rcar: Update help description for CAN_RCAR_CANFD config
The rcar_canfd driver supports R-Car Gen3 and RZ/G2 SoC's, update the description to reflect this. Signed-off-by: Lad Prabhakar --- drivers/net/can/rcar/Kconfig | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/can/rcar/Kconfig b/drivers/net/can/rcar/Kconfig index 6bb0e7c052ad..a669b9ac8057 100644 --- a/drivers/net/can/rcar/Kconfig +++ b/drivers/net/can/rcar/Kconfig @@ -10,13 +10,13 @@ config CAN_RCAR be called rcar_can. config CAN_RCAR_CANFD - tristate "Renesas R-Car CAN FD controller" + tristate "Renesas R-Car Gen3 and RZ/G2 CAN FD controller" depends on ARCH_RENESAS || ARM help Say Y here if you want to use CAN FD controller found on - Renesas R-Car SoCs. The driver puts the controller in CAN FD only - mode, which can interoperate with CAN2.0 nodes but does not support - dedicated CAN 2.0 mode. + Renesas R-Car Gen3 and RZ/G2 SoCs. The driver puts the + controller in CAN FD only mode, which can interoperate with + CAN2.0 nodes but does not support dedicated CAN 2.0 mode. To compile this driver as a module, choose M here: the module will be called rcar_canfd. -- 2.17.1
[PATCH] can: rcar: Update help description for CAN_RCAR config
The rcar_can driver supports R-Car Gen{1,2,3} and RZ/G{1,2} SoC's, update
the description to reflect this.
Signed-off-by: Lad Prabhakar
---
drivers/net/can/rcar/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/can/rcar/Kconfig b/drivers/net/can/rcar/Kconfig
index 8d36101b78e3..6bb0e7c052ad 100644
--- a/drivers/net/can/rcar/Kconfig
+++ b/drivers/net/can/rcar/Kconfig
@@ -1,10 +1,10 @@
# SPDX-License-Identifier: GPL-2.0
config CAN_RCAR
- tristate "Renesas R-Car CAN controller"
+ tristate "Renesas R-Car Gen{1,2,3} and RZ/G{1,2} CAN controller"
depends on ARCH_RENESAS || ARM
help
Say Y here if you want to use CAN controller found on Renesas R-Car
- SoCs.
+ Gen{1,2,3} and RZ/G{1,2} SoCs.
To compile this driver as a module, choose M here: the module will
be called rcar_can.
--
2.17.1
[PATCH] gpio: Kconfig: Update help description for GPIO_RCAR
The gpio-rcar driver supports R-Car Gen{1,2,3} and RZ/G{1,2} SoC's, update
the description to reflect this.
Signed-off-by: Lad Prabhakar
---
drivers/gpio/Kconfig | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c70f46e80a3b..47e545d71df1 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -486,11 +486,12 @@ config GPIO_PXA
Say yes here to support the PXA GPIO device
config GPIO_RCAR
- tristate "Renesas R-Car GPIO"
+ tristate "Renesas R-Car Gen{1,2,3} and RZ/G{1,2} GPIO support"
depends on ARCH_RENESAS || COMPILE_TEST
select GPIOLIB_IRQCHIP
help
- Say yes here to support GPIO on Renesas R-Car SoCs.
+ Say yes here to support GPIO on Renesas R-Car Gen{1,2,3} and
+ RZ/G{1,2} SoCs.
config GPIO_RDA
bool "RDA Micro GPIO controller support"
--
2.17.1
[PATCH] gpio: rcar: Remove redundant compatible values
The mandatory compatible values 'renesas,rcar-gen{1,2,3}-gpio' have been
already added to all the respective R-Car Gen{1,2,3} SoC DTSI files,
remove the redundant device specific values from the driver.
Signed-off-by: Lad Prabhakar
---
drivers/gpio/gpio-rcar.c | 27 ---
1 file changed, 27 deletions(-)
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 0b572dbc4a36..f3b8c4b44cab 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -392,33 +392,6 @@ static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
static const struct of_device_id gpio_rcar_of_table[] = {
{
- .compatible = "renesas,gpio-r8a7743",
- /* RZ/G1 GPIO is identical to R-Car Gen2. */
- .data = &gpio_rcar_info_gen2,
- }, {
- .compatible = "renesas,gpio-r8a7790",
- .data = &gpio_rcar_info_gen2,
- }, {
- .compatible = "renesas,gpio-r8a7791",
- .data = &gpio_rcar_info_gen2,
- }, {
- .compatible = "renesas,gpio-r8a7792",
- .data = &gpio_rcar_info_gen2,
- }, {
- .compatible = "renesas,gpio-r8a7793",
- .data = &gpio_rcar_info_gen2,
- }, {
- .compatible = "renesas,gpio-r8a7794",
- .data = &gpio_rcar_info_gen2,
- }, {
- .compatible = "renesas,gpio-r8a7795",
- /* Gen3 GPIO is identical to Gen2. */
- .data = &gpio_rcar_info_gen2,
- }, {
- .compatible = "renesas,gpio-r8a7796",
- /* Gen3 GPIO is identical to Gen2. */
- .data = &gpio_rcar_info_gen2,
- }, {
.compatible = "renesas,rcar-gen1-gpio",
.data = &gpio_rcar_info_gen1,
}, {
--
2.17.1
Re: [PATCH -next] media: platform: davinci: Use DEFINE_SPINLOCK() for spinlock
Hi Zheng,
Thank you for the patch.
On Mon, Dec 28, 2020 at 1:50 PM Zheng Yongjun wrote:
>
> spinlock can be initialized automatically with DEFINE_SPINLOCK()
> rather than explicitly calling spin_lock_init().
>
> Signed-off-by: Zheng Yongjun
> ---
> drivers/media/platform/davinci/vpif.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
Reviewed-by: Lad Prabhakar
Cheers,
Prabhakar
> diff --git a/drivers/media/platform/davinci/vpif.c
> b/drivers/media/platform/davinci/vpif.c
> index 5e67994e62cc..f1ce10828b8e 100644
> --- a/drivers/media/platform/davinci/vpif.c
> +++ b/drivers/media/platform/davinci/vpif.c
> @@ -41,7 +41,7 @@ MODULE_ALIAS("platform:" VPIF_DRIVER_NAME);
> #define VPIF_CH2_MAX_MODES 15
> #define VPIF_CH3_MAX_MODES 2
>
> -spinlock_t vpif_lock;
> +DEFINE_SPINLOCK(vpif_lock);
> EXPORT_SYMBOL_GPL(vpif_lock);
>
> void __iomem *vpif_base;
> @@ -437,7 +437,6 @@ static int vpif_probe(struct platform_device *pdev)
> pm_runtime_enable(&pdev->dev);
> pm_runtime_get(&pdev->dev);
>
> - spin_lock_init(&vpif_lock);
> dev_info(&pdev->dev, "vpif probe success\n");
>
> /*
> --
> 2.22.0
>
Re: [PATCH 1/2] spi: rpc-if: Avoid use of C++ style comments
Hi Sergei, On Wed, Dec 30, 2020 at 4:27 PM Sergei Shtylyov wrote: > > On 12/30/20 5:57 PM, Lad Prabhakar wrote: > > > Replace C++ style comment with C style. > >Note that the switch to // was made following the SPI maintainer's > request... > Thanks for letting me know, let's drop this patch. Cheers, Prabhakar > > Signed-off-by: Lad Prabhakar > [...] > > MBR, Sergei
[PATCH 2/2] spi: rpc-if: Remove CONFIG_PM_SLEEP ifdefery
Use __maybe_unused for the suspend()/resume() hooks and get rid of
the CONFIG_PM_SLEEP ifdefery to improve the code.
Suggested-by: Pavel Machek
Signed-off-by: Lad Prabhakar
---
drivers/spi/spi-rpc-if.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-rpc-if.c b/drivers/spi/spi-rpc-if.c
index bf64da322e67..b600becd4691 100644
--- a/drivers/spi/spi-rpc-if.c
+++ b/drivers/spi/spi-rpc-if.c
@@ -176,15 +176,14 @@ static int rpcif_spi_remove(struct platform_device *pdev)
return 0;
}
-#ifdef CONFIG_PM_SLEEP
-static int rpcif_spi_suspend(struct device *dev)
+static int __maybe_unused rpcif_spi_suspend(struct device *dev)
{
struct spi_controller *ctlr = dev_get_drvdata(dev);
return spi_controller_suspend(ctlr);
}
-static int rpcif_spi_resume(struct device *dev)
+static int __maybe_unused rpcif_spi_resume(struct device *dev)
{
struct spi_controller *ctlr = dev_get_drvdata(dev);
@@ -192,17 +191,13 @@ static int rpcif_spi_resume(struct device *dev)
}
static SIMPLE_DEV_PM_OPS(rpcif_spi_pm_ops, rpcif_spi_suspend,
rpcif_spi_resume);
-#define DEV_PM_OPS (&rpcif_spi_pm_ops)
-#else
-#define DEV_PM_OPS NULL
-#endif
static struct platform_driver rpcif_spi_driver = {
.probe = rpcif_spi_probe,
.remove = rpcif_spi_remove,
.driver = {
.name = "rpc-if-spi",
- .pm = DEV_PM_OPS,
+ .pm = &rpcif_spi_pm_ops,
},
};
module_platform_driver(rpcif_spi_driver);
--
2.17.1
[PATCH 0/2] spi: rpc-if: Trivial fixes
Hi All, These patches are trivial fixes for rpc-if SPI driver. Cheers, Prabhakar Lad Prabhakar (2): spi: rpc-if: Avoid use of C++ style comments spi: rpc-if: Remove CONFIG_PM_SLEEP ifdefery drivers/spi/spi-rpc-if.c | 25 ++--- 1 file changed, 10 insertions(+), 15 deletions(-) -- 2.17.1
[PATCH 1/2] spi: rpc-if: Avoid use of C++ style comments
Replace C++ style comment with C style. Signed-off-by: Lad Prabhakar --- drivers/spi/spi-rpc-if.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-rpc-if.c b/drivers/spi/spi-rpc-if.c index 3579675485a5..bf64da322e67 100644 --- a/drivers/spi/spi-rpc-if.c +++ b/drivers/spi/spi-rpc-if.c @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 -// -// RPC-IF SPI/QSPI/Octa driver -// -// Copyright (C) 2018 ~ 2019 Renesas Solutions Corp. -// Copyright (C) 2019 Macronix International Co., Ltd. -// Copyright (C) 2019 - 2020 Cogent Embedded, Inc. -// +/* + * RPC-IF SPI/QSPI/Octa driver + * + * Copyright (C) 2018 ~ 2019 Renesas Solutions Corp. + * Copyright (C) 2019 Macronix International Co., Ltd. + * Copyright (C) 2019 - 2020 Cogent Embedded, Inc. + */ #include #include -- 2.17.1
[PATCH] PCI: Drop PCIE_RCAR config option
All the defconfig files have replaced PCIE_RCAR config option with PCIE_RCAR_HOST config option which built the same driver, so we can now safely drop PCIE_RCAR config option. Signed-off-by: Lad Prabhakar --- Hi All, This patch is exact similar to [1], as all the defconfig files enabling PCIE_RCAR have switched to PCIE_RCAR_HOST and is part of v5.10. PCIE_RCAR can now be safely dropped. [1] http://patchwork.ozlabs.org/project/linux-pci/patch/ 1585856319-4380-4-git-send-email-prabhakar.mahadev-lad...@bp.renesas.com/ Cheers, Prabhakar --- drivers/pci/controller/Kconfig | 9 - 1 file changed, 9 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 64e2f5e379aa..0d98d8dd448b 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -55,15 +55,6 @@ config PCI_RCAR_GEN2 There are 3 internal PCI controllers available with a single built-in EHCI/OHCI host controller present on each one. -config PCIE_RCAR - bool "Renesas R-Car PCIe controller" - depends on ARCH_RENESAS || COMPILE_TEST - depends on PCI_MSI_IRQ_DOMAIN - select PCIE_RCAR_HOST - help - Say Y here if you want PCIe controller support on R-Car SoCs. - This option will be removed after arm64 defconfig is updated. - config PCIE_RCAR_HOST bool "Renesas R-Car PCIe host controller" depends on ARCH_RENESAS || COMPILE_TEST -- 2.17.1
Re: [PATCH v3 2/2] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add support for 8-bit ov7725 sensors
Hi Jacopo, Thank you for the review. On Tue, Dec 15, 2020 at 11:49 AM Jacopo Mondi wrote: > > Hello, > > On Thu, Nov 26, 2020 at 10:30:53AM +, Lad Prabhakar wrote: > > The 8-bit ov7725 sensors can also be connected to the camera daughter > > board. > > > > This patch creates a separate dtsi file for ov7725 sensors and is included > > in r8a7742-iwg21d-q7-dbcm-ca.dts. The user can set VINx_SENSOR depending > > on the cameras connected. > > > > Signed-off-by: Lad Prabhakar > > Reviewed-by: Biju Das > > --- > > .../boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts| 7 ++ > > .../dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi| 112 ++ > > 2 files changed, 119 insertions(+) > > create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi > > > > diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts > > b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts > > index 1ab4f9771a34..915ff5fd437c 100644 > > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts > > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts > > @@ -11,6 +11,7 @@ > > > > #define SENSOR_NONE 1 > > #define SENSOR_OV56402 > > +#define SENSOR_OV77253 > > > > /* 8bit CMOS Camera 1 (J13) */ > > #define CAM1_PARENT_I2C i2c0 > > @@ -40,6 +41,11 @@ > > * VIN2 interface and also the ov5640 node connected to it) > > * #define VIN2_SENSOR SENSOR_NONE > > * > > + * To tie VINx endpoints to ov7725_x endpoints set VINx_SENSOR to > > + * SENSOR_OV7725 for example if ov7725_3 is connected to the VIN3 > > + * interface set the below (this disables the ov5640_3) > > + * #define VIN3_SENSOR SENSOR_OV7725 > > + * > > */ > > #define VIN0_SENSOR SENSOR_OV5640 > > #define VIN1_SENSOR SENSOR_OV5640 > > @@ -47,6 +53,7 @@ > > #define VIN3_SENSOR SENSOR_OV5640 > > > > #include "r8a7742-iwg21d-q7-dbcm-ov5640.dtsi" > > +#include "r8a7742-iwg21d-q7-dbcm-ov7725.dtsi" > > Mmm, can't we alternatively include one .dtsi or the other depending > on a define symbol ? The .dtsi describe pluggable expansion boards, > they cannot be mixed, right ? > Since the cameras on the daughter can be mixed and matched a much better version of the patches [1] which handle this case elegantly has been posted by Geert. [1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20201126134031.4115211-1-ge...@linux-m68k.org/ Cheers, Prabhakar
Re: [PATCH] mtd: spi-nor: winbond: Add support for w25m512jw
Hi Tudor, On Mon, Dec 7, 2020 at 5:27 PM wrote: > > Hi, Lad, > > On 10/16/20 2:55 PM, Lad Prabhakar wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > > content is safe > > > > This chip is (nearly) identical to the Winbond w25m512jv which is > > already supported by Linux. Compared to the w25m512jv, the 'jw' > > has a different JEDEC ID. > > W25M512JW-IQ (2 x 256M-bit) Serial MCP (Multi Chip Package) Flash memory, > introduces a new “Software Die Select (C2h)” instruction, which we don't > support. I guess you can't access the second die with what we have in > mainline. Or am I wrong? We'll need to add support for multi-die support > if we want to add new multi-die flashes. > My bad, yes only the first die is accessible. I'll post a patch dropping this id. Cheers, Prabhakar
[RESEND TAKE 2 PATCH] dt-bindings: ata: renesas,rcar-sata: Add r8a774e1 support
Document SATA support for the RZ/G2H, no driver change required. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Acked-by: Rob Herring Reviewed-by: Geert Uytterhoeven --- Hi All, This patch is part of series [1] (original patch [2]) where rest of the patches have been picked up by the respective maintainers. I haven't received any response for the RESEND patch [3] so resending again. [1] https://patchwork.kernel.org/project/linux-renesas-soc/ list/?series=319563 [2] https://patchwork.kernel.org/patch/11668061/ [3] https://patchwork.kernel.org/project/linux-renesas-soc/ patch/20200921072206.15182-1-prabhakar.mahadev-lad...@bp.renesas.com/ Cheers, Prabhakar --- Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml index d06096a7ba4b..2ad2444f1042 100644 --- a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml +++ b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - renesas,sata-r8a774b1 # RZ/G2N + - renesas,sata-r8a774e1 # RZ/G2H - renesas,sata-r8a7795 # R-Car H3 - renesas,sata-r8a77965 # R-Car M3-N - const: renesas,rcar-gen3-sata # generic R-Car Gen3 or RZ/G2 -- 2.17.1
Re: [PATCH v2 0/5] memory: renesas-rpc-if: Trivial fixes
Hi Krzysztof,
On Thu, Dec 3, 2020 at 1:19 PM Krzysztof Kozlowski wrote:
>
> On Thu, Dec 03, 2020 at 10:41:54AM +0000, Lad, Prabhakar wrote:
> > Hi Krzysztof,
> >
> > On Thu, Nov 26, 2020 at 7:11 PM Lad Prabhakar
> > wrote:
> > >
> > > Hi All,
> > >
> > > This patch series fixes trivial issues in RPC-IF driver.
> > >
> > > Changes for v2:
> > > * Balanced PM in rpcif_disable_rpm
> > > * Fixed typo in patch 4/5
> > > * Dropped C++ style fixes patch
> > > * Included RB tags from Sergei
> > >
> > > Cheers,
> > > Prabhakar
> > >
> > > Lad Prabhakar (5):
> > > memory: renesas-rpc-if: Return correct value to the caller of
> > > rpcif_manual_xfer()
> > > memory: renesas-rpc-if: Fix unbalanced pm_runtime_enable in
> > > rpcif_{enable,disable}_rpm
> > > memory: renesas-rpc-if: Fix a reference leak in rpcif_probe()
> > > memory: renesas-rpc-if: Make rpcif_enable/disable_rpm() as static
> > > inline
> > > memory: renesas-rpc-if: Export symbols as GPL
> > >
> > As these are fixes to the existing driver will these be part of v5.10
> > release ?
>
> Quick look with:
> git lg v5.9..v5.10-rc1 -- drivers/memory/
> did not show that this driver was added in v5.10-rc1, so the fixes are
> not planned to be for v5.10 release never. Why they should be? Maybe I
> missed something here?
>
My bad the fixes can go into v5.11.
Cheers,
Prabhakar
Re: [PATCH v2 0/5] memory: renesas-rpc-if: Trivial fixes
Hi Krzysztof,
On Thu, Nov 26, 2020 at 7:11 PM Lad Prabhakar
wrote:
>
> Hi All,
>
> This patch series fixes trivial issues in RPC-IF driver.
>
> Changes for v2:
> * Balanced PM in rpcif_disable_rpm
> * Fixed typo in patch 4/5
> * Dropped C++ style fixes patch
> * Included RB tags from Sergei
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (5):
> memory: renesas-rpc-if: Return correct value to the caller of
> rpcif_manual_xfer()
> memory: renesas-rpc-if: Fix unbalanced pm_runtime_enable in
> rpcif_{enable,disable}_rpm
> memory: renesas-rpc-if: Fix a reference leak in rpcif_probe()
> memory: renesas-rpc-if: Make rpcif_enable/disable_rpm() as static
> inline
> memory: renesas-rpc-if: Export symbols as GPL
>
As these are fixes to the existing driver will these be part of v5.10 release ?
Cheers,
Prabhakar
> drivers/memory/renesas-rpc-if.c | 28 +---
> include/memory/renesas-rpc-if.h | 13 +++--
> 2 files changed, 20 insertions(+), 21 deletions(-)
>
> --
> 2.25.1
>
Re: [PATCH/RFC] dt-bindings: pci: rcar-pci-ep: Document missing interrupts property
Hi Geert,
Thank you for the patch.
On Thu, Nov 26, 2020 at 2:21 PM Geert Uytterhoeven wrote:
>
> The R-Car PCIe controller does not use interrupts when configured
> for endpoint mode, hence the bindings do not document the interrupt
> property. However, all DTS files provide interrupts properties, and
> thus fail to validate.
>
> Fix this by documenting the interrupts property.
>
> Fixes: 5be478f9c24fbdf8 ("dt-bindings: Another round of adding missing
> 'additionalProperties'")
> Fixes: 4c0f80920923f103 ("dt-bindings: PCI: rcar: Add bindings for R-Car PCIe
> endpoint controller")
> Signed-off-by: Geert Uytterhoeven
> ---
> Alternatively, the interrupts properties should be removed from the
> corresponding device nodes in the DTS files. Obviously they should be
> retained in the device nodes representing PCIe controllers configured in
> host mode, which describe the same hardware...
> ---
> Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml | 9 +
> 1 file changed, 9 insertions(+)
>
Reviewed-by: Lad Prabhakar
Cheers,
Prabhakar
> diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
> b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
> index fb97f4ea0e63682b..32a3b7665ff5473c 100644
> --- a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
> @@ -33,6 +33,10 @@ properties:
>- const: memory2
>- const: memory3
>
> + interrupts:
> +minItems: 3
> +maxItems: 3
> +
>power-domains:
> maxItems: 1
>
> @@ -54,6 +58,7 @@ required:
>- compatible
>- reg
>- reg-names
> + - interrupts
>- resets
>- power-domains
>- clocks
> @@ -65,6 +70,7 @@ additionalProperties: false
> examples:
>- |
> #include
> +#include
> #include
>
> pcie0_ep: pcie-ep@fe00 {
> @@ -76,6 +82,9 @@ examples:
><0x3000 0x800>,
><0x3800 0x800>;
> reg-names = "apb-base", "memory0", "memory1", "memory2",
> "memory3";
> +interrupts = ,
> + ,
> + ;
> resets = <&cpg 319>;
> power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
> clocks = <&cpg CPG_MOD 319>;
> --
> 2.25.1
>
[PATCH v2 1/5] memory: renesas-rpc-if: Return correct value to the caller of rpcif_manual_xfer()
In the error path of rpcif_manual_xfer() the value of ret is overwritten
by value returned by reset_control_reset() function and thus returning
incorrect value to the caller.
This patch makes sure the correct value is returned to the caller of
rpcif_manual_xfer() by dropping the overwrite of ret in error path.
Also now we ignore the value returned by reset_control_reset() in the
error path and instead print a error message when it fails.
Fixes: ca7d8b980b67f ("memory: add Renesas RPC-IF driver")
Reported-by: Pavel Machek
Signed-off-by: Lad Prabhakar
Cc: sta...@vger.kernel.org
Reviewed-by: Sergei Shtylyov
---
drivers/memory/renesas-rpc-if.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index f2a33a1af836..69f2e2b4cd50 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -508,7 +508,8 @@ int rpcif_manual_xfer(struct rpcif *rpc)
return ret;
err_out:
- ret = reset_control_reset(rpc->rstc);
+ if (reset_control_reset(rpc->rstc))
+ dev_err(rpc->dev, "Failed to reset HW\n");
rpcif_hw_init(rpc, rpc->bus_size == 2);
goto exit;
}
--
2.25.1
[PATCH v2 5/5] memory: renesas-rpc-if: Export symbols as GPL
Renesas RPC-IF driver is licensed under GPL2.0, to be in sync export the
symbols as GPL.
Suggested-by: Pavel Machek
Signed-off-by: Lad Prabhakar
Reviewed-by: Sergei Shtylyov
---
drivers/memory/renesas-rpc-if.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 8d36e221def1..99633986ffda 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -201,7 +201,7 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
return PTR_ERR_OR_ZERO(rpc->rstc);
}
-EXPORT_SYMBOL(rpcif_sw_init);
+EXPORT_SYMBOL_GPL(rpcif_sw_init);
void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
{
@@ -249,7 +249,7 @@ void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
rpc->bus_size = hyperflash ? 2 : 1;
}
-EXPORT_SYMBOL(rpcif_hw_init);
+EXPORT_SYMBOL_GPL(rpcif_hw_init);
static int wait_msg_xfer_end(struct rpcif *rpc)
{
@@ -358,7 +358,7 @@ void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op
*op, u64 *offs,
RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
}
}
-EXPORT_SYMBOL(rpcif_prepare);
+EXPORT_SYMBOL_GPL(rpcif_prepare);
int rpcif_manual_xfer(struct rpcif *rpc)
{
@@ -500,7 +500,7 @@ int rpcif_manual_xfer(struct rpcif *rpc)
rpcif_hw_init(rpc, rpc->bus_size == 2);
goto exit;
}
-EXPORT_SYMBOL(rpcif_manual_xfer);
+EXPORT_SYMBOL_GPL(rpcif_manual_xfer);
ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
{
@@ -529,7 +529,7 @@ ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs,
size_t len, void *buf)
return len;
}
-EXPORT_SYMBOL(rpcif_dirmap_read);
+EXPORT_SYMBOL_GPL(rpcif_dirmap_read);
static int rpcif_probe(struct platform_device *pdev)
{
--
2.25.1
[PATCH v2 3/5] memory: renesas-rpc-if: Fix a reference leak in rpcif_probe()
Release the node reference by calling of_node_put(flash) in the probe.
Fixes: ca7d8b980b67f ("memory: add Renesas RPC-IF driver")
Reported-by: Pavel Machek
Signed-off-by: Lad Prabhakar
Cc: sta...@vger.kernel.org
Reviewed-by: Sergei Shtylyov
---
drivers/memory/renesas-rpc-if.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index a8d0ba368625..da0fdb4c7595 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -561,9 +561,11 @@ static int rpcif_probe(struct platform_device *pdev)
} else if (of_device_is_compatible(flash, "cfi-flash")) {
name = "rpc-if-hyperflash";
} else {
+ of_node_put(flash);
dev_warn(&pdev->dev, "unknown flash type\n");
return -ENODEV;
}
+ of_node_put(flash);
vdev = platform_device_alloc(name, pdev->id);
if (!vdev)
--
2.25.1
[PATCH v2 4/5] memory: renesas-rpc-if: Make rpcif_enable/disable_rpm() as static inline
Define rpcif_enable_rpm() and rpcif_disable_rpm() as static
inline in the header instead of exporting them.
Suggested-by: Pavel Machek
Signed-off-by: Lad Prabhakar
---
drivers/memory/renesas-rpc-if.c | 13 -
include/memory/renesas-rpc-if.h | 13 +++--
2 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index da0fdb4c7595..8d36e221def1 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -12,7 +12,6 @@
#include
#include
#include
-#include
#include
#include
@@ -204,18 +203,6 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
}
EXPORT_SYMBOL(rpcif_sw_init);
-void rpcif_enable_rpm(struct rpcif *rpc)
-{
- pm_runtime_enable(rpc->dev);
-}
-EXPORT_SYMBOL(rpcif_enable_rpm);
-
-void rpcif_disable_rpm(struct rpcif *rpc)
-{
- pm_runtime_disable(rpc->dev);
-}
-EXPORT_SYMBOL(rpcif_disable_rpm);
-
void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
{
u32 dummy;
diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h
index 9ad136682c47..14cfd036268a 100644
--- a/include/memory/renesas-rpc-if.h
+++ b/include/memory/renesas-rpc-if.h
@@ -10,6 +10,7 @@
#ifndef __RENESAS_RPC_IF_H
#define __RENESAS_RPC_IF_H
+#include
#include
enum rpcif_data_dir {
@@ -77,11 +78,19 @@ struct rpcif {
int rpcif_sw_init(struct rpcif *rpc, struct device *dev);
void rpcif_hw_init(struct rpcif *rpc, bool hyperflash);
-void rpcif_enable_rpm(struct rpcif *rpc);
-void rpcif_disable_rpm(struct rpcif *rpc);
void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
size_t *len);
int rpcif_manual_xfer(struct rpcif *rpc);
ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf);
+static inline void rpcif_enable_rpm(struct rpcif *rpc)
+{
+ pm_runtime_enable(rpc->dev);
+}
+
+static inline void rpcif_disable_rpm(struct rpcif *rpc)
+{
+ pm_runtime_disable(rpc->dev);
+}
+
#endif // __RENESAS_RPC_IF_H
--
2.25.1
[PATCH v2 2/5] memory: renesas-rpc-if: Fix unbalanced pm_runtime_enable in rpcif_{enable,disable}_rpm
rpcif_enable_rpm calls pm_runtime_enable, so rpcif_disable_rpm needs to
call pm_runtime_disable and not pm_runtime_put_sync.
Fixes: ca7d8b980b67f ("memory: add Renesas RPC-IF driver")
Reported-by: Reported-by: Geert Uytterhoeven
Signed-off-by: Lad Prabhakar
Cc: sta...@vger.kernel.org
---
drivers/memory/renesas-rpc-if.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 69f2e2b4cd50..a8d0ba368625 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -212,7 +212,7 @@ EXPORT_SYMBOL(rpcif_enable_rpm);
void rpcif_disable_rpm(struct rpcif *rpc)
{
- pm_runtime_put_sync(rpc->dev);
+ pm_runtime_disable(rpc->dev);
}
EXPORT_SYMBOL(rpcif_disable_rpm);
--
2.25.1
[PATCH v2 0/5] memory: renesas-rpc-if: Trivial fixes
Hi All,
This patch series fixes trivial issues in RPC-IF driver.
Changes for v2:
* Balanced PM in rpcif_disable_rpm
* Fixed typo in patch 4/5
* Dropped C++ style fixes patch
* Included RB tags from Sergei
Cheers,
Prabhakar
Lad Prabhakar (5):
memory: renesas-rpc-if: Return correct value to the caller of
rpcif_manual_xfer()
memory: renesas-rpc-if: Fix unbalanced pm_runtime_enable in
rpcif_{enable,disable}_rpm
memory: renesas-rpc-if: Fix a reference leak in rpcif_probe()
memory: renesas-rpc-if: Make rpcif_enable/disable_rpm() as static
inline
memory: renesas-rpc-if: Export symbols as GPL
drivers/memory/renesas-rpc-if.c | 28 +---
include/memory/renesas-rpc-if.h | 13 +++--
2 files changed, 20 insertions(+), 21 deletions(-)
--
2.25.1
[PATCH v3 1/2] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Separate out ov5640 nodes
The camera daughter board can also be connected to 8-bit ov7725 sensors,
so in preparation for configurable option to choose depending on the
camera's connected separate out ov5640 nodes in a dtsi file.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
.../boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts| 159 +-
.../dts/r8a7742-iwg21d-q7-dbcm-ov5640.dtsi| 124 ++
2 files changed, 203 insertions(+), 80 deletions(-)
create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640.dtsi
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
index 98c3fbd89fa6..1ab4f9771a34 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
@@ -9,6 +9,77 @@
/dts-v1/;
#include "r8a7742-iwg21d-q7.dts"
+#define SENSOR_NONE1
+#define SENSOR_OV5640 2
+
+/* 8bit CMOS Camera 1 (J13) */
+#define CAM1_PARENT_I2Ci2c0
+#define MCLK_CAM1 mclk_cam1
+#define VIN0_EPvin0ep
+
+/* 8bit CMOS Camera 2 (J14) */
+#define CAM2_PARENT_I2Ci2c1
+#define MCLK_CAM2 mclk_cam2
+#define VIN1_EPvin1ep
+
+/* 8bit CMOS Camera 3 (J12) */
+#define CAM3_PARENT_I2Ci2c2
+#define MCLK_CAM3 mclk_cam3
+#define VIN2_EPvin2ep
+
+/* 8bit CMOS Camera 4 (J11) */
+#define CAM4_PARENT_I2Ci2c3
+#define MCLK_CAM4 mclk_cam4
+#define VIN3_EPvin3ep
+
+/*
+ * Below configuration ties VINx endpoints to ov5640_x endpoints
+ *
+ * To disable a VINx set VINx_SENSOR to SENSOR_NONE for example if no
+ * sensor is connected to VIN2 interface set the below (this disables the
+ * VIN2 interface and also the ov5640 node connected to it)
+ * #define VIN2_SENSORSENSOR_NONE
+ *
+ */
+#define VIN0_SENSORSENSOR_OV5640
+#define VIN1_SENSORSENSOR_OV5640
+#define VIN2_SENSORSENSOR_OV5640
+#define VIN3_SENSORSENSOR_OV5640
+
+#include "r8a7742-iwg21d-q7-dbcm-ov5640.dtsi"
+
+#if (VIN0_SENSOR == SENSOR_NONE)
+#undef VIN0_REMOTE_EP
+#define VIN0_REMOTE_EP 0
+#define VIN0_STATUS"disabled"
+#else
+#define VIN0_STATUS"okay"
+#endif
+
+#if (VIN1_SENSOR == SENSOR_NONE)
+#undef VIN1_REMOTE_EP
+#define VIN1_REMOTE_EP 0
+#define VIN1_STATUS"disabled"
+#else
+#define VIN1_STATUS"okay"
+#endif
+
+#if (VIN2_SENSOR == SENSOR_NONE)
+#undef VIN2_REMOTE_EP
+#define VIN2_REMOTE_EP 0
+#define VIN2_STATUS"disabled"
+#else
+#define VIN2_STATUS"okay"
+#endif
+
+#if (VIN3_SENSOR == SENSOR_NONE)
+#undef VIN3_REMOTE_EP
+#define VIN3_REMOTE_EP 0
+#define VIN3_STATUS"disabled"
+#else
+#define VIN3_STATUS"okay"
+#endif
+
/ {
model = "iWave Systems RZ/G1H Qseven development platform with camera
add-on";
compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";
@@ -91,67 +162,12 @@
status = "okay";
};
-&i2c0 {
- ov5640@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
- clocks = <&mclk_cam1>;
- clock-names = "xclk";
-
- port {
- ov5640_0: endpoint {
- bus-width = <8>;
- data-shift = <2>;
- bus-type = <6>;
- pclk-sample = <1>;
- remote-endpoint = <&vin0ep>;
- };
- };
- };
-};
-
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <40>;
-
- ov5640@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
- clocks = <&mclk_cam2>;
- clock-names = "xclk";
-
- port {
- ov5640_1: endpoint {
- bus-width = <8>;
- data-shift = <2>;
- bus-type = <6>;
- pclk-sample = <1>;
- remote-endpoint = <&vin1ep>;
- };
- };
- };
-};
-
-&i2c2 {
- ov5640@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
- clocks = <&mclk_cam3&
[PATCH v3 2/2] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add support for 8-bit ov7725 sensors
The 8-bit ov7725 sensors can also be connected to the camera daughter
board.
This patch creates a separate dtsi file for ov7725 sensors and is included
in r8a7742-iwg21d-q7-dbcm-ca.dts. The user can set VINx_SENSOR depending
on the cameras connected.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
.../boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts| 7 ++
.../dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi| 112 ++
2 files changed, 119 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
index 1ab4f9771a34..915ff5fd437c 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
@@ -11,6 +11,7 @@
#define SENSOR_NONE1
#define SENSOR_OV5640 2
+#define SENSOR_OV7725 3
/* 8bit CMOS Camera 1 (J13) */
#define CAM1_PARENT_I2Ci2c0
@@ -40,6 +41,11 @@
* VIN2 interface and also the ov5640 node connected to it)
* #define VIN2_SENSORSENSOR_NONE
*
+ * To tie VINx endpoints to ov7725_x endpoints set VINx_SENSOR to
+ * SENSOR_OV7725 for example if ov7725_3 is connected to the VIN3
+ * interface set the below (this disables the ov5640_3)
+ * #define VIN3_SENSORSENSOR_OV7725
+ *
*/
#define VIN0_SENSORSENSOR_OV5640
#define VIN1_SENSORSENSOR_OV5640
@@ -47,6 +53,7 @@
#define VIN3_SENSORSENSOR_OV5640
#include "r8a7742-iwg21d-q7-dbcm-ov5640.dtsi"
+#include "r8a7742-iwg21d-q7-dbcm-ov7725.dtsi"
#if (VIN0_SENSOR == SENSOR_NONE)
#undef VIN0_REMOTE_EP
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi
b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi
new file mode 100644
index ..054d0a7cc5ce
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This include file ties VIN interfaces with ov7725 sensors on
+ * iWave-RZ/G1H Qseven board development platform connected with
+ * camera daughter board.
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#if (VIN0_SENSOR == SENSOR_OV7725)
+#define OV7725_0_STATUS"okay"
+#define OV7725_0_REMOTE_EP &VIN0_EP
+#define VIN0_REMOTE_EP &ov7725_0
+#else
+#define OV7725_0_STATUS"disabled"
+#define OV7725_0_REMOTE_EP 0
+#endif
+
+#if (VIN1_SENSOR == SENSOR_OV7725)
+#define OV7725_1_STATUS"okay"
+#define OV7725_1_REMOTE_EP &VIN1_EP
+#define VIN1_REMOTE_EP &ov7725_1
+#else
+#define OV7725_1_STATUS"disabled"
+#define OV7725_1_REMOTE_EP 0
+#endif
+
+#if (VIN2_SENSOR == SENSOR_OV7725)
+#define OV7725_2_STATUS"okay"
+#define OV7725_2_REMOTE_EP &VIN2_EP
+#define VIN2_REMOTE_EP &ov7725_2
+#else
+#define OV7725_2_STATUS"disabled"
+#define OV7725_2_REMOTE_EP 0
+#endif
+
+#if (VIN3_SENSOR == SENSOR_OV7725)
+#define OV7725_3_STATUS"okay"
+#define OV7725_3_REMOTE_EP &VIN3_EP
+#define VIN3_REMOTE_EP &ov7725_3
+#else
+#define OV7725_3_STATUS"disabled"
+#define OV7725_3_REMOTE_EP 0
+#endif
+
+&CAM1_PARENT_I2C {
+ ov7725@21 {
+ compatible = "ovti,ov7725";
+ reg = <0x21>;
+ clocks = <&MCLK_CAM1>;
+ status = OV7725_0_STATUS;
+
+ port {
+ ov7725_0: endpoint {
+ bus-width = <8>;
+ bus-type = <6>;
+ remote-endpoint = ;
+ };
+ };
+ };
+};
+
+&CAM2_PARENT_I2C {
+ ov7725@21 {
+ compatible = "ovti,ov7725";
+ reg = <0x21>;
+ clocks = <&MCLK_CAM2>;
+ status = OV7725_1_STATUS;
+
+ port {
+ ov7725_1: endpoint {
+ bus-width = <8>;
+ bus-type = <6>;
+ remote-endpoint = ;
+ };
+ };
+ };
+};
+
+&CAM3_PARENT_I2C {
+ ov7725@21 {
+ compatible = "ovti,ov7725";
+ reg = <0x21>;
+ clocks = <&MCLK_CAM3>;
+ status = OV7725_2_STATUS;
+
+ port {
+ ov7725_2: endpoint {
+ bus-width = <8>;
+ bus-type = <6>;
+ remote-endpoint = ;
+ };
+ };
+ };
[PATCH v3 0/2] r8a7742-iwg21d-q7-dbcm: Add support for ov7725 sensors
Hi All, This patch set enables to connect ov7725 sensors on iWave-RZ/G1H Qseven board. This patch is based on top of [1]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/ renesas-devel.git/log/?h=renesas-arm-dt-for-v5.11 Changes for v3: * Added support to mix and match the cameras connected to VINx interfaces. Changes for v2: * Separated out ov5640 ep into a new dtsi v1: https://patchwork.kernel.org/project/linux-renesas-soc/patch/ 20201120151343.24175-1-prabhakar.mahadev-lad...@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (2): ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Separate out ov5640 nodes ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add support for 8-bit ov7725 sensors .../boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts| 166 +- .../dts/r8a7742-iwg21d-q7-dbcm-ov5640.dtsi| 124 + .../dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi| 112 3 files changed, 322 insertions(+), 80 deletions(-) create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640.dtsi create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi -- 2.17.1
Re: [PATCH v2 0/2] r8a7742-iwg21d-q7-dbcm: Add support for ov7725 sensors
Hi Geert,
On Wed, Nov 25, 2020 at 4:32 PM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Wed, Nov 25, 2020 at 5:26 PM Prabhakar Mahadev Lad
> wrote:
> > > -Original Message-
> > > From: Geert Uytterhoeven
> > > Sent: 25 November 2020 16:21
> > > To: Prabhakar Mahadev Lad
> > > Cc: Magnus Damm ; Rob Herring
> > > ; Linux-Renesas > > renesas-...@vger.kernel.org>; open list:OPEN FIRMWARE AND FLATTENED
> > > DEVICE TREE BINDINGS
> > > ; Linux Kernel Mailing List
> > > ; Biju Das
> > > ; Prabhakar
> > > Subject: Re: [PATCH v2 0/2] r8a7742-iwg21d-q7-dbcm: Add support for
> > > ov7725 sensors
> > >
> > > Hi Prabhakar,
> > >
> > > On Wed, Nov 25, 2020 at 2:02 PM Lad Prabhakar
> > > wrote:
> > > > This patch set enables to connect ov7725 sensors on iWave-RZ/G1H Qseven
> > > > board.
> > >
> > > Thanks for your series!
> > >
> > > Do you think it's a valid use case to mix and match ov5640 and ov7725
> > > cameras? E.g. connect two of each?
> > >
> > Yes that is valid case to mix and match. Do you want me to make it
> > configurable too ?
>
> If this is a valid use case, then please do so.
>
In that case do we still want to keep the ov7725/ov5640 nodes in
separate dtsi ?
Cheers,
Prabhakar
> Thanks!
>
> > > Or should all four cameras be of the same type?
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
Re: [PATCH 2/5] memory: renesas-rpc-if: Make rpcif_enable/disable_rpm() as static inline
Hi Geert,
Thank you for the review.
On Tue, Nov 24, 2020 at 3:43 PM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Tue, Nov 24, 2020 at 12:27 PM Lad Prabhakar
> wrote:
> > Define rpcif_enable_rpm() and rpcif_disable_rpm() as static
> > inline in the header instead of exporting it.
> >
> > Suggested-by: Pavel Machek
> > Signed-off-by: Lad Prabhakar
>
> Thanks for your patch, which is an improvement.
>
> > --- a/include/memory/renesas-rpc-if.h
> > +++ b/include/memory/renesas-rpc-if.h
> > @@ -10,6 +10,7 @@
> > #ifndef __RENESAS_RPC_IF_H
> > #define __RENESAS_RPC_IF_H
> >
> > +#include
> > #include
> >
> > enum rpcif_data_dir {
> > @@ -77,11 +78,19 @@ struct rpcif {
> >
> > int rpcif_sw_init(struct rpcif *rpc, struct device *dev);
> > void rpcif_hw_init(struct rpcif *rpc, bool hyperflash);
> > -void rpcif_enable_rpm(struct rpcif *rpc);
> > -void rpcif_disable_rpm(struct rpcif *rpc);
> > void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
> >size_t *len);
> > int rpcif_manual_xfer(struct rpcif *rpc);
> > ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void
> > *buf);
> >
> > +static inline void rpcif_enable_rpm(struct rpcif *rpc)
> > +{
> > + pm_runtime_enable(rpc->dev);
> > +}
> > +
> > +static inline void rpcif_disable_rpm(struct rpcif *rpc)
> > +{
> > + pm_runtime_put_sync(rpc->dev);
>
> Looking at how this is used, this should call pm_runtime_disable()
> instead.
>
> And probably this should be moved inside the core RPC-IF driver:
> 1. pm_runtime_enable() could be called from rpcif_sw_init(),
> 2. pm_runtime_put_sync() can be called from a new rpc_sw_deinit()
> function, to be called by the SPI and MTD drivers on probe failure
> and on remove.
>
Totally agree.
Sergei are you OK with the above suggestions ?
Cheers,
Prabhakar
Re: [PATCH 0/5] memory: renesas-rpc-if: Trivial fixes
On Tue, Nov 24, 2020 at 6:25 PM Sergei Shtylyov wrote: > > On 11/24/20 2:34 PM, Lad, Prabhakar wrote: > > [...] > >> This patch series fixes trivial issues in RPC-IF driver. > >> > >> Cheers, > >> Prabhakar > >> > >> Lad Prabhakar (5): > >> memory: renesas-rpc-if: Return correct value to the caller of > >> rpcif_manual_xfer() > >> memory: renesas-rpc-if: Make rpcif_enable/disable_rpm() as static > >> inline > >> memory: renesas-rpc-if: Export symbols as GPL > >> memory: renesas-rpc-if: Avoid use of C++ style comments > >> memory: renesas-rpc-if: Fix a reference leak in rpcif_probe() > >> > > Patches sent to sergei.shtyl...@cogentembedded.com have bounced back > > so including gmail address (patchwork [1]). > >Sorry, I got laid off by Cogent last May. Thanks for CCing my gmail > address... > Sorry to hear that. Thank you for the review. I'll fix the review comments for patch 2/2 and post a v2. Cheers, Prabhakar
[PATCH v2 1/2] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Separate out ov5640 nodes
The camera daughter board can also be connected to 8-bit ov7725 sensors,
so in preparation for configurable option to choose depending on the
camera's connected separate out ov5640 nodes in a dtsi file.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
.../boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts| 102 +-
.../dts/r8a7742-iwg21d-q7-dbcm-ov5640.dtsi| 89 +++
2 files changed, 115 insertions(+), 76 deletions(-)
create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640.dtsi
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
index 98c3fbd89fa6..a632b08a8dbb 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
@@ -9,6 +9,28 @@
/dts-v1/;
#include "r8a7742-iwg21d-q7.dts"
+/* 8bit CMOS Camera 1 (J13) */
+#define CAM1_PARENT_I2Ci2c0
+#define MCLK_CAM1 mclk_cam1
+#define VIN0_EPvin0ep
+
+/* 8bit CMOS Camera 2 (J14) */
+#define CAM2_PARENT_I2Ci2c1
+#define MCLK_CAM2 mclk_cam2
+#define VIN1_EPvin1ep
+
+/* 8bit CMOS Camera 3 (J12) */
+#define CAM3_PARENT_I2Ci2c2
+#define MCLK_CAM3 mclk_cam3
+#define VIN2_EPvin2ep
+
+/* 8bit CMOS Camera 4 (J11) */
+#define CAM4_PARENT_I2Ci2c3
+#define MCLK_CAM4 mclk_cam4
+#define VIN3_EPvin3ep
+
+#include "r8a7742-iwg21d-q7-dbcm-ov5640.dtsi"
+
/ {
model = "iWave Systems RZ/G1H Qseven development platform with camera
add-on";
compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";
@@ -91,67 +113,12 @@
status = "okay";
};
-&i2c0 {
- ov5640@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
- clocks = <&mclk_cam1>;
- clock-names = "xclk";
-
- port {
- ov5640_0: endpoint {
- bus-width = <8>;
- data-shift = <2>;
- bus-type = <6>;
- pclk-sample = <1>;
- remote-endpoint = <&vin0ep>;
- };
- };
- };
-};
-
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <40>;
-
- ov5640@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
- clocks = <&mclk_cam2>;
- clock-names = "xclk";
-
- port {
- ov5640_1: endpoint {
- bus-width = <8>;
- data-shift = <2>;
- bus-type = <6>;
- pclk-sample = <1>;
- remote-endpoint = <&vin1ep>;
- };
- };
- };
-};
-
-&i2c2 {
- ov5640@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
- clocks = <&mclk_cam3>;
- clock-names = "xclk";
-
- port {
- ov5640_2: endpoint {
- bus-width = <8>;
- data-shift = <2>;
- bus-type = <6>;
- pclk-sample = <1>;
- remote-endpoint = <&vin2ep>;
- };
- };
- };
};
&i2c3 {
@@ -160,23 +127,6 @@
status = "okay";
clock-frequency = <40>;
-
- ov5640@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
- clocks = <&mclk_cam4>;
- clock-names = "xclk";
-
- port {
- ov5640_3: endpoint {
- bus-width = <8>;
- data-shift = <2>;
- bus-type = <6>;
- pclk-sample = <1>;
- remote-endpoint = <&vin3ep>;
- };
- };
- };
};
&pfc {
@@ -278,7 +228,7 @@
port {
vin0ep: endpoint {
- remote-endpoint = <&ov5640_0>;
+ remote-endpoint = <&VIN0_REMOTE_EP>;
bus-width = <8>;
[PATCH v2 2/2] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add support for 8-bit ov7725 sensors
The 8-bit ov7725 sensors can also be connected to the camera daughter
board.
This patch creates a separate dtsi file for ov7725 sensors and is included
in r8a7742-iwg21d-q7-dbcm-ca.dts (which is commented out as by default
ov5640 is enabled)
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
.../boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts| 2 +
.../dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi| 77 +++
2 files changed, 79 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
index a632b08a8dbb..6216a6b0f927 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
@@ -29,7 +29,9 @@
#define MCLK_CAM4 mclk_cam4
#define VIN3_EPvin3ep
+/* Comment the below according to connected cameras */
#include "r8a7742-iwg21d-q7-dbcm-ov5640.dtsi"
+/* #include "r8a7742-iwg21d-q7-dbcm-ov7725.dtsi" */
/ {
model = "iWave Systems RZ/G1H Qseven development platform with camera
add-on";
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi
b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi
new file mode 100644
index ..28b509942702
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This include file ties VIN interfaces with ov7725 sensors on
+ * iWave-RZ/G1H Qseven board development platform connected with
+ * camera daughter board.
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#define VIN0_REMOTE_EP ov7725_0
+#define VIN1_REMOTE_EP ov7725_1
+#define VIN2_REMOTE_EP ov7725_2
+#define VIN3_REMOTE_EP ov7725_3
+
+&CAM1_PARENT_I2C {
+ ov7725@21 {
+ compatible = "ovti,ov7725";
+ reg = <0x21>;
+ clocks = <&MCLK_CAM1>;
+
+ port {
+ ov7725_0: endpoint {
+ bus-width = <8>;
+ bus-type = <6>;
+ remote-endpoint = <&VIN0_EP>;
+ };
+ };
+ };
+};
+
+&CAM2_PARENT_I2C {
+ ov7725@21 {
+ compatible = "ovti,ov7725";
+ reg = <0x21>;
+ clocks = <&MCLK_CAM2>;
+
+ port {
+ ov7725_1: endpoint {
+ bus-width = <8>;
+ bus-type = <6>;
+ remote-endpoint = <&VIN1_EP>;
+ };
+ };
+ };
+};
+
+&CAM3_PARENT_I2C {
+ ov7725@21 {
+ compatible = "ovti,ov7725";
+ reg = <0x21>;
+ clocks = <&MCLK_CAM3>;
+
+ port {
+ ov7725_2: endpoint {
+ bus-width = <8>;
+ bus-type = <6>;
+ remote-endpoint = <&VIN2_EP>;
+ };
+ };
+ };
+};
+
+&CAM4_PARENT_I2C {
+ ov7725@21 {
+ compatible = "ovti,ov7725";
+ reg = <0x21>;
+ clocks = <&MCLK_CAM4>;
+
+ port {
+ ov7725_3: endpoint {
+ bus-width = <8>;
+ bus-type = <6>;
+ remote-endpoint = <&VIN3_EP>;
+ };
+ };
+ };
+};
--
2.17.1
[PATCH v2 0/2] r8a7742-iwg21d-q7-dbcm: Add support for ov7725 sensors
Hi All, This patch set enables to connect ov7725 sensors on iWave-RZ/G1H Qseven board. This patch is based on top of [1]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/ renesas-devel.git/log/?h=renesas-arm-dt-for-v5.11 Changes for v2: * Separated out ov5640 ep into a dtsi v1: https://patchwork.kernel.org/project/linux-renesas-soc/patch/ 20201120151343.24175-1-prabhakar.mahadev-lad...@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (2): ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Separate out ov5640 nodes ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add support for 8-bit ov7725 sensors .../boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts| 104 +- .../dts/r8a7742-iwg21d-q7-dbcm-ov5640.dtsi| 89 +++ .../dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi| 77 + 3 files changed, 194 insertions(+), 76 deletions(-) create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640.dtsi create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725.dtsi -- 2.17.1
Re: [PATCH] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add OV7725 nodes
Hi Geert,
Thank you for the review.
On Tue, Nov 24, 2020 at 9:04 AM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Fri, Nov 20, 2020 at 4:13 PM Lad Prabhakar
> wrote:
> > Add the ov7725 endpoint nodes to the camera daughter board. The ov7725
> > sensors can be populated on I2C{0,1,2,3} buses.
> >
> > By default the VIN{0,1,2,3} are tied to OV5640{0,1,2,3} endpoints
> > respectively in the camera DB dts hence the remote-endpoint property in
> > OV7725{0,1,2,3} endpoints is commented out.
> >
> > Signed-off-by: Lad Prabhakar
> > Reviewed-by: Biju Das
>
> Thanks for your patch!
>
> The camera definitions look mostly OK to me.
>
> IIUIC, these are 4 plug-in cameras, that can be used instead of the
> (currently described) 4 other OV5640-based plug-in cameras?
> In addition, the user can mix and match them, in the 4 available
> slots (J11-J14), which would require editing the DTS?
>
> Wouldn't it be easier to have separate DTS files for the OV7725 and
> OV5640 cameras, and #include them from r8a7742-iwg21d-q7-dbcm-ca.dts?
>
Good point, will move the vin and ov5640 nodes to
r8a7742-iwg21d-q7-dbcm-ov5640.dtsi and similarly add vin and ov7725
nodes to r8a7742-iwg21d-q7-dbcm-ov7725.dtsi and by default shall
include r8a7742-iwg21d-q7-dbcm-ov5640.dtsi in
r8a7742-iwg21d-q7-dbcm-ca.dts file.(Will keep the mclk_camx and
pimuxes in r8a7742-iwg21d-q7-dbcm-ca.dts file)
> /* 8bit CMOS Camera 1 (J13) */
> #define MCLK_CAM&mclk_cam1
> #define ...
> /* Comment the below according to connected cameras */
> #include "ov5640.dts"
> //#include "ov7725.dts"
> #undef MCLK_CAM
> #undef ...
>
> [...]
>
> > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
> > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
>
> > @@ -152,6 +198,30 @@
> > };
> > };
> > };
> > +
> > + ov7725@21 {
> > + status = "disabled";
>
> This one is disabled, the three others aren't?
>
my bad should have dropped this.
Cheers,
Prabhakar
> > + compatible = "ovti,ov7725";
> > + reg = <0x21>;
> > + clocks = <&mclk_cam3>;
> > +
> > + port {
> > + ov7725_2: endpoint {
> > + bus-width = <8>;
> > + bus-type = <6>;
> > + /*
> > +* uncomment remote-endpoint property to
> > +* tie ov7725_2 to vin2ep also make
> > +* sure to comment/remove remote-endpoint
> > +* property from ov5640_2 endpoint and
> > +* replace remote-endpoint property in
> > +* vin2ep node with
> > +* remote-endpoint = <&ov7725_2>;
> > +*/
> > + /* remote-endpoint = <&vin2ep>; */
> > + };
> > + };
> > + };
> > };
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
Re: [PATCH 0/5] memory: renesas-rpc-if: Trivial fixes
Hi Sergei, On Tue, Nov 24, 2020 at 11:26 AM Lad Prabhakar wrote: > > Hi All, > > This patch series fixes trivial issues in RPC-IF driver. > > Cheers, > Prabhakar > > Lad Prabhakar (5): > memory: renesas-rpc-if: Return correct value to the caller of > rpcif_manual_xfer() > memory: renesas-rpc-if: Make rpcif_enable/disable_rpm() as static > inline > memory: renesas-rpc-if: Export symbols as GPL > memory: renesas-rpc-if: Avoid use of C++ style comments > memory: renesas-rpc-if: Fix a reference leak in rpcif_probe() > Patches sent to sergei.shtyl...@cogentembedded.com have bounced back so including gmail address (patchwork [1]). [1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=390163 Cheers, Prabhakar > drivers/memory/renesas-rpc-if.c | 28 +--- > include/memory/renesas-rpc-if.h | 19 ++- > 2 files changed, 23 insertions(+), 24 deletions(-) > > -- > 2.17.1 >
[PATCH 1/5] memory: renesas-rpc-if: Return correct value to the caller of rpcif_manual_xfer()
In the error path of rpcif_manual_xfer() the value of ret is overwritten
by value returned by reset_control_reset() function and thus returning
incorrect value to the caller.
This patch makes sure the correct value is returned to the caller of
rpcif_manual_xfer() by dropping the overwrite of ret in error path.
Also now we ignore the value returned by reset_control_reset() in the
error path and instead print a error message when it fails.
Fixes: ca7d8b980b67f ("memory: add Renesas RPC-IF driver")
Reported-by: Pavel Machek
Signed-off-by: Lad Prabhakar
Cc: sta...@vger.kernel.org
---
drivers/memory/renesas-rpc-if.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index f2a33a1af836..69f2e2b4cd50 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -508,7 +508,8 @@ int rpcif_manual_xfer(struct rpcif *rpc)
return ret;
err_out:
- ret = reset_control_reset(rpc->rstc);
+ if (reset_control_reset(rpc->rstc))
+ dev_err(rpc->dev, "Failed to reset HW\n");
rpcif_hw_init(rpc, rpc->bus_size == 2);
goto exit;
}
--
2.17.1
[PATCH 5/5] memory: renesas-rpc-if: Fix a reference leak in rpcif_probe()
Release the node reference by calling of_node_put(flash) in the probe.
Fixes: ca7d8b980b67f ("memory: add Renesas RPC-IF driver")
Reported-by: Pavel Machek
Signed-off-by: Lad Prabhakar
Cc: sta...@vger.kernel.org
---
drivers/memory/renesas-rpc-if.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index f5cbc762fda7..99633986ffda 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -548,9 +548,11 @@ static int rpcif_probe(struct platform_device *pdev)
} else if (of_device_is_compatible(flash, "cfi-flash")) {
name = "rpc-if-hyperflash";
} else {
+ of_node_put(flash);
dev_warn(&pdev->dev, "unknown flash type\n");
return -ENODEV;
}
+ of_node_put(flash);
vdev = platform_device_alloc(name, pdev->id);
if (!vdev)
--
2.17.1
[PATCH 4/5] memory: renesas-rpc-if: Avoid use of C++ style comments
Replace C++ style comment with C style.
While at it also replace the tab with a space between struct and
struct name.
Suggested-by: Pavel Machek
Signed-off-by: Lad Prabhakar
---
include/memory/renesas-rpc-if.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h
index b8c7cc63065f..30ea6bd969b4 100644
--- a/include/memory/renesas-rpc-if.h
+++ b/include/memory/renesas-rpc-if.h
@@ -19,7 +19,7 @@ enum rpcif_data_dir {
RPCIF_DATA_OUT,
};
-struct rpcif_op {
+struct rpcif_op {
struct {
u8 buswidth;
u8 opcode;
@@ -57,7 +57,7 @@ structrpcif_op {
} data;
};
-struct rpcif {
+struct rpcif {
struct device *dev;
void __iomem *dirmap;
struct regmap *regmap;
@@ -93,4 +93,4 @@ static inline void rpcif_disable_rpm(struct rpcif *rpc)
pm_runtime_put_sync(rpc->dev);
}
-#endif // __RENESAS_RPC_IF_H
+#endif /* __RENESAS_RPC_IF_H */
--
2.17.1
[PATCH 3/5] memory: renesas-rpc-if: Export symbols as GPL
Renesas RPC-IF driver is licensed under GPL2.0, to be in sync export the
symbols as GPL.
Suggested-by: Pavel Machek
Signed-off-by: Lad Prabhakar
---
drivers/memory/renesas-rpc-if.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index c5b5691503d7..f5cbc762fda7 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -201,7 +201,7 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
return PTR_ERR_OR_ZERO(rpc->rstc);
}
-EXPORT_SYMBOL(rpcif_sw_init);
+EXPORT_SYMBOL_GPL(rpcif_sw_init);
void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
{
@@ -249,7 +249,7 @@ void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
rpc->bus_size = hyperflash ? 2 : 1;
}
-EXPORT_SYMBOL(rpcif_hw_init);
+EXPORT_SYMBOL_GPL(rpcif_hw_init);
static int wait_msg_xfer_end(struct rpcif *rpc)
{
@@ -358,7 +358,7 @@ void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op
*op, u64 *offs,
RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
}
}
-EXPORT_SYMBOL(rpcif_prepare);
+EXPORT_SYMBOL_GPL(rpcif_prepare);
int rpcif_manual_xfer(struct rpcif *rpc)
{
@@ -500,7 +500,7 @@ int rpcif_manual_xfer(struct rpcif *rpc)
rpcif_hw_init(rpc, rpc->bus_size == 2);
goto exit;
}
-EXPORT_SYMBOL(rpcif_manual_xfer);
+EXPORT_SYMBOL_GPL(rpcif_manual_xfer);
ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
{
@@ -529,7 +529,7 @@ ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs,
size_t len, void *buf)
return len;
}
-EXPORT_SYMBOL(rpcif_dirmap_read);
+EXPORT_SYMBOL_GPL(rpcif_dirmap_read);
static int rpcif_probe(struct platform_device *pdev)
{
--
2.17.1
[PATCH 2/5] memory: renesas-rpc-if: Make rpcif_enable/disable_rpm() as static inline
Define rpcif_enable_rpm() and rpcif_disable_rpm() as static
inline in the header instead of exporting it.
Suggested-by: Pavel Machek
Signed-off-by: Lad Prabhakar
---
drivers/memory/renesas-rpc-if.c | 13 -
include/memory/renesas-rpc-if.h | 13 +++--
2 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 69f2e2b4cd50..c5b5691503d7 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -12,7 +12,6 @@
#include
#include
#include
-#include
#include
#include
@@ -204,18 +203,6 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
}
EXPORT_SYMBOL(rpcif_sw_init);
-void rpcif_enable_rpm(struct rpcif *rpc)
-{
- pm_runtime_enable(rpc->dev);
-}
-EXPORT_SYMBOL(rpcif_enable_rpm);
-
-void rpcif_disable_rpm(struct rpcif *rpc)
-{
- pm_runtime_put_sync(rpc->dev);
-}
-EXPORT_SYMBOL(rpcif_disable_rpm);
-
void rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
{
u32 dummy;
diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h
index 9ad136682c47..b8c7cc63065f 100644
--- a/include/memory/renesas-rpc-if.h
+++ b/include/memory/renesas-rpc-if.h
@@ -10,6 +10,7 @@
#ifndef __RENESAS_RPC_IF_H
#define __RENESAS_RPC_IF_H
+#include
#include
enum rpcif_data_dir {
@@ -77,11 +78,19 @@ struct rpcif {
int rpcif_sw_init(struct rpcif *rpc, struct device *dev);
void rpcif_hw_init(struct rpcif *rpc, bool hyperflash);
-void rpcif_enable_rpm(struct rpcif *rpc);
-void rpcif_disable_rpm(struct rpcif *rpc);
void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
size_t *len);
int rpcif_manual_xfer(struct rpcif *rpc);
ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf);
+static inline void rpcif_enable_rpm(struct rpcif *rpc)
+{
+ pm_runtime_enable(rpc->dev);
+}
+
+static inline void rpcif_disable_rpm(struct rpcif *rpc)
+{
+ pm_runtime_put_sync(rpc->dev);
+}
+
#endif // __RENESAS_RPC_IF_H
--
2.17.1
[PATCH 0/5] memory: renesas-rpc-if: Trivial fixes
Hi All, This patch series fixes trivial issues in RPC-IF driver. Cheers, Prabhakar Lad Prabhakar (5): memory: renesas-rpc-if: Return correct value to the caller of rpcif_manual_xfer() memory: renesas-rpc-if: Make rpcif_enable/disable_rpm() as static inline memory: renesas-rpc-if: Export symbols as GPL memory: renesas-rpc-if: Avoid use of C++ style comments memory: renesas-rpc-if: Fix a reference leak in rpcif_probe() drivers/memory/renesas-rpc-if.c | 28 +--- include/memory/renesas-rpc-if.h | 19 ++- 2 files changed, 23 insertions(+), 24 deletions(-) -- 2.17.1
[PATCH] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add OV7725 nodes
Add the ov7725 endpoint nodes to the camera daughter board. The ov7725
sensors can be populated on I2C{0,1,2,3} buses.
By default the VIN{0,1,2,3} are tied to OV5640{0,1,2,3} endpoints
respectively in the camera DB dts hence the remote-endpoint property in
OV7725{0,1,2,3} endpoints is commented out.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
Hi All,
This patch is based on top of [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/
renesas-devel.git/log/?h=renesas-arm-dt-for-v5.11
Cheers,
Prabhakar
---
.../boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts| 93 +++
1 file changed, 93 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
index 98c3fbd89fa6..d1386bf7bdbe 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
@@ -108,6 +108,29 @@
};
};
};
+
+ ov7725@21 {
+ compatible = "ovti,ov7725";
+ reg = <0x21>;
+ clocks = <&mclk_cam1>;
+
+ port {
+ ov7725_0: endpoint {
+ bus-width = <8>;
+ bus-type = <6>;
+ /*
+* uncomment remote-endpoint property to
+* tie ov7725_0 to vin0ep also make
+* sure to comment/remove remote-endpoint
+* property from ov5640_0 endpoint and
+* replace remote-endpoint property in
+* vin0ep node with
+* remote-endpoint = <&ov7725_0>;
+*/
+ /* remote-endpoint = <&vin0ep>; */
+ };
+ };
+ };
};
&i2c1 {
@@ -133,6 +156,29 @@
};
};
};
+
+ ov7725@21 {
+ compatible = "ovti,ov7725";
+ reg = <0x21>;
+ clocks = <&mclk_cam2>;
+
+ port {
+ ov7725_1: endpoint {
+ bus-width = <8>;
+ bus-type = <6>;
+ /*
+* uncomment remote-endpoint property to
+* tie ov7725_1 to vin1ep also make
+* sure to comment/remove remote-endpoint
+* property from ov5640_1 endpoint and
+* replace remote-endpoint property in
+* vin1ep node with
+* remote-endpoint = <&ov7725_1>;
+*/
+ /* remote-endpoint = <&vin1ep>; */
+ };
+ };
+ };
};
&i2c2 {
@@ -152,6 +198,30 @@
};
};
};
+
+ ov7725@21 {
+ status = "disabled";
+ compatible = "ovti,ov7725";
+ reg = <0x21>;
+ clocks = <&mclk_cam3>;
+
+ port {
+ ov7725_2: endpoint {
+ bus-width = <8>;
+ bus-type = <6>;
+ /*
+* uncomment remote-endpoint property to
+* tie ov7725_2 to vin2ep also make
+* sure to comment/remove remote-endpoint
+* property from ov5640_2 endpoint and
+* replace remote-endpoint property in
+* vin2ep node with
+* remote-endpoint = <&ov7725_2>;
+*/
+ /* remote-endpoint = <&vin2ep>; */
+ };
+ };
+ };
};
&i2c3 {
@@ -177,6 +247,29 @@
};
};
};
+
+ ov7725@21 {
+ compatible = "ovti,ov7725";
+ reg = <0x21>;
+ clocks = <&mclk_cam4>;
+
+ port {
+ ov7725_3: endpoint {
+ bus-width = <8>;
+ bus-type = <6>;
+ /*
+* uncomment remote-endpoint property to
+* tie ov7725_3 to vin3ep also make
+
Re: [PATCH 1/4] pinctrl: renesas: r8a77990: Add QSPI[01] pins, groups and functions
Hi Geert,
Thank you for the review.
On Fri, Nov 20, 2020 at 9:20 AM Geert Uytterhoeven wrote:
>
> On Thu, Nov 19, 2020 at 2:09 PM Lad Prabhakar
> wrote:
> > Add pins, groups and functions for QSPIO[01].
> >
> > Signed-off-by: Lad Prabhakar
> > Reviewed-by: Biju Das
>
> Reviewed-by: Geert Uytterhoeven
> i.e. will queue in renesas-pinctrl-for-v5.11...
>
> > --- a/drivers/pinctrl/renesas/pfc-r8a77990.c
> > +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
> > @@ -2810,6 +2810,57 @@ static const unsigned int pwm6_b_mux[] = {
> > PWM6_B_MARK,
> > };
> >
> > +/* - QSPI0
> > -- */
> > +static const unsigned int qspi0_ctrl_pins[] = {
> > + /* SPCLK, SSL */
>
> ... with the missing QSPI0_ prefix added...
>
Argh missed that.
> > + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5),
> > +};
> > +static const unsigned int qspi0_ctrl_mux[] = {
> > + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
> > +};
> > +static const unsigned int qspi0_data2_pins[] = {
> > + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
> > + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
> > +};
> > +static const unsigned int qspi0_data2_mux[] = {
> > + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
> > +};
> > +static const unsigned int qspi0_data4_pins[] = {
> > + /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
> > + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
> > + /* QSPI0_IO2, QSPI0_IO3 */
>
> ... and the bogus space dropped.
>
Thanks for taking care of it.
Cheers,
Prabhakar
> > + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
> > +};
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
[PATCH 3/4] pinctrl: renesas: r8a7796: Add QSPI[01] pins, groups and functions
Add pins, groups and functions for QSPIO[01].
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc-r8a7796.c | 75 ++-
1 file changed, 73 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c
b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 6e8e023410c4..aea7cb6bd41d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -3257,6 +3257,57 @@ static const unsigned int pwm6_b_mux[] = {
PWM6_B_MARK,
};
+/* - QSPI0 --
*/
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* QSPI0_SPCLK, QSPI0_SSL */
+ PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
+};
+static const unsigned int qspi0_data2_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
+ /* QSPI0_IO2, QSPI0_IO3 */
+ PIN_QSPI0_IO2, PIN_QSPI0_IO3,
+};
+static const unsigned int qspi0_data4_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+};
+/* - QSPI1 --
*/
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* QSPI1_SPCLK, QSPI1_SSL */
+ PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
+};
+static const unsigned int qspi1_data2_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
+ /* QSPI1_IO2, QSPI1_IO3 */
+ PIN_QSPI1_IO2, PIN_QSPI1_IO3,
+};
+static const unsigned int qspi1_data4_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+
/* - SCIF0 --
*/
static const unsigned int scif0_data_pins[] = {
/* RX, TX */
@@ -4134,7 +4185,7 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[316];
+ struct sh_pfc_pin_group common[322];
#if defined(CONFIG_PINCTRL_PFC_R8A77960) ||
defined(CONFIG_PINCTRL_PFC_R8A77961)
struct sh_pfc_pin_group automotive[30];
#endif
@@ -4339,6 +4390,12 @@ static const struct {
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ SH_PFC_PIN_GROUP(qspi0_data2),
+ SH_PFC_PIN_GROUP(qspi0_data4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ SH_PFC_PIN_GROUP(qspi1_data2),
+ SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -4829,6 +4886,18 @@ static const char * const pwm6_groups[] = {
"pwm6_b",
};
+static const char * const qspi0_groups[] = {
+ "qspi0_ctrl",
+ "qspi0_data2",
+ "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+ "qspi1_ctrl",
+ "qspi1_data2",
+ "qspi1_data4",
+};
+
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
@@ -5004,7 +5073,7 @@ static const char * const vin5_groups[] = {
};
static const struct {
- struct sh_pfc_function common[50];
+ struct sh_pfc_function common[52];
#if defined(CONFIG_PINCTRL_PFC_R8A77960) ||
defined(CONFIG_PINCTRL_PFC_R8A77961)
struct sh_pfc_function automotive[4];
#endif
@@ -5041,6 +5110,8 @@ static const struct {
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(qspi0),
+ SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
--
2.17.1
[PATCH 4/4] pinctrl: renesas: r8a77965: Add QSPI[01] pins, groups and functions
Add pins, groups and functions for QSPIO[01].
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc-r8a77965.c | 75 +-
1 file changed, 73 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c
b/drivers/pinctrl/renesas/pfc-r8a77965.c
index 590e5f8006d4..92f231baff7d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -3408,6 +3408,57 @@ static const unsigned int pwm6_b_mux[] = {
PWM6_B_MARK,
};
+/* - QSPI0 --
*/
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* QSPI0_SPCLK, QSPI0_SSL */
+ PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
+};
+static const unsigned int qspi0_data2_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
+ /* QSPI0_IO2, QSPI0_IO3 */
+ PIN_QSPI0_IO2, PIN_QSPI0_IO3,
+};
+static const unsigned int qspi0_data4_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+};
+/* - QSPI1 --
*/
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* QSPI1_SPCLK, QSPI1_SSL */
+ PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
+};
+static const unsigned int qspi1_data2_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
+ /* QSPI1_IO2, QSPI1_IO3 */
+ PIN_QSPI1_IO2, PIN_QSPI1_IO3,
+};
+static const unsigned int qspi1_data4_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+
/* - SATA
*/
static const unsigned int sata0_devslp_a_pins[] = {
/* DEVSLP */
@@ -4381,7 +4432,7 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[318];
+ struct sh_pfc_pin_group common[324];
#ifdef CONFIG_PINCTRL_PFC_R8A77965
struct sh_pfc_pin_group automotive[30];
#endif
@@ -4586,6 +4637,12 @@ static const struct {
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ SH_PFC_PIN_GROUP(qspi0_data2),
+ SH_PFC_PIN_GROUP(qspi0_data4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ SH_PFC_PIN_GROUP(qspi1_data2),
+ SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(sata0_devslp_a),
SH_PFC_PIN_GROUP(sata0_devslp_b),
SH_PFC_PIN_GROUP(scif0_data),
@@ -5078,6 +5135,18 @@ static const char * const pwm6_groups[] = {
"pwm6_b",
};
+static const char * const qspi0_groups[] = {
+ "qspi0_ctrl",
+ "qspi0_data2",
+ "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+ "qspi1_ctrl",
+ "qspi1_data2",
+ "qspi1_data4",
+};
+
static const char * const sata0_groups[] = {
"sata0_devslp_a",
"sata0_devslp_b",
@@ -5257,7 +5326,7 @@ static const char * const vin5_groups[] = {
};
static const struct {
- struct sh_pfc_function common[51];
+ struct sh_pfc_function common[53];
#ifdef CONFIG_PINCTRL_PFC_R8A77965
struct sh_pfc_function automotive[4];
#endif
@@ -5294,6 +5363,8 @@ static const struct {
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(qspi0),
+ SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(sata0),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
--
2.17.1
[PATCH 1/4] pinctrl: renesas: r8a77990: Add QSPI[01] pins, groups and functions
Add pins, groups and functions for QSPIO[01].
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc-r8a77990.c | 75 +-
1 file changed, 73 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c
b/drivers/pinctrl/renesas/pfc-r8a77990.c
index a51c1e684439..f1ce8572f3ab 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -2810,6 +2810,57 @@ static const unsigned int pwm6_b_mux[] = {
PWM6_B_MARK,
};
+/* - QSPI0 --
*/
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+};
+static const unsigned int qspi0_data2_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+ /* QSPI0_IO2, QSPI0_IO3 */
+ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+};
+static const unsigned int qspi0_data4_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+};
+/* - QSPI1 --
*/
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* QSPI1_SPCLK, QSPI1_SSL */
+ RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+};
+static const unsigned int qspi1_data2_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+ /* QSPI1_IO2, QSPI1_IO3 */
+ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int qspi1_data4_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+
/* - SCIF0 --
*/
static const unsigned int scif0_data_a_pins[] = {
/* RX, TX */
@@ -3762,7 +3813,7 @@ static const unsigned int vin5_clk_b_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[247];
+ struct sh_pfc_pin_group common[253];
#ifdef CONFIG_PINCTRL_PFC_R8A77990
struct sh_pfc_pin_group automotive[21];
#endif
@@ -3910,6 +3961,12 @@ static const struct {
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ SH_PFC_PIN_GROUP(qspi0_data2),
+ SH_PFC_PIN_GROUP(qspi0_data4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ SH_PFC_PIN_GROUP(qspi1_data2),
+ SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(scif0_data_a),
SH_PFC_PIN_GROUP(scif0_clk_a),
SH_PFC_PIN_GROUP(scif0_ctrl_a),
@@ -4313,6 +4370,18 @@ static const char * const pwm6_groups[] = {
"pwm6_b",
};
+static const char * const qspi0_groups[] = {
+ "qspi0_ctrl",
+ "qspi0_data2",
+ "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+ "qspi1_ctrl",
+ "qspi1_data2",
+ "qspi1_data4",
+};
+
static const char * const scif0_groups[] = {
"scif0_data_a",
"scif0_clk_a",
@@ -4467,7 +4536,7 @@ static const char * const vin5_groups[] = {
};
static const struct {
- struct sh_pfc_function common[47];
+ struct sh_pfc_function common[49];
#ifdef CONFIG_PINCTRL_PFC_R8A77990
struct sh_pfc_function automotive[4];
#endif
@@ -4504,6 +4573,8 @@ static const struct {
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(qspi0),
+ SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
--
2.17.1
[PATCH 0/4] Renesas add QSPI{0,1} pins to r8a77{96,951,965,990} SoC
Hi All,
This patch series adds QSPI{0,1} pins to r8a77{96,951,965,990} SoC.
Patches are based on top of [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/
renesas-drivers.git/log/?h=renesas-pinctrl-for-v5.11
Cheers,
Prabhakar
Lad Prabhakar (4):
pinctrl: renesas: r8a77990: Add QSPI[01] pins, groups and functions
pinctrl: renesas: r8a77951: Add QSPI[01] pins, groups and functions
pinctrl: renesas: r8a7796: Add QSPI[01] pins, groups and functions
pinctrl: renesas: r8a77965: Add QSPI[01] pins, groups and functions
drivers/pinctrl/renesas/pfc-r8a77951.c | 75 +-
drivers/pinctrl/renesas/pfc-r8a7796.c | 75 +-
drivers/pinctrl/renesas/pfc-r8a77965.c | 75 +-
drivers/pinctrl/renesas/pfc-r8a77990.c | 75 +-
4 files changed, 292 insertions(+), 8 deletions(-)
--
2.17.1
[PATCH 2/4] pinctrl: renesas: r8a77951: Add QSPI[01] pins, groups and functions
Add pins, groups and functions for QSPIO[01].
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/pinctrl/renesas/pfc-r8a77951.c | 75 +-
1 file changed, 73 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c
b/drivers/pinctrl/renesas/pfc-r8a77951.c
index 72252fdcbc21..cf14420794c7 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77951.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
@@ -3252,6 +3252,57 @@ static const unsigned int pwm6_b_mux[] = {
PWM6_B_MARK,
};
+/* - QSPI0 --
*/
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* QSPI0_SPCLK, QSPI0_SSL */
+ PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
+};
+static const unsigned int qspi0_data2_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
+ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
+ /* QSPI0_IO2, QSPI0_IO3 */
+ PIN_QSPI0_IO2, PIN_QSPI0_IO3,
+};
+static const unsigned int qspi0_data4_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+};
+/* - QSPI1 --
*/
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* QSPI1_SPCLK, QSPI1_SSL */
+ PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data2_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
+};
+static const unsigned int qspi1_data2_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+};
+static const unsigned int qspi1_data4_pins[] = {
+ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
+ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
+ /* QSPI1_IO2, QSPI1_IO3 */
+ PIN_QSPI1_IO2, PIN_QSPI1_IO3,
+};
+static const unsigned int qspi1_data4_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK,
+};
+
/* - SATA
*/
static const unsigned int sata0_devslp_a_pins[] = {
/* DEVSLP */
@@ -4160,7 +4211,7 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[320];
+ struct sh_pfc_pin_group common[326];
#ifdef CONFIG_PINCTRL_PFC_R8A77951
struct sh_pfc_pin_group automotive[30];
#endif
@@ -4365,6 +4416,12 @@ static const struct {
SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(pwm6_b),
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ SH_PFC_PIN_GROUP(qspi0_data2),
+ SH_PFC_PIN_GROUP(qspi0_data4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ SH_PFC_PIN_GROUP(qspi1_data2),
+ SH_PFC_PIN_GROUP(qspi1_data4),
SH_PFC_PIN_GROUP(sata0_devslp_a),
SH_PFC_PIN_GROUP(sata0_devslp_b),
SH_PFC_PIN_GROUP(scif0_data),
@@ -4859,6 +4916,18 @@ static const char * const pwm6_groups[] = {
"pwm6_b",
};
+static const char * const qspi0_groups[] = {
+ "qspi0_ctrl",
+ "qspi0_data2",
+ "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+ "qspi1_ctrl",
+ "qspi1_data2",
+ "qspi1_data4",
+};
+
static const char * const sata0_groups[] = {
"sata0_devslp_a",
"sata0_devslp_b",
@@ -5047,7 +5116,7 @@ static const char * const vin5_groups[] = {
};
static const struct {
- struct sh_pfc_function common[53];
+ struct sh_pfc_function common[55];
#ifdef CONFIG_PINCTRL_PFC_R8A77951
struct sh_pfc_function automotive[4];
#endif
@@ -5084,6 +5153,8 @@ static const struct {
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(qspi0),
+ SH_PFC_FUNCTION(qspi1),
SH_PFC_FUNCTION(sata0),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
--
2.17.1
[PATCH v4] clk: renesas: r8a774c0: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
driver.
Add new clk type CLK_TYPE_GEN3_E3_RPCSRC to register rpcsrc as a fixed
clock on R-Car Gen3 E3 (and also RZ/G2E which is identical to E3 SoC),
parent and the divider is set based on the register value CPG_RPCCKCR[4:3]
which has been set prior to booting the kernel.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
v3->v4
* Dropped cross verification of clock source
* Changed DEF_FIXED_RPCSRC_E3 macro so that SoC specific div can be passed
which would make addition of D3 SoC easier
* Renamed CLK_TYPE_GEN3E3_RPCSRC to CLK_TYPE_GEN3_E3_RPCSRC
* Updated the commit message
v2->v3
* Implemented as a fixed clock
v1->v2
* Fixed divider table depending on the clk source
* Introduced CLK_TYPE_GEN3E3_RPCSRC for E3/G2E.
v1: https://lkml.org/lkml/2020/10/16/474
---
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 9
drivers/clk/renesas/rcar-gen3-cpg.c | 28 +
drivers/clk/renesas/rcar-gen3-cpg.h | 5 +
3 files changed, 42 insertions(+)
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 9fc9fa9e531a..ed3a2cf0e0bb 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -44,6 +44,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
CLK_OCO,
@@ -74,6 +75,13 @@ static const struct cpg_core_clk r8a774c0_core_clks[]
__initconst = {
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc",CLK_SDSRC, CLK_PLL1, 2, 1),
+ DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
+CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+R8A774C0_CLK_RPC),
+
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO,8 * 1000 * 1000),
@@ -199,6 +207,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[]
__initconst = {
DEF_MOD("can-fd",914, R8A774C0_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4),
+ DEF_MOD("rpc-if",917, R8A774C0_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c
b/drivers/clk/renesas/rcar-gen3-cpg.c
index 488f8b3980c5..20de135e28ed 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -696,6 +696,34 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct
device *dev,
cpg_rpcsrc_div_table,
&cpg_lock);
+ case CLK_TYPE_GEN3_E3_RPCSRC:
+ /*
+* Register RPCSRC as fixed factor clock based on the
+* MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
+* which has been set prior to booting the kernel.
+*/
+ value = (readl(base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
+
+ switch (value) {
+ case 0:
+ div = 5;
+ break;
+ case 1:
+ div = 3;
+ break;
+ case 2:
+ parent = clks[core->parent >> 16];
+ if (IS_ERR(parent))
+ return ERR_CAST(parent);
+ div = core->div;
+ break;
+ case 3:
+ default:
+ div = 2;
+ break;
+ }
+ break;
+
case CLK_TYPE_GEN3_RPC:
return cpg_rpc_clk_register(core->name, base,
__clk_get_name(parent), notifiers);
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h
b/drivers/clk/renesas/rcar-gen3-cpg.h
index c4ac80cac6a0..3d949c4a3244 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -24,6 +24,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
CLK_TYPE_GEN3_RPCSRC,
+ CLK_TYPE_GEN
Re: [PATCH v3] clk: renesas: r8a774c0: Add RPC clocks
Hi Geert,
Thank you for the review.
On Mon, Nov 16, 2020 at 8:34 AM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Tue, Nov 10, 2020 at 1:56 PM Lad Prabhakar
> wrote:
> > Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
> > as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
> > driver.
> >
> > Add new clk type CLK_TYPE_GEN3E3_RPCSRC to register rpcsrc as a fixed
> > clock on R-Car Gen3 E3 (and also RZ/G2E which is identical to E3 SoC),
> > parent and the divider is set based on the register value CPG_RPCCKCR[4:3]
> > (parent is cross verified against MD[4:1] pins) which has been set prior
> > to booting the kernel.
> >
> > MD[4] MD[3] MD[2] MD[1]
> > 0 0 01 -> RPCSRC CLK source is PLL1
> > 0 0 11 -> RPCSRC CLK source is PLL1
> > 0 1 00 -> RPCSRC CLK source is PLL1
> > 1 0 11 -> RPCSRC CLK source is PLL1
> > x x xx -> For any other values RPCSRC CLK source is PLL0
> >
> > Signed-off-by: Lad Prabhakar
> > Reviewed-by: Biju Das
>
> Thanks for your patch!
>
> > ---
> > v2->v3
> > * Implemented as a fixed clock
>
> Sounds fine to me. If we ever need to configure this clock from Linux,
> the driver can be changed.
>
> > --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> > @@ -427,6 +427,19 @@ static struct clk * __init cpg_sd_clk_register(const
> > char *name,
> > return clk;
> > }
> >
> > +static bool __init cpg_rpcsrc_e3_parent_is_pll0(u32 mode)
> > +{
> > + unsigned int e3_rpcsrc = (mode & GENMASK(4, 1)) >> 1;
> > + unsigned int pll1[] = { 0x1, 0x3, 0x4, 0xb, };
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(pll1); i++)
> > + if (e3_rpcsrc == pll1[i])
> > + return false;
>
> Did you know gcc (version 9.3.0) generates smaller code for:
>
> switch (e3_rpcsrc) {
> case 0x1:
> case 0x3:
> case 0x4:
> case 0xb:
> return false;
>
> default:
> return true;
> }
>
> ?
>
That's insightful thank you for the pointer.
> > @@ -696,6 +709,42 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct
> > device *dev,
> > cpg_rpcsrc_div_table,
> > &cpg_lock);
> >
> > + case CLK_TYPE_GEN3E3_RPCSRC:
> > + /*
> > +* Register RPCSRC as fixed factor clock based on the
> > +* MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
> > +* which has been set prior to booting the kernel.
> > +*/
> > +
> > + value = (readl(base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
> > + if (cpg_rpcsrc_e3_parent_is_pll0(cpg_mode)) {
> > + if (value != 2)
> > + return ERR_PTR(-EINVAL);
> > + } else {
> > + if (value == 2)
> > + return ERR_PTR(-EINVAL);
> > + }
>
> IMHO this cross-verification is not needed, and harmful: it prevents the
> boot loader from changing the configuration, which I think is a valid
> use case.
>
Agreed will drop this check (and also cpg_rpcsrc_e3_parent_is_pll0())
> > +
> > + switch (value) {
> > + case 0:
> > + div = 5;
> > + break;
> > + case 1:
> > + div = 3;
> > + break;
> > + case 2:
> > + parent = clks[core->parent >> 16];
> > + if (IS_ERR(parent))
> > + return ERR_CAST(parent);
> > + div = 8;
>
> R-Car D3 is very similar, but uses div = 5 instead of 8.
> Perhaps this value can be retrieved from cpg_core_clk.div?
> Of course, we can do that later, when D3 support is added.
>
Agreed, should the below be OK ?
#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1, _div)
Cheers,
Prabhakar
> > + break;
> > + case 3:
> > + default:
> > + div = 2;
> > + break;
> > + }
> > + break;
> > +
> > case CLK_TYPE_GEN3_RPC:
> > return cpg_rpc_clk_register(core->name, base,
> > __clk_get_name(parent),
> > notifiers);
>
> The rest looks good to me.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
Re: [PATCH] mtd: spi-nor: winbond: Add support for w25m512jw
On Tue, Nov 10, 2020 at 12:58 PM Vignesh Raghavendra wrote: > > > > On 10/16/20 5:25 PM, Lad Prabhakar wrote: > > This chip is (nearly) identical to the Winbond w25m512jv which is > > already supported by Linux. Compared to the w25m512jv, the 'jw' > > has a different JEDEC ID. > > > > Signed-off-by: Lad Prabhakar > > Reviewed-by: Biju Das > > I believe this was tested on a real HW? Including Quad mode? > Yes it's tested on Renesas RZ/G2M platform (attached is the log). Cheers, Prabhakar NOTICE: BL2: RZ/G Initial Program Loader(CA57) Rev.2.0.6 NOTICE: BL2: PRR is RZG G2M Ver.1.3 NOTICE: BL2: Board is HiHope RZ/G2M Rev.4.0 NOTICE: BL2: Boot device is QSPI Flash(40MHz) NOTICE: BL2: LCM state is unknown NOTICE: BL2: DDR3200(rev.0.37) NOTICE: BL2: [COLD_BOOT] NOTICE: BL2: DRAM Split is 2ch NOTICE: BL2: QoS is default setting(rev.0.19) NOTICE: BL2: DRAM refresh interval 1.95 usec NOTICE: BL2: Periodic Write DQ Training NOTICE: BL2: CH0: 4 - 47fff, 2 GiB NOTICE: BL2: CH2: 6 - 67fff, 2 GiB NOTICE: BL2: Lossy Decomp areas NOTICE: Entry 0: DCMPAREACRAx:0x8540 DCMPAREACRBx:0x570 NOTICE: Entry 1: DCMPAREACRAx:0x4000 DCMPAREACRBx:0x0 NOTICE: Entry 2: DCMPAREACRAx:0x2000 DCMPAREACRBx:0x0 NOTICE: BL2: FDT at 0xe6323788 NOTICE: BL2: v2.3():v2.3-dirty NOTICE: BL2: Built : 09:45:09, Oct 20 2020 NOTICE: BL2: Normal boot NOTICE: BL2: dst=0xe6323300 src=0x818 len=512(0x200) NOTICE: BL2: dst=0x43f0 src=0x8180400 len=6144(0x1800) NOTICE: rcar_file_len: len: 0x0003e000 NOTICE: BL2: dst=0x4400 src=0x81c len=253952(0x3e000) NOTICE: rcar_file_len: len: 0x0010 NOTICE: BL2: dst=0x4410 src=0x820 len=1048576(0x10) NOTICE: rcar_file_len: len: 0x0010 NOTICE: BL2: dst=0x5000 src=0x830 len=1048576(0x10) NOTICE: BL2: Booting BL31 U-Boot 2020.10-rc5-00053-g499f91013a (Oct 19 2020 - 20:03:46 +0100) CPU: Renesas Electronics R8A774A1 rev 1.3 Model: HopeRun HiHope RZ/G2M with sub board DRAM: 5.8 GiB MMC: mmc@ee10: 0, mmc@ee16: 1 Loading Environment from MMC... OK In:serial@e6e88000 Out: serial@e6e88000 Err: serial@e6e88000 Net: eth0: ethernet@e680 Hit any key to stop autoboot: 0 ethernet@e680 Waiting for PHY auto negotiation to complete.. done BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 DHCP client bound to address 192.168.10.131 (1282 ms) Using ethernet@e680 device TFTP from server 192.168.10.1; our IP address is 192.168.10.131 Filename 'g2m/Image'. Load address: 0x4808 Loading: # # # # # # # # # # # # # # # # # # # # # # # 2.1 MiB/s done Bytes transferred = 21352960 (145d200 hex) Using ethernet@e680 device TFTP from server 192.168.10.1; our IP address is 192.168.10.131 Filename 'g2m/r8a774a1-hihope-rzg2m-ex.dtb'. Load address: 0x4800 Loading: 1.8 MiB/s done Bytes transferred = 57826 (e1e2 hex) Moving Image from 0x4808 to 0x4820, end=4a12 ## Flattened Device Tree blob at 4800 Booting using the fdt blob at 0x4800 Using Device Tree in place at 4800, end 480111e1 Starting kernel ... [0.00] Booting Linux on physical CPU 0x00 [0x411fd073] [0.00] Linux version 5.9.0-rc7+ (pr
[PATCH v3] clk: renesas: r8a774c0: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
driver.
Add new clk type CLK_TYPE_GEN3E3_RPCSRC to register rpcsrc as a fixed
clock on R-Car Gen3 E3 (and also RZ/G2E which is identical to E3 SoC),
parent and the divider is set based on the register value CPG_RPCCKCR[4:3]
(parent is cross verified against MD[4:1] pins) which has been set prior
to booting the kernel.
MD[4] MD[3] MD[2] MD[1]
0 0 01 -> RPCSRC CLK source is PLL1
0 0 11 -> RPCSRC CLK source is PLL1
0 1 00 -> RPCSRC CLK source is PLL1
1 0 11 -> RPCSRC CLK source is PLL1
x x xx -> For any other values RPCSRC CLK source is PLL0
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
v2->v3
* Implemented as a fixed clock
v1->v2
* Fixed divider table depending on the clk source
* Introduced CLK_TYPE_GEN3E3_RPCSRC for E3/G2E.
v1: https://lkml.org/lkml/2020/10/16/474
---
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 9 +
drivers/clk/renesas/rcar-gen3-cpg.c | 49 +
drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++
3 files changed, 62 insertions(+)
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 9fc9fa9e531a..ed3a2cf0e0bb 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -44,6 +44,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
CLK_OCO,
@@ -74,6 +75,13 @@ static const struct cpg_core_clk r8a774c0_core_clks[]
__initconst = {
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc",CLK_SDSRC, CLK_PLL1, 2, 1),
+ DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
+CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+R8A774C0_CLK_RPC),
+
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO,8 * 1000 * 1000),
@@ -199,6 +207,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[]
__initconst = {
DEF_MOD("can-fd",914, R8A774C0_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4),
+ DEF_MOD("rpc-if",917, R8A774C0_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c
b/drivers/clk/renesas/rcar-gen3-cpg.c
index 488f8b3980c5..00c3d5570274 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -427,6 +427,19 @@ static struct clk * __init cpg_sd_clk_register(const char
*name,
return clk;
}
+static bool __init cpg_rpcsrc_e3_parent_is_pll0(u32 mode)
+{
+ unsigned int e3_rpcsrc = (mode & GENMASK(4, 1)) >> 1;
+ unsigned int pll1[] = { 0x1, 0x3, 0x4, 0xb, };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pll1); i++)
+ if (e3_rpcsrc == pll1[i])
+ return false;
+
+ return true;
+}
+
struct rpc_clock {
struct clk_divider div;
struct clk_gate gate;
@@ -696,6 +709,42 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct
device *dev,
cpg_rpcsrc_div_table,
&cpg_lock);
+ case CLK_TYPE_GEN3E3_RPCSRC:
+ /*
+* Register RPCSRC as fixed factor clock based on the
+* MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
+* which has been set prior to booting the kernel.
+*/
+
+ value = (readl(base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
+ if (cpg_rpcsrc_e3_parent_is_pll0(cpg_mode)) {
+ if (value != 2)
+ return ERR_PTR(-EINVAL);
+ } else {
+ if (value == 2)
+ return ERR_PTR(-EINVAL);
+ }
+
+ switch (value) {
+ case 0:
+ div = 5;
+ break;
+ case 1:
+ div = 3;
+ break;
+ case 2:
+ parent = clks[core->parent >> 16];
+
[PATCH] arm64: dts: renesas: hihope-rev4: Add a comment explaining switch SW2404 required for audio_clk_b
Switch SW2404 should be at poistion 1 so that clock output from CS2000 is connected to AUDIO_CLKB_A. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson --- arch/arm64/boot/dts/renesas/hihope-rev4.dtsi | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi index 3046c07a288b..929f4a1d3f90 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi @@ -91,7 +91,11 @@ #clock-cells = <1>; clock-frequency = <12288000 11289600>; - /* update to */ + /* +* Update to +* Switch SW2404 should be at position 1 so that clock from +* CS2000 is connected to AUDIO_CLKB_A +*/ clocks = <&cpg CPG_MOD 1005>, <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, -- 2.17.1
Re: [RESEND PATCH] dt-bindings: ata: renesas,rcar-sata: Add r8a774e1 support
Hi Jens, On Mon, Sep 21, 2020 at 8:22 AM Lad Prabhakar wrote: > > Document SATA support for the RZ/G2H, no driver change required. > > Signed-off-by: Lad Prabhakar > Reviewed-by: Marian-Cristian Rotariu > > Acked-by: Rob Herring > Reviewed-by: Geert Uytterhoeven > --- > Hi All, > > This patch is part of series [1] (orignal patch [2]) where rest of the > patches have been picked up by the respective maintainers so just > resending this patch. > > I have included the Acks' from the maintainers. > > [1] https://patchwork.kernel.org/project/linux-renesas-soc/ > list/?series=319563 > [2] https://patchwork.kernel.org/patch/11668061/ > > Cheers, > Prabhakar > --- > Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml | 1 + > 1 file changed, 1 insertion(+) > This patch is not in mainline yet (first version was posted in July). Let me know if you want me to re-send it. Cheers, Prabhakar
[PATCH] arm64: dts: renesas: r8a774e1: Add missing audio_clk_b
Add audio_clk_b configured as 0 Hz, this will be overridden by the
boards providing the audio clock.
Fixes: 8183a7938cfec ("arm64: dts: renesas: r8a774e1: Add audio support")
Reported-by: Nobuhiro Iwamatsu
Signed-off-by: Lad Prabhakar
---
Hi Geert,
I have rebased this patch on renesas-arm-dt-for-v5.10 branch.
Cheers,
Prabhakar
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 9cbf963aa068..c29643442e91 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -28,6 +28,12 @@
clock-frequency = <0>;
};
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
--
2.17.1
Re: [PATCH v2] clk: renesas: r8a774c0: Add RPC clocks
Hi Geert,
Thank you for the review.
On Thu, Oct 29, 2020 at 2:29 PM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Thu, Oct 29, 2020 at 11:55 AM Lad Prabhakar
> wrote:
> > Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
> > as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
> > driver.
>
> Thanks for your patch!
>
> > Add new clk type CLK_TYPE_GEN3E3_RPCSRC to handle registering rpcsrc
> > clock as the source for RPCSRC can be either PLL0/PLL1 and this depends
> > on MD[1:4] pins where as compared to other R-Car Gen3 SoC's the RPCSRC
> > clock source is always PLL1.
> >
> > MD[4] MD[3] MD[2] MD[1]
> > 0 0 01 -> RPCSRC CLK source is PLL1
> > 0 0 11 -> RPCSRC CLK source is PLL1
> > 0 1 00 -> RPCSRC CLK source is PLL1
> > 1 0 11 -> RPCSRC CLK source is PLL1
> > x x xx -> For any other values RPCSRC CLK source is PLL0
>
> AFAIU, the _initial values_ of the RPCCKCR bits depend on the MD pins.
> They can still be changed at run-time, and might have been changed by
> the bootloader before transferring control to Linux.
>
> > R-Car Gen3 manual Rev.2.20 has in-correct information related to
> > determining the clock source for RPCSRC.
>
> Which part of the information is not correct?
> Where can I find corrected information?
> Is my understanding above incorrect, too?
>
R-Car Gen3 HW manual mentions the below statement (page 529, Rev.2.20 manual):
[R-Car E3]
When (MD4, MD3, MD2, MD1) = (0, 0, 0, 1) or (0, 1, 0, 0): DIV[2:0] =
011, DIV[4:3] = 00 (300 MHz PLL0)
Confirming with internal team this should be below:
When (MD4, MD3, MD2, MD1) = (0, 0, 0, 1) or (0, 1, 0, 0): DIV[2:0] =
011, DIV[4:3] = 00 (80 MHz PLL1)
This should be fixed in the next version of the document, and when
available I'll ask Chris P to send it across.
> > --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
>
> > @@ -73,6 +74,12 @@ static const struct cpg_core_clk r8a774c0_core_clks[]
> > __initconst = {
> > DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
> > DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
> > DEF_FIXED(".sdsrc",CLK_SDSRC, CLK_PLL1, 2, 1),
> > + DEF_BASE(".rpcsrc",CLK_RPCSRC, CLK_TYPE_GEN3E3_RPCSRC,
> > (CLK_PLL1 << 16) | CLK_PLL0),
>
> You may want to add a new DEF_* helper macro for this.
>
> > --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> > @@ -441,6 +441,14 @@ static const struct clk_div_table
> > cpg_rpcsrc_div_table[] = {
> > { 2, 5 }, { 3, 6 }, { 0, 0 },
> > };
> >
> > +static const struct clk_div_table cpg_rpcsrc_e3_pll0_div_table[] = {
> > + { 2, 8 }, { 0, 0 },
> > +};
> > +
> > +static const struct clk_div_table cpg_rpcsrc_e3_pll1_div_table[] = {
> > + { 0, 5 }, { 1, 3 }, { 3, 2 }, { 0, 0 },
> > +};
> > +
> > static const struct clk_div_table cpg_rpc_div_table[] = {
> > { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
> > };
> > @@ -515,6 +523,18 @@ static struct clk * __init
> > cpg_rpcd2_clk_register(const char *name,
> > return clk;
> > }
> >
> > +static int __init cpg_rpcsrc_e3_get_parent(u32 mode)
> > +{
> > + unsigned int e3_rpcsrc = (mode & GENMASK(4, 1)) >> 1;
> > + unsigned int pll1[] = { 0x1, 0x3, 0x4, 0xb, };
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(pll1); i++)
> > + if (e3_rpcsrc == pll1[i])
> > + return 1;
> > +
> > + return 0;
> > +}
> >
> > static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
> > static unsigned int cpg_clk_extalr __initdata;
> > @@ -552,6 +572,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct
> > device *dev,
> > const struct clk *parent;
> > unsigned int mult = 1;
> > unsigned int div = 1;
> > + int e3_rpcsrc_parent;
> > u32 value;
> >
> > parent = clks[core->parent & 0x]; /* some types use high bits
> > */
> > @@ -696,6 +717,22 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct
> > device *dev,
> > cpg_rpcsrc_div_table,
> >
[PATCH v2] clk: renesas: r8a774c0: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
driver.
Add new clk type CLK_TYPE_GEN3E3_RPCSRC to handle registering rpcsrc
clock as the source for RPCSRC can be either PLL0/PLL1 and this depends
on MD[1:4] pins where as compared to other R-Car Gen3 SoC's the RPCSRC
clock source is always PLL1.
MD[4] MD[3] MD[2] MD[1]
0 0 01 -> RPCSRC CLK source is PLL1
0 0 11 -> RPCSRC CLK source is PLL1
0 1 00 -> RPCSRC CLK source is PLL1
1 0 11 -> RPCSRC CLK source is PLL1
x x xx -> For any other values RPCSRC CLK source is PLL0
R-Car Gen3 manual Rev.2.20 has in-correct information related to
determining the clock source for RPCSRC.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
Hi All,
This patch is part of series of [1], since rest of the patches have been
acked I am just re-sending this single patch.
v1->v2
* Fixed divider table depending on the clk source
* Introduced CLK_TYPE_GEN3E3_RPCSRC for E3/G2E.
CLK output on g2e:
.pll1 360 16 0 0
5
.rpcsrc 010 32000 0 0
5
rpc 0108000 0 0
5
rpcd2 0104000 0 0
5
rpc-if 0104000 0 0
5
[1] https://lkml.org/lkml/2020/10/16/470
Cheers,
Prabhakar
---
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 8 ++
drivers/clk/renesas/rcar-gen3-cpg.c | 37 +
drivers/clk/renesas/rcar-gen3-cpg.h | 1 +
3 files changed, 46 insertions(+)
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 9fc9fa9e531a..cccb20de4d4b 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -44,6 +44,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
CLK_OCO,
@@ -73,6 +74,12 @@ static const struct cpg_core_clk r8a774c0_core_clks[]
__initconst = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc",CLK_SDSRC, CLK_PLL1, 2, 1),
+ DEF_BASE(".rpcsrc",CLK_RPCSRC, CLK_TYPE_GEN3E3_RPCSRC, (CLK_PLL1 <<
16) | CLK_PLL0),
+
+ DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
+CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+R8A774C0_CLK_RPC),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
@@ -199,6 +206,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[]
__initconst = {
DEF_MOD("can-fd",914, R8A774C0_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4),
+ DEF_MOD("rpc-if",917, R8A774C0_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c
b/drivers/clk/renesas/rcar-gen3-cpg.c
index 488f8b3980c5..90a30416c9cf 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -441,6 +441,14 @@ static const struct clk_div_table cpg_rpcsrc_div_table[] =
{
{ 2, 5 }, { 3, 6 }, { 0, 0 },
};
+static const struct clk_div_table cpg_rpcsrc_e3_pll0_div_table[] = {
+ { 2, 8 }, { 0, 0 },
+};
+
+static const struct clk_div_table cpg_rpcsrc_e3_pll1_div_table[] = {
+ { 0, 5 }, { 1, 3 }, { 3, 2 }, { 0, 0 },
+};
+
static const struct clk_div_table cpg_rpc_div_table[] = {
{ 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
};
@@ -515,6 +523,18 @@ static struct clk * __init cpg_rpcd2_clk_register(const
char *name,
return clk;
}
+static int __init cpg_rpcsrc_e3_get_parent(u32 mode)
+{
+ unsigned int e3_rpcsrc = (mode & GENMASK(4, 1)) >> 1;
+ unsigned int pll1[] = { 0x1, 0x3, 0x4, 0xb, };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pll1); i++)
+ if (e3_rpcsrc == pll1[i])
+ return 1;
+
+ return 0;
+}
static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
static unsigned int cpg_clk_extalr __initdata;
@@ -552,6 +572,7 @@ struct clk * __init rcar_gen3_cpg_clk_register
Re: [PATCH 0/2] RZ/G2x add optee node
Hi Geert,
On Fri, Oct 23, 2020 at 8:55 AM Lad Prabhakar
wrote:
>
> Hi All,
>
> This patch series adds optee node to HiHope RZ/G2{HMN} and EK874 boards.
>
> This patch series applies on top of [1].
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/
> renesas-devel.git/log/?h=renesas-arm-dt-for-v5.11
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (2):
> arm64: dts: renesas: hihope-common: Add optee node
> arm64: dts: renesas: r8a774c0-ek874: Add optee node
>
As agreed on the irc (optee nodes should be coming from firmware
stack) let's drop these patches.
Cheers,
Prabhakar
> arch/arm64/boot/dts/renesas/hihope-common.dtsi | 7 +++
> arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts | 7 +++
> 2 files changed, 14 insertions(+)
>
> --
> 2.17.1
>
[PATCH] PCI: pcie-rcar-host: Drop unused members from struct rcar_pcie_host
Drop unused members dev and base from struct rcar_pcie_host.
Signed-off-by: Lad Prabhakar
---
drivers/pci/controller/pcie-rcar-host.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-rcar-host.c
b/drivers/pci/controller/pcie-rcar-host.c
index cdc0963f154e..4d1c4b24e537 100644
--- a/drivers/pci/controller/pcie-rcar-host.c
+++ b/drivers/pci/controller/pcie-rcar-host.c
@@ -50,9 +50,7 @@ static inline struct rcar_msi *to_rcar_msi(struct
msi_controller *chip)
/* Structure representing the PCIe interface */
struct rcar_pcie_host {
struct rcar_pciepcie;
- struct device *dev;
struct phy *phy;
- void __iomem*base;
struct clk *bus_clk;
struct rcar_msi msi;
int (*phy_init_fn)(struct rcar_pcie_host *host);
--
2.17.1
Re: [PATCH 4/4] clk: renesas: r8a774c0: Add RPC clocks
Hi Geert,
Thank you for the review.
On Thu, Oct 22, 2020 at 3:09 PM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Fri, Oct 16, 2020 at 2:17 PM Lad Prabhakar
> wrote:
> > Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
> > as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
> > driver.
> >
> > Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
> >
> > Signed-off-by: Lad Prabhakar
> > Reviewed-by: Biju Das
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> > @@ -73,6 +74,12 @@ static const struct cpg_core_clk r8a774c0_core_clks[]
> > __initconst = {
> > DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
> > DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
> > DEF_FIXED(".sdsrc",CLK_SDSRC, CLK_PLL1, 2, 1),
> > + DEF_BASE(".rpcsrc",CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
> > +
> > + DEF_BASE("rpc",R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
> > +CLK_RPCSRC),
> > + DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
> > +R8A774C0_CLK_RPC),
> >
> > DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR,
> > 32),
> >
>
> > @@ -275,6 +283,10 @@ static int __init r8a774c0_cpg_mssr_init(struct device
> > *dev)
> > return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
> > }
> >
> > +static const struct clk_div_table cpg_rpcsrc_div_table[] = {
> > + { 0, 5 }, { 1, 3 }, { 2, 8 }, {3, 2}, {0, 0},
> > +};
>
> The above models RPCSRC as a clock generated by dividing PLL1 by either
> 5, 3, 8, or 2. This does not match the hardware user's manual, which
> states that RPCSRC is either PLL1 divided by 5 or 3, or PLL0 divided by
> 8 or 2.
>
Oops I completely missed that.
But as per the manual (R-Car manual Rev.2.20) which I am referring to
5, 3 and 2 are sourced from PLL1 and 5/8 (ie D3/E3) are sourced from
PLL0.
> I think you need a new clock type (CLK_TYPE_GEN3E_RPCSRC, as it applies
> to RZ/G2E, and R-Car E3?), which registers a composite clock consisting
> of a mux and divider. This is a bit similar to the RPC/RPCD2 clocks,
> which are composite clocks consisting of a divider and a gate.
>
atm rcar_gen3_cpg_clk_register() only supports single parent, so if I
am getting it right you mean I need to add two separate entries for
RPSRC one with PLL0 and one with PLL1 ?
> Note that R-Car D3 is similar, except that PLL0 is divided by 5 or 2, which
> means yet another clock type (and div_table).
>
I'm a bit confused here for D3 PLL0 is divided by 5 (n=5) ?
Cheers,
Prabhakar
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
[PATCH 2/2] arm64: dts: renesas: r8a774c0-ek874: Add optee node
Add optee device tree node to EK874 board.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts
b/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts
index e7b6619ab224..ac48b4ee237f 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts
@@ -11,4 +11,11 @@
/ {
model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)";
compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
};
--
2.17.1
[PATCH 1/2] arm64: dts: renesas: hihope-common: Add optee node
Add optee device tree node to HiHope RZ/G2{HMN} boards.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
arch/arm64/boot/dts/renesas/hihope-common.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi
b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
index 78096473d41d..32202e5263f6 100644
--- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi
@@ -110,6 +110,13 @@
#clock-cells = <0>;
clock-frequency = <2500>;
};
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
};
&audio_clk_a {
--
2.17.1
[PATCH 0/2] RZ/G2x add optee node
Hi All,
This patch series adds optee node to HiHope RZ/G2{HMN} and EK874 boards.
This patch series applies on top of [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/
renesas-devel.git/log/?h=renesas-arm-dt-for-v5.11
Cheers,
Prabhakar
Lad Prabhakar (2):
arm64: dts: renesas: hihope-common: Add optee node
arm64: dts: renesas: r8a774c0-ek874: Add optee node
arch/arm64/boot/dts/renesas/hihope-common.dtsi | 7 +++
arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts | 7 +++
2 files changed, 14 insertions(+)
--
2.17.1
Re: [PATCH] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Enable VIN instances
Hi Geert,
Thank you for the review.
On Thu, Oct 22, 2020 at 12:43 PM Geert Uytterhoeven
wrote:
>
> Hi Prabhakar,
>
> On Wed, Oct 14, 2020 at 4:56 PM Lad Prabhakar
> wrote:
> > Enable VIN instances along with OV5640 as endpoints on the adapter board.
> >
> > Signed-off-by: Lad Prabhakar
> > Reviewed-by: Biju Das
>
> Thanks for your patch!
>
> Reviewed-by: Geert Uytterhoeven
>
> I believe the "data-shift" patches for rcar-vin haven't been accepted yet,
> and this patch depends on it, logically?
>
They have been accepted and is currently in linux-next [1] (should be
part of v5.10)
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=e88349437654f9d1b3c144049b9990026f911e56
Cheers,
Prabhakar
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
[PATCH v2 4/4] arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2N
Add support for AISTARVISION MIPI Adapter V2.1 board connected to HiHope
RZ/G2N board.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
v1->v2 - No change
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
.../r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts| 16
2 files changed, 17 insertions(+)
create mode 100644
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile
b/arch/arm64/boot/dts/renesas/Makefile
index 6581d19a3217..5f163af16180 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_R8A774B1) +=
r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb
+dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts
b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts
new file mode 100644
index ..ce8e3bcc7dc9
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2N board
+ * connected with aistarvision-mipi-v2-adapter board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774b1-hihope-rzg2n-ex.dts"
+#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2N with sub board connected with
aistarvision-mipi-v2-adapter board";
+ compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
+};
--
2.17.1
[PATCH v2 1/4] arm64: dts: renesas: aistarvision-mipi-adapter-2.1: Add parent macro for each sensor
For HiHope RZ/G2H the OV5645 sensor is populated on i2c2 whereas the imx219
sensor is populated on i2c3 so add support for handling such cases by
adding a parent macro for each sensor.
Also update r8a774c0-ek874-mipi-2.1.dts to incorporate the changes.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
v1->v2 - No change
---
.../arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi | 4 +++-
arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts | 3 ++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi
b/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi
index dac6ff49020f..7ce986f0a06f 100644
--- a/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi
+++ b/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi
@@ -61,7 +61,7 @@
};
};
-&MIPI_PARENT_I2C {
+&MIPI_OV5645_PARENT_I2C {
ov5645: ov5645@3c {
compatible = "ovti,ov5645";
reg = <0x3c>;
@@ -77,7 +77,9 @@
};
};
};
+};
+&MIPI_IMX219_PARENT_I2C {
imx219: imx219@10 {
compatible = "sony,imx219";
reg = <0x10>;
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts
b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts
index f0829e905506..e7b4a929bb17 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts
@@ -8,7 +8,8 @@
/dts-v1/;
#include "r8a774c0-ek874.dts"
-#define MIPI_PARENT_I2C i2c3
+#define MIPI_OV5645_PARENT_I2C i2c3
+#define MIPI_IMX219_PARENT_I2C i2c3
#include "aistarvision-mipi-adapter-2.1.dtsi"
/ {
--
2.17.1
[PATCH v2 2/4] arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2H
Add support for AISTARVISION MIPI Adapter V2.1 board connected to HiHope
RZ/G2H board.
Common file hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi is created
which will be used by RZ/G2{HMN}, by default the CSI20 node is tied to
ov5645 camera endpoint and the imx219 camera endpoint is tied to CSI40.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
v1->v2 - No change
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
...rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi | 109 ++
.../r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts | 16 +++
3 files changed, 126 insertions(+)
create mode 100644
arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi
create mode 100644
arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile
b/arch/arm64/boot/dts/renesas/Makefile
index dffefe030a76..f98e9e2e520d 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb
dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb
+dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb
diff --git
a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi
b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi
new file mode 100644
index ..c62ddb9b2ba5
--- /dev/null
+++
b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2[HMN] MIPI common parts
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#define MIPI_OV5645_PARENT_I2C i2c2
+#define MIPI_IMX219_PARENT_I2C i2c3
+#include "aistarvision-mipi-adapter-2.1.dtsi"
+
+&csi20 {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ csi20_in: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&ov5645_ep>;
+ };
+ };
+ };
+};
+
+&csi40 {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ csi40_in: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&imx219_ep>;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&imx219 {
+ port {
+ imx219_ep: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ link-frequencies = /bits/ 64 <45600>;
+ remote-endpoint = <&csi40_in>;
+ };
+ };
+};
+
+&ov5645 {
+ enable-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>;
+
+ port {
+ ov5645_ep: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&csi20_in>;
+ };
+ };
+};
+
+&pfc {
+ i2c3_pins: i2c3 {
+ groups = "i2c3";
+ function = "i2c3";
+ };
+};
+
+&vin0 {
+ status = "okay";
+};
+
+&vin1 {
+ status = "okay";
+};
+
+&vin2 {
+ status = "okay";
+};
+
+&vin3 {
+ status = "okay";
+};
+
+&vin4 {
+ status = "okay";
+};
+
+&vin5 {
+ status = "okay";
+};
+
+&vin6 {
+ status = "okay";
+};
+
+&vin7 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts
b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts
new file mode 100644
index ..46adb6efb5e6
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2H board
+ * connected with aistarvision-mipi-v2-adapter board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774e1-hihope-rzg2h-ex.dts"
+#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2H with sub board connected with
aistarvision-mipi-v2-adapter board";
+ compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
+};
--
2.17.1
[PATCH v2 0/4] HiHope RZ/G2x add MIPI Adapter board support
Hi All,
This patch series adds support for MIPI Adapter V2.1 connected to
HiHope RZ/G2{HMN}.
Patches apply on top of [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/
renesas-devel.git/log/?h=renesas-arm-dt-for-v5.11
Cheers,
Prabhakar
Changes for v2:
* patches {1,2,4}/4 unchanged
* patch 3/4 disabled csi40 and imx219 nodes
Lad Prabhakar (4):
arm64: dts: renesas: aistarvision-mipi-adapter-2.1: Add parent macro
for each sensor
arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to
HiHope RZ/G2H
arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to
HiHope RZ/G2M
arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to
HiHope RZ/G2N
arch/arm64/boot/dts/renesas/Makefile | 3 +
.../aistarvision-mipi-adapter-2.1.dtsi| 4 +-
...rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi | 109 ++
.../r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts | 29 +
.../r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts | 16 +++
.../dts/renesas/r8a774c0-ek874-mipi-2.1.dts | 3 +-
.../r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts | 16 +++
7 files changed, 178 insertions(+), 2 deletions(-)
create mode 100644
arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi
create mode 100644
arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts
create mode 100644
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts
create mode 100644
arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts
--
2.17.1
[PATCH v2 3/4] arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2M
Add support for AISTARVISION MIPI Adapter V2.1 board connected to HiHope
RZ/G2M board.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
v1->v2
* Disabled CSI40 amd imx219 nodes
* Added a comment wrt CSI40 as it supports only 4 lane mode
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
.../r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts | 29 +++
2 files changed, 30 insertions(+)
create mode 100644
arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile
b/arch/arm64/boot/dts/renesas/Makefile
index f98e9e2e520d..6581d19a3217 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_R8A774A1) +=
r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
+dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-mipi-2.1.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts
b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts
new file mode 100644
index ..5c91e0d7e67b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the HiHope RZ/G2M board
+ * connected with aistarvision-mipi-v2-adapter board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774a1-hihope-rzg2m-ex.dts"
+#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi"
+
+/ {
+ model = "HopeRun HiHope RZ/G2M with sub board connected with
aistarvision-mipi-v2-adapter board";
+ compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1";
+};
+
+/*
+ * On RZ/G2M SoC LSI V1.3 CSI40 supports only 4 lane mode.
+ * HiHope RZ/G2M Rev.4.0 board is based on LSI V1.3 so disable csi40 and
+ * imx219 as the imx219 endpoint driver supports only 2 lane mode.
+ */
+&csi40 {
+ status = "disabled";
+};
+
+&imx219 {
+ status = "disabled";
+};
--
2.17.1
[PATCH 1/4] clk: renesas: rcar-gen3: Add support to pass custom RPCSRC div table
RPCSRC div table is SoC specific and is not common for all R-Car Gen3
devices, with the current implementation in rcar-gen3-cpg not all the
SoC's are covered.
To handle such case introduce a new member cpg_rpcsrc_div_table in
priv structure so that we pass SoC specific div table for RPCSRC.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/clk/renesas/rcar-gen3-cpg.c| 2 ++
drivers/clk/renesas/renesas-cpg-mssr.h | 6 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c
b/drivers/clk/renesas/rcar-gen3-cpg.c
index 488f8b3980c5..cdfcd108d1a3 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -693,6 +693,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct
device *dev,
return clk_register_divider_table(NULL, core->name,
__clk_get_name(parent), 0,
base + CPG_RPCCKCR, 3, 2, 0,
+ info->cpg_rpcsrc_div_table ?
+ info->cpg_rpcsrc_div_table :
cpg_rpcsrc_div_table,
&cpg_lock);
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h
b/drivers/clk/renesas/renesas-cpg-mssr.h
index f369b06c903b..3b0a70c59e04 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -8,6 +8,8 @@
#ifndef __CLK_RENESAS_CPG_MSSR_H__
#define __CLK_RENESAS_CPG_MSSR_H__
+#include
+
/*
* Definitions of CPG Core Clocks
*
@@ -116,6 +118,8 @@ enum clk_reg_layout {
*Management, in addition to Module Clocks
* @num_core_pm_clks: Number of entries in core_pm_clks[]
*
+ * @cpg_rpcsrc_div_table: DIV table for RPCSRC
+ *
* @init: Optional callback to perform SoC-specific initialization
* @cpg_clk_register: Optional callback to handle special Core Clock types
*/
@@ -147,6 +151,8 @@ struct cpg_mssr_info {
const unsigned int *core_pm_clks;
unsigned int num_core_pm_clks;
+ const struct clk_div_table *cpg_rpcsrc_div_table;
+
/* Callbacks */
int (*init)(struct device *dev);
struct clk *(*cpg_clk_register)(struct device *dev,
--
2.17.1
[PATCH 3/4] clk: renesas: r8a774b1: Add RPC clocks
From: Biju Das
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2N (R8A774B1) CPG/MSSR
driver.
Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
Signed-off-by: Biju Das
Signed-off-by: Lad Prabhakar
---
drivers/clk/renesas/r8a774b1-cpg-mssr.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index f436691271ec..6f04c40fe237 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -40,6 +40,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@@ -65,6 +66,12 @@ static const struct cpg_core_clk r8a774b1_core_clks[]
__initconst = {
DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
+CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+R8A774B1_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
@@ -196,6 +203,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[]
__initconst = {
DEF_MOD("can-fd",914, R8A774B1_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
+ DEF_MOD("rpc-if",917, R8A774B1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
--
2.17.1
[PATCH 4/4] clk: renesas: r8a774c0: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
driver.
Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 9fc9fa9e531a..1615b31c32ee 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -44,6 +44,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
CLK_OCO,
@@ -73,6 +74,12 @@ static const struct cpg_core_clk r8a774c0_core_clks[]
__initconst = {
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc",CLK_SDSRC, CLK_PLL1, 2, 1),
+ DEF_BASE(".rpcsrc",CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc",R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
+CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+R8A774C0_CLK_RPC),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
@@ -199,6 +206,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[]
__initconst = {
DEF_MOD("can-fd",914, R8A774C0_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4),
+ DEF_MOD("rpc-if",917, R8A774C0_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
@@ -275,6 +283,10 @@ static int __init r8a774c0_cpg_mssr_init(struct device
*dev)
return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
}
+static const struct clk_div_table cpg_rpcsrc_div_table[] = {
+ { 0, 5 }, { 1, 3 }, { 2, 8 }, {3, 2}, {0, 0},
+};
+
const struct cpg_mssr_info r8a774c0_cpg_mssr_info __initconst = {
/* Core Clocks */
.core_clks = r8a774c0_core_clks,
@@ -287,6 +299,8 @@ const struct cpg_mssr_info r8a774c0_cpg_mssr_info
__initconst = {
.num_mod_clks = ARRAY_SIZE(r8a774c0_mod_clks),
.num_hw_mod_clks = 12 * 32,
+ .cpg_rpcsrc_div_table = cpg_rpcsrc_div_table,
+
/* Critical Module Clocks */
.crit_mod_clks = r8a774c0_crit_mod_clks,
.num_crit_mod_clks = ARRAY_SIZE(r8a774c0_crit_mod_clks),
--
2.17.1
[PATCH 2/4] clk: renesas: r8a774a1: Add RPC clocks
From: Biju Das
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2M (R8A774A1) CPG/MSSR
driver.
Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
Signed-off-by: Biju Das
Signed-off-by: Lad Prabhakar
---
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index fd54b9f625da..4a43ebec7d5e 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -41,6 +41,7 @@ enum clk_ids {
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@@ -67,6 +68,12 @@ static const struct cpg_core_clk r8a774a1_core_clks[]
__initconst = {
DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,
+CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+R8A774A1_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
@@ -200,6 +207,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[]
__initconst = {
DEF_MOD("can-fd",914, R8A774A1_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4),
+ DEF_MOD("rpc-if",917, R8A774A1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
--
2.17.1
[PATCH 0/4] Renesas RZ/G2x enable RPC clocks
Hi All, This patch series enables RPC clocks on RZ/G2x SoC's. This series applies on top of [1]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/ renesas-drivers.git/log/?h=renesas-clk-for-v5.11 Cheers, Prabhakar Biju Das (2): clk: renesas: r8a774a1: Add RPC clocks clk: renesas: r8a774b1: Add RPC clocks Lad Prabhakar (2): clk: renesas: rcar-gen3: Add support to pass custom RPCSRC div table clk: renesas: r8a774c0: Add RPC clocks drivers/clk/renesas/r8a774a1-cpg-mssr.c | 8 drivers/clk/renesas/r8a774b1-cpg-mssr.c | 8 drivers/clk/renesas/r8a774c0-cpg-mssr.c | 14 ++ drivers/clk/renesas/rcar-gen3-cpg.c | 2 ++ drivers/clk/renesas/renesas-cpg-mssr.h | 6 ++ 5 files changed, 38 insertions(+) -- 2.17.1
[PATCH] mtd: spi-nor: winbond: Add support for w25m512jw
This chip is (nearly) identical to the Winbond w25m512jv which is
already supported by Linux. Compared to the w25m512jv, the 'jw'
has a different JEDEC ID.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/mtd/spi-nor/winbond.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 6dcde15fb1aa..b5dfc09fef30 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -88,6 +88,8 @@ static const struct flash_info winbond_parts[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
+ { "w25m512jw", INFO(0xef6119, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
};
/**
--
2.17.1
[PATCH] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Enable VIN instances
Enable VIN instances along with OV5640 as endpoints on the adapter board.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
This patch applies on top of [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/
renesas-devel.git/log/?h=renesas-arm-dt-for-v5.11
---
.../boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts| 222 ++
1 file changed, 222 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
index 961c0f2eeefb..98c3fbd89fa6 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
@@ -20,6 +20,30 @@
serial5 = &hscif0;
ethernet1 = ðer;
};
+
+ mclk_cam1: mclk-cam1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ };
+
+ mclk_cam2: mclk-cam2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ };
+
+ mclk_cam3: mclk-cam3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ };
+
+ mclk_cam4: mclk-cam4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ };
};
&avb {
@@ -47,6 +71,19 @@
};
};
+&gpio0 {
+ /* Disable hogging GP0_18 to output LOW */
+ /delete-node/ qspi_en;
+
+ /* Hog GP0_18 to output HIGH to enable VIN2 */
+ vin2_en {
+ gpio-hog;
+ gpios = <18 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "VIN2_EN";
+ };
+};
+
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
@@ -54,6 +91,94 @@
status = "okay";
};
+&i2c0 {
+ ov5640@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&mclk_cam1>;
+ clock-names = "xclk";
+
+ port {
+ ov5640_0: endpoint {
+ bus-width = <8>;
+ data-shift = <2>;
+ bus-type = <6>;
+ pclk-sample = <1>;
+ remote-endpoint = <&vin0ep>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <40>;
+
+ ov5640@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&mclk_cam2>;
+ clock-names = "xclk";
+
+ port {
+ ov5640_1: endpoint {
+ bus-width = <8>;
+ data-shift = <2>;
+ bus-type = <6>;
+ pclk-sample = <1>;
+ remote-endpoint = <&vin1ep>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ ov5640@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&mclk_cam3>;
+ clock-names = "xclk";
+
+ port {
+ ov5640_2: endpoint {
+ bus-width = <8>;
+ data-shift = <2>;
+ bus-type = <6>;
+ pclk-sample = <1>;
+ remote-endpoint = <&vin2ep>;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <40>;
+
+ ov5640@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&mclk_cam4>;
+ clock-names = "xclk";
+
+ port {
+ ov5640_3: endpoint {
+ bus-width = <8>;
+ data-shift = <2>;
+ bus-type = <6>;
+ pclk-sample = <1>;
+ remote-endpoint = <&vin3ep>;
+ };
+ };
+
Re: [PATCH v3 5/5] arm64: dts: r8a77965: Add DRIF support
Hi Fabrizio,
Thank you for the patch.
On Tue, Oct 13, 2020 at 6:25 PM Fabrizio Castro
wrote:
>
> Add the DRIF controller nodes for r8a77965 (a.k.a. R-Car M3-N).
>
> Signed-off-by: Fabrizio Castro
> ---
> v2->v3:
> * New patch
>
> arch/arm64/boot/dts/renesas/r8a77965.dtsi | 120 ++
> 1 file changed, 120 insertions(+)
>
Reviewed-by: Lad Prabhakar
Cheers,
Prabhakar
> diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> index fe4dc12e2bdf..c5a54dc7ede2 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
> @@ -1550,6 +1550,126 @@ vin7csi40: endpoint@2 {
> };
> };
>
> + drif00: rif@e6f4 {
> + compatible = "renesas,r8a77965-drif",
> +"renesas,rcar-gen3-drif";
> + reg = <0 0xe6f4 0 0x84>;
> + interrupts = ;
> + clocks = <&cpg CPG_MOD 515>;
> + clock-names = "fck";
> + dmas = <&dmac1 0x20>, <&dmac2 0x20>;
> + dma-names = "rx", "rx";
> + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
> + resets = <&cpg 515>;
> + renesas,bonding = <&drif01>;
> + status = "disabled";
> + };
> +
> + drif01: rif@e6f5 {
> + compatible = "renesas,r8a77965-drif",
> +"renesas,rcar-gen3-drif";
> + reg = <0 0xe6f5 0 0x84>;
> + interrupts = ;
> + clocks = <&cpg CPG_MOD 514>;
> + clock-names = "fck";
> + dmas = <&dmac1 0x22>, <&dmac2 0x22>;
> + dma-names = "rx", "rx";
> + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
> + resets = <&cpg 514>;
> + renesas,bonding = <&drif00>;
> + status = "disabled";
> + };
> +
> + drif10: rif@e6f6 {
> + compatible = "renesas,r8a77965-drif",
> +"renesas,rcar-gen3-drif";
> + reg = <0 0xe6f6 0 0x84>;
> + interrupts = ;
> + clocks = <&cpg CPG_MOD 513>;
> + clock-names = "fck";
> + dmas = <&dmac1 0x24>, <&dmac2 0x24>;
> + dma-names = "rx", "rx";
> + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
> + resets = <&cpg 513>;
> + renesas,bonding = <&drif11>;
> + status = "disabled";
> + };
> +
> + drif11: rif@e6f7 {
> + compatible = "renesas,r8a77965-drif",
> +"renesas,rcar-gen3-drif";
> + reg = <0 0xe6f7 0 0x84>;
> + interrupts = ;
> + clocks = <&cpg CPG_MOD 512>;
> + clock-names = "fck";
> + dmas = <&dmac1 0x26>, <&dmac2 0x26>;
> + dma-names = "rx", "rx";
> + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
> + resets = <&cpg 512>;
> + renesas,bonding = <&drif10>;
> + status = "disabled";
> + };
> +
> + drif20: rif@e6f8 {
> + compatible = "renesas,r8a77965-drif",
> +"renesas,rcar-gen3-drif";
> + reg = <0 0xe6f8 0 0x84>;
> + interrupts = ;
> + clocks = <&cpg CPG_MOD 511>;
> + clock-names = "fck";
> + dmas = <&dmac1 0x28>, <&dmac2 0x28>;
> + dma-names = "rx", &
Re: [PATCH v3 4/5] media: dt-bindings: media: renesas,drif: Add r8a77965 support
Hi Fabrizio, Thank you for the patch. On Tue, Oct 13, 2020 at 6:25 PM Fabrizio Castro wrote: > > The r8a77965 (a.k.a. R-Car M3-N) device tree schema is > compatible with the already documented R-Car Gen3 devices. > > Document r8a77965 support within renesas,drif.yaml. > > Signed-off-by: Fabrizio Castro > --- > v2->v3: > * New patch > > Documentation/devicetree/bindings/media/renesas,drif.yaml | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Lad Prabhakar Cheers, Prabhakar > diff --git a/Documentation/devicetree/bindings/media/renesas,drif.yaml > b/Documentation/devicetree/bindings/media/renesas,drif.yaml > index ae50b1448320..89445ddd598e 100644 > --- a/Documentation/devicetree/bindings/media/renesas,drif.yaml > +++ b/Documentation/devicetree/bindings/media/renesas,drif.yaml > @@ -53,6 +53,7 @@ properties: >- enum: > - renesas,r8a7795-drif# R-Car H3 > - renesas,r8a7796-drif# R-Car M3-W > +- renesas,r8a77965-drif # R-Car M3-N > - renesas,r8a77990-drif # R-Car E3 >- const: renesas,rcar-gen3-drif # Generic R-Car Gen3 compatible device > > -- > 2.25.1 >
[tip: irq/core] irqchip: Kconfig: Update description for RENESAS_IRQC config
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 72d44c0cbc4369cc028429b85f4697957226282c
Gitweb:
https://git.kernel.org/tip/72d44c0cbc4369cc028429b85f4697957226282c
Author:Lad Prabhakar
AuthorDate:Fri, 11 Sep 2020 11:04:39 +01:00
Committer: Marc Zyngier
CommitterDate: Sun, 13 Sep 2020 18:06:21 +01:00
irqchip: Kconfig: Update description for RENESAS_IRQC config
irq-renesas-irqc driver is also used on Renesas RZ/G{1,2} SoC's, update
the same to reflect the description for RENESAS_IRQC config.
Signed-off-by: Lad Prabhakar
Signed-off-by: Marc Zyngier
Reviewed-by: Chris Paterson
Link:
https://lore.kernel.org/r/20200911100439.19878-1-prabhakar.mahadev-lad...@bp.renesas.com
---
drivers/irqchip/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index bfc9719..cdb7693 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -232,12 +232,12 @@ config RENESAS_INTC_IRQPIN
interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
config RENESAS_IRQC
- bool "Renesas R-Mobile APE6 and R-Car IRQC support" if COMPILE_TEST
+ bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support"
if COMPILE_TEST
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
help
Enable support for the Renesas Interrupt Controller for external
- devices, as found on R-Mobile APE6, R-Car Gen2, and R-Car Gen3 SoCs.
+ devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
config RENESAS_RZA1_IRQC
bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
Re: [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller
Hi Pavel,
Thank you for the review.
On Fri, Oct 9, 2020 at 8:23 AM Pavel Machek wrote:
>
> Hi!
>
> > +&pciec {
> > + /* SW2[6] determines which connector is activated
> > + * ON = PCIe X4 (connector-J7)
> > + * OFF = mini-PCIe (connector-J26)
> > + */
> > + status = "okay";
> > +};
>
> Note this is wrong comment style for non-network parts of kernel.
>
Good point, i'll fix that.
Cheers,
Prabhakar
Re: [PATCH v2 3/3] ARM: dts: r8a7742-iwg21d-q7: Enable SD2 LED indication
Hi Pavel,
Thank you for the review.
On Fri, Oct 9, 2020 at 8:33 AM Pavel Machek wrote:
>
> Hi!
>
> > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
> > @@ -63,6 +63,16 @@
> > enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
> > };
> >
> > + leds {
> > + compatible = "gpio-leds";
> > +
> > + sdhi2_led {
> > + label = "sdio-led";
>
> This should use appropriate label... probably mmc1:green:activity.
>
$ grep -nr mmc | grep -i activity
$ grep -nr sd | grep -i activity
Results in 0 outputs in dts folder.
Cheers,
Prabhakar
Re: [PATCH 2/4] arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2H
Hi Pavel, Thank you for the review. On Fri, Oct 9, 2020 at 8:48 AM Pavel Machek wrote: > > Hi! > > > index ..c62ddb9b2ba5 > > --- /dev/null > > +++ > > b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi > > @@ -0,0 +1,109 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > dts files are normally dual-licensed...? > All the Renesas dts files are GPL-2.0 Cheers, Prabhakar
