Re: [PATCH net-next 3/3] net: stmmac: Introducing support for Page Pool

[Lars Persson]

On Mon, Jul 22, 2019 at 12:18 PM Ilias Apalodimas
 wrote:
>
> On Thu, Jul 18, 2019 at 07:48:04AM +, Jose Abreu wrote:
> > From: Jon Hunter 
> > Date: Jul/17/2019, 19:58:53 (UTC+00:00)
> >
> > > Let me know if you have any thoughts.
> >
> > Can you try attached patch ?
> >
>
> The log says  someone calls panic() right?
> Can we trye and figure were that happens during the stmmac init phase?
>

The reason for the panic is hidden in this one line of the kernel logs:
Kernel panic - not syncing: Attempted to kill init! exitcode=0x000b

The init process is killed by SIGSEGV (signal 11 = 0xb).

I would suggest you look for data corruption bugs in the RX path. If
the code is fetched from the NFS mount then a corrupt RX buffer can
trigger a crash in userspace.

/Lars

[PATCH] mmc: usdhi6rol0: Add maintainers

[Lars Persson]

The usdhi6rol0 driver is exclusively used for the ARTPEC family of
SoCs. Other SoCs with the same IP of Panasonic origin use the tmio_mmc
driver. Therefore we assigner maintainer responsibility to us at Axis
until the two drivers become unified.

Change-Id: I38b6fd0addc1d93ae172332b67e6eb71c0871508
Signed-off-by: Lars Persson 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 677ef41cb012..a91d04e5c084 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1432,6 +1432,7 @@ F:arch/arm/mach-artpec
 F: arch/arm/boot/dts/artpec6*
 F: drivers/clk/axis
 F: drivers/crypto/axis
+F: drivers/mmc/host/usdhi6rol0.c
 F: drivers/pinctrl/pinctrl-artpec*
 F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
 
-- 
2.11.0

Re: [PATCH] mmc: remove another TMIO MMC variant usdhi6rol0.c

[Lars Persson]

On Fri, Jun 21, 2019 at 12:50 PM Wolfram Sang  wrote:
>
> Hi,
>
> On Fri, Jun 21, 2019 at 03:16:11PM +0900, Masahiro Yamada wrote:
> > (Added Lars Persson, Guennadi Liakhovetski)
> >
> > On Fri, Jun 21, 2019 at 3:06 PM Masahiro Yamada
> >  wrote:
> >
> > This needs Ack from Renesas.
> > But, I do not know if TMIO folks are sure about this driver, though.
> > (If they had been sure about it, they should not have duplicated the driver
> > in the first place.)
>
> ... and from the original mail:
>
> > Delete this driver now. Please re-implement it based on tmio_mmc_core.c
> > if needed.
>
> I was never happy with this driver existing, yet I never knew which HW
> platform needed this, so I didn't touch it. But I'd like to see it go in
> favor of merging with the TMIO code base.
>
> >
> > Perhaps, some code snippets in this driver might be useful for cleaning
> > tmio_mmc. It will stay in git history forever, and you can dig for it
> > whenever you need it.
> >
> > Signed-off-by: Masahiro Yamada 
>
> I double checked there is no user in the current tree. I also searched
> the web and did not find any out-of-tree user or even a reference of it.
>
> So, for now:
>
> Reviewed-by: Wolfram Sang 
>
> But this seriously needs an Ack from Shimoda-san or Morimoto-san. And
> maybe Guennadi has remarks, too?
>

So let me tell you the real use of this driver.

It is used by Axis Communications in our Artpec-6 chips that will be
around for at least 5 years in active development at our side. The SoC
is upstreamed, but the upstreaming effort was side-tracked before the
usdhi6rol0 was added to the devicetree.

I do agree with you guys that we should not keep two drivers for the
same IP so there should be an effort to unify the drivers. In the mean
time, we can make the connection with Axis more explicit by assigning
us as maintainer and pushing the device tree entries.

BR,
 Lars

Re: [PATCH 4.14 082/115] cifs: fix memory leak in SMB2_read

[Lars Persson]

On Wed, May 15, 2019 at 1:19 PM Greg Kroah-Hartman
 wrote:
>
> [ Upstream commit 05fd5c2c61732152a6bddc318aae62d7e436629b ]
>
> Commit 088aaf17aa79300cab14dbee2569c58cfafd7d6e introduced a leak where
> if SMB2_read() returned an error we would return without freeing the
> request buffer.
>
> Cc: Stable 
> Signed-off-by: Ronnie Sahlberg 
> Reviewed-by: Pavel Shilovsky 
> Signed-off-by: Steve French 
> Signed-off-by: Sasha Levin 
> ---
>  fs/cifs/smb2pdu.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c
> index fd2d199dd413e..7936eac5a38a2 100644
> --- a/fs/cifs/smb2pdu.c
> +++ b/fs/cifs/smb2pdu.c
> @@ -2699,6 +2699,7 @@ SMB2_read(const unsigned int xid, struct cifs_io_parms 
> *io_parms,
> cifs_dbg(VFS, "Send error in read = %d\n", rc);
> }
> free_rsp_buf(resp_buftype, rsp_iov.iov_base);
> +   cifs_small_buf_release(req);
> return rc == -ENODATA ? 0 : rc;
> }
>
> --
> 2.20.1
>

This patch should not be in 4.14-stable because
088aaf17aa79300cab14dbee2569c58cfafd7d6e was for 4.18+.

Now we have a double-free crash in SMB2_read because there are 2 calls
to cifs_small_buf_release in the error path.

=
BUG cifs_small_rq (Tainted: GB  O   ): Object already free
-

INFO: Allocated in mempool_alloc+0x35/0xe4 age=1 cpu=0 pid=21107
kmem_cache_alloc+0x131/0x218
mempool_alloc+0x35/0xe4
cifs_small_buf_get+0x1d/0x3c [cifs]
smb2_new_read_req.constprop.2+0x29/0xd0 [cifs]
SMB2_read+0x39/0x17c [cifs]
cifs_readpage_worker+0x13f/0x470 [cifs]
cifs_readpage+0x67/0x1b8 [cifs]
generic_file_read_iter+0x269/0x904
cifs_strict_readv+0xa3/0xc8 [cifs]
__vfs_read+0x97/0xbc
vfs_read+0x61/0xc8
SyS_pread64+0x4d/0x6c
ret_fast_syscall+0x1/0x64
INFO: Freed in cifs_small_buf_release+0x19/0x90 [cifs] age=0 cpu=0 pid=21107
cifs_small_buf_release+0x19/0x90 [cifs]
SMB2_read+0x83/0x17c [cifs]
cifs_readpage_worker+0x13f/0x470 [cifs]
cifs_readpage+0x67/0x1b8 [cifs]
generic_file_read_iter+0x269/0x904
cifs_strict_readv+0xa3/0xc8 [cifs]
__vfs_read+0x97/0xbc
vfs_read+0x61/0xc8
SyS_pread64+0x4d/0x6c
ret_fast_syscall+0x1/0x64
INFO: Slab 0xbf6fe800 objects=12 used=1 fp=0x8cf00d40 flags=0x8101
INFO: Object 0x8cf01d00 @offset=7424 fp=0x8cf002c0

Redzone 8cf01ce0: bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb

Redzone 8cf01cf0: bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb

Object 8cf01d00: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01d10: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01d20: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01d30: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01d40: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01d50: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01d60: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01d70: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01d80: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01d90: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01da0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01db0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01dc0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01dd0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01de0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01df0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01e00: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01e10: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01e20: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01e30: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01e40: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01e50: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01e60: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01e70: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01e80: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01e90: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01ea0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b

Object 8cf01eb0: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b a5
kkk.
Redzone 8cf01ec0: bb bb bb bb  
Padding 8cf01f68: 5a 5a 5a 5a 5a 5a 

[PATCH v2] mm: migrate: add missing flush_dcache_page for non-mapped page migrate

[Lars Persson]

Our MIPS 1004Kc SoCs were seeing random userspace crashes with SIGILL
and SIGSEGV that could not be traced back to a userspace code
bug. They had all the magic signs of an I/D cache coherency issue.

Now recently we noticed that the /proc/sys/vm/compact_memory interface
was quite efficient at provoking this class of userspace crashes.

Studying the code in mm/migrate.c there is a distinction made between
migrating a page that is mapped at the instant of migration and one
that is not mapped. Our problem turned out to be the non-mapped pages.

For the non-mapped page the code performs a copy of the page content
and all relevant meta-data of the page without doing the required
D-cache maintenance. This leaves dirty data in the D-cache of the CPU
and on the 1004K cores this data is not visible to the I-cache. A
subsequent page-fault that triggers a mapping of the page will happily
serve the process with potentially stale code.

What about ARM then, this bug should have seen greater exposure? Well
ARM became immune to this flaw back in 2010, see commit c01778001a4f
("ARM: 6379/1: Assume new page cache pages have dirty D-cache").

My proposed fix moves the D-cache maintenance inside move_to_new_page
to make it common for both cases.

Cc: sta...@vger.kernel.org
Fixes: 97ee0524614 ("flush cache before installing new page at migraton")
Reviewed-by: Paul Burton 
Acked-by: Mel Gorman 
Signed-off-by: Lars Persson 
---
v2: Added a Fixes footer and CC for stable. No functional change.
---
 mm/migrate.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/mm/migrate.c b/mm/migrate.c
index ac6f4939bb59..663a5449367a 100644
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -248,10 +248,8 @@ static bool remove_migration_pte(struct page *page, struct 
vm_area_struct *vma,
pte = swp_entry_to_pte(entry);
} else if (is_device_public_page(new)) {
pte = pte_mkdevmap(pte);
-   flush_dcache_page(new);
}
-   } else
-   flush_dcache_page(new);
+   }
 
 #ifdef CONFIG_HUGETLB_PAGE
if (PageHuge(new)) {
@@ -995,6 +993,13 @@ static int move_to_new_page(struct page *newpage, struct 
page *page,
 */
if (!PageMappingFlags(page))
page->mapping = NULL;
+
+   if (unlikely(is_zone_device_page(newpage))) {
+   if (is_device_public_page(newpage))
+   flush_dcache_page(newpage);
+   } else
+   flush_dcache_page(newpage);
+
}
 out:
return rc;
-- 
2.11.0

Re: [PATCH] mm: migrate: add missing flush_dcache_page for non-mapped page migrate

[Lars Persson]

On 2/26/19 12:57 PM, Lars Persson wrote:



On 2/26/19 11:07 AM, Vlastimil Babka wrote:

On 2/26/19 9:40 AM, Lars Persson wrote:

What about CC stable and a Fixes tag, would it be applicable here?



Yes this is candidate for stable so let's add:
Cc: 

I do not find a good candidate for a Fixes tag.


How bout a version range where the bug needs to be fixed then?



The distinction between mapped and non-mapped old page was introduced in 2ebba6b7e1d9 
("mm: unmapped page migration avoid unmap+remap overhead") so at least it 
applies to stable 4.4+.

Before that patch there was always a call to remove_migration_ptes() but I 
cannot conclude if those earlier versions actually will reach the 
flush_dcache_page call if the old page was unmapped.



Should I submit a V2 patch with CC stable for v4.4+ ?

- Lars

Re: [PATCH] mm: migrate: add missing flush_dcache_page for non-mapped page migrate

[Lars Persson]

On 2/26/19 11:07 AM, Vlastimil Babka wrote:

On 2/26/19 9:40 AM, Lars Persson wrote:

What about CC stable and a Fixes tag, would it be applicable here?



Yes this is candidate for stable so let's add:
Cc: 

I do not find a good candidate for a Fixes tag.


How bout a version range where the bug needs to be fixed then?



The distinction between mapped and non-mapped old page was introduced in 2ebba6b7e1d9 
("mm: unmapped page migration avoid unmap+remap overhead") so at least it 
applies to stable 4.4+.

Before that patch there was always a call to remove_migration_ptes() but I 
cannot conclude if those earlier versions actually will reach the 
flush_dcache_page call if the old page was unmapped.

Re: [PATCH] mm: migrate: add missing flush_dcache_page for non-mapped page migrate

[Lars Persson]

On Tue, Feb 26, 2019 at 10:23 AM Anshuman Khandual
 wrote:
> On 02/19/2019 06:02 PM, Lars Persson wrote:
> > Our MIPS 1004Kc SoCs were seeing random userspace crashes with SIGILL
> > and SIGSEGV that could not be traced back to a userspace code
> > bug. They had all the magic signs of an I/D cache coherency issue.
> >
> > Now recently we noticed that the /proc/sys/vm/compact_memory interface
> > was quite efficient at provoking this class of userspace crashes.
> >
> > Studying the code in mm/migrate.c there is a distinction made between
> > migrating a page that is mapped at the instant of migration and one
> > that is not mapped. Our problem turned out to be the non-mapped pages.
> >
> > For the non-mapped page the code performs a copy of the page content
> > and all relevant meta-data of the page without doing the required
> > D-cache maintenance. This leaves dirty data in the D-cache of the CPU
> > and on the 1004K cores this data is not visible to the I-cache. A
> > subsequent page-fault that triggers a mapping of the page will happily
> > serve the process with potentially stale code.
>
> Just curious. Is not the code path which tries to map this page should
> do the invalidation just before setting it up in the page table via
> set_pte_at() or other similar variants ? How it maps without doing the
> necessary flush.

In fact this is what happens when the flush_dcache_page API was used
correctly, but it is an arch implementation detail. All kernel code
that writes to a page cage page must also call flush_dcache_page
before the page becomes eligible for mapping. The arch code has the
option to postpone the actual flush until set_pte_at maps the page.

Re: [PATCH] mm: migrate: add missing flush_dcache_page for non-mapped page migrate

[Lars Persson]

On 2/25/19 4:07 PM, Vlastimil Babka wrote:

On 2/19/19 1:32 PM, Lars Persson wrote:

Our MIPS 1004Kc SoCs were seeing random userspace crashes with SIGILL
and SIGSEGV that could not be traced back to a userspace code
bug. They had all the magic signs of an I/D cache coherency issue.

Now recently we noticed that the /proc/sys/vm/compact_memory interface
was quite efficient at provoking this class of userspace crashes.

Studying the code in mm/migrate.c there is a distinction made between
migrating a page that is mapped at the instant of migration and one
that is not mapped. Our problem turned out to be the non-mapped pages.

For the non-mapped page the code performs a copy of the page content
and all relevant meta-data of the page without doing the required
D-cache maintenance. This leaves dirty data in the D-cache of the CPU
and on the 1004K cores this data is not visible to the I-cache. A
subsequent page-fault that triggers a mapping of the page will happily
serve the process with potentially stale code.

What about ARM then, this bug should have seen greater exposure? Well
ARM became immune to this flaw back in 2010, see commit c01778001a4f
("ARM: 6379/1: Assume new page cache pages have dirty D-cache").

My proposed fix moves the D-cache maintenance inside move_to_new_page
to make it common for both cases.

Signed-off-by: Lars Persson 


What about CC stable and a Fixes tag, would it be applicable here?



Yes this is candidate for stable so let's add:
Cc: 

I do not find a good candidate for a Fixes tag.

[PATCH] mm: migrate: add missing flush_dcache_page for non-mapped page migrate

[Lars Persson]

Our MIPS 1004Kc SoCs were seeing random userspace crashes with SIGILL
and SIGSEGV that could not be traced back to a userspace code
bug. They had all the magic signs of an I/D cache coherency issue.

Now recently we noticed that the /proc/sys/vm/compact_memory interface
was quite efficient at provoking this class of userspace crashes.

Studying the code in mm/migrate.c there is a distinction made between
migrating a page that is mapped at the instant of migration and one
that is not mapped. Our problem turned out to be the non-mapped pages.

For the non-mapped page the code performs a copy of the page content
and all relevant meta-data of the page without doing the required
D-cache maintenance. This leaves dirty data in the D-cache of the CPU
and on the 1004K cores this data is not visible to the I-cache. A
subsequent page-fault that triggers a mapping of the page will happily
serve the process with potentially stale code.

What about ARM then, this bug should have seen greater exposure? Well
ARM became immune to this flaw back in 2010, see commit c01778001a4f
("ARM: 6379/1: Assume new page cache pages have dirty D-cache").

My proposed fix moves the D-cache maintenance inside move_to_new_page
to make it common for both cases.

Signed-off-by: Lars Persson 
---
 mm/migrate.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/mm/migrate.c b/mm/migrate.c
index d4fd680be3b0..80fc19e610b5 100644
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -248,10 +248,8 @@ static bool remove_migration_pte(struct page *page, struct 
vm_area_struct *vma,
pte = swp_entry_to_pte(entry);
} else if (is_device_public_page(new)) {
pte = pte_mkdevmap(pte);
-   flush_dcache_page(new);
}
-   } else
-   flush_dcache_page(new);
+   }
 
 #ifdef CONFIG_HUGETLB_PAGE
if (PageHuge(new)) {
@@ -995,6 +993,13 @@ static int move_to_new_page(struct page *newpage, struct 
page *page,
 */
if (!PageMappingFlags(page))
page->mapping = NULL;
+
+   if (unlikely(is_zone_device_page(newpage))) {
+   if (is_device_public_page(newpage))
+   flush_dcache_page(newpage);
+   } else
+   flush_dcache_page(newpage);
+
}
 out:
return rc;
-- 
2.11.0

Re: [PATCH v2] mm: page_mapped: don't assume compound page is huge or THP

[Lars Persson]

On Tue, Feb 5, 2019 at 8:14 AM Jan Stancek  wrote:
> Hi,
>
> are you using THP (CONFIG_TRANSPARENT_HUGEPAGE)?
>
> The changed line should affect only THP and normal compound pages,
> so a test with THP disabled might be interesting.
>
> >
> > The breakage consists of random processes dying with SIGILL or SIGSEGV
> > when we stress test the system with high memory pressure and explicit
> > memory compaction requested through /proc/sys/vm/compact_memory.
> > Reverting this patch fixes the crashes.
> >
> > We can put some effort on debugging if there are no obvious
> > explanations for this. Keep in mind that this is 32-bit system with
> > HIGHMEM.
>
> Nothing obvious that I can see. I've been trying to reproduce on
> 32-bit x86 Fedora with no luck so far.
>

Hi

Thanks for looking in to it. After some deep dive in MM code, I think
it is safe to say this patch was innocent.

All traces studied so far points to a missing cache coherency call in
mm/migrate.c:migrate_page that is needed only for those evil MIPSes
that lack I/D cache coherency. I will send a write-up to linux-mips
about this. Basically for a non-mapped page it does only a copy of
page data and metadata but no flush_dcache_page() call will be done.
This races with subsequent use of the page.

BR,
 Lars

Re: [PATCH v2] mm: page_mapped: don't assume compound page is huge or THP

[Lars Persson]

On Fri, Nov 30, 2018 at 1:07 PM Jan Stancek  wrote:
>
> LTP proc01 testcase has been observed to rarely trigger crashes
> on arm64:
> page_mapped+0x78/0xb4
> stable_page_flags+0x27c/0x338
> kpageflags_read+0xfc/0x164
> proc_reg_read+0x7c/0xb8
> __vfs_read+0x58/0x178
> vfs_read+0x90/0x14c
> SyS_read+0x60/0xc0
>
> Issue is that page_mapped() assumes that if compound page is not
> huge, then it must be THP. But if this is 'normal' compound page
> (COMPOUND_PAGE_DTOR), then following loop can keep running
> (for HPAGE_PMD_NR iterations) until it tries to read from memory
> that isn't mapped and triggers a panic:
> for (i = 0; i < hpage_nr_pages(page); i++) {
> if (atomic_read([i]._mapcount) >= 0)
> return true;
> }
>
> I could replicate this on x86 (v4.20-rc4-98-g60b548237fed) only
> with a custom kernel module [1] which:
> - allocates compound page (PAGEC) of order 1
> - allocates 2 normal pages (COPY), which are initialized to 0xff
>   (to satisfy _mapcount >= 0)
> - 2 PAGEC page structs are copied to address of first COPY page
> - second page of COPY is marked as not present
> - call to page_mapped(COPY) now triggers fault on access to 2nd
>   COPY page at offset 0x30 (_mapcount)
>
> [1] 
> https://github.com/jstancek/reproducers/blob/master/kernel/page_mapped_crash/repro.c
>
> Fix the loop to iterate for "1 << compound_order" pages.
>
> Debugged-by: Laszlo Ersek 
> Suggested-by: "Kirill A. Shutemov" 
> Signed-off-by: Jan Stancek 
> ---
>  mm/util.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> Changes in v2:
> - change the loop instead so we check also mapcount of subpages
>
> diff --git a/mm/util.c b/mm/util.c
> index 8bf08b5b5760..5c9c7359ee8a 100644
> --- a/mm/util.c
> +++ b/mm/util.c
> @@ -478,7 +478,7 @@ bool page_mapped(struct page *page)
> return true;
> if (PageHuge(page))
> return false;
> -   for (i = 0; i < hpage_nr_pages(page); i++) {
> +   for (i = 0; i < (1 << compound_order(page)); i++) {
> if (atomic_read([i]._mapcount) >= 0)
> return true;
> }
> --
> 1.8.3.1

Hi all

This patch landed in the 4.9-stable tree starting from 4.9.151 and it
broke our MIPS1004kc system with CONFIG_HIGHMEM=y.

The breakage consists of random processes dying with SIGILL or SIGSEGV
when we stress test the system with high memory pressure and explicit
memory compaction requested through /proc/sys/vm/compact_memory.
Reverting this patch fixes the crashes.

We can put some effort on debugging if there are no obvious
explanations for this. Keep in mind that this is 32-bit system with
HIGHMEM.

BR,
 Lars

Re: [PATCH 3/7] crypto: axis: no need to check return value of debugfs_create functions

[Lars Persson]

On 1/22/19 4:14 PM, Greg Kroah-Hartman wrote:

When calling debugfs functions, there is no need to ever check the
return value.  The function can work or not, but the code logic should
never do something different based on this.

Cc: Jesper Nilsson 
Cc: Lars Persson 
Cc: Herbert Xu 
Cc: "David S. Miller" 
Cc: linux-arm-ker...@axis.com
Cc: linux-cry...@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman 
---
  drivers/crypto/axis/artpec6_crypto.c | 9 -
  1 file changed, 9 deletions(-)


Acked-by: Lars Persson 

Thanks,
 Lars

Re: [PATCH 4.9 069/101] ubi: fastmap: Correctly handle interrupted erasures in EBA

[Lars Persson]

On Mon, Sep 24, 2018 at 8:32 AM Richard Weinberger  wrote:
>
> Lars,
>
> Am Sonntag, 23. September 2018, 15:49:42 CEST schrieb Lars Persson:
> > Hi Richard
> >
> > Sorry, I assumed this omission from -stable was a mistake.
> >
> > The timing for our boot increased from 45 seconds to 55 seconds on one
> > chip and 42 seconds to 48 seconds on another chip. The regression was
> > completely fixed by applying the extra patches. The way I see it the
> > first patch is a significant slow-down so the second patch is required
> > to restore performance.
>
> okay, this is not good. Let's put the performance patch also into -stable
> to get rid of that regression.
> Usually I'm rather conservative with adding non-trivial material to -stable.
> As history has shown, Fastmap is special. ;-)
>
> Out of interest, what flashes are these? I'm interested in page vs. erase 
> size.
> Did you give UBIFS bulk-read try?
>

Richard, sorry for the late follow-up. Below are the NAND chips that
we use on the affected products.
The products have different NAND timings, some ONFI mode 0 and some
ONFI mode 2, so not lightning fast access to the NAND.

nand: Toshiba NAND 256MiB 3,3V 8-bit
nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 128

nand: Micron MT29F2G08ABAFA 2G 3.3V 8-bit
nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 128

nand: AMD/Spansion S34ML04G2
nand: 512 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 128

- Lars

Re: [PATCH 4.9 069/101] ubi: fastmap: Correctly handle interrupted erasures in EBA

[Lars Persson]

On Mon, Sep 24, 2018 at 8:32 AM Richard Weinberger  wrote:
>
> Lars,
>
> Am Sonntag, 23. September 2018, 15:49:42 CEST schrieb Lars Persson:
> > Hi Richard
> >
> > Sorry, I assumed this omission from -stable was a mistake.
> >
> > The timing for our boot increased from 45 seconds to 55 seconds on one
> > chip and 42 seconds to 48 seconds on another chip. The regression was
> > completely fixed by applying the extra patches. The way I see it the
> > first patch is a significant slow-down so the second patch is required
> > to restore performance.
>
> okay, this is not good. Let's put the performance patch also into -stable
> to get rid of that regression.
> Usually I'm rather conservative with adding non-trivial material to -stable.
> As history has shown, Fastmap is special. ;-)
>
> Out of interest, what flashes are these? I'm interested in page vs. erase 
> size.
> Did you give UBIFS bulk-read try?
>

Richard, sorry for the late follow-up. Below are the NAND chips that
we use on the affected products.
The products have different NAND timings, some ONFI mode 0 and some
ONFI mode 2, so not lightning fast access to the NAND.

nand: Toshiba NAND 256MiB 3,3V 8-bit
nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 128

nand: Micron MT29F2G08ABAFA 2G 3.3V 8-bit
nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 128

nand: AMD/Spansion S34ML04G2
nand: 512 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 128

- Lars

Re: [PATCH 4.9 069/101] ubi: fastmap: Correctly handle interrupted erasures in EBA

[Lars Persson]

On Sun, Sep 23, 2018 at 2:58 PM Richard Weinberger  wrote:
>
> Lars,
>
> Am Sonntag, 23. September 2018, 14:49:23 CEST schrieb Lars Persson:
> > On Sun, Jul 1, 2018 at 6:27 PM Greg Kroah-Hartman
> >  wrote:
> > >
> > > 4.9-stable review patch.  If anyone has any objections, please let me 
> > > know.
> > >
> > > --
> > >
> > > From: Richard Weinberger 
> > >
> > > commit 781932375ffc6411713ee0926ccae8596ed0261c upstream.
> > >
> > > Fastmap cannot track the LEB unmap operation, therefore it can
> > > happen that after an interrupted erasure the mapping still looks
> > > good from Fastmap's point of view, while reading from the PEB will
> > > cause an ECC error and confuses the upper layer.
> > >
> > > Instead of teaching users of UBI how to deal with that, we read back
> > > the VID header and check for errors. If the PEB is empty or shows ECC
> > > errors we fixup the mapping and schedule the PEB for erasure.
> > >
> > > Fixes: dbb7d2a88d2a ("UBI: Add fastmap core")
> > > Cc: 
> > > Reported-by: martin bayern 
> > > Signed-off-by: Richard Weinberger 
> > > Signed-off-by: Greg Kroah-Hartman 
> > >
> > >
> > Hi Greg
> >
> > This commit belongs to a series of 3 commits that are intended to be
> > used together. Currently the stable branches have only the first
> > commit from the series and we get a UBI speed regression because an
> > extra NAND page read is always performed for each access to a UBI LEB.
> >
> > 3e5e4335cc0ffd668054564b113fb3c9c97badb8 ubi: fastmap: Detect EBA
> > mismatches on-the-fly
> > 34653fd8c46e771585fce5975e4243f8fd401914 ubi: fastmap: Check each
> > mapping only once
> > 781932375ffc6411713ee0926ccae8596ed0261c ubi: fastmap: Correctly
> > handle interrupted erasures in EBA
> >
> > This will in turn require also this follow-up patch:
> > 25677478474a91fa1b46f19a4a591a9848bca6fb ubi: Initialize Fastmap
> > checkmapping correctly
>
> Wait.
> Commit 34653fd8c46e771585fce5975e4243f8fd401914 was not scheduled for stable
> on purpose.
> It is just an optimization. How much is the performance regression you see?
> Commit 3e5e4335cc0ffd668054564b113fb3c9c97badb8 does not fix anything, all it
> does is adding another paranoia check to UBI.
>
> I'd appreciate if you would come up with regression reports on linux-mtd first
> before asking Greg to pick patches up...
>

Hi Richard

Sorry, I assumed this omission from -stable was a mistake.

The timing for our boot increased from 45 seconds to 55 seconds on one
chip and 42 seconds to 48 seconds on another chip. The regression was
completely fixed by applying the extra patches. The way I see it the
first patch is a significant slow-down so the second patch is required
to restore performance.

- Lars

Re: [PATCH 4.9 069/101] ubi: fastmap: Correctly handle interrupted erasures in EBA

[Lars Persson]

On Sun, Sep 23, 2018 at 2:58 PM Richard Weinberger  wrote:
>
> Lars,
>
> Am Sonntag, 23. September 2018, 14:49:23 CEST schrieb Lars Persson:
> > On Sun, Jul 1, 2018 at 6:27 PM Greg Kroah-Hartman
> >  wrote:
> > >
> > > 4.9-stable review patch.  If anyone has any objections, please let me 
> > > know.
> > >
> > > --
> > >
> > > From: Richard Weinberger 
> > >
> > > commit 781932375ffc6411713ee0926ccae8596ed0261c upstream.
> > >
> > > Fastmap cannot track the LEB unmap operation, therefore it can
> > > happen that after an interrupted erasure the mapping still looks
> > > good from Fastmap's point of view, while reading from the PEB will
> > > cause an ECC error and confuses the upper layer.
> > >
> > > Instead of teaching users of UBI how to deal with that, we read back
> > > the VID header and check for errors. If the PEB is empty or shows ECC
> > > errors we fixup the mapping and schedule the PEB for erasure.
> > >
> > > Fixes: dbb7d2a88d2a ("UBI: Add fastmap core")
> > > Cc: 
> > > Reported-by: martin bayern 
> > > Signed-off-by: Richard Weinberger 
> > > Signed-off-by: Greg Kroah-Hartman 
> > >
> > >
> > Hi Greg
> >
> > This commit belongs to a series of 3 commits that are intended to be
> > used together. Currently the stable branches have only the first
> > commit from the series and we get a UBI speed regression because an
> > extra NAND page read is always performed for each access to a UBI LEB.
> >
> > 3e5e4335cc0ffd668054564b113fb3c9c97badb8 ubi: fastmap: Detect EBA
> > mismatches on-the-fly
> > 34653fd8c46e771585fce5975e4243f8fd401914 ubi: fastmap: Check each
> > mapping only once
> > 781932375ffc6411713ee0926ccae8596ed0261c ubi: fastmap: Correctly
> > handle interrupted erasures in EBA
> >
> > This will in turn require also this follow-up patch:
> > 25677478474a91fa1b46f19a4a591a9848bca6fb ubi: Initialize Fastmap
> > checkmapping correctly
>
> Wait.
> Commit 34653fd8c46e771585fce5975e4243f8fd401914 was not scheduled for stable
> on purpose.
> It is just an optimization. How much is the performance regression you see?
> Commit 3e5e4335cc0ffd668054564b113fb3c9c97badb8 does not fix anything, all it
> does is adding another paranoia check to UBI.
>
> I'd appreciate if you would come up with regression reports on linux-mtd first
> before asking Greg to pick patches up...
>

Hi Richard

Sorry, I assumed this omission from -stable was a mistake.

The timing for our boot increased from 45 seconds to 55 seconds on one
chip and 42 seconds to 48 seconds on another chip. The regression was
completely fixed by applying the extra patches. The way I see it the
first patch is a significant slow-down so the second patch is required
to restore performance.

- Lars

Re: [PATCH 4.9 069/101] ubi: fastmap: Correctly handle interrupted erasures in EBA

[Lars Persson]

On Sun, Jul 1, 2018 at 6:27 PM Greg Kroah-Hartman
 wrote:
>
> 4.9-stable review patch.  If anyone has any objections, please let me know.
>
> --
>
> From: Richard Weinberger 
>
> commit 781932375ffc6411713ee0926ccae8596ed0261c upstream.
>
> Fastmap cannot track the LEB unmap operation, therefore it can
> happen that after an interrupted erasure the mapping still looks
> good from Fastmap's point of view, while reading from the PEB will
> cause an ECC error and confuses the upper layer.
>
> Instead of teaching users of UBI how to deal with that, we read back
> the VID header and check for errors. If the PEB is empty or shows ECC
> errors we fixup the mapping and schedule the PEB for erasure.
>
> Fixes: dbb7d2a88d2a ("UBI: Add fastmap core")
> Cc: 
> Reported-by: martin bayern 
> Signed-off-by: Richard Weinberger 
> Signed-off-by: Greg Kroah-Hartman 
>
>
Hi Greg

This commit belongs to a series of 3 commits that are intended to be
used together. Currently the stable branches have only the first
commit from the series and we get a UBI speed regression because an
extra NAND page read is always performed for each access to a UBI LEB.

3e5e4335cc0ffd668054564b113fb3c9c97badb8 ubi: fastmap: Detect EBA
mismatches on-the-fly
34653fd8c46e771585fce5975e4243f8fd401914 ubi: fastmap: Check each
mapping only once
781932375ffc6411713ee0926ccae8596ed0261c ubi: fastmap: Correctly
handle interrupted erasures in EBA

This will in turn require also this follow-up patch:
25677478474a91fa1b46f19a4a591a9848bca6fb ubi: Initialize Fastmap
checkmapping correctly


BR,
 Lars Persson

Re: [PATCH 4.9 069/101] ubi: fastmap: Correctly handle interrupted erasures in EBA

[Lars Persson]

On Sun, Jul 1, 2018 at 6:27 PM Greg Kroah-Hartman
 wrote:
>
> 4.9-stable review patch.  If anyone has any objections, please let me know.
>
> --
>
> From: Richard Weinberger 
>
> commit 781932375ffc6411713ee0926ccae8596ed0261c upstream.
>
> Fastmap cannot track the LEB unmap operation, therefore it can
> happen that after an interrupted erasure the mapping still looks
> good from Fastmap's point of view, while reading from the PEB will
> cause an ECC error and confuses the upper layer.
>
> Instead of teaching users of UBI how to deal with that, we read back
> the VID header and check for errors. If the PEB is empty or shows ECC
> errors we fixup the mapping and schedule the PEB for erasure.
>
> Fixes: dbb7d2a88d2a ("UBI: Add fastmap core")
> Cc: 
> Reported-by: martin bayern 
> Signed-off-by: Richard Weinberger 
> Signed-off-by: Greg Kroah-Hartman 
>
>
Hi Greg

This commit belongs to a series of 3 commits that are intended to be
used together. Currently the stable branches have only the first
commit from the series and we get a UBI speed regression because an
extra NAND page read is always performed for each access to a UBI LEB.

3e5e4335cc0ffd668054564b113fb3c9c97badb8 ubi: fastmap: Detect EBA
mismatches on-the-fly
34653fd8c46e771585fce5975e4243f8fd401914 ubi: fastmap: Check each
mapping only once
781932375ffc6411713ee0926ccae8596ed0261c ubi: fastmap: Correctly
handle interrupted erasures in EBA

This will in turn require also this follow-up patch:
25677478474a91fa1b46f19a4a591a9848bca6fb ubi: Initialize Fastmap
checkmapping correctly


BR,
 Lars Persson

Re: [PATCH] drivers/crypto: Convert timers to use timer_setup()

[Lars Persson]

On 10/25/2017 12:18 PM, Kees Cook wrote:

In preparation for unconditionally passing the struct timer_list pointer to
all timer callbacks, switch to using the new timer_setup() and from_timer()
to pass the timer pointer explicitly.

Cc: Herbert Xu <herb...@gondor.apana.org.au>
Cc: Jesper Nilsson <jesper.nils...@axis.com>
Cc: Lars Persson <lars.pers...@axis.com>
Cc: Niklas Cassel <niklas.cas...@axis.com>
Cc: "David S. Miller" <da...@davemloft.net>
Cc: Jamie Iles <ja...@jamieiles.com>
Cc: linux-arm-ker...@axis.com
Cc: linux-cry...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Kees Cook <keesc...@chromium.org>


For drivers/crypto/axis:
Acked-by: Lars Persson <lars.pers...@axis.com>

Thanks,
 Lars

Re: [PATCH] drivers/crypto: Convert timers to use timer_setup()

[Lars Persson]

On 10/25/2017 12:18 PM, Kees Cook wrote:

In preparation for unconditionally passing the struct timer_list pointer to
all timer callbacks, switch to using the new timer_setup() and from_timer()
to pass the timer pointer explicitly.

Cc: Herbert Xu 
Cc: Jesper Nilsson 
Cc: Lars Persson 
Cc: Niklas Cassel 
Cc: "David S. Miller" 
Cc: Jamie Iles 
Cc: linux-arm-ker...@axis.com
Cc: linux-cry...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Kees Cook 


For drivers/crypto/axis:
Acked-by: Lars Persson 

Thanks,
 Lars

Re: [PATCH] crypto: axis - hide an unused variable

[Lars Persson]

> 25 aug. 2017 kl. 01:20 skrev Arnd Bergmann <a...@arndb.de>:
> 
> Without CONFIG_DEBUG_FS, we get a harmless warning:
> 
> drivers/crypto/axis/artpec6_crypto.c:352:23: error: 'dbgfs_root' defined but 
> not used [-Werror=unused-variable]
> 
> This moves it into the #ifdef that hides the only user.
> 
> Fixes: a21eb94fc4d3 ("crypto: axis - add ARTPEC-6/7 crypto accelerator 
> driver")
> Signed-off-by: Arnd Bergmann <a...@arndb.de>
> ---
> drivers/crypto/axis/artpec6_crypto.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/crypto/axis/artpec6_crypto.c 
> b/drivers/crypto/axis/artpec6_crypto.c
> index d9fbbf01062b..0f9754e07719 100644
> --- a/drivers/crypto/axis/artpec6_crypto.c
> +++ b/drivers/crypto/axis/artpec6_crypto.c
> @@ -349,8 +349,6 @@ struct artpec6_crypto_aead_req_ctx {
> /* The crypto framework makes it hard to avoid this global. */
> static struct device *artpec6_crypto_dev;
> 
> -static struct dentry *dbgfs_root;
> -
> #ifdef CONFIG_FAULT_INJECTION
> static DECLARE_FAULT_ATTR(artpec6_crypto_fail_status_read);
> static DECLARE_FAULT_ATTR(artpec6_crypto_fail_dma_array_full);
> @@ -2984,6 +2982,8 @@ struct dbgfs_u32 {
>   char *desc;
> };
> 
> +static struct dentry *dbgfs_root;
> +
> static void artpec6_crypto_init_debugfs(void)
> {
>   dbgfs_root = debugfs_create_dir("artpec6_crypto", NULL);
> -- 
> 2.9.0
Acked-by: Lars Persson <lar...@axis.com>

Thanks,
 Lars

Re: [PATCH] crypto: axis - hide an unused variable

[Lars Persson]

> 25 aug. 2017 kl. 01:20 skrev Arnd Bergmann :
> 
> Without CONFIG_DEBUG_FS, we get a harmless warning:
> 
> drivers/crypto/axis/artpec6_crypto.c:352:23: error: 'dbgfs_root' defined but 
> not used [-Werror=unused-variable]
> 
> This moves it into the #ifdef that hides the only user.
> 
> Fixes: a21eb94fc4d3 ("crypto: axis - add ARTPEC-6/7 crypto accelerator 
> driver")
> Signed-off-by: Arnd Bergmann 
> ---
> drivers/crypto/axis/artpec6_crypto.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/crypto/axis/artpec6_crypto.c 
> b/drivers/crypto/axis/artpec6_crypto.c
> index d9fbbf01062b..0f9754e07719 100644
> --- a/drivers/crypto/axis/artpec6_crypto.c
> +++ b/drivers/crypto/axis/artpec6_crypto.c
> @@ -349,8 +349,6 @@ struct artpec6_crypto_aead_req_ctx {
> /* The crypto framework makes it hard to avoid this global. */
> static struct device *artpec6_crypto_dev;
> 
> -static struct dentry *dbgfs_root;
> -
> #ifdef CONFIG_FAULT_INJECTION
> static DECLARE_FAULT_ATTR(artpec6_crypto_fail_status_read);
> static DECLARE_FAULT_ATTR(artpec6_crypto_fail_dma_array_full);
> @@ -2984,6 +2982,8 @@ struct dbgfs_u32 {
>   char *desc;
> };
> 
> +static struct dentry *dbgfs_root;
> +
> static void artpec6_crypto_init_debugfs(void)
> {
>   dbgfs_root = debugfs_create_dir("artpec6_crypto", NULL);
> -- 
> 2.9.0
Acked-by: Lars Persson 

Thanks,
 Lars

Re: [PATCH v4 2/4] crypto: add crypto_(un)register_ahashes()

[Lars Persson]

On 08/10/2017 02:53 PM, Lars Persson wrote:

From: Rabin Vincent <rab...@axis.com>

There are already helpers to (un)register multiple normal
and AEAD algos.  Add one for ahashes too.

Signed-off-by: Lars Persson <lar...@axis.com>
Signed-off-by: Rabin Vincent <rab...@axis.com>
---
v4: crypto_register_skciphers was used where crypto_unregister_skciphers
 was intended.



The v4 change comment above in fact belongs to patch 3/4 of this series. 
Sorry for the confusion.


BR,
 Lars

Re: [PATCH v4 2/4] crypto: add crypto_(un)register_ahashes()

[Lars Persson]

On 08/10/2017 02:53 PM, Lars Persson wrote:

From: Rabin Vincent 

There are already helpers to (un)register multiple normal
and AEAD algos.  Add one for ahashes too.

Signed-off-by: Lars Persson 
Signed-off-by: Rabin Vincent 
---
v4: crypto_register_skciphers was used where crypto_unregister_skciphers
 was intended.



The v4 change comment above in fact belongs to patch 3/4 of this series. 
Sorry for the confusion.


BR,
 Lars

[PATCH v4 4/4] MAINTAINERS: Add ARTPEC crypto maintainer

[Lars Persson]

Assign the Axis kernel team as maintainer for crypto drivers under
drivers/crypto/axis.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d5b6c71e783e..72186cf9820d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1129,6 +1129,7 @@ L:linux-arm-ker...@axis.com
 F: arch/arm/mach-artpec
 F: arch/arm/boot/dts/artpec6*
 F: drivers/clk/axis
+F: drivers/crypto/axis
 F: drivers/pinctrl/pinctrl-artpec*
 F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
 
-- 
2.11.0

[PATCH v4 4/4] MAINTAINERS: Add ARTPEC crypto maintainer

[Lars Persson]

Assign the Axis kernel team as maintainer for crypto drivers under
drivers/crypto/axis.

Signed-off-by: Lars Persson 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d5b6c71e783e..72186cf9820d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1129,6 +1129,7 @@ L:linux-arm-ker...@axis.com
 F: arch/arm/mach-artpec
 F: arch/arm/boot/dts/artpec6*
 F: drivers/clk/axis
+F: drivers/crypto/axis
 F: drivers/pinctrl/pinctrl-artpec*
 F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
 
-- 
2.11.0

[PATCH v4 2/4] crypto: add crypto_(un)register_ahashes()

[Lars Persson]

From: Rabin Vincent <rab...@axis.com>

There are already helpers to (un)register multiple normal
and AEAD algos.  Add one for ahashes too.

Signed-off-by: Lars Persson <lar...@axis.com>
Signed-off-by: Rabin Vincent <rab...@axis.com>
---
v4: crypto_register_skciphers was used where crypto_unregister_skciphers
was intended.

 crypto/ahash.c | 29 +
 include/crypto/internal/hash.h |  2 ++
 2 files changed, 31 insertions(+)

diff --git a/crypto/ahash.c b/crypto/ahash.c
index 826cd7ab4d4a..5e8666e6ccae 100644
--- a/crypto/ahash.c
+++ b/crypto/ahash.c
@@ -588,6 +588,35 @@ int crypto_unregister_ahash(struct ahash_alg *alg)
 }
 EXPORT_SYMBOL_GPL(crypto_unregister_ahash);
 
+int crypto_register_ahashes(struct ahash_alg *algs, int count)
+{
+   int i, ret;
+
+   for (i = 0; i < count; i++) {
+   ret = crypto_register_ahash([i]);
+   if (ret)
+   goto err;
+   }
+
+   return 0;
+
+err:
+   for (--i; i >= 0; --i)
+   crypto_unregister_ahash([i]);
+
+   return ret;
+}
+EXPORT_SYMBOL_GPL(crypto_register_ahashes);
+
+void crypto_unregister_ahashes(struct ahash_alg *algs, int count)
+{
+   int i;
+
+   for (i = count - 1; i >= 0; --i)
+   crypto_unregister_ahash([i]);
+}
+EXPORT_SYMBOL_GPL(crypto_unregister_ahashes);
+
 int ahash_register_instance(struct crypto_template *tmpl,
struct ahash_instance *inst)
 {
diff --git a/include/crypto/internal/hash.h b/include/crypto/internal/hash.h
index f6d9af3efa45..f0b44c16e88f 100644
--- a/include/crypto/internal/hash.h
+++ b/include/crypto/internal/hash.h
@@ -76,6 +76,8 @@ static inline int crypto_ahash_walk_last(struct 
crypto_hash_walk *walk)
 
 int crypto_register_ahash(struct ahash_alg *alg);
 int crypto_unregister_ahash(struct ahash_alg *alg);
+int crypto_register_ahashes(struct ahash_alg *algs, int count);
+void crypto_unregister_ahashes(struct ahash_alg *algs, int count);
 int ahash_register_instance(struct crypto_template *tmpl,
struct ahash_instance *inst);
 void ahash_free_instance(struct crypto_instance *inst);
-- 
2.11.0

[PATCH v4 2/4] crypto: add crypto_(un)register_ahashes()

[Lars Persson]

From: Rabin Vincent 

There are already helpers to (un)register multiple normal
and AEAD algos.  Add one for ahashes too.

Signed-off-by: Lars Persson 
Signed-off-by: Rabin Vincent 
---
v4: crypto_register_skciphers was used where crypto_unregister_skciphers
was intended.

 crypto/ahash.c | 29 +
 include/crypto/internal/hash.h |  2 ++
 2 files changed, 31 insertions(+)

diff --git a/crypto/ahash.c b/crypto/ahash.c
index 826cd7ab4d4a..5e8666e6ccae 100644
--- a/crypto/ahash.c
+++ b/crypto/ahash.c
@@ -588,6 +588,35 @@ int crypto_unregister_ahash(struct ahash_alg *alg)
 }
 EXPORT_SYMBOL_GPL(crypto_unregister_ahash);
 
+int crypto_register_ahashes(struct ahash_alg *algs, int count)
+{
+   int i, ret;
+
+   for (i = 0; i < count; i++) {
+   ret = crypto_register_ahash([i]);
+   if (ret)
+   goto err;
+   }
+
+   return 0;
+
+err:
+   for (--i; i >= 0; --i)
+   crypto_unregister_ahash([i]);
+
+   return ret;
+}
+EXPORT_SYMBOL_GPL(crypto_register_ahashes);
+
+void crypto_unregister_ahashes(struct ahash_alg *algs, int count)
+{
+   int i;
+
+   for (i = count - 1; i >= 0; --i)
+   crypto_unregister_ahash([i]);
+}
+EXPORT_SYMBOL_GPL(crypto_unregister_ahashes);
+
 int ahash_register_instance(struct crypto_template *tmpl,
struct ahash_instance *inst)
 {
diff --git a/include/crypto/internal/hash.h b/include/crypto/internal/hash.h
index f6d9af3efa45..f0b44c16e88f 100644
--- a/include/crypto/internal/hash.h
+++ b/include/crypto/internal/hash.h
@@ -76,6 +76,8 @@ static inline int crypto_ahash_walk_last(struct 
crypto_hash_walk *walk)
 
 int crypto_register_ahash(struct ahash_alg *alg);
 int crypto_unregister_ahash(struct ahash_alg *alg);
+int crypto_register_ahashes(struct ahash_alg *algs, int count);
+void crypto_unregister_ahashes(struct ahash_alg *algs, int count);
 int ahash_register_instance(struct crypto_template *tmpl,
struct ahash_instance *inst);
 void ahash_free_instance(struct crypto_instance *inst);
-- 
2.11.0

[PATCH v4 1/4] dt-bindings: crypto: add ARTPEC crypto

[Lars Persson]

Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.

Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Lars Persson <lar...@axis.com>
---
 .../devicetree/bindings/crypto/artpec6-crypto.txt| 16 
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt

diff --git a/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt 
b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
new file mode 100644
index ..d9cca4875bd6
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
@@ -0,0 +1,16 @@
+Axis crypto engine with PDMA interface.
+
+Required properties:
+- compatible : Should be one of the following strings:
+   "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
+   "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
+- reg: Base address and size for the PDMA register area.
+- interrupts: Interrupt handle for the PDMA interrupt line.
+
+Example:
+
+crypto@f4264000 {
+   compatible = "axis,artpec6-crypto";
+   reg = <0xf4264000 0x1000>;
+   interrupts = ;
+};
-- 
2.11.0

[PATCH v4 1/4] dt-bindings: crypto: add ARTPEC crypto

[Lars Persson]

Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.

Acked-by: Rob Herring 
Signed-off-by: Lars Persson 
---
 .../devicetree/bindings/crypto/artpec6-crypto.txt| 16 
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt

diff --git a/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt 
b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
new file mode 100644
index ..d9cca4875bd6
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
@@ -0,0 +1,16 @@
+Axis crypto engine with PDMA interface.
+
+Required properties:
+- compatible : Should be one of the following strings:
+   "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
+   "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
+- reg: Base address and size for the PDMA register area.
+- interrupts: Interrupt handle for the PDMA interrupt line.
+
+Example:
+
+crypto@f4264000 {
+   compatible = "axis,artpec6-crypto";
+   reg = <0xf4264000 0x1000>;
+   interrupts = ;
+};
-- 
2.11.0

[PATCH v4 3/4] crypto: axis: add ARTPEC-6/7 crypto accelerator driver

[Lars Persson]

This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.

The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 drivers/crypto/Kconfig   |   21 +
 drivers/crypto/Makefile  |1 +
 drivers/crypto/axis/Makefile |1 +
 drivers/crypto/axis/artpec6_crypto.c | 3192 ++
 4 files changed, 3215 insertions(+)
 create mode 100644 drivers/crypto/axis/Makefile
 create mode 100644 drivers/crypto/axis/artpec6_crypto.c

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 5b5393f1b87a..fe33c199fc1a 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -708,4 +708,25 @@ config CRYPTO_DEV_SAFEXCEL
  chain mode, AES cipher mode and SHA1/SHA224/SHA256/SHA512 hash
  algorithms.
 
+config CRYPTO_DEV_ARTPEC6
+   tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
+   depends on ARM && (ARCH_ARTPEC || COMPILE_TEST)
+   depends on HAS_DMA
+   depends on OF
+   select CRYPTO_AEAD
+   select CRYPTO_AES
+   select CRYPTO_ALGAPI
+   select CRYPTO_BLKCIPHER
+   select CRYPTO_CTR
+   select CRYPTO_HASH
+   select CRYPTO_SHA1
+   select CRYPTO_SHA256
+   select CRYPTO_SHA384
+   select CRYPTO_SHA512
+   help
+ Enables the driver for the on-chip crypto accelerator
+ of Axis ARTPEC SoCs.
+
+ To compile this driver as a module, choose M here.
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index de629165fde7..7bf0997eae25 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
 obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
 obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
 obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
+obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
diff --git a/drivers/crypto/axis/Makefile b/drivers/crypto/axis/Makefile
new file mode 100644
index ..be9a84a4b667
--- /dev/null
+++ b/drivers/crypto/axis/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) := artpec6_crypto.o
diff --git a/drivers/crypto/axis/artpec6_crypto.c 
b/drivers/crypto/axis/artpec6_crypto.c
new file mode 100644
index ..d9fbbf01062b
--- /dev/null
+++ b/drivers/crypto/axis/artpec6_crypto.c
@@ -0,0 +1,3192 @@
+/*
+ *   Driver for ARTPEC-6 crypto block using the kernel asynchronous crypto api.
+ *
+ *Copyright (C) 2014-2017  Axis Communications AB
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Max length of a line in all cache levels for Artpec SoCs. */
+#define ARTPEC_CACHE_LINE_MAX  32
+
+#define PDMA_OUT_CFG   0x
+#define PDMA_OUT_BUF_CFG   0x0004
+#define PDMA_OUT_CMD   0x0008
+#define PDMA_OUT_DESCRQ_PUSH   0x0010
+#define PDMA_OUT_DESCRQ_STAT   0x0014
+
+#define A6_PDMA_IN_CFG 0x0028
+#define A6_PDMA_IN_BUF_CFG 0x002c
+#define A6_PDMA_IN_CMD 0x0030
+#define A6_PDMA_IN_STATQ_PUSH  0x0038
+#define A6_PDMA_IN_DESCRQ_PUSH 0x0044
+#define A6_PDMA_IN_DESCRQ_STAT 0x0048
+#define A6_PDMA_INTR_MASK  0x0068
+#define A6_PDMA_ACK_INTR   0x006c
+#define A6_PDMA_MASKED_INTR0x0074
+
+#define A7_PDMA_IN_CFG 0x002c
+#define A7_PDMA_IN_BUF_CFG 0x0030
+#define A7_PDMA_IN_CMD 0x0034
+#define A7_PDMA_IN_STATQ_PUSH  0x003c
+#define A7_PDMA_IN_DESCRQ_PUSH 0x0048
+#define A7_PDMA_IN_DESCRQ_STAT 0x004C
+#define A7_PDMA_INTR_MASK  0x006c
+#define A7_PDMA_ACK_INTR   0x0070
+#define A7_PDMA_MASKED_INTR0x0078
+
+#define PDMA_OUT_CFG_ENBIT(0)
+
+#define PDMA_OUT_BUF_CFG_DATA_BUF_SIZE GENMASK(4, 0)
+#define PDMA_OUT_BUF_CFG_DESCR_BUF_SIZEGENMASK(9, 5)
+
+#define PDMA_OUT_CMD_START BIT(0)
+#define A6_PDMA_OUT_CMD_STOP   BIT(3)
+#define A7_PDMA_OUT_CMD_STOP   BIT(2)
+
+#define PDMA_OUT_DESCRQ_PUSH_LEN   GENMASK(5, 0)
+#define PDMA_OUT_DESCRQ_PUSH_ADDR  GENMASK(31, 6)
+
+#define PDMA_OUT_DESCRQ_STAT_LEVEL GENMASK(3, 0)
+#define PDMA_OUT_DESCRQ_STAT_SIZE  GENMASK(7, 4)
+
+#define PDMA_IN_CFG_EN BIT(0)
+
+#define PDMA_IN_BUF_CFG_DATA_BUF_SIZE  GENMASK(4, 0)
+#define PDMA_IN_BUF_CFG_DESCR_BUF_SIZE GENMASK(9, 5)
+#define PDMA_IN_BUF_CFG_STAT_BUF_SIZE  GENMASK(14, 10)
+
+#define PDMA_IN_CMD_START  BIT(0)
+#define A6_PDMA_IN_CMD_FLUSH_STAT  BIT(2)
+#define A6_PDMA_IN_CMD_STOPBIT(3)

[PATCH v4 3/4] crypto: axis: add ARTPEC-6/7 crypto accelerator driver

[Lars Persson]

This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.

The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.

Signed-off-by: Lars Persson 
---
 drivers/crypto/Kconfig   |   21 +
 drivers/crypto/Makefile  |1 +
 drivers/crypto/axis/Makefile |1 +
 drivers/crypto/axis/artpec6_crypto.c | 3192 ++
 4 files changed, 3215 insertions(+)
 create mode 100644 drivers/crypto/axis/Makefile
 create mode 100644 drivers/crypto/axis/artpec6_crypto.c

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 5b5393f1b87a..fe33c199fc1a 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -708,4 +708,25 @@ config CRYPTO_DEV_SAFEXCEL
  chain mode, AES cipher mode and SHA1/SHA224/SHA256/SHA512 hash
  algorithms.
 
+config CRYPTO_DEV_ARTPEC6
+   tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
+   depends on ARM && (ARCH_ARTPEC || COMPILE_TEST)
+   depends on HAS_DMA
+   depends on OF
+   select CRYPTO_AEAD
+   select CRYPTO_AES
+   select CRYPTO_ALGAPI
+   select CRYPTO_BLKCIPHER
+   select CRYPTO_CTR
+   select CRYPTO_HASH
+   select CRYPTO_SHA1
+   select CRYPTO_SHA256
+   select CRYPTO_SHA384
+   select CRYPTO_SHA512
+   help
+ Enables the driver for the on-chip crypto accelerator
+ of Axis ARTPEC SoCs.
+
+ To compile this driver as a module, choose M here.
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index de629165fde7..7bf0997eae25 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
 obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
 obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
 obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
+obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
diff --git a/drivers/crypto/axis/Makefile b/drivers/crypto/axis/Makefile
new file mode 100644
index ..be9a84a4b667
--- /dev/null
+++ b/drivers/crypto/axis/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) := artpec6_crypto.o
diff --git a/drivers/crypto/axis/artpec6_crypto.c 
b/drivers/crypto/axis/artpec6_crypto.c
new file mode 100644
index ..d9fbbf01062b
--- /dev/null
+++ b/drivers/crypto/axis/artpec6_crypto.c
@@ -0,0 +1,3192 @@
+/*
+ *   Driver for ARTPEC-6 crypto block using the kernel asynchronous crypto api.
+ *
+ *Copyright (C) 2014-2017  Axis Communications AB
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Max length of a line in all cache levels for Artpec SoCs. */
+#define ARTPEC_CACHE_LINE_MAX  32
+
+#define PDMA_OUT_CFG   0x
+#define PDMA_OUT_BUF_CFG   0x0004
+#define PDMA_OUT_CMD   0x0008
+#define PDMA_OUT_DESCRQ_PUSH   0x0010
+#define PDMA_OUT_DESCRQ_STAT   0x0014
+
+#define A6_PDMA_IN_CFG 0x0028
+#define A6_PDMA_IN_BUF_CFG 0x002c
+#define A6_PDMA_IN_CMD 0x0030
+#define A6_PDMA_IN_STATQ_PUSH  0x0038
+#define A6_PDMA_IN_DESCRQ_PUSH 0x0044
+#define A6_PDMA_IN_DESCRQ_STAT 0x0048
+#define A6_PDMA_INTR_MASK  0x0068
+#define A6_PDMA_ACK_INTR   0x006c
+#define A6_PDMA_MASKED_INTR0x0074
+
+#define A7_PDMA_IN_CFG 0x002c
+#define A7_PDMA_IN_BUF_CFG 0x0030
+#define A7_PDMA_IN_CMD 0x0034
+#define A7_PDMA_IN_STATQ_PUSH  0x003c
+#define A7_PDMA_IN_DESCRQ_PUSH 0x0048
+#define A7_PDMA_IN_DESCRQ_STAT 0x004C
+#define A7_PDMA_INTR_MASK  0x006c
+#define A7_PDMA_ACK_INTR   0x0070
+#define A7_PDMA_MASKED_INTR0x0078
+
+#define PDMA_OUT_CFG_ENBIT(0)
+
+#define PDMA_OUT_BUF_CFG_DATA_BUF_SIZE GENMASK(4, 0)
+#define PDMA_OUT_BUF_CFG_DESCR_BUF_SIZEGENMASK(9, 5)
+
+#define PDMA_OUT_CMD_START BIT(0)
+#define A6_PDMA_OUT_CMD_STOP   BIT(3)
+#define A7_PDMA_OUT_CMD_STOP   BIT(2)
+
+#define PDMA_OUT_DESCRQ_PUSH_LEN   GENMASK(5, 0)
+#define PDMA_OUT_DESCRQ_PUSH_ADDR  GENMASK(31, 6)
+
+#define PDMA_OUT_DESCRQ_STAT_LEVEL GENMASK(3, 0)
+#define PDMA_OUT_DESCRQ_STAT_SIZE  GENMASK(7, 4)
+
+#define PDMA_IN_CFG_EN BIT(0)
+
+#define PDMA_IN_BUF_CFG_DATA_BUF_SIZE  GENMASK(4, 0)
+#define PDMA_IN_BUF_CFG_DESCR_BUF_SIZE GENMASK(9, 5)
+#define PDMA_IN_BUF_CFG_STAT_BUF_SIZE  GENMASK(14, 10)
+
+#define PDMA_IN_CMD_START  BIT(0)
+#define A6_PDMA_IN_CMD_FLUSH_STAT  BIT(2)
+#define A6_PDMA_IN_CMD_STOPBIT(3)
+#define A7_PDMA_IN_CMD_F

[PATCH v4 0/4] crypto: add driver for Axis ARTPEC crypto accelerator

[Lars Persson]

This series adds a driver for the crypto accelerator in the ARTPEC series of
SoCs from Axis Communications AB.

Changelog v4:
- The skcipher conversion had a mistake where the algos were registered
  instead of unregistered at module unloading.

Changelog v3:
- The patch author added his Signed-off-by on patch 2.

Changelog v2:
- Use xts_check_key() for xts keys.
- Use CRYPTO_ALG_TYPE_SKCIPHER instead of CRYPTO_ALG_TYPE_ABLKCIPHER
  in cra_flags.

Lars Persson (3):
  dt-bindings: crypto: add ARTPEC crypto
  crypto: axis: add ARTPEC-6/7 crypto accelerator driver
  MAINTAINERS: Add ARTPEC crypto maintainer

Rabin Vincent (1):
  crypto: add crypto_(un)register_ahashes()

 .../devicetree/bindings/crypto/artpec6-crypto.txt  |   16 +
 MAINTAINERS|1 +
 crypto/ahash.c |   29 +
 drivers/crypto/Kconfig |   21 +
 drivers/crypto/Makefile|1 +
 drivers/crypto/axis/Makefile   |1 +
 drivers/crypto/axis/artpec6_crypto.c   | 3192 
 include/crypto/internal/hash.h |2 +
 8 files changed, 3263 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
 create mode 100644 drivers/crypto/axis/Makefile
 create mode 100644 drivers/crypto/axis/artpec6_crypto.c

-- 
2.11.0

[PATCH v4 0/4] crypto: add driver for Axis ARTPEC crypto accelerator

[Lars Persson]

This series adds a driver for the crypto accelerator in the ARTPEC series of
SoCs from Axis Communications AB.

Changelog v4:
- The skcipher conversion had a mistake where the algos were registered
  instead of unregistered at module unloading.

Changelog v3:
- The patch author added his Signed-off-by on patch 2.

Changelog v2:
- Use xts_check_key() for xts keys.
- Use CRYPTO_ALG_TYPE_SKCIPHER instead of CRYPTO_ALG_TYPE_ABLKCIPHER
  in cra_flags.

Lars Persson (3):
  dt-bindings: crypto: add ARTPEC crypto
  crypto: axis: add ARTPEC-6/7 crypto accelerator driver
  MAINTAINERS: Add ARTPEC crypto maintainer

Rabin Vincent (1):
  crypto: add crypto_(un)register_ahashes()

 .../devicetree/bindings/crypto/artpec6-crypto.txt  |   16 +
 MAINTAINERS|1 +
 crypto/ahash.c |   29 +
 drivers/crypto/Kconfig |   21 +
 drivers/crypto/Makefile|1 +
 drivers/crypto/axis/Makefile   |1 +
 drivers/crypto/axis/artpec6_crypto.c   | 3192 
 include/crypto/internal/hash.h |2 +
 8 files changed, 3263 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
 create mode 100644 drivers/crypto/axis/Makefile
 create mode 100644 drivers/crypto/axis/artpec6_crypto.c

-- 
2.11.0

Re: [PATCH 02/17] pinctrl: artpec6: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures

[Lars Persson]

On 08/10/2017 12:06 PM, Julia Lawall wrote:

This pinctrl_ops structure is only stored in the const pctlops
field of a pinctrl_desc structure. Make the pinctrl_ops structure
const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall <julia.law...@lip6.fr>

---
  drivers/pinctrl/pinctrl-artpec6.c |2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 


Hi,

Acked-by: Lars Persson <lars.pers...@axis.com>

BR,
 Lars

Re: [PATCH 02/17] pinctrl: artpec6: constify pinconf_ops, pinctrl_ops, and pinmux_ops structures

[Lars Persson]

On 08/10/2017 12:06 PM, Julia Lawall wrote:

This pinctrl_ops structure is only stored in the const pctlops
field of a pinctrl_desc structure. Make the pinctrl_ops structure
const as well.

Done with the help of Coccinelle.

Signed-off-by: Julia Lawall 

---
  drivers/pinctrl/pinctrl-artpec6.c |2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 


Hi,

Acked-by: Lars Persson 

BR,
 Lars

Re: linux-next: Signed-off-by missing for commit in the crypto tree

[Lars Persson]

On 08/04/2017 03:29 AM, Herbert Xu wrote:

On Fri, Aug 04, 2017 at 07:50:22AM +1000, Stephen Rothwell wrote:

Hi all,

Commit

   9577212cc0e2 ("crypto: hash - add crypto_(un)register_ahashes()")

is missing a Signed-off-by from its author.


OK, I've backed out the patches in question.  Please resubmit
with a sign-off.  Thanks!



Sorry for missing this. We fixed it in patch set v3.

BR,
 Lars Persson

Re: linux-next: Signed-off-by missing for commit in the crypto tree

[Lars Persson]

On 08/04/2017 03:29 AM, Herbert Xu wrote:

On Fri, Aug 04, 2017 at 07:50:22AM +1000, Stephen Rothwell wrote:

Hi all,

Commit

   9577212cc0e2 ("crypto: hash - add crypto_(un)register_ahashes()")

is missing a Signed-off-by from its author.


OK, I've backed out the patches in question.  Please resubmit
with a sign-off.  Thanks!



Sorry for missing this. We fixed it in patch set v3.

BR,
 Lars Persson

[PATCH v3 4/4] MAINTAINERS: Add ARTPEC crypto maintainer

[Lars Persson]

Assign the Axis kernel team as maintainer for crypto drivers under
drivers/crypto/axis.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d5b6c71e783e..72186cf9820d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1129,6 +1129,7 @@ L:linux-arm-ker...@axis.com
 F: arch/arm/mach-artpec
 F: arch/arm/boot/dts/artpec6*
 F: drivers/clk/axis
+F: drivers/crypto/axis
 F: drivers/pinctrl/pinctrl-artpec*
 F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
 
-- 
2.11.0

[PATCH v3 4/4] MAINTAINERS: Add ARTPEC crypto maintainer

[Lars Persson]

Assign the Axis kernel team as maintainer for crypto drivers under
drivers/crypto/axis.

Signed-off-by: Lars Persson 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d5b6c71e783e..72186cf9820d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1129,6 +1129,7 @@ L:linux-arm-ker...@axis.com
 F: arch/arm/mach-artpec
 F: arch/arm/boot/dts/artpec6*
 F: drivers/clk/axis
+F: drivers/crypto/axis
 F: drivers/pinctrl/pinctrl-artpec*
 F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
 
-- 
2.11.0

[PATCH v3 0/4] crypto: add driver for Axis ARTPEC crypto accelerator

[Lars Persson]

This series adds a driver for the crypto accelerator in the ARTPEC series of
SoCs from Axis Communications AB.

Changelog v3:
- The patch author added his Signed-off-by on patch 2.

Changelog v2:
- Use xts_check_key() for xts keys.
- Use CRYPTO_ALG_TYPE_SKCIPHER instead of CRYPTO_ALG_TYPE_ABLKCIPHER
  in cra_flags.

Lars Persson (3):
  dt-bindings: crypto: add ARTPEC crypto
  crypto: axis: add ARTPEC-6/7 crypto accelerator driver
  MAINTAINERS: Add ARTPEC crypto maintainer

Rabin Vincent (1):
  crypto: add crypto_(un)register_ahashes()

 .../devicetree/bindings/crypto/artpec6-crypto.txt  |   16 +
 MAINTAINERS|1 +
 crypto/ahash.c |   29 +
 drivers/crypto/Kconfig |   21 +
 drivers/crypto/Makefile|1 +
 drivers/crypto/axis/Makefile   |1 +
 drivers/crypto/axis/artpec6_crypto.c   | 3193 
 include/crypto/internal/hash.h |2 +
 8 files changed, 3264 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
 create mode 100644 drivers/crypto/axis/Makefile
 create mode 100644 drivers/crypto/axis/artpec6_crypto.c

-- 
2.11.0

[PATCH v3 0/4] crypto: add driver for Axis ARTPEC crypto accelerator

[Lars Persson]

This series adds a driver for the crypto accelerator in the ARTPEC series of
SoCs from Axis Communications AB.

Changelog v3:
- The patch author added his Signed-off-by on patch 2.

Changelog v2:
- Use xts_check_key() for xts keys.
- Use CRYPTO_ALG_TYPE_SKCIPHER instead of CRYPTO_ALG_TYPE_ABLKCIPHER
  in cra_flags.

Lars Persson (3):
  dt-bindings: crypto: add ARTPEC crypto
  crypto: axis: add ARTPEC-6/7 crypto accelerator driver
  MAINTAINERS: Add ARTPEC crypto maintainer

Rabin Vincent (1):
  crypto: add crypto_(un)register_ahashes()

 .../devicetree/bindings/crypto/artpec6-crypto.txt  |   16 +
 MAINTAINERS|1 +
 crypto/ahash.c |   29 +
 drivers/crypto/Kconfig |   21 +
 drivers/crypto/Makefile|1 +
 drivers/crypto/axis/Makefile   |1 +
 drivers/crypto/axis/artpec6_crypto.c   | 3193 
 include/crypto/internal/hash.h |2 +
 8 files changed, 3264 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
 create mode 100644 drivers/crypto/axis/Makefile
 create mode 100644 drivers/crypto/axis/artpec6_crypto.c

-- 
2.11.0

[PATCH v3 2/4] crypto: add crypto_(un)register_ahashes()

[Lars Persson]

From: Rabin Vincent <rab...@axis.com>

There are already helpers to (un)register multiple normal
and AEAD algos.  Add one for ahashes too.

Signed-off-by: Lars Persson <lar...@axis.com>
Signed-off-by: Rabin Vincent <rab...@axis.com>
---
 crypto/ahash.c | 29 +
 include/crypto/internal/hash.h |  2 ++
 2 files changed, 31 insertions(+)

diff --git a/crypto/ahash.c b/crypto/ahash.c
index 826cd7ab4d4a..5e8666e6ccae 100644
--- a/crypto/ahash.c
+++ b/crypto/ahash.c
@@ -588,6 +588,35 @@ int crypto_unregister_ahash(struct ahash_alg *alg)
 }
 EXPORT_SYMBOL_GPL(crypto_unregister_ahash);
 
+int crypto_register_ahashes(struct ahash_alg *algs, int count)
+{
+   int i, ret;
+
+   for (i = 0; i < count; i++) {
+   ret = crypto_register_ahash([i]);
+   if (ret)
+   goto err;
+   }
+
+   return 0;
+
+err:
+   for (--i; i >= 0; --i)
+   crypto_unregister_ahash([i]);
+
+   return ret;
+}
+EXPORT_SYMBOL_GPL(crypto_register_ahashes);
+
+void crypto_unregister_ahashes(struct ahash_alg *algs, int count)
+{
+   int i;
+
+   for (i = count - 1; i >= 0; --i)
+   crypto_unregister_ahash([i]);
+}
+EXPORT_SYMBOL_GPL(crypto_unregister_ahashes);
+
 int ahash_register_instance(struct crypto_template *tmpl,
struct ahash_instance *inst)
 {
diff --git a/include/crypto/internal/hash.h b/include/crypto/internal/hash.h
index f6d9af3efa45..f0b44c16e88f 100644
--- a/include/crypto/internal/hash.h
+++ b/include/crypto/internal/hash.h
@@ -76,6 +76,8 @@ static inline int crypto_ahash_walk_last(struct 
crypto_hash_walk *walk)
 
 int crypto_register_ahash(struct ahash_alg *alg);
 int crypto_unregister_ahash(struct ahash_alg *alg);
+int crypto_register_ahashes(struct ahash_alg *algs, int count);
+void crypto_unregister_ahashes(struct ahash_alg *algs, int count);
 int ahash_register_instance(struct crypto_template *tmpl,
struct ahash_instance *inst);
 void ahash_free_instance(struct crypto_instance *inst);
-- 
2.11.0

[PATCH v3 2/4] crypto: add crypto_(un)register_ahashes()

[Lars Persson]

From: Rabin Vincent 

There are already helpers to (un)register multiple normal
and AEAD algos.  Add one for ahashes too.

Signed-off-by: Lars Persson 
Signed-off-by: Rabin Vincent 
---
 crypto/ahash.c | 29 +
 include/crypto/internal/hash.h |  2 ++
 2 files changed, 31 insertions(+)

diff --git a/crypto/ahash.c b/crypto/ahash.c
index 826cd7ab4d4a..5e8666e6ccae 100644
--- a/crypto/ahash.c
+++ b/crypto/ahash.c
@@ -588,6 +588,35 @@ int crypto_unregister_ahash(struct ahash_alg *alg)
 }
 EXPORT_SYMBOL_GPL(crypto_unregister_ahash);
 
+int crypto_register_ahashes(struct ahash_alg *algs, int count)
+{
+   int i, ret;
+
+   for (i = 0; i < count; i++) {
+   ret = crypto_register_ahash([i]);
+   if (ret)
+   goto err;
+   }
+
+   return 0;
+
+err:
+   for (--i; i >= 0; --i)
+   crypto_unregister_ahash([i]);
+
+   return ret;
+}
+EXPORT_SYMBOL_GPL(crypto_register_ahashes);
+
+void crypto_unregister_ahashes(struct ahash_alg *algs, int count)
+{
+   int i;
+
+   for (i = count - 1; i >= 0; --i)
+   crypto_unregister_ahash([i]);
+}
+EXPORT_SYMBOL_GPL(crypto_unregister_ahashes);
+
 int ahash_register_instance(struct crypto_template *tmpl,
struct ahash_instance *inst)
 {
diff --git a/include/crypto/internal/hash.h b/include/crypto/internal/hash.h
index f6d9af3efa45..f0b44c16e88f 100644
--- a/include/crypto/internal/hash.h
+++ b/include/crypto/internal/hash.h
@@ -76,6 +76,8 @@ static inline int crypto_ahash_walk_last(struct 
crypto_hash_walk *walk)
 
 int crypto_register_ahash(struct ahash_alg *alg);
 int crypto_unregister_ahash(struct ahash_alg *alg);
+int crypto_register_ahashes(struct ahash_alg *algs, int count);
+void crypto_unregister_ahashes(struct ahash_alg *algs, int count);
 int ahash_register_instance(struct crypto_template *tmpl,
struct ahash_instance *inst);
 void ahash_free_instance(struct crypto_instance *inst);
-- 
2.11.0

[PATCH v3 3/4] crypto: axis: add ARTPEC-6/7 crypto accelerator driver

[Lars Persson]

This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.

The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 drivers/crypto/Kconfig   |   21 +
 drivers/crypto/Makefile  |1 +
 drivers/crypto/axis/Makefile |1 +
 drivers/crypto/axis/artpec6_crypto.c | 3193 ++
 4 files changed, 3216 insertions(+)
 create mode 100644 drivers/crypto/axis/Makefile
 create mode 100644 drivers/crypto/axis/artpec6_crypto.c

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 5b5393f1b87a..fe33c199fc1a 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -708,4 +708,25 @@ config CRYPTO_DEV_SAFEXCEL
  chain mode, AES cipher mode and SHA1/SHA224/SHA256/SHA512 hash
  algorithms.
 
+config CRYPTO_DEV_ARTPEC6
+   tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
+   depends on ARM && (ARCH_ARTPEC || COMPILE_TEST)
+   depends on HAS_DMA
+   depends on OF
+   select CRYPTO_AEAD
+   select CRYPTO_AES
+   select CRYPTO_ALGAPI
+   select CRYPTO_BLKCIPHER
+   select CRYPTO_CTR
+   select CRYPTO_HASH
+   select CRYPTO_SHA1
+   select CRYPTO_SHA256
+   select CRYPTO_SHA384
+   select CRYPTO_SHA512
+   help
+ Enables the driver for the on-chip crypto accelerator
+ of Axis ARTPEC SoCs.
+
+ To compile this driver as a module, choose M here.
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index de629165fde7..7bf0997eae25 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
 obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
 obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
 obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
+obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
diff --git a/drivers/crypto/axis/Makefile b/drivers/crypto/axis/Makefile
new file mode 100644
index ..be9a84a4b667
--- /dev/null
+++ b/drivers/crypto/axis/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) := artpec6_crypto.o
diff --git a/drivers/crypto/axis/artpec6_crypto.c 
b/drivers/crypto/axis/artpec6_crypto.c
new file mode 100644
index ..72ce5acf9a24
--- /dev/null
+++ b/drivers/crypto/axis/artpec6_crypto.c
@@ -0,0 +1,3193 @@
+/*
+ *   Driver for ARTPEC-6 crypto block using the kernel asynchronous crypto api.
+ *
+ *Copyright (C) 2014-2017  Axis Communications AB
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Max length of a line in all cache levels for Artpec SoCs. */
+#define ARTPEC_CACHE_LINE_MAX  32
+
+#define PDMA_OUT_CFG   0x
+#define PDMA_OUT_BUF_CFG   0x0004
+#define PDMA_OUT_CMD   0x0008
+#define PDMA_OUT_DESCRQ_PUSH   0x0010
+#define PDMA_OUT_DESCRQ_STAT   0x0014
+
+#define A6_PDMA_IN_CFG 0x0028
+#define A6_PDMA_IN_BUF_CFG 0x002c
+#define A6_PDMA_IN_CMD 0x0030
+#define A6_PDMA_IN_STATQ_PUSH  0x0038
+#define A6_PDMA_IN_DESCRQ_PUSH 0x0044
+#define A6_PDMA_IN_DESCRQ_STAT 0x0048
+#define A6_PDMA_INTR_MASK  0x0068
+#define A6_PDMA_ACK_INTR   0x006c
+#define A6_PDMA_MASKED_INTR0x0074
+
+#define A7_PDMA_IN_CFG 0x002c
+#define A7_PDMA_IN_BUF_CFG 0x0030
+#define A7_PDMA_IN_CMD 0x0034
+#define A7_PDMA_IN_STATQ_PUSH  0x003c
+#define A7_PDMA_IN_DESCRQ_PUSH 0x0048
+#define A7_PDMA_IN_DESCRQ_STAT 0x004C
+#define A7_PDMA_INTR_MASK  0x006c
+#define A7_PDMA_ACK_INTR   0x0070
+#define A7_PDMA_MASKED_INTR0x0078
+
+#define PDMA_OUT_CFG_ENBIT(0)
+
+#define PDMA_OUT_BUF_CFG_DATA_BUF_SIZE GENMASK(4, 0)
+#define PDMA_OUT_BUF_CFG_DESCR_BUF_SIZEGENMASK(9, 5)
+
+#define PDMA_OUT_CMD_START BIT(0)
+#define A6_PDMA_OUT_CMD_STOP   BIT(3)
+#define A7_PDMA_OUT_CMD_STOP   BIT(2)
+
+#define PDMA_OUT_DESCRQ_PUSH_LEN   GENMASK(5, 0)
+#define PDMA_OUT_DESCRQ_PUSH_ADDR  GENMASK(31, 6)
+
+#define PDMA_OUT_DESCRQ_STAT_LEVEL GENMASK(3, 0)
+#define PDMA_OUT_DESCRQ_STAT_SIZE  GENMASK(7, 4)
+
+#define PDMA_IN_CFG_EN BIT(0)
+
+#define PDMA_IN_BUF_CFG_DATA_BUF_SIZE  GENMASK(4, 0)
+#define PDMA_IN_BUF_CFG_DESCR_BUF_SIZE GENMASK(9, 5)
+#define PDMA_IN_BUF_CFG_STAT_BUF_SIZE  GENMASK(14, 10)
+
+#define PDMA_IN_CMD_START  BIT(0)
+#define A6_PDMA_IN_CMD_FLUSH_STAT  BIT(2)
+#define A6_PDMA_IN_CMD_STOPBIT(3)

[PATCH v3 3/4] crypto: axis: add ARTPEC-6/7 crypto accelerator driver

[Lars Persson]

This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.

The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.

Signed-off-by: Lars Persson 
---
 drivers/crypto/Kconfig   |   21 +
 drivers/crypto/Makefile  |1 +
 drivers/crypto/axis/Makefile |1 +
 drivers/crypto/axis/artpec6_crypto.c | 3193 ++
 4 files changed, 3216 insertions(+)
 create mode 100644 drivers/crypto/axis/Makefile
 create mode 100644 drivers/crypto/axis/artpec6_crypto.c

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 5b5393f1b87a..fe33c199fc1a 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -708,4 +708,25 @@ config CRYPTO_DEV_SAFEXCEL
  chain mode, AES cipher mode and SHA1/SHA224/SHA256/SHA512 hash
  algorithms.
 
+config CRYPTO_DEV_ARTPEC6
+   tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
+   depends on ARM && (ARCH_ARTPEC || COMPILE_TEST)
+   depends on HAS_DMA
+   depends on OF
+   select CRYPTO_AEAD
+   select CRYPTO_AES
+   select CRYPTO_ALGAPI
+   select CRYPTO_BLKCIPHER
+   select CRYPTO_CTR
+   select CRYPTO_HASH
+   select CRYPTO_SHA1
+   select CRYPTO_SHA256
+   select CRYPTO_SHA384
+   select CRYPTO_SHA512
+   help
+ Enables the driver for the on-chip crypto accelerator
+ of Axis ARTPEC SoCs.
+
+ To compile this driver as a module, choose M here.
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index de629165fde7..7bf0997eae25 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
 obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
 obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
 obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
+obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
diff --git a/drivers/crypto/axis/Makefile b/drivers/crypto/axis/Makefile
new file mode 100644
index ..be9a84a4b667
--- /dev/null
+++ b/drivers/crypto/axis/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) := artpec6_crypto.o
diff --git a/drivers/crypto/axis/artpec6_crypto.c 
b/drivers/crypto/axis/artpec6_crypto.c
new file mode 100644
index ..72ce5acf9a24
--- /dev/null
+++ b/drivers/crypto/axis/artpec6_crypto.c
@@ -0,0 +1,3193 @@
+/*
+ *   Driver for ARTPEC-6 crypto block using the kernel asynchronous crypto api.
+ *
+ *Copyright (C) 2014-2017  Axis Communications AB
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Max length of a line in all cache levels for Artpec SoCs. */
+#define ARTPEC_CACHE_LINE_MAX  32
+
+#define PDMA_OUT_CFG   0x
+#define PDMA_OUT_BUF_CFG   0x0004
+#define PDMA_OUT_CMD   0x0008
+#define PDMA_OUT_DESCRQ_PUSH   0x0010
+#define PDMA_OUT_DESCRQ_STAT   0x0014
+
+#define A6_PDMA_IN_CFG 0x0028
+#define A6_PDMA_IN_BUF_CFG 0x002c
+#define A6_PDMA_IN_CMD 0x0030
+#define A6_PDMA_IN_STATQ_PUSH  0x0038
+#define A6_PDMA_IN_DESCRQ_PUSH 0x0044
+#define A6_PDMA_IN_DESCRQ_STAT 0x0048
+#define A6_PDMA_INTR_MASK  0x0068
+#define A6_PDMA_ACK_INTR   0x006c
+#define A6_PDMA_MASKED_INTR0x0074
+
+#define A7_PDMA_IN_CFG 0x002c
+#define A7_PDMA_IN_BUF_CFG 0x0030
+#define A7_PDMA_IN_CMD 0x0034
+#define A7_PDMA_IN_STATQ_PUSH  0x003c
+#define A7_PDMA_IN_DESCRQ_PUSH 0x0048
+#define A7_PDMA_IN_DESCRQ_STAT 0x004C
+#define A7_PDMA_INTR_MASK  0x006c
+#define A7_PDMA_ACK_INTR   0x0070
+#define A7_PDMA_MASKED_INTR0x0078
+
+#define PDMA_OUT_CFG_ENBIT(0)
+
+#define PDMA_OUT_BUF_CFG_DATA_BUF_SIZE GENMASK(4, 0)
+#define PDMA_OUT_BUF_CFG_DESCR_BUF_SIZEGENMASK(9, 5)
+
+#define PDMA_OUT_CMD_START BIT(0)
+#define A6_PDMA_OUT_CMD_STOP   BIT(3)
+#define A7_PDMA_OUT_CMD_STOP   BIT(2)
+
+#define PDMA_OUT_DESCRQ_PUSH_LEN   GENMASK(5, 0)
+#define PDMA_OUT_DESCRQ_PUSH_ADDR  GENMASK(31, 6)
+
+#define PDMA_OUT_DESCRQ_STAT_LEVEL GENMASK(3, 0)
+#define PDMA_OUT_DESCRQ_STAT_SIZE  GENMASK(7, 4)
+
+#define PDMA_IN_CFG_EN BIT(0)
+
+#define PDMA_IN_BUF_CFG_DATA_BUF_SIZE  GENMASK(4, 0)
+#define PDMA_IN_BUF_CFG_DESCR_BUF_SIZE GENMASK(9, 5)
+#define PDMA_IN_BUF_CFG_STAT_BUF_SIZE  GENMASK(14, 10)
+
+#define PDMA_IN_CMD_START  BIT(0)
+#define A6_PDMA_IN_CMD_FLUSH_STAT  BIT(2)
+#define A6_PDMA_IN_CMD_STOPBIT(3)
+#define A7_PDMA_IN_CMD_F

[PATCH v3 1/4] dt-bindings: crypto: add ARTPEC crypto

[Lars Persson]

Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 .../devicetree/bindings/crypto/artpec6-crypto.txt| 16 
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt

diff --git a/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt 
b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
new file mode 100644
index ..d9cca4875bd6
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
@@ -0,0 +1,16 @@
+Axis crypto engine with PDMA interface.
+
+Required properties:
+- compatible : Should be one of the following strings:
+   "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
+   "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
+- reg: Base address and size for the PDMA register area.
+- interrupts: Interrupt handle for the PDMA interrupt line.
+
+Example:
+
+crypto@f4264000 {
+   compatible = "axis,artpec6-crypto";
+   reg = <0xf4264000 0x1000>;
+   interrupts = ;
+};
-- 
2.11.0

[PATCH v3 1/4] dt-bindings: crypto: add ARTPEC crypto

[Lars Persson]

Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.

Signed-off-by: Lars Persson 
---
 .../devicetree/bindings/crypto/artpec6-crypto.txt| 16 
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt

diff --git a/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt 
b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
new file mode 100644
index ..d9cca4875bd6
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
@@ -0,0 +1,16 @@
+Axis crypto engine with PDMA interface.
+
+Required properties:
+- compatible : Should be one of the following strings:
+   "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
+   "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
+- reg: Base address and size for the PDMA register area.
+- interrupts: Interrupt handle for the PDMA interrupt line.
+
+Example:
+
+crypto@f4264000 {
+   compatible = "axis,artpec6-crypto";
+   reg = <0xf4264000 0x1000>;
+   interrupts = ;
+};
-- 
2.11.0

[PATCH v2 1/4] dt-bindings: crypto: add ARTPEC crypto

[Lars Persson]

Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 .../devicetree/bindings/crypto/artpec6-crypto.txt| 16 
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt

diff --git a/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt 
b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
new file mode 100644
index ..d9cca4875bd6
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
@@ -0,0 +1,16 @@
+Axis crypto engine with PDMA interface.
+
+Required properties:
+- compatible : Should be one of the following strings:
+   "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
+   "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
+- reg: Base address and size for the PDMA register area.
+- interrupts: Interrupt handle for the PDMA interrupt line.
+
+Example:
+
+crypto@f4264000 {
+   compatible = "axis,artpec6-crypto";
+   reg = <0xf4264000 0x1000>;
+   interrupts = ;
+};
-- 
2.11.0

[PATCH v2 3/4] crypto: axis: add ARTPEC-6/7 crypto accelerator driver

[Lars Persson]

This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.

The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 drivers/crypto/Kconfig   |   21 +
 drivers/crypto/Makefile  |1 +
 drivers/crypto/axis/Makefile |1 +
 drivers/crypto/axis/artpec6_crypto.c | 3193 ++
 4 files changed, 3216 insertions(+)
 create mode 100644 drivers/crypto/axis/Makefile
 create mode 100644 drivers/crypto/axis/artpec6_crypto.c

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 5b5393f1b87a..fe33c199fc1a 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -708,4 +708,25 @@ config CRYPTO_DEV_SAFEXCEL
  chain mode, AES cipher mode and SHA1/SHA224/SHA256/SHA512 hash
  algorithms.
 
+config CRYPTO_DEV_ARTPEC6
+   tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
+   depends on ARM && (ARCH_ARTPEC || COMPILE_TEST)
+   depends on HAS_DMA
+   depends on OF
+   select CRYPTO_AEAD
+   select CRYPTO_AES
+   select CRYPTO_ALGAPI
+   select CRYPTO_BLKCIPHER
+   select CRYPTO_CTR
+   select CRYPTO_HASH
+   select CRYPTO_SHA1
+   select CRYPTO_SHA256
+   select CRYPTO_SHA384
+   select CRYPTO_SHA512
+   help
+ Enables the driver for the on-chip crypto accelerator
+ of Axis ARTPEC SoCs.
+
+ To compile this driver as a module, choose M here.
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index de629165fde7..7bf0997eae25 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
 obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
 obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
 obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
+obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
diff --git a/drivers/crypto/axis/Makefile b/drivers/crypto/axis/Makefile
new file mode 100644
index ..be9a84a4b667
--- /dev/null
+++ b/drivers/crypto/axis/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) := artpec6_crypto.o
diff --git a/drivers/crypto/axis/artpec6_crypto.c 
b/drivers/crypto/axis/artpec6_crypto.c
new file mode 100644
index ..72ce5acf9a24
--- /dev/null
+++ b/drivers/crypto/axis/artpec6_crypto.c
@@ -0,0 +1,3193 @@
+/*
+ *   Driver for ARTPEC-6 crypto block using the kernel asynchronous crypto api.
+ *
+ *Copyright (C) 2014-2017  Axis Communications AB
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Max length of a line in all cache levels for Artpec SoCs. */
+#define ARTPEC_CACHE_LINE_MAX  32
+
+#define PDMA_OUT_CFG   0x
+#define PDMA_OUT_BUF_CFG   0x0004
+#define PDMA_OUT_CMD   0x0008
+#define PDMA_OUT_DESCRQ_PUSH   0x0010
+#define PDMA_OUT_DESCRQ_STAT   0x0014
+
+#define A6_PDMA_IN_CFG 0x0028
+#define A6_PDMA_IN_BUF_CFG 0x002c
+#define A6_PDMA_IN_CMD 0x0030
+#define A6_PDMA_IN_STATQ_PUSH  0x0038
+#define A6_PDMA_IN_DESCRQ_PUSH 0x0044
+#define A6_PDMA_IN_DESCRQ_STAT 0x0048
+#define A6_PDMA_INTR_MASK  0x0068
+#define A6_PDMA_ACK_INTR   0x006c
+#define A6_PDMA_MASKED_INTR0x0074
+
+#define A7_PDMA_IN_CFG 0x002c
+#define A7_PDMA_IN_BUF_CFG 0x0030
+#define A7_PDMA_IN_CMD 0x0034
+#define A7_PDMA_IN_STATQ_PUSH  0x003c
+#define A7_PDMA_IN_DESCRQ_PUSH 0x0048
+#define A7_PDMA_IN_DESCRQ_STAT 0x004C
+#define A7_PDMA_INTR_MASK  0x006c
+#define A7_PDMA_ACK_INTR   0x0070
+#define A7_PDMA_MASKED_INTR0x0078
+
+#define PDMA_OUT_CFG_ENBIT(0)
+
+#define PDMA_OUT_BUF_CFG_DATA_BUF_SIZE GENMASK(4, 0)
+#define PDMA_OUT_BUF_CFG_DESCR_BUF_SIZEGENMASK(9, 5)
+
+#define PDMA_OUT_CMD_START BIT(0)
+#define A6_PDMA_OUT_CMD_STOP   BIT(3)
+#define A7_PDMA_OUT_CMD_STOP   BIT(2)
+
+#define PDMA_OUT_DESCRQ_PUSH_LEN   GENMASK(5, 0)
+#define PDMA_OUT_DESCRQ_PUSH_ADDR  GENMASK(31, 6)
+
+#define PDMA_OUT_DESCRQ_STAT_LEVEL GENMASK(3, 0)
+#define PDMA_OUT_DESCRQ_STAT_SIZE  GENMASK(7, 4)
+
+#define PDMA_IN_CFG_EN BIT(0)
+
+#define PDMA_IN_BUF_CFG_DATA_BUF_SIZE  GENMASK(4, 0)
+#define PDMA_IN_BUF_CFG_DESCR_BUF_SIZE GENMASK(9, 5)
+#define PDMA_IN_BUF_CFG_STAT_BUF_SIZE  GENMASK(14, 10)
+
+#define PDMA_IN_CMD_START  BIT(0)
+#define A6_PDMA_IN_CMD_FLUSH_STAT  BIT(2)
+#define A6_PDMA_IN_CMD_STOPBIT(3)

[PATCH v2 1/4] dt-bindings: crypto: add ARTPEC crypto

[Lars Persson]

Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.

Signed-off-by: Lars Persson 
---
 .../devicetree/bindings/crypto/artpec6-crypto.txt| 16 
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt

diff --git a/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt 
b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
new file mode 100644
index ..d9cca4875bd6
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
@@ -0,0 +1,16 @@
+Axis crypto engine with PDMA interface.
+
+Required properties:
+- compatible : Should be one of the following strings:
+   "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
+   "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
+- reg: Base address and size for the PDMA register area.
+- interrupts: Interrupt handle for the PDMA interrupt line.
+
+Example:
+
+crypto@f4264000 {
+   compatible = "axis,artpec6-crypto";
+   reg = <0xf4264000 0x1000>;
+   interrupts = ;
+};
-- 
2.11.0

[PATCH v2 3/4] crypto: axis: add ARTPEC-6/7 crypto accelerator driver

[Lars Persson]

This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.

The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.

Signed-off-by: Lars Persson 
---
 drivers/crypto/Kconfig   |   21 +
 drivers/crypto/Makefile  |1 +
 drivers/crypto/axis/Makefile |1 +
 drivers/crypto/axis/artpec6_crypto.c | 3193 ++
 4 files changed, 3216 insertions(+)
 create mode 100644 drivers/crypto/axis/Makefile
 create mode 100644 drivers/crypto/axis/artpec6_crypto.c

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 5b5393f1b87a..fe33c199fc1a 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -708,4 +708,25 @@ config CRYPTO_DEV_SAFEXCEL
  chain mode, AES cipher mode and SHA1/SHA224/SHA256/SHA512 hash
  algorithms.
 
+config CRYPTO_DEV_ARTPEC6
+   tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
+   depends on ARM && (ARCH_ARTPEC || COMPILE_TEST)
+   depends on HAS_DMA
+   depends on OF
+   select CRYPTO_AEAD
+   select CRYPTO_AES
+   select CRYPTO_ALGAPI
+   select CRYPTO_BLKCIPHER
+   select CRYPTO_CTR
+   select CRYPTO_HASH
+   select CRYPTO_SHA1
+   select CRYPTO_SHA256
+   select CRYPTO_SHA384
+   select CRYPTO_SHA512
+   help
+ Enables the driver for the on-chip crypto accelerator
+ of Axis ARTPEC SoCs.
+
+ To compile this driver as a module, choose M here.
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index de629165fde7..7bf0997eae25 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
 obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
 obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
 obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
+obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
diff --git a/drivers/crypto/axis/Makefile b/drivers/crypto/axis/Makefile
new file mode 100644
index ..be9a84a4b667
--- /dev/null
+++ b/drivers/crypto/axis/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) := artpec6_crypto.o
diff --git a/drivers/crypto/axis/artpec6_crypto.c 
b/drivers/crypto/axis/artpec6_crypto.c
new file mode 100644
index ..72ce5acf9a24
--- /dev/null
+++ b/drivers/crypto/axis/artpec6_crypto.c
@@ -0,0 +1,3193 @@
+/*
+ *   Driver for ARTPEC-6 crypto block using the kernel asynchronous crypto api.
+ *
+ *Copyright (C) 2014-2017  Axis Communications AB
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Max length of a line in all cache levels for Artpec SoCs. */
+#define ARTPEC_CACHE_LINE_MAX  32
+
+#define PDMA_OUT_CFG   0x
+#define PDMA_OUT_BUF_CFG   0x0004
+#define PDMA_OUT_CMD   0x0008
+#define PDMA_OUT_DESCRQ_PUSH   0x0010
+#define PDMA_OUT_DESCRQ_STAT   0x0014
+
+#define A6_PDMA_IN_CFG 0x0028
+#define A6_PDMA_IN_BUF_CFG 0x002c
+#define A6_PDMA_IN_CMD 0x0030
+#define A6_PDMA_IN_STATQ_PUSH  0x0038
+#define A6_PDMA_IN_DESCRQ_PUSH 0x0044
+#define A6_PDMA_IN_DESCRQ_STAT 0x0048
+#define A6_PDMA_INTR_MASK  0x0068
+#define A6_PDMA_ACK_INTR   0x006c
+#define A6_PDMA_MASKED_INTR0x0074
+
+#define A7_PDMA_IN_CFG 0x002c
+#define A7_PDMA_IN_BUF_CFG 0x0030
+#define A7_PDMA_IN_CMD 0x0034
+#define A7_PDMA_IN_STATQ_PUSH  0x003c
+#define A7_PDMA_IN_DESCRQ_PUSH 0x0048
+#define A7_PDMA_IN_DESCRQ_STAT 0x004C
+#define A7_PDMA_INTR_MASK  0x006c
+#define A7_PDMA_ACK_INTR   0x0070
+#define A7_PDMA_MASKED_INTR0x0078
+
+#define PDMA_OUT_CFG_ENBIT(0)
+
+#define PDMA_OUT_BUF_CFG_DATA_BUF_SIZE GENMASK(4, 0)
+#define PDMA_OUT_BUF_CFG_DESCR_BUF_SIZEGENMASK(9, 5)
+
+#define PDMA_OUT_CMD_START BIT(0)
+#define A6_PDMA_OUT_CMD_STOP   BIT(3)
+#define A7_PDMA_OUT_CMD_STOP   BIT(2)
+
+#define PDMA_OUT_DESCRQ_PUSH_LEN   GENMASK(5, 0)
+#define PDMA_OUT_DESCRQ_PUSH_ADDR  GENMASK(31, 6)
+
+#define PDMA_OUT_DESCRQ_STAT_LEVEL GENMASK(3, 0)
+#define PDMA_OUT_DESCRQ_STAT_SIZE  GENMASK(7, 4)
+
+#define PDMA_IN_CFG_EN BIT(0)
+
+#define PDMA_IN_BUF_CFG_DATA_BUF_SIZE  GENMASK(4, 0)
+#define PDMA_IN_BUF_CFG_DESCR_BUF_SIZE GENMASK(9, 5)
+#define PDMA_IN_BUF_CFG_STAT_BUF_SIZE  GENMASK(14, 10)
+
+#define PDMA_IN_CMD_START  BIT(0)
+#define A6_PDMA_IN_CMD_FLUSH_STAT  BIT(2)
+#define A6_PDMA_IN_CMD_STOPBIT(3)
+#define A7_PDMA_IN_CMD_F

[PATCH v2 4/4] MAINTAINERS: Add ARTPEC crypto maintainer

[Lars Persson]

Assign the Axis kernel team as maintainer for crypto drivers under
drivers/crypto/axis.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d5b6c71e783e..72186cf9820d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1129,6 +1129,7 @@ L:linux-arm-ker...@axis.com
 F: arch/arm/mach-artpec
 F: arch/arm/boot/dts/artpec6*
 F: drivers/clk/axis
+F: drivers/crypto/axis
 F: drivers/pinctrl/pinctrl-artpec*
 F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
 
-- 
2.11.0

[PATCH v2 0/4] crypto: add driver for Axis ARTPEC crypto accelerator

[Lars Persson]

This series adds a driver for the crypto accelerator in the ARTPEC series of
SoCs from Axis Communications AB.

Changelog v2:
- Use xts_check_key() for xts keys.
- Use CRYPTO_ALG_TYPE_SKCIPHER instead of CRYPTO_ALG_TYPE_ABLKCIPHER
  in cra_flags.

Lars Persson (3):
  dt-bindings: crypto: add ARTPEC crypto
  crypto: axis: add ARTPEC-6/7 crypto accelerator driver
  MAINTAINERS: Add ARTPEC crypto maintainer

Rabin Vincent (1):
  crypto: add crypto_(un)register_ahashes()

 .../devicetree/bindings/crypto/artpec6-crypto.txt  |   16 +
 MAINTAINERS|1 +
 crypto/ahash.c |   29 +
 drivers/crypto/Kconfig |   21 +
 drivers/crypto/Makefile|1 +
 drivers/crypto/axis/Makefile   |1 +
 drivers/crypto/axis/artpec6_crypto.c   | 3193 
 include/crypto/internal/hash.h |2 +
 8 files changed, 3264 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
 create mode 100644 drivers/crypto/axis/Makefile
 create mode 100644 drivers/crypto/axis/artpec6_crypto.c

-- 
2.11.0

[PATCH v2 4/4] MAINTAINERS: Add ARTPEC crypto maintainer

[Lars Persson]

Assign the Axis kernel team as maintainer for crypto drivers under
drivers/crypto/axis.

Signed-off-by: Lars Persson 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d5b6c71e783e..72186cf9820d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1129,6 +1129,7 @@ L:linux-arm-ker...@axis.com
 F: arch/arm/mach-artpec
 F: arch/arm/boot/dts/artpec6*
 F: drivers/clk/axis
+F: drivers/crypto/axis
 F: drivers/pinctrl/pinctrl-artpec*
 F: Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
 
-- 
2.11.0

[PATCH v2 0/4] crypto: add driver for Axis ARTPEC crypto accelerator

[Lars Persson]

This series adds a driver for the crypto accelerator in the ARTPEC series of
SoCs from Axis Communications AB.

Changelog v2:
- Use xts_check_key() for xts keys.
- Use CRYPTO_ALG_TYPE_SKCIPHER instead of CRYPTO_ALG_TYPE_ABLKCIPHER
  in cra_flags.

Lars Persson (3):
  dt-bindings: crypto: add ARTPEC crypto
  crypto: axis: add ARTPEC-6/7 crypto accelerator driver
  MAINTAINERS: Add ARTPEC crypto maintainer

Rabin Vincent (1):
  crypto: add crypto_(un)register_ahashes()

 .../devicetree/bindings/crypto/artpec6-crypto.txt  |   16 +
 MAINTAINERS|1 +
 crypto/ahash.c |   29 +
 drivers/crypto/Kconfig |   21 +
 drivers/crypto/Makefile|1 +
 drivers/crypto/axis/Makefile   |1 +
 drivers/crypto/axis/artpec6_crypto.c   | 3193 
 include/crypto/internal/hash.h |2 +
 8 files changed, 3264 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt
 create mode 100644 drivers/crypto/axis/Makefile
 create mode 100644 drivers/crypto/axis/artpec6_crypto.c

-- 
2.11.0

[PATCH v2 2/4] crypto: add crypto_(un)register_ahashes()

[Lars Persson]

From: Rabin Vincent <rab...@axis.com>

There are already helpers to (un)register multiple normal
and AEAD algos.  Add one for ahashes too.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 crypto/ahash.c | 29 +
 include/crypto/internal/hash.h |  2 ++
 2 files changed, 31 insertions(+)

diff --git a/crypto/ahash.c b/crypto/ahash.c
index 826cd7ab4d4a..5e8666e6ccae 100644
--- a/crypto/ahash.c
+++ b/crypto/ahash.c
@@ -588,6 +588,35 @@ int crypto_unregister_ahash(struct ahash_alg *alg)
 }
 EXPORT_SYMBOL_GPL(crypto_unregister_ahash);
 
+int crypto_register_ahashes(struct ahash_alg *algs, int count)
+{
+   int i, ret;
+
+   for (i = 0; i < count; i++) {
+   ret = crypto_register_ahash([i]);
+   if (ret)
+   goto err;
+   }
+
+   return 0;
+
+err:
+   for (--i; i >= 0; --i)
+   crypto_unregister_ahash([i]);
+
+   return ret;
+}
+EXPORT_SYMBOL_GPL(crypto_register_ahashes);
+
+void crypto_unregister_ahashes(struct ahash_alg *algs, int count)
+{
+   int i;
+
+   for (i = count - 1; i >= 0; --i)
+   crypto_unregister_ahash([i]);
+}
+EXPORT_SYMBOL_GPL(crypto_unregister_ahashes);
+
 int ahash_register_instance(struct crypto_template *tmpl,
struct ahash_instance *inst)
 {
diff --git a/include/crypto/internal/hash.h b/include/crypto/internal/hash.h
index f6d9af3efa45..f0b44c16e88f 100644
--- a/include/crypto/internal/hash.h
+++ b/include/crypto/internal/hash.h
@@ -76,6 +76,8 @@ static inline int crypto_ahash_walk_last(struct 
crypto_hash_walk *walk)
 
 int crypto_register_ahash(struct ahash_alg *alg);
 int crypto_unregister_ahash(struct ahash_alg *alg);
+int crypto_register_ahashes(struct ahash_alg *algs, int count);
+void crypto_unregister_ahashes(struct ahash_alg *algs, int count);
 int ahash_register_instance(struct crypto_template *tmpl,
struct ahash_instance *inst);
 void ahash_free_instance(struct crypto_instance *inst);
-- 
2.11.0

[PATCH v2 2/4] crypto: add crypto_(un)register_ahashes()

[Lars Persson]

From: Rabin Vincent 

There are already helpers to (un)register multiple normal
and AEAD algos.  Add one for ahashes too.

Signed-off-by: Lars Persson 
---
 crypto/ahash.c | 29 +
 include/crypto/internal/hash.h |  2 ++
 2 files changed, 31 insertions(+)

diff --git a/crypto/ahash.c b/crypto/ahash.c
index 826cd7ab4d4a..5e8666e6ccae 100644
--- a/crypto/ahash.c
+++ b/crypto/ahash.c
@@ -588,6 +588,35 @@ int crypto_unregister_ahash(struct ahash_alg *alg)
 }
 EXPORT_SYMBOL_GPL(crypto_unregister_ahash);
 
+int crypto_register_ahashes(struct ahash_alg *algs, int count)
+{
+   int i, ret;
+
+   for (i = 0; i < count; i++) {
+   ret = crypto_register_ahash([i]);
+   if (ret)
+   goto err;
+   }
+
+   return 0;
+
+err:
+   for (--i; i >= 0; --i)
+   crypto_unregister_ahash([i]);
+
+   return ret;
+}
+EXPORT_SYMBOL_GPL(crypto_register_ahashes);
+
+void crypto_unregister_ahashes(struct ahash_alg *algs, int count)
+{
+   int i;
+
+   for (i = count - 1; i >= 0; --i)
+   crypto_unregister_ahash([i]);
+}
+EXPORT_SYMBOL_GPL(crypto_unregister_ahashes);
+
 int ahash_register_instance(struct crypto_template *tmpl,
struct ahash_instance *inst)
 {
diff --git a/include/crypto/internal/hash.h b/include/crypto/internal/hash.h
index f6d9af3efa45..f0b44c16e88f 100644
--- a/include/crypto/internal/hash.h
+++ b/include/crypto/internal/hash.h
@@ -76,6 +76,8 @@ static inline int crypto_ahash_walk_last(struct 
crypto_hash_walk *walk)
 
 int crypto_register_ahash(struct ahash_alg *alg);
 int crypto_unregister_ahash(struct ahash_alg *alg);
+int crypto_register_ahashes(struct ahash_alg *algs, int count);
+void crypto_unregister_ahashes(struct ahash_alg *algs, int count);
 int ahash_register_instance(struct crypto_template *tmpl,
struct ahash_instance *inst);
 void ahash_free_instance(struct crypto_instance *inst);
-- 
2.11.0

Re: Synopsys Ethernet QoS Driver

[Lars Persson]

> 23 nov. 2016 kl. 12:11 skrev Joao Pinto :
> 
> Hi Peppe and Lars,
> 
>> On 23-11-2016 10:59, Giuseppe CAVALLARO wrote:
>> Hello Joao, Lars.
>> 
>>> On 11/22/2016 3:16 PM, Joao Pinto wrote:
> Ok, it makes sense.
> Just for curiosity the target setup is the following:
> https://www.youtube.com/watch?v=8V-LB5y2Cos
> but instead of using internal drivers, we desire to use mainline drivers 
> only.
> 
> Thanks!
>>> Regarding this subject, I am thinking of making the following adaption:
>>> 
>>> a) delete ethernet/synopsys
>>> b) rename ethernet/stmicro/stmmac to ethernet/synopsys
>>> 
>>> and send you a patch for you to evaluate. Both agree with the approach?
>>> To have a new work base would be important, because I will add to the "new"
>>> structure some missing QoS features like Multichannel support, CBS and 
>>> later TSN.
>> 
>> IMO, we have to agree on a common strategy making the change for
>> net-next; I imaged the following steps:
> 
> Yes it makes totally sense.
> 
>> 
>> - to port missing feature or fixes from ethernet/synopsys
>>  inside the stmmac taking care about the documentation too.
> 
> @Lars: You are familiar with the synopsys qos driver. Could you please do this
> porting. You can also make an analysis of what to port and I can do the 
> porting
> for you if you don't have the availability for it.

As my main duty is changing diapers until March next year, please go ahead with 
this step if you can spend time on it before I am back in office.

Rabin Vincent can review and test that the port works properly on our 
Artpec-chips that use dwc_eth_qos.c today.

The main porting step is to implement the device tree binding in 
bindings/net/snps,dwc-qos-ethernet.txt. Also our chip has a strict requirement 
that the phy is enabled when the SWR reset bit is set (it needs a tx clock to 
complete the reset).

- Lars

> 
>> - remove ethernet/synopsys
>> - rename ethernet/stmicro/stmmac to ethernet/synopsys
> 
> I volunteer to do this task.
> 
>> 
>>  These latest two have some relevant impacts.
>> 
>>  This change should be propagated to all the platforms that are using:
>>  CONFIG_SYNOPSYS_DWC_ETH_QOS and CONFIG_STMMAC_ETH
>>  plus device-tree compatibility.
> 
> I volunteer to do this task also.
> 
>> 
>> - enhance the stmmac with new features and new glue (part of these
>>  can be anticipated for sure).
> 
> I have to implement 3 new features for now, but I will take some time for it, 
> so
> I would suggest to make the previous task and incrementally add features.
> 
>> 
>> what do you think? does it make sense? If yes, we can also
>> understand how/who starts.
>> 
>> Regards,
>> Peppe
> 
> Thanks and regards.
> 
> Joao
> 
>> 
>>> Thanks.
>> 
> 

Re: Synopsys Ethernet QoS Driver

[Lars Persson]

> 23 nov. 2016 kl. 12:11 skrev Joao Pinto :
> 
> Hi Peppe and Lars,
> 
>> On 23-11-2016 10:59, Giuseppe CAVALLARO wrote:
>> Hello Joao, Lars.
>> 
>>> On 11/22/2016 3:16 PM, Joao Pinto wrote:
> Ok, it makes sense.
> Just for curiosity the target setup is the following:
> https://www.youtube.com/watch?v=8V-LB5y2Cos
> but instead of using internal drivers, we desire to use mainline drivers 
> only.
> 
> Thanks!
>>> Regarding this subject, I am thinking of making the following adaption:
>>> 
>>> a) delete ethernet/synopsys
>>> b) rename ethernet/stmicro/stmmac to ethernet/synopsys
>>> 
>>> and send you a patch for you to evaluate. Both agree with the approach?
>>> To have a new work base would be important, because I will add to the "new"
>>> structure some missing QoS features like Multichannel support, CBS and 
>>> later TSN.
>> 
>> IMO, we have to agree on a common strategy making the change for
>> net-next; I imaged the following steps:
> 
> Yes it makes totally sense.
> 
>> 
>> - to port missing feature or fixes from ethernet/synopsys
>>  inside the stmmac taking care about the documentation too.
> 
> @Lars: You are familiar with the synopsys qos driver. Could you please do this
> porting. You can also make an analysis of what to port and I can do the 
> porting
> for you if you don't have the availability for it.

As my main duty is changing diapers until March next year, please go ahead with 
this step if you can spend time on it before I am back in office.

Rabin Vincent can review and test that the port works properly on our 
Artpec-chips that use dwc_eth_qos.c today.

The main porting step is to implement the device tree binding in 
bindings/net/snps,dwc-qos-ethernet.txt. Also our chip has a strict requirement 
that the phy is enabled when the SWR reset bit is set (it needs a tx clock to 
complete the reset).

- Lars

> 
>> - remove ethernet/synopsys
>> - rename ethernet/stmicro/stmmac to ethernet/synopsys
> 
> I volunteer to do this task.
> 
>> 
>>  These latest two have some relevant impacts.
>> 
>>  This change should be propagated to all the platforms that are using:
>>  CONFIG_SYNOPSYS_DWC_ETH_QOS and CONFIG_STMMAC_ETH
>>  plus device-tree compatibility.
> 
> I volunteer to do this task also.
> 
>> 
>> - enhance the stmmac with new features and new glue (part of these
>>  can be anticipated for sure).
> 
> I have to implement 3 new features for now, but I will take some time for it, 
> so
> I would suggest to make the previous task and incrementally add features.
> 
>> 
>> what do you think? does it make sense? If yes, we can also
>> understand how/who starts.
>> 
>> Regards,
>> Peppe
> 
> Thanks and regards.
> 
> Joao
> 
>> 
>>> Thanks.
>> 
> 

Re: Synopsys Ethernet QoS Driver

[Lars Persson]

> 21 nov. 2016 kl. 16:06 skrev Joao Pinto <joao.pi...@synopsys.com>:
> 
>> On 21-11-2016 14:25, Giuseppe CAVALLARO wrote:
>>> On 11/21/2016 2:28 PM, Lars Persson wrote:
>>> 
>>> 
>>>> 21 nov. 2016 kl. 13:53 skrev Giuseppe CAVALLARO <peppe.cavall...@st.com>:
>>>> 
>>>> Hello Joao
>>>> 
>>>>> On 11/21/2016 1:32 PM, Joao Pinto wrote:
>>>>> Hello,
>>>>> 
>>>>>>> On 21-11-2016 05:29, Rayagond Kokatanur wrote:
>>>>>>>> On Sat, Nov 19, 2016 at 7:26 PM, Rabin Vincent <ra...@rab.in> wrote:
>>>>>>>> On Fri, Nov 18, 2016 at 02:20:27PM +, Joao Pinto wrote:
>>>>>>>> For now we are interesting in improving the synopsys QoS driver under
>>>>>>>> /nect/ethernet/synopsys. For now the driver structure consists of a
>>>>>>>> single file
>>>>>>>> called dwc_eth_qos.c, containing synopsys ethernet qos common ops and
>>>>>>>> platform
>>>>>>>> related stuff.
>>>>>>>> 
>>>>>>>> Our strategy would be:
>>>>>>>> 
>>>>>>>> a) Implement a platform glue driver (dwc_eth_qos_pltfm.c)
>>>>>>>> b) Implement a pci glue driver (dwc_eth_qos_pci.c)
>>>>>>>> c) Implement a "core driver" (dwc_eth_qos.c) that would only have
>>>>>>>> Ethernet QoS
>>>>>>>> related stuff to be reused by the platform / pci drivers
>>>>>>>> d) Add a set of features to the "core driver" that we have available
>>>>>>>> internally
>>>>>>> 
>>>>>>> Note that there are actually two drivers in mainline for this hardware:
>>>>>>> 
>>>>>>> drivers/net/ethernet/synopsis/
>>>>>>> drivers/net/ethernet/stmicro/stmmac/
>>>>>> 
>>>>>> Yes the later driver (drivers/net/ethernet/stmicro/stmmac/) supports
>>>>>> both 3.x and 4.x. It has glue layer for pci, platform, core etc,
>>>>>> please refer this driver once before you start.
>>>>>> 
>>>>>> You can start adding missing feature of 4.x in stmmac driver.
>>>>> 
>>>>> Thanks you all for all the info.
>>>>> Well, I think we are in a good position to organize the ethernet drivers
>>>>> concerning Synopsys IPs.
>>>>> 
>>>>> First of all, in my opinion, it does not make sense to have a 
>>>>> ethernet/synopsis
>>>>> (typo :)) when ethernet/stmicro is also for a synopsys IP. If we have 
>>>>> another
>>>>> vendor using the same IP it should be able to reuse the commonn 
>>>>> operations. But
>>>>> I would put that discussion for later :)
>>>>> 
>>>>> For now I suggest that for we create ethernet/qos and create there a 
>>>>> folder
>>>>> called dwc (designware controller) where all the synopsys qos IP specific 
>>>>> code
>>>>> in order to be reused for example by ethernet/stmicro/stmmac/. We just 
>>>>> have to
>>>>> figure out a clean interface for "client drivers" like stmmac to interact 
>>>>> with
>>>>> the new qos driver.
>>>>> 
>>>>> What do you think about this approach?
>>>> 
>>>> The stmmac drivers run since many years on several platforms
>>>> (sh4, stm32, arm, x86, mips ...) and it supports an huge of amount of
>>>> configurations starting from 3.1x to 3.7x databooks.
>>>> 
>>>> It also supports QoS hardware; for example, 4.00a, 4.10a and 4.20a
>>>> are fully working.
>>>> 
>>>> Also the stmmac has platform, device-tree and pcie supports and
>>>> a lot of maintained glue-logic files.
>>>> 
>>>> It is fully documented inside the kernel tree.
>>>> 
>>>> I am happy to have new enhancements from other developers.
>>>> So, on my side, if you want to spend your time on improving it on your
>>>> platforms please feel free to do it!
>>>> 
>>>> Concerning the stmicro/stmmac naming, these come from a really old
>>>> story and have no issue to adopt new folder/file names.
>>>> 
>>>> I

Re: Synopsys Ethernet QoS Driver

[Lars Persson]

> 21 nov. 2016 kl. 16:06 skrev Joao Pinto :
> 
>> On 21-11-2016 14:25, Giuseppe CAVALLARO wrote:
>>> On 11/21/2016 2:28 PM, Lars Persson wrote:
>>> 
>>> 
>>>> 21 nov. 2016 kl. 13:53 skrev Giuseppe CAVALLARO :
>>>> 
>>>> Hello Joao
>>>> 
>>>>> On 11/21/2016 1:32 PM, Joao Pinto wrote:
>>>>> Hello,
>>>>> 
>>>>>>> On 21-11-2016 05:29, Rayagond Kokatanur wrote:
>>>>>>>> On Sat, Nov 19, 2016 at 7:26 PM, Rabin Vincent  wrote:
>>>>>>>> On Fri, Nov 18, 2016 at 02:20:27PM +, Joao Pinto wrote:
>>>>>>>> For now we are interesting in improving the synopsys QoS driver under
>>>>>>>> /nect/ethernet/synopsys. For now the driver structure consists of a
>>>>>>>> single file
>>>>>>>> called dwc_eth_qos.c, containing synopsys ethernet qos common ops and
>>>>>>>> platform
>>>>>>>> related stuff.
>>>>>>>> 
>>>>>>>> Our strategy would be:
>>>>>>>> 
>>>>>>>> a) Implement a platform glue driver (dwc_eth_qos_pltfm.c)
>>>>>>>> b) Implement a pci glue driver (dwc_eth_qos_pci.c)
>>>>>>>> c) Implement a "core driver" (dwc_eth_qos.c) that would only have
>>>>>>>> Ethernet QoS
>>>>>>>> related stuff to be reused by the platform / pci drivers
>>>>>>>> d) Add a set of features to the "core driver" that we have available
>>>>>>>> internally
>>>>>>> 
>>>>>>> Note that there are actually two drivers in mainline for this hardware:
>>>>>>> 
>>>>>>> drivers/net/ethernet/synopsis/
>>>>>>> drivers/net/ethernet/stmicro/stmmac/
>>>>>> 
>>>>>> Yes the later driver (drivers/net/ethernet/stmicro/stmmac/) supports
>>>>>> both 3.x and 4.x. It has glue layer for pci, platform, core etc,
>>>>>> please refer this driver once before you start.
>>>>>> 
>>>>>> You can start adding missing feature of 4.x in stmmac driver.
>>>>> 
>>>>> Thanks you all for all the info.
>>>>> Well, I think we are in a good position to organize the ethernet drivers
>>>>> concerning Synopsys IPs.
>>>>> 
>>>>> First of all, in my opinion, it does not make sense to have a 
>>>>> ethernet/synopsis
>>>>> (typo :)) when ethernet/stmicro is also for a synopsys IP. If we have 
>>>>> another
>>>>> vendor using the same IP it should be able to reuse the commonn 
>>>>> operations. But
>>>>> I would put that discussion for later :)
>>>>> 
>>>>> For now I suggest that for we create ethernet/qos and create there a 
>>>>> folder
>>>>> called dwc (designware controller) where all the synopsys qos IP specific 
>>>>> code
>>>>> in order to be reused for example by ethernet/stmicro/stmmac/. We just 
>>>>> have to
>>>>> figure out a clean interface for "client drivers" like stmmac to interact 
>>>>> with
>>>>> the new qos driver.
>>>>> 
>>>>> What do you think about this approach?
>>>> 
>>>> The stmmac drivers run since many years on several platforms
>>>> (sh4, stm32, arm, x86, mips ...) and it supports an huge of amount of
>>>> configurations starting from 3.1x to 3.7x databooks.
>>>> 
>>>> It also supports QoS hardware; for example, 4.00a, 4.10a and 4.20a
>>>> are fully working.
>>>> 
>>>> Also the stmmac has platform, device-tree and pcie supports and
>>>> a lot of maintained glue-logic files.
>>>> 
>>>> It is fully documented inside the kernel tree.
>>>> 
>>>> I am happy to have new enhancements from other developers.
>>>> So, on my side, if you want to spend your time on improving it on your
>>>> platforms please feel free to do it!
>>>> 
>>>> Concerning the stmicro/stmmac naming, these come from a really old
>>>> story and have no issue to adopt new folder/file names.
>>>> 
>>>> I am also open to merge fixes and changes from ethernet/synopsis.
>>>> I want to po

Re: Synopsys Ethernet QoS Driver

[Lars Persson]

> 21 nov. 2016 kl. 13:53 skrev Giuseppe CAVALLARO :
> 
> Hello Joao
> 
>> On 11/21/2016 1:32 PM, Joao Pinto wrote:
>> Hello,
>> 
>>> On 21-11-2016 05:29, Rayagond Kokatanur wrote:
 On Sat, Nov 19, 2016 at 7:26 PM, Rabin Vincent  wrote:
> On Fri, Nov 18, 2016 at 02:20:27PM +, Joao Pinto wrote:
> For now we are interesting in improving the synopsys QoS driver under
> /nect/ethernet/synopsys. For now the driver structure consists of a 
> single file
> called dwc_eth_qos.c, containing synopsys ethernet qos common ops and 
> platform
> related stuff.
> 
> Our strategy would be:
> 
> a) Implement a platform glue driver (dwc_eth_qos_pltfm.c)
> b) Implement a pci glue driver (dwc_eth_qos_pci.c)
> c) Implement a "core driver" (dwc_eth_qos.c) that would only have 
> Ethernet QoS
> related stuff to be reused by the platform / pci drivers
> d) Add a set of features to the "core driver" that we have available 
> internally
 
 Note that there are actually two drivers in mainline for this hardware:
 
 drivers/net/ethernet/synopsis/
 drivers/net/ethernet/stmicro/stmmac/
>>> 
>>> Yes the later driver (drivers/net/ethernet/stmicro/stmmac/) supports
>>> both 3.x and 4.x. It has glue layer for pci, platform, core etc,
>>> please refer this driver once before you start.
>>> 
>>> You can start adding missing feature of 4.x in stmmac driver.
>> 
>> Thanks you all for all the info.
>> Well, I think we are in a good position to organize the ethernet drivers
>> concerning Synopsys IPs.
>> 
>> First of all, in my opinion, it does not make sense to have a 
>> ethernet/synopsis
>> (typo :)) when ethernet/stmicro is also for a synopsys IP. If we have another
>> vendor using the same IP it should be able to reuse the commonn operations. 
>> But
>> I would put that discussion for later :)
>> 
>> For now I suggest that for we create ethernet/qos and create there a folder
>> called dwc (designware controller) where all the synopsys qos IP specific 
>> code
>> in order to be reused for example by ethernet/stmicro/stmmac/. We just have 
>> to
>> figure out a clean interface for "client drivers" like stmmac to interact 
>> with
>> the new qos driver.
>> 
>> What do you think about this approach?
> 
> The stmmac drivers run since many years on several platforms
> (sh4, stm32, arm, x86, mips ...) and it supports an huge of amount of
> configurations starting from 3.1x to 3.7x databooks.
> 
> It also supports QoS hardware; for example, 4.00a, 4.10a and 4.20a
> are fully working.
> 
> Also the stmmac has platform, device-tree and pcie supports and
> a lot of maintained glue-logic files.
> 
> It is fully documented inside the kernel tree.
> 
> I am happy to have new enhancements from other developers.
> So, on my side, if you want to spend your time on improving it on your
> platforms please feel free to do it!
> 
> Concerning the stmicro/stmmac naming, these come from a really old
> story and have no issue to adopt new folder/file names.
> 
> I am also open to merge fixes and changes from ethernet/synopsis.
> I want to point you on some benchmarks made by Alex some months ago
> (IIRC) that showed an stmmac winner (due to the several optimizations
> analyzed and reviewed in this mailing list).
> 
> Peppe
> 

Hello Joao and others,

As the maintainer of dwc_eth_qos.c I prefer also that we put efforts on the 
most mature driver, the stmmac.

I hope that the code can migrate into an ethernet/synopsys folder to keep the 
convention of naming the folder after the vendor. This makes it easy for others 
to find the driver. 

The dwc_eth_qos.c will eventually be removed and its DT binding interface can 
then be implemented in the stmmac driver.

- Lars

>> 
>> 
>>> 
 
 (See http://lists.openwall.net/netdev/2016/02/29/127)
 
 The former only supports 4.x of the hardware.
 
 The later supports 4.x and 3.x and already has a platform glue driver
 with support for several platforms, a PCI glue driver, and a core driver
 with several features not present in the former (for example: TX/RX
 interrupt coalescing, EEE, PTP).
 
 Have you evaluated both drivers?  Why have you decided to work on the
 former rather than the latter?
>>> 
>>> 
>> 
>> Thanks.
>> 
>> 
>> 
>> 
> 

Re: Synopsys Ethernet QoS Driver

[Lars Persson]

> 21 nov. 2016 kl. 13:53 skrev Giuseppe CAVALLARO :
> 
> Hello Joao
> 
>> On 11/21/2016 1:32 PM, Joao Pinto wrote:
>> Hello,
>> 
>>> On 21-11-2016 05:29, Rayagond Kokatanur wrote:
 On Sat, Nov 19, 2016 at 7:26 PM, Rabin Vincent  wrote:
> On Fri, Nov 18, 2016 at 02:20:27PM +, Joao Pinto wrote:
> For now we are interesting in improving the synopsys QoS driver under
> /nect/ethernet/synopsys. For now the driver structure consists of a 
> single file
> called dwc_eth_qos.c, containing synopsys ethernet qos common ops and 
> platform
> related stuff.
> 
> Our strategy would be:
> 
> a) Implement a platform glue driver (dwc_eth_qos_pltfm.c)
> b) Implement a pci glue driver (dwc_eth_qos_pci.c)
> c) Implement a "core driver" (dwc_eth_qos.c) that would only have 
> Ethernet QoS
> related stuff to be reused by the platform / pci drivers
> d) Add a set of features to the "core driver" that we have available 
> internally
 
 Note that there are actually two drivers in mainline for this hardware:
 
 drivers/net/ethernet/synopsis/
 drivers/net/ethernet/stmicro/stmmac/
>>> 
>>> Yes the later driver (drivers/net/ethernet/stmicro/stmmac/) supports
>>> both 3.x and 4.x. It has glue layer for pci, platform, core etc,
>>> please refer this driver once before you start.
>>> 
>>> You can start adding missing feature of 4.x in stmmac driver.
>> 
>> Thanks you all for all the info.
>> Well, I think we are in a good position to organize the ethernet drivers
>> concerning Synopsys IPs.
>> 
>> First of all, in my opinion, it does not make sense to have a 
>> ethernet/synopsis
>> (typo :)) when ethernet/stmicro is also for a synopsys IP. If we have another
>> vendor using the same IP it should be able to reuse the commonn operations. 
>> But
>> I would put that discussion for later :)
>> 
>> For now I suggest that for we create ethernet/qos and create there a folder
>> called dwc (designware controller) where all the synopsys qos IP specific 
>> code
>> in order to be reused for example by ethernet/stmicro/stmmac/. We just have 
>> to
>> figure out a clean interface for "client drivers" like stmmac to interact 
>> with
>> the new qos driver.
>> 
>> What do you think about this approach?
> 
> The stmmac drivers run since many years on several platforms
> (sh4, stm32, arm, x86, mips ...) and it supports an huge of amount of
> configurations starting from 3.1x to 3.7x databooks.
> 
> It also supports QoS hardware; for example, 4.00a, 4.10a and 4.20a
> are fully working.
> 
> Also the stmmac has platform, device-tree and pcie supports and
> a lot of maintained glue-logic files.
> 
> It is fully documented inside the kernel tree.
> 
> I am happy to have new enhancements from other developers.
> So, on my side, if you want to spend your time on improving it on your
> platforms please feel free to do it!
> 
> Concerning the stmicro/stmmac naming, these come from a really old
> story and have no issue to adopt new folder/file names.
> 
> I am also open to merge fixes and changes from ethernet/synopsis.
> I want to point you on some benchmarks made by Alex some months ago
> (IIRC) that showed an stmmac winner (due to the several optimizations
> analyzed and reviewed in this mailing list).
> 
> Peppe
> 

Hello Joao and others,

As the maintainer of dwc_eth_qos.c I prefer also that we put efforts on the 
most mature driver, the stmmac.

I hope that the code can migrate into an ethernet/synopsys folder to keep the 
convention of naming the folder after the vendor. This makes it easy for others 
to find the driver. 

The dwc_eth_qos.c will eventually be removed and its DT binding interface can 
then be implemented in the stmmac driver.

- Lars

>> 
>> 
>>> 
 
 (See http://lists.openwall.net/netdev/2016/02/29/127)
 
 The former only supports 4.x of the hardware.
 
 The later supports 4.x and 3.x and already has a platform glue driver
 with support for several platforms, a PCI glue driver, and a core driver
 with several features not present in the former (for example: TX/RX
 interrupt coalescing, EEE, PTP).
 
 Have you evaluated both drivers?  Why have you decided to work on the
 former rather than the latter?
>>> 
>>> 
>> 
>> Thanks.
>> 
>> 
>> 
>> 
> 

[PATCH net] dwc_eth_qos: do not register semi-initialized device

[Lars Persson]

We move register_netdev() to the end of dwceqos_probe() to close any
races where the netdev callbacks are called before the initialization
has finished.

Reported-by: Pavel Andrianov <andria...@ispras.ru>
Signed-off-by: Lars Persson <lar...@axis.com>
---
 drivers/net/ethernet/synopsys/dwc_eth_qos.c | 38 ++---
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/drivers/net/ethernet/synopsys/dwc_eth_qos.c 
b/drivers/net/ethernet/synopsys/dwc_eth_qos.c
index 5a3941b..4490eba 100644
--- a/drivers/net/ethernet/synopsys/dwc_eth_qos.c
+++ b/drivers/net/ethernet/synopsys/dwc_eth_qos.c
@@ -1246,7 +1246,7 @@ static int dwceqos_mii_init(struct net_local *lp)
lp->mii_bus->read  = _mdio_read;
lp->mii_bus->write = _mdio_write;
lp->mii_bus->priv = lp;
-   lp->mii_bus->parent = >ndev->dev;
+   lp->mii_bus->parent = >pdev->dev;
 
of_address_to_resource(lp->pdev->dev.of_node, 0, );
snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%.8llx",
@@ -2853,25 +2853,17 @@ static int dwceqos_probe(struct platform_device *pdev)
 
ndev->features = ndev->hw_features;
 
-   netif_napi_add(ndev, >napi, dwceqos_rx_poll, NAPI_POLL_WEIGHT);
-
-   ret = register_netdev(ndev);
-   if (ret) {
-   dev_err(>dev, "Cannot register net device, aborting.\n");
-   goto err_out_clk_dis_aper;
-   }
-
lp->phy_ref_clk = devm_clk_get(>dev, "phy_ref_clk");
if (IS_ERR(lp->phy_ref_clk)) {
dev_err(>dev, "phy_ref_clk clock not found.\n");
ret = PTR_ERR(lp->phy_ref_clk);
-   goto err_out_unregister_netdev;
+   goto err_out_clk_dis_aper;
}
 
ret = clk_prepare_enable(lp->phy_ref_clk);
if (ret) {
dev_err(>dev, "Unable to enable device clock.\n");
-   goto err_out_unregister_netdev;
+   goto err_out_clk_dis_aper;
}
 
lp->phy_node = of_parse_phandle(lp->pdev->dev.of_node,
@@ -2880,7 +2872,7 @@ static int dwceqos_probe(struct platform_device *pdev)
ret = of_phy_register_fixed_link(lp->pdev->dev.of_node);
if (ret < 0) {
dev_err(>dev, "invalid fixed-link");
-   goto err_out_unregister_clk_notifier;
+   goto err_out_clk_dis_phy;
}
 
lp->phy_node = of_node_get(lp->pdev->dev.of_node);
@@ -2889,7 +2881,7 @@ static int dwceqos_probe(struct platform_device *pdev)
ret = of_get_phy_mode(lp->pdev->dev.of_node);
if (ret < 0) {
dev_err(>pdev->dev, "error in getting phy i/f\n");
-   goto err_out_unregister_clk_notifier;
+   goto err_out_clk_dis_phy;
}
 
lp->phy_interface = ret;
@@ -2897,14 +2889,14 @@ static int dwceqos_probe(struct platform_device *pdev)
ret = dwceqos_mii_init(lp);
if (ret) {
dev_err(>pdev->dev, "error in dwceqos_mii_init\n");
-   goto err_out_unregister_clk_notifier;
+   goto err_out_clk_dis_phy;
}
 
ret = dwceqos_mii_probe(ndev);
if (ret != 0) {
netdev_err(ndev, "mii_probe fail.\n");
ret = -ENXIO;
-   goto err_out_unregister_clk_notifier;
+   goto err_out_clk_dis_phy;
}
 
dwceqos_set_umac_addr(lp, lp->ndev->dev_addr, 0);
@@ -2922,7 +2914,7 @@ static int dwceqos_probe(struct platform_device *pdev)
if (ret) {
dev_err(>pdev->dev, "Unable to retrieve DT, error %d\n",
ret);
-   goto err_out_unregister_clk_notifier;
+   goto err_out_clk_dis_phy;
}
dev_info(>pdev->dev, "pdev->id %d, baseaddr 0x%08lx, irq %d\n",
 pdev->id, ndev->base_addr, ndev->irq);
@@ -2932,18 +2924,24 @@ static int dwceqos_probe(struct platform_device *pdev)
if (ret) {
dev_err(>pdev->dev, "Unable to request IRQ %d, error %d\n",
ndev->irq, ret);
-   goto err_out_unregister_clk_notifier;
+   goto err_out_clk_dis_phy;
}
 
if (netif_msg_probe(lp))
netdev_dbg(ndev, "net_local@%p\n", lp);
 
+   netif_napi_add(ndev, >napi, dwceqos_rx_poll, NAPI_POLL_WEIGHT);
+
+   ret = register_netdev(ndev);
+   if (ret) {
+   dev_err(>dev, "Cannot register net device, aborting.\n");
+   goto err_out_clk_dis_phy;
+   }
+
return 0;
 
-err_out_unregister_clk_notifier:
+err_out_clk_dis_phy:
clk_disable_unprepare(lp->phy_ref_clk);
-err_out_unregister_netdev:
-   unregister_netdev(ndev);
 err_out_clk_dis_aper:
clk_disable_unprepare(lp->apb_pclk);
 err_out_free_netdev:
-- 
2.1.4

[PATCH net] dwc_eth_qos: do not register semi-initialized device

[Lars Persson]

We move register_netdev() to the end of dwceqos_probe() to close any
races where the netdev callbacks are called before the initialization
has finished.

Reported-by: Pavel Andrianov 
Signed-off-by: Lars Persson 
---
 drivers/net/ethernet/synopsys/dwc_eth_qos.c | 38 ++---
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/drivers/net/ethernet/synopsys/dwc_eth_qos.c 
b/drivers/net/ethernet/synopsys/dwc_eth_qos.c
index 5a3941b..4490eba 100644
--- a/drivers/net/ethernet/synopsys/dwc_eth_qos.c
+++ b/drivers/net/ethernet/synopsys/dwc_eth_qos.c
@@ -1246,7 +1246,7 @@ static int dwceqos_mii_init(struct net_local *lp)
lp->mii_bus->read  = _mdio_read;
lp->mii_bus->write = _mdio_write;
lp->mii_bus->priv = lp;
-   lp->mii_bus->parent = >ndev->dev;
+   lp->mii_bus->parent = >pdev->dev;
 
of_address_to_resource(lp->pdev->dev.of_node, 0, );
snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%.8llx",
@@ -2853,25 +2853,17 @@ static int dwceqos_probe(struct platform_device *pdev)
 
ndev->features = ndev->hw_features;
 
-   netif_napi_add(ndev, >napi, dwceqos_rx_poll, NAPI_POLL_WEIGHT);
-
-   ret = register_netdev(ndev);
-   if (ret) {
-   dev_err(>dev, "Cannot register net device, aborting.\n");
-   goto err_out_clk_dis_aper;
-   }
-
lp->phy_ref_clk = devm_clk_get(>dev, "phy_ref_clk");
if (IS_ERR(lp->phy_ref_clk)) {
dev_err(>dev, "phy_ref_clk clock not found.\n");
ret = PTR_ERR(lp->phy_ref_clk);
-   goto err_out_unregister_netdev;
+   goto err_out_clk_dis_aper;
}
 
ret = clk_prepare_enable(lp->phy_ref_clk);
if (ret) {
dev_err(>dev, "Unable to enable device clock.\n");
-   goto err_out_unregister_netdev;
+   goto err_out_clk_dis_aper;
}
 
lp->phy_node = of_parse_phandle(lp->pdev->dev.of_node,
@@ -2880,7 +2872,7 @@ static int dwceqos_probe(struct platform_device *pdev)
ret = of_phy_register_fixed_link(lp->pdev->dev.of_node);
if (ret < 0) {
dev_err(>dev, "invalid fixed-link");
-   goto err_out_unregister_clk_notifier;
+   goto err_out_clk_dis_phy;
}
 
lp->phy_node = of_node_get(lp->pdev->dev.of_node);
@@ -2889,7 +2881,7 @@ static int dwceqos_probe(struct platform_device *pdev)
ret = of_get_phy_mode(lp->pdev->dev.of_node);
if (ret < 0) {
dev_err(>pdev->dev, "error in getting phy i/f\n");
-   goto err_out_unregister_clk_notifier;
+   goto err_out_clk_dis_phy;
}
 
lp->phy_interface = ret;
@@ -2897,14 +2889,14 @@ static int dwceqos_probe(struct platform_device *pdev)
ret = dwceqos_mii_init(lp);
if (ret) {
dev_err(>pdev->dev, "error in dwceqos_mii_init\n");
-   goto err_out_unregister_clk_notifier;
+   goto err_out_clk_dis_phy;
}
 
ret = dwceqos_mii_probe(ndev);
if (ret != 0) {
netdev_err(ndev, "mii_probe fail.\n");
ret = -ENXIO;
-   goto err_out_unregister_clk_notifier;
+   goto err_out_clk_dis_phy;
}
 
dwceqos_set_umac_addr(lp, lp->ndev->dev_addr, 0);
@@ -2922,7 +2914,7 @@ static int dwceqos_probe(struct platform_device *pdev)
if (ret) {
dev_err(>pdev->dev, "Unable to retrieve DT, error %d\n",
ret);
-   goto err_out_unregister_clk_notifier;
+   goto err_out_clk_dis_phy;
}
dev_info(>pdev->dev, "pdev->id %d, baseaddr 0x%08lx, irq %d\n",
 pdev->id, ndev->base_addr, ndev->irq);
@@ -2932,18 +2924,24 @@ static int dwceqos_probe(struct platform_device *pdev)
if (ret) {
dev_err(>pdev->dev, "Unable to request IRQ %d, error %d\n",
ndev->irq, ret);
-   goto err_out_unregister_clk_notifier;
+   goto err_out_clk_dis_phy;
}
 
if (netif_msg_probe(lp))
netdev_dbg(ndev, "net_local@%p\n", lp);
 
+   netif_napi_add(ndev, >napi, dwceqos_rx_poll, NAPI_POLL_WEIGHT);
+
+   ret = register_netdev(ndev);
+   if (ret) {
+   dev_err(>dev, "Cannot register net device, aborting.\n");
+   goto err_out_clk_dis_phy;
+   }
+
return 0;
 
-err_out_unregister_clk_notifier:
+err_out_clk_dis_phy:
clk_disable_unprepare(lp->phy_ref_clk);
-err_out_unregister_netdev:
-   unregister_netdev(ndev);
 err_out_clk_dis_aper:
clk_disable_unprepare(lp->apb_pclk);
 err_out_free_netdev:
-- 
2.1.4

Re: A potential bug in drivers/net/ethernet/synopsys/dwc_eth_qos.ko

[Lars Persson]

Hi Pavel,

Thanks for the notification. I agree that we should register the device 
after all initialization has completed. A patch will be sent shortly.


BR,
 Lars


On 09/05/2016 10:26 AM, Pavel Andrianov wrote:

Hi!

There is a potential bug in
drivers/net/ethernet/synopsys/dwc_eth_qos.ko. In dwceqos_probe there is
a registration of net device (line 2879). After that initialization of
common resources is continued (lines 2918, 2924, 2941), but at the
moment handlers from net device may be already executed.

Should the registration of net device be at the end of dwceqos_probe?

Re: A potential bug in drivers/net/ethernet/synopsys/dwc_eth_qos.ko

[Lars Persson]

Hi Pavel,

Thanks for the notification. I agree that we should register the device 
after all initialization has completed. A patch will be sent shortly.


BR,
 Lars


On 09/05/2016 10:26 AM, Pavel Andrianov wrote:

Hi!

There is a potential bug in
drivers/net/ethernet/synopsys/dwc_eth_qos.ko. In dwceqos_probe there is
a registration of net device (line 2879). After that initialization of
common resources is continued (lines 2918, 2924, 2941), but at the
moment handlers from net device may be already executed.

Should the registration of net device be at the end of dwceqos_probe?

[PATCH net] dwc_eth_qos: fix interrupt enable race

[Lars Persson]

From: Rabin Vincent <rab...@axis.com>

We currently enable interrupts before we enable NAPI. If an RX interrupt
hits before we enabled NAPI then the NAPI callback is never called and
we leave the hardware with RX interrupts disabled, which of course leads
us to never handling received packets.  Fix this by moving the interrupt
enable to after we've enable NAPI and the reclaim tasklet.

Fixes: cd5e41234729 ("dwc_eth_qos: do phy_start before resetting hardware")
Signed-off-by: Rabin Vincent <rab...@axis.com>
Signed-off-by: Lars Persson <lar...@axis.com>
---
 drivers/net/ethernet/synopsys/dwc_eth_qos.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/synopsys/dwc_eth_qos.c 
b/drivers/net/ethernet/synopsys/dwc_eth_qos.c
index 9f159a7..5a3941b 100644
--- a/drivers/net/ethernet/synopsys/dwc_eth_qos.c
+++ b/drivers/net/ethernet/synopsys/dwc_eth_qos.c
@@ -1622,13 +1622,7 @@ static void dwceqos_init_hw(struct net_local *lp)
DWCEQOS_MMC_CTRL_RSTONRD);
dwceqos_enable_mmc_interrupt(lp);
 
-   /* Enable Interrupts */
-   dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE,
- DWCEQOS_DMA_CH0_IE_NIE |
- DWCEQOS_DMA_CH0_IE_RIE | DWCEQOS_DMA_CH0_IE_TIE |
- DWCEQOS_DMA_CH0_IE_AIE |
- DWCEQOS_DMA_CH0_IE_FBEE);
-
+   dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE, 0);
dwceqos_write(lp, REG_DWCEQOS_MAC_IE, 0);
 
dwceqos_write(lp, REG_DWCEQOS_MAC_CFG, DWCEQOS_MAC_CFG_IPC |
@@ -1905,6 +1899,15 @@ static int dwceqos_open(struct net_device *ndev)
netif_start_queue(ndev);
tasklet_enable(>tx_bdreclaim_tasklet);
 
+   /* Enable Interrupts -- do this only after we enable NAPI and the
+* tasklet.
+*/
+   dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE,
+ DWCEQOS_DMA_CH0_IE_NIE |
+ DWCEQOS_DMA_CH0_IE_RIE | DWCEQOS_DMA_CH0_IE_TIE |
+ DWCEQOS_DMA_CH0_IE_AIE |
+ DWCEQOS_DMA_CH0_IE_FBEE);
+
return 0;
 }
 
-- 
2.1.4

[PATCH net] dwc_eth_qos: fix interrupt enable race

[Lars Persson]

From: Rabin Vincent 

We currently enable interrupts before we enable NAPI. If an RX interrupt
hits before we enabled NAPI then the NAPI callback is never called and
we leave the hardware with RX interrupts disabled, which of course leads
us to never handling received packets.  Fix this by moving the interrupt
enable to after we've enable NAPI and the reclaim tasklet.

Fixes: cd5e41234729 ("dwc_eth_qos: do phy_start before resetting hardware")
Signed-off-by: Rabin Vincent 
Signed-off-by: Lars Persson 
---
 drivers/net/ethernet/synopsys/dwc_eth_qos.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ethernet/synopsys/dwc_eth_qos.c 
b/drivers/net/ethernet/synopsys/dwc_eth_qos.c
index 9f159a7..5a3941b 100644
--- a/drivers/net/ethernet/synopsys/dwc_eth_qos.c
+++ b/drivers/net/ethernet/synopsys/dwc_eth_qos.c
@@ -1622,13 +1622,7 @@ static void dwceqos_init_hw(struct net_local *lp)
DWCEQOS_MMC_CTRL_RSTONRD);
dwceqos_enable_mmc_interrupt(lp);
 
-   /* Enable Interrupts */
-   dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE,
- DWCEQOS_DMA_CH0_IE_NIE |
- DWCEQOS_DMA_CH0_IE_RIE | DWCEQOS_DMA_CH0_IE_TIE |
- DWCEQOS_DMA_CH0_IE_AIE |
- DWCEQOS_DMA_CH0_IE_FBEE);
-
+   dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE, 0);
dwceqos_write(lp, REG_DWCEQOS_MAC_IE, 0);
 
dwceqos_write(lp, REG_DWCEQOS_MAC_CFG, DWCEQOS_MAC_CFG_IPC |
@@ -1905,6 +1899,15 @@ static int dwceqos_open(struct net_device *ndev)
netif_start_queue(ndev);
tasklet_enable(>tx_bdreclaim_tasklet);
 
+   /* Enable Interrupts -- do this only after we enable NAPI and the
+* tasklet.
+*/
+   dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE,
+ DWCEQOS_DMA_CH0_IE_NIE |
+ DWCEQOS_DMA_CH0_IE_RIE | DWCEQOS_DMA_CH0_IE_TIE |
+ DWCEQOS_DMA_CH0_IE_AIE |
+ DWCEQOS_DMA_CH0_IE_FBEE);
+
return 0;
 }
 
-- 
2.1.4

[PATCH 3/3] ARM: dts: artpec: set irq affinity on pmu interrupts

[Lars Persson]

The irq affinity is required for pmu interrupts.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 arch/arm/boot/dts/artpec6.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 4e40d55..3489019c 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -150,6 +150,7 @@
compatible = "arm,cortex-a9-pmu";
interrupts = ,
;
+   interrupt-affinity = <>, <>;
interrupt-parent = <>;
};
 
-- 
2.1.4

[PATCH 3/3] ARM: dts: artpec: set irq affinity on pmu interrupts

[Lars Persson]

The irq affinity is required for pmu interrupts.

Signed-off-by: Lars Persson 
---
 arch/arm/boot/dts/artpec6.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 4e40d55..3489019c 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -150,6 +150,7 @@
compatible = "arm,cortex-a9-pmu";
interrupts = ,
;
+   interrupt-affinity = <>, <>;
interrupt-parent = <>;
};
 
-- 
2.1.4

[PATCH 1/3] ARM: dts: artpec: use clock binding header

[Lars Persson]

Use defines from the clock binding header as clock indexes.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 arch/arm/boot/dts/artpec6.dtsi | 23 ---
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 3fac4c4..db41b52 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -41,6 +41,7 @@
  */
 
 #include 
+#include 
 #include "skeleton.dtsi"
 
 / {
@@ -109,14 +110,14 @@
compatible = "arm,cortex-a9-global-timer";
reg = <0xfaf00200 0x20>;
interrupts = ;
-   clocks = < 1>;
+   clocks = < ARTPEC6_CLK_CPU_PERIPH>;
};
 
timer@faf00600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xfaf00600 0x20>;
interrupts = ;
-   clocks = < 1>;
+   clocks = < ARTPEC6_CLK_CPU_PERIPH>;
status = "disabled";
};
 
@@ -157,7 +158,7 @@
ethernet: ethernet@f801 {
clock-names = "phy_ref_clk", "apb_pclk";
clocks = <_phy_ref_clk>,
-   < 4>;
+   < ARTPEC6_CLK_ETH_ACLK>;
compatible = "snps,dwc-qos-ethernet-4.10";
interrupt-parent = <>;
interrupts = ;
@@ -175,8 +176,8 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0xf8036000 0x1000>;
interrupts = ;
-   clocks = < 13>,
-   < 12>;
+   clocks = < ARTPEC6_CLK_UART_REFCLK>,
+   < ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
status = "disabled";
};
@@ -184,8 +185,8 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0xf8037000 0x1000>;
interrupts = ;
-   clocks = < 13>,
-   < 12>;
+   clocks = < ARTPEC6_CLK_UART_REFCLK>,
+   < ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
status = "disabled";
};
@@ -193,8 +194,8 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0xf8038000 0x1000>;
interrupts = ;
-   clocks = < 13>,
-   < 12>;
+   clocks = < ARTPEC6_CLK_UART_REFCLK>,
+   < ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
status = "disabled";
};
@@ -202,8 +203,8 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0xf8039000 0x1000>;
interrupts = ;
-   clocks = < 13>,
-   < 12>;
+   clocks = < ARTPEC6_CLK_UART_REFCLK>,
+   < ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
status = "disabled";
};
-- 
2.1.4

[PATCH 1/3] ARM: dts: artpec: use clock binding header

[Lars Persson]

Use defines from the clock binding header as clock indexes.

Signed-off-by: Lars Persson 
---
 arch/arm/boot/dts/artpec6.dtsi | 23 ---
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 3fac4c4..db41b52 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -41,6 +41,7 @@
  */
 
 #include 
+#include 
 #include "skeleton.dtsi"
 
 / {
@@ -109,14 +110,14 @@
compatible = "arm,cortex-a9-global-timer";
reg = <0xfaf00200 0x20>;
interrupts = ;
-   clocks = < 1>;
+   clocks = < ARTPEC6_CLK_CPU_PERIPH>;
};
 
timer@faf00600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xfaf00600 0x20>;
interrupts = ;
-   clocks = < 1>;
+   clocks = < ARTPEC6_CLK_CPU_PERIPH>;
status = "disabled";
};
 
@@ -157,7 +158,7 @@
ethernet: ethernet@f801 {
clock-names = "phy_ref_clk", "apb_pclk";
clocks = <_phy_ref_clk>,
-   < 4>;
+   < ARTPEC6_CLK_ETH_ACLK>;
compatible = "snps,dwc-qos-ethernet-4.10";
interrupt-parent = <>;
interrupts = ;
@@ -175,8 +176,8 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0xf8036000 0x1000>;
interrupts = ;
-   clocks = < 13>,
-   < 12>;
+   clocks = < ARTPEC6_CLK_UART_REFCLK>,
+   < ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
status = "disabled";
};
@@ -184,8 +185,8 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0xf8037000 0x1000>;
interrupts = ;
-   clocks = < 13>,
-   < 12>;
+   clocks = < ARTPEC6_CLK_UART_REFCLK>,
+   < ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
status = "disabled";
};
@@ -193,8 +194,8 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0xf8038000 0x1000>;
interrupts = ;
-   clocks = < 13>,
-   < 12>;
+   clocks = < ARTPEC6_CLK_UART_REFCLK>,
+   < ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
status = "disabled";
};
@@ -202,8 +203,8 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0xf8039000 0x1000>;
interrupts = ;
-   clocks = < 13>,
-   < 12>;
+   clocks = < ARTPEC6_CLK_UART_REFCLK>,
+   < ARTPEC6_CLK_UART_PCLK>;
clock-names = "uart_clk", "apb_pclk";
status = "disabled";
};
-- 
2.1.4

[PATCH 0/3] ARM: dts: artpec6.dtsi updates

[Lars Persson]

This brings the dtsi up to date with with tested and optimized settings from the
Axis tree.

Lars Persson (3):
  ARM: dts: artpec: use clock binding header
  ARM: dts: artpec: use optimized pl310 settings
  ARM: dts: artpec: set irq affinity on pmu interrupts

 arch/arm/boot/dts/artpec6.dtsi | 31 ---
 1 file changed, 20 insertions(+), 11 deletions(-)

-- 
2.1.4

[PATCH 0/3] ARM: dts: artpec6.dtsi updates

[Lars Persson]

This brings the dtsi up to date with with tested and optimized settings from the
Axis tree.

Lars Persson (3):
  ARM: dts: artpec: use clock binding header
  ARM: dts: artpec: use optimized pl310 settings
  ARM: dts: artpec: set irq affinity on pmu interrupts

 arch/arm/boot/dts/artpec6.dtsi | 31 ---
 1 file changed, 20 insertions(+), 11 deletions(-)

-- 
2.1.4

[PATCH 2/3] ARM: dts: artpec: use optimized pl310 settings

[Lars Persson]

Use the cache settings that were determined to give best performance
on artpec-6 typical workloads.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 arch/arm/boot/dts/artpec6.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index db41b52..4e40d55 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -137,6 +137,13 @@
arm,data-latency = <1 1 1>;
arm,tag-latency = <1 1 1>;
arm,filter-ranges = <0x0 0x8000>;
+   arm,double-linefill = <1>;
+   arm,double-linefill-incr = <0>;
+   arm,double-linefill-wrap = <0>;
+   prefetch-data = <1>;
+   prefetch-instr = <1>;
+   arm,prefetch-offset = <0>;
+   arm,prefetch-drop = <1>;
};
 
pmu {
-- 
2.1.4

[PATCH 2/3] ARM: dts: artpec: use optimized pl310 settings

[Lars Persson]

Use the cache settings that were determined to give best performance
on artpec-6 typical workloads.

Signed-off-by: Lars Persson 
---
 arch/arm/boot/dts/artpec6.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index db41b52..4e40d55 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -137,6 +137,13 @@
arm,data-latency = <1 1 1>;
arm,tag-latency = <1 1 1>;
arm,filter-ranges = <0x0 0x8000>;
+   arm,double-linefill = <1>;
+   arm,double-linefill-incr = <0>;
+   arm,double-linefill-wrap = <0>;
+   prefetch-data = <1>;
+   prefetch-instr = <1>;
+   arm,prefetch-offset = <0>;
+   arm,prefetch-drop = <1>;
};
 
pmu {
-- 
2.1.4

Re: [PATCH] kbuild: do not add srctree to sysroot relative includes

[Lars Persson]

On 08/16/2016 01:59 PM, Michal Marek wrote:

On 2016-08-16 13:40, Lars Persson wrote:

We need to filter out also -I=/path to allow sysroot relative
include paths in the makefiles of external modules.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 scripts/Kbuild.include | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index 1792198..ffe5c6c 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -206,7 +206,7 @@ hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
 # Prefix -I with $(srctree) if it is not an absolute path.
 # skip if -I has no parameter
 addtree = $(if $(patsubst -I%,%,$(1)), \
-$(if $(filter-out -I/% -I./% -I../%,$(1)),$(patsubst 
-I%,-I$(srctree)/%,$(1)),$(1)))
+$(if $(filter-out -I/% -I./% -I../% -I=%,$(1)),$(patsubst 
-I%,-I$(srctree)/%,$(1)),$(1)))


Hi Lars,

Two questions: 1) Where is the -I=/... syntax documented? I could not
find it gcc docs.


You should find this in your gcc manual:
If dir begins with "=", then the "=" will be replaced by the sysroot 
prefix; see --sysroot and -isysroot.



2) Why do these Makefiles use --sysroot at all? The

kernel does not use any system libraries and the host programs are
compiled for the host architecture.


One use-case is with the yocto build system. Suppose we have two kernel 
modules A and B. A installs header files into the sysroot that B will 
include.



- Lars

Re: [PATCH] kbuild: do not add srctree to sysroot relative includes

[Lars Persson]

On 08/16/2016 01:59 PM, Michal Marek wrote:

On 2016-08-16 13:40, Lars Persson wrote:

We need to filter out also -I=/path to allow sysroot relative
include paths in the makefiles of external modules.

Signed-off-by: Lars Persson 
---
 scripts/Kbuild.include | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index 1792198..ffe5c6c 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -206,7 +206,7 @@ hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
 # Prefix -I with $(srctree) if it is not an absolute path.
 # skip if -I has no parameter
 addtree = $(if $(patsubst -I%,%,$(1)), \
-$(if $(filter-out -I/% -I./% -I../%,$(1)),$(patsubst 
-I%,-I$(srctree)/%,$(1)),$(1)))
+$(if $(filter-out -I/% -I./% -I../% -I=%,$(1)),$(patsubst 
-I%,-I$(srctree)/%,$(1)),$(1)))


Hi Lars,

Two questions: 1) Where is the -I=/... syntax documented? I could not
find it gcc docs.


You should find this in your gcc manual:
If dir begins with "=", then the "=" will be replaced by the sysroot 
prefix; see --sysroot and -isysroot.



2) Why do these Makefiles use --sysroot at all? The

kernel does not use any system libraries and the host programs are
compiled for the host architecture.


One use-case is with the yocto build system. Suppose we have two kernel 
modules A and B. A installs header files into the sysroot that B will 
include.



- Lars

[PATCH] kbuild: do not add srctree to sysroot relative includes

[Lars Persson]

We need to filter out also -I=/path to allow sysroot relative
include paths in the makefiles of external modules.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 scripts/Kbuild.include | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index 1792198..ffe5c6c 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -206,7 +206,7 @@ hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
 # Prefix -I with $(srctree) if it is not an absolute path.
 # skip if -I has no parameter
 addtree = $(if $(patsubst -I%,%,$(1)), \
-$(if $(filter-out -I/% -I./% -I../%,$(1)),$(patsubst 
-I%,-I$(srctree)/%,$(1)),$(1)))
+$(if $(filter-out -I/% -I./% -I../% -I=%,$(1)),$(patsubst 
-I%,-I$(srctree)/%,$(1)),$(1)))
 
 # Find all -I options and call addtree
 flags = $(foreach o,$($(1)),$(if $(filter -I%,$(o)),$(call addtree,$(o)),$(o)))
-- 
2.1.4

[PATCH] kbuild: do not add srctree to sysroot relative includes

[Lars Persson]

We need to filter out also -I=/path to allow sysroot relative
include paths in the makefiles of external modules.

Signed-off-by: Lars Persson 
---
 scripts/Kbuild.include | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index 1792198..ffe5c6c 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -206,7 +206,7 @@ hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
 # Prefix -I with $(srctree) if it is not an absolute path.
 # skip if -I has no parameter
 addtree = $(if $(patsubst -I%,%,$(1)), \
-$(if $(filter-out -I/% -I./% -I../%,$(1)),$(patsubst 
-I%,-I$(srctree)/%,$(1)),$(1)))
+$(if $(filter-out -I/% -I./% -I../% -I=%,$(1)),$(patsubst 
-I%,-I$(srctree)/%,$(1)),$(1)))
 
 # Find all -I options and call addtree
 flags = $(foreach o,$($(1)),$(if $(filter -I%,$(o)),$(call addtree,$(o)),$(o)))
-- 
2.1.4

Re: [PATCH v2] ARM: dts: artpec: update clock bindings in artpec6.dtsi

[Lars Persson]

> 24 apr. 2016 kl. 01:31 skrev Arnd Bergmann <a...@arndb.de>:
> 
>> On Monday 14 March 2016, Lars Persson wrote:
>> The clock binding for the main clock controller was changed to an
>> indexed controller style binding on request of the clk
>> maintainers. This updates the dtsi to use the new bindings.
>> 
>> Signed-off-by: Lars Persson <lar...@axis.com>
>> ---
>> v2: Use numerical clock indexes to enable merge before the clock driver 
>> bindings
>> are in the tree.
>> 
>> arch/arm/boot/dts/artpec6.dtsi | 99 
>> +-
>> 1 file changed, 20 insertions(+), 79 deletions(-)
> 
> I found this patch while going through stuff that had not been applied yet.
> Is this still the latest version that we should apply for v4.7?
> 
>Arnd

Yes it the latest. The clock driver will hit the tree in 4.7-rc1, not until 
then can we use the binding header file.

Thanks.

- Lars

Re: [PATCH v2] ARM: dts: artpec: update clock bindings in artpec6.dtsi

[Lars Persson]

> 24 apr. 2016 kl. 01:31 skrev Arnd Bergmann :
> 
>> On Monday 14 March 2016, Lars Persson wrote:
>> The clock binding for the main clock controller was changed to an
>> indexed controller style binding on request of the clk
>> maintainers. This updates the dtsi to use the new bindings.
>> 
>> Signed-off-by: Lars Persson 
>> ---
>> v2: Use numerical clock indexes to enable merge before the clock driver 
>> bindings
>> are in the tree.
>> 
>> arch/arm/boot/dts/artpec6.dtsi | 99 
>> +-
>> 1 file changed, 20 insertions(+), 79 deletions(-)
> 
> I found this patch while going through stuff that had not been applied yet.
> Is this still the latest version that we should apply for v4.7?
> 
>Arnd

Yes it the latest. The clock driver will hit the tree in 4.7-rc1, not until 
then can we use the binding header file.

Thanks.

- Lars

[PATCH net v3] net: sched: do not requeue a NULL skb

[Lars Persson]

A failure in validate_xmit_skb_list() triggered an unconditional call
to dev_requeue_skb with skb=NULL. This slowly grows the queue
discipline's qlen count until all traffic through the queue stops.

We take the optimistic approach and continue running the queue after a
failure since it is unknown if later packets also will fail in the
validate path.

Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-by: Lars Persson <lar...@axis.com>
---
v3: After a discussion with Eric and Cong I went back to v1 and added the
likely() for the common path.
---
 net/sched/sch_generic.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c
index f18c350..80742ed 100644
--- a/net/sched/sch_generic.c
+++ b/net/sched/sch_generic.c
@@ -159,12 +159,15 @@ int sch_direct_xmit(struct sk_buff *skb, struct Qdisc *q,
if (validate)
skb = validate_xmit_skb_list(skb, dev);
 
-   if (skb) {
+   if (likely(skb)) {
HARD_TX_LOCK(dev, txq, smp_processor_id());
if (!netif_xmit_frozen_or_stopped(txq))
skb = dev_hard_start_xmit(skb, dev, txq, );
 
HARD_TX_UNLOCK(dev, txq);
+   } else {
+   spin_lock(root_lock);
+   return qdisc_qlen(q);
}
spin_lock(root_lock);
 
-- 
2.1.4

[PATCH net v3] net: sched: do not requeue a NULL skb

[Lars Persson]

A failure in validate_xmit_skb_list() triggered an unconditional call
to dev_requeue_skb with skb=NULL. This slowly grows the queue
discipline's qlen count until all traffic through the queue stops.

We take the optimistic approach and continue running the queue after a
failure since it is unknown if later packets also will fail in the
validate path.

Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-by: Lars Persson 
---
v3: After a discussion with Eric and Cong I went back to v1 and added the
likely() for the common path.
---
 net/sched/sch_generic.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c
index f18c350..80742ed 100644
--- a/net/sched/sch_generic.c
+++ b/net/sched/sch_generic.c
@@ -159,12 +159,15 @@ int sch_direct_xmit(struct sk_buff *skb, struct Qdisc *q,
if (validate)
skb = validate_xmit_skb_list(skb, dev);
 
-   if (skb) {
+   if (likely(skb)) {
HARD_TX_LOCK(dev, txq, smp_processor_id());
if (!netif_xmit_frozen_or_stopped(txq))
skb = dev_hard_start_xmit(skb, dev, txq, );
 
HARD_TX_UNLOCK(dev, txq);
+   } else {
+   spin_lock(root_lock);
+   return qdisc_qlen(q);
}
spin_lock(root_lock);
 
-- 
2.1.4

Re: [PATCH net v2] net: sched: do not requeue a NULL skb

[Lars Persson]

On 04/11/2016 04:22 PM, Eric Dumazet wrote:

On Mon, 2016-04-11 at 15:38 +0200, Lars Persson wrote:


I though it would be prudent because the queue can be non-empty even for
the case of skb=NULL. So should it be there in this patch, another patch
or not at all ?


Then maybe change return code ?

It seems strange that a validate_xmit_skb_list() failure stops the
__qdisc_run() loop but schedules another round.




It was suggested by Cong Wang to return 0 in order to stop the loop. Do 
you guys agree that the loop should be stopped for such failures ? Then 
I will put the schedule call inside the if as you proposed earlier.


- Lars

Re: [PATCH net v2] net: sched: do not requeue a NULL skb

[Lars Persson]

On 04/11/2016 04:22 PM, Eric Dumazet wrote:

On Mon, 2016-04-11 at 15:38 +0200, Lars Persson wrote:


I though it would be prudent because the queue can be non-empty even for
the case of skb=NULL. So should it be there in this patch, another patch
or not at all ?


Then maybe change return code ?

It seems strange that a validate_xmit_skb_list() failure stops the
__qdisc_run() loop but schedules another round.




It was suggested by Cong Wang to return 0 in order to stop the loop. Do 
you guys agree that the loop should be stopped for such failures ? Then 
I will put the schedule call inside the if as you proposed earlier.


- Lars

Re: [PATCH net v2] net: sched: do not requeue a NULL skb

[Lars Persson]

On 04/11/2016 03:23 PM, Eric Dumazet wrote:

On Mon, 2016-04-11 at 08:24 +0200, Lars Persson wrote:

A failure in validate_xmit_skb_list() triggered an unconditional call
to dev_requeue_skb with skb=NULL. This slowly grows the queue
discipline's qlen count until all traffic through the queue stops.

By introducing a NULL check in dev_requeue_skb it was also necessary
to make the __netif_schedule call conditional to avoid scheduling an
empty queue.

Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-by: Lars Persson <lar...@axis.com>
---
  net/sched/sch_generic.c | 11 +++
  1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c
index f18c350..4e6a79c 100644
--- a/net/sched/sch_generic.c
+++ b/net/sched/sch_generic.c
@@ -47,10 +47,13 @@ EXPORT_SYMBOL(default_qdisc_ops);

  static inline int dev_requeue_skb(struct sk_buff *skb, struct Qdisc *q)
  {
-   q->gso_skb = skb;
-   q->qstats.requeues++;
-   q->q.qlen++; /* it's still part of the queue */
-   __netif_schedule(q);
+   if (skb) {
+   q->gso_skb = skb;
+   q->qstats.requeues++;
+   q->q.qlen++; /* it's still part of the queue */
+   }
+   if (qdisc_qlen(q))
+   __netif_schedule(q);

return 0;
  }



Please always CC patch author when fixing a bug.

Why adding the if (qdisc_qlen(q)) extra test ?

This seems unrelated to the bug fix, and probably should be part of a
second patch targeting net-next tree.


I though it would be prudent because the queue can be non-empty even for 
the case of skb=NULL. So should it be there in this patch, another patch 
or not at all ?




Also please add a likely() clause

if (likely(skb)) {
 q->gso_skb = skb;
 q->qstats.requeues++;
 q->q.qlen++;/* it's still part of the queue */
 __netif_schedule(q);
}


Will fix.


Thanks !

Re: [PATCH net v2] net: sched: do not requeue a NULL skb

[Lars Persson]

On 04/11/2016 03:23 PM, Eric Dumazet wrote:

On Mon, 2016-04-11 at 08:24 +0200, Lars Persson wrote:

A failure in validate_xmit_skb_list() triggered an unconditional call
to dev_requeue_skb with skb=NULL. This slowly grows the queue
discipline's qlen count until all traffic through the queue stops.

By introducing a NULL check in dev_requeue_skb it was also necessary
to make the __netif_schedule call conditional to avoid scheduling an
empty queue.

Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-by: Lars Persson 
---
  net/sched/sch_generic.c | 11 +++
  1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c
index f18c350..4e6a79c 100644
--- a/net/sched/sch_generic.c
+++ b/net/sched/sch_generic.c
@@ -47,10 +47,13 @@ EXPORT_SYMBOL(default_qdisc_ops);

  static inline int dev_requeue_skb(struct sk_buff *skb, struct Qdisc *q)
  {
-   q->gso_skb = skb;
-   q->qstats.requeues++;
-   q->q.qlen++; /* it's still part of the queue */
-   __netif_schedule(q);
+   if (skb) {
+   q->gso_skb = skb;
+   q->qstats.requeues++;
+   q->q.qlen++; /* it's still part of the queue */
+   }
+   if (qdisc_qlen(q))
+   __netif_schedule(q);

return 0;
  }



Please always CC patch author when fixing a bug.

Why adding the if (qdisc_qlen(q)) extra test ?

This seems unrelated to the bug fix, and probably should be part of a
second patch targeting net-next tree.


I though it would be prudent because the queue can be non-empty even for 
the case of skb=NULL. So should it be there in this patch, another patch 
or not at all ?




Also please add a likely() clause

if (likely(skb)) {
 q->gso_skb = skb;
 q->qstats.requeues++;
 q->q.qlen++;/* it's still part of the queue */
 __netif_schedule(q);
}


Will fix.


Thanks !

[PATCH net v2] net: sched: do not requeue a NULL skb

[Lars Persson]

A failure in validate_xmit_skb_list() triggered an unconditional call
to dev_requeue_skb with skb=NULL. This slowly grows the queue
discipline's qlen count until all traffic through the queue stops.

By introducing a NULL check in dev_requeue_skb it was also necessary
to make the __netif_schedule call conditional to avoid scheduling an
empty queue.

Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-by: Lars Persson <lar...@axis.com>
---
 net/sched/sch_generic.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c
index f18c350..4e6a79c 100644
--- a/net/sched/sch_generic.c
+++ b/net/sched/sch_generic.c
@@ -47,10 +47,13 @@ EXPORT_SYMBOL(default_qdisc_ops);
 
 static inline int dev_requeue_skb(struct sk_buff *skb, struct Qdisc *q)
 {
-   q->gso_skb = skb;
-   q->qstats.requeues++;
-   q->q.qlen++;/* it's still part of the queue */
-   __netif_schedule(q);
+   if (skb) {
+   q->gso_skb = skb;
+   q->qstats.requeues++;
+   q->q.qlen++;/* it's still part of the queue */
+   }
+   if (qdisc_qlen(q))
+   __netif_schedule(q);
 
return 0;
 }
-- 
2.1.4

[PATCH net v2] net: sched: do not requeue a NULL skb

[Lars Persson]

A failure in validate_xmit_skb_list() triggered an unconditional call
to dev_requeue_skb with skb=NULL. This slowly grows the queue
discipline's qlen count until all traffic through the queue stops.

By introducing a NULL check in dev_requeue_skb it was also necessary
to make the __netif_schedule call conditional to avoid scheduling an
empty queue.

Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-by: Lars Persson 
---
 net/sched/sch_generic.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c
index f18c350..4e6a79c 100644
--- a/net/sched/sch_generic.c
+++ b/net/sched/sch_generic.c
@@ -47,10 +47,13 @@ EXPORT_SYMBOL(default_qdisc_ops);
 
 static inline int dev_requeue_skb(struct sk_buff *skb, struct Qdisc *q)
 {
-   q->gso_skb = skb;
-   q->qstats.requeues++;
-   q->q.qlen++;/* it's still part of the queue */
-   __netif_schedule(q);
+   if (skb) {
+   q->gso_skb = skb;
+   q->qstats.requeues++;
+   q->q.qlen++;/* it's still part of the queue */
+   }
+   if (qdisc_qlen(q))
+   __netif_schedule(q);
 
return 0;
 }
-- 
2.1.4

[PATCH net] net: sched: do not requeue a NULL skb

[Lars Persson]

A failure in validate_xmit_skb_list() triggered an unconditional call
to dev_requeue_skb with skb=NULL. This slowly grows the queue
discipline's qlen count until all traffic through the queue stops.

Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-by: Lars Persson <lar...@axis.com>
---
 net/sched/sch_generic.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c
index f18c350..1031536 100644
--- a/net/sched/sch_generic.c
+++ b/net/sched/sch_generic.c
@@ -165,6 +165,9 @@ int sch_direct_xmit(struct sk_buff *skb, struct Qdisc *q,
skb = dev_hard_start_xmit(skb, dev, txq, );
 
HARD_TX_UNLOCK(dev, txq);
+   } else {
+   spin_lock(root_lock);
+   return qdisc_qlen(q);
}
spin_lock(root_lock);
 
-- 
2.1.4

[PATCH net] net: sched: do not requeue a NULL skb

[Lars Persson]

A failure in validate_xmit_skb_list() triggered an unconditional call
to dev_requeue_skb with skb=NULL. This slowly grows the queue
discipline's qlen count until all traffic through the queue stops.

Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-by: Lars Persson 
---
 net/sched/sch_generic.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c
index f18c350..1031536 100644
--- a/net/sched/sch_generic.c
+++ b/net/sched/sch_generic.c
@@ -165,6 +165,9 @@ int sch_direct_xmit(struct sk_buff *skb, struct Qdisc *q,
skb = dev_hard_start_xmit(skb, dev, txq, );
 
HARD_TX_UNLOCK(dev, txq);
+   } else {
+   spin_lock(root_lock);
+   return qdisc_qlen(q);
}
spin_lock(root_lock);
 
-- 
2.1.4

[PATCH v6 1/2] clk: add device tree binding for Artpec-6 clock controller

[Lars Persson]

Add device tree documentation for the main clock controller in the
Artpec-6 SoC.

Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Lars Persson <lar...@axis.com>
---
 .../devicetree/bindings/clock/artpec6.txt  | 41 ++
 include/dt-bindings/clock/axis,artpec6-clkctrl.h   | 38 
 2 files changed, 79 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
 create mode 100644 include/dt-bindings/clock/axis,artpec6-clkctrl.h

diff --git a/Documentation/devicetree/bindings/clock/artpec6.txt 
b/Documentation/devicetree/bindings/clock/artpec6.txt
new file mode 100644
index 000..9ba9bd0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/artpec6.txt
@@ -0,0 +1,41 @@
+* Clock bindings for Axis ARTPEC-6 chip
+
+The bindings are based on the clock provider binding in
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+External clocks:
+
+
+There are two external inputs to the main clock controller which should be
+provided using the common clock bindings.
+- "sys_refclk": External 50 Mhz oscillator (required)
+- "i2s_refclk": Alternate audio reference clock (optional).
+
+Main clock controller
+-
+
+Required properties:
+- #clock-cells: Should be <1>
+  See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid 
identifiers.
+- compatible: Should be "axis,artpec6-clkctrl"
+- reg: Must contain the base address and length of the system controller
+- clocks:  Must contain a phandle entry for each clock in clock-names
+- clock-names: Must include the external oscillator ("sys_refclk"). Optional
+  ones are the audio reference clock ("i2s_refclk") and the audio fractional
+  dividers ("frac_clk0" and "frac_clk1").
+
+Examples:
+
+ext_clk: ext_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <5000>;
+};
+
+clkctrl: clkctrl {
+   #clock-cells = <1>;
+   compatible = "axis,artpec6-clkctrl";
+   reg = <0xf800 0x48>;
+   clocks = <_clk>;
+   clock-names = "sys_refclk";
+};
diff --git a/include/dt-bindings/clock/axis,artpec6-clkctrl.h 
b/include/dt-bindings/clock/axis,artpec6-clkctrl.h
new file mode 100644
index 000..f9f04dc
--- /dev/null
+++ b/include/dt-bindings/clock/axis,artpec6-clkctrl.h
@@ -0,0 +1,38 @@
+/*
+ * ARTPEC-6 clock controller indexes
+ *
+ * Copyright 2016 Axis Comunications AB.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+
+#define ARTPEC6_CLK_CPU0
+#define ARTPEC6_CLK_CPU_PERIPH 1
+#define ARTPEC6_CLK_NAND_CLKA  2
+#define ARTPEC6_CLK_NAND_CLKB  3
+#define ARTPEC6_CLK_ETH_ACLK   4
+#define ARTPEC6_CLK_DMA_ACLK   5
+#define ARTPEC6_CLK_PTP_REF6
+#define ARTPEC6_CLK_SD_PCLK7
+#define ARTPEC6_CLK_SD_IMCLK   8
+#define ARTPEC6_CLK_I2S_HST9
+#define ARTPEC6_CLK_I2S0_CLK   10
+#define ARTPEC6_CLK_I2S1_CLK   11
+#define ARTPEC6_CLK_UART_PCLK  12
+#define ARTPEC6_CLK_UART_REFCLK13
+#define ARTPEC6_CLK_I2C14
+#define ARTPEC6_CLK_SPI_PCLK   15
+#define ARTPEC6_CLK_SPI_SSPCLK 16
+#define ARTPEC6_CLK_SYS_TIMER  17
+#define ARTPEC6_CLK_FRACDIV_IN 18
+#define ARTPEC6_CLK_DBG_PCLK   19
+
+/* This must be the highest clock index plus one. */
+#define ARTPEC6_CLK_NUMCLOCKS  20
+
+#endif
-- 
2.1.4

[PATCH v6 1/2] clk: add device tree binding for Artpec-6 clock controller

[Lars Persson]

Add device tree documentation for the main clock controller in the
Artpec-6 SoC.

Acked-by: Rob Herring 
Signed-off-by: Lars Persson 
---
 .../devicetree/bindings/clock/artpec6.txt  | 41 ++
 include/dt-bindings/clock/axis,artpec6-clkctrl.h   | 38 
 2 files changed, 79 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
 create mode 100644 include/dt-bindings/clock/axis,artpec6-clkctrl.h

diff --git a/Documentation/devicetree/bindings/clock/artpec6.txt 
b/Documentation/devicetree/bindings/clock/artpec6.txt
new file mode 100644
index 000..9ba9bd0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/artpec6.txt
@@ -0,0 +1,41 @@
+* Clock bindings for Axis ARTPEC-6 chip
+
+The bindings are based on the clock provider binding in
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+External clocks:
+
+
+There are two external inputs to the main clock controller which should be
+provided using the common clock bindings.
+- "sys_refclk": External 50 Mhz oscillator (required)
+- "i2s_refclk": Alternate audio reference clock (optional).
+
+Main clock controller
+-
+
+Required properties:
+- #clock-cells: Should be <1>
+  See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid 
identifiers.
+- compatible: Should be "axis,artpec6-clkctrl"
+- reg: Must contain the base address and length of the system controller
+- clocks:  Must contain a phandle entry for each clock in clock-names
+- clock-names: Must include the external oscillator ("sys_refclk"). Optional
+  ones are the audio reference clock ("i2s_refclk") and the audio fractional
+  dividers ("frac_clk0" and "frac_clk1").
+
+Examples:
+
+ext_clk: ext_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <5000>;
+};
+
+clkctrl: clkctrl {
+   #clock-cells = <1>;
+   compatible = "axis,artpec6-clkctrl";
+   reg = <0xf800 0x48>;
+   clocks = <_clk>;
+   clock-names = "sys_refclk";
+};
diff --git a/include/dt-bindings/clock/axis,artpec6-clkctrl.h 
b/include/dt-bindings/clock/axis,artpec6-clkctrl.h
new file mode 100644
index 000..f9f04dc
--- /dev/null
+++ b/include/dt-bindings/clock/axis,artpec6-clkctrl.h
@@ -0,0 +1,38 @@
+/*
+ * ARTPEC-6 clock controller indexes
+ *
+ * Copyright 2016 Axis Comunications AB.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+
+#define ARTPEC6_CLK_CPU0
+#define ARTPEC6_CLK_CPU_PERIPH 1
+#define ARTPEC6_CLK_NAND_CLKA  2
+#define ARTPEC6_CLK_NAND_CLKB  3
+#define ARTPEC6_CLK_ETH_ACLK   4
+#define ARTPEC6_CLK_DMA_ACLK   5
+#define ARTPEC6_CLK_PTP_REF6
+#define ARTPEC6_CLK_SD_PCLK7
+#define ARTPEC6_CLK_SD_IMCLK   8
+#define ARTPEC6_CLK_I2S_HST9
+#define ARTPEC6_CLK_I2S0_CLK   10
+#define ARTPEC6_CLK_I2S1_CLK   11
+#define ARTPEC6_CLK_UART_PCLK  12
+#define ARTPEC6_CLK_UART_REFCLK13
+#define ARTPEC6_CLK_I2C14
+#define ARTPEC6_CLK_SPI_PCLK   15
+#define ARTPEC6_CLK_SPI_SSPCLK 16
+#define ARTPEC6_CLK_SYS_TIMER  17
+#define ARTPEC6_CLK_FRACDIV_IN 18
+#define ARTPEC6_CLK_DBG_PCLK   19
+
+/* This must be the highest clock index plus one. */
+#define ARTPEC6_CLK_NUMCLOCKS  20
+
+#endif
-- 
2.1.4

[PATCH v6 0/2] clk: Add Artpec-6 SoC support

[Lars Persson]

Add clock support for the Artpec-6 SoC port. The ARM parts are merged in
4.6-rc1.

Changes since v5:
- Improved code formatting.
- Pass device pointer when registering the clocks.
- Detect registration failures in the probe function.

Changes since v4:
- Update the maintainer entry with the correct clock directory.
- Implement split clock registration with early clocks through CLK_OF_DECLARE
  and deferrable clocks through a platform driver.

Changes since v3:
- The binding was corrected to handle two fractional divider clocks as input to
  the clock controller.
- Updated clk-artpec6.c to handle a distinct fractional divider input for each
  i2s clock mux.

Changes since v2:
- Moved axis,artpec6-clkctrl.h to the first patch with the DT bindings.

Changes since v1:
- The driver now provides all clocks from the main clock controller block
  through one DT node.
- Added a header file for the clock indexes.
- Refer to clock-bindings.txt in the bindings document.

Lars Persson (2):
  clk: add device tree binding for Artpec-6 clock controller
  clk: add artpec-6 clock controller

Lars Persson (2):
  clk: add device tree binding for Artpec-6 clock controller
  clk: add artpec-6 clock controller

 .../devicetree/bindings/clock/artpec6.txt  |  41 
 MAINTAINERS|   2 +-
 drivers/clk/Makefile   |   1 +
 drivers/clk/axis/Makefile  |   1 +
 drivers/clk/axis/clk-artpec6.c | 242 +
 include/dt-bindings/clock/axis,artpec6-clkctrl.h   |  38 
 6 files changed, 324 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
 create mode 100644 drivers/clk/axis/Makefile
 create mode 100644 drivers/clk/axis/clk-artpec6.c
 create mode 100644 include/dt-bindings/clock/axis,artpec6-clkctrl.h

-- 
2.1.4

[PATCH v6 2/2] clk: add artpec-6 clock controller

[Lars Persson]

Add a driver for the main clock controller of the Artpec-6 Soc.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 MAINTAINERS|   2 +-
 drivers/clk/Makefile   |   1 +
 drivers/clk/axis/Makefile  |   1 +
 drivers/clk/axis/clk-artpec6.c | 242 +
 4 files changed, 245 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/axis/Makefile
 create mode 100644 drivers/clk/axis/clk-artpec6.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 378ebff..074e39e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -973,7 +973,7 @@ S:  Maintained
 L: linux-arm-ker...@axis.com
 F: arch/arm/mach-artpec
 F: arch/arm/boot/dts/artpec6*
-F: drivers/clk/clk-artpec6.c
+F: drivers/clk/axis
 
 ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
 M: Nicolas Ferre <nicolas.fe...@atmel.com>
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 46869d6..ca9aa7b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X)   += clk-wm831x.o
 obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
 obj-$(CONFIG_COMMON_CLK_PWM)   += clk-pwm.o
 obj-$(CONFIG_COMMON_CLK_AT91)  += at91/
+obj-$(CONFIG_ARCH_ARTPEC)  += axis/
 obj-y  += bcm/
 obj-$(CONFIG_ARCH_BERLIN)  += berlin/
 obj-$(CONFIG_ARCH_HISI)+= hisilicon/
diff --git a/drivers/clk/axis/Makefile b/drivers/clk/axis/Makefile
new file mode 100644
index 000..628c9d3
--- /dev/null
+++ b/drivers/clk/axis/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MACH_ARTPEC6) += clk-artpec6.o
diff --git a/drivers/clk/axis/clk-artpec6.c b/drivers/clk/axis/clk-artpec6.c
new file mode 100644
index 000..2554d6e
--- /dev/null
+++ b/drivers/clk/axis/clk-artpec6.c
@@ -0,0 +1,242 @@
+/*
+ * ARTPEC-6 clock initialization
+ *
+ * Copyright 2015-2016 Axis Comunications AB.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define NUM_I2S_CLOCKS 2
+
+struct artpec6_clkctrl_drvdata {
+   struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS];
+   void __iomem *syscon_base;
+   struct clk_onecell_data clk_data;
+   spinlock_t i2scfg_lock;
+};
+
+static struct artpec6_clkctrl_drvdata *clkdata;
+
+static const char *const i2s_clk_names[NUM_I2S_CLOCKS] = {
+   "i2s0",
+   "i2s1",
+};
+
+static const int i2s_clk_indexes[NUM_I2S_CLOCKS] = {
+   ARTPEC6_CLK_I2S0_CLK,
+   ARTPEC6_CLK_I2S1_CLK,
+};
+
+static void of_artpec6_clkctrl_setup(struct device_node *np)
+{
+   int i;
+   const char *sys_refclk_name;
+   u32 pll_mode, pll_m, pll_n;
+   struct clk **clks;
+
+   /* Mandatory parent clock. */
+   i = of_property_match_string(np, "clock-names", "sys_refclk");
+   if (i < 0)
+   return;
+
+   sys_refclk_name = of_clk_get_parent_name(np, i);
+
+   clkdata = kzalloc(sizeof(*clkdata), GFP_KERNEL);
+   if (!clkdata)
+   return;
+
+   clks = clkdata->clk_table;
+
+   for (i = 0; i < ARTPEC6_CLK_NUMCLOCKS; ++i)
+   clks[i] = ERR_PTR(-EPROBE_DEFER);
+
+   clkdata->syscon_base = of_iomap(np, 0);
+   BUG_ON(clkdata->syscon_base == NULL);
+
+   /* Read PLL1 factors configured by boot strap pins. */
+   pll_mode = (readl(clkdata->syscon_base) >> 6) & 3;
+   switch (pll_mode) {
+   case 0: /* DDR3-2133 mode */
+   pll_m = 4;
+   pll_n = 85;
+   break;
+   case 1: /* DDR3-1866 mode */
+   pll_m = 6;
+   pll_n = 112;
+   break;
+   case 2: /* DDR3-1600 mode */
+   pll_m = 4;
+   pll_n = 64;
+   break;
+   case 3: /* DDR3-1333 mode */
+   pll_m = 8;
+   pll_n = 106;
+   break;
+   }
+
+   clks[ARTPEC6_CLK_CPU] =
+   clk_register_fixed_factor(NULL, "cpu", sys_refclk_name, 0, pll_n,
+ pll_m);
+   clks[ARTPEC6_CLK_CPU_PERIPH] =
+   clk_register_fixed_factor(NULL, "cpu_periph", "cpu", 0, 1, 2);
+
+   /* EPROBE_DEFER on the apb_clock is not handled in amba devices. */
+   clks[ARTPEC6_CLK_UART_PCLK] =
+   clk_register_fixed_factor(NULL, "uart_pclk", "cpu", 0, 1, 8);
+   clks[ARTPEC6_CLK_UART_REFCLK] =
+   clk_register_fixed_rate(NULL, "uart_ref", sys_refclk_name, 0,
+   5000);
+
+   clks[ARTPEC6_CLK_SPI_PCLK] =
+   clk_register_fixed_factor(NULL, &q

[PATCH v6 0/2] clk: Add Artpec-6 SoC support

[Lars Persson]

Add clock support for the Artpec-6 SoC port. The ARM parts are merged in
4.6-rc1.

Changes since v5:
- Improved code formatting.
- Pass device pointer when registering the clocks.
- Detect registration failures in the probe function.

Changes since v4:
- Update the maintainer entry with the correct clock directory.
- Implement split clock registration with early clocks through CLK_OF_DECLARE
  and deferrable clocks through a platform driver.

Changes since v3:
- The binding was corrected to handle two fractional divider clocks as input to
  the clock controller.
- Updated clk-artpec6.c to handle a distinct fractional divider input for each
  i2s clock mux.

Changes since v2:
- Moved axis,artpec6-clkctrl.h to the first patch with the DT bindings.

Changes since v1:
- The driver now provides all clocks from the main clock controller block
  through one DT node.
- Added a header file for the clock indexes.
- Refer to clock-bindings.txt in the bindings document.

Lars Persson (2):
  clk: add device tree binding for Artpec-6 clock controller
  clk: add artpec-6 clock controller

Lars Persson (2):
  clk: add device tree binding for Artpec-6 clock controller
  clk: add artpec-6 clock controller

 .../devicetree/bindings/clock/artpec6.txt  |  41 
 MAINTAINERS|   2 +-
 drivers/clk/Makefile   |   1 +
 drivers/clk/axis/Makefile  |   1 +
 drivers/clk/axis/clk-artpec6.c | 242 +
 include/dt-bindings/clock/axis,artpec6-clkctrl.h   |  38 
 6 files changed, 324 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
 create mode 100644 drivers/clk/axis/Makefile
 create mode 100644 drivers/clk/axis/clk-artpec6.c
 create mode 100644 include/dt-bindings/clock/axis,artpec6-clkctrl.h

-- 
2.1.4