Re: [PATCH v1 2/2] dt-bindings: arm: add property for coresight component name
en it would be better to add this name as an alias rather than a direct replacement. Therefore any coresight device could have an alias_name entry, that could be interrogated by a script and used as required. This avoids breaking any existing scripts using the established naming convention. 4) Any devicetree attribute should follow the , naming convention. e.g. arm,some_attribute. I agree with Alex that it may not be normal practice to add in attributes in these circumstances - this does not appear to relate to a specific hardware feature or limitation. You may wish to discuss this with the device tree maintainers. Thanks and Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
[PATCH] coresight: etm-perf: Fix define build issue when built as module
CONFIG_CORESIGHT_SOURCE_ETM4X is undefined when built as module,
CONFIG_CORESIGHT_SOURCE_ETM4X_MODULE is defined instead.
Therefore code in format_attr_contextid_show() not correctly complied
when coresight built as module.
Use IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) to correct this.
Fixes: 88f11864cf1d ("coresight: etm-perf: Support PID tracing for kernel at
EL2")
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 560baefdfed8..b2d6db78a025 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -78,7 +78,7 @@ static ssize_t format_attr_contextid_show(struct device *dev,
{
int pid_fmt = ETM_OPT_CTXTID;
-#if defined(CONFIG_CORESIGHT_SOURCE_ETM4X)
+#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X)
pid_fmt = is_kernel_in_hyp_mode() ? ETM_OPT_CTXTID2 : ETM_OPT_CTXTID;
#endif
return sprintf(page, "config:%d\n", pid_fmt);
--
2.17.1
[PATCH v7 10/10] Documentation: coresight: Add documentation for CoreSight config
Adds documentation for the CoreSight System configuration manager. Cc: Jonathan Corbet Cc: linux-...@vger.kernel.org Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- .../trace/coresight/coresight-config.rst | 244 ++ Documentation/trace/coresight/coresight.rst | 16 ++ 2 files changed, 260 insertions(+) create mode 100644 Documentation/trace/coresight/coresight-config.rst diff --git a/Documentation/trace/coresight/coresight-config.rst b/Documentation/trace/coresight/coresight-config.rst new file mode 100644 index ..a4e3ef295240 --- /dev/null +++ b/Documentation/trace/coresight/coresight-config.rst @@ -0,0 +1,244 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== +CoreSight System Configuration Manager +== + +:Author: Mike Leach +:Date: October 2020 + +Introduction + + +The CoreSight System Configuration manager is an API that allows the +programming of the CoreSight system with pre-defined configurations that +can then be easily enabled from sysfs or perf. + +Many CoreSight components can be programmed in complex ways - especially ETMs. +In addition, components can interact across the CoreSight system, often via +the cross trigger components such as CTI and CTM. These system settings can +be defined and enabled as named configurations. + + +Basic Concepts +== + +This section introduces the basic concepts of a CoreSight system configuration. + + +Features + + +A feature is a named set of programming for a CoreSight device. The programming +is device dependent, and can be defined in terms of absolute register values, +resource usage and parameter values. + +The feature is defined using a descriptor. This descriptor is used to load onto +a matching device, either when the feature is loaded into the system, or when the +CoreSight device is registered with the configuration manager. + +The load process involves interpreting the descriptor into a set of register +accesses in the driver - the resource usage and parameter descriptions +translated into appropriate register accesses. This interpretation makes it easy +and efficient for the feature to be programmed onto the device when required. + +The feature will not be active on the device until the feature is enabled, and +the device itself is enabled. When the device is enabled then enabled features +will be programmed into the device hardware. + +A feature is enabled as part of a configuration being enabled on the system. + + +Parameter Value +~~~ + +A parameter value is a named value that may be set by the user prior to the +feature being enabled that can adjust the behaviour of the operation programmed +by the feature. + +For example, this could be a count value in a programmed operation that repeats +at a given rate. When the feature is enabled then the current value of the +parameter is used in programming the device. + +The feature descriptor defines a default value for a parameter, which is used +if the user does not supply a new value. + +Users can update parameter values using the configfs API for the CoreSight +system - which is described below. + +The current value of the parameter is loaded into the device when the feature +is enabled on that device. + + +Configurations +-- + +A configuration defines a set of features that are to be used in a trace +session where the configuration is selected. For any trace session only one +configuration may be selected. + +The features defined may be on any type of device that is registered +to support system configuration. A configuration may select features to be +enabled on a class of devices - i.e. any ETMv4, or specific devices, e.g. a +specific CTI on the system. + +As with the feature, a descriptor is used to define the configuration. +This will define the features that must be enabled as part of the configuration +as well as any preset values that can be used to override default parameter +values. + + +Preset Values +~ + +Preset values are easily selectable sets of parameter values for the features +that the configuration uses. The number of values in a single preset set, equals +the sum of parameter values in the features used by the configuration. + +e.g. a configuration consists of 3 features, one has 2 parameters, one has +a single parameter, and another has no parameters. A single preset set will +therefore have 3 values. + +Presets are optionally defined by the configuration, up to 15 can be defined. +If no preset is selected, then the parameter values defined in the feature +are used as normal. + + +Operation +~ + +The following steps take place in the operation of a configuration. + +1) In this example, the configuration is 'autofdo', which has an + associated feature 'strobing' that works on ETMv4 CoreSight Devices. + +2) The configuration is enabled. For example &
[PATCH v7 09/10] coresight: syscfg: Add initial configfs support
Adds configfs subsystem and attributes to the configuration manager
to enable the listing of loaded configurations and features.
The default values of feature parameters can be accessed and altered
from these attributes to affect all installed devices using the feature.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../coresight/coresight-syscfg-configfs.c | 396 ++
.../coresight/coresight-syscfg-configfs.h | 45 ++
.../hwtracing/coresight/coresight-syscfg.c| 76
.../hwtracing/coresight/coresight-syscfg.h| 7 +
5 files changed, 526 insertions(+), 1 deletion(-)
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.c
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index ad44f0fe3069..b6c4a48140ec 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -5,7 +5,8 @@
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
coresight-sysfs.o coresight-syscfg.o coresight-config.o \
- coresight-cfg-preload.o coresight-cfg-afdo.o
+ coresight-cfg-preload.o coresight-cfg-afdo.o \
+ coresight-syscfg-configfs.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
new file mode 100644
index ..c547816b9000
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
@@ -0,0 +1,396 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Linaro Limited, All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include
+
+#include "coresight-syscfg-configfs.h"
+
+/* create a default ci_type. */
+static inline struct config_item_type *cscfg_create_ci_type(void)
+{
+ struct config_item_type *ci_type;
+
+ ci_type = devm_kzalloc(cscfg_device(), sizeof(*ci_type), GFP_KERNEL);
+ if (ci_type)
+ ci_type->ct_owner = THIS_MODULE;
+
+ return ci_type;
+}
+
+/* configurations sub-group */
+
+/* attributes for the config view group */
+static ssize_t cscfg_cfg_description_show(struct config_item *item, char *page)
+{
+ struct cscfg_fs_config *fs_config = container_of(to_config_group(item),
+struct
cscfg_fs_config, group);
+
+ return scnprintf(page, PAGE_SIZE, "%s",
fs_config->config_desc->description);
+}
+CONFIGFS_ATTR_RO(cscfg_cfg_, description);
+
+static ssize_t cscfg_cfg_feature_refs_show(struct config_item *item, char
*page)
+{
+ struct cscfg_fs_config *fs_config = container_of(to_config_group(item),
+struct
cscfg_fs_config, group);
+ const struct cscfg_config_desc *config_desc = fs_config->config_desc;
+ ssize_t ch_used = 0;
+ int i;
+
+ for (i = 0; i < config_desc->nr_feat_refs; i++)
+ ch_used += scnprintf(page + ch_used, PAGE_SIZE - ch_used,
+"%s\n", config_desc->feat_ref_names[i]);
+ return ch_used;
+}
+CONFIGFS_ATTR_RO(cscfg_cfg_, feature_refs);
+
+/* list preset values in order of features and params */
+static ssize_t cscfg_cfg_values_show(struct config_item *item, char *page)
+{
+ const struct cscfg_feature_desc *feat_desc;
+ const struct cscfg_config_desc *config_desc;
+ struct cscfg_fs_preset *fs_preset;
+ int i, j, val_idx, preset_idx;
+ ssize_t used = 0;
+
+ fs_preset = container_of(to_config_group(item), struct cscfg_fs_preset,
group);
+ config_desc = fs_preset->config_desc;
+
+ if (!config_desc->nr_presets)
+ return 0;
+
+ preset_idx = fs_preset->preset_num - 1;
+
+ /* start index on the correct array line */
+ val_idx = config_desc->nr_total_params * preset_idx;
+
+ /*
+* A set of presets is the sum of all params in used features,
+* in order of declaration of features and params in the features
+*/
+ for (i = 0; i < config_desc->nr_feat_refs; i++) {
+ feat_desc =
cscfg_get_named_feat_desc(config_desc->feat_ref_names[i]);
+ for (j = 0; j < feat_desc->nr_params; j++) {
+ used += scnprintf(page + used, PAGE_SIZE - used,
+ "%s.%s = 0x%llx ",
+ feat_desc->name,
+ feat_desc->params_desc[j].name,
+
[PATCH v7 08/10] coresight: config: Add preloaded configurations
Preload set of configurations.
This patch creates a small set of preloaded configurations and features
that are available immediately after coresight has been initialised.
The current set provides a strobing feature for ETMv4, that creates a
periodic sampling of trace by switching trace generation on and off
using counters in the ETM.
A configuration called "autofdo" is also provided that uses the 'strobing'
feature and provides a couple of preset values, selectable on the perf
command line.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../hwtracing/coresight/coresight-cfg-afdo.c | 153 ++
.../coresight/coresight-cfg-preload.c | 31
.../coresight/coresight-cfg-preload.h | 13 ++
.../hwtracing/coresight/coresight-etm4x-cfg.h | 15 ++
.../hwtracing/coresight/coresight-syscfg.c| 9 ++
.../hwtracing/coresight/coresight-syscfg.h| 1 +
7 files changed, 224 insertions(+), 1 deletion(-)
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-afdo.c
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.c
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index 9420d33b23ac..ad44f0fe3069 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -4,7 +4,8 @@
#
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
- coresight-sysfs.o coresight-syscfg.o coresight-config.o
+ coresight-sysfs.o coresight-syscfg.o coresight-config.o \
+ coresight-cfg-preload.o coresight-cfg-afdo.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-cfg-afdo.c
b/drivers/hwtracing/coresight/coresight-cfg-afdo.c
new file mode 100644
index ..84b31184252b
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-cfg-afdo.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2020 Linaro Limited. All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include "coresight-config.h"
+
+/* ETMv4 includes and features */
+#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X)
+#include "coresight-etm4x-cfg.h"
+
+/* preload configurations and features */
+
+/* preload in features for ETMv4 */
+
+/* strobe feature */
+static struct cscfg_parameter_desc strobe_params[] = {
+ {
+ .name = "window",
+ .value = 5000,
+ },
+ {
+ .name = "period",
+ .value = 1,
+ },
+};
+
+static struct cscfg_regval_desc strobe_regs[] = {
+ /* resource selectors */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCRSCTLRn(2),
+ .hw_info = ETM4_CFG_RES_SEL,
+ .val32 = 0x20001,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCRSCTLRn(3),
+ .hw_info = ETM4_CFG_RES_SEQ,
+ .val32 = 0x20002,
+ },
+ /* strobe window counter 0 - reload from param 0 */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE,
+ .offset = TRCCNTVRn(0),
+ .hw_info = ETM4_CFG_RES_CTR,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM,
+ .offset = TRCCNTRLDVRn(0),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 0,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCCNTCTLRn(0),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 0x10001,
+ },
+ /* strobe period counter 1 - reload from param 1 */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE,
+ .offset = TRCCNTVRn(1),
+ .hw_info = ETM4_CFG_RES_CTR,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM,
+ .offset = TRCCNTRLDVRn(1),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 1,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCCNTCTLRn(1),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 0x8102,
+ },
+ /* sequencer */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCSEQEVRn(0),
+ .hw_info = ETM4_CFG_RES_SEQ,
+ .val32 = 0x0081,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCSEQEVRn(1),
+
[PATCH v7 07/10] coresight: etm4x: Add complex configuration handlers to etmv4
Adds in handlers to allow the ETMv4 to use the complex configuration
support. Features and configurations can be loaded and selected in the
device.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../hwtracing/coresight/coresight-etm4x-cfg.c | 182 ++
.../hwtracing/coresight/coresight-etm4x-cfg.h | 15 ++
.../coresight/coresight-etm4x-core.c | 38 +++-
.../coresight/coresight-etm4x-sysfs.c | 3 +
5 files changed, 238 insertions(+), 3 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c
create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index 63ecfc3cf66d..9420d33b23ac 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -16,7 +16,8 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o
coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \
coresight-etm3x-sysfs.o
obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o
-coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o
+coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o \
+ coresight-etm4x-cfg.o
obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
new file mode 100644
index ..d2ea903231b2
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2020 Linaro Limited. All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include "coresight-etm4x.h"
+#include "coresight-etm4x-cfg.h"
+#include "coresight-priv.h"
+#include "coresight-syscfg.h"
+
+/* defines to associate register IDs with driver data locations */
+#define CHECKREG(cval, elem) \
+ { \
+ if (offset == cval) { \
+ reg_csdev->driver_regval = &drvcfg->elem; \
+ err = 0; \
+ break; \
+ } \
+ }
+
+#define CHECKREGIDX(cval, elem, off_idx, mask) \
+ { \
+ if (mask == cval) { \
+ reg_csdev->driver_regval = &drvcfg->elem[off_idx]; \
+ err = 0; \
+ break; \
+ } \
+ }
+
+/**
+ * etm4_cfg_map_reg_offset - validate and map the register offset into a
+ * location in the driver config struct.
+ *
+ * Limits the number of registers that can be accessed and programmed in
+ * features, to those which are used to control the trace capture parameters.
+ *
+ * Omits or limits access to those which the driver must use exclusively.
+ *
+ * Invalid offsets will result in fail code return and feature load failure.
+ *
+ * @drvdata: driver data to map into.
+ * @reg: register to map.
+ * @offset:device offset for the register
+ */
+static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
+ struct cscfg_regval_csdev *reg_csdev, u32
offset)
+{
+ int err = -EINVAL, idx;
+ struct etmv4_config *drvcfg = &drvdata->config;
+ u32 off_mask;
+
+ if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) ||
+ ((offset >= TRCSEQRSTEVR) && (offset <= TRCEXTINSELR)) ||
+ ((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) {
+ do {
+ CHECKREG(TRCEVENTCTL0R, eventctrl0);
+ CHECKREG(TRCEVENTCTL1R, eventctrl1);
+ CHECKREG(TRCSTALLCTLR, stall_ctrl);
+ CHECKREG(TRCTSCTLR, ts_ctrl);
+ CHECKREG(TRCSYNCPR, syncfreq);
+ CHECKREG(TRTLR, ccctlr);
+ CHECKREG(TRCBBCTLR, bb_ctrl);
+ CHECKREG(TRCVICTLR, vinst_ctrl);
+ CHECKREG(TRCVIIECTLR, viiectlr);
+ CHECKREG(TRCVISSCTLR, vissctlr);
+ CHECKREG(TRCVIPCSSCTLR, vipcssctlr);
+ CHECKREG(TRCSEQRSTEVR, seq_rst);
+ CHECKREG(TRCSEQSTR, seq_state);
+ CHECKREG(TRCEXTINSELR, ext_inp);
+ CHECKREG(TRCCIDCCTLR0, ctxid_mask0);
+ CHECKREG(TRCCIDCCTLR1, ctxid_mask1);
+ CHECKREG(TRCVMIDCCTLR0, vmid_mask0);
+ CHECKREG(TRCVMIDCCTLR1, vmid_mask1);
+ } while (0);
+ } else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) {
+ /*
[PATCH v7 05/10] coresight: syscfg: Add API to activate and enable configurations
Configurations are first activated, then when any coresight device is
enabled, the active configurations are checked and any matching
one is enabled.
This patch provides the activation / enable API.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../hwtracing/coresight/coresight-config.h| 2 +
.../hwtracing/coresight/coresight-syscfg.c| 172 ++
.../hwtracing/coresight/coresight-syscfg.h| 8 +
include/linux/coresight.h | 2 +
4 files changed, 184 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
index 0667581822c1..25eb6c632692 100644
--- a/drivers/hwtracing/coresight/coresight-config.h
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -127,6 +127,7 @@ struct cscfg_feature_desc {
* @nr_total_params: Sum of all parameters declared by used features
* @presets: Array of preset values.
* @event_ea: Extended attribute for perf event value
+ * @active_cnt:ref count for activate on this configuration.
*
*/
struct cscfg_config_desc {
@@ -139,6 +140,7 @@ struct cscfg_config_desc {
int nr_total_params;
const u64 *presets; /* nr_presets * nr_total_params */
struct dev_ext_attribute *event_ea;
+ atomic_t active_cnt;
};
/**
diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c
b/drivers/hwtracing/coresight/coresight-syscfg.c
index e35f8c0ac2f8..b234e45c153f 100644
--- a/drivers/hwtracing/coresight/coresight-syscfg.c
+++ b/drivers/hwtracing/coresight/coresight-syscfg.c
@@ -283,6 +283,7 @@ static int cscfg_load_config(struct cscfg_config_desc
*config_desc)
return err;
list_add(&config_desc->item, &cscfg_mgr->config_desc_list);
+ atomic_set(&config_desc->active_cnt, 0);
return 0;
}
@@ -468,6 +469,176 @@ void cscfg_unregister_csdev(struct coresight_device
*csdev)
}
EXPORT_SYMBOL_GPL(cscfg_unregister_csdev);
+/**
+ * cscfg_csdev_reset_feats - reset features for a CoreSight device.
+ *
+ * Resets all parameters and register values for any features loaded
+ * into @csdev to their default values.
+ *
+ * @csdev: The CoreSight device.
+ */
+void cscfg_csdev_reset_feats(struct coresight_device *csdev)
+{
+ struct cscfg_feature_csdev *feat_csdev;
+
+ mutex_lock(&cscfg_csdev_mutex);
+ if (list_empty(&csdev->feature_csdev_list))
+ goto unlock_exit;
+
+ list_for_each_entry(feat_csdev, &csdev->feature_csdev_list, node)
+ cscfg_reset_feat(feat_csdev);
+
+unlock_exit:
+ mutex_unlock(&cscfg_csdev_mutex);
+}
+EXPORT_SYMBOL_GPL(cscfg_csdev_reset_feats);
+
+/**
+ * cscfg_activate_config - Mark a configuration descriptor as active.
+ *
+ * This will be seen when csdev devices are enabled in the system.
+ * Only activated configurations can be enabled on individual devices.
+ * Activation protects the configuration from alteration or removal while
+ * active.
+ *
+ * Selection by hash value - generated from the configuration name when it
+ * was loaded and added to the cs_etm/configurations file system for selection
+ * by perf.
+ *
+ * Increments the configuration descriptor active count and the global active
+ * count.
+ *
+ * @cfg_hash: Hash value of the selected configuration name.
+ */
+int cscfg_activate_config(unsigned long cfg_hash)
+{
+ struct cscfg_config_desc *config_desc;
+ int err = -EINVAL;
+
+ mutex_lock(&cscfg_mutex);
+
+ list_for_each_entry(config_desc, &cscfg_mgr->config_desc_list, item) {
+ if ((unsigned long)config_desc->event_ea->var == cfg_hash) {
+ /*
+* increment the global active count - control changes
to
+* active configurations
+*/
+ atomic_inc(&cscfg_mgr->sys_active_cnt);
+
+ /*
+* mark the descriptor as active so enable config on a
+* device instance will use it
+*/
+ atomic_inc(&config_desc->active_cnt);
+
+ err = 0;
+ dev_dbg(cscfg_device(), "Activate config %s.\n",
config_desc->name);
+ break;
+ }
+ }
+ mutex_unlock(&cscfg_mutex);
+
+ return err;
+}
+EXPORT_SYMBOL_GPL(cscfg_activate_config);
+
+/**
+ * cscfg_deactivate_config - Mark a config descriptor as inactive.
+ *
+ * Decrement the configuration and global active counts.
+ *
+ * @cfg_hash: Hash value of the selected configuration name.
+ */
+void cscfg_deactivate_config(unsigned long cfg_hash)
+{
+ struct cscfg_config_desc *config_desc;
+
+ mutex_lock(&cscfg_mutex);
+
+ list_for_each_entry(config_desc, &cscfg_mgr-&
[PATCH v7 06/10] coresight: etm-perf: Update to activate selected configuration
Add calls to activate the selected configuration as perf starts
and stops the tracing session.
Signed-off-by: Mike Leach
Reviewed-by: Suzuki K Poulose
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 14 +-
drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 26b4bca156aa..560baefdfed8 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -215,6 +215,10 @@ static void free_event_data(struct work_struct *work)
/* Free the sink buffers, if there are any */
free_sink_buffer(event_data);
+ /* clear any configuration we were using */
+ if (event_data->cfg_hash)
+ cscfg_deactivate_config(event_data->cfg_hash);
+
for_each_cpu(cpu, mask) {
struct list_head **ppath;
@@ -292,7 +296,7 @@ static bool sinks_compatible(struct coresight_device *a,
static void *etm_setup_aux(struct perf_event *event, void **pages,
int nr_pages, bool overwrite)
{
- u32 id;
+ u32 id, cfg_hash;
int cpu = event->cpu;
cpumask_t *mask;
struct coresight_device *sink = NULL;
@@ -310,6 +314,14 @@ static void *etm_setup_aux(struct perf_event *event, void
**pages,
sink = user_sink = coresight_get_sink_by_id(id);
}
+ /* check if user wants a coresight configuration selected */
+ cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32);
+ if (cfg_hash) {
+ if (cscfg_activate_config(cfg_hash))
+ goto err;
+ event_data->cfg_hash = cfg_hash;
+ }
+
mask = &event_data->mask;
/*
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h
b/drivers/hwtracing/coresight/coresight-etm-perf.h
index ba617fe2217e..468f7799ab4f 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.h
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.h
@@ -49,12 +49,14 @@ struct etm_filters {
* @work: Handle to free allocated memory outside IRQ context.
* @mask: Hold the CPU(s) this event was set for.
* @snk_config:The sink configuration.
+ * @cfg_hash: The hash id of any coresight config selected.
* @path: An array of path, each slot for one CPU.
*/
struct etm_event_data {
struct work_struct work;
cpumask_t mask;
void *snk_config;
+ u32 cfg_hash;
struct list_head * __percpu *path;
};
--
2.17.1
[PATCH v7 02/10] coresight: syscfg: Add registration and feature loading for cs devices
API for individual devices to register with the syscfg management
system is added.
Devices register with matching information, and any features or
configurations that match will be loaded into the device.
The feature and configuration loading is extended so that on load these
are loaded into any currently registered devices. This allows
configuration loading after devices have been registered.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../hwtracing/coresight/coresight-config.h| 98 +
.../hwtracing/coresight/coresight-syscfg.c| 338 +-
.../hwtracing/coresight/coresight-syscfg.h| 19 +
include/linux/coresight.h | 5 +
4 files changed, 459 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
index 21aa7464dcdc..685fb46ce893 100644
--- a/drivers/hwtracing/coresight/coresight-config.h
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -139,4 +139,102 @@ struct cscfg_config_desc {
const u64 *presets; /* nr_presets * nr_total_params */
};
+/**
+ * config register instance - part of a loaded feature.
+ *maps register values to csdev driver structures
+ *
+ * @reg_desc: value to use when setting feature on device / store for
+ * readback of volatile values.
+ * @driver_regval: pointer to internal driver element used to set the value
+ * in hardware.
+ */
+struct cscfg_regval_csdev {
+ struct cscfg_regval_desc reg_desc;
+ void *driver_regval;
+};
+
+/**
+ * config parameter instance - part of a loaded feature.
+ *
+ * @feat_csdev:parent feature
+ * @reg_csdev: register value updated by this parameter.
+ * @current_value: current value of parameter - may be set by user via
+ * sysfs, or modified during device operation.
+ * @val64: true if 64 bit value
+ */
+struct cscfg_parameter_csdev {
+ struct cscfg_feature_csdev *feat_csdev;
+ struct cscfg_regval_csdev *reg_csdev;
+ u64 current_value;
+ bool val64;
+};
+
+/**
+ * Feature instance loaded into a CoreSight device.
+ *
+ * When a feature is loaded into a specific device, then this structure holds
+ * the connections between the register / parameter values used and the
+ * internal data structures that are written when the feature is enabled.
+ *
+ * Since applying a feature modifies internal data structures in the device,
+ * then we have a reference to the device spinlock to protect access to these
+ * structures (@drv_spinlock).
+ *
+ * @feat_desc: pointer to the static descriptor for this feature.
+ * @csdev: parent CoreSight device instance.
+ * @node: list entry into feature list for this device.
+ * @drv_spinlock: device spinlock for access to driver register data.
+ * @nr_params: number of parameters.
+ * @params_csdev: current parameter values on this device
+ * @nr_regs: number of registers to be programmed.
+ * @regs_csdev:Programming details for the registers
+ */
+struct cscfg_feature_csdev {
+ const struct cscfg_feature_desc *feat_desc;
+ struct coresight_device *csdev;
+ struct list_head node;
+ spinlock_t *drv_spinlock;
+ int nr_params;
+ struct cscfg_parameter_csdev *params_csdev;
+ int nr_regs;
+ struct cscfg_regval_csdev *regs_csdev;
+};
+
+/**
+ * Configuration instance when loaded into a CoreSight device.
+ *
+ * The instance contains references to loaded features on this device that are
+ * used by the configuration.
+ *
+ * @config_desc:reference to the descriptor for this configuration
+ * @csdev: parent coresight device for this configuration instance.
+ * @enabled: true if configuration is enabled on this device.
+ * @node: list entry within the coresight device
+ * @nr_feat: Number of features on this device that are used in the
+ * configuration.
+ * @feats_csdev:references to the device features to enable.
+ */
+struct cscfg_config_csdev {
+ const struct cscfg_config_desc *config_desc;
+ struct coresight_device *csdev;
+ bool enabled;
+ struct list_head node;
+ int nr_feat;
+ struct cscfg_feature_csdev *feats_csdev[0];
+};
+
+/**
+ * Coresight device operations.
+ *
+ * Registered coresight devices provide these operations to manage feature
+ * instances compatible with the device hardware and drivers
+ *
+ * @load_feat: Pass a feature descriptor into the device and create the
+ * loaded feature instance (struct cscfg_feature_csdev).
+ */
+struct cscfg_csdev_feat_ops {
+ int (*load_feat)(struct coresight_device *csdev,
+struct cscfg_feature_csdev *feat_csdev);
+};
+
#endif /* _CORESIGHT_CORESIGHT_CONFIG_H */
diff --git a/drivers/hwtracing/coresight/coresight
[PATCH v7 04/10] coresight: etm-perf: update to handle configuration selection
Loaded coresight configurations are registered in the cs_etm\events sub
directory. This extends the etm-perf code to handle these registrations,
and the cs_syscfg driver to perform the registration on load.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../hwtracing/coresight/coresight-config.h| 2 +
.../hwtracing/coresight/coresight-etm-perf.c | 134 ++
.../hwtracing/coresight/coresight-etm-perf.h | 8 ++
.../hwtracing/coresight/coresight-syscfg.c| 11 ++
4 files changed, 127 insertions(+), 28 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
index 5a39cbbc38a4..0667581822c1 100644
--- a/drivers/hwtracing/coresight/coresight-config.h
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -126,6 +126,7 @@ struct cscfg_feature_desc {
* @nr_presets:Number of sets of presets supplied by this
configuration.
* @nr_total_params: Sum of all parameters declared by used features
* @presets: Array of preset values.
+ * @event_ea: Extended attribute for perf event value
*
*/
struct cscfg_config_desc {
@@ -137,6 +138,7 @@ struct cscfg_config_desc {
int nr_presets;
int nr_total_params;
const u64 *presets; /* nr_presets * nr_total_params */
+ struct dev_ext_attribute *event_ea;
};
/**
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 15310c72f89f..26b4bca156aa 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -18,8 +18,10 @@
#include
#include
+#include "coresight-config.h"
#include "coresight-etm-perf.h"
#include "coresight-priv.h"
+#include "coresight-syscfg.h"
static struct pmu etm_pmu;
static bool etm_perf_up;
@@ -57,8 +59,13 @@ PMU_FORMAT_ATTR(contextid1, "config:"
__stringify(ETM_OPT_CTXTID));
PMU_FORMAT_ATTR(contextid2,"config:" __stringify(ETM_OPT_CTXTID2));
PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS));
PMU_FORMAT_ATTR(retstack, "config:" __stringify(ETM_OPT_RETSTK));
+/* preset - if sink ID is used as a configuration selector */
+PMU_FORMAT_ATTR(preset,"config:0-3");
/* Sink ID - same for all ETMs */
PMU_FORMAT_ATTR(sinkid,"config2:0-31");
+/* config ID - set if a system configuration is selected */
+PMU_FORMAT_ATTR(configid, "config2:32-63");
+
/*
* contextid always traces the "PID". The PID is in CONTEXTIDR_EL1
@@ -88,6 +95,8 @@ static struct attribute *etm_config_formats_attr[] = {
&format_attr_timestamp.attr,
&format_attr_retstack.attr,
&format_attr_sinkid.attr,
+ &format_attr_preset.attr,
+ &format_attr_configid.attr,
NULL,
};
@@ -105,9 +114,19 @@ static const struct attribute_group etm_pmu_sinks_group = {
.attrs = etm_config_sinks_attr,
};
+static struct attribute *etm_config_events_attr[] = {
+ NULL,
+};
+
+static const struct attribute_group etm_pmu_events_group = {
+ .name = "events",
+ .attrs = etm_config_events_attr,
+};
+
static const struct attribute_group *etm_pmu_attr_groups[] = {
&etm_pmu_format_group,
&etm_pmu_sinks_group,
+ &etm_pmu_events_group,
NULL,
};
@@ -286,7 +305,7 @@ static void *etm_setup_aux(struct perf_event *event, void
**pages,
INIT_WORK(&event_data->work, free_event_data);
/* First get the selected sink from user space. */
- if (event->attr.config2) {
+ if (event->attr.config2 & GENMASK_ULL(31, 0)) {
id = (u32)event->attr.config2;
sink = user_sink = coresight_get_sink_by_id(id);
}
@@ -658,68 +677,127 @@ static ssize_t etm_perf_sink_name_show(struct device
*dev,
return scnprintf(buf, PAGE_SIZE, "0x%lx\n", (unsigned long)(ea->var));
}
-int etm_perf_add_symlink_sink(struct coresight_device *csdev)
+static struct dev_ext_attribute *
+etm_perf_add_symlink_group(struct device *dev, const char *name, const char
*group_name)
{
- int ret;
+ struct dev_ext_attribute *ea;
unsigned long hash;
- const char *name;
+ int ret;
struct device *pmu_dev = etm_pmu.dev;
- struct device *dev = &csdev->dev;
- struct dev_ext_attribute *ea;
-
- if (csdev->type != CORESIGHT_DEV_TYPE_SINK &&
- csdev->type != CORESIGHT_DEV_TYPE_LINKSINK)
- return -EINVAL;
-
- if (csdev->ea != NULL)
- return -EINVAL;
if (!etm_perf_up)
- return -EPROBE_DEFER;
+ return ERR_PTR(-EPROBE_DEFER);
ea = devm_kzalloc(dev, sizeof
[PATCH v7 03/10] coresight: config: Add configuration and feature generic functions
Adds a set of generic support functions that allow devices to set and save
features values on the device, and enable and disable configurations.
Additional functions for other common operations including feature
reset.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile | 2 +-
.../hwtracing/coresight/coresight-config.c| 275 ++
.../hwtracing/coresight/coresight-config.h| 9 +
.../hwtracing/coresight/coresight-syscfg.c| 3 +-
4 files changed, 287 insertions(+), 2 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-config.c
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index 3d037f17aade..63ecfc3cf66d 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -4,7 +4,7 @@
#
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
- coresight-sysfs.o coresight-syscfg.o
+ coresight-sysfs.o coresight-syscfg.o coresight-config.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-config.c
b/drivers/hwtracing/coresight/coresight-config.c
new file mode 100644
index ..3c501e027bc0
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-config.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2020 Linaro Limited. All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include
+#include "coresight-config.h"
+#include "coresight-priv.h"
+
+/*
+ * This provides a set of generic functions that operate on configurations
+ * and features to manage the handling of parameters, the programming and
+ * saving of registers used by features on devices.
+ */
+
+/*
+ * Write the value held in the register structure into the driver internal
memory
+ * location.
+ */
+static void cscfg_set_reg(struct cscfg_regval_csdev *reg_csdev)
+{
+ u32 *p_val32 = (u32 *)reg_csdev->driver_regval;
+ u32 tmp32 = reg_csdev->reg_desc.val32;
+
+ if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT) {
+ *((u64 *)reg_csdev->driver_regval) = reg_csdev->reg_desc.val64;
+ return;
+ }
+
+ if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_MASK) {
+ tmp32 = *p_val32;
+ tmp32 &= ~reg_csdev->reg_desc.mask32;
+ tmp32 |= reg_csdev->reg_desc.val32 & reg_csdev->reg_desc.mask32;
+ }
+ *p_val32 = tmp32;
+}
+
+/*
+ * Read the driver value into the reg if this is marked as one we want to save.
+ */
+static void cscfg_save_reg(struct cscfg_regval_csdev *reg_csdev)
+{
+ if (!(reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_SAVE))
+ return;
+ if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT)
+ reg_csdev->reg_desc.val64 = *(u64 *)(reg_csdev->driver_regval);
+ else
+ reg_csdev->reg_desc.val32 = *(u32 *)(reg_csdev->driver_regval);
+}
+
+/*
+ * Some register values are set from parameters. Initialise these registers
+ * from the current parameter values.
+ */
+static void cscfg_init_reg_param(struct cscfg_feature_csdev *feat_csdev,
+struct cscfg_regval_desc *reg_desc,
+struct cscfg_regval_csdev *reg_csdev)
+{
+ struct cscfg_parameter_csdev *param_csdev;
+
+ /* for param, load routines have validated the index */
+ param_csdev = &feat_csdev->params_csdev[reg_desc->param_idx];
+ param_csdev->reg_csdev = reg_csdev;
+ param_csdev->val64 = reg_csdev->reg_desc.type &
CS_CFG_REG_TYPE_VAL_64BIT;
+
+ if (param_csdev->val64)
+ reg_csdev->reg_desc.val64 = param_csdev->current_value;
+ else
+ reg_csdev->reg_desc.val32 = (u32)param_csdev->current_value;
+}
+
+/* set values into the driver locations referenced in cscfg_reg_csdev */
+static int cscfg_set_on_enable(struct cscfg_feature_csdev *feat_csdev)
+{
+ int i;
+
+ spin_lock(feat_csdev->drv_spinlock);
+ for (i = 0; i < feat_csdev->nr_regs; i++)
+ cscfg_set_reg(&feat_csdev->regs_csdev[i]);
+ spin_unlock(feat_csdev->drv_spinlock);
+ dev_dbg(&feat_csdev->csdev->dev, "Feature %s: %s",
+ feat_csdev->feat_desc->name, "set on enable");
+ return 0;
+}
+
+/* copy back values from the driver locations referenced in cscfg_reg_csdev */
+static void cscfg_save_on_disable(struct cscfg_feature_csdev *feat_csdev)
+{
+ int i;
+
+ spin_lock(feat_csdev->drv_spinlock);
+ for (i = 0; i < f
[PATCH v7 00/10] CoreSight configuration management; ETM strobing
1) Moved preloaded configurations and features out of individual drivers. 2) Added cs_syscfg driver to manage configurations and features. Individual drivers register with cs_syscfg indicating support for config, and provide matching information that the system uses to load features into the drivers. This allows individual drivers to be updated on an as needed basis - and removes the need to consider devices that cannot benefit from configuration - static replicators, funnels, tpiu. 3) Added perf selection of configuarations. 4) Rebased onto the coresight module loading set. To follow in future revisions / sets:- a) load of additional config and features by loadable module. b) load of additional config and features by configfs c) enhanced resource management for ETMv4 and checking features have sufficient resources to be enabled. d) ECT and CTI support for configuration and features. Mike Leach (10): coresight: syscfg: Initial coresight system configuration coresight: syscfg: Add registration and feature loading for cs devices coresight: config: Add configuration and feature generic functions coresight: etm-perf: update to handle configuration selection coresight: syscfg: Add API to activate and enable configurations coresight: etm-perf: Update to activate selected configuration coresight: etm4x: Add complex configuration handlers to etmv4 coresight: config: Add preloaded configurations coresight: syscfg: Add initial configfs support Documentation: coresight: Add documentation for CoreSight config .../trace/coresight/coresight-config.rst | 244 ++ Documentation/trace/coresight/coresight.rst | 16 + drivers/hwtracing/coresight/Makefile | 7 +- .../hwtracing/coresight/coresight-cfg-afdo.c | 153 .../coresight/coresight-cfg-preload.c | 31 + .../coresight/coresight-cfg-preload.h | 13 + .../hwtracing/coresight/coresight-config.c| 275 ++ .../hwtracing/coresight/coresight-config.h| 253 ++ drivers/hwtracing/coresight/coresight-core.c | 12 +- .../hwtracing/coresight/coresight-etm-perf.c | 150 +++- .../hwtracing/coresight/coresight-etm-perf.h | 12 +- .../hwtracing/coresight/coresight-etm4x-cfg.c | 182 .../hwtracing/coresight/coresight-etm4x-cfg.h | 30 + .../coresight/coresight-etm4x-core.c | 38 +- .../coresight/coresight-etm4x-sysfs.c | 3 + .../coresight/coresight-syscfg-configfs.c | 396 + .../coresight/coresight-syscfg-configfs.h | 45 + .../hwtracing/coresight/coresight-syscfg.c| 804 ++ .../hwtracing/coresight/coresight-syscfg.h| 81 ++ include/linux/coresight.h | 7 + 20 files changed, 2716 insertions(+), 36 deletions(-) create mode 100644 Documentation/trace/coresight/coresight-config.rst create mode 100644 drivers/hwtracing/coresight/coresight-cfg-afdo.c create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.c create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.h create mode 100644 drivers/hwtracing/coresight/coresight-config.c create mode 100644 drivers/hwtracing/coresight/coresight-config.h create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.c create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.h create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.c create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.h -- 2.17.1
[PATCH v7 01/10] coresight: syscfg: Initial coresight system configuration
Creates an system management API to allow complex configurations and
features to be programmed into a CoreSight infrastructure.
A feature is defined as a programming set for a device or class of
devices.
A configuration is a set of features across the system that are enabled
for a trace session.
The API will manage system wide configuration, and allow complex
programmed features to be added to individual device instances, and
provide for system wide configuration selection on trace capture
operations.
This patch creates the initial data object and the initial API for
loading configurations and features.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile | 2 +-
.../hwtracing/coresight/coresight-config.h| 142 +
drivers/hwtracing/coresight/coresight-core.c | 12 +-
.../hwtracing/coresight/coresight-etm-perf.c | 2 +-
.../hwtracing/coresight/coresight-etm-perf.h | 2 +-
.../hwtracing/coresight/coresight-syscfg.c| 199 ++
.../hwtracing/coresight/coresight-syscfg.h| 46
7 files changed, 401 insertions(+), 4 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-config.h
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.c
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index d60816509755..3d037f17aade 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -4,7 +4,7 @@
#
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
- coresight-sysfs.o
+ coresight-sysfs.o coresight-syscfg.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
new file mode 100644
index ..21aa7464dcdc
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 Linaro Limited, All rights reserved.
+ * Author: Mike Leach
+ */
+
+#ifndef _CORESIGHT_CORESIGHT_CONFIG_H
+#define _CORESIGHT_CORESIGHT_CONFIG_H
+
+#include
+#include
+
+/* CoreSight Configuration Management - component and system wide
configuration */
+
+/*
+ * Register type flags for register value descriptor:
+ * describe how the value is interpreted, and handled.
+ */
+#define CS_CFG_REG_TYPE_STD0x80/* reg is standard reg */
+#define CS_CFG_REG_TYPE_RESOURCE 0x40/* reg is a resource */
+#define CS_CFG_REG_TYPE_VAL_PARAM 0x08/* reg value uses param */
+#define CS_CFG_REG_TYPE_VAL_MASK 0x04/* reg value bit masked */
+#define CS_CFG_REG_TYPE_VAL_64BIT 0x02/* reg value 64 bit */
+#define CS_CFG_REG_TYPE_VAL_SAVE 0x01/* reg value save on disable */
+
+/*
+ * flags defining what device class a feature will match to when processing a
+ * system configuration - used by config data and devices.
+ */
+#define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */
+#define CS_CFG_MATCH_CLASS_SRC_ETM40x0002 /* match any ETMv4 device */
+
+/* flags defining device instance matching - used in config match desc data. */
+#define CS_CFG_MATCH_INST_ANY 0x8000 /* any instance of a class */
+
+/*
+ * Limit number of presets in a configuration
+ * This is related to the number of bits (4) we use to select the preset on
+ * the perf command line. Preset 0 is always none selected.
+ * See PMU_FORMAT_ATTR(preset, "config:0-3") in coresight-etm-perf.c
+ */
+#define CS_CFG_CONFIG_PRESET_MAX 15
+
+/**
+ * Parameter descriptor for a device feature.
+ *
+ * @name: Name of parameter.
+ * @value: Initial or default value.
+ */
+struct cscfg_parameter_desc {
+ const char *name;
+ u64 value;
+};
+
+/**
+ * Representation of register value and a descriptor of register usage.
+ *
+ * Used as a descriptor in the feature descriptors.
+ * Used as a value in when in a feature loading into a csdev.
+ *
+ * Supports full 64 bit register value, or 32 bit value with optional mask
+ * value.
+ *
+ * @type: define register usage and interpretation.
+ * @offset:the address offset for register in the hardware device (per
device specification).
+ * @hw_info: optional hardware device type specific information. (ETM / CTI
specific etc)
+ * @val64: 64 bit value.
+ * @val32: 32 bit value.
+ * @mask32:32 bit mask when using 32 bit value to access device register -
if mask type.
+ * @param_idx: parameter index value into parameter array if param type.
+ */
+struct cscfg_regval_desc {
+ struct {
+ u32 type:8;
+ u32 offset:12;
+ u32
Re: [PATCH v6 07/10] coresight: etm4x: Add complex configuration handlers to etmv4
HI Suzuki
OK - realized that this is an aarch32 kernel thing on closer
inspection of the kernel test robot info. Now have a reproducer so
can fix
Thanks
Mike
On Mon, 12 Apr 2021 at 12:29, Mike Leach wrote:
>
> HI Suzuki,
>
> On Mon, 12 Apr 2021 at 11:28, Suzuki K Poulose wrote:
> >
> > On 09/04/2021 11:37, Mike Leach wrote:
> > > Adds in handlers to allow the ETMv4 to use the complex configuration
> > > support. Features and configurations can be loaded and selected in the
> > > device.
> > >
> > > Signed-off-by: Mike Leach
> > > Reviewed-by: Mathieu Poirier
> > > ---
> > > drivers/hwtracing/coresight/Makefile | 3 +-
> > > .../hwtracing/coresight/coresight-etm4x-cfg.c | 182 ++
> > > .../hwtracing/coresight/coresight-etm4x-cfg.h | 15 ++
> > > .../coresight/coresight-etm4x-core.c | 38 +++-
> > > .../coresight/coresight-etm4x-sysfs.c | 3 +
> > > 5 files changed, 238 insertions(+), 3 deletions(-)
> > > create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > > create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h
> > >
> > > diff --git a/drivers/hwtracing/coresight/Makefile
> > > b/drivers/hwtracing/coresight/Makefile
> > > index 63ecfc3cf66d..9420d33b23ac 100644
> > > --- a/drivers/hwtracing/coresight/Makefile
> > > +++ b/drivers/hwtracing/coresight/Makefile
> > > @@ -16,7 +16,8 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) +=
> > > coresight-etm3x.o
> > > coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \
> > >coresight-etm3x-sysfs.o
> > > obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o
> > > -coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o
> > > +coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o \
> > > + coresight-etm4x-cfg.o
> > > obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
> > > obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
> > > obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > > b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > > new file mode 100644
> > > index ..d2ea903231b2
> > > --- /dev/null
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > > @@ -0,0 +1,182 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Copyright(C) 2020 Linaro Limited. All rights reserved.
> > > + * Author: Mike Leach
> > > + */
> > > +
> >
> > > +#include "coresight-etm4x.h"
> > > +#include "coresight-etm4x-cfg.h"
> > > +#include "coresight-priv.h"
> > > +#include "coresight-syscfg.h"
> > > +
> > > +/* defines to associate register IDs with driver data locations */
> > > +#define CHECKREG(cval, elem) \
> > > + { \
> > > + if (offset == cval) { \
> > > + reg_csdev->driver_regval = &drvcfg->elem; \
> > > + err = 0; \
> > > + break; \
> > > + } \
> > > + }
> > > +
> > > +#define CHECKREGIDX(cval, elem, off_idx, mask) \
> > > + { \
> > > + if (mask == cval) { \
> > > + reg_csdev->driver_regval = &drvcfg->elem[off_idx]; \
> > > + err = 0; \
> > > + break; \
> > > + } \
> > > + }
> > > +
> > > +/**
> > > + * etm4_cfg_map_reg_offset - validate and map the register offset into a
> > > + *location in the driver config struct.
> > > + *
> > > + * Limits the number of registers that can be accessed and programmed in
> > > + * features, to those which are used to control the trace capture
> > > parameters.
> > > + *
> > > + * Omits or limits access to those which the driver must use exclusively.
> > > + *
> > > + * Invalid offsets will result in fail code return and feature load
> > > failure.
> > > + *
> > > + * @drvdata: driver data to map into.
> > > + * @reg: register to map.
> > > + * @offset: device offset for the register
> > > + */
> > > +static int etm4_cfg_map_reg_offset(struct e
Re: [PATCH v6 07/10] coresight: etm4x: Add complex configuration handlers to etmv4
HI Suzuki,
On Mon, 12 Apr 2021 at 11:28, Suzuki K Poulose wrote:
>
> On 09/04/2021 11:37, Mike Leach wrote:
> > Adds in handlers to allow the ETMv4 to use the complex configuration
> > support. Features and configurations can be loaded and selected in the
> > device.
> >
> > Signed-off-by: Mike Leach
> > Reviewed-by: Mathieu Poirier
> > ---
> > drivers/hwtracing/coresight/Makefile | 3 +-
> > .../hwtracing/coresight/coresight-etm4x-cfg.c | 182 ++
> > .../hwtracing/coresight/coresight-etm4x-cfg.h | 15 ++
> > .../coresight/coresight-etm4x-core.c | 38 +++-
> > .../coresight/coresight-etm4x-sysfs.c | 3 +
> > 5 files changed, 238 insertions(+), 3 deletions(-)
> > create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h
> >
> > diff --git a/drivers/hwtracing/coresight/Makefile
> > b/drivers/hwtracing/coresight/Makefile
> > index 63ecfc3cf66d..9420d33b23ac 100644
> > --- a/drivers/hwtracing/coresight/Makefile
> > +++ b/drivers/hwtracing/coresight/Makefile
> > @@ -16,7 +16,8 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o
> > coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \
> >coresight-etm3x-sysfs.o
> > obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o
> > -coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o
> > +coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o \
> > + coresight-etm4x-cfg.o
> > obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
> > obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
> > obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > new file mode 100644
> > index ..d2ea903231b2
> > --- /dev/null
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > @@ -0,0 +1,182 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright(C) 2020 Linaro Limited. All rights reserved.
> > + * Author: Mike Leach
> > + */
> > +
>
> > +#include "coresight-etm4x.h"
> > +#include "coresight-etm4x-cfg.h"
> > +#include "coresight-priv.h"
> > +#include "coresight-syscfg.h"
> > +
> > +/* defines to associate register IDs with driver data locations */
> > +#define CHECKREG(cval, elem) \
> > + { \
> > + if (offset == cval) { \
> > + reg_csdev->driver_regval = &drvcfg->elem; \
> > + err = 0; \
> > + break; \
> > + } \
> > + }
> > +
> > +#define CHECKREGIDX(cval, elem, off_idx, mask) \
> > + { \
> > + if (mask == cval) { \
> > + reg_csdev->driver_regval = &drvcfg->elem[off_idx]; \
> > + err = 0; \
> > + break; \
> > + } \
> > + }
> > +
> > +/**
> > + * etm4_cfg_map_reg_offset - validate and map the register offset into a
> > + *location in the driver config struct.
> > + *
> > + * Limits the number of registers that can be accessed and programmed in
> > + * features, to those which are used to control the trace capture
> > parameters.
> > + *
> > + * Omits or limits access to those which the driver must use exclusively.
> > + *
> > + * Invalid offsets will result in fail code return and feature load
> > failure.
> > + *
> > + * @drvdata: driver data to map into.
> > + * @reg: register to map.
> > + * @offset: device offset for the register
> > + */
> > +static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
> > +struct cscfg_regval_csdev *reg_csdev, u32
> > offset)
> > +{
> > + int err = -EINVAL, idx;
> > + struct etmv4_config *drvcfg = &drvdata->config;
> > + u32 off_mask;
> > +
> > + if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) ||
> > + ((offset >= TRCSEQRSTEVR) && (offset <= TRCEXTINSELR)) ||
> > + ((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) {
> > + do {
> > + CHECKREG(TRCEVENTCTL0R, eventctrl0);
> > + CHECKREG(TRCEVE
[PATCH v6 10/10] Documentation: coresight: Add documentation for CoreSight config
Adds documentation for the CoreSight System configuration manager. Cc: Jonathan Corbet Cc: linux-...@vger.kernel.org Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- .../trace/coresight/coresight-config.rst | 244 ++ Documentation/trace/coresight/coresight.rst | 16 ++ 2 files changed, 260 insertions(+) create mode 100644 Documentation/trace/coresight/coresight-config.rst diff --git a/Documentation/trace/coresight/coresight-config.rst b/Documentation/trace/coresight/coresight-config.rst new file mode 100644 index ..a4e3ef295240 --- /dev/null +++ b/Documentation/trace/coresight/coresight-config.rst @@ -0,0 +1,244 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== +CoreSight System Configuration Manager +== + +:Author: Mike Leach +:Date: October 2020 + +Introduction + + +The CoreSight System Configuration manager is an API that allows the +programming of the CoreSight system with pre-defined configurations that +can then be easily enabled from sysfs or perf. + +Many CoreSight components can be programmed in complex ways - especially ETMs. +In addition, components can interact across the CoreSight system, often via +the cross trigger components such as CTI and CTM. These system settings can +be defined and enabled as named configurations. + + +Basic Concepts +== + +This section introduces the basic concepts of a CoreSight system configuration. + + +Features + + +A feature is a named set of programming for a CoreSight device. The programming +is device dependent, and can be defined in terms of absolute register values, +resource usage and parameter values. + +The feature is defined using a descriptor. This descriptor is used to load onto +a matching device, either when the feature is loaded into the system, or when the +CoreSight device is registered with the configuration manager. + +The load process involves interpreting the descriptor into a set of register +accesses in the driver - the resource usage and parameter descriptions +translated into appropriate register accesses. This interpretation makes it easy +and efficient for the feature to be programmed onto the device when required. + +The feature will not be active on the device until the feature is enabled, and +the device itself is enabled. When the device is enabled then enabled features +will be programmed into the device hardware. + +A feature is enabled as part of a configuration being enabled on the system. + + +Parameter Value +~~~ + +A parameter value is a named value that may be set by the user prior to the +feature being enabled that can adjust the behaviour of the operation programmed +by the feature. + +For example, this could be a count value in a programmed operation that repeats +at a given rate. When the feature is enabled then the current value of the +parameter is used in programming the device. + +The feature descriptor defines a default value for a parameter, which is used +if the user does not supply a new value. + +Users can update parameter values using the configfs API for the CoreSight +system - which is described below. + +The current value of the parameter is loaded into the device when the feature +is enabled on that device. + + +Configurations +-- + +A configuration defines a set of features that are to be used in a trace +session where the configuration is selected. For any trace session only one +configuration may be selected. + +The features defined may be on any type of device that is registered +to support system configuration. A configuration may select features to be +enabled on a class of devices - i.e. any ETMv4, or specific devices, e.g. a +specific CTI on the system. + +As with the feature, a descriptor is used to define the configuration. +This will define the features that must be enabled as part of the configuration +as well as any preset values that can be used to override default parameter +values. + + +Preset Values +~ + +Preset values are easily selectable sets of parameter values for the features +that the configuration uses. The number of values in a single preset set, equals +the sum of parameter values in the features used by the configuration. + +e.g. a configuration consists of 3 features, one has 2 parameters, one has +a single parameter, and another has no parameters. A single preset set will +therefore have 3 values. + +Presets are optionally defined by the configuration, up to 15 can be defined. +If no preset is selected, then the parameter values defined in the feature +are used as normal. + + +Operation +~ + +The following steps take place in the operation of a configuration. + +1) In this example, the configuration is 'autofdo', which has an + associated feature 'strobing' that works on ETMv4 CoreSight Devices. + +2) The configuration is enabled. For example &
[PATCH v6 09/10] coresight: syscfg: Add initial configfs support
Adds configfs subsystem and attributes to the configuration manager
to enable the listing of loaded configurations and features.
The default values of feature parameters can be accessed and altered
from these attributes to affect all installed devices using the feature.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../coresight/coresight-syscfg-configfs.c | 396 ++
.../coresight/coresight-syscfg-configfs.h | 45 ++
.../hwtracing/coresight/coresight-syscfg.c| 76
.../hwtracing/coresight/coresight-syscfg.h| 7 +
5 files changed, 526 insertions(+), 1 deletion(-)
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.c
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index ad44f0fe3069..b6c4a48140ec 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -5,7 +5,8 @@
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
coresight-sysfs.o coresight-syscfg.o coresight-config.o \
- coresight-cfg-preload.o coresight-cfg-afdo.o
+ coresight-cfg-preload.o coresight-cfg-afdo.o \
+ coresight-syscfg-configfs.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
new file mode 100644
index ..c547816b9000
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
@@ -0,0 +1,396 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Linaro Limited, All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include
+
+#include "coresight-syscfg-configfs.h"
+
+/* create a default ci_type. */
+static inline struct config_item_type *cscfg_create_ci_type(void)
+{
+ struct config_item_type *ci_type;
+
+ ci_type = devm_kzalloc(cscfg_device(), sizeof(*ci_type), GFP_KERNEL);
+ if (ci_type)
+ ci_type->ct_owner = THIS_MODULE;
+
+ return ci_type;
+}
+
+/* configurations sub-group */
+
+/* attributes for the config view group */
+static ssize_t cscfg_cfg_description_show(struct config_item *item, char *page)
+{
+ struct cscfg_fs_config *fs_config = container_of(to_config_group(item),
+struct
cscfg_fs_config, group);
+
+ return scnprintf(page, PAGE_SIZE, "%s",
fs_config->config_desc->description);
+}
+CONFIGFS_ATTR_RO(cscfg_cfg_, description);
+
+static ssize_t cscfg_cfg_feature_refs_show(struct config_item *item, char
*page)
+{
+ struct cscfg_fs_config *fs_config = container_of(to_config_group(item),
+struct
cscfg_fs_config, group);
+ const struct cscfg_config_desc *config_desc = fs_config->config_desc;
+ ssize_t ch_used = 0;
+ int i;
+
+ for (i = 0; i < config_desc->nr_feat_refs; i++)
+ ch_used += scnprintf(page + ch_used, PAGE_SIZE - ch_used,
+"%s\n", config_desc->feat_ref_names[i]);
+ return ch_used;
+}
+CONFIGFS_ATTR_RO(cscfg_cfg_, feature_refs);
+
+/* list preset values in order of features and params */
+static ssize_t cscfg_cfg_values_show(struct config_item *item, char *page)
+{
+ const struct cscfg_feature_desc *feat_desc;
+ const struct cscfg_config_desc *config_desc;
+ struct cscfg_fs_preset *fs_preset;
+ int i, j, val_idx, preset_idx;
+ ssize_t used = 0;
+
+ fs_preset = container_of(to_config_group(item), struct cscfg_fs_preset,
group);
+ config_desc = fs_preset->config_desc;
+
+ if (!config_desc->nr_presets)
+ return 0;
+
+ preset_idx = fs_preset->preset_num - 1;
+
+ /* start index on the correct array line */
+ val_idx = config_desc->nr_total_params * preset_idx;
+
+ /*
+* A set of presets is the sum of all params in used features,
+* in order of declaration of features and params in the features
+*/
+ for (i = 0; i < config_desc->nr_feat_refs; i++) {
+ feat_desc =
cscfg_get_named_feat_desc(config_desc->feat_ref_names[i]);
+ for (j = 0; j < feat_desc->nr_params; j++) {
+ used += scnprintf(page + used, PAGE_SIZE - used,
+ "%s.%s = 0x%llx ",
+ feat_desc->name,
+ feat_desc->params_desc[j].name,
+ confi
[PATCH v6 08/10] coresight: config: Add preloaded configurations
Preload set of configurations.
This patch creates a small set of preloaded configurations and features
that are available immediately after coresight has been initialised.
The current set provides a strobing feature for ETMv4, that creates a
periodic sampling of trace by switching trace generation on and off
using counters in the ETM.
A configuration called "autofdo" is also provided that uses the 'strobing'
feature and provides a couple of preset values, selectable on the perf
command line.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../hwtracing/coresight/coresight-cfg-afdo.c | 147 ++
.../coresight/coresight-cfg-preload.c | 27
.../coresight/coresight-cfg-preload.h | 11 ++
.../hwtracing/coresight/coresight-etm4x-cfg.h | 15 ++
.../hwtracing/coresight/coresight-syscfg.c| 9 ++
.../hwtracing/coresight/coresight-syscfg.h| 1 +
7 files changed, 212 insertions(+), 1 deletion(-)
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-afdo.c
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.c
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index 9420d33b23ac..ad44f0fe3069 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -4,7 +4,8 @@
#
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
- coresight-sysfs.o coresight-syscfg.o coresight-config.o
+ coresight-sysfs.o coresight-syscfg.o coresight-config.o \
+ coresight-cfg-preload.o coresight-cfg-afdo.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-cfg-afdo.c
b/drivers/hwtracing/coresight/coresight-cfg-afdo.c
new file mode 100644
index ..d6faf27b8326
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-cfg-afdo.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2020 Linaro Limited. All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include "coresight-config.h"
+#include "coresight-etm4x-cfg.h"
+
+/* preload configurations and features */
+
+/* preload in features for ETMv4 */
+
+/* strobe feature */
+static struct cscfg_parameter_desc strobe_params[] = {
+ {
+ .name = "window",
+ .value = 5000,
+ },
+ {
+ .name = "period",
+ .value = 1,
+ },
+};
+
+static struct cscfg_regval_desc strobe_regs[] = {
+ /* resource selectors */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCRSCTLRn(2),
+ .hw_info = ETM4_CFG_RES_SEL,
+ .val32 = 0x20001,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCRSCTLRn(3),
+ .hw_info = ETM4_CFG_RES_SEQ,
+ .val32 = 0x20002,
+ },
+ /* strobe window counter 0 - reload from param 0 */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE,
+ .offset = TRCCNTVRn(0),
+ .hw_info = ETM4_CFG_RES_CTR,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM,
+ .offset = TRCCNTRLDVRn(0),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 0,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCCNTCTLRn(0),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 0x10001,
+ },
+ /* strobe period counter 1 - reload from param 1 */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE,
+ .offset = TRCCNTVRn(1),
+ .hw_info = ETM4_CFG_RES_CTR,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM,
+ .offset = TRCCNTRLDVRn(1),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 1,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCCNTCTLRn(1),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 0x8102,
+ },
+ /* sequencer */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCSEQEVRn(0),
+ .hw_info = ETM4_CFG_RES_SEQ,
+ .val32 = 0x0081,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCSEQEVRn(1),
+ .hw_info = ETM4_CFG_RES_SEQ,
+ .val32 = 0x,
+
[PATCH v6 07/10] coresight: etm4x: Add complex configuration handlers to etmv4
Adds in handlers to allow the ETMv4 to use the complex configuration
support. Features and configurations can be loaded and selected in the
device.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../hwtracing/coresight/coresight-etm4x-cfg.c | 182 ++
.../hwtracing/coresight/coresight-etm4x-cfg.h | 15 ++
.../coresight/coresight-etm4x-core.c | 38 +++-
.../coresight/coresight-etm4x-sysfs.c | 3 +
5 files changed, 238 insertions(+), 3 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c
create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index 63ecfc3cf66d..9420d33b23ac 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -16,7 +16,8 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o
coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \
coresight-etm3x-sysfs.o
obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o
-coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o
+coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o \
+ coresight-etm4x-cfg.o
obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
new file mode 100644
index ..d2ea903231b2
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2020 Linaro Limited. All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include "coresight-etm4x.h"
+#include "coresight-etm4x-cfg.h"
+#include "coresight-priv.h"
+#include "coresight-syscfg.h"
+
+/* defines to associate register IDs with driver data locations */
+#define CHECKREG(cval, elem) \
+ { \
+ if (offset == cval) { \
+ reg_csdev->driver_regval = &drvcfg->elem; \
+ err = 0; \
+ break; \
+ } \
+ }
+
+#define CHECKREGIDX(cval, elem, off_idx, mask) \
+ { \
+ if (mask == cval) { \
+ reg_csdev->driver_regval = &drvcfg->elem[off_idx]; \
+ err = 0; \
+ break; \
+ } \
+ }
+
+/**
+ * etm4_cfg_map_reg_offset - validate and map the register offset into a
+ * location in the driver config struct.
+ *
+ * Limits the number of registers that can be accessed and programmed in
+ * features, to those which are used to control the trace capture parameters.
+ *
+ * Omits or limits access to those which the driver must use exclusively.
+ *
+ * Invalid offsets will result in fail code return and feature load failure.
+ *
+ * @drvdata: driver data to map into.
+ * @reg: register to map.
+ * @offset:device offset for the register
+ */
+static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
+ struct cscfg_regval_csdev *reg_csdev, u32
offset)
+{
+ int err = -EINVAL, idx;
+ struct etmv4_config *drvcfg = &drvdata->config;
+ u32 off_mask;
+
+ if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) ||
+ ((offset >= TRCSEQRSTEVR) && (offset <= TRCEXTINSELR)) ||
+ ((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) {
+ do {
+ CHECKREG(TRCEVENTCTL0R, eventctrl0);
+ CHECKREG(TRCEVENTCTL1R, eventctrl1);
+ CHECKREG(TRCSTALLCTLR, stall_ctrl);
+ CHECKREG(TRCTSCTLR, ts_ctrl);
+ CHECKREG(TRCSYNCPR, syncfreq);
+ CHECKREG(TRTLR, ccctlr);
+ CHECKREG(TRCBBCTLR, bb_ctrl);
+ CHECKREG(TRCVICTLR, vinst_ctrl);
+ CHECKREG(TRCVIIECTLR, viiectlr);
+ CHECKREG(TRCVISSCTLR, vissctlr);
+ CHECKREG(TRCVIPCSSCTLR, vipcssctlr);
+ CHECKREG(TRCSEQRSTEVR, seq_rst);
+ CHECKREG(TRCSEQSTR, seq_state);
+ CHECKREG(TRCEXTINSELR, ext_inp);
+ CHECKREG(TRCCIDCCTLR0, ctxid_mask0);
+ CHECKREG(TRCCIDCCTLR1, ctxid_mask1);
+ CHECKREG(TRCVMIDCCTLR0, vmid_mask0);
+ CHECKREG(TRCVMIDCCTLR1, vmid_mask1);
+ } while (0);
+ } else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) {
+ /*
[PATCH v6 06/10] coresight: etm-perf: Update to activate selected configuration
Add calls to activate the selected configuration as perf starts
and stops the tracing session.
Signed-off-by: Mike Leach
Reviewed-by: Suzuki K Poulose
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 14 +-
drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 26b4bca156aa..560baefdfed8 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -215,6 +215,10 @@ static void free_event_data(struct work_struct *work)
/* Free the sink buffers, if there are any */
free_sink_buffer(event_data);
+ /* clear any configuration we were using */
+ if (event_data->cfg_hash)
+ cscfg_deactivate_config(event_data->cfg_hash);
+
for_each_cpu(cpu, mask) {
struct list_head **ppath;
@@ -292,7 +296,7 @@ static bool sinks_compatible(struct coresight_device *a,
static void *etm_setup_aux(struct perf_event *event, void **pages,
int nr_pages, bool overwrite)
{
- u32 id;
+ u32 id, cfg_hash;
int cpu = event->cpu;
cpumask_t *mask;
struct coresight_device *sink = NULL;
@@ -310,6 +314,14 @@ static void *etm_setup_aux(struct perf_event *event, void
**pages,
sink = user_sink = coresight_get_sink_by_id(id);
}
+ /* check if user wants a coresight configuration selected */
+ cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32);
+ if (cfg_hash) {
+ if (cscfg_activate_config(cfg_hash))
+ goto err;
+ event_data->cfg_hash = cfg_hash;
+ }
+
mask = &event_data->mask;
/*
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h
b/drivers/hwtracing/coresight/coresight-etm-perf.h
index ba617fe2217e..468f7799ab4f 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.h
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.h
@@ -49,12 +49,14 @@ struct etm_filters {
* @work: Handle to free allocated memory outside IRQ context.
* @mask: Hold the CPU(s) this event was set for.
* @snk_config:The sink configuration.
+ * @cfg_hash: The hash id of any coresight config selected.
* @path: An array of path, each slot for one CPU.
*/
struct etm_event_data {
struct work_struct work;
cpumask_t mask;
void *snk_config;
+ u32 cfg_hash;
struct list_head * __percpu *path;
};
--
2.17.1
[PATCH v6 05/10] coresight: syscfg: Add API to activate and enable configurations
Configurations are first activated, then when any coresight device is
enabled, the active configurations are checked and any matching
one is enabled.
This patch provides the activation / enable API.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../hwtracing/coresight/coresight-config.h| 2 +
.../hwtracing/coresight/coresight-syscfg.c| 172 ++
.../hwtracing/coresight/coresight-syscfg.h| 8 +
include/linux/coresight.h | 2 +
4 files changed, 184 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
index 0667581822c1..25eb6c632692 100644
--- a/drivers/hwtracing/coresight/coresight-config.h
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -127,6 +127,7 @@ struct cscfg_feature_desc {
* @nr_total_params: Sum of all parameters declared by used features
* @presets: Array of preset values.
* @event_ea: Extended attribute for perf event value
+ * @active_cnt:ref count for activate on this configuration.
*
*/
struct cscfg_config_desc {
@@ -139,6 +140,7 @@ struct cscfg_config_desc {
int nr_total_params;
const u64 *presets; /* nr_presets * nr_total_params */
struct dev_ext_attribute *event_ea;
+ atomic_t active_cnt;
};
/**
diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c
b/drivers/hwtracing/coresight/coresight-syscfg.c
index e35f8c0ac2f8..b234e45c153f 100644
--- a/drivers/hwtracing/coresight/coresight-syscfg.c
+++ b/drivers/hwtracing/coresight/coresight-syscfg.c
@@ -283,6 +283,7 @@ static int cscfg_load_config(struct cscfg_config_desc
*config_desc)
return err;
list_add(&config_desc->item, &cscfg_mgr->config_desc_list);
+ atomic_set(&config_desc->active_cnt, 0);
return 0;
}
@@ -468,6 +469,176 @@ void cscfg_unregister_csdev(struct coresight_device
*csdev)
}
EXPORT_SYMBOL_GPL(cscfg_unregister_csdev);
+/**
+ * cscfg_csdev_reset_feats - reset features for a CoreSight device.
+ *
+ * Resets all parameters and register values for any features loaded
+ * into @csdev to their default values.
+ *
+ * @csdev: The CoreSight device.
+ */
+void cscfg_csdev_reset_feats(struct coresight_device *csdev)
+{
+ struct cscfg_feature_csdev *feat_csdev;
+
+ mutex_lock(&cscfg_csdev_mutex);
+ if (list_empty(&csdev->feature_csdev_list))
+ goto unlock_exit;
+
+ list_for_each_entry(feat_csdev, &csdev->feature_csdev_list, node)
+ cscfg_reset_feat(feat_csdev);
+
+unlock_exit:
+ mutex_unlock(&cscfg_csdev_mutex);
+}
+EXPORT_SYMBOL_GPL(cscfg_csdev_reset_feats);
+
+/**
+ * cscfg_activate_config - Mark a configuration descriptor as active.
+ *
+ * This will be seen when csdev devices are enabled in the system.
+ * Only activated configurations can be enabled on individual devices.
+ * Activation protects the configuration from alteration or removal while
+ * active.
+ *
+ * Selection by hash value - generated from the configuration name when it
+ * was loaded and added to the cs_etm/configurations file system for selection
+ * by perf.
+ *
+ * Increments the configuration descriptor active count and the global active
+ * count.
+ *
+ * @cfg_hash: Hash value of the selected configuration name.
+ */
+int cscfg_activate_config(unsigned long cfg_hash)
+{
+ struct cscfg_config_desc *config_desc;
+ int err = -EINVAL;
+
+ mutex_lock(&cscfg_mutex);
+
+ list_for_each_entry(config_desc, &cscfg_mgr->config_desc_list, item) {
+ if ((unsigned long)config_desc->event_ea->var == cfg_hash) {
+ /*
+* increment the global active count - control changes
to
+* active configurations
+*/
+ atomic_inc(&cscfg_mgr->sys_active_cnt);
+
+ /*
+* mark the descriptor as active so enable config on a
+* device instance will use it
+*/
+ atomic_inc(&config_desc->active_cnt);
+
+ err = 0;
+ dev_dbg(cscfg_device(), "Activate config %s.\n",
config_desc->name);
+ break;
+ }
+ }
+ mutex_unlock(&cscfg_mutex);
+
+ return err;
+}
+EXPORT_SYMBOL_GPL(cscfg_activate_config);
+
+/**
+ * cscfg_deactivate_config - Mark a config descriptor as inactive.
+ *
+ * Decrement the configuration and global active counts.
+ *
+ * @cfg_hash: Hash value of the selected configuration name.
+ */
+void cscfg_deactivate_config(unsigned long cfg_hash)
+{
+ struct cscfg_config_desc *config_desc;
+
+ mutex_lock(&cscfg_mutex);
+
+ list_for_each_entry(config_desc, &cscfg_mgr-&
[PATCH v6 04/10] coresight: etm-perf: update to handle configuration selection
Loaded coresight configurations are registered in the cs_etm\events sub
directory. This extends the etm-perf code to handle these registrations,
and the cs_syscfg driver to perform the registration on load.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../hwtracing/coresight/coresight-config.h| 2 +
.../hwtracing/coresight/coresight-etm-perf.c | 134 ++
.../hwtracing/coresight/coresight-etm-perf.h | 8 ++
.../hwtracing/coresight/coresight-syscfg.c| 11 ++
4 files changed, 127 insertions(+), 28 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
index 5a39cbbc38a4..0667581822c1 100644
--- a/drivers/hwtracing/coresight/coresight-config.h
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -126,6 +126,7 @@ struct cscfg_feature_desc {
* @nr_presets:Number of sets of presets supplied by this
configuration.
* @nr_total_params: Sum of all parameters declared by used features
* @presets: Array of preset values.
+ * @event_ea: Extended attribute for perf event value
*
*/
struct cscfg_config_desc {
@@ -137,6 +138,7 @@ struct cscfg_config_desc {
int nr_presets;
int nr_total_params;
const u64 *presets; /* nr_presets * nr_total_params */
+ struct dev_ext_attribute *event_ea;
};
/**
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 15310c72f89f..26b4bca156aa 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -18,8 +18,10 @@
#include
#include
+#include "coresight-config.h"
#include "coresight-etm-perf.h"
#include "coresight-priv.h"
+#include "coresight-syscfg.h"
static struct pmu etm_pmu;
static bool etm_perf_up;
@@ -57,8 +59,13 @@ PMU_FORMAT_ATTR(contextid1, "config:"
__stringify(ETM_OPT_CTXTID));
PMU_FORMAT_ATTR(contextid2,"config:" __stringify(ETM_OPT_CTXTID2));
PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS));
PMU_FORMAT_ATTR(retstack, "config:" __stringify(ETM_OPT_RETSTK));
+/* preset - if sink ID is used as a configuration selector */
+PMU_FORMAT_ATTR(preset,"config:0-3");
/* Sink ID - same for all ETMs */
PMU_FORMAT_ATTR(sinkid,"config2:0-31");
+/* config ID - set if a system configuration is selected */
+PMU_FORMAT_ATTR(configid, "config2:32-63");
+
/*
* contextid always traces the "PID". The PID is in CONTEXTIDR_EL1
@@ -88,6 +95,8 @@ static struct attribute *etm_config_formats_attr[] = {
&format_attr_timestamp.attr,
&format_attr_retstack.attr,
&format_attr_sinkid.attr,
+ &format_attr_preset.attr,
+ &format_attr_configid.attr,
NULL,
};
@@ -105,9 +114,19 @@ static const struct attribute_group etm_pmu_sinks_group = {
.attrs = etm_config_sinks_attr,
};
+static struct attribute *etm_config_events_attr[] = {
+ NULL,
+};
+
+static const struct attribute_group etm_pmu_events_group = {
+ .name = "events",
+ .attrs = etm_config_events_attr,
+};
+
static const struct attribute_group *etm_pmu_attr_groups[] = {
&etm_pmu_format_group,
&etm_pmu_sinks_group,
+ &etm_pmu_events_group,
NULL,
};
@@ -286,7 +305,7 @@ static void *etm_setup_aux(struct perf_event *event, void
**pages,
INIT_WORK(&event_data->work, free_event_data);
/* First get the selected sink from user space. */
- if (event->attr.config2) {
+ if (event->attr.config2 & GENMASK_ULL(31, 0)) {
id = (u32)event->attr.config2;
sink = user_sink = coresight_get_sink_by_id(id);
}
@@ -658,68 +677,127 @@ static ssize_t etm_perf_sink_name_show(struct device
*dev,
return scnprintf(buf, PAGE_SIZE, "0x%lx\n", (unsigned long)(ea->var));
}
-int etm_perf_add_symlink_sink(struct coresight_device *csdev)
+static struct dev_ext_attribute *
+etm_perf_add_symlink_group(struct device *dev, const char *name, const char
*group_name)
{
- int ret;
+ struct dev_ext_attribute *ea;
unsigned long hash;
- const char *name;
+ int ret;
struct device *pmu_dev = etm_pmu.dev;
- struct device *dev = &csdev->dev;
- struct dev_ext_attribute *ea;
-
- if (csdev->type != CORESIGHT_DEV_TYPE_SINK &&
- csdev->type != CORESIGHT_DEV_TYPE_LINKSINK)
- return -EINVAL;
-
- if (csdev->ea != NULL)
- return -EINVAL;
if (!etm_perf_up)
- return -EPROBE_DEFER;
+ return ERR_PTR(-EPROBE_DEFER);
ea = devm_kzalloc(dev, sizeof
[PATCH v6 03/10] coresight: config: Add configuration and feature generic functions
Adds a set of generic support functions that allow devices to set and save
features values on the device, and enable and disable configurations.
Additional functions for other common operations including feature
reset.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile | 2 +-
.../hwtracing/coresight/coresight-config.c| 275 ++
.../hwtracing/coresight/coresight-config.h| 9 +
.../hwtracing/coresight/coresight-syscfg.c| 3 +-
4 files changed, 287 insertions(+), 2 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-config.c
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index 3d037f17aade..63ecfc3cf66d 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -4,7 +4,7 @@
#
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
- coresight-sysfs.o coresight-syscfg.o
+ coresight-sysfs.o coresight-syscfg.o coresight-config.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-config.c
b/drivers/hwtracing/coresight/coresight-config.c
new file mode 100644
index ..3c501e027bc0
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-config.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2020 Linaro Limited. All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include
+#include "coresight-config.h"
+#include "coresight-priv.h"
+
+/*
+ * This provides a set of generic functions that operate on configurations
+ * and features to manage the handling of parameters, the programming and
+ * saving of registers used by features on devices.
+ */
+
+/*
+ * Write the value held in the register structure into the driver internal
memory
+ * location.
+ */
+static void cscfg_set_reg(struct cscfg_regval_csdev *reg_csdev)
+{
+ u32 *p_val32 = (u32 *)reg_csdev->driver_regval;
+ u32 tmp32 = reg_csdev->reg_desc.val32;
+
+ if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT) {
+ *((u64 *)reg_csdev->driver_regval) = reg_csdev->reg_desc.val64;
+ return;
+ }
+
+ if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_MASK) {
+ tmp32 = *p_val32;
+ tmp32 &= ~reg_csdev->reg_desc.mask32;
+ tmp32 |= reg_csdev->reg_desc.val32 & reg_csdev->reg_desc.mask32;
+ }
+ *p_val32 = tmp32;
+}
+
+/*
+ * Read the driver value into the reg if this is marked as one we want to save.
+ */
+static void cscfg_save_reg(struct cscfg_regval_csdev *reg_csdev)
+{
+ if (!(reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_SAVE))
+ return;
+ if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT)
+ reg_csdev->reg_desc.val64 = *(u64 *)(reg_csdev->driver_regval);
+ else
+ reg_csdev->reg_desc.val32 = *(u32 *)(reg_csdev->driver_regval);
+}
+
+/*
+ * Some register values are set from parameters. Initialise these registers
+ * from the current parameter values.
+ */
+static void cscfg_init_reg_param(struct cscfg_feature_csdev *feat_csdev,
+struct cscfg_regval_desc *reg_desc,
+struct cscfg_regval_csdev *reg_csdev)
+{
+ struct cscfg_parameter_csdev *param_csdev;
+
+ /* for param, load routines have validated the index */
+ param_csdev = &feat_csdev->params_csdev[reg_desc->param_idx];
+ param_csdev->reg_csdev = reg_csdev;
+ param_csdev->val64 = reg_csdev->reg_desc.type &
CS_CFG_REG_TYPE_VAL_64BIT;
+
+ if (param_csdev->val64)
+ reg_csdev->reg_desc.val64 = param_csdev->current_value;
+ else
+ reg_csdev->reg_desc.val32 = (u32)param_csdev->current_value;
+}
+
+/* set values into the driver locations referenced in cscfg_reg_csdev */
+static int cscfg_set_on_enable(struct cscfg_feature_csdev *feat_csdev)
+{
+ int i;
+
+ spin_lock(feat_csdev->drv_spinlock);
+ for (i = 0; i < feat_csdev->nr_regs; i++)
+ cscfg_set_reg(&feat_csdev->regs_csdev[i]);
+ spin_unlock(feat_csdev->drv_spinlock);
+ dev_dbg(&feat_csdev->csdev->dev, "Feature %s: %s",
+ feat_csdev->feat_desc->name, "set on enable");
+ return 0;
+}
+
+/* copy back values from the driver locations referenced in cscfg_reg_csdev */
+static void cscfg_save_on_disable(struct cscfg_feature_csdev *feat_csdev)
+{
+ int i;
+
+ spin_lock(feat_csdev->drv_spinlock);
+ for (i = 0; i < f
[PATCH v6 02/10] coresight: syscfg: Add registration and feature loading for cs devices
API for individual devices to register with the syscfg management
system is added.
Devices register with matching information, and any features or
configurations that match will be loaded into the device.
The feature and configuration loading is extended so that on load these
are loaded into any currently registered devices. This allows
configuration loading after devices have been registered.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
.../hwtracing/coresight/coresight-config.h| 98 +
.../hwtracing/coresight/coresight-syscfg.c| 338 +-
.../hwtracing/coresight/coresight-syscfg.h| 19 +
include/linux/coresight.h | 5 +
4 files changed, 459 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
index 21aa7464dcdc..685fb46ce893 100644
--- a/drivers/hwtracing/coresight/coresight-config.h
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -139,4 +139,102 @@ struct cscfg_config_desc {
const u64 *presets; /* nr_presets * nr_total_params */
};
+/**
+ * config register instance - part of a loaded feature.
+ *maps register values to csdev driver structures
+ *
+ * @reg_desc: value to use when setting feature on device / store for
+ * readback of volatile values.
+ * @driver_regval: pointer to internal driver element used to set the value
+ * in hardware.
+ */
+struct cscfg_regval_csdev {
+ struct cscfg_regval_desc reg_desc;
+ void *driver_regval;
+};
+
+/**
+ * config parameter instance - part of a loaded feature.
+ *
+ * @feat_csdev:parent feature
+ * @reg_csdev: register value updated by this parameter.
+ * @current_value: current value of parameter - may be set by user via
+ * sysfs, or modified during device operation.
+ * @val64: true if 64 bit value
+ */
+struct cscfg_parameter_csdev {
+ struct cscfg_feature_csdev *feat_csdev;
+ struct cscfg_regval_csdev *reg_csdev;
+ u64 current_value;
+ bool val64;
+};
+
+/**
+ * Feature instance loaded into a CoreSight device.
+ *
+ * When a feature is loaded into a specific device, then this structure holds
+ * the connections between the register / parameter values used and the
+ * internal data structures that are written when the feature is enabled.
+ *
+ * Since applying a feature modifies internal data structures in the device,
+ * then we have a reference to the device spinlock to protect access to these
+ * structures (@drv_spinlock).
+ *
+ * @feat_desc: pointer to the static descriptor for this feature.
+ * @csdev: parent CoreSight device instance.
+ * @node: list entry into feature list for this device.
+ * @drv_spinlock: device spinlock for access to driver register data.
+ * @nr_params: number of parameters.
+ * @params_csdev: current parameter values on this device
+ * @nr_regs: number of registers to be programmed.
+ * @regs_csdev:Programming details for the registers
+ */
+struct cscfg_feature_csdev {
+ const struct cscfg_feature_desc *feat_desc;
+ struct coresight_device *csdev;
+ struct list_head node;
+ spinlock_t *drv_spinlock;
+ int nr_params;
+ struct cscfg_parameter_csdev *params_csdev;
+ int nr_regs;
+ struct cscfg_regval_csdev *regs_csdev;
+};
+
+/**
+ * Configuration instance when loaded into a CoreSight device.
+ *
+ * The instance contains references to loaded features on this device that are
+ * used by the configuration.
+ *
+ * @config_desc:reference to the descriptor for this configuration
+ * @csdev: parent coresight device for this configuration instance.
+ * @enabled: true if configuration is enabled on this device.
+ * @node: list entry within the coresight device
+ * @nr_feat: Number of features on this device that are used in the
+ * configuration.
+ * @feats_csdev:references to the device features to enable.
+ */
+struct cscfg_config_csdev {
+ const struct cscfg_config_desc *config_desc;
+ struct coresight_device *csdev;
+ bool enabled;
+ struct list_head node;
+ int nr_feat;
+ struct cscfg_feature_csdev *feats_csdev[0];
+};
+
+/**
+ * Coresight device operations.
+ *
+ * Registered coresight devices provide these operations to manage feature
+ * instances compatible with the device hardware and drivers
+ *
+ * @load_feat: Pass a feature descriptor into the device and create the
+ * loaded feature instance (struct cscfg_feature_csdev).
+ */
+struct cscfg_csdev_feat_ops {
+ int (*load_feat)(struct coresight_device *csdev,
+struct cscfg_feature_csdev *feat_csdev);
+};
+
#endif /* _CORESIGHT_CORESIGHT_CONFIG_H */
diff --git a/drivers/hwtracing/coresight/coresight
[PATCH v6 01/10] coresight: syscfg: Initial coresight system configuration
Creates an system management API to allow complex configurations and
features to be programmed into a CoreSight infrastructure.
A feature is defined as a programming set for a device or class of
devices.
A configuration is a set of features across the system that are enabled
for a trace session.
The API will manage system wide configuration, and allow complex
programmed features to be added to individual device instances, and
provide for system wide configuration selection on trace capture
operations.
This patch creates the initial data object and the initial API for
loading configurations and features.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile | 2 +-
.../hwtracing/coresight/coresight-config.h| 142 +
drivers/hwtracing/coresight/coresight-core.c | 12 +-
.../hwtracing/coresight/coresight-etm-perf.c | 2 +-
.../hwtracing/coresight/coresight-etm-perf.h | 2 +-
.../hwtracing/coresight/coresight-syscfg.c| 199 ++
.../hwtracing/coresight/coresight-syscfg.h| 46
7 files changed, 401 insertions(+), 4 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-config.h
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.c
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index d60816509755..3d037f17aade 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -4,7 +4,7 @@
#
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
- coresight-sysfs.o
+ coresight-sysfs.o coresight-syscfg.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
new file mode 100644
index ..21aa7464dcdc
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 Linaro Limited, All rights reserved.
+ * Author: Mike Leach
+ */
+
+#ifndef _CORESIGHT_CORESIGHT_CONFIG_H
+#define _CORESIGHT_CORESIGHT_CONFIG_H
+
+#include
+#include
+
+/* CoreSight Configuration Management - component and system wide
configuration */
+
+/*
+ * Register type flags for register value descriptor:
+ * describe how the value is interpreted, and handled.
+ */
+#define CS_CFG_REG_TYPE_STD0x80/* reg is standard reg */
+#define CS_CFG_REG_TYPE_RESOURCE 0x40/* reg is a resource */
+#define CS_CFG_REG_TYPE_VAL_PARAM 0x08/* reg value uses param */
+#define CS_CFG_REG_TYPE_VAL_MASK 0x04/* reg value bit masked */
+#define CS_CFG_REG_TYPE_VAL_64BIT 0x02/* reg value 64 bit */
+#define CS_CFG_REG_TYPE_VAL_SAVE 0x01/* reg value save on disable */
+
+/*
+ * flags defining what device class a feature will match to when processing a
+ * system configuration - used by config data and devices.
+ */
+#define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */
+#define CS_CFG_MATCH_CLASS_SRC_ETM40x0002 /* match any ETMv4 device */
+
+/* flags defining device instance matching - used in config match desc data. */
+#define CS_CFG_MATCH_INST_ANY 0x8000 /* any instance of a class */
+
+/*
+ * Limit number of presets in a configuration
+ * This is related to the number of bits (4) we use to select the preset on
+ * the perf command line. Preset 0 is always none selected.
+ * See PMU_FORMAT_ATTR(preset, "config:0-3") in coresight-etm-perf.c
+ */
+#define CS_CFG_CONFIG_PRESET_MAX 15
+
+/**
+ * Parameter descriptor for a device feature.
+ *
+ * @name: Name of parameter.
+ * @value: Initial or default value.
+ */
+struct cscfg_parameter_desc {
+ const char *name;
+ u64 value;
+};
+
+/**
+ * Representation of register value and a descriptor of register usage.
+ *
+ * Used as a descriptor in the feature descriptors.
+ * Used as a value in when in a feature loading into a csdev.
+ *
+ * Supports full 64 bit register value, or 32 bit value with optional mask
+ * value.
+ *
+ * @type: define register usage and interpretation.
+ * @offset:the address offset for register in the hardware device (per
device specification).
+ * @hw_info: optional hardware device type specific information. (ETM / CTI
specific etc)
+ * @val64: 64 bit value.
+ * @val32: 32 bit value.
+ * @mask32:32 bit mask when using 32 bit value to access device register -
if mask type.
+ * @param_idx: parameter index value into parameter array if param type.
+ */
+struct cscfg_regval_desc {
+ struct {
+ u32 type:8;
+ u32 offset:12;
+ u32
[PATCH v6 00/10] CoreSight configuration management; ETM strobing
Added cs_syscfg driver to manage configurations and features. Individual drivers register with cs_syscfg indicating support for config, and provide matching information that the system uses to load features into the drivers. This allows individual drivers to be updated on an as needed basis - and removes the need to consider devices that cannot benefit from configuration - static replicators, funnels, tpiu. 3) Added perf selection of configuarations. 4) Rebased onto the coresight module loading set. To follow in future revisions / sets:- a) load of additional config and features by loadable module. b) load of additional config and features by configfs c) enhanced resource management for ETMv4 and checking features have sufficient resources to be enabled. d) ECT and CTI support for configuration and features. Mike Leach (10): coresight: syscfg: Initial coresight system configuration coresight: syscfg: Add registration and feature loading for cs devices coresight: config: Add configuration and feature generic functions coresight: etm-perf: update to handle configuration selection coresight: syscfg: Add API to activate and enable configurations coresight: etm-perf: Update to activate selected configuration coresight: etm4x: Add complex configuration handlers to etmv4 coresight: config: Add preloaded configurations coresight: syscfg: Add initial configfs support Documentation: coresight: Add documentation for CoreSight config .../trace/coresight/coresight-config.rst | 244 ++ Documentation/trace/coresight/coresight.rst | 16 + drivers/hwtracing/coresight/Makefile | 7 +- .../hwtracing/coresight/coresight-cfg-afdo.c | 147 .../coresight/coresight-cfg-preload.c | 27 + .../coresight/coresight-cfg-preload.h | 11 + .../hwtracing/coresight/coresight-config.c| 275 ++ .../hwtracing/coresight/coresight-config.h| 253 ++ drivers/hwtracing/coresight/coresight-core.c | 12 +- .../hwtracing/coresight/coresight-etm-perf.c | 150 +++- .../hwtracing/coresight/coresight-etm-perf.h | 12 +- .../hwtracing/coresight/coresight-etm4x-cfg.c | 182 .../hwtracing/coresight/coresight-etm4x-cfg.h | 30 + .../coresight/coresight-etm4x-core.c | 38 +- .../coresight/coresight-etm4x-sysfs.c | 3 + .../coresight/coresight-syscfg-configfs.c | 396 + .../coresight/coresight-syscfg-configfs.h | 45 + .../hwtracing/coresight/coresight-syscfg.c| 804 ++ .../hwtracing/coresight/coresight-syscfg.h| 81 ++ include/linux/coresight.h | 7 + 20 files changed, 2704 insertions(+), 36 deletions(-) create mode 100644 Documentation/trace/coresight/coresight-config.rst create mode 100644 drivers/hwtracing/coresight/coresight-cfg-afdo.c create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.c create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.h create mode 100644 drivers/hwtracing/coresight/coresight-config.c create mode 100644 drivers/hwtracing/coresight/coresight-config.h create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.c create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.h create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.c create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.h -- 2.17.1
Re: [PATCH v5 09/10] coresight: syscfg: Add initial configfs support
Hi Mathieu,
On Mon, 5 Apr 2021 at 21:56, Mathieu Poirier wrote:
>
> On Tue, Mar 16, 2021 at 06:03:59PM +, Mike Leach wrote:
> > Adds configfs subsystem and attributes to the configuration manager
> > to enable the listing of loaded configurations and features.
> >
> > The default values of feature parameters can be accessed and altered
> > from these attributes to affect all installed devices using the feature.
> >
> > Signed-off-by: Mike Leach
> > ---
> > drivers/hwtracing/coresight/Makefile | 3 +-
> > .../coresight/coresight-syscfg-configfs.c | 399 ++
> > .../coresight/coresight-syscfg-configfs.h | 45 ++
> > .../hwtracing/coresight/coresight-syscfg.c| 77
> > .../hwtracing/coresight/coresight-syscfg.h| 7 +
> > 5 files changed, 530 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.c
> > create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.h
> >
> > diff --git a/drivers/hwtracing/coresight/Makefile
> > b/drivers/hwtracing/coresight/Makefile
> > index 2707bfef1b76..391c93a08902 100644
> > --- a/drivers/hwtracing/coresight/Makefile
> > +++ b/drivers/hwtracing/coresight/Makefile
> > @@ -5,7 +5,8 @@
> > obj-$(CONFIG_CORESIGHT) += coresight.o
> > coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o
> > \
> > coresight-sysfs.o coresight-syscfg.o coresight-config.o \
> > - coresight-cfg-preload.o coresight-cfg-afdo.o
> > + coresight-cfg-preload.o coresight-cfg-afdo.o \
> > + coresight-syscfg-configfs.o
> > obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
> > coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
> > coresight-tmc-etr.o
> > diff --git a/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
> > b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
> > new file mode 100644
> > index ..7cefad81d1f6
> > --- /dev/null
> > +++ b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
> > @@ -0,0 +1,399 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2020 Linaro Limited, All rights reserved.
> > + * Author: Mike Leach
> > + */
> > +
> > +#include
> > +
> > +#include "coresight-syscfg-configfs.h"
> > +
> > +/* create a default ci_type. */
> > +static inline struct config_item_type *cscfg_create_ci_type(void)
> > +{
> > + struct config_item_type *ci_type;
> > +
> > + ci_type = devm_kzalloc(cscfg_device(), sizeof(*ci_type), GFP_KERNEL);
> > + if (ci_type)
> > + ci_type->ct_owner = THIS_MODULE;
> > +
> > + return ci_type;
> > +}
> > +
> > +/* configurations sub-group */
> > +
> > +/* attributes for the config view group */
> > +static ssize_t cscfg_cfg_description_show(struct config_item *item, char
> > *page)
> > +{
> > + struct cscfg_fs_config *fs_config =
> > container_of(to_config_group(item),
> > + struct
> > cscfg_fs_config, group);
> > +
> > + return scnprintf(page, PAGE_SIZE, "%s\n",
> > fs_config->config_desc->description);
> > +}
> > +CONFIGFS_ATTR_RO(cscfg_cfg_, description);
> > +
> > +static ssize_t cscfg_cfg_feature_refs_show(struct config_item *item, char
> > *page)
> > +{
> > + struct cscfg_fs_config *fs_config =
> > container_of(to_config_group(item),
> > + struct
> > cscfg_fs_config, group);
> > + const struct cscfg_config_desc *config_desc = fs_config->config_desc;
> > + ssize_t ch_used = 0;
> > + int i;
> > +
> > + if (config_desc->nr_feat_refs) {
>
> This check isn't needed.
>
Agreed.
> > + for (i = 0; i < config_desc->nr_feat_refs; i++) {
> > + ch_used += scnprintf(page + ch_used, PAGE_SIZE -
> > ch_used,
> > + "%s\n",
> > config_desc->feat_ref_names[i]);
> > + }
> > + }
> > + return ch_used;
> > +}
> > +CONFIGFS_ATTR_RO(cscfg_cfg_, feature_refs);
> > +
> > +/* list preset values in order of features and params */
> > +static ssize_t cscfg_cfg_values_show(struct config_item *item, char *page)
> > +{
> > + const struct cscfg_featu
Re: [PATCH v5 04/10] coresight: etm-perf: update to handle configuration selection
Hi Mathieu,
On Wed, 31 Mar 2021 at 21:49, Mathieu Poirier
wrote:
>
> On Tue, Mar 16, 2021 at 06:03:54PM +, Mike Leach wrote:
> > Loaded coresight configurations are registered in the cs_etm\cs_config sub
>
> This changelog is obsolete - cs_config is no longer under cs_etm.
>
Agreed.
> > directory. This extends the etm-perf code to handle these registrations,
> > and the cs_syscfg driver to perform the registration on load.
> >
> > Signed-off-by: Mike Leach
> > ---
> > .../hwtracing/coresight/coresight-config.h| 2 +
> > .../hwtracing/coresight/coresight-etm-perf.c | 139 ++
> > .../hwtracing/coresight/coresight-etm-perf.h | 8 +
> > .../hwtracing/coresight/coresight-syscfg.c| 12 ++
> > 4 files changed, 130 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-config.h
> > b/drivers/hwtracing/coresight/coresight-config.h
> > index f70561c1504b..38fd1c71eb05 100644
> > --- a/drivers/hwtracing/coresight/coresight-config.h
> > +++ b/drivers/hwtracing/coresight/coresight-config.h
> > @@ -126,6 +126,7 @@ struct cscfg_feature_desc {
> > * @nr_presets: Number of sets of presets supplied by this
> > configuration.
> > * @nr_total_params: Sum of all parameters declared by used features
> > * @presets: Array of preset values.
> > + * @event_ea:Extended attribute for perf event value
> > *
> > */
> > struct cscfg_config_desc {
> > @@ -137,6 +138,7 @@ struct cscfg_config_desc {
> > int nr_presets;
> > int nr_total_params;
> > const u64 *presets; /* nr_presets * nr_total_params */
> > + struct dev_ext_attribute *event_ea;
> > };
> >
> > /**
> > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
> > b/drivers/hwtracing/coresight/coresight-etm-perf.c
> > index 0e392513b2d6..66bda452a2f4 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> > @@ -18,8 +18,10 @@
> > #include
> > #include
> >
> > +#include "coresight-config.h"
> > #include "coresight-etm-perf.h"
> > #include "coresight-priv.h"
> > +#include "coresight-syscfg.h"
> >
> > static struct pmu etm_pmu;
> > static bool etm_perf_up;
> > @@ -38,8 +40,13 @@ PMU_FORMAT_ATTR(contextid1,"config:"
> > __stringify(ETM_OPT_CTXTID));
> > PMU_FORMAT_ATTR(contextid2, "config:" __stringify(ETM_OPT_CTXTID2));
> > PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS));
> > PMU_FORMAT_ATTR(retstack,"config:" __stringify(ETM_OPT_RETSTK));
> > +/* preset - if sink ID is used as a configuration selector */
> > +PMU_FORMAT_ATTR(preset, "config:0-3");
> > /* Sink ID - same for all ETMs */
> > PMU_FORMAT_ATTR(sinkid, "config2:0-31");
> > +/* config ID - set if a system configuration is selected */
> > +PMU_FORMAT_ATTR(configid,"config2:32-63");
> > +
> >
> > /*
> > * contextid always traces the "PID". The PID is in CONTEXTIDR_EL1
> > @@ -69,6 +76,8 @@ static struct attribute *etm_config_formats_attr[] = {
> > &format_attr_timestamp.attr,
> > &format_attr_retstack.attr,
> > &format_attr_sinkid.attr,
> > + &format_attr_preset.attr,
> > + &format_attr_configid.attr,
> > NULL,
> > };
> >
> > @@ -86,9 +95,19 @@ static const struct attribute_group etm_pmu_sinks_group
> > = {
> > .attrs = etm_config_sinks_attr,
> > };
> >
> > +static struct attribute *etm_config_events_attr[] = {
> > + NULL,
> > +};
> > +
> > +static const struct attribute_group etm_pmu_events_group = {
> > + .name = "events",
> > + .attrs = etm_config_events_attr,
> > +};
> > +
> > static const struct attribute_group *etm_pmu_attr_groups[] = {
> > &etm_pmu_format_group,
> > &etm_pmu_sinks_group,
> > + &etm_pmu_events_group,
> > NULL,
> > };
> >
> > @@ -247,7 +266,7 @@ static void *etm_setup_aux(struct perf_event *event,
> > void **pages,
> > INIT_WORK(&event_data->work, free_event_data);
> >
> > /* First get the selected sink from user space. */
> > - if (event->attr.config2) {
> > + if (event->attr.config2 & GENMASK_ULL(31, 0)) {
>
Re: [PATCH v4 18/19] coresight: sink: Add TRBE driver
HI Suzuki,
On Fri, 19 Mar 2021 at 10:30, Suzuki K Poulose wrote:
>
> Hi Mike
>
> > On 8 Mar 2021, at 17:26, Mike Leach wrote:
> >
> > Hi Suzuki,
> >
> > On Thu, 25 Feb 2021 at 19:36, Suzuki K Poulose
> > wrote:
> >>
> >> From: Anshuman Khandual
> >>
> >> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
> >> accessible via the system registers. The TRBE supports different addressing
> >> modes including CPU virtual address and buffer modes including the circular
> >> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
> >> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
> >> access to the trace buffer could be prohibited by a higher exception level
> >> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
> >> private interrupt (PPI) on address translation errors and when the buffer
> >> is full. Overall implementation here is inspired from the Arm SPE driver.
> >>
> >> Cc: Mathieu Poirier
> >> Cc: Mike Leach
> >> Cc: Suzuki K Poulose
> >> Signed-off-by: Anshuman Khandual
> >> Signed-off-by: Suzuki K Poulose
> >>
> >> +
> >> +static unsigned long arm_trbe_update_buffer(struct coresight_device
> >> *csdev,
> >> + struct perf_output_handle
> >> *handle,
> >> + void *config)
> >> +{
> >> + struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> >> + struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
> >> + struct trbe_buf *buf = config;
> >> + enum trbe_fault_action act;
> >> + unsigned long size, offset;
> >> + unsigned long write, base, status;
> >> + unsigned long flags;
> >> +
> >> + WARN_ON(buf->cpudata != cpudata);
> >> + WARN_ON(cpudata->cpu != smp_processor_id());
> >> + WARN_ON(cpudata->drvdata != drvdata);
> >> + if (cpudata->mode != CS_MODE_PERF)
> >> + return 0;
> >> +
> >> + perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW);
> >> +
> >> + /*
> >> +* We are about to disable the TRBE. And this could in turn
> >> +* fill up the buffer triggering, an IRQ. This could be consumed
> >> +* by the PE asynchronously, causing a race here against
> >> +* the IRQ handler in closing out the handle. So, let us
> >> +* make sure the IRQ can't trigger while we are collecting
> >> +* the buffer. We also make sure that a WRAP event is handled
> >> +* accordingly.
> >> +*/
> >> + local_irq_save(flags);
> >> +
> >> + /*
> >> +* If the TRBE was disabled due to lack of space in the AUX buffer
> >> or a
> >> +* spurious fault, the driver leaves it disabled, truncating the
> >> buffer.
> >> +* Since the etm_perf driver expects to close out the AUX buffer,
> >> the
> >> +* driver skips it. Thus, just pass in 0 size here to indicate
> >> that the
> >> +* buffer was truncated.
> >> +*/
> >> + if (!is_trbe_enabled()) {
> >> + size = 0;
> >> + goto done;
> >> + }
> >> + /*
> >> +* perf handle structure needs to be shared with the TRBE IRQ
> >> handler for
> >> +* capturing trace data and restarting the handle. There is a
> >> probability
> >> +* of an undefined reference based crash when etm event is being
> >> stopped
> >> +* while a TRBE IRQ also getting processed. This happens due the
> >> release
> >> +* of perf handle via perf_aux_output_end() in etm_event_stop().
> >> Stopping
> >> +* the TRBE here will ensure that no IRQ could be generated when
> >> the perf
> >> +* handle gets freed in etm_event_stop().
> >> +*/
> >> + trbe_drain_and_disable_local();
> >> + write = get_trbe_write_pointer();
> >> + base = get_trbe_base_pointer();
> >> +
> >> + /* Check if there is a pending interrupt and handle it here */
> >> + status = read_sysreg_s(SYS_TRBSR_EL1);
> >> +
Re: [PATCH v4 07/10] coresight: etm4x: Add complex configuration handlers to etmv4
Hi Suzuki,
Realised I hadn't answered the question below...
On Fri, 5 Mar 2021 at 10:18, Suzuki K Poulose wrote:
>
> On 1/28/21 5:09 PM, Mike Leach wrote:
> > Adds in handlers to allow the ETMv4 to use the complex configuration
> > support. Features and configurations can be loaded and selected in the
> > device.
> >
> > Signed-off-by: Mike Leach
> > ---
> > drivers/hwtracing/coresight/Makefile | 3 +-
> > .../hwtracing/coresight/coresight-etm4x-cfg.c | 184 ++
> > .../hwtracing/coresight/coresight-etm4x-cfg.h | 29 +++
> > .../coresight/coresight-etm4x-core.c | 38 +++-
> > .../coresight/coresight-etm4x-sysfs.c | 3 +
> > 5 files changed, 254 insertions(+), 3 deletions(-)
> > create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h
> >
> > diff --git a/drivers/hwtracing/coresight/Makefile
> > b/drivers/hwtracing/coresight/Makefile
> > index daad9f103a78..ea544206204d 100644
> > --- a/drivers/hwtracing/coresight/Makefile
> > +++ b/drivers/hwtracing/coresight/Makefile
> > @@ -16,7 +16,8 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o
> > coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \
> >coresight-etm3x-sysfs.o
> > obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o
> > -coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o
> > +coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o \
> > + coresight-etm4x-cfg.o
> > obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
> > obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
> > obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > new file mode 100644
> > index ..f237a8d02360
> > --- /dev/null
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> > @@ -0,0 +1,184 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright(C) 2020 Linaro Limited. All rights reserved.
> > + * Author: Mike Leach
> > + */
> > +
> > +#include "coresight-etm4x.h"
> > +#include "coresight-etm4x-cfg.h"
> > +#include "coresight-priv.h"
> > +#include "coresight-syscfg.h"
> > +
> > +/**
> > + * etm4_cfg_map_reg_offset - validate and map the register offset into a
> > + *location in the driver config struct.
> > + *
> > + * Limits the number of registers that can be accessed and programmed in
> > + * features, to those which are used to control the trace capture
> > parameters.
> > + *
> > + * Omits or limits access to those which the driver must use exclusively.
> > + *
> > + * Invalid offsets will result in fail code return and feature load
> > failure.
> > + *
> > + * @drvdata: driver data to map into.
> > + * @reg: register to map.
> > + * @offset: device offset for the register
> > + */
> > +static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
> > +struct cscfg_reg_csdev *reg, u32 offset)
> > +{
> > + int err = -EINVAL, idx;
> > + struct etmv4_config *drvcfg = &drvdata->config;
> > + u32 off_mask;
> > +
> > +#define CHECKREG(cval, elem) \
> > + { \
> > + if (offset == cval) { \
> > + reg->drv_store = &drvcfg->elem; \
> > + err = 0; \
> > + break; \
> > + } \
> > + }
> > +
> > +#define CHECKREGIDX(cval, elem, off_idx, mask) \
> > + { \
> > + if (mask == cval) { \
> > + reg->drv_store = &drvcfg->elem[off_idx]; \
> > + err = 0; \
> > + break; \
> > + } \
> > + }
> > +
>
> I think we can live with switch-case, ignoring the Warnings generated by the
> checkpatch, making the code much more readable and less error prone.
>
> Otherwise, please could you move the above macro definitions to the top,
> outside this function ?
>
> > + if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) ||
> > + ((offset >= TRCSEQRSTEVR) && (offset <= TRCEXTINSELR)) ||
> > + ((offset >= TRCCIDCCTLR0) && (offse
[PATCH v5 10/10] coresight: docs: Add documentation for CoreSight config
Adds documentation for the CoreSight System configuration manager. Signed-off-by: Mike Leach Reviewed-by: Mathieu Poirier --- .../trace/coresight/coresight-config.rst | 244 ++ Documentation/trace/coresight/coresight.rst | 16 ++ 2 files changed, 260 insertions(+) create mode 100644 Documentation/trace/coresight/coresight-config.rst diff --git a/Documentation/trace/coresight/coresight-config.rst b/Documentation/trace/coresight/coresight-config.rst new file mode 100644 index ..a4e3ef295240 --- /dev/null +++ b/Documentation/trace/coresight/coresight-config.rst @@ -0,0 +1,244 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== +CoreSight System Configuration Manager +== + +:Author: Mike Leach +:Date: October 2020 + +Introduction + + +The CoreSight System Configuration manager is an API that allows the +programming of the CoreSight system with pre-defined configurations that +can then be easily enabled from sysfs or perf. + +Many CoreSight components can be programmed in complex ways - especially ETMs. +In addition, components can interact across the CoreSight system, often via +the cross trigger components such as CTI and CTM. These system settings can +be defined and enabled as named configurations. + + +Basic Concepts +== + +This section introduces the basic concepts of a CoreSight system configuration. + + +Features + + +A feature is a named set of programming for a CoreSight device. The programming +is device dependent, and can be defined in terms of absolute register values, +resource usage and parameter values. + +The feature is defined using a descriptor. This descriptor is used to load onto +a matching device, either when the feature is loaded into the system, or when the +CoreSight device is registered with the configuration manager. + +The load process involves interpreting the descriptor into a set of register +accesses in the driver - the resource usage and parameter descriptions +translated into appropriate register accesses. This interpretation makes it easy +and efficient for the feature to be programmed onto the device when required. + +The feature will not be active on the device until the feature is enabled, and +the device itself is enabled. When the device is enabled then enabled features +will be programmed into the device hardware. + +A feature is enabled as part of a configuration being enabled on the system. + + +Parameter Value +~~~ + +A parameter value is a named value that may be set by the user prior to the +feature being enabled that can adjust the behaviour of the operation programmed +by the feature. + +For example, this could be a count value in a programmed operation that repeats +at a given rate. When the feature is enabled then the current value of the +parameter is used in programming the device. + +The feature descriptor defines a default value for a parameter, which is used +if the user does not supply a new value. + +Users can update parameter values using the configfs API for the CoreSight +system - which is described below. + +The current value of the parameter is loaded into the device when the feature +is enabled on that device. + + +Configurations +-- + +A configuration defines a set of features that are to be used in a trace +session where the configuration is selected. For any trace session only one +configuration may be selected. + +The features defined may be on any type of device that is registered +to support system configuration. A configuration may select features to be +enabled on a class of devices - i.e. any ETMv4, or specific devices, e.g. a +specific CTI on the system. + +As with the feature, a descriptor is used to define the configuration. +This will define the features that must be enabled as part of the configuration +as well as any preset values that can be used to override default parameter +values. + + +Preset Values +~ + +Preset values are easily selectable sets of parameter values for the features +that the configuration uses. The number of values in a single preset set, equals +the sum of parameter values in the features used by the configuration. + +e.g. a configuration consists of 3 features, one has 2 parameters, one has +a single parameter, and another has no parameters. A single preset set will +therefore have 3 values. + +Presets are optionally defined by the configuration, up to 15 can be defined. +If no preset is selected, then the parameter values defined in the feature +are used as normal. + + +Operation +~ + +The following steps take place in the operation of a configuration. + +1) In this example, the configuration is 'autofdo', which has an + associated feature 'strobing' that works on ETMv4 CoreSight Devices. + +2) The configuration is enabled. For example 'perf' may select the + configurati
[PATCH v5 09/10] coresight: syscfg: Add initial configfs support
Adds configfs subsystem and attributes to the configuration manager
to enable the listing of loaded configurations and features.
The default values of feature parameters can be accessed and altered
from these attributes to affect all installed devices using the feature.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../coresight/coresight-syscfg-configfs.c | 399 ++
.../coresight/coresight-syscfg-configfs.h | 45 ++
.../hwtracing/coresight/coresight-syscfg.c| 77
.../hwtracing/coresight/coresight-syscfg.h| 7 +
5 files changed, 530 insertions(+), 1 deletion(-)
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.c
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index 2707bfef1b76..391c93a08902 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -5,7 +5,8 @@
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
coresight-sysfs.o coresight-syscfg.o coresight-config.o \
- coresight-cfg-preload.o coresight-cfg-afdo.o
+ coresight-cfg-preload.o coresight-cfg-afdo.o \
+ coresight-syscfg-configfs.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
new file mode 100644
index ..7cefad81d1f6
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Linaro Limited, All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include
+
+#include "coresight-syscfg-configfs.h"
+
+/* create a default ci_type. */
+static inline struct config_item_type *cscfg_create_ci_type(void)
+{
+ struct config_item_type *ci_type;
+
+ ci_type = devm_kzalloc(cscfg_device(), sizeof(*ci_type), GFP_KERNEL);
+ if (ci_type)
+ ci_type->ct_owner = THIS_MODULE;
+
+ return ci_type;
+}
+
+/* configurations sub-group */
+
+/* attributes for the config view group */
+static ssize_t cscfg_cfg_description_show(struct config_item *item, char *page)
+{
+ struct cscfg_fs_config *fs_config = container_of(to_config_group(item),
+struct
cscfg_fs_config, group);
+
+ return scnprintf(page, PAGE_SIZE, "%s\n",
fs_config->config_desc->description);
+}
+CONFIGFS_ATTR_RO(cscfg_cfg_, description);
+
+static ssize_t cscfg_cfg_feature_refs_show(struct config_item *item, char
*page)
+{
+ struct cscfg_fs_config *fs_config = container_of(to_config_group(item),
+struct
cscfg_fs_config, group);
+ const struct cscfg_config_desc *config_desc = fs_config->config_desc;
+ ssize_t ch_used = 0;
+ int i;
+
+ if (config_desc->nr_feat_refs) {
+ for (i = 0; i < config_desc->nr_feat_refs; i++) {
+ ch_used += scnprintf(page + ch_used, PAGE_SIZE -
ch_used,
+"%s\n",
config_desc->feat_ref_names[i]);
+ }
+ }
+ return ch_used;
+}
+CONFIGFS_ATTR_RO(cscfg_cfg_, feature_refs);
+
+/* list preset values in order of features and params */
+static ssize_t cscfg_cfg_values_show(struct config_item *item, char *page)
+{
+ const struct cscfg_feature_desc *feat_desc;
+ const struct cscfg_config_desc *config_desc;
+ struct cscfg_fs_preset *fs_preset;
+ int i, j, val_idx, preset_idx;
+ ssize_t used = 0;
+
+ fs_preset = container_of(to_config_group(item), struct cscfg_fs_preset,
group);
+ config_desc = fs_preset->config_desc;
+
+ if (!config_desc->nr_presets)
+ return 0;
+
+ preset_idx = fs_preset->preset_num - 1;
+
+ /* start index on the correct array line */
+ val_idx = config_desc->nr_total_params * preset_idx;
+
+ /*
+* A set of presets is the sum of all params in used features,
+* in order of declaration of features and params in the features
+*/
+ for (i = 0; i < config_desc->nr_feat_refs; i++) {
+ feat_desc =
cscfg_get_named_feat_desc(config_desc->feat_ref_names[i]);
+ for (j = 0; j < feat_desc->nr_params; j++) {
+ used += scnprintf(page + used, PAGE_SIZE - used,
+ "%s.%s = 0x%llx ",
+
[PATCH v5 08/10] coresight: config: Add preloaded configurations
Preload set of configurations.
This patch creates a small set of preloaded configurations and features
that are available immediately after coresight has been initialised.
The current set provides a strobing feature for ETMv4, that creates a
periodic sampling of trace by switching trace generation on and off
using counters in the ETM.
A configuration called "autofdo" is also provided that uses the 'strobing'
feature and provides a couple of preset values, selectable on the perf
command line.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../hwtracing/coresight/coresight-cfg-afdo.c | 149 ++
.../coresight/coresight-cfg-preload.c | 27
.../coresight/coresight-cfg-preload.h | 11 ++
.../hwtracing/coresight/coresight-etm4x-cfg.h | 15 ++
.../hwtracing/coresight/coresight-syscfg.c| 9 ++
.../hwtracing/coresight/coresight-syscfg.h| 1 +
7 files changed, 214 insertions(+), 1 deletion(-)
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-afdo.c
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.c
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index ea544206204d..2707bfef1b76 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -4,7 +4,8 @@
#
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
- coresight-sysfs.o coresight-syscfg.o coresight-config.o
+ coresight-sysfs.o coresight-syscfg.o coresight-config.o \
+ coresight-cfg-preload.o coresight-cfg-afdo.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-cfg-afdo.c
b/drivers/hwtracing/coresight/coresight-cfg-afdo.c
new file mode 100644
index ..44d60ca1da49
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-cfg-afdo.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2020 Linaro Limited. All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include "coresight-config.h"
+#include "coresight-etm4x-cfg.h"
+
+/* preload configurations and features */
+
+/* preload in features for ETMv4 */
+
+/* strobe feature */
+static struct cscfg_parameter_desc strobe_params[] = {
+ {
+ .name = "window",
+ .value = 5000,
+ },
+ {
+ .name = "period",
+ .value = 1,
+ },
+};
+
+static struct cscfg_regval_desc strobe_regs[] = {
+ /* resource selectors */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCRSCTLRn(2),
+ .hw_info = ETM4_CFG_RES_SEL,
+ .val32 = 0x20001,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCRSCTLRn(3),
+ .hw_info = ETM4_CFG_RES_SEQ,
+ .val32 = 0x20002,
+ },
+ /* strobe window counter 0 - reload from param 0 */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE,
+ .offset = TRCCNTVRn(0),
+ .hw_info = ETM4_CFG_RES_CTR,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM,
+ .offset = TRCCNTRLDVRn(0),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 0,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCCNTCTLRn(0),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 0x10001,
+ },
+ /* strobe period counter 1 - reload from param 1 */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE,
+ .offset = TRCCNTVRn(1),
+ .hw_info = ETM4_CFG_RES_CTR,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM,
+ .offset = TRCCNTRLDVRn(1),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 1,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCCNTCTLRn(1),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 0x8102,
+ },
+ /* sequencer */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCSEQEVRn(0),
+ .hw_info = ETM4_CFG_RES_SEQ,
+ .val32 = 0x0081,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCSEQEVRn(1),
+ .hw_info = ETM4_CFG_RES_SEQ,
+ .val32 = 0x,
+ },
+ /* view-i
[PATCH v5 06/10] coresight: etm-perf: Update to activate selected configuration
Add calls to activate the selected configuration as perf starts
and stops the tracing session.
Signed-off-by: Mike Leach
Reviewed-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 14 +-
drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 66bda452a2f4..9128f59864a8 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -196,6 +196,10 @@ static void free_event_data(struct work_struct *work)
/* Free the sink buffers, if there are any */
free_sink_buffer(event_data);
+ /* clear any configuration we were using */
+ if (event_data->cfg_hash)
+ cscfg_deactivate_config(event_data->cfg_hash);
+
for_each_cpu(cpu, mask) {
struct list_head **ppath;
@@ -254,7 +258,7 @@ static void etm_free_aux(void *data)
static void *etm_setup_aux(struct perf_event *event, void **pages,
int nr_pages, bool overwrite)
{
- u32 id;
+ u32 id, cfg_hash;
int cpu = event->cpu;
cpumask_t *mask;
struct coresight_device *sink = NULL;
@@ -271,6 +275,14 @@ static void *etm_setup_aux(struct perf_event *event, void
**pages,
sink = coresight_get_sink_by_id(id);
}
+ /* check if user wants a coresight configuration selected */
+ cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32);
+ if (cfg_hash) {
+ if (cscfg_activate_config(cfg_hash))
+ goto err;
+ event_data->cfg_hash = cfg_hash;
+ }
+
mask = &event_data->mask;
/*
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h
b/drivers/hwtracing/coresight/coresight-etm-perf.h
index ba617fe2217e..468f7799ab4f 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.h
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.h
@@ -49,12 +49,14 @@ struct etm_filters {
* @work: Handle to free allocated memory outside IRQ context.
* @mask: Hold the CPU(s) this event was set for.
* @snk_config:The sink configuration.
+ * @cfg_hash: The hash id of any coresight config selected.
* @path: An array of path, each slot for one CPU.
*/
struct etm_event_data {
struct work_struct work;
cpumask_t mask;
void *snk_config;
+ u32 cfg_hash;
struct list_head * __percpu *path;
};
--
2.17.1
[PATCH v5 05/10] coresight: syscfg: Add API to activate and enable configurations
Configurations are first activated, then when any coresight device is
enabled, the active configurations are checked and any matching
one is enabled.
This patch provides the activation / enable API.
Signed-off-by: Mike Leach
---
.../hwtracing/coresight/coresight-config.h| 2 +
.../hwtracing/coresight/coresight-syscfg.c| 122 ++
.../hwtracing/coresight/coresight-syscfg.h| 8 ++
include/linux/coresight.h | 2 +
4 files changed, 134 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
index 38fd1c71eb05..f1a5957a25c9 100644
--- a/drivers/hwtracing/coresight/coresight-config.h
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -127,6 +127,7 @@ struct cscfg_feature_desc {
* @nr_total_params: Sum of all parameters declared by used features
* @presets: Array of preset values.
* @event_ea: Extended attribute for perf event value
+ * @active_cnt:ref count for activate on this configuration.
*
*/
struct cscfg_config_desc {
@@ -139,6 +140,7 @@ struct cscfg_config_desc {
int nr_total_params;
const u64 *presets; /* nr_presets * nr_total_params */
struct dev_ext_attribute *event_ea;
+ atomic_t active_cnt;
};
/**
diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c
b/drivers/hwtracing/coresight/coresight-syscfg.c
index 03014a2142c1..c44746d6cd6d 100644
--- a/drivers/hwtracing/coresight/coresight-syscfg.c
+++ b/drivers/hwtracing/coresight/coresight-syscfg.c
@@ -284,6 +284,7 @@ static int cscfg_load_config(struct cscfg_config_desc
*config_desc)
return err;
list_add(&config_desc->item, &cscfg_mgr->config_desc_list);
+ atomic_set(&config_desc->active_cnt, 0);
return 0;
}
@@ -451,6 +452,126 @@ void cscfg_unregister_csdev(struct coresight_device
*csdev)
}
EXPORT_SYMBOL_GPL(cscfg_unregister_csdev);
+void cscfg_csdev_reset_feats(struct coresight_device *csdev)
+{
+ struct cscfg_feature_csdev *feat_csdev;
+
+ mutex_lock(&cscfg_csdev_mutex);
+ if (list_empty(&csdev->feature_csdev_list))
+ goto unlock_exit;
+
+ list_for_each_entry(feat_csdev, &csdev->feature_csdev_list, node)
+ cscfg_reset_feat(feat_csdev);
+
+unlock_exit:
+ mutex_unlock(&cscfg_csdev_mutex);
+}
+EXPORT_SYMBOL_GPL(cscfg_csdev_reset_feats);
+
+/**
+ * Mark a config descriptor as active.
+ * This will be seen when csdev devices are activated in the system.
+ *
+ * Selection by hash value - generated from the configuration name when it
+ * was loaded and added to the cs_etm/configurations file system for selection
+ * by perf.
+ *
+ * @cfg_hash: Hash value of the selected configuration name.
+ */
+int cscfg_activate_config(unsigned long cfg_hash)
+{
+ struct cscfg_config_desc *config_desc;
+ int err = -EINVAL;
+
+ mutex_lock(&cscfg_mutex);
+
+ list_for_each_entry(config_desc, &cscfg_mgr->config_desc_list, item) {
+ if ((unsigned long)config_desc->event_ea->var == cfg_hash) {
+ /*
+* increment the global active count - control changes
to
+* active configurations
+*/
+ atomic_inc(&cscfg_mgr->sys_active_cnt);
+
+ /*
+* mark the descriptor as active so enable config on a
+* device instance will use it
+*/
+ atomic_inc(&config_desc->active_cnt);
+
+ err = 0;
+ dev_dbg(cscfg_device(), "Activate config %s.\n",
config_desc->name);
+ break;
+ }
+ }
+ mutex_unlock(&cscfg_mutex);
+
+ return err;
+}
+EXPORT_SYMBOL_GPL(cscfg_activate_config);
+
+void cscfg_deactivate_config(unsigned long cfg_hash)
+{
+ struct cscfg_config_desc *config_desc;
+
+ mutex_lock(&cscfg_mutex);
+
+ list_for_each_entry(config_desc, &cscfg_mgr->config_desc_list, item) {
+ if ((unsigned long)config_desc->event_ea->var == cfg_hash) {
+ atomic_dec(&config_desc->active_cnt);
+ atomic_dec(&cscfg_mgr->sys_active_cnt);
+ dev_dbg(cscfg_device(), "Deactivate config %s.\n",
config_desc->name);
+ break;
+ }
+ }
+ mutex_unlock(&cscfg_mutex);
+}
+EXPORT_SYMBOL_GPL(cscfg_deactivate_config);
+
+/* Find and program any active config for the supplied device.*/
+int cscfg_csdev_enable_active_config(struct coresight_device *csdev,
+unsigned long cfg_hash, int preset)
+{
+ struct cscfg_config_csdev *config_csdev_acti
[PATCH v5 04/10] coresight: etm-perf: update to handle configuration selection
Loaded coresight configurations are registered in the cs_etm\cs_config sub
directory. This extends the etm-perf code to handle these registrations,
and the cs_syscfg driver to perform the registration on load.
Signed-off-by: Mike Leach
---
.../hwtracing/coresight/coresight-config.h| 2 +
.../hwtracing/coresight/coresight-etm-perf.c | 139 ++
.../hwtracing/coresight/coresight-etm-perf.h | 8 +
.../hwtracing/coresight/coresight-syscfg.c| 12 ++
4 files changed, 130 insertions(+), 31 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
index f70561c1504b..38fd1c71eb05 100644
--- a/drivers/hwtracing/coresight/coresight-config.h
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -126,6 +126,7 @@ struct cscfg_feature_desc {
* @nr_presets:Number of sets of presets supplied by this
configuration.
* @nr_total_params: Sum of all parameters declared by used features
* @presets: Array of preset values.
+ * @event_ea: Extended attribute for perf event value
*
*/
struct cscfg_config_desc {
@@ -137,6 +138,7 @@ struct cscfg_config_desc {
int nr_presets;
int nr_total_params;
const u64 *presets; /* nr_presets * nr_total_params */
+ struct dev_ext_attribute *event_ea;
};
/**
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 0e392513b2d6..66bda452a2f4 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -18,8 +18,10 @@
#include
#include
+#include "coresight-config.h"
#include "coresight-etm-perf.h"
#include "coresight-priv.h"
+#include "coresight-syscfg.h"
static struct pmu etm_pmu;
static bool etm_perf_up;
@@ -38,8 +40,13 @@ PMU_FORMAT_ATTR(contextid1, "config:"
__stringify(ETM_OPT_CTXTID));
PMU_FORMAT_ATTR(contextid2,"config:" __stringify(ETM_OPT_CTXTID2));
PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS));
PMU_FORMAT_ATTR(retstack, "config:" __stringify(ETM_OPT_RETSTK));
+/* preset - if sink ID is used as a configuration selector */
+PMU_FORMAT_ATTR(preset,"config:0-3");
/* Sink ID - same for all ETMs */
PMU_FORMAT_ATTR(sinkid,"config2:0-31");
+/* config ID - set if a system configuration is selected */
+PMU_FORMAT_ATTR(configid, "config2:32-63");
+
/*
* contextid always traces the "PID". The PID is in CONTEXTIDR_EL1
@@ -69,6 +76,8 @@ static struct attribute *etm_config_formats_attr[] = {
&format_attr_timestamp.attr,
&format_attr_retstack.attr,
&format_attr_sinkid.attr,
+ &format_attr_preset.attr,
+ &format_attr_configid.attr,
NULL,
};
@@ -86,9 +95,19 @@ static const struct attribute_group etm_pmu_sinks_group = {
.attrs = etm_config_sinks_attr,
};
+static struct attribute *etm_config_events_attr[] = {
+ NULL,
+};
+
+static const struct attribute_group etm_pmu_events_group = {
+ .name = "events",
+ .attrs = etm_config_events_attr,
+};
+
static const struct attribute_group *etm_pmu_attr_groups[] = {
&etm_pmu_format_group,
&etm_pmu_sinks_group,
+ &etm_pmu_events_group,
NULL,
};
@@ -247,7 +266,7 @@ static void *etm_setup_aux(struct perf_event *event, void
**pages,
INIT_WORK(&event_data->work, free_event_data);
/* First get the selected sink from user space. */
- if (event->attr.config2) {
+ if (event->attr.config2 & GENMASK_ULL(31, 0)) {
id = (u32)event->attr.config2;
sink = coresight_get_sink_by_id(id);
}
@@ -555,9 +574,9 @@ int etm_perf_symlink(struct coresight_device *csdev, bool
link)
}
EXPORT_SYMBOL_GPL(etm_perf_symlink);
-static ssize_t etm_perf_sink_name_show(struct device *dev,
- struct device_attribute *dattr,
- char *buf)
+static ssize_t etm_perf_name_show(struct device *dev,
+ struct device_attribute *dattr,
+ char *buf)
{
struct dev_ext_attribute *ea;
@@ -565,68 +584,126 @@ static ssize_t etm_perf_sink_name_show(struct device
*dev,
return scnprintf(buf, PAGE_SIZE, "0x%lx\n", (unsigned long)(ea->var));
}
-int etm_perf_add_symlink_sink(struct coresight_device *csdev)
+static struct dev_ext_attribute *
+etm_perf_add_symlink_group(struct device *dev, const char *name, const char
*group_name)
{
- int ret;
+ struct dev_ext_attribute *ea;
unsigned long hash;
- const char *name;
+ int ret;
struct device *pmu_dev = etm_pmu.
[PATCH v5 07/10] coresight: etm4x: Add complex configuration handlers to etmv4
Adds in handlers to allow the ETMv4 to use the complex configuration
support. Features and configurations can be loaded and selected in the
device.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../hwtracing/coresight/coresight-etm4x-cfg.c | 182 ++
.../hwtracing/coresight/coresight-etm4x-cfg.h | 15 ++
.../coresight/coresight-etm4x-core.c | 38 +++-
.../coresight/coresight-etm4x-sysfs.c | 3 +
5 files changed, 238 insertions(+), 3 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c
create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index daad9f103a78..ea544206204d 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -16,7 +16,8 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o
coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \
coresight-etm3x-sysfs.o
obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o
-coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o
+coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o \
+ coresight-etm4x-cfg.o
obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
new file mode 100644
index ..de612498b29d
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2020 Linaro Limited. All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include "coresight-etm4x.h"
+#include "coresight-etm4x-cfg.h"
+#include "coresight-priv.h"
+#include "coresight-syscfg.h"
+
+/* defines to associate register IDs with driver data locations */
+#define CHECKREG(cval, elem) \
+ { \
+ if (offset == cval) { \
+ reg_csdev->driver_regval = &drvcfg->elem; \
+ err = 0; \
+ break; \
+ } \
+ }
+
+#define CHECKREGIDX(cval, elem, off_idx, mask) \
+ { \
+ if (mask == cval) { \
+ reg_csdev->driver_regval = &drvcfg->elem[off_idx]; \
+ err = 0; \
+ break; \
+ } \
+ }
+
+/**
+ * etm4_cfg_map_reg_offset - validate and map the register offset into a
+ * location in the driver config struct.
+ *
+ * Limits the number of registers that can be accessed and programmed in
+ * features, to those which are used to control the trace capture parameters.
+ *
+ * Omits or limits access to those which the driver must use exclusively.
+ *
+ * Invalid offsets will result in fail code return and feature load failure.
+ *
+ * @drvdata: driver data to map into.
+ * @reg: register to map.
+ * @offset:device offset for the register
+ */
+static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
+ struct cscfg_regval_csdev *reg_csdev, u32
offset)
+{
+ int err = -EINVAL, idx;
+ struct etmv4_config *drvcfg = &drvdata->config;
+ u32 off_mask;
+
+ if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) ||
+ ((offset >= TRCSEQRSTEVR) && (offset <= TRCEXTINSELR)) ||
+ ((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) {
+ do {
+ CHECKREG(TRCEVENTCTL0R, eventctrl0);
+ CHECKREG(TRCEVENTCTL1R, eventctrl1);
+ CHECKREG(TRCSTALLCTLR, stall_ctrl);
+ CHECKREG(TRCTSCTLR, ts_ctrl);
+ CHECKREG(TRCSYNCPR, syncfreq);
+ CHECKREG(TRTLR, ccctlr);
+ CHECKREG(TRCBBCTLR, bb_ctrl);
+ CHECKREG(TRCVICTLR, vinst_ctrl);
+ CHECKREG(TRCVIIECTLR, viiectlr);
+ CHECKREG(TRCVISSCTLR, vissctlr);
+ CHECKREG(TRCVIPCSSCTLR, vipcssctlr);
+ CHECKREG(TRCSEQRSTEVR, seq_rst);
+ CHECKREG(TRCSEQSTR, seq_state);
+ CHECKREG(TRCEXTINSELR, ext_inp);
+ CHECKREG(TRCCIDCCTLR0, ctxid_mask0);
+ CHECKREG(TRCCIDCCTLR1, ctxid_mask1);
+ CHECKREG(TRCVMIDCCTLR0, vmid_mask0);
+ CHECKREG(TRCVMIDCCTLR1, vmid_mask1);
+ } while (0);
+ } else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) {
+ /* sequencer state cont
[PATCH v5 02/10] coresight: syscfg: Add registration and feature loading for cs devices
API for individual devices to register with the syscfg management
system is added.
Devices register with matching information, and any features or
configurations that match will be loaded into the device.
The feature and configuration loading is extended so that on load these
are loaded into any currently registered devices. This allows
configuration loading after devices have been registered.
Signed-off-by: Mike Leach
---
.../hwtracing/coresight/coresight-config.h| 98 ++
.../hwtracing/coresight/coresight-syscfg.c| 324 +-
.../hwtracing/coresight/coresight-syscfg.h| 19 +
include/linux/coresight.h | 5 +
4 files changed, 445 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
index 21aa7464dcdc..685fb46ce893 100644
--- a/drivers/hwtracing/coresight/coresight-config.h
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -139,4 +139,102 @@ struct cscfg_config_desc {
const u64 *presets; /* nr_presets * nr_total_params */
};
+/**
+ * config register instance - part of a loaded feature.
+ *maps register values to csdev driver structures
+ *
+ * @reg_desc: value to use when setting feature on device / store for
+ * readback of volatile values.
+ * @driver_regval: pointer to internal driver element used to set the value
+ * in hardware.
+ */
+struct cscfg_regval_csdev {
+ struct cscfg_regval_desc reg_desc;
+ void *driver_regval;
+};
+
+/**
+ * config parameter instance - part of a loaded feature.
+ *
+ * @feat_csdev:parent feature
+ * @reg_csdev: register value updated by this parameter.
+ * @current_value: current value of parameter - may be set by user via
+ * sysfs, or modified during device operation.
+ * @val64: true if 64 bit value
+ */
+struct cscfg_parameter_csdev {
+ struct cscfg_feature_csdev *feat_csdev;
+ struct cscfg_regval_csdev *reg_csdev;
+ u64 current_value;
+ bool val64;
+};
+
+/**
+ * Feature instance loaded into a CoreSight device.
+ *
+ * When a feature is loaded into a specific device, then this structure holds
+ * the connections between the register / parameter values used and the
+ * internal data structures that are written when the feature is enabled.
+ *
+ * Since applying a feature modifies internal data structures in the device,
+ * then we have a reference to the device spinlock to protect access to these
+ * structures (@drv_spinlock).
+ *
+ * @feat_desc: pointer to the static descriptor for this feature.
+ * @csdev: parent CoreSight device instance.
+ * @node: list entry into feature list for this device.
+ * @drv_spinlock: device spinlock for access to driver register data.
+ * @nr_params: number of parameters.
+ * @params_csdev: current parameter values on this device
+ * @nr_regs: number of registers to be programmed.
+ * @regs_csdev:Programming details for the registers
+ */
+struct cscfg_feature_csdev {
+ const struct cscfg_feature_desc *feat_desc;
+ struct coresight_device *csdev;
+ struct list_head node;
+ spinlock_t *drv_spinlock;
+ int nr_params;
+ struct cscfg_parameter_csdev *params_csdev;
+ int nr_regs;
+ struct cscfg_regval_csdev *regs_csdev;
+};
+
+/**
+ * Configuration instance when loaded into a CoreSight device.
+ *
+ * The instance contains references to loaded features on this device that are
+ * used by the configuration.
+ *
+ * @config_desc:reference to the descriptor for this configuration
+ * @csdev: parent coresight device for this configuration instance.
+ * @enabled: true if configuration is enabled on this device.
+ * @node: list entry within the coresight device
+ * @nr_feat: Number of features on this device that are used in the
+ * configuration.
+ * @feats_csdev:references to the device features to enable.
+ */
+struct cscfg_config_csdev {
+ const struct cscfg_config_desc *config_desc;
+ struct coresight_device *csdev;
+ bool enabled;
+ struct list_head node;
+ int nr_feat;
+ struct cscfg_feature_csdev *feats_csdev[0];
+};
+
+/**
+ * Coresight device operations.
+ *
+ * Registered coresight devices provide these operations to manage feature
+ * instances compatible with the device hardware and drivers
+ *
+ * @load_feat: Pass a feature descriptor into the device and create the
+ * loaded feature instance (struct cscfg_feature_csdev).
+ */
+struct cscfg_csdev_feat_ops {
+ int (*load_feat)(struct coresight_device *csdev,
+struct cscfg_feature_csdev *feat_csdev);
+};
+
#endif /* _CORESIGHT_CORESIGHT_CONFIG_H */
diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c
b/drivers/hwtracing
[PATCH v5 03/10] coresight: config: Add configuration and feature generic functions
Adds a set of generic support functions that allow devices to set and save
features values on the device, and enable and disable configurations.
Additional functions for other common operations including feature
reset.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 2 +-
.../hwtracing/coresight/coresight-config.c| 274 ++
.../hwtracing/coresight/coresight-config.h| 9 +
.../hwtracing/coresight/coresight-syscfg.c| 3 +-
4 files changed, 286 insertions(+), 2 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-config.c
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index 4ce854c434b1..daad9f103a78 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -4,7 +4,7 @@
#
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
- coresight-sysfs.o coresight-syscfg.o
+ coresight-sysfs.o coresight-syscfg.o coresight-config.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-config.c
b/drivers/hwtracing/coresight/coresight-config.c
new file mode 100644
index ..571e90485c06
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-config.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2020 Linaro Limited. All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include
+#include "coresight-config.h"
+#include "coresight-priv.h"
+
+/*
+ * This provides a set of generic functions that operate on configurations
+ * and features to manage the handling of parameters, the programming and
+ * saving of registers used by features on devices.
+ */
+
+/*
+ * Write the value held in the register structure into the driver internal
memory
+ * location.
+ */
+static void cscfg_set_reg(struct cscfg_regval_csdev *reg_csdev)
+{
+ u32 *p_val32 = (u32 *)reg_csdev->driver_regval;
+ u32 tmp32 = reg_csdev->reg_desc.val32;
+
+ if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT) {
+ *((u64 *)reg_csdev->driver_regval) = reg_csdev->reg_desc.val64;
+ return;
+ }
+
+ if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_MASK) {
+ tmp32 = *p_val32;
+ tmp32 &= ~reg_csdev->reg_desc.mask32;
+ tmp32 |= reg_csdev->reg_desc.val32 & reg_csdev->reg_desc.mask32;
+ }
+ *p_val32 = tmp32;
+}
+
+/*
+ * Read the driver value into the reg if this is marked as one we want to save.
+ */
+static void cscfg_save_reg(struct cscfg_regval_csdev *reg_csdev)
+{
+ if (!(reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_SAVE))
+ return;
+ if (reg_csdev->reg_desc.type & CS_CFG_REG_TYPE_VAL_64BIT)
+ reg_csdev->reg_desc.val64 = *(u64 *)(reg_csdev->driver_regval);
+ else
+ reg_csdev->reg_desc.val32 = *(u32 *)(reg_csdev->driver_regval);
+}
+
+/*
+ * Some register values are set from parameters. Initialise these registers
+ * from the current parameter values.
+ */
+static void cscfg_init_reg_param(struct cscfg_feature_csdev *feat_csdev,
+struct cscfg_regval_desc *reg_desc,
+struct cscfg_regval_csdev *reg_csdev)
+{
+ struct cscfg_parameter_csdev *param_csdev;
+
+ /* for param, load routines have validated the index */
+ param_csdev = &feat_csdev->params_csdev[reg_desc->param_idx];
+ param_csdev->reg_csdev = reg_csdev;
+ param_csdev->val64 = reg_csdev->reg_desc.type &
CS_CFG_REG_TYPE_VAL_64BIT;
+
+ if (param_csdev->val64)
+ reg_csdev->reg_desc.val64 = param_csdev->current_value;
+ else
+ reg_csdev->reg_desc.val32 = (u32)param_csdev->current_value;
+}
+
+/* set values into the driver locations referenced in cscfg_reg_csdev */
+static int cscfg_set_on_enable(struct cscfg_feature_csdev *feat_csdev)
+{
+ int i;
+
+ spin_lock(feat_csdev->drv_spinlock);
+ for (i = 0; i < feat_csdev->nr_regs; i++)
+ cscfg_set_reg(&feat_csdev->regs_csdev[i]);
+ spin_unlock(feat_csdev->drv_spinlock);
+ dev_dbg(&feat_csdev->csdev->dev, "Feature %s: %s",
+ feat_csdev->feat_desc->name, "set on enable");
+ return 0;
+}
+
+/* copy back values from the driver locations referenced in cscfg_reg_csdev */
+static void cscfg_save_on_disable(struct cscfg_feature_csdev *feat_csdev)
+{
+ int i;
+
+ spin_lock(feat_csdev->drv_spinlock);
+ for (i = 0; i < feat_csdev->nr_regs; i++)
+
[PATCH v5 01/10] coresight: syscfg: Initial coresight system configuration
Creates an system management API to allow complex configurations and
features to be programmed into a CoreSight infrastructure.
A feature is defined as a programming set for a device or class of
devices.
A configuration is a set of features across the system that are enabled
for a trace session.
The API will manage system wide configuration, and allow complex
programmed features to be added to individual device instances, and
provide for system wide configuration selection on trace capture
operations.
This patch creates the initial data object and the initial API for
loading configurations and features.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 2 +-
.../hwtracing/coresight/coresight-config.h| 142 +
drivers/hwtracing/coresight/coresight-core.c | 12 +-
.../hwtracing/coresight/coresight-etm-perf.c | 2 +-
.../hwtracing/coresight/coresight-etm-perf.h | 2 +-
.../hwtracing/coresight/coresight-syscfg.c| 195 ++
.../hwtracing/coresight/coresight-syscfg.h| 46 +
7 files changed, 397 insertions(+), 4 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-config.h
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.c
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index f20e357758d1..4ce854c434b1 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -4,7 +4,7 @@
#
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
- coresight-sysfs.o
+ coresight-sysfs.o coresight-syscfg.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
new file mode 100644
index ..21aa7464dcdc
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 Linaro Limited, All rights reserved.
+ * Author: Mike Leach
+ */
+
+#ifndef _CORESIGHT_CORESIGHT_CONFIG_H
+#define _CORESIGHT_CORESIGHT_CONFIG_H
+
+#include
+#include
+
+/* CoreSight Configuration Management - component and system wide
configuration */
+
+/*
+ * Register type flags for register value descriptor:
+ * describe how the value is interpreted, and handled.
+ */
+#define CS_CFG_REG_TYPE_STD0x80/* reg is standard reg */
+#define CS_CFG_REG_TYPE_RESOURCE 0x40/* reg is a resource */
+#define CS_CFG_REG_TYPE_VAL_PARAM 0x08/* reg value uses param */
+#define CS_CFG_REG_TYPE_VAL_MASK 0x04/* reg value bit masked */
+#define CS_CFG_REG_TYPE_VAL_64BIT 0x02/* reg value 64 bit */
+#define CS_CFG_REG_TYPE_VAL_SAVE 0x01/* reg value save on disable */
+
+/*
+ * flags defining what device class a feature will match to when processing a
+ * system configuration - used by config data and devices.
+ */
+#define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */
+#define CS_CFG_MATCH_CLASS_SRC_ETM40x0002 /* match any ETMv4 device */
+
+/* flags defining device instance matching - used in config match desc data. */
+#define CS_CFG_MATCH_INST_ANY 0x8000 /* any instance of a class */
+
+/*
+ * Limit number of presets in a configuration
+ * This is related to the number of bits (4) we use to select the preset on
+ * the perf command line. Preset 0 is always none selected.
+ * See PMU_FORMAT_ATTR(preset, "config:0-3") in coresight-etm-perf.c
+ */
+#define CS_CFG_CONFIG_PRESET_MAX 15
+
+/**
+ * Parameter descriptor for a device feature.
+ *
+ * @name: Name of parameter.
+ * @value: Initial or default value.
+ */
+struct cscfg_parameter_desc {
+ const char *name;
+ u64 value;
+};
+
+/**
+ * Representation of register value and a descriptor of register usage.
+ *
+ * Used as a descriptor in the feature descriptors.
+ * Used as a value in when in a feature loading into a csdev.
+ *
+ * Supports full 64 bit register value, or 32 bit value with optional mask
+ * value.
+ *
+ * @type: define register usage and interpretation.
+ * @offset:the address offset for register in the hardware device (per
device specification).
+ * @hw_info: optional hardware device type specific information. (ETM / CTI
specific etc)
+ * @val64: 64 bit value.
+ * @val32: 32 bit value.
+ * @mask32:32 bit mask when using 32 bit value to access device register -
if mask type.
+ * @param_idx: parameter index value into parameter array if param type.
+ */
+struct cscfg_regval_desc {
+ struct {
+ u32 type:8;
+ u32 offset:12;
+ u32 hw_info:12;
+ };
+
[PATCH v5 00/10] CoreSight configuration management; ETM strobing
rom configuration - static replicators, funnels, tpiu. 3) Added perf selection of configuarations. 4) Rebased onto the coresight module loading set. To follow in future revisions / sets:- a) load of additional config and features by loadable module. b) load of additional config and features by configfs c) enhanced resource management for ETMv4 and checking features have sufficient resources to be enabled. d) ECT and CTI support for configuration and features. Mike Leach (10): coresight: syscfg: Initial coresight system configuration coresight: syscfg: Add registration and feature loading for cs devices coresight: config: Add configuration and feature generic functions coresight: etm-perf: update to handle configuration selection coresight: syscfg: Add API to activate and enable configurations coresight: etm-perf: Update to activate selected configuration coresight: etm4x: Add complex configuration handlers to etmv4 coresight: config: Add preloaded configurations coresight: syscfg: Add initial configfs support coresight: docs: Add documentation for CoreSight config .../trace/coresight/coresight-config.rst | 244 ++ Documentation/trace/coresight/coresight.rst | 16 + drivers/hwtracing/coresight/Makefile | 7 +- .../hwtracing/coresight/coresight-cfg-afdo.c | 149 .../coresight/coresight-cfg-preload.c | 27 + .../coresight/coresight-cfg-preload.h | 11 + .../hwtracing/coresight/coresight-config.c| 274 +++ .../hwtracing/coresight/coresight-config.h| 253 ++ drivers/hwtracing/coresight/coresight-core.c | 12 +- .../hwtracing/coresight/coresight-etm-perf.c | 155 +++- .../hwtracing/coresight/coresight-etm-perf.h | 12 +- .../hwtracing/coresight/coresight-etm4x-cfg.c | 182 + .../hwtracing/coresight/coresight-etm4x-cfg.h | 30 + .../coresight/coresight-etm4x-core.c | 38 +- .../coresight/coresight-etm4x-sysfs.c | 3 + .../coresight/coresight-syscfg-configfs.c | 399 ++ .../coresight/coresight-syscfg-configfs.h | 45 ++ .../hwtracing/coresight/coresight-syscfg.c| 738 ++ .../hwtracing/coresight/coresight-syscfg.h| 81 ++ include/linux/coresight.h | 7 + 20 files changed, 2644 insertions(+), 39 deletions(-) create mode 100644 Documentation/trace/coresight/coresight-config.rst create mode 100644 drivers/hwtracing/coresight/coresight-cfg-afdo.c create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.c create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.h create mode 100644 drivers/hwtracing/coresight/coresight-config.c create mode 100644 drivers/hwtracing/coresight/coresight-config.h create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.c create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.h create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.c create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.h -- 2.17.1
Re: [PATCH v4 02/10] coresight: syscfg: Add registration and feature loading for cs devices
Hi Suzuki
On Thu, 4 Mar 2021 at 10:33, Suzuki K Poulose wrote:
>
> Hi Mike
>
> There are some minor comments on the naming scheme of the structures,
> which I think might improve the code readability.
>
> e.g, in general anything that is associated with a csdev could be named
> as such csdev_*, rather than cscfg_*_csdev. The latter kind of implies
> "cscfg" is the "primary" object, while it is the csdev where we track
> this.
>
> Feel free to ignore.
>
> On 1/28/21 5:09 PM, Mike Leach wrote:
> > API for individual devices to register with the syscfg management
> > system is added.
> >
> > Devices register with matching information, and any features or
> > configurations that match will be loaded into the device.
> >
> > The feature and configuration loading is extended so that on load these
> > are loaded into any currently registered devices. This allows
> > configuration loading after devices have been registered.
> >
> > Signed-off-by: Mike Leach
> > ---
> > .../hwtracing/coresight/coresight-config.h| 98 +
> > .../hwtracing/coresight/coresight-syscfg.c| 348 ++
> > .../hwtracing/coresight/coresight-syscfg.h| 20 +
> > include/linux/coresight.h | 5 +
> > 4 files changed, 471 insertions(+)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-config.h
> > b/drivers/hwtracing/coresight/coresight-config.h
> > index 3fedf8ab3cee..75ecdecf7013 100644
> > --- a/drivers/hwtracing/coresight/coresight-config.h
> > +++ b/drivers/hwtracing/coresight/coresight-config.h
> > @@ -164,4 +164,102 @@ struct cscfg_config_desc {
> > const u64 *presets; /* nr_presets * nr_total_params */
> > };
> >
> > +/**
> > + * config register instance - part of a loaded feature.
> > + *maps register values to csdev driver
> > structures
> > + *
> > + * @value: value to use when setting feature on device / store for
> > + * readback of volatile values.
> > + * @drv_store: pointer to internal driver element used to set the
> > value
> > + * in hardware.
> > + */
> > +struct cscfg_reg_csdev {
>
> minor nit: csdev_csfg_reg ?
>
> > + struct cscfg_regval_desc value;
> > + void *drv_store;
> > +};
>
> I am not sure if it helps to move this drv_store field into csfg_regval_desc
> as "void *private". I haven't looked at the following patches. That way we
> have less number of structures to deal with.
>
drv_store is a per csdev instance value accessing per device data - so
cannot be part of the single registerregval_desc descriptor in the
feature desc.
> > +
> > +/**
> > + * config parameter instance - part of a loaded feature.
> > + *
> > + * @feat:parent feature
> > + * @reg: register value updated by this parameter.
> > + * @current_value: current value of parameter - may be set by user via
> > + * sysfs, or modified during device operation.
> > + * @val64: true if 64 bit value
> > + */
> > +struct cscfg_parameter_csdev {
>
> nit: cscdev_cfg_parameter ?
>
> > + struct cscfg_feature_csdev *feat;
>
> nit: s/feat/cscfg_feat ?
>
> > + struct cscfg_reg_csdev *reg;
>
> nit: s/reg/cscfg_reg/ ?
>
> > + u64 current_value;
> > + bool val64;
> > +};
> > +
> > +/**
> > + * Feature instance loaded into a CoreSight device.
> > + *
> > + * When a feature is loaded into a specific device, then this structure
> > holds
> > + * the connections between the register / parameter values used and the
> > + * internal data structures that are written when the feature is enabled.
> > + *
> > + * Since applying a feature modifies internal data structures in the
> > device,
> > + * then we have a reference to the device spinlock to protect access to
> > these
> > + * structures (@csdev_spinlock).
> > + *
> > + * @desc:pointer to the static descriptor for this feature.
> > + * @csdev: parent CoreSight device instance.
> > + * @node:list entry into feature list for this device.
> > + * @csdev_spinlock: device spinlock from csdev instance..
> > + * @nr_params: number of parameters.
> > + * @params: current parameter values on this device
> > + * @nr_regs: number of registers to be programmed.
> > + * @regs:Programming details for the registers
> > + */
> >
Re: [PATCH v4 18/19] coresight: sink: Add TRBE driver
Hi Suzuki, On Thu, 25 Feb 2021 at 19:36, Suzuki K Poulose wrote: > > From: Anshuman Khandual > > Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is > accessible via the system registers. The TRBE supports different addressing > modes including CPU virtual address and buffer modes including the circular > buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1), > an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the > access to the trace buffer could be prohibited by a higher exception level > (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU > private interrupt (PPI) on address translation errors and when the buffer > is full. Overall implementation here is inspired from the Arm SPE driver. > > Cc: Mathieu Poirier > Cc: Mike Leach > Cc: Suzuki K Poulose > Signed-off-by: Anshuman Khandual > Signed-off-by: Suzuki K Poulose > --- > Changes: > - Replaced TRBLIMITR_LIMIT_SHIFT with TRBBASER_BASE_SHIFT in > set_trbe_base_pointer() > - Dropped TRBBASER_BASE_MASK and TRBBASER_BASE_SHIFT from > get_trbe_base_pointer() > - Indentation changes for TRBE_BSC_NOT_[STOPPED|FILLED|TRIGGERED] definitions > - Moved DECLARE_PER_CPU(, csdev_sink) into coresight-priv.h > - Moved isb() from trbe_enable_hw() into set_trbe_limit_pointer_enabled() > - Dropped the space after type casting before vmap() > - Return 0 instead of EINVAL in arm_trbe_update_buffer() > - Add a comment in trbe_handle_overflow() > - Add a comment in arm_trbe_cpu_startup() > - Unregister coresight TRBE device when not supported > - Fix potential NULL handle dereference in IRQ handler with a spurious IRQ > - Read TRBIDR after is_trbe_programmable() in arm_trbe_probe_coresight_cpu() > - Replaced and modified trbe_drain_and_disable_local() in IRQ handler > - Updated arm_trbe_update_buffer() for handling a missing interrupt > - Dropped kfree() for all devm_xxx() allocated buffer > - Dropped additional blank line in documentation coresight/coresight-trbe.rst > - Added Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe > - Changed CONFIG_CORESIGHT_TRBE options, dependencies and helper write up > - Added comment for irq_work_run() > - Updated comment for minumum buffer length in arm_trbe_alloc_buffer() > - Dropped redundant smp_processor_id() from arm_trbe_probe_coresight_cpu() > - Fixed indentation in arm_trbe_probe_cpuhp() > - Added static for arm_trbe_free_buffer() > - Added comment for trbe_base element in trbe_buf structure > - Dropped IS_ERR() check from vmap() returned pointer > - Added WARN_ON(trbe_csdev) in arm_trbe_probe_coresight_cpu() > - Changed TRBE device names from arm_trbeX to just trbeX > - Dropped unused argument perf_output_handle from trbe_get_fault_act() > - Dropped IS_ERR() from kzalloc_node()/kcalloc() buffer in > arm_trbe_alloc_buffer() > - Dropped IS_ERR() and return -ENOMEM in arm_trbe_probe_coresight() > - Moved TRBE HW disabling before coresight cleanup in > arm_trbe_remove_coresight_cpu() > - Changed error return codes from arm_trbe_probe_irq() > - Changed error return codes from arm_trbe_device_probe() > - Changed arm_trbe_remove_coresight() order in arm_trbe_device_remove() > - Changed TRBE CPU support probe/remove sequence with for_each_cpu() iterator > - Changed coresight_register() in arm_trbe_probe_coresight_cpu() > - Changed error return code when cpuhp_setup_state_multi() fails in > arm_trbe_probe_cpuhp() > - Changed error return code when cpuhp_state_add_instance() fails in > arm_trbe_probe_cpuhp() > - Changed trbe_dbm as trbe_flag including its sysfs interface > - Handle race between update_buffer & IRQ handler > - Rework and split the TRBE probe to avoid lockdep due to memory allocation >from IPI calls (via coresight_register()) > - Fix handle->head updat for snapshot mode. > --- > .../testing/sysfs-bus-coresight-devices-trbe | 14 + > .../trace/coresight/coresight-trbe.rst| 38 + > drivers/hwtracing/coresight/Kconfig | 14 + > drivers/hwtracing/coresight/Makefile |1 + > drivers/hwtracing/coresight/coresight-trbe.c | 1149 + > drivers/hwtracing/coresight/coresight-trbe.h | 153 +++ > 6 files changed, 1369 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe > create mode 100644 Documentation/trace/coresight/coresight-trbe.rst > create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c > create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe > b/Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe > new file mode
Re: [PATCH v4 15/19] dts: bindings: Document device tree bindings for ETE
Hi Suzuki
Need to add this file and the TRBE bindings file to the ARM/CORESIGHT
section of the MAINTAINERS file.
Regards
Mike
On Sat, 6 Mar 2021 at 21:06, Rob Herring wrote:
>
> On Thu, Feb 25, 2021 at 07:35:39PM +, Suzuki K Poulose wrote:
> > Document the device tree bindings for Embedded Trace Extensions.
> > ETE can be connected to legacy coresight components and thus
> > could optionally contain a connection graph as described by
> > the CoreSight bindings.
> >
> > Cc: devicet...@vger.kernel.org
> > Cc: Mathieu Poirier
> > Cc: Mike Leach
> > Cc: Rob Herring
> > Signed-off-by: Suzuki K Poulose
> > ---
> > Changes:
> > - Fix out-ports defintion
> > ---
> > .../devicetree/bindings/arm/ete.yaml | 71 +++
> > 1 file changed, 71 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/arm/ete.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/arm/ete.yaml
> > b/Documentation/devicetree/bindings/arm/ete.yaml
> > new file mode 100644
> > index ..35a42d92bf97
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/ete.yaml
> > @@ -0,0 +1,71 @@
> > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> > +# Copyright 2021, Arm Ltd
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/arm/ete.yaml#";
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#";
> > +
> > +title: ARM Embedded Trace Extensions
> > +
> > +maintainers:
> > + - Suzuki K Poulose
> > + - Mathieu Poirier
> > +
> > +description: |
> > + Arm Embedded Trace Extension(ETE) is a per CPU trace component that
> > + allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
> > + architecture and has extended support for future architecture changes.
> > + The trace generated by the ETE could be stored via legacy CoreSight
> > + components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
> > + Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
> > + legacy CoreSight components, a node must be listed per instance, along
> > + with any optional connection graph as per the coresight bindings.
> > + See bindings/arm/coresight.txt.
> > +
> > +properties:
> > + $nodename:
> > +pattern: "^ete([0-9a-f]+)$"
> > + compatible:
> > +items:
> > + - const: arm,embedded-trace-extension
> > +
> > + cpu:
> > +description: |
> > + Handle to the cpu this ETE is bound to.
> > +$ref: /schemas/types.yaml#/definitions/phandle
> > +
> > + out-ports:
> > +description: |
> > + Output connections from the ETE to legacy CoreSight trace bus.
> > +$ref: /schemas/graph.yaml#/properties/port
>
> s/port/ports/
>
> And then you need:
>
>properties:
> port:
>description: what this port is
>$ref: /schemas/graph.yaml#/properties/port
>
> > +
> > +required:
> > + - compatible
> > + - cpu
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +
> > +# An ETE node without legacy CoreSight connections
> > + - |
> > +ete0 {
> > + compatible = "arm,embedded-trace-extension";
> > + cpu = <&cpu_0>;
> > +};
> > +# An ETE node with legacy CoreSight connections
> > + - |
> > + ete1 {
> > + compatible = "arm,embedded-trace-extension";
> > + cpu = <&cpu_1>;
> > +
> > + out-ports {/* legacy coresight connection */
> > + port {
> > + ete1_out_port: endpoint {
> > +remote-endpoint = <&funnel_in_port0>;
> > + };
> > + };
> > + };
> > + };
> > +
> > +...
> > --
> > 2.24.1
> >
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Re: [PATCH v4 17/19] coresight: core: Add support for dedicated percpu sinks
Hi,
On Thu, 25 Feb 2021 at 19:36, Suzuki K Poulose wrote:
>
> From: Anshuman Khandual
>
> Add support for dedicated sinks that are bound to individual CPUs. (e.g,
> TRBE). To allow quicker access to the sink for a given CPU bound source,
> keep a percpu array of the sink devices. Also, add support for building
> a path to the CPU local sink from the ETM.
>
> This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM.
> This new sink type is exclusively available and can only work with percpu
> source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PROC.
>
Minor nit: FEAT_TRBE architecturally guarantees a compatible
architectural FEAT_ETE source.
However _all_ CPU sources have CORESIGHT_DEV_SUBTYPE_SOURCE_PROC set,
ETMv3.x, PTM, ETM4.x and ETE alike.
In the code that follows - coresight_is_percpu_source() checks it is
any type of CPU source, not the FEAT_ETE type, which is fine as we
then check the cpu and if it has TRBE.
So the simplifications to the code from the first couple of patch sets
make this explanation slightly misleading. Could do to adjust if
re-spinning set.
Reviewed-by: Mike Leach
> This defines a percpu structure that accommodates a single coresight_device
> which can be used to store an initialized instance from a sink driver. As
> these sinks are exclusively linked and dependent on corresponding percpu
> sources devices, they should also be the default sink device during a perf
> session.
>
> Outwards device connections are scanned while establishing paths between a
> source and a sink device. But such connections are not present for certain
> percpu source and sink devices which are exclusively linked and dependent.
> Build the path directly and skip connection scanning for such devices.
>
> Cc: Mathieu Poirier
> Cc: Mike Leach
> Cc: Suzuki K Poulose
> Tested-by: Suzuki K Poulose
> Reviewed-by: Suzuki K Poulose
> Signed-off-by: Anshuman Khandual
> [Moved the set/get percpu sink APIs from TRBE patch to here]
> Signed-off-by: Suzuki K Poulose
> ---
> Changes:
> - Export methods to set/get percpu sinks for fixing module
>build for TRBE
> - Addressed coding style comments (Suzuki)
> - Check status of _coresight_build_path() (Mathieu)
> ---
> drivers/hwtracing/coresight/coresight-core.c | 29 ++--
> drivers/hwtracing/coresight/coresight-priv.h | 3 ++
> include/linux/coresight.h| 12
> 3 files changed, 42 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-core.c
> b/drivers/hwtracing/coresight/coresight-core.c
> index 0062c8935653..55c645616bf6 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -23,6 +23,7 @@
> #include "coresight-priv.h"
>
> static DEFINE_MUTEX(coresight_mutex);
> +DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
>
> /**
> * struct coresight_node - elements of a path, from source to sink
> @@ -70,6 +71,18 @@ void coresight_remove_cti_ops(void)
> }
> EXPORT_SYMBOL_GPL(coresight_remove_cti_ops);
>
> +void coresight_set_percpu_sink(int cpu, struct coresight_device *csdev)
> +{
> + per_cpu(csdev_sink, cpu) = csdev;
> +}
> +EXPORT_SYMBOL_GPL(coresight_set_percpu_sink);
> +
> +struct coresight_device *coresight_get_percpu_sink(int cpu)
> +{
> + return per_cpu(csdev_sink, cpu);
> +}
> +EXPORT_SYMBOL_GPL(coresight_get_percpu_sink);
> +
> static int coresight_id_match(struct device *dev, void *data)
> {
> int trace_id, i_trace_id;
> @@ -784,6 +797,14 @@ static int _coresight_build_path(struct coresight_device
> *csdev,
> if (csdev == sink)
> goto out;
>
> + if (coresight_is_percpu_source(csdev) &&
> coresight_is_percpu_sink(sink) &&
> + sink == per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev))) {
> + if (_coresight_build_path(sink, sink, path) == 0) {
> + found = true;
> + goto out;
> + }
> + }
> +
> /* Not a sink - recursively explore each port found on this element */
> for (i = 0; i < csdev->pdata->nr_outport; i++) {
> struct coresight_device *child_dev;
> @@ -999,8 +1020,12 @@ coresight_find_default_sink(struct coresight_device
> *csdev)
> int depth = 0;
>
> /* look for a default sink if we have not found for this device */
> - if (!csdev->def_sink)
> - csdev->def_sink = coresight_find_sink(csdev, &depth);
> + if (!csdev->def_sink) {
> + if (coresight_is_percpu_source(csdev))
> + c
Re: [PATCH v4 10/19] coresight: etm-perf: Allow an event to use different sinks
On Thu, 25 Feb 2021 at 19:36, Suzuki K Poulose wrote:
>
> When a sink is not specified by the user, the etm perf driver
> finds a suitable sink automatically, based on the first ETM
> where this event could be scheduled. Then we allocate the
> sink buffer based on the selected sink. This is fine for a
> CPU bound event as the "sink" is always guaranteed to be
> reachable from the ETM (as this is the only ETM where the
> event is going to be scheduled). However, if we have a thread
> bound event, the event could be scheduled on any of the ETMs
> on the system. In this case, currently we automatically select
> a sink and exclude any ETMs that cannot reach the selected
> sink. This is problematic especially for 1x1 configurations.
> We end up in tracing the event only on the "first" ETM,
> as the default sink is local to the first ETM and unreachable
> from the rest. However, we could allow the other ETMs to
> trace if they all have a sink that is compatible with the
> "selected" sink and can use the sink buffer. This can be
> easily done by verifying that they are all driven by the
> same driver and matches the same subtype. Please note
> that at anytime there can be only one ETM tracing the event.
>
> Adding support for different types of sinks for a single
> event is complex and is not something that we expect
> on a sane configuration.
>
> Cc: Mathieu Poirier
> Cc: Mike Leach
> Tested-by: Linu Cherian
> Signed-off-by: Suzuki K Poulose
> ---
> Changes:
> - Rename sinks_match => sinks_compatible
> - Tighten the check by matching the sink subtype
> - Use user_sink instead of "sink_forced" and clean up the code (Mathieu)
> - More comments, better commit description
> ---
> .../hwtracing/coresight/coresight-etm-perf.c | 60 ---
> 1 file changed, 52 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
> b/drivers/hwtracing/coresight/coresight-etm-perf.c
> index 0f603b4094f2..aa0974bd265b 100644
> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> @@ -232,6 +232,25 @@ static void etm_free_aux(void *data)
> schedule_work(&event_data->work);
> }
>
> +/*
> + * Check if two given sinks are compatible with each other,
> + * so that they can use the same sink buffers, when an event
> + * moves around.
> + */
> +static bool sinks_compatible(struct coresight_device *a,
> +struct coresight_device *b)
> +{
> + if (!a || !b)
> + return false;
> + /*
> +* If the sinks are of the same subtype and driven
> +* by the same driver, we can use the same buffer
> +* on these sinks.
> +*/
> + return (a->subtype.sink_subtype == b->subtype.sink_subtype) &&
> + (sink_ops(a) == sink_ops(b));
> +}
> +
> static void *etm_setup_aux(struct perf_event *event, void **pages,
>int nr_pages, bool overwrite)
> {
> @@ -239,6 +258,7 @@ static void *etm_setup_aux(struct perf_event *event, void
> **pages,
> int cpu = event->cpu;
> cpumask_t *mask;
> struct coresight_device *sink = NULL;
> + struct coresight_device *user_sink = NULL, *last_sink = NULL;
> struct etm_event_data *event_data = NULL;
>
> event_data = alloc_event_data(cpu);
> @@ -249,7 +269,7 @@ static void *etm_setup_aux(struct perf_event *event, void
> **pages,
> /* First get the selected sink from user space. */
> if (event->attr.config2) {
> id = (u32)event->attr.config2;
> - sink = coresight_get_sink_by_id(id);
> + sink = user_sink = coresight_get_sink_by_id(id);
> }
>
> mask = &event_data->mask;
> @@ -277,14 +297,33 @@ static void *etm_setup_aux(struct perf_event *event,
> void **pages,
> }
>
> /*
> -* No sink provided - look for a default sink for one of the
> -* devices. At present we only support topology where all CPUs
> -* use the same sink [N:1], so only need to find one sink. The
> -* coresight_build_path later will remove any CPU that does
> not
> -* attach to the sink, or if we have not found a sink.
> +* No sink provided - look for a default sink for all the
> ETMs,
> +* where this event can be scheduled.
> +* We allocate the sink specific buffers only once for this
> +* event. If the ETMs have different default
Re: [PATCH v4 09/19] coresight: etm4x: Move ETM to prohibited region for disable
On Thu, 25 Feb 2021 at 19:36, Suzuki K Poulose wrote:
>
> If the CPU implements Arm v8.4 Trace filter controls (FEAT_TRF),
> move the ETM to trace prohibited region using TRFCR, while disabling.
>
> Cc: Mathieu Poirier
> Cc: Mike Leach
> Cc: Anshuman Khandual
> Signed-off-by: Suzuki K Poulose
> ---
> New patch
> ---
> .../coresight/coresight-etm4x-core.c | 21 +--
> drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++
> 2 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 15016f757828..00297906669c 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -31,6 +31,7 @@
> #include
> #include
>
> +#include
> #include
> #include
> #include
> @@ -654,6 +655,7 @@ static int etm4_enable(struct coresight_device *csdev,
> static void etm4_disable_hw(void *info)
> {
> u32 control;
> + u64 trfcr;
> struct etmv4_drvdata *drvdata = info;
> struct etmv4_config *config = &drvdata->config;
> struct coresight_device *csdev = drvdata->csdev;
> @@ -676,6 +678,16 @@ static void etm4_disable_hw(void *info)
> /* EN, bit[0] Trace unit enable bit */
> control &= ~0x1;
>
> + /*
> +* If the CPU supports v8.4 Trace filter Control,
> +* set the ETM to trace prohibited region.
> +*/
> + if (drvdata->trfc) {
> + trfcr = read_sysreg_s(SYS_TRFCR_EL1);
> + write_sysreg_s(trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE),
> + SYS_TRFCR_EL1);
> + isb();
> + }
> /*
> * Make sure everything completes before disabling, as recommended
> * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
> @@ -683,12 +695,16 @@ static void etm4_disable_hw(void *info)
> */
> dsb(sy);
> isb();
> + /* Trace synchronization barrier, is a nop if not supported */
> + tsb_csync();
> etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
>
> /* wait for TRCSTATR.PMSTABLE to go to '1' */
> if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
> dev_err(etm_dev,
> "timeout while waiting for PM stable Trace Status\n");
> + if (drvdata->trfc)
> + write_sysreg_s(trfcr, SYS_TRFCR_EL1);
>
> /* read the status of the single shot comparators */
> for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> @@ -873,7 +889,7 @@ static bool etm4_init_csdev_access(struct etmv4_drvdata
> *drvdata,
> return false;
> }
>
> -static void cpu_enable_tracing(void)
> +static void cpu_enable_tracing(struct etmv4_drvdata *drvdata)
> {
> u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
> u64 trfcr;
> @@ -881,6 +897,7 @@ static void cpu_enable_tracing(void)
> if (!cpuid_feature_extract_unsigned_field(dfr0,
> ID_AA64DFR0_TRACE_FILT_SHIFT))
> return;
>
> + drvdata->trfc = true;
> /*
> * If the CPU supports v8.4 SelfHosted Tracing, enable
> * tracing at the kernel EL and EL0, forcing to use the
> @@ -1082,7 +1099,7 @@ static void etm4_init_arch_data(void *info)
> /* NUMCNTR, bits[30:28] number of counters available for tracing */
> drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
> etm4_cs_lock(drvdata, csa);
> - cpu_enable_tracing();
> + cpu_enable_tracing(drvdata);
> }
>
> static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h
> b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 0af60571aa23..f6478ef642bf 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -862,6 +862,7 @@ struct etmv4_save_state {
> * @nooverflow:Indicate if overflow prevention is supported.
> * @atbtrig: If the implementation can support ATB triggers
> * @lpoverride:If the implementation can support low-power state
> over.
> + * @trfc: If the implementation supports Arm v8.4 trace filter controls.
> * @config:structure holding configuration parameters.
> * @save_state:State to be preserved across power loss
> * @state_needs_restore: True when there is context to restore after PM exit
> @@ -912,6 +913,7 @@ struct etmv4_drvdata {
> bool
Re: [PATCH v4 05/10] coresight: syscfg: Add API to activate and enable configurations
Hi Suzuki,
On Thu, 4 Mar 2021 at 16:49, Suzuki K Poulose wrote:
>
> On 1/28/21 5:09 PM, Mike Leach wrote:
> > Configurations are first activated, then when any coresight device is
> > enabled, the active configurations are checked and any matching
> > one is enabled.
> >
> > This patch provides the activation / enable API.
> >
> > Signed-off-by: Mike Leach
> > ---
> > .../hwtracing/coresight/coresight-config.h| 2 +
> > .../hwtracing/coresight/coresight-syscfg.c| 127 ++
> > .../hwtracing/coresight/coresight-syscfg.h| 10 +-
> > include/linux/coresight.h | 2 +
> > 4 files changed, 140 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-config.h
> > b/drivers/hwtracing/coresight/coresight-config.h
> > index 98380b496046..26396b70c826 100644
> > --- a/drivers/hwtracing/coresight/coresight-config.h
> > +++ b/drivers/hwtracing/coresight/coresight-config.h
> > @@ -156,6 +156,7 @@ struct cscfg_config_feat_ref {
> >* @presets:Array of preset values.
> >* @id_ea: Extended attribute for perf configid value
> >* @event_ea: Extended attribute for perf event value
> > + * @active_cnt: ref count for activate on this configuration.
> >*/
> > struct cscfg_config_desc {
> > const char *name;
> > @@ -168,6 +169,7 @@ struct cscfg_config_desc {
> > const u64 *presets; /* nr_presets * nr_total_params */
> > struct dev_ext_attribute *id_ea;
> > struct dev_ext_attribute *event_ea;
> > + atomic_t active_cnt;
> > };
> >
> > /**
> > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c
> > b/drivers/hwtracing/coresight/coresight-syscfg.c
> > index a070f135eca3..d79cf5b36758 100644
> > --- a/drivers/hwtracing/coresight/coresight-syscfg.c
> > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c
> > @@ -298,6 +298,7 @@ static int cscfg_load_config(struct cscfg_config_desc
> > *cfg_desc)
> > return err;
> >
> > list_add(&cfg_desc->item, &cscfg_mgr->data.config_desc_list);
> > + atomic_set(&cfg_desc->active_cnt, 0);
> > return 0;
> > }
> >
> > @@ -477,6 +478,131 @@ void cscfg_unregister_csdev(struct coresight_device
> > *csdev)
> > }
> > EXPORT_SYMBOL_GPL(cscfg_unregister_csdev);
> >
> > +void cscfg_csdev_reset_feats(struct coresight_device *csdev)
> > +{
> > + struct cscfg_feature_csdev *feat;
> > +
> > + mutex_lock(&cscfg_csdev_mutex);
> > + if (list_empty(&csdev->feature_csdev_list))
> > + goto unlock_exit;
> > +
> > + list_for_each_entry(feat, &csdev->feature_csdev_list, node)
> > + cscfg_reset_feat(feat);
> > +
> > +unlock_exit:
> > + mutex_unlock(&cscfg_csdev_mutex);
> > +}
> > +EXPORT_SYMBOL_GPL(cscfg_csdev_reset_feats);
> > +
> > +/**
> > + * Mark a config descriptor as active.
> > + * This will be seen when csdev devices are activated in the system.
> > + *
> > + * Selection by hash value - generated from the configuration name when it
> > + * was loaded and added to the cs_etm/configurations file system for
> > selection
> > + * by perf.
> > + *
> > + * @cfg_hash: Hash value of the selected configuration name.
> > + */
> > +int cscfg_activate_config(unsigned long cfg_hash)
> > +{
> > + struct cscfg_config_desc *curr_item, *match_item = 0;
>
> nit: s/0/NULL
>
OK.
> > +
> > + mutex_lock(&cscfg_mutex);
> > +
> > + list_for_each_entry(curr_item, &cscfg_mgr->data.config_desc_list,
> > item) {
> > + if ((unsigned long)curr_item->id_ea->var == cfg_hash) {
> > + match_item = curr_item;
> > + atomic_inc(&cscfg_mgr->data.sys_active_cnt);
> > + break;
> > + }
> > + }
> > + mutex_unlock(&cscfg_mutex);
> > +
> > + if (!match_item)
> > + return -EINVAL;
> > +
> > + dev_dbg(to_device_cscfg(), "Activate config %s.\n", match_item->name);
> > +
> > + /* mark the descriptors as active so enable config will use them */
> > + mutex_lock(&cscfg_csdev_mutex);
> > + atomic_inc(&match_item->active_cnt);
> > + mutex_unlock(&cscfg_csdev_mutex);
>
> Is there a guarantee that this item is active and present in t
Re: [PATCH v4 04/10] coresight: etm-perf: update to handle configuration selection
Hi
On Thu, 4 Mar 2021 at 14:25, Suzuki K Poulose wrote:
>
> On 3/4/21 2:19 PM, Mike Leach wrote:
> > Hi Suzuki,
> >
> > On Thu, 4 Mar 2021 at 12:13, Suzuki K Poulose
> > wrote:
> >>
> >> On 1/28/21 5:09 PM, Mike Leach wrote:
> >>> Loaded coresight configurations are registered in the cs_etm\cs_config sub
> >>> directory. This extends the etm-perf code to handle these registrations,
> >>> and the cs_syscfg driver to perform the registration on load.
> >>>
> >>> Signed-off-by: Mike Leach
> >>> ---
> >>>.../hwtracing/coresight/coresight-config.h| 5 +-
> >>>.../hwtracing/coresight/coresight-etm-perf.c | 164 +++---
> >>>.../hwtracing/coresight/coresight-etm-perf.h | 8 +
> >>>.../hwtracing/coresight/coresight-syscfg.c| 13 +-
> >>>4 files changed, 166 insertions(+), 24 deletions(-)
> >>>
>
>
> >>> +static ssize_t etm_perf_cscfg_event_show(struct device *dev,
> >>> + struct device_attribute *dattr,
> >>> + char *buf)
> >>> +{
> >>> + struct dev_ext_attribute *ea;
> >>> +
> >>> + ea = container_of(dattr, struct dev_ext_attribute, attr);
> >>> + return scnprintf(buf, PAGE_SIZE, "%s\n", (const char *)(ea->var));
> >>> +}
> >>
> >> "configid=0x%lx", (unsigned long)ea->var ?
> >>
> >
> > ea->var _is_ "configid=0x%lx" due to the way perf handles the events
> > sub-dir entries.
> >
>
> This must be combined with the suggestion below.
>
> >>> +
> >>> +static int etm_perf_add_cscfg_event(struct device *dev, struct
> >>> cscfg_config_desc *cs_cfg)
> >>> +{
> >>> + struct dev_ext_attribute *ea;
> >>> + unsigned long hash;
> >>> + int ret;
> >>> + struct device *pmu_dev = etm_pmu.dev;
> >>> +
> >>> + ea = devm_kzalloc(dev, sizeof(*ea), GFP_KERNEL);
> >>> + if (!ea)
> >>> + return -ENOMEM;
> >>> +
> >>> + hash = (unsigned long)cs_cfg->id_ea->var;
> >>> +
> >>> + sysfs_attr_init(&ea->attr.attr);
> >>> + ea->attr.attr.name = devm_kstrdup(dev, cs_cfg->name, GFP_KERNEL);
> >>> + if (!ea->attr.attr.name)
> >>> + return -ENOMEM;
> >>> +
> >>> + /*
> >>> + * attribute value is "configid=".
> >>> + * this will be what perf evaluates when the config name is used
> >>> + * on the command line.
> >>> + */
> >>> + ea->var = devm_kzalloc(dev, CSCFG_EVENT_STR_SIZE, GFP_KERNEL);
> >>> + if (!ea->var)
> >>> + return -ENOMEM;
> >>
> >> Could we drop this string and use the "hash" instead ?
> >>
> >
> > No. My understanding is that we have added an events directory to
> > cs_etm, and add the configurations in there:-
> >
> > cs_etm/events/autofdo
> >
> > Now the contents of autofdo are "configid=0x" - where
> > hash-value is the hash of "autofdo".
> >
> > On the perf command line:-
> >
> > perf record -e cs_etm/autofdo/ .
> >
> > will result in perf parsing autofdo, looking in the events dir for
> > cs_etm, seeing the configid=-string, and parsing that to assign to
> > configid attribute - which we have allocated to config2:63:32 - this
> > will then appear as a value in the perf_event and we can load the
> > configuration when starting up the event on the ETM etc.
>
> Sorry, I was not explicit in my comments. You could drop the string and
> have ea->var = hash. And the _show() could simply do
>
> "configid=0x%lx" , hash
>
> as mentioned above.
>
> That would avoid another string allocation, with the same interface.
>
OK, that makes sense.
Mike
> Suzuki
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Re: [PATCH v4 04/10] coresight: etm-perf: update to handle configuration selection
Hi Suzuki,
On Thu, 4 Mar 2021 at 12:13, Suzuki K Poulose wrote:
>
> On 1/28/21 5:09 PM, Mike Leach wrote:
> > Loaded coresight configurations are registered in the cs_etm\cs_config sub
> > directory. This extends the etm-perf code to handle these registrations,
> > and the cs_syscfg driver to perform the registration on load.
> >
> > Signed-off-by: Mike Leach
> > ---
> > .../hwtracing/coresight/coresight-config.h| 5 +-
> > .../hwtracing/coresight/coresight-etm-perf.c | 164 +++---
> > .../hwtracing/coresight/coresight-etm-perf.h | 8 +
> > .../hwtracing/coresight/coresight-syscfg.c| 13 +-
> > 4 files changed, 166 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-config.h
> > b/drivers/hwtracing/coresight/coresight-config.h
> > index 9d66e0071f38..98380b496046 100644
> > --- a/drivers/hwtracing/coresight/coresight-config.h
> > +++ b/drivers/hwtracing/coresight/coresight-config.h
> > @@ -154,7 +154,8 @@ struct cscfg_config_feat_ref {
> >* @nr_presets: Number of sets of presets supplied by this
> > configuration.
> >* @nr_total_params: Sum of all parameters declared by used features
> >* @presets:Array of preset values.
> > - *
> > + * @id_ea: Extended attribute for perf configid value
> > + * @event_ea:Extended attribute for perf event value
> >*/
> > struct cscfg_config_desc {
> > const char *name;
> > @@ -165,6 +166,8 @@ struct cscfg_config_desc {
> > int nr_presets;
> > int nr_total_params;
> > const u64 *presets; /* nr_presets * nr_total_params */
> > + struct dev_ext_attribute *id_ea;
> > + struct dev_ext_attribute *event_ea;
> > };
> >
> > /**
> > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
> > b/drivers/hwtracing/coresight/coresight-etm-perf.c
> > index a608081bd446..e270bb1e0f7d 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> > @@ -18,8 +18,10 @@
> > #include
> > #include
> >
> > +#include "coresight-config.h"
> > #include "coresight-etm-perf.h"
> > #include "coresight-priv.h"
> > +#include "coresight-syscfg.h"
> >
> > static struct pmu etm_pmu;
> > static bool etm_perf_up;
> > @@ -32,8 +34,13 @@ PMU_FORMAT_ATTR(cycacc,"config:"
> > __stringify(ETM_OPT_CYCACC));
> > PMU_FORMAT_ATTR(contextid, "config:" __stringify(ETM_OPT_CTXTID));
> > PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS));
> > PMU_FORMAT_ATTR(retstack, "config:" __stringify(ETM_OPT_RETSTK));
> > +/* preset - if sink ID is used as a configuration selector */
> > +PMU_FORMAT_ATTR(preset, "config:0-3");
> > /* Sink ID - same for all ETMs */
> > PMU_FORMAT_ATTR(sinkid, "config2:0-31");
> > +/* config ID - set if a system configuration is selected */
> > +PMU_FORMAT_ATTR(configid,"config2:32-63");
> > +
> >
> > static struct attribute *etm_config_formats_attr[] = {
> > &format_attr_cycacc.attr,
> > @@ -41,6 +48,8 @@ static struct attribute *etm_config_formats_attr[] = {
> > &format_attr_timestamp.attr,
> > &format_attr_retstack.attr,
> > &format_attr_sinkid.attr,
> > + &format_attr_preset.attr,
> > + &format_attr_configid.attr,
> > NULL,
> > };
> >
> > @@ -58,9 +67,29 @@ static const struct attribute_group etm_pmu_sinks_group
> > = {
> > .attrs = etm_config_sinks_attr,
> > };
> >
> > +static struct attribute *etm_config_cscfg_attr[] = {
> > + NULL,
> > +};
> > +
> > +static const struct attribute_group etm_pmu_cscfg_group = {
> > + .name = "configurations",
> > + .attrs = etm_config_cscfg_attr,
> > +};
> > +
> > +static struct attribute *etm_config_events_attr[] = {
> > + NULL,
> > +};
> > +
> > +static const struct attribute_group etm_pmu_events_group = {
> > + .name = "events",
> > + .attrs = etm_config_events_attr,
> > +};
> > +
> > static const struct attribute_group *etm_pmu_attr_groups[] = {
> > &etm_pmu_format_group,
> > &etm_pmu_sinks_group,
> > + &etm_pmu_cscfg_group,
> > + &etm_pmu_events_grou
Re: [PATCH v4 01/10] coresight: syscfg: Initial coresight system configuration
Hi Suzuki, On Thu, 4 Mar 2021 at 10:08, Suzuki K Poulose wrote: > > On 1/28/21 5:09 PM, Mike Leach wrote: > > Creates an system management API to allow complex configurations and > > features to be programmed into a CoreSight infrastructure. > > > > A feature is defined as a programming set for a device or class of > > devices. > > > > A configuration is a set of features across the system that are enabled > > for a trace session. > > > > The API will manage system wide configuration, and allow complex > > programmed features to be added to individual device instances, and > > provide for system wide configuration selection on trace capture > > operations. > > > > This patch creates the initial data object and the initial API for > > loading configurations and features. > > > > Signed-off-by: Mike Leach > > --- > > drivers/hwtracing/coresight/Makefile | 2 +- > > .../hwtracing/coresight/coresight-config.h| 167 +++ > > drivers/hwtracing/coresight/coresight-core.c | 12 +- > > .../hwtracing/coresight/coresight-etm-perf.c | 2 +- > > .../hwtracing/coresight/coresight-etm-perf.h | 2 +- > > .../hwtracing/coresight/coresight-syscfg.c| 197 ++ > > .../hwtracing/coresight/coresight-syscfg.h| 54 + > > 7 files changed, 432 insertions(+), 4 deletions(-) > > create mode 100644 drivers/hwtracing/coresight/coresight-config.h > > create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.c > > create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.h > > > > diff --git a/drivers/hwtracing/coresight/Makefile > > b/drivers/hwtracing/coresight/Makefile > > index f20e357758d1..4ce854c434b1 100644 > > --- a/drivers/hwtracing/coresight/Makefile > > +++ b/drivers/hwtracing/coresight/Makefile > > @@ -4,7 +4,7 @@ > > # > > obj-$(CONFIG_CORESIGHT) += coresight.o > > coresight-y := coresight-core.o coresight-etm-perf.o > > coresight-platform.o \ > > - coresight-sysfs.o > > + coresight-sysfs.o coresight-syscfg.o > > obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o > > coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ > > coresight-tmc-etr.o > > diff --git a/drivers/hwtracing/coresight/coresight-config.h > > b/drivers/hwtracing/coresight/coresight-config.h > > new file mode 100644 > > index ..3fedf8ab3cee > > --- /dev/null > > +++ b/drivers/hwtracing/coresight/coresight-config.h > > @@ -0,0 +1,167 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (c) 2020 Linaro Limited, All rights reserved. > > + * Author: Mike Leach > > + */ > > + > > +#ifndef _CORESIGHT_CORESIGHT_CONFIG_H > > +#define _CORESIGHT_CORESIGHT_CONFIG_H > > + > > +#include > > +#include > > + > > +/* CoreSight Configuration Management - component and system wide > > configuration */ > > + > > +/* > > + * Register type flags for register value descriptor: > > + * describe how the value is interpreted, and handled. > > + */ > > +#define CS_CFG_REG_TYPE_STD 0x80/* reg is standard reg */ > > +#define CS_CFG_REG_TYPE_RESOURCE 0x40/* reg is a resource */ > > +#define CS_CFG_REG_TYPE_VAL_PARAM0x08/* reg value uses param */ > > +#define CS_CFG_REG_TYPE_VAL_MASK 0x04/* reg value bit masked */ > > +#define CS_CFG_REG_TYPE_VAL_64BIT0x02/* reg value 64 bit */ > > +#define CS_CFG_REG_TYPE_VAL_SAVE 0x01/* reg value save on disable > > */ > > + > > +/* > > + * flags defining what device class a feature will match to when > > processing a > > + * system configuration - used by config data and devices. > > + */ > > +#define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */ > > +#define CS_CFG_MATCH_CLASS_SRC_ETM4 0x0002 /* match any ETMv4 device */ > > + > > +/* flags defining device instance matching - used in config match desc > > data. */ > > +#define CS_CFG_MATCH_INST_ANY0x8000 /* any instance of > > a class */ > > + > > +/* > > + * Limit number of presets in a configuration > > + * This is related to the number of bits (4) we use to select the preset on > > + * the perf command line. Preset 0 is always none selected. > > + * See PMU_FORMAT_ATTR(preset, "config:0-3") in coresight-etm-perf.c > > + */ > > +#define CS_CFG_CONFIG_PRESET_MAX 15 > > + > > +/**
Re: [PATCH v4 01/10] coresight: syscfg: Initial coresight system configuration
Hi Suzuki, On Wed, 3 Mar 2021 at 10:09, Suzuki K Poulose wrote: > > On 1/28/21 5:09 PM, Mike Leach wrote: > > Creates an system management API to allow complex configurations and > > features to be programmed into a CoreSight infrastructure. > > > > A feature is defined as a programming set for a device or class of > > devices. > > > > A configuration is a set of features across the system that are enabled > > for a trace session. > > > > The API will manage system wide configuration, and allow complex > > programmed features to be added to individual device instances, and > > provide for system wide configuration selection on trace capture > > operations. > > > > This patch creates the initial data object and the initial API for > > loading configurations and features. > > > > Signed-off-by: Mike Leach > > --- > > drivers/hwtracing/coresight/Makefile | 2 +- > > .../hwtracing/coresight/coresight-config.h| 167 +++ > > drivers/hwtracing/coresight/coresight-core.c | 12 +- > > .../hwtracing/coresight/coresight-etm-perf.c | 2 +- > > .../hwtracing/coresight/coresight-etm-perf.h | 2 +- > > .../hwtracing/coresight/coresight-syscfg.c| 197 ++ > > .../hwtracing/coresight/coresight-syscfg.h| 54 + > > 7 files changed, 432 insertions(+), 4 deletions(-) > > create mode 100644 drivers/hwtracing/coresight/coresight-config.h > > create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.c > > create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.h > > > > diff --git a/drivers/hwtracing/coresight/Makefile > > b/drivers/hwtracing/coresight/Makefile > > index f20e357758d1..4ce854c434b1 100644 > > --- a/drivers/hwtracing/coresight/Makefile > > +++ b/drivers/hwtracing/coresight/Makefile > > @@ -4,7 +4,7 @@ > > # > > obj-$(CONFIG_CORESIGHT) += coresight.o > > coresight-y := coresight-core.o coresight-etm-perf.o > > coresight-platform.o \ > > - coresight-sysfs.o > > + coresight-sysfs.o coresight-syscfg.o > > obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o > > coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ > > coresight-tmc-etr.o > > diff --git a/drivers/hwtracing/coresight/coresight-config.h > > b/drivers/hwtracing/coresight/coresight-config.h > > new file mode 100644 > > index ..3fedf8ab3cee > > --- /dev/null > > +++ b/drivers/hwtracing/coresight/coresight-config.h > > @@ -0,0 +1,167 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (c) 2020 Linaro Limited, All rights reserved. > > + * Author: Mike Leach > > + */ > > + > > +#ifndef _CORESIGHT_CORESIGHT_CONFIG_H > > +#define _CORESIGHT_CORESIGHT_CONFIG_H > > + > > +#include > > +#include > > + > > +/* CoreSight Configuration Management - component and system wide > > configuration */ > > + > > +/* > > + * Register type flags for register value descriptor: > > + * describe how the value is interpreted, and handled. > > + */ > > +#define CS_CFG_REG_TYPE_STD 0x80/* reg is standard reg */ > > +#define CS_CFG_REG_TYPE_RESOURCE 0x40/* reg is a resource */ > > +#define CS_CFG_REG_TYPE_VAL_PARAM0x08/* reg value uses param */ > > +#define CS_CFG_REG_TYPE_VAL_MASK 0x04/* reg value bit masked */ > > +#define CS_CFG_REG_TYPE_VAL_64BIT0x02/* reg value 64 bit */ > > +#define CS_CFG_REG_TYPE_VAL_SAVE 0x01/* reg value save on disable > > */ > > + > > +/* > > + * flags defining what device class a feature will match to when > > processing a > > + * system configuration - used by config data and devices. > > + */ > > +#define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */ > > nit: spurious TAB instead of SPACE > > > +#define CS_CFG_MATCH_CLASS_SRC_ETM4 0x0002 /* match any ETMv4 device */ > > + > > +/* flags defining device instance matching - used in config match desc > > data. */ > > +#define CS_CFG_MATCH_INST_ANY0x8000 /* any instance of > > a class */ > > + > > +/* > > + * Limit number of presets in a configuration > > + * This is related to the number of bits (4) we use to select the preset on > > + * the perf command line. Preset 0 is always none selected. > > + * See PMU_FORMAT_ATTR(preset, "config:0-3") in coresight-etm-perf.c > > + */ > > +#define CS_CF
Re: [PATCH 0/6] coresight: Patches for v5.12 (perf tools)
On Tue, 2 Mar 2021 at 16:42, Mathieu Poirier wrote: > > On Tue, Mar 02, 2021 at 01:24:27PM -0300, Arnaldo Carvalho de Melo wrote: > > Em Tue, Mar 02, 2021 at 02:23:14PM +, Mike Leach escreveu: > > > On Tue, 2 Mar 2021 at 12:52, Arnaldo Carvalho de Melo > > > wrote: > > > > Em Wed, Feb 24, 2021 at 09:48:29AM -0700, Mathieu Poirier escreveu: > > > > > I noticed there is a couple of patchsets [1][2] that haven't made it > > > > > to your tree for the coming v5.12 cycle. Do you think that can still > > > > > be done? > > > > > > > I tallied the patches here to make it easier for you to pick up. > > > > > > > Applies cleanly on perf/core (84b7725536d8) > > > > > > > [1]. > > > > > https://lore.kernel.org/lkml/20210202214040.32349-1-mike.le...@linaro.org/ > > > > > [2]. > > > > > https://lore.kernel.org/lkml/20210213113220.292229-1-leo@linaro.org/ > > > > > > These are not applying right now, I've pushed what I have to > > > > tmp.perf/core, please take a look, I'll get back to this after > > > > processing fixes for v5.12 and what is outstanding for v5.13. > > > > > I've tried [1] on both Linux-5.12-rc1 and your tmp.perf/core and it > > > applies cleanly on both. > > > > Can you please try one more time, these are the last csets on this > > branch: > > > > $ git log --oneline acme/tmp.perf/core -10 > > 8e1488a46dcf73b1 (HEAD -> perf/core, five/perf/core, acme/tmp.perf/core, > > acme.korg/tmp.perf/core) perf cs-etm: Detect pid in VMID for kernel running > > at EL2 > > 47f0d94c203751dd perf cs-etm: Add helper cs_etm__get_pid_fmt() > > 30cb76aabfb4deab perf cs-etm: Support PID tracing in config > > 8c559e8d68630d64 perf cs-etm: Fix bitmap for option > > 2bb4ccbd95d7fbf5 tools headers UAPI: Update tools' copy of > > linux/coresight-pmu.h > > 42b2b570b34afb5f perf cs-etm: Update ETM metadata format > > 83bf6fb8b076c72f perf vendor events power9: Remove unsupported metrics > > 34968b9327c83589 perf buildid-cache: Add test for PE executable > > 9bb8b74bdb186bd3 perf docs: Add man pages to see also > > d9fd5a718977702f perf tools: Generate mips syscalls_n64.c syscall table > > $ > > As far as I can tell you have all 6 patches. > Agreed - [1] I was trying is in fact: 42b2b570b34afb5f perf cs-etm: Update ETM metadata format in the above list. Mike > > > > I think it doesn't apply because I applied a series from Mathieu > > touching files affected by those two patchkits. > > > > - Arnaldo > > > > > Let me know if there is anything else I can try. > > > > > > Thanks > > > > > > Mike > > > > > > > > > > > > -- > > > Mike Leach > > > Principal Engineer, ARM Ltd. > > > Manchester Design Centre. UK > > > > -- > > > > - Arnaldo -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
Re: [PATCH 0/6] coresight: Patches for v5.12 (perf tools)
Hi Arnaldo, On Tue, 2 Mar 2021 at 12:52, Arnaldo Carvalho de Melo wrote: > > Em Wed, Feb 24, 2021 at 09:48:29AM -0700, Mathieu Poirier escreveu: > > Good day Arnaldo, > > > > I noticed there is a couple of patchsets [1][2] that haven't made it > > to your tree for the coming v5.12 cycle. Do you think that can still > > be done? > > > > I tallied the patches here to make it easier for you to pick up. > > > > Applies cleanly on perf/core (84b7725536d8) > > > > Thanks, > > Mathieu > > > > [1]. > > https://lore.kernel.org/lkml/20210202214040.32349-1-mike.le...@linaro.org/ > > [2]. > > https://lore.kernel.org/lkml/20210213113220.292229-1-leo@linaro.org/ > > These are not applying right now, I've pushed what I have to > tmp.perf/core, please take a look, I'll get back to this after > processing fixes for v5.12 and what is outstanding for v5.13. > > - Arnaldo I've tried [1] on both Linux-5.12-rc1 and your tmp.perf/core and it applies cleanly on both. Let me know if there is anything else I can try. Thanks Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
Re: [PATCH v4 06/10] coresight: etm-perf: Update to activate selected configuration
Hi Mathieu,
On Thu, 25 Feb 2021 at 21:51, Mathieu Poirier
wrote:
>
> On Thu, Jan 28, 2021 at 05:09:32PM +, Mike Leach wrote:
> > Add calls to activate the selected configuration as perf starts
> > and stops the tracing session.
> >
> > Signed-off-by: Mike Leach
> > ---
> > drivers/hwtracing/coresight/coresight-etm-perf.c | 14 +-
> > drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++
> > 2 files changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
> > b/drivers/hwtracing/coresight/coresight-etm-perf.c
> > index e270bb1e0f7d..5c1aeddabc59 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> > @@ -178,6 +178,10 @@ static void free_event_data(struct work_struct *work)
> > /* Free the sink buffers, if there are any */
> > free_sink_buffer(event_data);
> >
> > + /* clear any configuration we were using */
> > + if (event_data->config_id_hash)
> > + cscfg_deactivate_config(event_data->config_id_hash);
> > +
> > for_each_cpu(cpu, mask) {
> > struct list_head **ppath;
> >
> > @@ -236,7 +240,7 @@ static void etm_free_aux(void *data)
> > static void *etm_setup_aux(struct perf_event *event, void **pages,
> > int nr_pages, bool overwrite)
> > {
> > - u32 id;
> > + u32 id, config_id;
>
> config_id, cfg_hash, id_hash...
>
OK - I'll get the naming consistent.
> > int cpu = event->cpu;
> > cpumask_t *mask;
> > struct coresight_device *sink = NULL;
> > @@ -253,6 +257,14 @@ static void *etm_setup_aux(struct perf_event *event,
> > void **pages,
> > sink = coresight_get_sink_by_id(id);
> > }
> >
> > + /* check if user wants a coresight configuration selected */
> > + config_id = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32);
> > + if (config_id) {
> > + if (cscfg_activate_config(config_id))
> > + goto err;
> > + event_data->config_id_hash = config_id;
> > + }
> > +
> > mask = &event_data->mask;
> >
> > /*
> > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h
> > b/drivers/hwtracing/coresight/coresight-etm-perf.h
> > index 3646a3837a0b..751d768939d8 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm-perf.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h
> > @@ -49,12 +49,14 @@ struct etm_filters {
> > * @work:Handle to free allocated memory outside IRQ context.
> > * @mask:Hold the CPU(s) this event was set for.
> > * @snk_config: The sink configuration.
> > + * @config_id_hash: The id of any coresight config selected.
> > * @path:An array of path, each slot for one CPU.
> > */
> > struct etm_event_data {
> > struct work_struct work;
> > cpumask_t mask;
> > void *snk_config;
> > + u32 config_id_hash;
>
> Please align this with the naming convention you will be using above and
> throughout.
>
> More comments tomorrow.
>
> Thanks,
> Mathieu
>
> > struct list_head * __percpu *path;
> > };
> >
> > --
> > 2.17.1
> >
Thanks
Mike
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Re: [PATCH v4 05/10] coresight: syscfg: Add API to activate and enable configurations
HI Mathieu,
On Thu, 25 Feb 2021 at 21:20, Mathieu Poirier
wrote:
>
> On Thu, Jan 28, 2021 at 05:09:31PM +, Mike Leach wrote:
> > Configurations are first activated, then when any coresight device is
> > enabled, the active configurations are checked and any matching
> > one is enabled.
> >
> > This patch provides the activation / enable API.
> >
> > Signed-off-by: Mike Leach
> > ---
> > .../hwtracing/coresight/coresight-config.h| 2 +
> > .../hwtracing/coresight/coresight-syscfg.c| 127 ++
> > .../hwtracing/coresight/coresight-syscfg.h| 10 +-
> > include/linux/coresight.h | 2 +
> > 4 files changed, 140 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-config.h
> > b/drivers/hwtracing/coresight/coresight-config.h
> > index 98380b496046..26396b70c826 100644
> > --- a/drivers/hwtracing/coresight/coresight-config.h
> > +++ b/drivers/hwtracing/coresight/coresight-config.h
> > @@ -156,6 +156,7 @@ struct cscfg_config_feat_ref {
> > * @presets: Array of preset values.
> > * @id_ea: Extended attribute for perf configid value
> > * @event_ea:Extended attribute for perf event value
> > + * @active_cnt: ref count for activate on this configuration.
> > */
> > struct cscfg_config_desc {
> > const char *name;
> > @@ -168,6 +169,7 @@ struct cscfg_config_desc {
> > const u64 *presets; /* nr_presets * nr_total_params */
> > struct dev_ext_attribute *id_ea;
> > struct dev_ext_attribute *event_ea;
> > + atomic_t active_cnt;
> > };
> >
> > /**
> > diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c
> > b/drivers/hwtracing/coresight/coresight-syscfg.c
> > index a070f135eca3..d79cf5b36758 100644
> > --- a/drivers/hwtracing/coresight/coresight-syscfg.c
> > +++ b/drivers/hwtracing/coresight/coresight-syscfg.c
> > @@ -298,6 +298,7 @@ static int cscfg_load_config(struct cscfg_config_desc
> > *cfg_desc)
> > return err;
> >
> > list_add(&cfg_desc->item, &cscfg_mgr->data.config_desc_list);
> > + atomic_set(&cfg_desc->active_cnt, 0);
> > return 0;
> > }
> >
> > @@ -477,6 +478,131 @@ void cscfg_unregister_csdev(struct coresight_device
> > *csdev)
> > }
> > EXPORT_SYMBOL_GPL(cscfg_unregister_csdev);
> >
> > +void cscfg_csdev_reset_feats(struct coresight_device *csdev)
> > +{
> > + struct cscfg_feature_csdev *feat;
> > +
> > + mutex_lock(&cscfg_csdev_mutex);
> > + if (list_empty(&csdev->feature_csdev_list))
> > + goto unlock_exit;
> > +
> > + list_for_each_entry(feat, &csdev->feature_csdev_list, node)
> > + cscfg_reset_feat(feat);
> > +
> > +unlock_exit:
> > + mutex_unlock(&cscfg_csdev_mutex);
> > +}
> > +EXPORT_SYMBOL_GPL(cscfg_csdev_reset_feats);
> > +
> > +/**
> > + * Mark a config descriptor as active.
> > + * This will be seen when csdev devices are activated in the system.
> > + *
> > + * Selection by hash value - generated from the configuration name when it
> > + * was loaded and added to the cs_etm/configurations file system for
> > selection
> > + * by perf.
> > + *
> > + * @cfg_hash: Hash value of the selected configuration name.
> > + */
> > +int cscfg_activate_config(unsigned long cfg_hash)
> > +{
> > + struct cscfg_config_desc *curr_item, *match_item = 0;
> > +
> > + mutex_lock(&cscfg_mutex);
> > +
> > + list_for_each_entry(curr_item, &cscfg_mgr->data.config_desc_list,
> > item) {
> > + if ((unsigned long)curr_item->id_ea->var == cfg_hash) {
> > + match_item = curr_item;
> > + atomic_inc(&cscfg_mgr->data.sys_active_cnt);
>
> It would be nice to have a comment that mentions why this is needed. I had to
> go look in patch 09 to see that it prevents a feature from being changed when
> any configuration is active. And since patch 09 is the only place where
> @sys_active_cnt is used, please move the declaration and handling of the
> variable there.
>
sys_active_cnt is used later in this patch in
cscfg_csdev_enable_active_config().
In that case it is to give a fast exit to the enable function if
nothing is actually active. The set is written so that the process of
enabling or disabling the config onto an actual device is effiecient
as possible - as this can happen frequently and across many d
Re: [PATCH v4 04/10] coresight: etm-perf: update to handle configuration selection
HI Mathieu.
On Wed, 24 Feb 2021 at 18:33, Mathieu Poirier
wrote:
>
> On Thu, Jan 28, 2021 at 05:09:30PM +, Mike Leach wrote:
> > Loaded coresight configurations are registered in the cs_etm\cs_config sub
> > directory. This extends the etm-perf code to handle these registrations,
> > and the cs_syscfg driver to perform the registration on load.
> >
> > Signed-off-by: Mike Leach
> > ---
> > .../hwtracing/coresight/coresight-config.h| 5 +-
> > .../hwtracing/coresight/coresight-etm-perf.c | 164 +++---
> > .../hwtracing/coresight/coresight-etm-perf.h | 8 +
> > .../hwtracing/coresight/coresight-syscfg.c| 13 +-
> > 4 files changed, 166 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-config.h
> > b/drivers/hwtracing/coresight/coresight-config.h
> > index 9d66e0071f38..98380b496046 100644
> > --- a/drivers/hwtracing/coresight/coresight-config.h
> > +++ b/drivers/hwtracing/coresight/coresight-config.h
> > @@ -154,7 +154,8 @@ struct cscfg_config_feat_ref {
> > * @nr_presets: Number of sets of presets supplied by this
> > configuration.
> > * @nr_total_params: Sum of all parameters declared by used features
> > * @presets: Array of preset values.
> > - *
> > + * @id_ea: Extended attribute for perf configid value
> > + * @event_ea:Extended attribute for perf event value
> > */
> > struct cscfg_config_desc {
> > const char *name;
> > @@ -165,6 +166,8 @@ struct cscfg_config_desc {
> > int nr_presets;
> > int nr_total_params;
> > const u64 *presets; /* nr_presets * nr_total_params */
> > + struct dev_ext_attribute *id_ea;
> > + struct dev_ext_attribute *event_ea;
> > };
> >
> > /**
> > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
> > b/drivers/hwtracing/coresight/coresight-etm-perf.c
> > index a608081bd446..e270bb1e0f7d 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> > @@ -18,8 +18,10 @@
> > #include
> > #include
> >
> > +#include "coresight-config.h"
> > #include "coresight-etm-perf.h"
> > #include "coresight-priv.h"
> > +#include "coresight-syscfg.h"
> >
> > static struct pmu etm_pmu;
> > static bool etm_perf_up;
> > @@ -32,8 +34,13 @@ PMU_FORMAT_ATTR(cycacc,"config:"
> > __stringify(ETM_OPT_CYCACC));
> > PMU_FORMAT_ATTR(contextid, "config:" __stringify(ETM_OPT_CTXTID));
> > PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS));
> > PMU_FORMAT_ATTR(retstack,"config:" __stringify(ETM_OPT_RETSTK));
> > +/* preset - if sink ID is used as a configuration selector */
> > +PMU_FORMAT_ATTR(preset, "config:0-3");
> > /* Sink ID - same for all ETMs */
> > PMU_FORMAT_ATTR(sinkid, "config2:0-31");
> > +/* config ID - set if a system configuration is selected */
> > +PMU_FORMAT_ATTR(configid,"config2:32-63");
> > +
> >
> > static struct attribute *etm_config_formats_attr[] = {
> > &format_attr_cycacc.attr,
> > @@ -41,6 +48,8 @@ static struct attribute *etm_config_formats_attr[] = {
> > &format_attr_timestamp.attr,
> > &format_attr_retstack.attr,
> > &format_attr_sinkid.attr,
> > + &format_attr_preset.attr,
> > + &format_attr_configid.attr,
> > NULL,
> > };
> >
> > @@ -58,9 +67,29 @@ static const struct attribute_group etm_pmu_sinks_group
> > = {
> > .attrs = etm_config_sinks_attr,
> > };
> >
> > +static struct attribute *etm_config_cscfg_attr[] = {
> > + NULL,
> > +};
> > +
> > +static const struct attribute_group etm_pmu_cscfg_group = {
> > + .name = "configurations",
> > + .attrs = etm_config_cscfg_attr,
> > +};
> > +
> > +static struct attribute *etm_config_events_attr[] = {
> > + NULL,
> > +};
> > +
> > +static const struct attribute_group etm_pmu_events_group = {
> > + .name = "events",
> > + .attrs = etm_config_events_attr,
> > +};
> > +
> > static const struct attribute_group *etm_pmu_attr_groups[] = {
> > &etm_pmu_format_group,
> > &etm_pmu_sinks_group,
> > + &etm_pmu_cscfg_group,
> > + &etm_pmu_events_group,
> >
Re: [PATCH v4 02/10] coresight: syscfg: Add registration and feature loading for cs devices
Hi Mathieu,
On Mon, 22 Feb 2021 at 17:38, Mathieu Poirier
wrote:
>
> Hi Mike,
>
> On Thu, Jan 28, 2021 at 05:09:28PM +, Mike Leach wrote:
> > API for individual devices to register with the syscfg management
> > system is added.
> >
> > Devices register with matching information, and any features or
> > configurations that match will be loaded into the device.
> >
> > The feature and configuration loading is extended so that on load these
> > are loaded into any currently registered devices. This allows
> > configuration loading after devices have been registered.
> >
> > Signed-off-by: Mike Leach
> > ---
> > .../hwtracing/coresight/coresight-config.h| 98 +
> > .../hwtracing/coresight/coresight-syscfg.c| 348 ++
> > .../hwtracing/coresight/coresight-syscfg.h| 20 +
> > include/linux/coresight.h | 5 +
> > 4 files changed, 471 insertions(+)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-config.h
> > b/drivers/hwtracing/coresight/coresight-config.h
> > index 3fedf8ab3cee..75ecdecf7013 100644
> > --- a/drivers/hwtracing/coresight/coresight-config.h
> > +++ b/drivers/hwtracing/coresight/coresight-config.h
> > @@ -164,4 +164,102 @@ struct cscfg_config_desc {
> > const u64 *presets; /* nr_presets * nr_total_params */
> > };
> >
> > +/**
> > + * config register instance - part of a loaded feature.
> > + *maps register values to csdev driver
> > structures
> > + *
> > + * @value: value to use when setting feature on device / store for
> > + * readback of volatile values.
> > + * @drv_store: pointer to internal driver element used to set the
> > value
> > + * in hardware.
> > + */
> > +struct cscfg_reg_csdev {
>
> Please rename this cscfg_regval_csdev to highlight the 1:1 mapping with
> cscfg_regval_desc. Or rename cscfg_regval_desc to cscfg_reg_desc. I have no
> opinion on which one it should be, as long as they are consistent. Doing so
> really helps getting over the naming convention so that we can focus on the
> core
> of the feature.
>
Will do.
> > + struct cscfg_regval_desc value;
> > + void *drv_store;
> > +};
> > +
> > +/**
> > + * config parameter instance - part of a loaded feature.
> > + *
> > + * @feat:parent feature
> > + * @reg: register value updated by this parameter.
> > + * @current_value: current value of parameter - may be set by user via
> > + * sysfs, or modified during device operation.
> > + * @val64: true if 64 bit value
> > + */
> > +struct cscfg_parameter_csdev {
> > + struct cscfg_feature_csdev *feat;
> > + struct cscfg_reg_csdev *reg;
> > + u64 current_value;
> > + bool val64;
> > +};
> > +
> > +/**
> > + * Feature instance loaded into a CoreSight device.
> > + *
> > + * When a feature is loaded into a specific device, then this structure
> > holds
> > + * the connections between the register / parameter values used and the
> > + * internal data structures that are written when the feature is enabled.
> > + *
> > + * Since applying a feature modifies internal data structures in the
> > device,
> > + * then we have a reference to the device spinlock to protect access to
> > these
> > + * structures (@csdev_spinlock).
> > + *
> > + * @desc:pointer to the static descriptor for this feature.
> > + * @csdev: parent CoreSight device instance.
> > + * @node:list entry into feature list for this device.
> > + * @csdev_spinlock: device spinlock from csdev instance..
> > + * @nr_params: number of parameters.
> > + * @params: current parameter values on this device
> > + * @nr_regs: number of registers to be programmed.
> > + * @regs:Programming details for the registers
> > + */
> > +struct cscfg_feature_csdev {
> > + const struct cscfg_feature_desc *desc;
> > + struct coresight_device *csdev;
> > + struct list_head node;
> > + spinlock_t *csdev_spinlock;
> > + int nr_params;
> > + struct cscfg_parameter_csdev *params;
> > + int nr_regs;
> > + struct cscfg_reg_csdev *regs;
> > +};
> > +
> > +/**
> > + * Configuration instance when loaded into a CoreSight device.
> > + *
> > + * The instance contains references to loaded features on this device that
Re: [PATCH v4 02/10] coresight: syscfg: Add registration and feature loading for cs devices
Hi Mathieu,
On Fri, 19 Feb 2021 at 18:43, Mathieu Poirier
wrote:
>
> [...]
>
> > +/**
> > + * List entry for Coresight devices that are registered as supporting
> > complex
> > + * config operations.
> > + *
> > + * @csdev: The registered device.
> > + * @match_info: The matching type information.
> > + * @ops: Operations supported by the registered device.
> > + * @item:list entry.
> > + */
> > +struct cscfg_csdev_register {
> > + struct coresight_device *csdev;
> > + struct cscfg_match_desc match_info;
> > + struct cscfg_csdev_feat_ops ops;
> > + struct list_head item;
> > +};
>
> I would call this structure cscfg_registered_csdev and move it to
> coresight-config.h. That way it is consistent with cscfg_config_csdev and
> cscfg_feature_csdev and located all in the same file.
>
I was trying to separate structures that are used to define
configurations and features, with those that are used to manage the
same. Hence, most things in coresight_config.h define configurations,
or their device loaded instance equivalents, and things in
coresight_syscfg.h are management items. I am happy to change the name
but would prefer is stay in coresight_syscfg.h
Thanks
Mike
> I may have to come back to this patch but for now it holds together.
>
> More comments to come on Monday.
>
> Thanks,
> Mathieu
>
> > +
> > /* internal core operations for cscfg */
> > int __init cscfg_init(void);
> > void __exit cscfg_exit(void);
> > @@ -33,6 +49,10 @@ void __exit cscfg_exit(void);
> > /* syscfg manager external API */
> > int cscfg_load_config_sets(struct cscfg_config_desc **cfg_descs,
> > struct cscfg_feature_desc **feat_descs);
> > +int cscfg_register_csdev(struct coresight_device *csdev,
> > + struct cscfg_match_desc *info,
> > + struct cscfg_csdev_feat_ops *ops);
> > +void cscfg_unregister_csdev(struct coresight_device *csdev);
> >
> > /**
> > * System configuration manager device.
> > diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> > index 976ec2697610..d0126ed326a6 100644
> > --- a/include/linux/coresight.h
> > +++ b/include/linux/coresight.h
> > @@ -219,6 +219,8 @@ struct coresight_sysfs_link {
> > * @nr_links: number of sysfs links created to other components from this
> > * device. These will appear in the "connections" group.
> > * @has_conns_grp: Have added a "connections" group for sysfs links.
> > + * @feature_csdev_list: List of complex feature programming added to the
> > device.
> > + * @config_csdev_list: List of system configurations added to the device.
> > */
> > struct coresight_device {
> > struct coresight_platform_data *pdata;
> > @@ -240,6 +242,9 @@ struct coresight_device {
> > int nr_links;
> > bool has_conns_grp;
> > bool ect_enabled; /* true only if associated ect device is enabled */
> > + /* system configuration and feature lists */
> > + struct list_head feature_csdev_list;
> > + struct list_head config_csdev_list;
> > };
> >
> > /*
> > --
> > 2.17.1
> >
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Re: [PATCH v4 01/10] coresight: syscfg: Initial coresight system configuration
Hi Mathieu, On Thu, 18 Feb 2021 at 23:52, Mathieu Poirier wrote: > > On Thu, Jan 28, 2021 at 05:09:27PM +, Mike Leach wrote: > > Creates an system management API to allow complex configurations and > > features to be programmed into a CoreSight infrastructure. > > > > A feature is defined as a programming set for a device or class of > > devices. > > > > A configuration is a set of features across the system that are enabled > > for a trace session. > > > > The API will manage system wide configuration, and allow complex > > programmed features to be added to individual device instances, and > > provide for system wide configuration selection on trace capture > > operations. > > > > This patch creates the initial data object and the initial API for > > loading configurations and features. > > > > Signed-off-by: Mike Leach > > --- > > drivers/hwtracing/coresight/Makefile | 2 +- > > .../hwtracing/coresight/coresight-config.h| 167 +++ > > drivers/hwtracing/coresight/coresight-core.c | 12 +- > > .../hwtracing/coresight/coresight-etm-perf.c | 2 +- > > .../hwtracing/coresight/coresight-etm-perf.h | 2 +- > > .../hwtracing/coresight/coresight-syscfg.c| 197 ++ > > .../hwtracing/coresight/coresight-syscfg.h| 54 + > > 7 files changed, 432 insertions(+), 4 deletions(-) > > create mode 100644 drivers/hwtracing/coresight/coresight-config.h > > create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.c > > create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.h > > > > diff --git a/drivers/hwtracing/coresight/Makefile > > b/drivers/hwtracing/coresight/Makefile > > index f20e357758d1..4ce854c434b1 100644 > > --- a/drivers/hwtracing/coresight/Makefile > > +++ b/drivers/hwtracing/coresight/Makefile > > @@ -4,7 +4,7 @@ > > # > > obj-$(CONFIG_CORESIGHT) += coresight.o > > coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o > > \ > > - coresight-sysfs.o > > + coresight-sysfs.o coresight-syscfg.o > > obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o > > coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ > > coresight-tmc-etr.o > > diff --git a/drivers/hwtracing/coresight/coresight-config.h > > b/drivers/hwtracing/coresight/coresight-config.h > > new file mode 100644 > > index ..3fedf8ab3cee > > --- /dev/null > > +++ b/drivers/hwtracing/coresight/coresight-config.h > > @@ -0,0 +1,167 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (c) 2020 Linaro Limited, All rights reserved. > > + * Author: Mike Leach > > + */ > > + > > +#ifndef _CORESIGHT_CORESIGHT_CONFIG_H > > +#define _CORESIGHT_CORESIGHT_CONFIG_H > > + > > +#include > > +#include > > + > > +/* CoreSight Configuration Management - component and system wide > > configuration */ > > + > > +/* > > + * Register type flags for register value descriptor: > > + * describe how the value is interpreted, and handled. > > + */ > > +#define CS_CFG_REG_TYPE_STD 0x80/* reg is standard reg */ > > +#define CS_CFG_REG_TYPE_RESOURCE 0x40/* reg is a resource */ > > +#define CS_CFG_REG_TYPE_VAL_PARAM0x08/* reg value uses param */ > > +#define CS_CFG_REG_TYPE_VAL_MASK 0x04/* reg value bit masked */ > > +#define CS_CFG_REG_TYPE_VAL_64BIT0x02/* reg value 64 bit */ > > +#define CS_CFG_REG_TYPE_VAL_SAVE 0x01/* reg value save on disable > > */ > > + > > +/* > > + * flags defining what device class a feature will match to when > > processing a > > + * system configuration - used by config data and devices. > > + */ > > +#define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */ > > +#define CS_CFG_MATCH_CLASS_SRC_ETM4 0x0002 /* match any ETMv4 device */ > > + > > +/* flags defining device instance matching - used in config match desc > > data. */ > > +#define CS_CFG_MATCH_INST_ANY0x8000 /* any instance of > > a class */ > > + > > +/* > > + * Limit number of presets in a configuration > > + * This is related to the number of bits (4) we use to select the preset on > > + * the perf command line. Preset 0 is always none selected. > > + * See PMU_FORMAT_ATTR(preset, "config:0-3") in coresight-etm-perf.c > > + */ > > +#define CS_CFG_CONFIG_PRESET_MAX 15 > > + >
Re: [PATCH v4 01/10] coresight: syscfg: Initial coresight system configuration
Hi Mathieu, On Mon, 22 Feb 2021 at 18:50, Mathieu Poirier wrote: > > On Thu, Jan 28, 2021 at 05:09:27PM +, Mike Leach wrote: > > Creates an system management API to allow complex configurations and > > features to be programmed into a CoreSight infrastructure. > > > > A feature is defined as a programming set for a device or class of > > devices. > > > > A configuration is a set of features across the system that are enabled > > for a trace session. > > > > The API will manage system wide configuration, and allow complex > > programmed features to be added to individual device instances, and > > provide for system wide configuration selection on trace capture > > operations. > > > > This patch creates the initial data object and the initial API for > > loading configurations and features. > > > > Signed-off-by: Mike Leach > > --- > > drivers/hwtracing/coresight/Makefile | 2 +- > > .../hwtracing/coresight/coresight-config.h| 167 +++ > > drivers/hwtracing/coresight/coresight-core.c | 12 +- > > .../hwtracing/coresight/coresight-etm-perf.c | 2 +- > > .../hwtracing/coresight/coresight-etm-perf.h | 2 +- > > .../hwtracing/coresight/coresight-syscfg.c| 197 ++ > > .../hwtracing/coresight/coresight-syscfg.h| 54 + > > 7 files changed, 432 insertions(+), 4 deletions(-) > > create mode 100644 drivers/hwtracing/coresight/coresight-config.h > > create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.c > > create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.h > > > > diff --git a/drivers/hwtracing/coresight/Makefile > > b/drivers/hwtracing/coresight/Makefile > > index f20e357758d1..4ce854c434b1 100644 > > --- a/drivers/hwtracing/coresight/Makefile > > +++ b/drivers/hwtracing/coresight/Makefile > > @@ -4,7 +4,7 @@ > > # > > obj-$(CONFIG_CORESIGHT) += coresight.o > > coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o > > \ > > - coresight-sysfs.o > > + coresight-sysfs.o coresight-syscfg.o > > obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o > > coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ > > coresight-tmc-etr.o > > diff --git a/drivers/hwtracing/coresight/coresight-config.h > > b/drivers/hwtracing/coresight/coresight-config.h > > new file mode 100644 > > index ..3fedf8ab3cee > > --- /dev/null > > +++ b/drivers/hwtracing/coresight/coresight-config.h > > @@ -0,0 +1,167 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (c) 2020 Linaro Limited, All rights reserved. > > + * Author: Mike Leach > > + */ > > + > > +#ifndef _CORESIGHT_CORESIGHT_CONFIG_H > > +#define _CORESIGHT_CORESIGHT_CONFIG_H > > + > > +#include > > +#include > > + > > +/* CoreSight Configuration Management - component and system wide > > configuration */ > > + > > +/* > > + * Register type flags for register value descriptor: > > + * describe how the value is interpreted, and handled. > > + */ > > +#define CS_CFG_REG_TYPE_STD 0x80/* reg is standard reg */ > > +#define CS_CFG_REG_TYPE_RESOURCE 0x40/* reg is a resource */ > > +#define CS_CFG_REG_TYPE_VAL_PARAM0x08/* reg value uses param */ > > +#define CS_CFG_REG_TYPE_VAL_MASK 0x04/* reg value bit masked */ > > +#define CS_CFG_REG_TYPE_VAL_64BIT0x02/* reg value 64 bit */ > > +#define CS_CFG_REG_TYPE_VAL_SAVE 0x01/* reg value save on disable > > */ > > + > > +/* > > + * flags defining what device class a feature will match to when > > processing a > > + * system configuration - used by config data and devices. > > + */ > > +#define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */ > > +#define CS_CFG_MATCH_CLASS_SRC_ETM4 0x0002 /* match any ETMv4 device */ > > + > > +/* flags defining device instance matching - used in config match desc > > data. */ > > +#define CS_CFG_MATCH_INST_ANY0x8000 /* any instance of > > a class */ > > + > > +/* > > + * Limit number of presets in a configuration > > + * This is related to the number of bits (4) we use to select the preset on > > + * the perf command line. Preset 0 is always none selected. > > + * See PMU_FORMAT_ATTR(preset, "config:0-3") in coresight-etm-perf.c > > + */ > > +#define CS_CFG_CONFIG_PRESET_MAX 15 > > + >
Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
Hi Suzuki, On Thu, 18 Feb 2021 at 15:14, Suzuki K Poulose wrote: > > On 2/18/21 2:30 PM, Mike Leach wrote: > > HI Suzuki, > > > > On Thu, 18 Feb 2021 at 07:50, Suzuki K Poulose > > wrote: > >> > >> Hi Mike > >> > >> On 2/16/21 9:00 AM, Mike Leach wrote: > >>> Hi Anshuman, > >>> > >>> There have been plenty of detailed comments so I will restrict mine to > >>> a few general issues:- > >>> > >>> 1) Currently there appears to be no sysfs support (I cannot see the > >>> MODE_SYSFS constants running alongside the MODE_PERF ones present in > >>> the other sink drivers). This is present on all other coresight > >>> devices, and must be provided for this device. It is useful for > >>> testing, and there are users out there who will have scripts to use > >>> it. It is not essential it makes it into this set, but should be a > >>> follow up set. > >> > >> This is mentioned in the cover-letter and as you rightly said > >> we could add this in a later series. > >> > > > > Yes - I see that it was mentioned at the end as an open question - so > > I guess this is my answer! > > > >>> > >>> 2) Using FILL mode for TRBE means that the trace will by definition be > >>> lossy. Fill mode will halt collection without cleanly stopping and > >>> flushing the source. This will result in the sink missing the last of > >>> the data from the source as it stops. Even if taking the exception > >>> moves into a prohibited region there is still the possibility the last > >>> trace operations will not be seen. Further it is possible that the > >> > >> Correct. > >> > >>> last few bytes of trace will be an incomplete packet, and indeed the > >>> start of the next buffer could contain incomplete packets too. > >> > >> Yes, this is possible. > >> > >>> > >>> This operation differs from the other sinks which will only halt after > >>> the sources have stopped and the path has been flushed. This ensures > >>> that the latest trace is complete. The weakness with the older sinks > >>> is the lack of interrupt meaning buffers were frequently wrapped so > >>> that only the latest trace is available. > >> > >> This is true, when there was no overflow. i.e, we follow the normal > >> source-stop-flush, sink-stop. > >> > >>> > >>> By using TRBE WRAP mode, with a watermark as described in the TRBE > >>> spec, using the interrupts it is possible to approach lossless trace > >>> in a way that is not possible with earlier ETR/ETB. This is something > >> > >> It may be possible to do lossless trace, but not without double buffering > >> in perf mode. In perf mode, with a single buffer, we have to honor the > >> boundaries set by the aux_buffer head and tail, otherwise we could be > >> corrupting the trace being consumed by the userland. > >> > >> Please remember that the "water mark" is considered as the END of the > >> buffer by TRBE (unlike the SoC-600 ETR). So the LIMIT pointer could be > >> one of : > >> > >> * Tail pointer ( of the handle space, <= End_of_the_Buffer) > >> * Wake up pointer ( when the userspace would like to be woken up ,<= > >> End_of_the_Buffer) > >> > >> So, if we use WRAP mode for perf, the TRBE would overwrite the from > >> the Base, after we hit the LIMIT, where we should have started > >> writing *after* the LIMIT (when LIMIT < End_of_the_Buffer). Moreover > >> restarting from the Base is going to be even more trouble some > >> as it is most likely the data, perf is still collecting. > >> > > > > I agree that the TRBE must write inbetween head and tail / wakeup. > > Howver, there is no reason that I can see why the trbe_base register > > has to remain constant @ the start of the vmapped aux buffer. > > A valid trbe write buffer could be set by: > > trbe_base >= head (rounded up to page boundary) > > trbe_limit <= min(tail, wakeup) (rounded down to page boundary) > > trbe_write is then trbe_base + "watermark" offset. - as suggested in > > the TRBE spec. > > The problem is we are dealing with separate entities. The producer > and the consumer are separate entities playing with a single, > infinite running ring buffer. Had this been a double buffering scheme, >
Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
HI Suzuki, On Thu, 18 Feb 2021 at 07:50, Suzuki K Poulose wrote: > > Hi Mike > > On 2/16/21 9:00 AM, Mike Leach wrote: > > Hi Anshuman, > > > > There have been plenty of detailed comments so I will restrict mine to > > a few general issues:- > > > > 1) Currently there appears to be no sysfs support (I cannot see the > > MODE_SYSFS constants running alongside the MODE_PERF ones present in > > the other sink drivers). This is present on all other coresight > > devices, and must be provided for this device. It is useful for > > testing, and there are users out there who will have scripts to use > > it. It is not essential it makes it into this set, but should be a > > follow up set. > > This is mentioned in the cover-letter and as you rightly said > we could add this in a later series. > Yes - I see that it was mentioned at the end as an open question - so I guess this is my answer! > > > > 2) Using FILL mode for TRBE means that the trace will by definition be > > lossy. Fill mode will halt collection without cleanly stopping and > > flushing the source. This will result in the sink missing the last of > > the data from the source as it stops. Even if taking the exception > > moves into a prohibited region there is still the possibility the last > > trace operations will not be seen. Further it is possible that the > > Correct. > > > last few bytes of trace will be an incomplete packet, and indeed the > > start of the next buffer could contain incomplete packets too. > > Yes, this is possible. > > > > > This operation differs from the other sinks which will only halt after > > the sources have stopped and the path has been flushed. This ensures > > that the latest trace is complete. The weakness with the older sinks > > is the lack of interrupt meaning buffers were frequently wrapped so > > that only the latest trace is available. > > This is true, when there was no overflow. i.e, we follow the normal > source-stop-flush, sink-stop. > > > > > By using TRBE WRAP mode, with a watermark as described in the TRBE > > spec, using the interrupts it is possible to approach lossless trace > > in a way that is not possible with earlier ETR/ETB. This is something > > It may be possible to do lossless trace, but not without double buffering > in perf mode. In perf mode, with a single buffer, we have to honor the > boundaries set by the aux_buffer head and tail, otherwise we could be > corrupting the trace being consumed by the userland. > > Please remember that the "water mark" is considered as the END of the > buffer by TRBE (unlike the SoC-600 ETR). So the LIMIT pointer could be > one of : > >* Tail pointer ( of the handle space, <= End_of_the_Buffer) >* Wake up pointer ( when the userspace would like to be woken up ,<= > End_of_the_Buffer) > > So, if we use WRAP mode for perf, the TRBE would overwrite the from > the Base, after we hit the LIMIT, where we should have started > writing *after* the LIMIT (when LIMIT < End_of_the_Buffer). Moreover > restarting from the Base is going to be even more trouble some > as it is most likely the data, perf is still collecting. > I agree that the TRBE must write inbetween head and tail / wakeup. Howver, there is no reason that I can see why the trbe_base register has to remain constant @ the start of the vmapped aux buffer. A valid trbe write buffer could be set by: trbe_base >= head (rounded up to page boundary) trbe_limit <= min(tail, wakeup) (rounded down to page boundary) trbe_write is then trbe_base + "watermark" offset. - as suggested in the TRBE spec. The issue then becomes unravelling the buffer. Given what we know now, and the work on aux buffers, I would suggest that we can easily insert meta data to do this in the front of the buffer, saving any trace overwirtten at the end of the buffer, and setting a new flag in the aux buffer to tell userspace decode to sort it out. Thus the only copy needed is in the region of 8 bytes perhaps. Of course there are potential inefficiencies here in usage of buffer space, and yes we cannot guarantee lossless trace, but FILL mode guarantees lossy trace and a truncated buffer for every time it wraps (by definition, if FILL mode wraps then you cannot be sure that you have all the possible trace so it has to be marked as truncated in the same way we mark wrapped ETR buffers as truncated whenever they are wrapped). > > that has been requested by partners since trace became available in > > linux systems. (There is still a possibility of loss due to filling > > the buffer completely and overflowing the watermark, but that can be > > flagged). > > > > While FIL
Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
Hi Anshuman, On Tue, 16 Feb 2021 at 09:44, Anshuman Khandual wrote: > > Hello Mike, > > On 2/16/21 2:30 PM, Mike Leach wrote: > > Hi Anshuman, > > > > There have been plenty of detailed comments so I will restrict mine to > > a few general issues:- > > > > 1) Currently there appears to be no sysfs support (I cannot see the > > MODE_SYSFS constants running alongside the MODE_PERF ones present in > > the other sink drivers). This is present on all other coresight > > devices, and must be provided for this device. It is useful for > > testing, and there are users out there who will have scripts to use > > it. It is not essential it makes it into this set, but should be a > > follow up set. > > Sure, will try and add it in a follow up series. > > > > > 2) Using FILL mode for TRBE means that the trace will by definition be > > lossy. Fill mode will halt collection without cleanly stopping and > > flushing the source. This will result in the sink missing the last of > > the data from the source as it stops. Even if taking the exception > > moves into a prohibited region there is still the possibility the last > > trace operations will not be seen. Further it is possible that the > > last few bytes of trace will be an incomplete packet, and indeed the > > start of the next buffer could contain incomplete packets too. > > Just wondering why TRBE and ETE would not sync with each other in order > for the ETE to possibly resend all the lost trace data, when the TRBE > runs out of buffer and wrappers around ? The ETE and TRBE are separate devices - there is no feedback between them. The ETE can also send to external sinks. Given the rate of trace generation, buffering enough trace in the ETE to resend is not realistic, and would be very complicated in terms of hardware. Therefore the solution is to stop the source (disable ETE or prohibit using TFR), flush (TSB CSYNC), then stop collection. A TSB CSYNC without stopping the ETE, or after TRBE has stopped collection will have no effect in terms of getting cleanly stopped trace into the buffer. > Is this ETE/TRBE behavior same > for all implementations in the FILL mode ? Just wondering. > Yes - there is nothing in either spec that would suggest otherwise. > > > > This operation differs from the other sinks which will only halt after > > the sources have stopped and the path has been flushed. This ensures > > that the latest trace is complete. The weakness with the older sinks > > is the lack of interrupt meaning buffers were frequently wrapped so > > that only the latest trace is available. > > Right. > > > > > By using TRBE WRAP mode, with a watermark as described in the TRBE > > spec, using the interrupts it is possible to approach lossless trace > > in a way that is not possible with earlier ETR/ETB. This is somethin > Using TRBTRG_EL1 as the above mentioned watermark ? > Using TRBTRG_EL1 precludes using the ETE Event triggers for activating and marking trace. It is preferable to use the write pointer offset from the initial base to allow a portion of the buffer to be filled after wrap. This a little more complex but more flexible in terms of ETE usage. > > that has been requested by partners since trace became available in > > linux systems. (There is still a possibility of loss due to filling > > the buffer completely and overflowing the watermark, but that can be > > flagged). > > > > While FILL mode trace is a good start, and suitable for some scenarios > > - WRAP mode needs implementing as well. > > I would like to understand this mechanism more. Besides how the perf > interface suppose to choose between FILL and WRAP mode ? via a new > event attribute ? > That is an open question. Event option is one possibility, configfs or compile time options are others. Probably have to look at the performance of wrap mode and decide if it could be used all the time or if FILL still has value. We are in the early days of ETE / TRBE development here. I do not think there is anything wrong with using FILL as a first step. as long as the limitations are well understood. Regards Mike > > > > 3) Padding: To be clear, it is not safe for the decoder to run off the > > end of one buffer, into the padding area and continue decoding, or > > continue through the padding into the next buffer. However I believe > > the buffer start / stop points are demarked by the aux_output_start / > > aux_output_end calls? > > Yes. > > > > > With upcoming perf decode updates this should enable the decoder to > > correctly be started and stopped on the buffer boundaries. The padding > > is there primarily to ensure that
Re: [PATCH V3 14/14] coresight: etm-perf: Add support for trace buffer format
On Wed, 27 Jan 2021 at 08:56, Anshuman Khandual
wrote:
>
> From: Suzuki K Poulose
>
> CoreSight PMU supports aux-buffer for the ETM tracing. The trace
> generated by the ETM (associated with individual CPUs, like Intel PT)
> is captured by a separate IP (CoreSight TMC-ETR/ETF until now).
>
> The TMC-ETR applies formatting of the raw ETM trace data, as it
> can collect traces from multiple ETMs, with the TraceID to indicate
> the source of a given trace packet.
>
> Arm Trace Buffer Extension is new "sink" IP, attached to individual
> CPUs and thus do not provide additional formatting, like TMC-ETR.
>
> Additionally, a system could have both TRBE *and* TMC-ETR for
> the trace collection. e.g, TMC-ETR could be used as a single
> trace buffer to collect data from multiple ETMs to correlate
> the traces from different CPUs. It is possible to have a
> perf session where some events end up collecting the trace
> in TMC-ETR while the others in TRBE. Thus we need a way
> to identify the type of the trace for each AUX record.
>
> Define the trace formats exported by the CoreSight PMU.
> We don't define the flags following the "ETM" as this
> information is available to the user when issuing
> the session. What is missing is the additional
> formatting applied by the "sink" which is decided
> at the runtime and the user may not have a control on.
>
> So we define :
> - CORESIGHT format (indicates the Frame format)
> - RAW format (indicates the format of the source)
>
> The default value is CORESIGHT format for all the records
> (i,e == 0). Add the RAW format for the TRBE sink driver.
>
> Cc: Peter Zijlstra
> Cc: Mike Leach
> Cc: Mathieu Poirier
> Cc: Leo Yan
> Cc: Anshuman Khandual
> Signed-off-by: Suzuki K Poulose
> Signed-off-by: Anshuman Khandual
> ---
> drivers/hwtracing/coresight/coresight-trbe.c | 2 ++
> include/uapi/linux/perf_event.h | 4
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c
> b/drivers/hwtracing/coresight/coresight-trbe.c
> index 1464d8b..7c0e691 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -511,6 +511,7 @@ static unsigned long arm_trbe_update_buffer(struct
> coresight_device *csdev,
> if (cpudata->mode != CS_MODE_PERF)
> return -EINVAL;
>
> + perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW);
> /*
> * If the TRBE was disabled due to lack of space in the AUX buffer or
> a
> * spurious fault, the driver leaves it disabled, truncating the
> buffer.
> @@ -606,6 +607,7 @@ static void trbe_handle_overflow(struct
> perf_output_handle *handle)
> size = offset - PERF_IDX2OFF(handle->head, buf);
> if (buf->snapshot)
> handle->head = offset;
> + perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW);
> perf_aux_output_end(handle, size);
>
> event_data = perf_aux_output_begin(handle, event);
> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
> index 9a5ca45..169e6b3 100644
> --- a/include/uapi/linux/perf_event.h
> +++ b/include/uapi/linux/perf_event.h
> @@ -,6 +,10 @@ enum perf_callchain_context {
> #define PERF_AUX_FLAG_COLLISION0x08/* sample
> collided with another */
> #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace
> format type */
>
> +/* CoreSight PMU AUX buffer formats */
> +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x /* Default for
> backward compatibility */
> +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format
> of the source */
> +
> #define PERF_FLAG_FD_NO_GROUP (1UL << 0)
> #define PERF_FLAG_FD_OUTPUT(1UL << 1)
> #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu
> mode only */
> --
> 2.7.4
>
Reviewed-by: Mike Leach
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Re: [PATCH V3 13/14] perf: aux: Add flags for the buffer format
On Wed, 27 Jan 2021 at 08:56, Anshuman Khandual
wrote:
>
> From: Suzuki K Poulose
>
> Allocate a byte for advertising the PMU specific format type
> of the given AUX record. A PMU could end up providing hardware
> trace data in multiple format in a single session.
>
> e.g, The format of hardware buffer produced by CoreSight ETM
> PMU depends on the type of the "sink" device used for collection
> for an event (Traditional TMC-ETR/Bs with formatting or
> TRBEs without any formatting).
>
> # Boring story of why this is needed. Goto The_End_of_Story for skipping.
>
> CoreSight ETM trace allows instruction level tracing of Arm CPUs.
> The ETM generates the CPU excecution trace and pumps it into CoreSight
> AMBA Trace Bus and is collected by a different CoreSight component
> (traditionally CoreSight TMC-ETR /ETB/ETF), called "sink".
> Important to note that there is no guarantee that every CPU has
> a dedicated sink. Thus multiple ETMs could pump the trace data
> into the same "sink" and thus they apply additional formatting
> of the trace data for the user to decode it properly and attribute
> the trace data to the corresponding ETM.
>
> However, with the introduction of Arm Trace buffer Extensions (TRBE),
> we now have a dedicated per-CPU architected sink for collecting the
> trace. Since the TRBE is always per-CPU, it doesn't apply any formatting
> of the trace. The support for this driver is under review [1].
>
> Now a system could have a per-cpu TRBE and one or more shared
> TMC-ETRs on the system. A user could choose a "specific" sink
> for a perf session (e.g, a TMC-ETR) or the driver could automatically
> select the nearest sink for a given ETM. It is possible that
> some ETMs could end up using TMC-ETR (e.g, if the TRBE is not
> usable on the CPU) while the others using TRBE in a single
> perf session. Thus we now have "formatted" trace collected
> from TMC-ETR and "unformatted" trace collected from TRBE.
> However, we don't get into a situation where a single event
> could end up using TMC-ETR & TRBE. i.e, any AUX buffer is
> guaranteed to be either RAW or FORMATTED, but not a mix
> of both.
>
> As for perf decoding, we need to know the type of the data
> in the individual AUX buffers, so that it can set up the
> "OpenCSD" (library for decoding CoreSight trace) decoder
> instance appropriately. Thus the perf.data file must conatin
> the hints for the tool to decode the data correctly.
>
> Since this is a runtime variable, and perf tool doesn't have
> a control on what sink gets used (in case of automatic sink
> selection), we need this information made available from
> the PMU driver for each AUX record.
>
> # The_End_of_Story
>
> Cc: Peter Ziljstra
> Cc: alexander.shish...@linux.intel.com
> Cc: mi...@redhat.com
> Cc: w...@kernel.org
> Cc: mark.rutl...@arm.com
> Cc: mike.le...@linaro.org
> Cc: a...@kernel.org
> Cc: jo...@redhat.com
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> Signed-off-by: Anshuman Khandual
> ---
> include/uapi/linux/perf_event.h | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
> index b15e344..9a5ca45 100644
> --- a/include/uapi/linux/perf_event.h
> +++ b/include/uapi/linux/perf_event.h
> @@ -1105,10 +1105,11 @@ enum perf_callchain_context {
> /**
> * PERF_RECORD_AUX::flags bits
> */
> -#define PERF_AUX_FLAG_TRUNCATED0x01/* record was
> truncated to fit */
> -#define PERF_AUX_FLAG_OVERWRITE0x02/* snapshot from
> overwrite mode */
> -#define PERF_AUX_FLAG_PARTIAL 0x04/* record contains gaps */
> -#define PERF_AUX_FLAG_COLLISION0x08/* sample collided
> with another */
> +#define PERF_AUX_FLAG_TRUNCATED0x01/* record was
> truncated to fit */
> +#define PERF_AUX_FLAG_OVERWRITE0x02/* snapshot
> from overwrite mode */
> +#define PERF_AUX_FLAG_PARTIAL 0x04/* record contains
> gaps */
> +#define PERF_AUX_FLAG_COLLISION0x08/* sample
> collided with another */
> +#define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace
> format type */
>
> #define PERF_FLAG_FD_NO_GROUP (1UL << 0)
> #define PERF_FLAG_FD_OUTPUT(1UL << 1)
> --
> 2.7.4
>
Reviewed by: Mike Leach
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Re: [PATCH V3 11/14] coresight: sink: Add TRBE driver
Hi Anshuman, There have been plenty of detailed comments so I will restrict mine to a few general issues:- 1) Currently there appears to be no sysfs support (I cannot see the MODE_SYSFS constants running alongside the MODE_PERF ones present in the other sink drivers). This is present on all other coresight devices, and must be provided for this device. It is useful for testing, and there are users out there who will have scripts to use it. It is not essential it makes it into this set, but should be a follow up set. 2) Using FILL mode for TRBE means that the trace will by definition be lossy. Fill mode will halt collection without cleanly stopping and flushing the source. This will result in the sink missing the last of the data from the source as it stops. Even if taking the exception moves into a prohibited region there is still the possibility the last trace operations will not be seen. Further it is possible that the last few bytes of trace will be an incomplete packet, and indeed the start of the next buffer could contain incomplete packets too. This operation differs from the other sinks which will only halt after the sources have stopped and the path has been flushed. This ensures that the latest trace is complete. The weakness with the older sinks is the lack of interrupt meaning buffers were frequently wrapped so that only the latest trace is available. By using TRBE WRAP mode, with a watermark as described in the TRBE spec, using the interrupts it is possible to approach lossless trace in a way that is not possible with earlier ETR/ETB. This is something that has been requested by partners since trace became available in linux systems. (There is still a possibility of loss due to filling the buffer completely and overflowing the watermark, but that can be flagged). While FILL mode trace is a good start, and suitable for some scenarios - WRAP mode needs implementing as well. 3) Padding: To be clear, it is not safe for the decoder to run off the end of one buffer, into the padding area and continue decoding, or continue through the padding into the next buffer. However I believe the buffer start / stop points are demarked by the aux_output_start / aux_output_end calls? With upcoming perf decode updates this should enable the decoder to correctly be started and stopped on the buffer boundaries. The padding is there primarily to ensure that the decoder does not synchronize with the data stream until a genuine sync point is found. 4) TRBE needs to be a loadable module like the rest of coresight. Regards Mike On Mon, 15 Feb 2021 at 09:46, Anshuman Khandual wrote: > > > On 2/13/21 1:56 AM, Mathieu Poirier wrote: > > On Wed, Jan 27, 2021 at 02:25:35PM +0530, Anshuman Khandual wrote: > >> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is > >> accessible via the system registers. The TRBE supports different addressing > >> modes including CPU virtual address and buffer modes including the circular > >> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1), > >> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the > >> access to the trace buffer could be prohibited by a higher exception level > >> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU > >> private interrupt (PPI) on address translation errors and when the buffer > >> is full. Overall implementation here is inspired from the Arm SPE driver. > >> > >> Cc: Mathieu Poirier > >> Cc: Mike Leach > >> Cc: Suzuki K Poulose > >> Signed-off-by: Anshuman Khandual > >> --- > >> Changes in V3: > >> > >> - Added new DT bindings document TRBE.yaml > >> - Changed TRBLIMITR_TRIG_MODE_SHIFT from 2 to 3 > >> - Dropped isb() from trbe_reset_local() > >> - Dropped gap between (void *) and buf->trbe_base > >> - Changed 'int' to 'unsigned int' in is_trbe_available() > >> - Dropped unused function set_trbe_running(), set_trbe_virtual_mode(), > >> set_trbe_enabled() and set_trbe_limit_pointer() > >> - Changed get_trbe_flag_update(), is_trbe_programmable() and > >> get_trbe_address_align() to accept TRBIDR value > >> - Changed is_trbe_running(), is_trbe_abort(), is_trbe_wrap(), > >> is_trbe_trg(), > >> is_trbe_irq(), get_trbe_bsc() and get_trbe_ec() to accept TRBSR value > >> - Dropped snapshot mode condition in arm_trbe_alloc_buffer() > >> - Exit arm_trbe_init() when arm64_kernel_unmapped_at_el0() is enabled > >> - Compute trbe_limit before trbe_write to get the updated handle > >> - Added trbe_stop_and_truncate_event() > >> - Dropped trbe_handle_fatal() > >> > >> Documentation/trace/coresight
Re: [PATCH V3 09/14] arm64: Add TRBE definitions
On Thu, 28 Jan 2021 at 17:18, Catalin Marinas wrote: > > On Wed, Jan 27, 2021 at 02:25:33PM +0530, Anshuman Khandual wrote: > > This adds TRBE related registers and corresponding feature macros. > > > > Cc: Mathieu Poirier > > Cc: Mike Leach > > Cc: Suzuki K Poulose > > Signed-off-by: Anshuman Khandual > > Acked-by: Catalin Marinas Reviewed-by: Mike Leach -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
Re: [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks
Hi Mathieu, On Mon, 15 Feb 2021 at 16:56, Mathieu Poirier wrote: > > On Mon, Feb 15, 2021 at 04:27:26PM +, Mike Leach wrote: > > HI Anshuman > > > > On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual > > wrote: > > > > > > Add support for dedicated sinks that are bound to individual CPUs. (e.g, > > > TRBE). To allow quicker access to the sink for a given CPU bound source, > > > keep a percpu array of the sink devices. Also, add support for building > > > a path to the CPU local sink from the ETM. > > > > > > > Really need to tighten up the terminology here - I think what you mean > > is a PE architecturally defined sink - i.e. one that can be determined > > by reading the feature registers on the PE, rather than an ETR which > > cannot. > > However, the Coresight Base System Architecture specification does > > recommend a per cpu design using an ETR per CPU - now I assume that > > this case is not catered for in this patch? > > > > > This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM. > > > This new sink type is exclusively available and can only work with percpu > > > source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC. > > > > > > > CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC - this does not exist. > > > > > > > > This defines a percpu structure that accommodates a single > > > coresight_device > > > which can be used to store an initialized instance from a sink driver. As > > > these sinks are exclusively linked and dependent on corresponding percpu > > > sources devices, they should also be the default sink device during a perf > > > session. > > > > > > Outwards device connections are scanned while establishing paths between a > > > source and a sink device. But such connections are not present for certain > > > percpu source and sink devices which are exclusively linked and dependent. > > > Build the path directly and skip connection scanning for such devices. > > > > > > Cc: Mathieu Poirier > > > Cc: Mike Leach > > > Cc: Suzuki K Poulose > > > Signed-off-by: Anshuman Khandual > > > --- > > > Changes in V3: > > > > > > - Updated coresight_find_default_sink() > > > > > > drivers/hwtracing/coresight/coresight-core.c | 16 ++-- > > > include/linux/coresight.h| 12 > > > 2 files changed, 26 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/hwtracing/coresight/coresight-core.c > > > b/drivers/hwtracing/coresight/coresight-core.c > > > index 0062c89..4795e28 100644 > > > --- a/drivers/hwtracing/coresight/coresight-core.c > > > +++ b/drivers/hwtracing/coresight/coresight-core.c > > > @@ -23,6 +23,7 @@ > > > #include "coresight-priv.h" > > > > > > static DEFINE_MUTEX(coresight_mutex); > > > +DEFINE_PER_CPU(struct coresight_device *, csdev_sink); > > > > > > > If you do indeed mean the architecturally defined sinks then this > > could be 'csdev_pe_arch_sink' - or something similar to indicate the > > reliance on the PE architecture, unless per-cpu ETR topologies are > > also handled here. > > I would like to treat systems with one ETR per CPU the same way we do for > TRBEs. > That way we have two distinct way of working, i.e topologies where the sink is > shared and 1:1 topologies. As such moving forward with "csdev_pe_arch_sink" > could become misleading when 1:1 ETR topologies are supported. > > Mathieu > I believe that In terms of connecting source -> sink for 1:1 ETM:ETR, then the existing code will already work via the normal build path and ports declarations. Suzukis changes in coresight-etm-perf to allow multiple sinks of the same type to be active for ETE:TRBE will also work for ETx:ETR. (at least in terms of path building - there may still be other issues that come into play about buffers etc). The TRBE .dts doesn''t have any ports and is as such outside this framework. This patch appears to be making it detectable when connecting source -> sink where we have ETE:TRBE on a given CPU - as in the subsequent patches, the TRBE driver registers in the per cpu sink array. So these changes are not really related to 1:1 specifically, but the detectability of PE architected sinks. There is a need for the per cpu array for TRBE as there is no other way of finding them - but not for ETR - which should work just fine without changes I think. Regards Mike > > > > > /** &
Re: [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks
HI Anshuman
On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
wrote:
>
> Add support for dedicated sinks that are bound to individual CPUs. (e.g,
> TRBE). To allow quicker access to the sink for a given CPU bound source,
> keep a percpu array of the sink devices. Also, add support for building
> a path to the CPU local sink from the ETM.
>
Really need to tighten up the terminology here - I think what you mean
is a PE architecturally defined sink - i.e. one that can be determined
by reading the feature registers on the PE, rather than an ETR which
cannot.
However, the Coresight Base System Architecture specification does
recommend a per cpu design using an ETR per CPU - now I assume that
this case is not catered for in this patch?
> This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM.
> This new sink type is exclusively available and can only work with percpu
> source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC.
>
CORESIGHT_DEV_SUBTYPE_SOURCE_PERCPU_PROC - this does not exist.
>
> This defines a percpu structure that accommodates a single coresight_device
> which can be used to store an initialized instance from a sink driver. As
> these sinks are exclusively linked and dependent on corresponding percpu
> sources devices, they should also be the default sink device during a perf
> session.
>
> Outwards device connections are scanned while establishing paths between a
> source and a sink device. But such connections are not present for certain
> percpu source and sink devices which are exclusively linked and dependent.
> Build the path directly and skip connection scanning for such devices.
>
> Cc: Mathieu Poirier
> Cc: Mike Leach
> Cc: Suzuki K Poulose
> Signed-off-by: Anshuman Khandual
> ---
> Changes in V3:
>
> - Updated coresight_find_default_sink()
>
> drivers/hwtracing/coresight/coresight-core.c | 16 ++--
> include/linux/coresight.h| 12
> 2 files changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-core.c
> b/drivers/hwtracing/coresight/coresight-core.c
> index 0062c89..4795e28 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -23,6 +23,7 @@
> #include "coresight-priv.h"
>
> static DEFINE_MUTEX(coresight_mutex);
> +DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
>
If you do indeed mean the architecturally defined sinks then this
could be 'csdev_pe_arch_sink' - or something similar to indicate the
reliance on the PE architecture, unless per-cpu ETR topologies are
also handled here.
> /**
> * struct coresight_node - elements of a path, from source to sink
> @@ -784,6 +785,13 @@ static int _coresight_build_path(struct coresight_device
> *csdev,
> if (csdev == sink)
> goto out;
>
> + if (coresight_is_percpu_source(csdev) &&
> coresight_is_percpu_sink(sink) &&
> + sink == per_cpu(csdev_sink, source_ops(csdev)->cpu_id(csdev))) {
> + _coresight_build_path(sink, sink, path);
> + found = true;
> + goto out;
> + }
> +
> /* Not a sink - recursively explore each port found on this element */
> for (i = 0; i < csdev->pdata->nr_outport; i++) {
> struct coresight_device *child_dev;
> @@ -999,8 +1007,12 @@ coresight_find_default_sink(struct coresight_device
> *csdev)
> int depth = 0;
>
> /* look for a default sink if we have not found for this device */
> - if (!csdev->def_sink)
> - csdev->def_sink = coresight_find_sink(csdev, &depth);
> + if (!csdev->def_sink) {
> + if (coresight_is_percpu_source(csdev))
> + csdev->def_sink = per_cpu(csdev_sink,
> source_ops(csdev)->cpu_id(csdev));
> + if (!csdev->def_sink)
> + csdev->def_sink = coresight_find_sink(csdev, &depth);
> + }
> return csdev->def_sink;
> }
>
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 976ec26..bc3a5ca 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -50,6 +50,7 @@ enum coresight_dev_subtype_sink {
> CORESIGHT_DEV_SUBTYPE_SINK_PORT,
> CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
> CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
> + CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
If this is needed then could it not be ..._SINK_SYSMEM_PROC - to be
consistent with ..._SOURCE_PROC?
> };
>
> enum coresight_dev_subtype_link {
> @@ -428,6 +429,17 @@ static inline void csdev_acces
Re: [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles
On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
wrote:
>
> From: Suzuki K Poulose
>
> The context associated with an ETM for a given perf event
> includes :
> - handle -> the perf output handle for the AUX buffer.
> - the path for the trace components
> - the buffer config for the sink.
>
> The path and the buffer config are part of the "aux_priv" data
> (etm_event_data) setup by the setup_aux() callback, and made available
> via perf_get_aux(handle).
>
> Now with a sink supporting IRQ, the sink could "end" an output
> handle when the buffer reaches the programmed limit and would try
> to restart a handle. This could fail if there is not enough
> space left the AUX buffer (e.g, the userspace has not consumed
> the data). This leaves the "handle" disconnected from the "event"
> and also the "perf_get_aux()" cleared. This all happens within
> the sink driver, without the etm_perf driver being aware.
> Now when the event is actually stopped, etm_event_stop()
> will need to access the "event_data". But since the handle
> is not valid anymore, we loose the information to stop the
> "trace" path. So, we need a reliable way to access the etm_event_data
> even when the handle may not be active.
>
> This patch replaces the per_cpu handle array with a per_cpu context
> for the ETM, which tracks the "handle" as well as the "etm_event_data".
> The context notes the etm_event_data at etm_event_start() and clears
> it at etm_event_stop(). This makes sure that we don't access a
> stale "etm_event_data" as we are guaranteed that it is not
> freed by free_aux() as long as the event is active and tracing,
> also provides us with access to the critical information
> needed to wind up a session even in the absence of an active
> output_handle.
>
> This is not an issue for the legacy sinks as none of them supports
> an IRQ and is centrally handled by the etm-perf.
>
> Cc: Mathieu Poirier
> Cc: Anshuman Khandual
> Cc: Leo Yan
> Cc: Mike Leach
> Signed-off-by: Suzuki K Poulose
> Signed-off-by: Anshuman Khandual
> ---
> drivers/hwtracing/coresight/coresight-etm-perf.c | 45
> +---
> 1 file changed, 40 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
> b/drivers/hwtracing/coresight/coresight-etm-perf.c
> index eb9e7e9..a3977b0 100644
> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> @@ -24,7 +24,26 @@
> static struct pmu etm_pmu;
> static bool etm_perf_up;
>
> -static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle);
> +/*
> + * An ETM context for a running event includes the perf aux handle
> + * and aux_data. For ETM, the aux_data (etm_event_data), consists of
> + * the trace path and the sink configuration. The event data is accessible
> + * via perf_get_aux(handle). However, a sink could "end" a perf output
> + * handle via the IRQ handler. And if the "sink" encounters a failure
> + * to "begin" another session (e.g due to lack of space in the buffer),
> + * the handle will be cleared. Thus, the event_data may not be accessible
> + * from the handle when we get to the etm_event_stop(), which is required
> + * for stopping the trace path. The event_data is guaranteed to stay alive
> + * until "free_aux()", which cannot happen as long as the event is active on
> + * the ETM. Thus the event_data for the session must be part of the ETM
> context
> + * to make sure we can disable the trace path.
> + */
> +struct etm_ctxt {
> + struct perf_output_handle handle;
> + struct etm_event_data *event_data;
> +};
> +
> +static DEFINE_PER_CPU(struct etm_ctxt, etm_ctxt);
> static DEFINE_PER_CPU(struct coresight_device *, csdev_src);
>
> /* ETMv3.5/PTM's ETMCR is 'config' */
> @@ -332,7 +351,8 @@ static void etm_event_start(struct perf_event *event, int
> flags)
> {
> int cpu = smp_processor_id();
> struct etm_event_data *event_data;
> - struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
> + struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
> + struct perf_output_handle *handle = &ctxt->handle;
> struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
> struct list_head *path;
>
> @@ -374,6 +394,8 @@ static void etm_event_start(struct perf_event *event, int
> flags)
> if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF))
> goto fail_disable_path;
>
> + /* Save the event_data for this
Re: [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access
Reviewed-by: Mike Leach
On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
wrote:
>
> From: Suzuki K Poulose
>
> Add support for handling the system registers for Embedded Trace
> Extensions (ETE). ETE shares most of the registers with ETMv4 except
> for some and also adds some new registers. Re-arrange the ETMv4x list
> to share the common definitions and add the ETE sysreg support.
>
> Cc: Mike Leach
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> Signed-off-by: Anshuman Khandual
> ---
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 32 +
> drivers/hwtracing/coresight/coresight-etm4x.h | 52
> ++
> 2 files changed, 75 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 9edf8be..9e92d2a 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -114,6 +114,38 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool
> _relaxed, bool _64bit)
> }
> }
>
> +u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
> +{
> + u64 res = 0;
> +
> + switch (offset) {
> + ETE_READ_CASES(res)
> + default :
> + WARN_ONCE(1, "ete: trying to read unsupported register @%x\n",
> +offset);
> + }
> +
> + if (!_relaxed)
> + __iormb(res); /* Imitate the !relaxed I/O helpers */
> +
> + return res;
> +}
> +
> +void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
> +{
> + if (!_relaxed)
> + __iowmb(); /* Imitate the !relaxed I/O helpers */
> + if (!_64bit)
> + val &= GENMASK(31, 0);
> +
> + switch (offset) {
> + ETE_WRITE_CASES(val)
> + default :
> + WARN_ONCE(1, "ete: trying to write to unsupported register
> @%x\n",
> + offset);
> + }
> +}
> +
> static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
>struct csdev_access *csa)
> {
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h
> b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 0e86eba..ca24ac5 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -29,6 +29,7 @@
> #define TRCAUXCTLR 0x018
> #define TRCEVENTCTL0R 0x020
> #define TRCEVENTCTL1R 0x024
> +#define TRCRSR 0x028
> #define TRCSTALLCTLR 0x02C
> #define TRCTSCTLR 0x030
> #define TRCSYNCPR 0x034
> @@ -49,6 +50,7 @@
> #define TRCSEQRSTEVR 0x118
> #define TRCSEQSTR 0x11C
> #define TRCEXTINSELR 0x120
> +#define TRCEXTINSELRn(n) (0x120 + (n * 4)) /* n = 0-3 */
> #define TRCCNTRLDVRn(n)(0x140 + (n * 4)) /* n = 0-3
> */
> #define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */
> #define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */
> @@ -160,10 +162,22 @@
> #define CASE_NOP(__unused, x) \
> case (x): /* fall through */
>
> +#define ETE_ONLY_SYSREG_LIST(op, val) \
> + CASE_##op((val), TRCRSR)\
> + CASE_##op((val), TRCEXTINSELRn(1)) \
> + CASE_##op((val), TRCEXTINSELRn(2)) \
> + CASE_##op((val), TRCEXTINSELRn(3))
> +
> /* List of registers accessible via System instructions */
> -#define ETM_SYSREG_LIST(op, val) \
> - CASE_##op((val), TRCPRGCTLR)\
> +#define ETM4x_ONLY_SYSREG_LIST(op, val)\
> CASE_##op((val), TRCPROCSELR) \
> + CASE_##op((val), TRCVDCTLR) \
> + CASE_##op((val), TRCVDSACCTLR) \
> + CASE_##op((val), TRCVDARCCTLR) \
> + CASE_##op((val), TRCOSLAR)
> +
> +#define ETM_COMMON_SYSREG_LIST(op, val)\
> + CASE_##op((val), TRCPRGCTLR)\
> CASE_##op((val), TRCSTATR) \
> CASE_##op((val), TRCCONFIGR)\
> CASE_##op((val), TRCAUXCTLR)\
> @@ -180,9 +194,6 @@
> CASE_##op((val), TRCVIIECTLR) \
> CASE_##op((val), TRCVISSCTLR) \
> CASE_##op((val), TRCVIPCSSCTLR) \
> - CASE_##op((val), TRCVDCTLR) \
> - CASE_##op((val),
Re: [PATCH V3 05/14] coresight: ete: Add support for ETE tracing
Reviewed-by: Mike Leach
On Mon, 15 Feb 2021 at 13:21, Mike Leach wrote:
>
> HI,
>
> On Tue, 2 Feb 2021 at 18:56, Mathieu Poirier
> wrote:
> >
> > On Wed, Jan 27, 2021 at 02:25:29PM +0530, Anshuman Khandual wrote:
> > > From: Suzuki K Poulose
> > >
> > > Add ETE as one of the supported device types we support
> > > with ETM4x driver. The devices are named following the
> > > existing convention as ete.
> > >
> > > ETE mandates that the trace resource status register is programmed
> > > before the tracing is turned on. For the moment simply write to
> > > it indicating TraceActive.
> > >
> > > Cc: Mathieu Poirier
> > > Cc: Mike Leach
> > > Signed-off-by: Suzuki K Poulose
> > > Signed-off-by: Anshuman Khandual
> > > ---
> > > drivers/hwtracing/coresight/Kconfig| 10 ++--
> > > drivers/hwtracing/coresight/coresight-etm4x-core.c | 56
> > > +-
> > > .../hwtracing/coresight/coresight-etm4x-sysfs.c| 19 ++--
> > > drivers/hwtracing/coresight/coresight-etm4x.h | 16 ++-
> > > 4 files changed, 79 insertions(+), 22 deletions(-)
> > >
> > > diff --git a/drivers/hwtracing/coresight/Kconfig
> > > b/drivers/hwtracing/coresight/Kconfig
> > > index 7b44ba2..f154ae7 100644
> > > --- a/drivers/hwtracing/coresight/Kconfig
> > > +++ b/drivers/hwtracing/coresight/Kconfig
> > > @@ -97,15 +97,15 @@ config CORESIGHT_SOURCE_ETM3X
> > > module will be called coresight-etm3x.
> > >
> > > config CORESIGHT_SOURCE_ETM4X
> > > - tristate "CoreSight Embedded Trace Macrocell 4.x driver"
> > > + tristate "CoreSight ETMv4.x / ETE driver"
> > > depends on ARM64
> > > select CORESIGHT_LINKS_AND_SINKS
> > > select PID_IN_CONTEXTIDR
> > > help
> > > - This driver provides support for the ETM4.x tracer module,
> > > tracing the
> > > - instructions that a processor is executing. This is primarily
> > > useful
> > > - for instruction level tracing. Depending on the implemented
> > > version
> > > - data tracing may also be available.
> > > + This driver provides support for the CoreSight Embedded Trace
> > > Macrocell
> > > + version 4.x and the Embedded Trace Extensions (ETE). Both are CPU
> > > tracer
> > > + modules, tracing the instructions that a processor is executing.
> > > This is
> > > + primarily useful for instruction level tracing.
> > >
> > > To compile this driver as a module, choose M here: the
> > > module will be called coresight-etm4x.
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > index 9e92d2a..b40e3c2 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > > @@ -431,6 +431,13 @@ static int etm4_enable_hw(struct etmv4_drvdata
> > > *drvdata)
> > > etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
> > > }
> > >
> > > + /*
> > > + * ETE mandates that the TRCRSR is written to before
> > > + * enabling it.
> > > + */
> > > + if (etm4x_is_ete(drvdata))
> > > + etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
> > > +
> > > /* Enable the trace unit */
> > > etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
> > >
> > > @@ -864,13 +871,24 @@ static bool etm4_init_sysreg_access(struct
> > > etmv4_drvdata *drvdata,
> > >* ETMs implementing sysreg access must implement TRCDEVARCH.
> > >*/
> > > devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
> > > - if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH)
> > > + switch (devarch & ETM_DEVARCH_ID_MASK) {
> > > + case ETM_DEVARCH_ETMv4x_ARCH:
> > > + *csa = (struct csdev_access) {
> > > + .io_mem = false,
> > > + .read = etm4x_sysreg_read,
> > > + .write = etm4x_sysreg_write,
> > > + };
> > > + break;
> > > + case ETM_DEVARCH_ETE_ARCH:
> > > + *csa = (struct csdev_
Re: [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock
Reviewed-by: mike.leach
On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
wrote:
>
> From: Suzuki K Poulose
>
> ETE may not implement the OS lock and instead could rely on
> the PE OS Lock for the trace unit access. This is indicated
> by the TRCOLSR.OSM == 0b100. Add support for handling the
> PE OS lock
>
> Cc: Mathieu Poirier
> Cc: Mike Leach
> Signed-off-by: Suzuki K Poulose
> Signed-off-by: Anshuman Khandual
> ---
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 50
> ++
> drivers/hwtracing/coresight/coresight-etm4x.h | 15 +++
> 2 files changed, 56 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 473ab74..9edf8be 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -114,30 +114,59 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool
> _relaxed, bool _64bit)
> }
> }
>
> -static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct
> csdev_access *csa)
> +static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
> + struct csdev_access *csa)
> {
> - /* Writing 0 to TRCOSLAR unlocks the trace registers */
> - etm4x_relaxed_write32(csa, 0x0, TRCOSLAR);
> - drvdata->os_unlock = true;
> + u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
> +
> + drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
> +}
> +
> +static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
> + struct csdev_access *csa, u32 val)
> +{
> + val = !!val;
> +
> + switch (drvdata->os_lock_model) {
> + case ETM_OSLOCK_PRESENT:
> + etm4x_relaxed_write32(csa, val, TRCOSLAR);
> + break;
> + case ETM_OSLOCK_PE:
> + write_sysreg_s(val, SYS_OSLAR_EL1);
> + break;
> + default:
> + pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
> +smp_processor_id(), drvdata->os_lock_model);
> + fallthrough;
> + case ETM_OSLOCK_NI:
> + return;
> + }
> isb();
> }
>
> +static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
> + struct csdev_access *csa)
> +{
> + WARN_ON(drvdata->cpu != smp_processor_id());
> +
> + /* Writing 0 to OS Lock unlocks the trace unit registers */
> + etm_write_os_lock(drvdata, csa, 0x0);
> + drvdata->os_unlock = true;
> +}
> +
> static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
> {
> if (!WARN_ON(!drvdata->csdev))
> etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
> -
> }
>
> static void etm4_os_lock(struct etmv4_drvdata *drvdata)
> {
> if (WARN_ON(!drvdata->csdev))
> return;
> -
> - /* Writing 0x1 to TRCOSLAR locks the trace registers */
> - etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR);
> + /* Writing 0x1 to OS Lock locks the trace registers */
> + etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
> drvdata->os_unlock = false;
> - isb();
> }
>
> static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
> @@ -906,6 +935,9 @@ static void etm4_init_arch_data(void *info)
> if (!etm4_init_csdev_access(drvdata, csa))
> return;
>
> + /* Detect the support for OS Lock before we actuall use it */
> + etm_detect_os_lock(drvdata, csa);
> +
> /* Make sure all registers are accessible */
> etm4_os_unlock_csa(drvdata, csa);
> etm4_cs_unlock(drvdata, csa);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h
> b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 0af6057..0e86eba 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -506,6 +506,20 @@
> ETM_MODE_EXCL_USER)
>
> /*
> + * TRCOSLSR.OSLM advertises the OS Lock model.
> + * OSLM[2:0] = TRCOSLSR[4:3,0]
> + *
> + * 0b000 - Trace OS Lock is not implemented.
> + * 0b010 - Trace OS Lock is implemented.
> + * 0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS
> Lock.
> + */
> +#define ETM_OSLOCK_NI 0b000
> +#define ETM_OSLOCK_PRESENT 0b010
> +#define ETM_OSLOCK_PE 0b100
> +
>
Re: [PATCH V3 05/14] coresight: ete: Add support for ETE tracing
HI,
On Tue, 2 Feb 2021 at 18:56, Mathieu Poirier wrote:
>
> On Wed, Jan 27, 2021 at 02:25:29PM +0530, Anshuman Khandual wrote:
> > From: Suzuki K Poulose
> >
> > Add ETE as one of the supported device types we support
> > with ETM4x driver. The devices are named following the
> > existing convention as ete.
> >
> > ETE mandates that the trace resource status register is programmed
> > before the tracing is turned on. For the moment simply write to
> > it indicating TraceActive.
> >
> > Cc: Mathieu Poirier
> > Cc: Mike Leach
> > Signed-off-by: Suzuki K Poulose
> > Signed-off-by: Anshuman Khandual
> > ---
> > drivers/hwtracing/coresight/Kconfig| 10 ++--
> > drivers/hwtracing/coresight/coresight-etm4x-core.c | 56
> > +-
> > .../hwtracing/coresight/coresight-etm4x-sysfs.c| 19 ++--
> > drivers/hwtracing/coresight/coresight-etm4x.h | 16 ++-
> > 4 files changed, 79 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/Kconfig
> > b/drivers/hwtracing/coresight/Kconfig
> > index 7b44ba2..f154ae7 100644
> > --- a/drivers/hwtracing/coresight/Kconfig
> > +++ b/drivers/hwtracing/coresight/Kconfig
> > @@ -97,15 +97,15 @@ config CORESIGHT_SOURCE_ETM3X
> > module will be called coresight-etm3x.
> >
> > config CORESIGHT_SOURCE_ETM4X
> > - tristate "CoreSight Embedded Trace Macrocell 4.x driver"
> > + tristate "CoreSight ETMv4.x / ETE driver"
> > depends on ARM64
> > select CORESIGHT_LINKS_AND_SINKS
> > select PID_IN_CONTEXTIDR
> > help
> > - This driver provides support for the ETM4.x tracer module, tracing
> > the
> > - instructions that a processor is executing. This is primarily useful
> > - for instruction level tracing. Depending on the implemented version
> > - data tracing may also be available.
> > + This driver provides support for the CoreSight Embedded Trace
> > Macrocell
> > + version 4.x and the Embedded Trace Extensions (ETE). Both are CPU
> > tracer
> > + modules, tracing the instructions that a processor is executing.
> > This is
> > + primarily useful for instruction level tracing.
> >
> > To compile this driver as a module, choose M here: the
> > module will be called coresight-etm4x.
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > index 9e92d2a..b40e3c2 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > @@ -431,6 +431,13 @@ static int etm4_enable_hw(struct etmv4_drvdata
> > *drvdata)
> > etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
> > }
> >
> > + /*
> > + * ETE mandates that the TRCRSR is written to before
> > + * enabling it.
> > + */
> > + if (etm4x_is_ete(drvdata))
> > + etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
> > +
> > /* Enable the trace unit */
> > etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
> >
> > @@ -864,13 +871,24 @@ static bool etm4_init_sysreg_access(struct
> > etmv4_drvdata *drvdata,
> >* ETMs implementing sysreg access must implement TRCDEVARCH.
> >*/
> > devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
> > - if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH)
> > + switch (devarch & ETM_DEVARCH_ID_MASK) {
> > + case ETM_DEVARCH_ETMv4x_ARCH:
> > + *csa = (struct csdev_access) {
> > + .io_mem = false,
> > + .read = etm4x_sysreg_read,
> > + .write = etm4x_sysreg_write,
> > + };
> > + break;
> > + case ETM_DEVARCH_ETE_ARCH:
> > + *csa = (struct csdev_access) {
> > + .io_mem = false,
> > + .read = ete_sysreg_read,
> > + .write = ete_sysreg_write,
> > + };
> > + break;
> > + default:
> > return false;
> > - *csa = (struct csdev_access) {
> > - .io_mem = false,
> > - .read = etm4x_sysreg_read,
> > - .write = etm4x_sysreg_write,
> > - };
> > + }
> >
> > drvdata->arch = etm_devarch_t
Re: [PATCHv2] coresight: etm4x: Add ETM PID for Cortex-A78
Reviewed-by: Mike Leach
On Sat, 13 Feb 2021 at 11:28, Sai Prakash Ranjan
wrote:
>
> Add ETM PID for Cortex-A78 to the list of supported ETMs.
>
> Signed-off-by: Sai Prakash Ranjan
> ---
>
> Changes in v2:
> * Rebased on top of coresight/next from kernel.org coresight repo.
>
> ---
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 15016f757828..a5b13a7779c3 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -1951,6 +1951,7 @@ static const struct amba_id etm4_ids[] = {
> CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
> CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
> CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
> + CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
> CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
> CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
> CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385
> Cortex-A55 */
>
> base-commit: 06c18e28c402ecfb842df8e22a19a097c35ffca9
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Re: [PATCH] coresight: etm4x: Add ETM PIDs for Cortex-A55 and Cortex-A78
Hi Sai,
This patch does not apply to coresight/next - possibly because the PID
for A55 has been added in an earlier patch ( [b8336ad947e19 ]
coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75).
Regards
Mike
On Fri, 12 Feb 2021 at 17:23, Sai Prakash Ranjan
wrote:
>
> Add ETM PIDs for Cortex-A55 and Cortex-A78 to the list of
> supported ETMs.
>
> Signed-off-by: Sai Prakash Ranjan
> ---
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index b20b6ff17cf6..193233792ab5 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -1713,7 +1713,9 @@ static const struct amba_id etm4_ids[] = {
> CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
> CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
> CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
> + CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
> CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
> + CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
> CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
> CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
> CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385
> Cortex-A55 */
>
> base-commit: 1efbcec2ef8c037f1e801c76e4b9434ee2400be7
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Re: [PATCH v7 28/28] coresight: Add support for v8.4 SelfHosted tracing
Hi Suzuki,
On Fri, 12 Feb 2021 at 15:36, Suzuki K Poulose wrote:
>
> Hi Mike
>
> On 2/12/21 10:34 AM, Mike Leach wrote:
> > Hi Mathieu, Suzuki,
> >
> > Sorry for the really late response on this patch, but I noticed a
> > problem while doing a review of the ETE / TRBE set. (TRBE specs
> > mention TRFCR_ELx, so I was confirming a couple of things).
> >
> > On Sun, 10 Jan 2021 at 22:49, Suzuki K Poulose
> > wrote:
> >>
> >> From: Jonathan Zhou
> >>
> >> v8.4 tracing extensions added support for trace filtering controlled
> >> by TRFCR_ELx. This must be programmed to allow tracing at EL1/EL2 and
> >> EL0. The timestamp used is the virtual time. Also enable CONTEXIDR_EL2
> >> tracing if we are running the kernel at EL2.
> >>
> >> Cc: Catalin Marinas
> >> Cc: Mike Leach
> >> Cc: Will Deacon
> >> Reviewed-by: Mathieu Poirier
> >> Signed-off-by: Jonathan Zhou
> >> [ Move the trace filtering setup etm_init_arch_data() and
> >> clean ups]
> >> Signed-off-by: Suzuki K Poulose
> >> ---
> >> .../coresight/coresight-etm4x-core.c | 25 +++
> >> 1 file changed, 25 insertions(+)
> >>
> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> >> b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> >> index 3d3165dd09d4..18c1a80abab8 100644
> >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> >> @@ -859,6 +859,30 @@ static bool etm4_init_csdev_access(struct
> >> etmv4_drvdata *drvdata,
> >> return false;
> >> }
> >>
> >> +static void cpu_enable_tracing(void)
> >> +{
> >> + u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
> >> + u64 trfcr;
> >> +
> >> + if (!cpuid_feature_extract_unsigned_field(dfr0,
> >> ID_AA64DFR0_TRACE_FILT_SHIFT))
> >> + return;
> >> +
> >> + /*
> >> +* If the CPU supports v8.4 SelfHosted Tracing, enable
> >> +* tracing at the kernel EL and EL0, forcing to use the
> >> +* virtual time as the timestamp.
> >> +*/
> >> + trfcr = (TRFCR_ELx_TS_VIRTUAL |
> >> +TRFCR_ELx_ExTRE |
> >> +TRFCR_ELx_E0TRE);
> >> +
> >> + /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
> >> + if (is_kernel_in_hyp_mode())
> >> + trfcr |= TRFCR_EL2_CX;
> >> +
> >
> > This is wrong - CX bit is present on TRFCR_EL2, not TRFCR_EL1.
>
> Why is this wrong ? We do this only when we are in EL2.
>
Sorry - must have been looking at an older version of the ARMARM when
I looked for EL1 registers that are aliased to EL2. So this does
indeed work!
> > Moreover, TRFCR_EL2 has a separate enables for tracing at EL0 and EL2.
> >
>
> True, that is for EL0&2 translation regimes. i.e, tracing EL0 with
> the kernel running at EL2. But bits TRFCR_EL2.E2TRE == TRFCR_EL1.E1TRE
> If notice, we name the bit TRFCR_ELx_ExTRE. And E0TRE == E0HTRE.
>
> So we do the following :
>
>1) When kernel running at EL2:
> Enable tracing at EL2 and EL0 and context tracking
>2) When kernel running at EL1:
> Enable tracing at EL1 and EL0.
>
>
> > Secondly - is this correct in principal? Should the driver not be
> > reading the access it is permitted by the kernel, rather than giving
> > itself unfettered access to trace where it wants to.
>
> I dont follow the "access permitted by the kernel" here. What are we
> referrring to ?
>
By that I mean that as I suggest below this should be controlled by
what we could call the hypervisor, rather than a driver.
> > Surely TRFCR_ELx levels should be chosen in KConfig and then should
> > be set up in kernel initialisation?
>
> I disagree with yet another Kconfig. This basic requirement for
> enabling the trace collection. It is not something that we can optionally
> use from the architecture. So we should transparently do the right
> thing for making sure that we set up the system for something that
> didn't require any other steps. Or in other words, if we add a Kconfig
> option for TRFCR programming, if someone forgets to select it
> when they upgraded the kernel they are in for a surprisingly long
> debugging to find why the trace doesnt work.
>
> As for the TRFCR programming, we have two choices. etm4x driver
> or generic boot up for th
Re: [PATCH v7 28/28] coresight: Add support for v8.4 SelfHosted tracing
Hi Mathieu, Suzuki,
Sorry for the really late response on this patch, but I noticed a
problem while doing a review of the ETE / TRBE set. (TRBE specs
mention TRFCR_ELx, so I was confirming a couple of things).
On Sun, 10 Jan 2021 at 22:49, Suzuki K Poulose wrote:
>
> From: Jonathan Zhou
>
> v8.4 tracing extensions added support for trace filtering controlled
> by TRFCR_ELx. This must be programmed to allow tracing at EL1/EL2 and
> EL0. The timestamp used is the virtual time. Also enable CONTEXIDR_EL2
> tracing if we are running the kernel at EL2.
>
> Cc: Catalin Marinas
> Cc: Mike Leach
> Cc: Will Deacon
> Reviewed-by: Mathieu Poirier
> Signed-off-by: Jonathan Zhou
> [ Move the trace filtering setup etm_init_arch_data() and
> clean ups]
> Signed-off-by: Suzuki K Poulose
> ---
> .../coresight/coresight-etm4x-core.c | 25 +++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 3d3165dd09d4..18c1a80abab8 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -859,6 +859,30 @@ static bool etm4_init_csdev_access(struct etmv4_drvdata
> *drvdata,
> return false;
> }
>
> +static void cpu_enable_tracing(void)
> +{
> + u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
> + u64 trfcr;
> +
> + if (!cpuid_feature_extract_unsigned_field(dfr0,
> ID_AA64DFR0_TRACE_FILT_SHIFT))
> + return;
> +
> + /*
> +* If the CPU supports v8.4 SelfHosted Tracing, enable
> +* tracing at the kernel EL and EL0, forcing to use the
> +* virtual time as the timestamp.
> +*/
> + trfcr = (TRFCR_ELx_TS_VIRTUAL |
> +TRFCR_ELx_ExTRE |
> +TRFCR_ELx_E0TRE);
> +
> + /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
> + if (is_kernel_in_hyp_mode())
> + trfcr |= TRFCR_EL2_CX;
> +
This is wrong - CX bit is present on TRFCR_EL2, not TRFCR_EL1.
Moreover, TRFCR_EL2 has a separate enables for tracing at EL0 and EL2.
Secondly - is this correct in principal? Should the driver not be
reading the access it is permitted by the kernel, rather than giving
itself unfettered access to trace where it wants to.
Surely TRFCR_ELx levels should be chosen in KConfig and then should
be set up in kernel initialisation?
Regards
Mike
> + write_sysreg_s(trfcr, SYS_TRFCR_EL1);
> +}
> +
> static void etm4_init_arch_data(void *info)
> {
> u32 etmidr0;
> @@ -1044,6 +1068,7 @@ static void etm4_init_arch_data(void *info)
> /* NUMCNTR, bits[30:28] number of counters available for tracing */
> drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
> etm4_cs_lock(drvdata, csa);
> + cpu_enable_tracing();
> }
>
> static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
> --
> 2.24.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Re: [PATCH v3 8/8] Documentation: coresight: Add PID tracing description
I think Suzuki may be on holiday for two weeks. But this does appear to pick up both mine and his suggestions. Suzuki gave his conditional reviewed by in the last patch. Reviewed-by: Mike Leach On Mon, 8 Feb 2021 at 20:50, Mathieu Poirier wrote: > > On Sat, Feb 06, 2021 at 11:08:33PM +0800, Leo Yan wrote: > > After support the PID tracing for the kernel in EL1 or EL2, the usage > > gets more complicated. > > > > This patch gives description for the PMU formats of contextID configs, > > this can help users to understand how to control the knobs for PID > > tracing when the kernel is in different ELs. > > > > Signed-off-by: Leo Yan > > As I indicated I have picked up the kernel patches in this set and there > should > be a new patchset sent to Arnaldo. The only thing left is this patch and I > will > give time to Mike and Suzuki to look at it before I add it to my tree. > > Thanks, > Mathieu > > > --- > > Documentation/trace/coresight/coresight.rst | 32 + > > 1 file changed, 32 insertions(+) > > > > diff --git a/Documentation/trace/coresight/coresight.rst > > b/Documentation/trace/coresight/coresight.rst > > index 0b73acb44efa..169749efd8d1 100644 > > --- a/Documentation/trace/coresight/coresight.rst > > +++ b/Documentation/trace/coresight/coresight.rst > > @@ -512,6 +512,38 @@ The --itrace option controls the type and frequency of > > synthesized events > > Note that only 64-bit programs are currently supported - further work is > > required to support instruction decode of 32-bit Arm programs. > > > > +2.2) Tracing PID > > + > > +The kernel can be built to write the PID value into the PE ContextID > > registers. > > +For a kernel running at EL1, the PID is stored in CONTEXTIDR_EL1. A PE may > > +implement Arm Virtualization Host Extensions (VHE), which the kernel can > > +run at EL2 as a virtualisation host; in this case, the PID value is stored > > in > > +CONTEXTIDR_EL2. > > + > > +perf provides PMU formats that program the ETM to insert these values into > > the > > +trace data; the PMU formats are defined as below: > > + > > + "contextid1": Available on both EL1 kernel and EL2 kernel. When the > > +kernel is running at EL1, "contextid1" enables the PID > > +tracing; when the kernel is running at EL2, this enables > > +tracing the PID of guest applications. > > + > > + "contextid2": Only usable when the kernel is running at EL2. When > > +selected, enables PID tracing on EL2 kernel. > > + > > + "contextid": Will be an alias for the option that enables PID > > +tracing. I.e, > > +contextid == contextid1, on EL1 kernel. > > +contextid == contextid2, on EL2 kernel. > > + > > +perf will always enable PID tracing at the relevant EL, this is > > accomplished by > > +automatically enable the "contextid" config - but for EL2 it is possible > > to make > > +specific adjustments using configs "contextid1" and "contextid2", E.g. if > > a user > > +wants to trace PIDs for both host and guest, the two configs "contextid1" > > and > > +"contextid2" can be set at the same time: > > + > > + perf record -e cs_etm/contextid1,contextid2/u -- vm > > + > > > > Generating coverage files for Feedback Directed Optimization: AutoFDO > > - > > -- > > 2.25.1 > > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
Re: [PATCH v2 2/7] coresight: etm-perf: Support PID tracing for kernel at EL2
On Tue, 2 Feb 2021 at 23:06, Suzuki K Poulose wrote: > > On 2/2/21 4:38 PM, Leo Yan wrote: > > From: Suzuki K Poulose > > > > When the kernel is running at EL2, the PID is stored in CONTEXTIDR_EL2. > > So, tracing CONTEXTIDR_EL1 doesn't give us the pid of the process. > > Thus we should trace the VMID with VMIDOPT set to trace CONTEXTIDR_EL2 > > instead of CONTEXTIDR_EL1. Given that we have an existing config > > option "contextid" and this will be useful for tracing virtual machines > > (when we get to support virtualization). > > > > So instead, this patch extends option CTXTID with an extra bit > > ETM_OPT_CTXTID2 (bit 15), thus on an EL2 kernel, we will have another > > bit available for the perf tool: ETM_OPT_CTXTID is for kernel running in > > EL1, ETM_OPT_CTXTID2 is used when kernel runs in EL2 with VHE enabled. > > > > The tool must be backward compatible for users, i.e, "contextid" today > > traces PID and that should remain the same; for this purpose, the perf > > tool is updated to automatically set corresponding bit for the > > "contextid" config, therefore, the user doesn't have to bother which EL > > the kernel is running. > > > >i.e, perf record -e cs_etm/contextid/u -- > > > > will always do the "pid" tracing, independent of the kernel EL. > > > > The driver parses the format "contextid", which traces CONTEXTIDR_EL1 > > for ETM_OPT_CTXTID (on EL1 kernel) and traces CONTEXTIDR_EL2 for > > ETM_OPT_CTXTID2 (on EL2 kernel). > > > > Besides the enhancement for format "contexid", extra two formats are > > introduced: "contextid1" and "contextid2". This considers to support > > tracing both CONTEXTIDR_EL1 and CONTEXTIDR_EL2 when the kernel is > > running at EL2. Finally, the PMU formats are defined as follow: > > > >"contextid1": Available on both EL1 kernel and EL2 kernel. When the > > kernel is running at EL1, "contextid1" enables the PID > > tracing; when the kernel is running at EL2, this enables > > tracing the PID of guest applications. > > > >"contextid2": Only usable when the kernel is running at EL2. When > > selected, enables PID tracing on EL2 kernel. > > > >"contextid": Will be an alias for the option that enables PID > > tracing. I.e, > > contextid == contextid1, on EL1 kernel. > > contextid == contextid2, on EL2 kernel. > > > > Cc: Mathieu Poirier > > Cc: Al Grant > > Cc: Mike Leach > > Cc: Leo Yan > > Signed-off-by: Suzuki K Poulose > > You may add the following line here : > > [ Added two config formats: contextid1, contextid2 ] > > > Signed-off-by: Leo Yan > > The patch as such looks good to me. > > Suzuki Reviewed-by: Mike Leach -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
Re: [PATCH v2 4/7] perf cs-etm: Support PID tracing in config
On Tue, 2 Feb 2021 at 16:39, Leo Yan wrote:
>
> From: Suzuki K Poulose
>
> If the kernel is running at EL2, the pid of a task is exposed via VMID
> instead of the CONTEXTID. Add support for this in the perf tool.
>
> This patch respects user setting if user has specified any configs
> from "contextid", "contextid1" or "contextid2"; otherwise, it
> dynamically sets config based on PMU format "contextid".
>
> Cc: Mike Leach
> Cc: Mathieu Poirier
> Cc: Al Grant
> Co-developed-by: Leo Yan
> Signed-off-by: Suzuki K Poulose
> Signed-off-by: Leo Yan
> ---
> tools/include/linux/coresight-pmu.h | 3 ++
> tools/perf/arch/arm/util/cs-etm.c | 61 +++--
> 2 files changed, 52 insertions(+), 12 deletions(-)
>
> diff --git a/tools/include/linux/coresight-pmu.h
> b/tools/include/linux/coresight-pmu.h
> index 5dc47cfdcf07..4ac5c081af93 100644
> --- a/tools/include/linux/coresight-pmu.h
> +++ b/tools/include/linux/coresight-pmu.h
> @@ -20,14 +20,17 @@
> */
> #define ETM_OPT_CYCACC 12
> #define ETM_OPT_CTXTID 14
> +#define ETM_OPT_CTXTID215
> #define ETM_OPT_TS 28
> #define ETM_OPT_RETSTK 29
>
> /* ETMv4 CONFIGR programming bits for the ETM OPTs */
> #define ETM4_CFG_BIT_CYCACC4
> #define ETM4_CFG_BIT_CTXTID6
> +#define ETM4_CFG_BIT_VMID 7
> #define ETM4_CFG_BIT_TS11
> #define ETM4_CFG_BIT_RETSTK12
> +#define ETM4_CFG_BIT_VMID_OPT 15
>
> static inline int coresight_get_trace_id(int cpu)
> {
> diff --git a/tools/perf/arch/arm/util/cs-etm.c
> b/tools/perf/arch/arm/util/cs-etm.c
> index c25c878fd06c..fa6f91a7c8a1 100644
> --- a/tools/perf/arch/arm/util/cs-etm.c
> +++ b/tools/perf/arch/arm/util/cs-etm.c
> @@ -67,6 +67,7 @@ static int cs_etm_set_context_id(struct auxtrace_record
> *itr,
> char path[PATH_MAX];
> int err = -EINVAL;
> u32 val;
> + u64 contextid;
>
> ptr = container_of(itr, struct cs_etm_recording, itr);
> cs_etm_pmu = ptr->cs_etm_pmu;
> @@ -86,25 +87,59 @@ static int cs_etm_set_context_id(struct auxtrace_record
> *itr,
> goto out;
> }
>
> + /* User has configured for PID tracing, respects it. */
> + contextid = evsel->core.attr.config &
> + (BIT(ETM_OPT_CTXTID) | BIT(ETM_OPT_CTXTID2));
> +
> /*
> -* TRCIDR2.CIDSIZE, bit [9-5], indicates whether contextID tracing
> -* is supported:
> -* 0b0 Context ID tracing is not supported.
> -* 0b00100 Maximum of 32-bit Context ID size.
> -* All other values are reserved.
> +* If user doesn't configure the contextid format, parse PMU format
> and
> +* enable PID tracing according to the "contextid" format bits:
> +*
> +* If bit ETM_OPT_CTXTID is set, trace CONTEXTIDR_EL1;
> +* If bit ETM_OPT_CTXTID2 is set, trace CONTEXTIDR_EL2.
> */
> - val = BMVAL(val, 5, 9);
> - if (!val || val != 0x4) {
> - err = -EINVAL;
> - goto out;
> + if (!contextid)
> + contextid = perf_pmu__format_bits(&cs_etm_pmu->format,
> + "contextid");
> +
> + if (contextid & BIT(ETM_OPT_CTXTID)) {
> + /*
> +* TRCIDR2.CIDSIZE, bit [9-5], indicates whether contextID
> +* tracing is supported:
> +* 0b0 Context ID tracing is not supported.
> +* 0b00100 Maximum of 32-bit Context ID size.
> +* All other values are reserved.
> +*/
> + val = BMVAL(val, 5, 9);
> + if (!val || val != 0x4) {
> + pr_err("%s: CONTEXTIDR_EL1 isn't supported\n",
> + CORESIGHT_ETM_PMU_NAME);
> + err = -EINVAL;
> + goto out;
> + }
> + }
> +
> + if (contextid & BIT(ETM_OPT_CTXTID2)) {
> + /*
> +* TRCIDR2.VMIDOPT[30:29] != 0 and
> +* TRCIDR2.VMIDSIZE[14:10] == 0b00100 (32bit virtual
> contextid)
> +* We can't support CONTEXTIDR in VMID if the size of the
> +* virtual context id is < 32bit.
> +* Any value of VMIDSIZE >= 4 (i.e, > 32bit) is fine for us.
> +*/
> + if (!BMVAL(val, 29, 30) || BMVAL(val, 10, 14) < 4) {
> +
Re: [PATCH v2 3/7] perf cs-etm: Fix bitmap for option
On Tue, 2 Feb 2021 at 16:39, Leo Yan wrote:
>
> From: Suzuki K Poulose
>
> When set option with macros ETM_OPT_CTXTID and ETM_OPT_TS, it wrongly
> takes these two values (14 and 28 prespectively) as bit masks, but
> actually both are the offset for bits. But this doesn't lead to
> further failure due to the AND logic operation will be always true for
> ETM_OPT_CTXTID / ETM_OPT_TS.
>
> This patch defines new independent macros (rather than using the
> "config" bits) for requesting the "contextid" and "timestamp" for
> cs_etm_set_option().
>
> [leoy: Extract the change as a separate patch for easier review]
> Signed-off-by: Suzuki K Poulose
> Signed-off-by: Leo Yan
> ---
> tools/perf/arch/arm/util/cs-etm.c | 12
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/tools/perf/arch/arm/util/cs-etm.c
> b/tools/perf/arch/arm/util/cs-etm.c
> index bd446aba64f7..c25c878fd06c 100644
> --- a/tools/perf/arch/arm/util/cs-etm.c
> +++ b/tools/perf/arch/arm/util/cs-etm.c
> @@ -156,6 +156,10 @@ static int cs_etm_set_timestamp(struct auxtrace_record
> *itr,
> return err;
> }
>
> +#define ETM_SET_OPT_CTXTID (1 << 0)
> +#define ETM_SET_OPT_TS (1 << 1)
> +#define ETM_SET_OPT_MASK (ETM_SET_OPT_CTXTID | ETM_SET_OPT_TS)
> +
> static int cs_etm_set_option(struct auxtrace_record *itr,
> struct evsel *evsel, u32 option)
> {
> @@ -169,17 +173,17 @@ static int cs_etm_set_option(struct auxtrace_record
> *itr,
> !cpu_map__has(online_cpus, i))
> continue;
>
> - if (option & ETM_OPT_CTXTID) {
> + if (option & ETM_SET_OPT_CTXTID) {
> err = cs_etm_set_context_id(itr, evsel, i);
> if (err)
> goto out;
> }
> - if (option & ETM_OPT_TS) {
> + if (option & ETM_SET_OPT_TS) {
> err = cs_etm_set_timestamp(itr, evsel, i);
> if (err)
> goto out;
> }
> - if (option & ~(ETM_OPT_CTXTID | ETM_OPT_TS))
> + if (option & ~(ETM_SET_OPT_MASK))
> /* Nothing else is currently supported */
> goto out;
> }
> @@ -406,7 +410,7 @@ static int cs_etm_recording_options(struct
> auxtrace_record *itr,
> evsel__set_sample_bit(cs_etm_evsel, CPU);
>
> err = cs_etm_set_option(itr, cs_etm_evsel,
> - ETM_OPT_CTXTID | ETM_OPT_TS);
> + ETM_SET_OPT_CTXTID | ETM_SET_OPT_TS);
> if (err)
> goto out;
> }
> --
> 2.25.1
>
Reivewed-by: Mike Leach
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
Re: [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks
Hi Suzuki,. On Tue, 2 Feb 2021 at 22:42, Suzuki K Poulose wrote: > > On 2/2/21 4:33 PM, Mike Leach wrote: > > Hi, > > > > On Tue, 2 Feb 2021 at 09:42, Suzuki K Poulose > > wrote: > >> > >> On 2/1/21 11:17 PM, Mathieu Poirier wrote: > >>> Hi Anshuman, > >>> > >>> I have started reviewing this set. As it is quite voluminous comments > >>> will > >>> come over serveral days. I will let you know when I am done. > >>> > >>> On Wed, Jan 27, 2021 at 02:25:25PM +0530, Anshuman Khandual wrote: > >>>> From: Suzuki K Poulose > >>>> > >>>> When there are multiple sinks on the system, in the absence > >>>> of a specified sink, it is quite possible that a default sink > >>>> for an ETM could be different from that of another ETM. However > >>>> we do not support having multiple sinks for an event yet. This > >>>> patch allows the event to use the default sinks on the ETMs > >>>> where they are scheduled as long as the sinks are of the same > >>>> type. > >>>> > >>>> e.g, if we have 1x1 topology with per-CPU ETRs, the event can > >>>> use the per-CPU ETR for the session. However, if the sinks > >>>> are of different type, e.g TMC-ETR on one and a custom sink > >>>> on another, the event will only trace on the first detected > >>>> sink. > >>>> > >>> > >>> I found the above changelog very confusing - I read it several times and > >>> still > >>> couldn't get all of it. In the end this patch prevents sinks of > >>> different types > >>> from being used for session, and this is what the text should reflect. > >> > >> Sorry about that. Your inference is correct, but it is only a side effect > >> of the primary motive. How about the following : > >> > >> "When a sink is not specified by the user, the etm perf driver > >> finds a suitable sink automatically based on the first ETM, where > >> this event could be scheduled. Then we allocate the sink buffer based > >> on the selected sink. This is fine for a CPU bound event as the "sink" > >> is always guaranteed to be reachable from the ETM (as this is the only > >> ETM where the event is going to be scheduled). However, if we have a task > >> bound event, the event could be scheduled on any of the ETMs on the > >> system. In this case, currently we automatically select a sink and exclude > >> any ETMs that are not reachable from the selected sink. This is > >> problematic for 1x1 configurations as we end up in tracing the event > >> only on the "first" ETM, as the default sink is local to the first > >> ETM and unreachable from the rest. > >> However, we could allow the other ETMs to trace if they all have a > >> sink that is compatible with the "selected" sink and can use the > >> sink buffer. This can be easily done by verifying that they are > >> all driven by the same driver and matches the same subtype." > >> > > > > > > Not sure that the logic here makes total sense - I can't see _why_ > > multiple sinks need to be of the same type. > > Because we have a single "sink_config" (read, single sink specific > buffer) for an event. i.e, we do the sink_ops->alloc_buffer() only once > and rightly so. This allocates any buffers that is used by a given sink. > e.g, for ETR it allocates an etr_perf_buffer. Now if we wanted the same > event to run on an ETM with TRBE, the TRBE doesn't have any buffer set up to > collect the trace and cant make any sense of etr_perf_buffer. > However, if there is another ETM with a different ETR, the second > ETR can make sense of the sink_config (etr_perf_buffer) and trace the event. > Please remember that this only applies to task bound events where > the event can be scheduled on different ETMs. > I have had a look around the ETR driver and can see the issue - something very sink specific is being bound to the more generic event, which does undermine the abstraction a little bit! The ETR drivers refer to per-thread and cpu-wide - not cpu-bound / task-bound - could do to get consistent terminology here. The cpu-wide version is designed to be called multiple times - but obviously only allocates a single buffer. This implies that for the cpu-wide case, we could tolerate sinks of differing types, as setup_aux will be called once per CPU. Whether we want to is another question. Given we do
Re: [PATCH v2 7/7] Documentation: coresight: Add PID tracing description
Hi, On Thu, 4 Feb 2021 at 11:08, Suzuki K Poulose wrote: > > On 2/4/21 4:09 AM, Leo Yan wrote: > > Hi Mike, > > > > On Wed, Feb 03, 2021 at 05:39:54PM +, Mike Leach wrote: > > > > [...] > > > >>> +2.2) Tracing PID > >>> + > >>> +When the kernel is running at EL2 with Virtualization Host Extensions > >>> (VHE), > >>> +perf records CONTEXTIDR_EL2 in the trace data and can be used as PID when > >>> +decoding; and if the kernel is running at EL1 with nVHE, CONTEXTIDR_EL1 > >>> is > >>> +traced for PID. > >>> + > >> > >> Would this introductory paragraph be better if is explained where the > >> kernel stores the PID for the different levels, then we logically move > >> on to how to trace this in perf. > >> > >> e.g:- > >> > >> "The lernel can be built to write the PID value into the PE ContextID > >> registers. > >> For a kernel running at EL1, the PID is stored in CONTEXTIDR_EL1. > >> A PE may implement ARM Virtualisation Host Extensions (VHE), were the > >> kernel can run at EL2 as a virtualisation host. > >> In this case the PID value is stored in CONTEXTIDR_EL2. > >> perf provides PMU options which program the ETM to insert these values > >> into the trace data." > > > > Will in next spin; thanks a lot for writing up! > > > >>> +To support tracing PID for the kernel runs at different exception levels, > >>> +the PMU formats are defined as follow: > >>> + > >>> + "contextid1": Available on both EL1 kernel and EL2 kernel. When the > >>> +kernel is running at EL1, "contextid1" enables the PID > >>> +tracing; when the kernel is running at EL2, this enables > >>> +tracing the PID of guest applications. > >>> + > >>> + "contextid2": Only usable when the kernel is running at EL2. When > >>> +selected, enables PID tracing on EL2 kernel. > >>> + > >>> + "contextid": Will be an alias for the option that enables PID > >>> +tracing. I.e, > >>> +contextid == contextid1, on EL1 kernel. > >>> +contextid == contextid2, on EL2 kernel. > >>> + > >>> +The perf tool automatically sets corresponding bit for the "contextid" > >>> config, > >>> +therefore, the user doesn't have to bother which EL the kernel is > >>> running. > >>> + > >>> + i.e, perf record -e cs_etm/contextid/u -- uname > >>> +or perf record -e cs_etm//u -- uname > >>> + > >>> +will always do the "PID" tracing, independent of the kernel EL. > >>> + > >> > >> This is telling me that both cs_etm// and cs_etm/contextid/ have the > >> same effect - trace PID. Is this correct? > > > > Just to make this clear, this is not a side effect of the patch. Which is fine - but the documentation should accurately reflect what is happening on the system. This is a new paragraph about the PID tracing or otherwise, Even if some of the effects pre-date this patch, they have to be accurately communicated. I am also reading the new paragraph in the context of the rest of the coresight.rst document - which is a user level document explaining the basic operation of the coresight system and tools. This document mentions no other perf command line parameters relevant to coresight other than the @sink option.It actually calls out to the OpenCSD docs to provide further information. > The perf > tool driver automatically adds the "contextid" tracing and timestamp for > "system wide" and process bound events, as they traces get mixed into > the single sink. So these options are added implicitly by the perf tool > to make the decoding easier. > That's fine - I have no problem with contextID trace enabled by default. Context ID is relatively low overhead - and only emitted at start of trace / context changes. But the explanation of the parameters currently reads as though they always have an effect - and not putting them in there will omit the effect - unless you spot the very subtle line at the end. The user does not need to know about parameters that have no effect! Perhaps a better approach would be to explain the above - an explicit statement that "perf will always enable PID/ contextID tracing at the relevant EL - but for EL2 it is possible to make specific adjustments using para
Re: [PATCH v2 7/7] Documentation: coresight: Add PID tracing description
Hi, On Tue, 2 Feb 2021 at 16:39, Leo Yan wrote: > > After support the PID tracing for the kernel in EL1 or EL2, the usage > gets more complicated. > > This patch gives description for the PMU formats of contextID configs, > this can help users to understand how to control the knobs for PID > tracing when the kernel is in different ELs. > > Signed-off-by: Leo Yan > --- > Documentation/trace/coresight/coresight.rst | 37 + > 1 file changed, 37 insertions(+) > > diff --git a/Documentation/trace/coresight/coresight.rst > b/Documentation/trace/coresight/coresight.rst > index 0b73acb44efa..771558f22938 100644 > --- a/Documentation/trace/coresight/coresight.rst > +++ b/Documentation/trace/coresight/coresight.rst > @@ -512,6 +512,43 @@ The --itrace option controls the type and frequency of > synthesized events > Note that only 64-bit programs are currently supported - further work is > required to support instruction decode of 32-bit Arm programs. > > +2.2) Tracing PID > + > +When the kernel is running at EL2 with Virtualization Host Extensions (VHE), > +perf records CONTEXTIDR_EL2 in the trace data and can be used as PID when > +decoding; and if the kernel is running at EL1 with nVHE, CONTEXTIDR_EL1 is > +traced for PID. > + Would this introductory paragraph be better if is explained where the kernel stores the PID for the different levels, then we logically move on to how to trace this in perf. e.g:- "The lernel can be built to write the PID value into the PE ContextID registers. For a kernel running at EL1, the PID is stored in CONTEXTIDR_EL1. A PE may implement ARM Virtualisation Host Extensions (VHE), were the kernel can run at EL2 as a virtualisation host. In this case the PID value is stored in CONTEXTIDR_EL2. perf provides PMU options which program the ETM to insert these values into the trace data." > +To support tracing PID for the kernel runs at different exception levels, > +the PMU formats are defined as follow: > + > + "contextid1": Available on both EL1 kernel and EL2 kernel. When the > +kernel is running at EL1, "contextid1" enables the PID > +tracing; when the kernel is running at EL2, this enables > +tracing the PID of guest applications. > + > + "contextid2": Only usable when the kernel is running at EL2. When > +selected, enables PID tracing on EL2 kernel. > + > + "contextid": Will be an alias for the option that enables PID > +tracing. I.e, > +contextid == contextid1, on EL1 kernel. > +contextid == contextid2, on EL2 kernel. > + > +The perf tool automatically sets corresponding bit for the "contextid" > config, > +therefore, the user doesn't have to bother which EL the kernel is running. > + > + i.e, perf record -e cs_etm/contextid/u -- uname > +or perf record -e cs_etm//u -- uname > + > +will always do the "PID" tracing, independent of the kernel EL. > + This is telling me that both cs_etm// and cs_etm/contextid/ have the same effect - trace PID. Is this correct? If so, then contextid, contextid1 and contextid2 have no effect except in specific EL2 circumstances. > +When the kernel is running at EL2 with VHE, if user wants to trace both the > +PIDs for both host and guest, the two configs "contextid1" and "contextid2" > +can be set at the same time: > + > + perf record -e cs_etm/contextid1,contextid2/u -- uname > + > Regards Mike > Generating coverage files for Feedback Directed Optimization: AutoFDO > - > -- > 2.25.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
[PATCH v5] perf: cs-etm: update ETM metadata format
The current fixed metadata version format (version 0), means that adding
metadata parameter items renders files from a previous version of perf
unreadable. Per CPU parameters appear in a fixed order, but there is no
field to indicate the number of ETM parameters per CPU.
This patch updates the per CPU parameter blocks to include a NR_PARAMs
value which indicates the number of parameters in the block.
The header version is incremented to 1. Fixed ordering is retained,
new ETM parameters are added to the end of the list.
The reader code is updated to be able to read current version 0 files,
For version 1, the reader will read the number of parameters in the
per CPU block. This allows the reader to process older or newer files
that may have different numbers of parameters than in use at the
time perf was built.
Signed-off-by: Mike Leach
Reviewed-by: Leo Yan
Tested-by: Leo Yan
---
Changes since v4
1. Syntax fixes suggested by Mathieu.
Changes since v3
1. Fixed index bug (Leo)
Changes since v2
1. Add error path print to improve --dump logging
2. Replace some hardcoded values with enum consts (Mathieu).
Changes since v1 (from Review by Leo):
1. Split printing routine into sub functions per version
2. Renamed NR_PARAMs to NR_TRC_PARAMs to emphasise use as count of trace
related parameters, not total block parameter.
3. Misc other fixes.
---
tools/perf/arch/arm/util/cs-etm.c | 7 +-
tools/perf/util/cs-etm.c | 235 --
tools/perf/util/cs-etm.h | 30 +++-
3 files changed, 223 insertions(+), 49 deletions(-)
diff --git a/tools/perf/arch/arm/util/cs-etm.c
b/tools/perf/arch/arm/util/cs-etm.c
index bd446aba64f7..b0470f2a955a 100644
--- a/tools/perf/arch/arm/util/cs-etm.c
+++ b/tools/perf/arch/arm/util/cs-etm.c
@@ -572,7 +572,7 @@ static void cs_etm_get_metadata(int cpu, u32 *offset,
struct auxtrace_record *itr,
struct perf_record_auxtrace_info *info)
{
- u32 increment;
+ u32 increment, nr_trc_params;
u64 magic;
struct cs_etm_recording *ptr =
container_of(itr, struct cs_etm_recording, itr);
@@ -607,6 +607,7 @@ static void cs_etm_get_metadata(int cpu, u32 *offset,
/* How much space was used */
increment = CS_ETMV4_PRIV_MAX;
+ nr_trc_params = CS_ETMV4_PRIV_MAX - CS_ETMV4_TRCCONFIGR;
} else {
magic = __perf_cs_etmv3_magic;
/* Get configuration register */
@@ -624,11 +625,13 @@ static void cs_etm_get_metadata(int cpu, u32 *offset,
/* How much space was used */
increment = CS_ETM_PRIV_MAX;
+ nr_trc_params = CS_ETM_PRIV_MAX - CS_ETM_ETMCR;
}
/* Build generic header portion */
info->priv[*offset + CS_ETM_MAGIC] = magic;
info->priv[*offset + CS_ETM_CPU] = cpu;
+ info->priv[*offset + CS_ETM_NR_TRC_PARAMS] = nr_trc_params;
/* Where the next CPU entry should start from */
*offset += increment;
}
@@ -674,7 +677,7 @@ static int cs_etm_info_fill(struct auxtrace_record *itr,
/* First fill out the session header */
info->type = PERF_AUXTRACE_CS_ETM;
- info->priv[CS_HEADER_VERSION_0] = 0;
+ info->priv[CS_HEADER_VERSION] = CS_HEADER_CURRENT_VERSION;
info->priv[CS_PMU_TYPE_CPUS] = type << 32;
info->priv[CS_PMU_TYPE_CPUS] |= nr_cpu;
info->priv[CS_ETM_SNAPSHOT] = ptr->snapshot_mode;
diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index a2a369e2fbb6..ee32d023e9bd 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -2435,7 +2435,7 @@ static bool cs_etm__is_timeless_decoding(struct
cs_etm_auxtrace *etm)
}
static const char * const cs_etm_global_header_fmts[] = {
- [CS_HEADER_VERSION_0] = " Header version %llx\n",
+ [CS_HEADER_VERSION] = " Header version %llx\n",
[CS_PMU_TYPE_CPUS] = " PMU type/num cpus %llx\n",
[CS_ETM_SNAPSHOT] = " Snapshot %llx\n",
};
@@ -2443,6 +2443,7 @@ static const char * const cs_etm_global_header_fmts[] = {
static const char * const cs_etm_priv_fmts[] = {
[CS_ETM_MAGIC] = " Magic number %llx\n",
[CS_ETM_CPU]= " CPU%lld\n",
+ [CS_ETM_NR_TRC_PARAMS] = " NR_TRC_PARAMS %llx\n",
[CS_ETM_ETMCR] = " ETMCR %llx\n",
[CS_ETM_ETMTRACEIDR]= " ETMTRACEIDR%llx\n",
[CS_ETM_ETMCCER]= " ETMCCER%llx\n",
@@ -2452,6 +2453,7 @@ static const char * const cs_etm_priv_fmts
Re: [PATCH v4] perf: cs-etm: update ETM metadata format
Hi Mathieu,
On Fri, 29 Jan 2021 at 18:57, Mathieu Poirier
wrote:
>
> It just dawned on me that this file doesn't go through my tree, Arnaldo
> handles
> perf tools modifications. Please see below for further instructions.
>
> On Fri, Jan 29, 2021 at 11:40:04AM -0700, Mathieu Poirier wrote:
> > Good morning,
> >
> > On Wed, Jan 27, 2021 at 05:53:50PM +, Mike Leach wrote:
> > > The current fixed metadata version format (version 0), means that adding
> > > metadata parameter items renders files from a previous version of perf
> > > unreadable. Per CPU parameters appear in a fixed order, but there is no
> > > field to indicate the number of ETM parameters per CPU.
> > >
> > > This patch updates the per CPU parameter blocks to include a NR_PARAMs
> > > value which indicates the number of parameters in the block.
> > >
> > > The header version is incremented to 1. Fixed ordering is retained,
> > > new ETM parameters are added to the end of the list.
> > >
> > > The reader code is updated to be able to read current version 0 files,
> > > For version 1, the reader will read the number of parameters in the
> > > per CPU block. This allows the reader to process older or newer files
> > > that may have different numbers of parameters than in use at the
> > > time perf was built.
> > >
> > > Changes since v3
> > > 1. Fixed index bug (Leo)
> > >
> > > Changes since v2
> > > 1. Add error path print to improve --dump logging
> > > 2. Replace some hardcoded values with enum consts (Mathieu).
> > >
> > > Changes since v1 (from Review by Leo):
> > > 1. Split printing routine into sub functions per version
> > > 2. Renamed NR_PARAMs to NR_TRC_PARAMs to emphasise use as count of trace
> > > related parameters, not total block parameter.
> > > 3. Misc other fixes.
> > >
> > > Signed-off-by: Mike Leach
> >
> > Leo added his RB and TB tags to this patch for V3. When that happens the
> > author
> > is expected to carry them in the next revision. I added them.
>
Yes sorry - oversight on my part. Fixed in v5
> Version logs needs to go below the "---". Otherwise they will be added
> to the changelog and we don't want that.
>
OK
> >
> > > ---
> > > tools/perf/arch/arm/util/cs-etm.c | 7 +-
> > > tools/perf/util/cs-etm.c | 235 --
> > > tools/perf/util/cs-etm.h | 30 +++-
> > > 3 files changed, 223 insertions(+), 49 deletions(-)
> > >
> > > diff --git a/tools/perf/arch/arm/util/cs-etm.c
> > > b/tools/perf/arch/arm/util/cs-etm.c
> > > index bd446aba64f7..b0470f2a955a 100644
> > > --- a/tools/perf/arch/arm/util/cs-etm.c
> > > +++ b/tools/perf/arch/arm/util/cs-etm.c
> > > @@ -572,7 +572,7 @@ static void cs_etm_get_metadata(int cpu, u32 *offset,
> > > struct auxtrace_record *itr,
> > > struct perf_record_auxtrace_info *info)
> > > {
> > > - u32 increment;
> > > + u32 increment, nr_trc_params;
> > > u64 magic;
> > > struct cs_etm_recording *ptr =
> > > container_of(itr, struct cs_etm_recording, itr);
> > > @@ -607,6 +607,7 @@ static void cs_etm_get_metadata(int cpu, u32 *offset,
> > >
> > > /* How much space was used */
> > > increment = CS_ETMV4_PRIV_MAX;
> > > + nr_trc_params = CS_ETMV4_PRIV_MAX - CS_ETMV4_TRCCONFIGR;
> > > } else {
> > > magic = __perf_cs_etmv3_magic;
> > > /* Get configuration register */
> > > @@ -624,11 +625,13 @@ static void cs_etm_get_metadata(int cpu, u32
> > > *offset,
> > >
> > > /* How much space was used */
> > > increment = CS_ETM_PRIV_MAX;
> > > + nr_trc_params = CS_ETM_PRIV_MAX - CS_ETM_ETMCR;
> > > }
> > >
> > > /* Build generic header portion */
> > > info->priv[*offset + CS_ETM_MAGIC] = magic;
> > > info->priv[*offset + CS_ETM_CPU] = cpu;
> > > + info->priv[*offset + CS_ETM_NR_TRC_PARAMS] = nr_trc_params;
> > > /* Where the next CPU entry should start from */
> > > *offset += increment;
> > > }
> > > @@ -674,7 +677,7 @@ static int cs_etm_info_fill(struct auxtrace_record
> > > *itr,
> > >
> > > /* First fill out
Re: [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks
Hi, On Tue, 2 Feb 2021 at 09:42, Suzuki K Poulose wrote: > > On 2/1/21 11:17 PM, Mathieu Poirier wrote: > > Hi Anshuman, > > > > I have started reviewing this set. As it is quite voluminous comments will > > come over serveral days. I will let you know when I am done. > > > > On Wed, Jan 27, 2021 at 02:25:25PM +0530, Anshuman Khandual wrote: > >> From: Suzuki K Poulose > >> > >> When there are multiple sinks on the system, in the absence > >> of a specified sink, it is quite possible that a default sink > >> for an ETM could be different from that of another ETM. However > >> we do not support having multiple sinks for an event yet. This > >> patch allows the event to use the default sinks on the ETMs > >> where they are scheduled as long as the sinks are of the same > >> type. > >> > >> e.g, if we have 1x1 topology with per-CPU ETRs, the event can > >> use the per-CPU ETR for the session. However, if the sinks > >> are of different type, e.g TMC-ETR on one and a custom sink > >> on another, the event will only trace on the first detected > >> sink. > >> > > > > I found the above changelog very confusing - I read it several times and > > still > > couldn't get all of it. In the end this patch prevents sinks of different > > types > > from being used for session, and this is what the text should reflect. > > Sorry about that. Your inference is correct, but it is only a side effect > of the primary motive. How about the following : > > "When a sink is not specified by the user, the etm perf driver > finds a suitable sink automatically based on the first ETM, where > this event could be scheduled. Then we allocate the sink buffer based > on the selected sink. This is fine for a CPU bound event as the "sink" > is always guaranteed to be reachable from the ETM (as this is the only > ETM where the event is going to be scheduled). However, if we have a task > bound event, the event could be scheduled on any of the ETMs on the > system. In this case, currently we automatically select a sink and exclude > any ETMs that are not reachable from the selected sink. This is > problematic for 1x1 configurations as we end up in tracing the event > only on the "first" ETM, as the default sink is local to the first > ETM and unreachable from the rest. > However, we could allow the other ETMs to trace if they all have a > sink that is compatible with the "selected" sink and can use the > sink buffer. This can be easily done by verifying that they are > all driven by the same driver and matches the same subtype." > Not sure that the logic here makes total sense - I can't see _why_ multiple sinks need to be of the same type. 1) This patch is designed to allow multiple sinks to be used in a 1:1 topology system - but there is no specific restriction here - and N:M should work on the same basis 2) This implies that multiple sinks will work within the coresight infrastucture. 3) The sink interface -> struct coresight_ops_sink allows sinks to be abstracted - therefore whichever sink is chosen the coresight infrastructure calls the operations for the given sink. 4) Each individual sink, will have its own hardware buffer - copied into the perf buffers at some appropriate point. Thus if the users specifies a selected sink - we need to eliminate any source that cannot reach it. If not we need to find the relevant default sink for the source, which might be a shared ETR, or per CPU TRBE / ETR, and the abstraction logic ought to handle getting the captured data to the correct place. If it doesn't then we are on shaky ground with any multiple sink solution. On the face of it - type is irrelevant. If I am missing something - this patch needs a better explanation. > > > > >> Cc: Mathieu Poirier > >> Cc: Mike Leach > >> Tested-by: Linu Cherian > >> Signed-off-by: Suzuki K Poulose > >> Signed-off-by: Anshuman Khandual > >> --- > >> drivers/hwtracing/coresight/coresight-etm-perf.c | 48 > >> +++- > >> 1 file changed, 38 insertions(+), 10 deletions(-) > >> > >> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c > >> b/drivers/hwtracing/coresight/coresight-etm-perf.c > >> index bdc34ca..eb9e7e9 100644 > >> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > >> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > >> @@ -204,6 +204,13 @@ static void etm_free_aux(void *data) > >> schedule_work(&event_data->work); > >> } > >> > >> +stati
Re: [PATCH V3 02/14] coresight: Do not scan for graph if none is present
Hi Ansuman,
On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
wrote:
>
> From: Suzuki K Poulose
>
> If a graph node is not found for a given node, of_get_next_endpoint()
> will emit the following error message :
>
> OF: graph: no port node found in /
>
> If the given component doesn't have any explicit connections (e.g,
> ETE) we could simply ignore the graph parsing.
>
> Cc: Mathieu Poirier
> Cc: Mike Leach
> Signed-off-by: Suzuki K Poulose
> Signed-off-by: Anshuman Khandual
> ---
> drivers/hwtracing/coresight/coresight-platform.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-platform.c
> b/drivers/hwtracing/coresight/coresight-platform.c
> index 3629b78..c594f45 100644
> --- a/drivers/hwtracing/coresight/coresight-platform.c
> +++ b/drivers/hwtracing/coresight/coresight-platform.c
> @@ -90,6 +90,12 @@ static void of_coresight_get_ports_legacy(const struct
> device_node *node,
> struct of_endpoint endpoint;
> int in = 0, out = 0;
>
> + /*
> +* Avoid warnings in of_graph_get_next_endpoint()
> +* if the device doesn't have any graph connections
> +*/
> + if (!of_graph_is_present(node))
> + return;
The problem here is that you are masking genuine errors.
The solution is to either call this only if the device type is one
that ports are not required - i.e. ETE, or upgrade the .dts bindings
for the rest of the ETM devices to yaml so that the ports requirement
is checked and validated there.
Regards
Mike
> do {
> ep = of_graph_get_next_endpoint(node, ep);
> if (!ep)
> --
> 2.7.4
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
[PATCH v4 00/10] CoreSight configuration management; ETM strobing
This patchset introduces initial concepts in CoreSight system configuration management support. to allow more detailed and complex programming to be applied to CoreSight systems during trace capture. Configurations consist of 2 elements:- 1) Features - programming combinations for devices, applied to a class of device on the system (all ETMv4), or individual devices. 2) Configurations - a set of programmed features used when the named configuration is selected. Features and configurations are declared as a data table, a set of register, resource and parameter requirements. Features and configurations are loaded into the system by the virtual cs_syscfg device. This then matches features to any registered devices and loads the feature into them. Individual device classes that support feature and configuration register with cs_syscfg. Once loaded a configuration can be enabled for a specific trace run. Configurations are registered with the perf cs_etm event as entries in cs_etm/cs_config. These can be selected on the perf command line as follows:- perf record -e cs_etm// ... This patch set has one pre-loaded configuration and feature. A named "strobing" feature is provided for ETMv4. A named "autofdo" configuration is provided. This configuration enables strobing on any ETM in used. Thus the command: perf record -e cs_etm/autofdo/ ... will trace the supplied application while enabling the "autofdo" configuation on each ETM as it is enabled by perf. This in turn will enable strobing for the ETM - with default parameters. Parameters can be adjusted using configfs. The sink used in the trace run will be automatically selected. A configuation can supply up to 15 of preset parameter values, which will subsitute in parameter values for any feature used in the configuration. Selection of preset values as follows perf record -e cs_etm/autofdo,preset=1/ ... (valid presets 1-N, where N is the number supplied in the configuration, not exceeding 15. preset=0 is the same as not selecting a preset.) Applies to coresight/next (5.11-rc2 base) Changes since v3: (Primarily based on comments from Matthieu) 1) Locking mechanisms simplified. 2) Removed the possibility to enable features independently from configurations.Only configurations can be enabled now. Simplifies programming logic. 3) Configuration now uses an activate->enable mechanism. This means that perf will activate a selected configuration at the start of a session (during setup_aux), and disable at the end of a session (around free_aux) The active configuration and associated features will be programmed into the CoreSight device instances when they are enabled. This locks the configuration into the system while in use. Parameters cannot be altered while this is in place. This mechanism will be extended in future for dynamic load / unload of configurations to prevent removal while in use. 4) Removed the custom bus / driver as un-necessary. A single device is registered to own perf fs elements and configfs. 5) Various other minor issues addressed. Changes since v2: 1) Added documentation file. 2) Altered cs_syscfg driver to no longer be coresight_device based, and moved to its own custom bus to remove it from the main coresight bus. (Mathieu) 3) Added configfs support to inspect and control loaded configurations and features. Allows listing of preset values (Yabin Cui) 4) Dropped sysfs support for adjusting feature parameters on the per device basis, in favour of a single point adjustment in configfs that is pushed to all device instances. 5) Altered how the config and preset command line options are handled in perf and the drivers. (Mathieu and Suzuki). 6) Fixes for various issues and technical points (Mathieu, Yabin) Changes since v1: 1) Moved preloaded configurations and features out of individual drivers. 2) Added cs_syscfg driver to manage configurations and features. Individual drivers register with cs_syscfg indicating support for config, and provide matching information that the system uses to load features into the drivers. This allows individual drivers to be updated on an as needed basis - and removes the need to consider devices that cannot benefit from configuration - static replicators, funnels, tpiu. 3) Added perf selection of configuarations. 4) Rebased onto the coresight module loading set. To follow in future revisions / sets:- a) load of additional config and features by loadable module. b) load of additional config and features by configfs c) enhanced resource management for ETMv4 and checking features have sufficient resources to be enabled. d) ECT and CTI support for configuration and features. Mike Leach (10): coresight: syscfg: Initial coresight system configuration coresight: syscfg: Add registration and feature loading for cs devices coresight: config: Add configuration and feature generic functions coresight: etm-perf: update to handle configuration selection coresight: syscf
[PATCH v4 02/10] coresight: syscfg: Add registration and feature loading for cs devices
API for individual devices to register with the syscfg management
system is added.
Devices register with matching information, and any features or
configurations that match will be loaded into the device.
The feature and configuration loading is extended so that on load these
are loaded into any currently registered devices. This allows
configuration loading after devices have been registered.
Signed-off-by: Mike Leach
---
.../hwtracing/coresight/coresight-config.h| 98 +
.../hwtracing/coresight/coresight-syscfg.c| 348 ++
.../hwtracing/coresight/coresight-syscfg.h| 20 +
include/linux/coresight.h | 5 +
4 files changed, 471 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
index 3fedf8ab3cee..75ecdecf7013 100644
--- a/drivers/hwtracing/coresight/coresight-config.h
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -164,4 +164,102 @@ struct cscfg_config_desc {
const u64 *presets; /* nr_presets * nr_total_params */
};
+/**
+ * config register instance - part of a loaded feature.
+ *maps register values to csdev driver structures
+ *
+ * @value: value to use when setting feature on device / store for
+ * readback of volatile values.
+ * @drv_store: pointer to internal driver element used to set the value
+ * in hardware.
+ */
+struct cscfg_reg_csdev {
+ struct cscfg_regval_desc value;
+ void *drv_store;
+};
+
+/**
+ * config parameter instance - part of a loaded feature.
+ *
+ * @feat: parent feature
+ * @reg: register value updated by this parameter.
+ * @current_value: current value of parameter - may be set by user via
+ * sysfs, or modified during device operation.
+ * @val64: true if 64 bit value
+ */
+struct cscfg_parameter_csdev {
+ struct cscfg_feature_csdev *feat;
+ struct cscfg_reg_csdev *reg;
+ u64 current_value;
+ bool val64;
+};
+
+/**
+ * Feature instance loaded into a CoreSight device.
+ *
+ * When a feature is loaded into a specific device, then this structure holds
+ * the connections between the register / parameter values used and the
+ * internal data structures that are written when the feature is enabled.
+ *
+ * Since applying a feature modifies internal data structures in the device,
+ * then we have a reference to the device spinlock to protect access to these
+ * structures (@csdev_spinlock).
+ *
+ * @desc: pointer to the static descriptor for this feature.
+ * @csdev: parent CoreSight device instance.
+ * @node: list entry into feature list for this device.
+ * @csdev_spinlock:device spinlock from csdev instance..
+ * @nr_params: number of parameters.
+ * @params:current parameter values on this device
+ * @nr_regs: number of registers to be programmed.
+ * @regs: Programming details for the registers
+ */
+struct cscfg_feature_csdev {
+ const struct cscfg_feature_desc *desc;
+ struct coresight_device *csdev;
+ struct list_head node;
+ spinlock_t *csdev_spinlock;
+ int nr_params;
+ struct cscfg_parameter_csdev *params;
+ int nr_regs;
+ struct cscfg_reg_csdev *regs;
+};
+
+/**
+ * Configuration instance when loaded into a CoreSight device.
+ *
+ * The instance contains references to loaded features on this device that are
+ * used by the configuration.
+ *
+ * @desc: reference to the descriptor for this configuration
+ * @csdev: parent coresight device for this configuration instance.
+ * @node: list entry within the coresight device
+ * @nr_feat: Number of features on this device that are used in the
+ * configuration.
+ * @feats: reference to the device features to enable.
+ * @enabled: true if configuration is enabled on this device.
+ */
+struct cscfg_config_csdev {
+ const struct cscfg_config_desc *desc;
+ struct coresight_device *csdev;
+ struct list_head node;
+ int nr_feat;
+ struct cscfg_feature_csdev **feats;
+ bool enabled;
+};
+
+/**
+ * Coresight device operations.
+ *
+ * Registered coresight devices provide these operations to manage feature
+ * instances compatible with the device hardware and drivers
+ *
+ * @load_feat: Pass a feature descriptor into the device and create the
+ * loaded feature instance (struct cscfg_feature_csdev).
+ */
+struct cscfg_csdev_feat_ops {
+ int (*load_feat)(struct coresight_device *csdev,
+struct cscfg_feature_csdev *feat);
+};
+
#endif /* _CORESIGHT_CORESIGHT_CONFIG_H */
diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c
b/drivers/hwtracing/coresight/coresight-syscfg.c
index f7e396a5f9cb..c04cea0c1db2 100644
--- a/drivers/hwtracing/coresight/coresight-syscfg.c
+++ b/drivers
[PATCH v4 04/10] coresight: etm-perf: update to handle configuration selection
Loaded coresight configurations are registered in the cs_etm\cs_config sub
directory. This extends the etm-perf code to handle these registrations,
and the cs_syscfg driver to perform the registration on load.
Signed-off-by: Mike Leach
---
.../hwtracing/coresight/coresight-config.h| 5 +-
.../hwtracing/coresight/coresight-etm-perf.c | 164 +++---
.../hwtracing/coresight/coresight-etm-perf.h | 8 +
.../hwtracing/coresight/coresight-syscfg.c| 13 +-
4 files changed, 166 insertions(+), 24 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
index 9d66e0071f38..98380b496046 100644
--- a/drivers/hwtracing/coresight/coresight-config.h
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -154,7 +154,8 @@ struct cscfg_config_feat_ref {
* @nr_presets:Number of sets of presets supplied by this
configuration.
* @nr_total_params: Sum of all parameters declared by used features
* @presets: Array of preset values.
- *
+ * @id_ea: Extended attribute for perf configid value
+ * @event_ea: Extended attribute for perf event value
*/
struct cscfg_config_desc {
const char *name;
@@ -165,6 +166,8 @@ struct cscfg_config_desc {
int nr_presets;
int nr_total_params;
const u64 *presets; /* nr_presets * nr_total_params */
+ struct dev_ext_attribute *id_ea;
+ struct dev_ext_attribute *event_ea;
};
/**
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index a608081bd446..e270bb1e0f7d 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -18,8 +18,10 @@
#include
#include
+#include "coresight-config.h"
#include "coresight-etm-perf.h"
#include "coresight-priv.h"
+#include "coresight-syscfg.h"
static struct pmu etm_pmu;
static bool etm_perf_up;
@@ -32,8 +34,13 @@ PMU_FORMAT_ATTR(cycacc, "config:"
__stringify(ETM_OPT_CYCACC));
PMU_FORMAT_ATTR(contextid, "config:" __stringify(ETM_OPT_CTXTID));
PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS));
PMU_FORMAT_ATTR(retstack, "config:" __stringify(ETM_OPT_RETSTK));
+/* preset - if sink ID is used as a configuration selector */
+PMU_FORMAT_ATTR(preset,"config:0-3");
/* Sink ID - same for all ETMs */
PMU_FORMAT_ATTR(sinkid,"config2:0-31");
+/* config ID - set if a system configuration is selected */
+PMU_FORMAT_ATTR(configid, "config2:32-63");
+
static struct attribute *etm_config_formats_attr[] = {
&format_attr_cycacc.attr,
@@ -41,6 +48,8 @@ static struct attribute *etm_config_formats_attr[] = {
&format_attr_timestamp.attr,
&format_attr_retstack.attr,
&format_attr_sinkid.attr,
+ &format_attr_preset.attr,
+ &format_attr_configid.attr,
NULL,
};
@@ -58,9 +67,29 @@ static const struct attribute_group etm_pmu_sinks_group = {
.attrs = etm_config_sinks_attr,
};
+static struct attribute *etm_config_cscfg_attr[] = {
+ NULL,
+};
+
+static const struct attribute_group etm_pmu_cscfg_group = {
+ .name = "configurations",
+ .attrs = etm_config_cscfg_attr,
+};
+
+static struct attribute *etm_config_events_attr[] = {
+ NULL,
+};
+
+static const struct attribute_group etm_pmu_events_group = {
+ .name = "events",
+ .attrs = etm_config_events_attr,
+};
+
static const struct attribute_group *etm_pmu_attr_groups[] = {
&etm_pmu_format_group,
&etm_pmu_sinks_group,
+ &etm_pmu_cscfg_group,
+ &etm_pmu_events_group,
NULL,
};
@@ -219,7 +248,7 @@ static void *etm_setup_aux(struct perf_event *event, void
**pages,
INIT_WORK(&event_data->work, free_event_data);
/* First get the selected sink from user space. */
- if (event->attr.config2) {
+ if (event->attr.config2 & GENMASK_ULL(31, 0)) {
id = (u32)event->attr.config2;
sink = coresight_get_sink_by_id(id);
}
@@ -537,21 +566,17 @@ static ssize_t etm_perf_sink_name_show(struct device *dev,
return scnprintf(buf, PAGE_SIZE, "0x%lx\n", (unsigned long)(ea->var));
}
-int etm_perf_add_symlink_sink(struct coresight_device *csdev)
+int etm_perf_add_symlink_group(struct device *dev,
+ struct dev_ext_attribute **ext_attr,
+ const char *name,
+ const char *group_name)
{
- int ret;
+ struct dev_ext_attribute *ea;
unsigned long hash;
- const char *name;
+ int ret;
struct device *pmu_dev = etm_pmu.dev;
- struct device *dev = &csdev->
[PATCH v4 10/10] coresight: docs: Add documentation for CoreSight config
Adds documentation for the CoreSight System configuration manager. Signed-off-by: Mike Leach --- .../trace/coresight/coresight-config.rst | 244 ++ Documentation/trace/coresight/coresight.rst | 16 ++ 2 files changed, 260 insertions(+) create mode 100644 Documentation/trace/coresight/coresight-config.rst diff --git a/Documentation/trace/coresight/coresight-config.rst b/Documentation/trace/coresight/coresight-config.rst new file mode 100644 index ..3a4aa7bfa131 --- /dev/null +++ b/Documentation/trace/coresight/coresight-config.rst @@ -0,0 +1,244 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== +CoreSight System Configuration Manager +== + +:Author: Mike Leach +:Date: October 2020 + +Introduction + + +The CoreSight System Configuration manager is an API that allows the +programming of the CoreSight system with pre-defined configurations that +can then be easily enabled from sysfs or perf. + +Many CoreSight components can be programmed in complex ways - especially ETMs. +In addition, components can interact across the CoreSight system, often via +the cross trigger components such as CTI and CTM. These system settings can +be defined and enabled as named configurations. + + +Basic Concepts +== + +This section introduces the basic concepts of a CoreSight system configuration. + + +Features + + +A feature is a named set of programming for a CoreSight device. The programming +is device dependent, and can be defined in terms of absolute register values, +resource usage and parameter values. + +The feature is defined using a descriptor. This descriptor is used to load onto +a matching device, either when the feature is loaded into the system, or when the +CoreSight device is registered with the configuration manager. + +The load process involves interpreting the descriptor into a set of register +accesses in the driver - the resource usage and parameter descriptions +translated into appropriate register accesses. This interpretation makes it easy +and efficient for the feature to be programmed onto the device when required. + +The feature will not be active on the device until the feature is enabled, and +the device itself is enabled. When the device is enabled then enabled features +will be programmed into the device hardware. + +A feature is enabled as part of a configuration being enabled on the system. + + +Parameter Value +~~~ + +A parameter value is a named value that may be set by the user prior to the +feature being enabled that can adjust the behaviour of the operation programmed +by the feature. + +For example, this could be a count value in a programmed operation that repeats +at a given rate. When the feature is enabled then the current value of the +parameter is used in programming the device. + +The feature descriptor defines a default value for a parameter, which is used +if the user does not supply a new value. + +Users can update parameter values using the configfs API for the CoreSight +system - which is described below. + +The current value of the parameter is loaded into the device when the feature +is enabled on that device. + + +Configurations +-- + +A configuration defines a set of features that are to be used in a trace +session where the configuration is selected. For any trace session only one +configuration may be selected. + +The features defined may be on any type of device that is registered +to support system configuration. A configuration may select features to be +enabled on a class of devices - i.e. any ETMv4, or specific devices, e.g. a +specific CTI on the system. + +As with the feature, a descriptor is used to define the configuration. +This will define the features that must be enabled as part of the configuration +as well as any preset values that can be used to override default parameter +values. + + +Preset Values +~ + +Preset values are easily selectable sets of parameter values for the features +that the configuration uses. The number of values in a single preset set, equals +the sum of parameter values in the features used by the configuration. + +e.g. a configuration consists of 3 features, one has 2 parameters, one has +a single parameter, and another has no parameters. A single preset set will +therefore have 3 values. + +Presets are optionally defined by the configuration, up to 15 can be defined. +If no preset is selected, then the parameter values defined in the feature +are used as normal. + + +Operation +~ + +The following steps take place in the operation of a configuration. + +1) In this example, the configuration is 'autofdo', which has an + associated feature 'strobing' that works on ETMv4 CoreSight Devices. + +2) The configuration is enabled. For example 'perf' may select the + configuration as part of its command line:
[PATCH v4 08/10] coresight: config: Add preloaded configurations
Preload set of configurations.
This patch creates a small set of preloaded configurations and features
that are available immediately after coresight has been initialised.
The current set provides a strobing feature for ETMv4, that creates a
periodic sampling of trace by switching trace generation on and off
using counters in the ETM.
A configuration called "autofdo" is also provided that uses the 'strobing'
feature and provides a couple of preset values, selectable on the perf
command line.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../hwtracing/coresight/coresight-cfg-afdo.c | 154 ++
.../coresight/coresight-cfg-preload.c | 25 +++
.../coresight/coresight-cfg-preload.h | 11 ++
drivers/hwtracing/coresight/coresight-core.c | 6 +
.../hwtracing/coresight/coresight-syscfg.h| 1 +
6 files changed, 199 insertions(+), 1 deletion(-)
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-afdo.c
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.c
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-preload.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index ea544206204d..2707bfef1b76 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -4,7 +4,8 @@
#
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
- coresight-sysfs.o coresight-syscfg.o coresight-config.o
+ coresight-sysfs.o coresight-syscfg.o coresight-config.o \
+ coresight-cfg-preload.o coresight-cfg-afdo.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-cfg-afdo.c
b/drivers/hwtracing/coresight/coresight-cfg-afdo.c
new file mode 100644
index ..ff69fb3f4434
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-cfg-afdo.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2020 Linaro Limited. All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include "coresight-config.h"
+#include "coresight-etm4x-cfg.h"
+
+/* preload configurations and features */
+
+/* preload in features for ETMv4 */
+
+/* strobe feature */
+static struct cscfg_parameter_desc strobe_params[] = {
+ {
+ .name = "window",
+ .value = 5000,
+ },
+ {
+ .name = "period",
+ .value = 1,
+ },
+};
+
+static struct cscfg_regval_desc strobe_regs[] = {
+ /* resource selectors */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCRSCTLRn(2),
+ .hw_info = ETM4_CFG_RES_SEL,
+ .val32 = 0x20001,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCRSCTLRn(3),
+ .hw_info = ETM4_CFG_RES_SEQ,
+ .val32 = 0x20002,
+ },
+ /* strobe window counter 0 - reload from param 0 */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE,
+ .offset = TRCCNTVRn(0),
+ .hw_info = ETM4_CFG_RES_CTR,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM,
+ .offset = TRCCNTRLDVRn(0),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 0,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCCNTCTLRn(0),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 0x10001,
+ },
+ /* strobe period counter 1 - reload from param 1 */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_SAVE,
+ .offset = TRCCNTVRn(1),
+ .hw_info = ETM4_CFG_RES_CTR,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_PARAM,
+ .offset = TRCCNTRLDVRn(1),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 1,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCCNTCTLRn(1),
+ .hw_info = ETM4_CFG_RES_CTR,
+ .val32 = 0x8102,
+ },
+ /* sequencer */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCSEQEVRn(0),
+ .hw_info = ETM4_CFG_RES_SEQ,
+ .val32 = 0x0081,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCSEQEVRn(1),
+ .hw_info = ETM4_CFG_RES_SEQ,
+ .val32 = 0x,
+ },
+ /* view-inst */
+ {
+ .type = CS_CFG_REG_TYPE_STD | C
[PATCH v4 05/10] coresight: syscfg: Add API to activate and enable configurations
Configurations are first activated, then when any coresight device is
enabled, the active configurations are checked and any matching
one is enabled.
This patch provides the activation / enable API.
Signed-off-by: Mike Leach
---
.../hwtracing/coresight/coresight-config.h| 2 +
.../hwtracing/coresight/coresight-syscfg.c| 127 ++
.../hwtracing/coresight/coresight-syscfg.h| 10 +-
include/linux/coresight.h | 2 +
4 files changed, 140 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-config.h
b/drivers/hwtracing/coresight/coresight-config.h
index 98380b496046..26396b70c826 100644
--- a/drivers/hwtracing/coresight/coresight-config.h
+++ b/drivers/hwtracing/coresight/coresight-config.h
@@ -156,6 +156,7 @@ struct cscfg_config_feat_ref {
* @presets: Array of preset values.
* @id_ea: Extended attribute for perf configid value
* @event_ea: Extended attribute for perf event value
+ * @active_cnt: ref count for activate on this configuration.
*/
struct cscfg_config_desc {
const char *name;
@@ -168,6 +169,7 @@ struct cscfg_config_desc {
const u64 *presets; /* nr_presets * nr_total_params */
struct dev_ext_attribute *id_ea;
struct dev_ext_attribute *event_ea;
+ atomic_t active_cnt;
};
/**
diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c
b/drivers/hwtracing/coresight/coresight-syscfg.c
index a070f135eca3..d79cf5b36758 100644
--- a/drivers/hwtracing/coresight/coresight-syscfg.c
+++ b/drivers/hwtracing/coresight/coresight-syscfg.c
@@ -298,6 +298,7 @@ static int cscfg_load_config(struct cscfg_config_desc
*cfg_desc)
return err;
list_add(&cfg_desc->item, &cscfg_mgr->data.config_desc_list);
+ atomic_set(&cfg_desc->active_cnt, 0);
return 0;
}
@@ -477,6 +478,131 @@ void cscfg_unregister_csdev(struct coresight_device
*csdev)
}
EXPORT_SYMBOL_GPL(cscfg_unregister_csdev);
+void cscfg_csdev_reset_feats(struct coresight_device *csdev)
+{
+ struct cscfg_feature_csdev *feat;
+
+ mutex_lock(&cscfg_csdev_mutex);
+ if (list_empty(&csdev->feature_csdev_list))
+ goto unlock_exit;
+
+ list_for_each_entry(feat, &csdev->feature_csdev_list, node)
+ cscfg_reset_feat(feat);
+
+unlock_exit:
+ mutex_unlock(&cscfg_csdev_mutex);
+}
+EXPORT_SYMBOL_GPL(cscfg_csdev_reset_feats);
+
+/**
+ * Mark a config descriptor as active.
+ * This will be seen when csdev devices are activated in the system.
+ *
+ * Selection by hash value - generated from the configuration name when it
+ * was loaded and added to the cs_etm/configurations file system for selection
+ * by perf.
+ *
+ * @cfg_hash: Hash value of the selected configuration name.
+ */
+int cscfg_activate_config(unsigned long cfg_hash)
+{
+ struct cscfg_config_desc *curr_item, *match_item = 0;
+
+ mutex_lock(&cscfg_mutex);
+
+ list_for_each_entry(curr_item, &cscfg_mgr->data.config_desc_list, item)
{
+ if ((unsigned long)curr_item->id_ea->var == cfg_hash) {
+ match_item = curr_item;
+ atomic_inc(&cscfg_mgr->data.sys_active_cnt);
+ break;
+ }
+ }
+ mutex_unlock(&cscfg_mutex);
+
+ if (!match_item)
+ return -EINVAL;
+
+ dev_dbg(to_device_cscfg(), "Activate config %s.\n", match_item->name);
+
+ /* mark the descriptors as active so enable config will use them */
+ mutex_lock(&cscfg_csdev_mutex);
+ atomic_inc(&match_item->active_cnt);
+ mutex_unlock(&cscfg_csdev_mutex);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(cscfg_activate_config);
+
+void cscfg_deactivate_config(unsigned long cfg_hash)
+{
+ struct cscfg_config_desc *curr_item, *match_item = 0;
+
+ mutex_lock(&cscfg_mutex);
+
+ list_for_each_entry(curr_item, &cscfg_mgr->data.config_desc_list, item)
{
+ if ((unsigned long)curr_item->id_ea->var == cfg_hash) {
+ match_item = curr_item;
+ break;
+ }
+ }
+ mutex_unlock(&cscfg_mutex);
+ if (!match_item)
+ return;
+
+ dev_dbg(to_device_cscfg(), "Deactivate config %s.\n", match_item->name);
+
+ mutex_lock(&cscfg_csdev_mutex);
+ atomic_dec(&match_item->active_cnt);
+ mutex_unlock(&cscfg_csdev_mutex);
+
+ atomic_dec(&cscfg_mgr->data.sys_active_cnt);
+}
+EXPORT_SYMBOL_GPL(cscfg_deactivate_config);
+
+/* Find and program any active config for the supplied device.*/
+int cscfg_csdev_enable_active_config(struct coresight_device *csdev,
+unsigned long id_hash, int preset)
+{
+ struct cscfg_config_csdev *cfg = NULL, *item;
+ con
[PATCH v4 06/10] coresight: etm-perf: Update to activate selected configuration
Add calls to activate the selected configuration as perf starts
and stops the tracing session.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 14 +-
drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c
b/drivers/hwtracing/coresight/coresight-etm-perf.c
index e270bb1e0f7d..5c1aeddabc59 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -178,6 +178,10 @@ static void free_event_data(struct work_struct *work)
/* Free the sink buffers, if there are any */
free_sink_buffer(event_data);
+ /* clear any configuration we were using */
+ if (event_data->config_id_hash)
+ cscfg_deactivate_config(event_data->config_id_hash);
+
for_each_cpu(cpu, mask) {
struct list_head **ppath;
@@ -236,7 +240,7 @@ static void etm_free_aux(void *data)
static void *etm_setup_aux(struct perf_event *event, void **pages,
int nr_pages, bool overwrite)
{
- u32 id;
+ u32 id, config_id;
int cpu = event->cpu;
cpumask_t *mask;
struct coresight_device *sink = NULL;
@@ -253,6 +257,14 @@ static void *etm_setup_aux(struct perf_event *event, void
**pages,
sink = coresight_get_sink_by_id(id);
}
+ /* check if user wants a coresight configuration selected */
+ config_id = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32);
+ if (config_id) {
+ if (cscfg_activate_config(config_id))
+ goto err;
+ event_data->config_id_hash = config_id;
+ }
+
mask = &event_data->mask;
/*
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h
b/drivers/hwtracing/coresight/coresight-etm-perf.h
index 3646a3837a0b..751d768939d8 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.h
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.h
@@ -49,12 +49,14 @@ struct etm_filters {
* @work: Handle to free allocated memory outside IRQ context.
* @mask: Hold the CPU(s) this event was set for.
* @snk_config:The sink configuration.
+ * @config_id_hash:The id of any coresight config selected.
* @path: An array of path, each slot for one CPU.
*/
struct etm_event_data {
struct work_struct work;
cpumask_t mask;
void *snk_config;
+ u32 config_id_hash;
struct list_head * __percpu *path;
};
--
2.17.1
[PATCH v4 09/10] coresight: syscfg: Add initial configfs support
Adds configfs subsystem and attributes to the configuration manager
to enable the listing of loaded configurations and features.
The default values of feature parameters can be accessed and altered
from these attributes to affect all installed devices using the feature.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../hwtracing/coresight/coresight-config.c| 1 +
.../coresight/coresight-syscfg-configfs.c | 399 ++
.../coresight/coresight-syscfg-configfs.h | 45 ++
.../hwtracing/coresight/coresight-syscfg.c| 77
.../hwtracing/coresight/coresight-syscfg.h| 7 +
6 files changed, 531 insertions(+), 1 deletion(-)
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.c
create mode 100644 drivers/hwtracing/coresight/coresight-syscfg-configfs.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index 2707bfef1b76..391c93a08902 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -5,7 +5,8 @@
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
coresight-sysfs.o coresight-syscfg.o coresight-config.o \
- coresight-cfg-preload.o coresight-cfg-afdo.o
+ coresight-cfg-preload.o coresight-cfg-afdo.o \
+ coresight-syscfg-configfs.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-config.c
b/drivers/hwtracing/coresight/coresight-config.c
index 6cc4b213d9b6..225ceca1428c 100644
--- a/drivers/hwtracing/coresight/coresight-config.c
+++ b/drivers/hwtracing/coresight/coresight-config.c
@@ -243,3 +243,4 @@ void cscfg_csdev_disable_config(struct cscfg_config_csdev
*cfg)
cfg->enabled = false;
}
}
+
diff --git a/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
new file mode 100644
index ..79a11ebd6782
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Linaro Limited, All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include
+
+#include "coresight-syscfg-configfs.h"
+
+/* create a default ci_type. */
+static inline struct config_item_type *cscfg_create_ci_type(void)
+{
+ struct config_item_type *ci_type;
+
+ ci_type = devm_kzalloc(to_device_cscfg(), sizeof(*ci_type), GFP_KERNEL);
+ if (ci_type)
+ ci_type->ct_owner = THIS_MODULE;
+
+ return ci_type;
+}
+
+/* configurations sub-group */
+
+/* attributes for the config view group */
+static ssize_t cscfg_cfg_description_show(struct config_item *item, char *page)
+{
+ struct cscfg_fs_config *fs_config = container_of(to_config_group(item),
+struct
cscfg_fs_config, group);
+
+ return scnprintf(page, PAGE_SIZE, "%s\n", fs_config->desc->brief);
+}
+CONFIGFS_ATTR_RO(cscfg_cfg_, description);
+
+static ssize_t cscfg_cfg_feature_refs_show(struct config_item *item, char
*page)
+{
+ struct cscfg_fs_config *fs_config = container_of(to_config_group(item),
+struct
cscfg_fs_config, group);
+ const struct cscfg_config_desc *desc = fs_config->desc;
+ ssize_t ch_used = 0;
+ int i;
+
+ if (desc->nr_refs) {
+ for (i = 0; i < desc->nr_refs; i++) {
+ ch_used += scnprintf(page + ch_used, PAGE_SIZE -
ch_used,
+"%s\n", desc->refs[i].name);
+ }
+ }
+ return ch_used;
+}
+CONFIGFS_ATTR_RO(cscfg_cfg_, feature_refs);
+
+/* list preset values in order of features and params */
+static ssize_t cscfg_cfg_values_show(struct config_item *item, char *page)
+{
+ const struct cscfg_feature_desc *feat;
+ const struct cscfg_config_desc *cfg;
+ struct cscfg_fs_preset *fs_preset;
+ int i, j, val_idx, preset_idx;
+ ssize_t used = 0;
+
+ fs_preset = container_of(to_config_group(item), struct cscfg_fs_preset,
group);
+ cfg = fs_preset->desc;
+
+ if (!cfg->nr_presets)
+ return 0;
+
+ preset_idx = fs_preset->preset_num - 1;
+
+ /* start index on the correct array line */
+ val_idx = cfg->nr_total_params * preset_idx;
+
+ /*
+* A set of presets is the sum of all params in used features,
+* in order of declaration of features and params in the features
+*/
+ for (i = 0; i < cfg->nr_refs; i++) {
+ feat = cscfg_get_named_feat_
[PATCH v4 07/10] coresight: etm4x: Add complex configuration handlers to etmv4
Adds in handlers to allow the ETMv4 to use the complex configuration
support. Features and configurations can be loaded and selected in the
device.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 3 +-
.../hwtracing/coresight/coresight-etm4x-cfg.c | 184 ++
.../hwtracing/coresight/coresight-etm4x-cfg.h | 29 +++
.../coresight/coresight-etm4x-core.c | 38 +++-
.../coresight/coresight-etm4x-sysfs.c | 3 +
5 files changed, 254 insertions(+), 3 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.c
create mode 100644 drivers/hwtracing/coresight/coresight-etm4x-cfg.h
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index daad9f103a78..ea544206204d 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -16,7 +16,8 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o
coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \
coresight-etm3x-sysfs.o
obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o
-coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o
+coresight-etm4x-y := coresight-etm4x-core.o coresight-etm4x-sysfs.o \
+ coresight-etm4x-cfg.o
obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
new file mode 100644
index ..f237a8d02360
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2020 Linaro Limited. All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include "coresight-etm4x.h"
+#include "coresight-etm4x-cfg.h"
+#include "coresight-priv.h"
+#include "coresight-syscfg.h"
+
+/**
+ * etm4_cfg_map_reg_offset - validate and map the register offset into a
+ * location in the driver config struct.
+ *
+ * Limits the number of registers that can be accessed and programmed in
+ * features, to those which are used to control the trace capture parameters.
+ *
+ * Omits or limits access to those which the driver must use exclusively.
+ *
+ * Invalid offsets will result in fail code return and feature load failure.
+ *
+ * @drvdata: driver data to map into.
+ * @reg: register to map.
+ * @offset:device offset for the register
+ */
+static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
+ struct cscfg_reg_csdev *reg, u32 offset)
+{
+ int err = -EINVAL, idx;
+ struct etmv4_config *drvcfg = &drvdata->config;
+ u32 off_mask;
+
+#define CHECKREG(cval, elem) \
+ { \
+ if (offset == cval) { \
+ reg->drv_store = &drvcfg->elem; \
+ err = 0; \
+ break; \
+ } \
+ }
+
+#define CHECKREGIDX(cval, elem, off_idx, mask) \
+ { \
+ if (mask == cval) { \
+ reg->drv_store = &drvcfg->elem[off_idx]; \
+ err = 0; \
+ break; \
+ } \
+ }
+
+ if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) ||
+ ((offset >= TRCSEQRSTEVR) && (offset <= TRCEXTINSELR)) ||
+ ((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) {
+ do {
+ CHECKREG(TRCEVENTCTL0R, eventctrl0);
+ CHECKREG(TRCEVENTCTL1R, eventctrl1);
+ CHECKREG(TRCSTALLCTLR, stall_ctrl);
+ CHECKREG(TRCTSCTLR, ts_ctrl);
+ CHECKREG(TRCSYNCPR, syncfreq);
+ CHECKREG(TRTLR, ccctlr);
+ CHECKREG(TRCBBCTLR, bb_ctrl);
+ CHECKREG(TRCVICTLR, vinst_ctrl);
+ CHECKREG(TRCVIIECTLR, viiectlr);
+ CHECKREG(TRCVISSCTLR, vissctlr);
+ CHECKREG(TRCVIPCSSCTLR, vipcssctlr);
+ CHECKREG(TRCSEQRSTEVR, seq_rst);
+ CHECKREG(TRCSEQSTR, seq_state);
+ CHECKREG(TRCEXTINSELR, ext_inp);
+ CHECKREG(TRCCIDCCTLR0, ctxid_mask0);
+ CHECKREG(TRCCIDCCTLR1, ctxid_mask1);
+ CHECKREG(TRCVMIDCCTLR0, vmid_mask0);
+ CHECKREG(TRCVMIDCCTLR1, vmid_mask1);
+ } while (0);
+ } else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) {
+ /* sequencer state control registers */
+ idx = (offset & GENMASK(3, 0)) / 4;
+ if (idx <
[PATCH v4 03/10] coresight: config: Add configuration and feature generic functions
Adds a set of generic support functions that allow devices to set and save
features values on the device, and enable and disable configurations.
Additional functions for other common operations including feature
reset.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 2 +-
.../hwtracing/coresight/coresight-config.c| 245 ++
.../hwtracing/coresight/coresight-config.h| 14 +-
.../hwtracing/coresight/coresight-syscfg.c| 5 +-
4 files changed, 262 insertions(+), 4 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-config.c
diff --git a/drivers/hwtracing/coresight/Makefile
b/drivers/hwtracing/coresight/Makefile
index 4ce854c434b1..daad9f103a78 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -4,7 +4,7 @@
#
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
- coresight-sysfs.o coresight-syscfg.o
+ coresight-sysfs.o coresight-syscfg.o coresight-config.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
coresight-tmc-etr.o
diff --git a/drivers/hwtracing/coresight/coresight-config.c
b/drivers/hwtracing/coresight/coresight-config.c
new file mode 100644
index ..6cc4b213d9b6
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-config.c
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2020 Linaro Limited. All rights reserved.
+ * Author: Mike Leach
+ */
+
+#include
+#include "coresight-config.h"
+#include "coresight-priv.h"
+
+/*
+ * Write the value held in the register structure into the driver internal
memory
+ * location.
+ */
+static void cscfg_set_reg(struct cscfg_reg_csdev *reg)
+{
+ u32 *p_val32 = (u32 *)reg->drv_store;
+ u32 tmp32 = reg->value.val32;
+
+ if (reg->value.type & CS_CFG_REG_TYPE_VAL_64BIT) {
+ *((u64 *)reg->drv_store) = reg->value.val64;
+ return;
+ }
+
+ if (reg->value.type & CS_CFG_REG_TYPE_VAL_MASK) {
+ tmp32 = *p_val32;
+ tmp32 &= ~reg->value.mask32;
+ tmp32 |= reg->value.val32 & reg->value.mask32;
+ }
+ *p_val32 = tmp32;
+}
+
+/*
+ * Read the driver value into the reg if this is marked as one we want to save.
+ */
+static void cscfg_save_reg(struct cscfg_reg_csdev *reg)
+{
+ if (!(reg->value.type & CS_CFG_REG_TYPE_VAL_SAVE))
+ return;
+ if (reg->value.type & CS_CFG_REG_TYPE_VAL_64BIT)
+ reg->value.val64 = *(u64 *)(reg->drv_store);
+ else
+ reg->value.val32 = *(u32 *)(reg->drv_store);
+}
+
+static void cscfg_init_reg_param(struct cscfg_parameter_csdev *param_csdev,
+struct cscfg_reg_csdev *reg_csdev)
+{
+ param_csdev->reg = reg_csdev;
+ param_csdev->val64 = reg_csdev->value.type & CS_CFG_REG_TYPE_VAL_64BIT;
+
+ if (param_csdev->val64)
+ param_csdev->reg->value.val64 = param_csdev->current_value;
+ else
+ param_csdev->reg->value.val32 = (u32)param_csdev->current_value;
+}
+
+/* set values into the driver locations referenced in cscfg_reg_csdev */
+static int cscfg_set_on_enable(struct cscfg_feature_csdev *feat)
+{
+ int i;
+
+ spin_lock(feat->csdev_spinlock);
+ for (i = 0; i < feat->nr_regs; i++)
+ cscfg_set_reg(&feat->regs[i]);
+ spin_unlock(feat->csdev_spinlock);
+ dev_dbg(&feat->csdev->dev, "Feature %s: %s", feat->desc->name, "set on
enable");
+ return 0;
+}
+
+/* copy back values from the driver locations referenced in cscfg_reg_csdev */
+static void cscfg_save_on_disable(struct cscfg_feature_csdev *feat)
+{
+ int i;
+
+ spin_lock(feat->csdev_spinlock);
+ for (i = 0; i < feat->nr_regs; i++)
+ cscfg_save_reg(&feat->regs[i]);
+ spin_unlock(feat->csdev_spinlock);
+ dev_dbg(&feat->csdev->dev, "Feature %s: %s", feat->desc->name, "save on
disable");
+}
+
+/* default reset - restore default values */
+void cscfg_reset_feat(struct cscfg_feature_csdev *feat)
+{
+ struct cscfg_parameter_csdev *param_csdev;
+ struct cscfg_regval_desc *reg_desc;
+ struct cscfg_reg_csdev *reg_csdev;
+ int i;
+
+ /*
+* set the default values for all parameters and regs from the
+* relevant static descriptors.
+*/
+ for (i = 0; i < feat->nr_params; i++)
+ feat->params[i].current_value = feat->desc->params[i].value;
+
+ for (i = 0; i < feat->nr_regs; i++) {
+
