[PATCH v3 2/5] arm64: tegra: Specify sdhci clock parent for Tegra194 SDMMC1 and SDMMC3
Use PLLC4_MUXED as clock source for SDMMC1 and SDMMC3 core clocks. This enables more suitable interface clocks for higher data rate modes. Signed-off-by: Tamás Szűcs --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 058fdb1ffa1a..7e3ceeb5bc43 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -701,6 +701,9 @@ clocks = < TEGRA194_CLK_SDMMC1>, < TEGRA194_CLK_SDMMC_LEGACY_TM>; clock-names = "sdhci", "tmclk"; + assigned-clocks = < TEGRA194_CLK_SDMMC1>, + < TEGRA194_CLK_PLLC4_MUXED>; + assigned-clock-parents = < TEGRA194_CLK_PLLC4_MUXED>; resets = < TEGRA194_RESET_SDMMC1>; reset-names = "sdhci"; interconnects = < TEGRA194_MEMORY_CLIENT_SDMMCRA >, @@ -739,6 +742,9 @@ clocks = < TEGRA194_CLK_SDMMC3>, < TEGRA194_CLK_SDMMC_LEGACY_TM>; clock-names = "sdhci", "tmclk"; + assigned-clocks = < TEGRA194_CLK_SDMMC3>, + < TEGRA194_CLK_PLLC4_MUXED>; + assigned-clock-parents = < TEGRA194_CLK_PLLC4_MUXED>; resets = < TEGRA194_RESET_SDMMC3>; reset-names = "sdhci"; interconnects = < TEGRA194_MEMORY_CLIENT_SDMMCR >, -- 2.20.1
[PATCH v3 1/5] arm64: tegra: Enable signal voltage switching on Tegra194 SDMMC1 and SDMMC3
Add pad voltage configuration nodes for SDMMC pads with configurable voltages
and enable supported SD card, SDIO and eMMC modes.
Signed-off-by: Tamás Szűcs
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 45
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index e9c90f0f44ff..058fdb1ffa1a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -4,6 +4,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -705,6 +706,9 @@
interconnects = < TEGRA194_MEMORY_CLIENT_SDMMCRA
>,
< TEGRA194_MEMORY_CLIENT_SDMMCWA
>;
interconnect-names = "dma-mem", "write";
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+ pinctrl-0 = <_3v3>;
+ pinctrl-1 = <_1v8>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -716,6 +720,15 @@
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
nvidia,default-tap = <0x9>;
nvidia,default-trim = <0x5>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ cap-sdio-irq;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
status = "disabled";
};
@@ -731,6 +744,9 @@
interconnects = < TEGRA194_MEMORY_CLIENT_SDMMCR
>,
< TEGRA194_MEMORY_CLIENT_SDMMCW
>;
interconnect-names = "dma-mem", "write";
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+ pinctrl-0 = <_3v3>;
+ pinctrl-1 = <_1v8>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -743,6 +759,15 @@
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
nvidia,default-tap = <0x9>;
nvidia,default-trim = <0x5>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ cap-sdio-irq;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
status = "disabled";
};
@@ -1269,6 +1294,26 @@
#interrupt-cells = <2>;
interrupt-controller;
+
+ sdmmc1_3v3: sdmmc1-3v3 {
+ pins = "sdmmc1-hv";
+ power-source = ;
+ };
+
+ sdmmc1_1v8: sdmmc1-1v8 {
+ pins = "sdmmc1-hv";
+ power-source = ;
+ };
+
+ sdmmc3_3v3: sdmmc3-3v3 {
+ pins = "sdmmc3-hv";
+ power-source = ;
+ };
+
+ sdmmc3_1v8: sdmmc3-1v8 {
+ pins = "sdmmc3-hv";
+ power-source = ;
+ };
};
host1x@13e0 {
--
2.20.1
[PATCH v3 3/5] arm64: tegra: Fix CD on Jetson AGX Xavier SDMMC1
Change GPIO used for card detection on SDMMC1. Also, specify bus width and
disable write protect while at it.
Signed-off-by: Tamás Szűcs
---
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index d71b7a1140fe..31b5f00a7547 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -75,7 +75,9 @@
/* SDMMC1 (SD/MMC) */
mmc@340 {
- cd-gpios = < TEGRA194_MAIN_GPIO(A, 0)
GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ cd-gpios = < TEGRA194_MAIN_GPIO(G, 7)
GPIO_ACTIVE_LOW>;
+ disable-wp;
};
/* SDMMC4 (eMMC) */
--
2.20.1
[PATCH v3 4/5] arm64: tegra: Add vmmc-supply regulator for Jetson AGX Xavier SDMMC1
Create regulator for VDD_3V3_SD and add it to SDMMC1. When vmmc-supply is
undefined the initialization sequence specified in aliases is disregarded.
Signed-off-by: Tamás Szűcs
---
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index 31b5f00a7547..604a2c8a7478 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -78,6 +78,8 @@
bus-width = <4>;
cd-gpios = < TEGRA194_MAIN_GPIO(G, 7)
GPIO_ACTIVE_LOW>;
disable-wp;
+
+ vmmc-supply = <_3v3_sd>;
};
/* SDMMC4 (eMMC) */
@@ -356,4 +358,14 @@
gpio = < TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ vdd_3v3_sd: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_3V3_SD";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ enable-active-high;
+ };
};
--
2.20.1
[PATCH v3 5/5] arm64: tegra: Configure SDIO cards on Jetson AGX Xavier SDMMC1
Preserve SDIO card power during suspend/resume cycles and enable waking up the host system on SDIO IRQ assertion. Signed-off-by: Tamás Szűcs --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 604a2c8a7478..e3098b1555bc 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -78,6 +78,8 @@ bus-width = <4>; cd-gpios = < TEGRA194_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>; disable-wp; + keep-power-in-suspend; + wakeup-source; vmmc-supply = <_3v3_sd>; }; -- 2.20.1
[PATCH v3 0/5] arm64: tegra: Xavier SDMMC changes
Upstream Xavier SDMMC needs some love. I've been able to test with a Jetson AGX Xavier. Changes here work for me with 1.8 V and 3.3 V SD and SDIO devices. Changes in v3: - I started seeing ocasional eMMC init timeouts on cold starts when HS400 is enabled, so drop this until fix is found - add missing vmmc-supply regulator for SDMMC1 - specify bus width and disable WP for SDMMC1 - specify primary clock source for SDMMC1 and SDMMC3 Changes in v2: - fix board name in commit messages - rebase on for-next Kind regards, Tamas Tamás Szűcs (5): arm64: tegra: Enable signal voltage switching on Tegra194 SDMMC1 and SDMMC3 arm64: tegra: Specify sdhci clock parent for Tegra194 SDMMC1 and SDMMC3 arm64: tegra: Fix CD on Jetson AGX Xavier SDMMC1 arm64: tegra: Add vmmc-supply regulator for Jetson AGX Xavier SDMMC1 arm64: tegra: Configure SDIO cards on Jetson AGX Xavier SDMMC1 .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 18 ++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 51 +++ 2 files changed, 68 insertions(+), 1 deletion(-) -- 2.20.1
[PATCH] Bluetooth: btmrvl: eliminate duplicates introducing btmrvl_reg_89xx
SD89xx devices use identical card register settings. Make sure a single common
instance is used to describe them.
Signed-off-by: Tamás Szűcs
---
drivers/bluetooth/btmrvl_sdio.c | 54 +++--
1 file changed, 4 insertions(+), 50 deletions(-)
diff --git a/drivers/bluetooth/btmrvl_sdio.c b/drivers/bluetooth/btmrvl_sdio.c
index cfb9f9db44a0..92b28ff331b4 100644
--- a/drivers/bluetooth/btmrvl_sdio.c
+++ b/drivers/bluetooth/btmrvl_sdio.c
@@ -215,30 +215,7 @@ static const struct btmrvl_sdio_card_reg btmrvl_reg_8897 =
{
.fw_dump_end = 0xea,
};
-static const struct btmrvl_sdio_card_reg btmrvl_reg_8977 = {
- .cfg = 0x00,
- .host_int_mask = 0x08,
- .host_intstatus = 0x0c,
- .card_status = 0x5c,
- .sq_read_base_addr_a0 = 0xf8,
- .sq_read_base_addr_a1 = 0xf9,
- .card_revision = 0xc8,
- .card_fw_status0 = 0xe8,
- .card_fw_status1 = 0xe9,
- .card_rx_len = 0xea,
- .card_rx_unit = 0xeb,
- .io_port_0 = 0xe4,
- .io_port_1 = 0xe5,
- .io_port_2 = 0xe6,
- .int_read_to_clear = true,
- .host_int_rsr = 0x04,
- .card_misc_cfg = 0xD8,
- .fw_dump_ctrl = 0xf0,
- .fw_dump_start = 0xf1,
- .fw_dump_end = 0xf8,
-};
-
-static const struct btmrvl_sdio_card_reg btmrvl_reg_8987 = {
+static const struct btmrvl_sdio_card_reg btmrvl_reg_89xx = {
.cfg = 0x00,
.host_int_mask = 0x08,
.host_intstatus = 0x0c,
@@ -261,29 +238,6 @@ static const struct btmrvl_sdio_card_reg btmrvl_reg_8987 =
{
.fw_dump_end = 0xf8,
};
-static const struct btmrvl_sdio_card_reg btmrvl_reg_8997 = {
- .cfg = 0x00,
- .host_int_mask = 0x08,
- .host_intstatus = 0x0c,
- .card_status = 0x5c,
- .sq_read_base_addr_a0 = 0xf8,
- .sq_read_base_addr_a1 = 0xf9,
- .card_revision = 0xc8,
- .card_fw_status0 = 0xe8,
- .card_fw_status1 = 0xe9,
- .card_rx_len = 0xea,
- .card_rx_unit = 0xeb,
- .io_port_0 = 0xe4,
- .io_port_1 = 0xe5,
- .io_port_2 = 0xe6,
- .int_read_to_clear = true,
- .host_int_rsr = 0x04,
- .card_misc_cfg = 0xD8,
- .fw_dump_ctrl = 0xf0,
- .fw_dump_start = 0xf1,
- .fw_dump_end = 0xf8,
-};
-
static const struct btmrvl_sdio_device btmrvl_sdio_sd8688 = {
.helper = "mrvl/sd8688_helper.bin",
.firmware = "mrvl/sd8688.bin",
@@ -332,7 +286,7 @@ static const struct btmrvl_sdio_device btmrvl_sdio_sd8897 =
{
static const struct btmrvl_sdio_device btmrvl_sdio_sd8977 = {
.helper = NULL,
.firmware = "mrvl/sdsd8977_combo_v2.bin",
- .reg= _reg_8977,
+ .reg= _reg_89xx,
.support_pscan_win_report = true,
.sd_blksz_fw_dl = 256,
.supports_fw_dump = true,
@@ -341,7 +295,7 @@ static const struct btmrvl_sdio_device btmrvl_sdio_sd8977 =
{
static const struct btmrvl_sdio_device btmrvl_sdio_sd8987 = {
.helper = NULL,
.firmware = "mrvl/sd8987_uapsta.bin",
- .reg= _reg_8987,
+ .reg= _reg_89xx,
.support_pscan_win_report = true,
.sd_blksz_fw_dl = 256,
.supports_fw_dump = true,
@@ -350,7 +304,7 @@ static const struct btmrvl_sdio_device btmrvl_sdio_sd8987 =
{
static const struct btmrvl_sdio_device btmrvl_sdio_sd8997 = {
.helper = NULL,
.firmware = "mrvl/sdsd8997_combo_v4.bin",
- .reg= _reg_8997,
+ .reg= _reg_89xx,
.support_pscan_win_report = true,
.sd_blksz_fw_dl = 256,
.supports_fw_dump = true,
--
2.20.1
[PATCH v2 3/4] arm64: tegra: Configure SDIO cards on Jetson AGX Xavier SDMMC1
Preserve SDIO card power during a suspend/resume cycle and enable wake up of
host system on SDIO IRQ assertion.
Signed-off-by: Tamás Szűcs
---
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index 6c4a19cee34c..156e961a4557 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -60,6 +60,8 @@
/* SDMMC1 (SD/MMC) */
mmc@340 {
cd-gpios = < TEGRA194_MAIN_GPIO(G, 7)
GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ wakeup-source;
};
/* SDMMC4 (eMMC) */
--
2.20.1
[PATCH v2 0/4] arm64: tegra: Xavier SDMMC changes
It turns out uSD card detection on the Jetson AGX Xavier is not working and I/Os are limited to 3.3 V. SDIO is supported but not enabled. Also, the on-board eMMC module is using HS200 only. Changes in v2: - fix board name in commit messages - rebase on for-next Kind regards, Tamas Tamás Szűcs (4): arm64: tegra: Enable signal voltage switching on Tegra194 SDMMC1 and SDMMC3 arm64: tegra: Fix CD on Jetson AGX Xavier SDMMC1 arm64: tegra: Configure SDIO cards on Jetson AGX Xavier SDMMC1 arm64: tegra: Enable HS400 on Tegra194 SDMMC4 .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 46 +++ 2 files changed, 49 insertions(+), 1 deletion(-) -- 2.20.1
[PATCH v2 2/4] arm64: tegra: Fix CD on Jetson AGX Xavier SDMMC1
Change GPIO used for card detection on SDMMC1.
Signed-off-by: Tamás Szűcs
---
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index 4c005b811233..6c4a19cee34c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -59,7 +59,7 @@
/* SDMMC1 (SD/MMC) */
mmc@340 {
- cd-gpios = < TEGRA194_MAIN_GPIO(A, 0)
GPIO_ACTIVE_LOW>;
+ cd-gpios = < TEGRA194_MAIN_GPIO(G, 7)
GPIO_ACTIVE_LOW>;
};
/* SDMMC4 (eMMC) */
--
2.20.1
[PATCH v2 4/4] arm64: tegra: Enable HS400 on Tegra194 SDMMC4
Enable HS400 signaling on Tegra194 SDMMC4 controller. Signed-off-by: Tamás Szűcs --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 8351035bb6a7..e26f35b6279b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -558,6 +558,7 @@ nvidia,default-tap = <0x8>; nvidia,default-trim = <0x14>; nvidia,dqs-trim = <40>; + mmc-hs400-1_8v; supports-cqe; status = "disabled"; }; -- 2.20.1
[PATCH v2 1/4] arm64: tegra: Enable signal voltage switching on Tegra194 SDMMC1 and SDMMC3
Add pad voltage configuration nodes for SDMMC pads with configurable voltages
and enable supported SD card, SDIO and eMMC modes.
Signed-off-by: Tamás Szűcs
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 45
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 48160f48003a..8351035bb6a7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -4,6 +4,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -467,6 +468,9 @@
interconnects = < TEGRA194_MEMORY_CLIENT_SDMMCRA
>,
< TEGRA194_MEMORY_CLIENT_SDMMCWA
>;
interconnect-names = "dma-mem", "write";
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+ pinctrl-0 = <_3v3>;
+ pinctrl-1 = <_1v8>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -478,6 +482,15 @@
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
nvidia,default-tap = <0x9>;
nvidia,default-trim = <0x5>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ cap-sdio-irq;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
status = "disabled";
};
@@ -492,6 +505,9 @@
interconnects = < TEGRA194_MEMORY_CLIENT_SDMMCR
>,
< TEGRA194_MEMORY_CLIENT_SDMMCW
>;
interconnect-names = "dma-mem", "write";
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+ pinctrl-0 = <_3v3>;
+ pinctrl-1 = <_1v8>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -504,6 +520,15 @@
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
nvidia,default-tap = <0x9>;
nvidia,default-trim = <0x5>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ cap-sdio-irq;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
status = "disabled";
};
@@ -1029,6 +1054,26 @@
#interrupt-cells = <2>;
interrupt-controller;
+
+ sdmmc1_3v3: sdmmc1-3v3 {
+ pins = "sdmmc1-hv";
+ power-source = ;
+ };
+
+ sdmmc1_1v8: sdmmc1-1v8 {
+ pins = "sdmmc1-hv";
+ power-source = ;
+ };
+
+ sdmmc3_3v3: sdmmc3-3v3 {
+ pins = "sdmmc3-hv";
+ power-source = ;
+ };
+
+ sdmmc3_1v8: sdmmc3-1v8 {
+ pins = "sdmmc3-hv";
+ power-source = ;
+ };
};
host1x@13e0 {
--
2.20.1
[PATCH 1/4] arm64: tegra: Enable signal voltage switching on Tegra194 SDMMC1 and SDMMC3
Add pad voltage configuration nodes for SDMMC pads with configurable voltages
and enable supported SD card, SDIO and eMMC modes.
Signed-off-by: Tamás Szűcs
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 45
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 4bc187a4eacd..0a07930e68d1 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -4,6 +4,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -457,6 +458,9 @@
clock-names = "sdhci";
resets = < TEGRA194_RESET_SDMMC1>;
reset-names = "sdhci";
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+ pinctrl-0 = <_3v3>;
+ pinctrl-1 = <_1v8>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -468,6 +472,15 @@
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
nvidia,default-tap = <0x9>;
nvidia,default-trim = <0x5>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ cap-sdio-irq;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
status = "disabled";
};
@@ -479,6 +492,9 @@
clock-names = "sdhci";
resets = < TEGRA194_RESET_SDMMC3>;
reset-names = "sdhci";
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+ pinctrl-0 = <_3v3>;
+ pinctrl-1 = <_1v8>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -491,6 +507,15 @@
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
nvidia,default-tap = <0x9>;
nvidia,default-trim = <0x5>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ cap-sdio-irq;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
status = "disabled";
};
@@ -1014,6 +1039,26 @@
#interrupt-cells = <2>;
interrupt-controller;
+
+ sdmmc1_3v3: sdmmc1-3v3 {
+ pins = "sdmmc1-hv";
+ power-source = ;
+ };
+
+ sdmmc1_1v8: sdmmc1-1v8 {
+ pins = "sdmmc1-hv";
+ power-source = ;
+ };
+
+ sdmmc3_3v3: sdmmc3-3v3 {
+ pins = "sdmmc3-hv";
+ power-source = ;
+ };
+
+ sdmmc3_1v8: sdmmc3-1v8 {
+ pins = "sdmmc3-hv";
+ power-source = ;
+ };
};
host1x@13e0 {
--
2.20.1
[PATCH 4/4] arm64: tegra: Enable HS400 on Tegra194 SDMMC4
Enable HS400 signaling on Tegra194 SDMMC4 controller. Signed-off-by: Tamás Szűcs --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 0a07930e68d1..ecb47a534f54 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -542,6 +542,7 @@ nvidia,default-tap = <0x8>; nvidia,default-trim = <0x14>; nvidia,dqs-trim = <40>; + mmc-hs400-1_8v; supports-cqe; status = "disabled"; }; -- 2.20.1
[PATCH 3/4] arm64: tegra: Configure SDIO cards on Jetson Xavier SDMMC1
Preserve SDIO card power during a suspend/resume cycle and enable wake up of
host system on SDIO IRQ assertion.
Signed-off-by: Tamás Szűcs
---
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index 5c40e5c7ee9c..4cf3830e37c3 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -59,6 +59,8 @@
/* SDMMC1 (SD/MMC) */
sdhci@340 {
cd-gpios = < TEGRA194_MAIN_GPIO(G, 7)
GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ wakeup-source;
};
/* SDMMC4 (eMMC) */
--
2.20.1
[PATCH 0/4] arm64: tegra: Xavier SDMMC changes
Hi All, I've encountered some issues with the Xavier while integrating some of our SDIO modules. It turns out card detection was not working for the uSD socket and I/Os were limited to 3.3 V. Also, the on-board eMMC module was using HS200 only. I think it would make sense for the changes to go upstream. Please have a look. Kind regards, Tamas Tamás Szűcs (4): arm64: tegra: Enable signal voltage switching on Tegra194 SDMMC1 and SDMMC3 arm64: tegra: Fix CD on Jetson Xavier SDMMC1 arm64: tegra: Configure SDIO cards on Jetson Xavier SDMMC1 arm64: tegra: Enable HS400 on Tegra194 SDMMC4 .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 46 +++ 2 files changed, 49 insertions(+), 1 deletion(-) -- 2.20.1
[PATCH 2/4] arm64: tegra: Fix CD on Jetson Xavier SDMMC1
Change GPIO used for card detection on SDMMC1.
Signed-off-by: Tamás Szűcs
---
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index b96eb4e14556..5c40e5c7ee9c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -58,7 +58,7 @@
/* SDMMC1 (SD/MMC) */
sdhci@340 {
- cd-gpios = < TEGRA194_MAIN_GPIO(A, 0)
GPIO_ACTIVE_LOW>;
+ cd-gpios = < TEGRA194_MAIN_GPIO(G, 7)
GPIO_ACTIVE_LOW>;
};
/* SDMMC4 (eMMC) */
--
2.20.1
[PATCH 1/1] arm64: tegra: enable SDIO on Jetson Nano M.2 Key E
Enable SDMMC3 and set it up for SDIO devices.
Signed-off-by: Tamás Szűcs
---
arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts
b/arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts
index 9d17ec707bce..66f913ba0b1c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts
@@ -515,6 +515,16 @@
vmmc-supply = <_3v3_sd>;
};
+ sdhci@700b0400 {
+ status = "okay";
+ bus-width = <4>;
+ cap-sdio-irq;
+ non-removable;
+
+ vqmmc-supply = <_1v8>;
+ vmmc-supply = <_3v3_sys>;
+ };
+
clocks {
compatible = "simple-bus";
#address-cells = <1>;
--
2.20.1
[PATCH 0/1] arm64: tegra: enable SDIO on Jetson Nano M.2 Key E
Hi All, Changes here have been tested with various u-blox SDIO Wi-Fi modules. It would be great to have support upstream. Kind regards, Tamas Tamás Szűcs (1): arm64: tegra: enable SDIO on Jetson Nano M.2 Key E arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts | 10 ++ 1 file changed, 10 insertions(+) -- 2.20.1
[PATCH] arm64: tegra: enable PWM fan on Jetson Nano
Enable PWM fan and extend CPU thermal zones for monitoring and fan control.
This will trigger the PWM fan on J15 and cool down the system if necessary.
Signed-off-by: Tamás Szűcs
---
.../boot/dts/nvidia/tegra210-p3450-.dts | 64 +++
1 file changed, 64 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts
b/arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts
index 9d17ec707bce..43c3613e7217 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-.dts
@@ -552,6 +552,70 @@
};
};
+ fan: fan {
+ compatible = "pwm-fan";
+ pwms = < 3 45334>;
+
+ cooling-levels = <0 64 128 255>;
+ #cooling-cells = <2>;
+ };
+
+ thermal-zones {
+ cpu {
+ polling-delay = <0>;
+ polling-delay-passive = <500>;
+ status = "okay";
+
+ trips {
+ cpu_trip_critical: critical {
+ temperature = <96500>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ cpu_trip_hot: hot {
+ temperature = <7>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_trip_active: active {
+ temperature = <5>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_passive: passive {
+ temperature = <3>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu-critical {
+ cooling-device = < 3 3>;
+ trip = <_trip_critical>;
+ };
+
+ cpu-hot {
+ cooling-device = < 2 2>;
+ trip = <_trip_hot>;
+ };
+
+ cpu-active {
+ cooling-device = < 1 1>;
+ trip = <_trip_active>;
+ };
+
+ cpu-passive {
+ cooling-device = < 0 0>;
+ trip = <_trip_passive>;
+ };
+ };
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
--
2.20.1
Re: [PATCH v2] mmc: sdhi: fill in actual_clock
Hi Geert,
You are correct, there is no way to distinguish between the old and new kernels
just by mmc ios output when the bus is down. I don't think it's an issue. I
find it more helpful to have this information available.
Yes, actual_clock should only display when non-zero and it should be zero when
the bus is down. I fixed this in v2.
Kind regards,
Tamas
Tamás Szűcs
tsz...@protonmail.ch
‐‐‐ Original Message ‐‐‐
On Friday, August 30, 2019 9:21 AM, Geert Uytterhoeven
wrote:
> Hi Tamás,
>
> On Thu, Aug 29, 2019 at 8:37 PM Tamás Szűcs tsz...@protonmail.ch wrote:
>
> > Save set clock in mmc_host actual_clock enabling exporting it via debugfs.
> > This will indicate the precise SD clock in I/O settings rather than only the
> > sometimes misleading requested clock.
> > Signed-off-by: Tamás Szűcs tsz...@protonmail.ch
>
> Thanks for the update!
>
> Reviewed-by: Geert Uytterhoeven geert+rene...@glider.be
>
> However, one question below.
>
> > --- a/drivers/mmc/host/renesas_sdhi_core.c
> > +++ b/drivers/mmc/host/renesas_sdhi_core.c
> > @@ -166,10 +166,13 @@ static void renesas_sdhi_set_clock(struct
> > tmio_mmc_host *host,
> > sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
> > sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
> >
> > - if (new_clock == 0)
> >
> >
> >
> > - if (new_clock == 0) {
> >
> >
> > - host->mmc->actual_clock = 0;
> >
> >
>
> The actual clock is present in the debugfs output only when non-zero.
> Hence userspace cannot distinguish between an old kernel where the
> Renesas SDHI driver didn't fill in actual_clock, and a new kernel when
> the SDHI controller is powered down.
> Could that be an issue? Should the old value be retained?
> Probably it's OK, as this is debugfs, not an official ABI.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> ---
>
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
[PATCH v2] mmc: sdhi: fill in actual_clock
Save set clock in mmc_host actual_clock enabling exporting it via debugfs.
This will indicate the precise SD clock in I/O settings rather than only the
sometimes misleading requested clock.
Signed-off-by: Tamás Szűcs
---
drivers/mmc/host/renesas_sdhi_core.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/renesas_sdhi_core.c
b/drivers/mmc/host/renesas_sdhi_core.c
index 64d3b5fb7fe5..4c9774dbcfc1 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -124,7 +124,7 @@ static unsigned int renesas_sdhi_clk_update(struct
tmio_mmc_host *host,
{
struct renesas_sdhi *priv = host_to_priv(host);
unsigned int freq, diff, best_freq = 0, diff_min = ~0;
- int i, ret;
+ int i;
/* tested only on R-Car Gen2+ currently; may work for others */
if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
@@ -153,9 +153,9 @@ static unsigned int renesas_sdhi_clk_update(struct
tmio_mmc_host *host,
}
}
- ret = clk_set_rate(priv->clk, best_freq);
+ clk_set_rate(priv->clk, best_freq);
- return ret == 0 ? best_freq : clk_get_rate(priv->clk);
+ return clk_get_rate(priv->clk);
}
static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
@@ -166,10 +166,13 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host
*host,
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
- if (new_clock == 0)
+ if (new_clock == 0) {
+ host->mmc->actual_clock = 0;
goto out;
+ }
- clock = renesas_sdhi_clk_update(host, new_clock) / 512;
+ host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
+ clock = host->mmc->actual_clock / 512;
for (clk = 0x8080; new_clock >= (clock << 1); clk >>= 1)
clock <<= 1;
--
2.11.0
Re: [PATCH] mmc: sdhi: fill in actual_clock
Hi Geert,
It would be possible to call clk_get_rate() unconditionally but there's usually
no need, thus the ternary. Are you in favor of that though?
It turns out I need to send a followup to fix some glitches. Please stay tuned.
Kind regards,
Tamas
Tamás Szűcs
tsz...@protonmail.ch
‐‐‐ Original Message ‐‐‐
On Thursday, August 29, 2019 9:47 AM, Geert Uytterhoeven
wrote:
> Hi Tamás,
>
> On Wed, Aug 28, 2019 at 9:02 PM Tamás Szűcs tsz...@protonmail.ch wrote:
>
> > Save set clock in mmc_host actual_clock enabling exporting it via debugfs.
> > This will indicate the precise SD clock in I/O settings rather than only the
> > sometimes misleading requested clock.
> > Signed-off-by: Tamás Szűcs tsz...@protonmail.ch
>
> Thanks for your patch!
>
> > --- a/drivers/mmc/host/renesas_sdhi_core.c
> > +++ b/drivers/mmc/host/renesas_sdhi_core.c
> > @@ -124,7 +124,7 @@ static unsigned int renesas_sdhi_clk_update(struct
> > tmio_mmc_host *host,
> > {
> > struct renesas_sdhi *priv = host_to_priv(host);
> > unsigned int freq, diff, best_freq = 0, diff_min = ~0;
> >
> > - int i, ret;
> >
> >
> >
> > - int i;
> >
> > /* tested only on R-Car Gen2+ currently; may work for others */
> > if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
> >
> >
> >
> > @@ -153,9 +153,11 @@ static unsigned int renesas_sdhi_clk_update(struct
> > tmio_mmc_host *host,
> > }
> > }
> >
> > - ret = clk_set_rate(priv->clk, best_freq);
> >
> >
> >
> > - host->mmc->actual_clock =
> >
> >
> > - clk_set_rate(priv->clk, best_freq) == 0 ?
> >
> >
> > - best_freq : clk_get_rate(priv->clk);
> >
> >
>
> When clk_set_rate() returns 0 to indicate success, it may still have
> rounded the requested clock rate, no?
> So wouldn't it be better to always call clk_get_rate()?
>
> > - return ret == 0 ? best_freq : clk_get_rate(priv->clk);
> >
> >
> >
> > - return host->mmc->actual_clock;
> >
> >
> >
> > }
>
> Gr{oetje,eeting}s,
>
> Geert
>
>
>
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
> -- Linus Torvalds
[PATCH] mmc: sdhi: fill in actual_clock
Save set clock in mmc_host actual_clock enabling exporting it via debugfs.
This will indicate the precise SD clock in I/O settings rather than only the
sometimes misleading requested clock.
Signed-off-by: Tamás Szűcs
---
drivers/mmc/host/renesas_sdhi_core.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/renesas_sdhi_core.c
b/drivers/mmc/host/renesas_sdhi_core.c
index 64d3b5fb7fe5..ae842d0b59f9 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -124,7 +124,7 @@ static unsigned int renesas_sdhi_clk_update(struct
tmio_mmc_host *host,
{
struct renesas_sdhi *priv = host_to_priv(host);
unsigned int freq, diff, best_freq = 0, diff_min = ~0;
- int i, ret;
+ int i;
/* tested only on R-Car Gen2+ currently; may work for others */
if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
@@ -153,9 +153,11 @@ static unsigned int renesas_sdhi_clk_update(struct
tmio_mmc_host *host,
}
}
- ret = clk_set_rate(priv->clk, best_freq);
+ host->mmc->actual_clock =
+ clk_set_rate(priv->clk, best_freq) == 0 ?
+ best_freq : clk_get_rate(priv->clk);
- return ret == 0 ? best_freq : clk_get_rate(priv->clk);
+ return host->mmc->actual_clock;
}
static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
--
2.11.0
[PATCH 0/1] Bluetooth: btmrvl: add support for SD8987 chipset
Hi All, Changes here have been tested with u-blox JODY-W2XX and Marvell TB-AQB8987-QFN-EPA-2A. It would be great to have driver support upstream. Kindly review. Kind regards, Tamas Tamás Szűcs (1): Bluetooth: btmrvl: add support for SD8987 chipset drivers/bluetooth/Kconfig | 4 ++-- drivers/bluetooth/btmrvl_sdio.c | 36 2 files changed, 38 insertions(+), 2 deletions(-) -- 2.11.0
[PATCH 1/1] Bluetooth: btmrvl: add support for SD8987 chipset
This patch adds support for Marvell 88W8987 chipset with SDIO interface.
Register offsets and supported feature flags are updated. The corresponding
firmware image file shall be "mrvl/sd8987_uapsta.bin".
Signed-off-by: Tamás Szűcs
---
drivers/bluetooth/Kconfig | 4 ++--
drivers/bluetooth/btmrvl_sdio.c | 36
2 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig
index b0f9a20401d6..b9c34ff9a0d3 100644
--- a/drivers/bluetooth/Kconfig
+++ b/drivers/bluetooth/Kconfig
@@ -336,7 +336,7 @@ config BT_MRVL
The core driver to support Marvell Bluetooth devices.
This driver is required if you want to support
- Marvell Bluetooth devices, such as 8688/8787/8797/8887/8897/8977/8997.
+ Marvell Bluetooth devices, such as
8688/8787/8797/8887/8897/8977/8987/8997.
Say Y here to compile Marvell Bluetooth driver
into the kernel or say M to compile it as module.
@@ -350,7 +350,7 @@ config BT_MRVL_SDIO
The driver for Marvell Bluetooth chipsets with SDIO interface.
This driver is required if you want to use Marvell Bluetooth
- devices with SDIO interface. Currently
SD8688/SD8787/SD8797/SD8887/SD8897/SD8977/SD8997
+ devices with SDIO interface. Currently
SD8688/SD8787/SD8797/SD8887/SD8897/SD8977/SD8987/SD8997
chipsets are supported.
Say Y here to compile support for Marvell BT-over-SDIO driver
diff --git a/drivers/bluetooth/btmrvl_sdio.c b/drivers/bluetooth/btmrvl_sdio.c
index 047b75ce1deb..0f3a020703ab 100644
--- a/drivers/bluetooth/btmrvl_sdio.c
+++ b/drivers/bluetooth/btmrvl_sdio.c
@@ -235,6 +235,29 @@ static const struct btmrvl_sdio_card_reg btmrvl_reg_8977 =
{
.fw_dump_end = 0xf8,
};
+static const struct btmrvl_sdio_card_reg btmrvl_reg_8987 = {
+ .cfg = 0x00,
+ .host_int_mask = 0x08,
+ .host_intstatus = 0x0c,
+ .card_status = 0x5c,
+ .sq_read_base_addr_a0 = 0xf8,
+ .sq_read_base_addr_a1 = 0xf9,
+ .card_revision = 0xc8,
+ .card_fw_status0 = 0xe8,
+ .card_fw_status1 = 0xe9,
+ .card_rx_len = 0xea,
+ .card_rx_unit = 0xeb,
+ .io_port_0 = 0xe4,
+ .io_port_1 = 0xe5,
+ .io_port_2 = 0xe6,
+ .int_read_to_clear = true,
+ .host_int_rsr = 0x04,
+ .card_misc_cfg = 0xd8,
+ .fw_dump_ctrl = 0xf0,
+ .fw_dump_start = 0xf1,
+ .fw_dump_end = 0xf8,
+};
+
static const struct btmrvl_sdio_card_reg btmrvl_reg_8997 = {
.cfg = 0x00,
.host_int_mask = 0x08,
@@ -312,6 +335,15 @@ static const struct btmrvl_sdio_device btmrvl_sdio_sd8977
= {
.supports_fw_dump = true,
};
+static const struct btmrvl_sdio_device btmrvl_sdio_sd8987 = {
+ .helper = NULL,
+ .firmware = "mrvl/sd8987_uapsta.bin",
+ .reg= _reg_8987,
+ .support_pscan_win_report = true,
+ .sd_blksz_fw_dl = 256,
+ .supports_fw_dump = true,
+};
+
static const struct btmrvl_sdio_device btmrvl_sdio_sd8997 = {
.helper = NULL,
.firmware = "mrvl/sd8997_uapsta.bin",
@@ -343,6 +375,9 @@ static const struct sdio_device_id btmrvl_sdio_ids[] = {
/* Marvell SD8977 Bluetooth device */
{ SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, 0x9146),
.driver_data = (unsigned long)_sdio_sd8977 },
+ /* Marvell SD8987 Bluetooth device */
+ { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, 0x914A),
+ .driver_data = (unsigned long)_sdio_sd8987 },
/* Marvell SD8997 Bluetooth device */
{ SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, 0x9142),
.driver_data = (unsigned long)_sdio_sd8997 },
@@ -1797,4 +1832,5 @@ MODULE_FIRMWARE("mrvl/sd8797_uapsta.bin");
MODULE_FIRMWARE("mrvl/sd8887_uapsta.bin");
MODULE_FIRMWARE("mrvl/sd8897_uapsta.bin");
MODULE_FIRMWARE("mrvl/sd8977_uapsta.bin");
+MODULE_FIRMWARE("mrvl/sd8987_uapsta.bin");
MODULE_FIRMWARE("mrvl/sd8997_uapsta.bin");
--
2.11.0
[RESEND PATCH] mmc: tegra: enable ddr_signaling for MMC_TIMING_MMC_DDR52
This fixes sampling errors with eMMC modules using DDR52 when host capabilities via setting NVQUIRK_ENABLE_DDR50 and NVQUIRK_ENABLE_SDHCI_SPEC_300 are enabled. Signed-off-by: Tamás Szűcs --- drivers/mmc/host/sdhci-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 970d38f68939..a3bfaa7067c8 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -228,7 +228,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); - if (timing == MMC_TIMING_UHS_DDR50) + if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) tegra_host->ddr_signaling = true; sdhci_set_uhs_signaling(host, timing); -- 2.11.0
[RESEND PATCH] mmc: tegra: enable ddr_signaling for MMC_TIMING_MMC_DDR52
This fixes sampling errors with eMMC modules using DDR52 when host capabilities via setting NVQUIRK_ENABLE_DDR50 and NVQUIRK_ENABLE_SDHCI_SPEC_300 are enabled. Signed-off-by: Tamás Szűcs --- drivers/mmc/host/sdhci-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 970d38f68939..a3bfaa7067c8 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -228,7 +228,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); - if (timing == MMC_TIMING_UHS_DDR50) + if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) tegra_host->ddr_signaling = true; sdhci_set_uhs_signaling(host, timing); -- 2.11.0
