[PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree
Add Nuvoton NPCM730 SoC device tree.
The Nuvoton NPCN730 SoC is a part of the
Nuvoton NPCM7xx SoCs family.
Signed-off-by: Tomer Maimon
---
arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++
1 file changed, 44 insertions(+)
create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi
diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi
b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
new file mode 100644
index ..86ec12ec2b50
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2020 Nuvoton Technology
+
+#include "nuvoton-common-npcm7xx.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "nuvoton,npcm750-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = < NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <0>;
+ next-level-cache = <>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ clocks = < NPCM7XX_CLK_CPU>;
+ clock-names = "clk_cpu";
+ reg = <1>;
+ next-level-cache = <>;
+ };
+ };
+
+ soc {
+ timer@3fe600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x3fe600 0x20>;
+ interrupts = ;
+ clocks = < NPCM7XX_CLK_AHB>;
+ };
+ };
+};
--
2.22.0
[PATCH v8 4/5] arm: dts: add new device nodes to NPCM7XX device tree
Add the following new device nodes to NPCM7XX:
- NPCM7xx PWM and FAN.
- NPCM7xx EHCI USB.
- NPCM7xx KCS.
- NPCM Reset.
- NPCM Peripheral SPI.
- NPCM FIU SPI.
- NPCM HWRNG.
- NPCM I2C.
- STMicro STMMAC.
Signed-off-by: Tomer Maimon
Reviewed-by: Joel Stanley
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 382 +-
arch/arm/boot/dts/nuvoton-npcm750.dtsi| 18 +
2 files changed, 394 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 7755a3de7c53..3696980a3da1 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -4,6 +4,7 @@
#include
#include
+#include
/ {
#address-cells = <1>;
@@ -64,12 +65,6 @@
interrupt-parent = <>;
ranges = <0x0 0xf000 0x0090>;
- gcr: gcr@80 {
- compatible = "nuvoton,npcm750-gcr", "syscon",
- "simple-mfd";
- reg = <0x80 0x1000>;
- };
-
scu: scu@3fe000 {
compatible = "arm,cortex-a9-scu";
reg = <0x3fe000 0x1000>;
@@ -92,6 +87,16 @@
reg = <0x3ff000 0x1000>,
<0x3fe100 0x100>;
};
+
+ gcr: gcr@80 {
+ compatible = "nuvoton,npcm750-gcr", "syscon",
"simple-mfd";
+ reg = <0x80 0x1000>;
+ };
+
+ rst: rst@801000 {
+ compatible = "nuvoton,npcm750-rst", "syscon",
"simple-mfd";
+ reg = <0x801000 0x6C>;
+ };
};
ahb {
@@ -101,6 +106,12 @@
interrupt-parent = <>;
ranges;
+ rstc: rstc@f0801000 {
+ compatible = "nuvoton,npcm750-reset";
+ reg = <0xf0801000 0x70>;
+ #reset-cells = <2>;
+ };
+
clk: clock-controller@f0801000 {
compatible = "nuvoton,npcm750-clk", "syscon";
#clock-cells = <1>;
@@ -110,6 +121,63 @@
clocks = <_refclk>, <_sysbypck>, <_mcbypck>;
};
+ gmac0: eth@f0802000 {
+ device_type = "network";
+ compatible = "snps,dwmac";
+ reg = <0xf0802000 0x2000>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ ethernet = <0>;
+ clocks = <_rg1refck>, < NPCM7XX_CLK_AHB>;
+ clock-names = "stmmaceth", "clk_gmac";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins
+ _pins>;
+ status = "disabled";
+ };
+
+ ehci1: usb@f0806000 {
+ compatible = "nuvoton,npcm750-ehci";
+ reg = <0xf0806000 0x1000>;
+ interrupts = ;
+ status = "disabled";
+ };
+
+ fiu0: spi@fb00 {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfb00 0x1000>;
+ reg-names = "control", "memory";
+ clocks = < NPCM7XX_CLK_SPI0>;
+ clock-names = "clk_spi0";
+ status = "disabled";
+ };
+
+ fiu3: spi@c000 {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc000 0x1000>;
+ reg-names = "control", "memory";
+ clocks = < NPCM7XX_CLK_SPI3>;
+ clock-names = "clk_spi3";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "disabled";
+ };
+
+ fiux: spi@fb001000 {
+ compatible = &q
[PATCH v8 3/5] arm: dts: add pinctrl and GPIO node to NPCM7XX device tree
Add pin controller and GPIO node to NPCM7XX device tree.
Signed-off-by: Tomer Maimon
Reviewed-by: Joel Stanley
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 564 ++
1 file changed, 564 insertions(+)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 72e364054e72..7755a3de7c53 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -185,4 +185,568 @@
};
};
};
+
+ pinctrl: pinctrl@f080 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd";
+ ranges = <0 0xf001 0x8000>;
+ gpio0: gpio@f001 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 0 32>;
+ };
+ gpio1: gpio@f0011000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 32 32>;
+ };
+ gpio2: gpio@f0012000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 64 32>;
+ };
+ gpio3: gpio@f0013000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x3000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 96 32>;
+ };
+ gpio4: gpio@f0014000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x4000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 128 32>;
+ };
+ gpio5: gpio@f0015000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x5000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 160 32>;
+ };
+ gpio6: gpio@f0016000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x6000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 192 32>;
+ };
+ gpio7: gpio@f0017000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x7000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 224 32>;
+ };
+
+ iox1_pins: iox1-pins {
+ groups = "iox1";
+ function = "iox1";
+ };
+ iox2_pins: iox2-pins {
+ groups = "iox2";
+ function = "iox2";
+ };
+ smb1d_pins: smb1d-pins {
+ groups = "smb1d";
+ function = "smb1d";
+ };
+ smb2d_pins: smb2d-pins {
+ groups = "smb2d";
+ function = "smb2d";
+ };
+ lkgpo1_pins: lkgpo1-pins {
+ groups = "lkgpo1";
+ function = "lkgpo1";
+ };
+ lkgpo2_pins: lkgpo2-pins {
+ groups = "lkgpo2";
+ function = "lkgpo2";
+ };
+ ioxh_pins: ioxh-pins {
+ groups = "ioxh";
+ function = "ioxh";
+ };
+ gspi_pins: gspi-pins {
+ groups = "gspi";
+ function = "gspi";
+ };
+ smb5b_pins: smb5b-pins {
+ groups = "smb5b";
+ function = "smb5b";
+ };
+ smb5c_pins: smb5c-pins {
+ groups = "smb5c";
+ function = "smb5c";
+ };
+ lkgpo0_pins: lkgpo0-pins {
+ groups = "lkgpo0";
+ function = "l
[PATCH v8 2/5] arm: dts: modify NPCM7xx device tree timer register size
Modify NPCM7xx device tree timer register size
from 0x50 to 0x1C to control only the timer registers
and not other hw modules.
Signed-off-by: Tomer Maimon
Reviewed-by: Joel Stanley
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 16a28c5c4131..72e364054e72 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -120,7 +120,7 @@
timer0: timer@8000 {
compatible = "nuvoton,npcm750-timer";
interrupts = ;
- reg = <0x8000 0x50>;
+ reg = <0x8000 0x1C>;
clocks = < NPCM7XX_CLK_TIMER>;
};
--
2.22.0
[PATCH v8 1/5] arm: dts: modify NPCM7xx device tree clock parameter
Modify NPCM7xx device tree clock parameter to clock constants that
define at include/dt-bindings/clock/nuvoton,npcm7xx-clock.h file.
Signed-off-by: Tomer Maimon
Reviewed-by: Joel Stanley
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 19 ++-
arch/arm/boot/dts/nuvoton-npcm750.dtsi| 6 +++---
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index d2d0761295a4..16a28c5c4131 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -3,6 +3,7 @@
// Copyright 2018 Google, Inc.
#include
+#include
/ {
#address-cells = <1>;
@@ -80,7 +81,7 @@
interrupts = ;
cache-unified;
cache-level = <2>;
- clocks = < 10>;
+ clocks = < NPCM7XX_CLK_AXI>;
arm,shared-override;
};
@@ -120,7 +121,7 @@
compatible = "nuvoton,npcm750-timer";
interrupts = ;
reg = <0x8000 0x50>;
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
watchdog0: watchdog@801C {
@@ -128,7 +129,7 @@
interrupts = ;
reg = <0x801C 0x4>;
status = "disabled";
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
watchdog1: watchdog@901C {
@@ -136,7 +137,7 @@
interrupts = ;
reg = <0x901C 0x4>;
status = "disabled";
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
watchdog2: watchdog@a01C {
@@ -144,13 +145,13 @@
interrupts = ;
reg = <0xa01C 0x4>;
status = "disabled";
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
serial0: serial@1000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x1000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
@@ -159,7 +160,7 @@
serial1: serial@2000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x2000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
@@ -168,7 +169,7 @@
serial2: serial@3000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x3000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
@@ -177,7 +178,7 @@
serial3: serial@4000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x4000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
index 6ac340533587..a37bb2294b8f 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -17,7 +17,7 @@
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
- clocks = < 0>;
+
[PATCH v8 5/5] arm: dts: add new device nodes to NPCM750 device tree EVB
Add the following new device nodes to
NPCM750 evolution board device tree:
- NPCM7xx Pin controller and GPIO
- NPCM7xx PWM and FAN.
- NPCM7xx EHCI USB.
- NPCM7xx KCS.
- NPCM Reset.
- NPCM Peripheral SPI.
- NPCM FIU SPI.
- NPCM HWRNG.
- NPCM I2C.
- STMicro STMMAC.
Signed-off-by: Tomer Maimon
---
arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 367 +-
.../boot/dts/nuvoton-npcm750-pincfg-evb.dtsi | 157
2 files changed, 523 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
index 15f744f1beea..9f13d08f5804 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
@@ -4,24 +4,161 @@
/dts-v1/;
#include "nuvoton-npcm750.dtsi"
+#include "dt-bindings/gpio/gpio.h"
+#include "nuvoton-npcm750-pincfg-evb.dtsi"
/ {
model = "Nuvoton npcm750 Development Board (Device Tree)";
compatible = "nuvoton,npcm750";
+ aliases {
+ ethernet2 =
+ ethernet3 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ i2c4 =
+ i2c5 =
+ i2c6 =
+ i2c7 =
+ i2c8 =
+ i2c9 =
+ i2c10 =
+ i2c11 =
+ i2c12 =
+ i2c13 =
+ i2c14 =
+ i2c15 =
+ spi0 =
+ spi1 =
+ fiu0 =
+ fiu1 =
+ fiu2 =
+ };
+
chosen {
stdout-path =
};
memory {
- reg = <0 0x4000>;
+ device_type = "memory";
+ reg = <0x0 0x2000>;
+ };
+};
+
+ {
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+ {
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-rx-bus-width = <2>;
+ reg = <0>;
+ spi-max-frequency = <500>;
+ partitions@8000 {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bbuboot1@0 {
+ label = "bb-uboot-1";
+ reg = <0x000 0x8>;
+ read-only;
+ };
+ bbuboot2@8 {
+ label = "bb-uboot-2";
+ reg = <0x008 0x8>;
+ read-only;
+ };
+ envparam@10 {
+ label = "env-param";
+ reg = <0x010 0x4>;
+ read-only;
+ };
+ spare@14 {
+ label = "spare";
+ reg = <0x014 0xC>;
+ };
+ kernel@20 {
+ label = "kernel";
+ reg = <0x020 0x40>;
+ };
+ rootfs@60 {
+ label = "rootfs";
+ reg = <0x060 0x70>;
+ };
+ spare1@D0 {
+ label = "spare1";
+ reg = <0x0D0 0x20>;
+ };
+ spare2@0F0 {
+ label = "spare2";
+ reg = <0x0F0 0x20>;
+ };
+ spare3@110 {
+ label = "spare3";
+ reg = <0x110 0x20>;
+ };
+ spare4@130 {
+ label = "spare4";
+ reg = <0x130 0x0>;
+
[PATCH v8 0/5] arm: dts: add and modify device node in NPCM7xx device tree
This patch set adds and modify device tree nodes in the NPCM7xx Baseboard Management Controller (BMC) device tree. The following device node add: - NPCM7xx Pin controller and GPIO - NPCM7xx PWM and FAN. - NPCM7xx EHCI USB. - NPCM7xx KCS. - NPCM Reset. - NPCM Peripheral SPI. - NPCM FIU SPI. - NPCM HWRNG. - NPCM I2C. - STMicro STMMAC. The following device node modified: - NPCM7xx timer. - NPCM7xx clock constants parameters. NPCM7xx device tree tested on NPCM750 evaluation board. Changes since version 7: Address comments from Joel Stanely: https://www.spinics.net/lists/devicetree/msg380191.html Changes since version 6: Split commits. Changes since version 5: Address comments from Joel Stanely: https://lkml.org/lkml/2020/9/16/994 Changes since version 4: - Tested patches in Linux kernel 5.9. Changes since version 3: - Tested patches in Linux kernel 5.6. Changes since version 2: - Remove unnecessary output-enable flags. Changes since version 1: - Add NPCM reset device node. - Add reset parameters to NPCM driver device nodes. Tomer Maimon (5): arm: dts: modify NPCM7xx device tree clock parameter arm: dts: modify NPCM7xx device tree timer register size arm: dts: add pinctrl and GPIO node to NPCM7XX device tree arm: dts: add new device nodes to NPCM7XX device tree arm: dts: add new device nodes to NPCM750 device tree EVB arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 967 +- arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 367 ++- .../boot/dts/nuvoton-npcm750-pincfg-evb.dtsi | 157 +++ arch/arm/boot/dts/nuvoton-npcm750.dtsi| 24 +- 4 files changed, 1495 insertions(+), 20 deletions(-) create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi -- 2.22.0
[PATCH v1] hw_random: npcm: modify readl to readb
Modify the read size to the correct HW random
registers size, 8bit.
The incorrect read size caused and faulty
HW random value.
Signed-off-by: Tomer Maimon
---
drivers/char/hw_random/npcm-rng.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/char/hw_random/npcm-rng.c
b/drivers/char/hw_random/npcm-rng.c
index 5d0d13f891b7..1ec5f267a656 100644
--- a/drivers/char/hw_random/npcm-rng.c
+++ b/drivers/char/hw_random/npcm-rng.c
@@ -58,24 +58,24 @@ static int npcm_rng_read(struct hwrng *rng, void *buf,
size_t max, bool wait)
pm_runtime_get_sync((struct device *)priv->rng.priv);
- while (max >= sizeof(u32)) {
+ while (max) {
if (wait) {
- if (readl_poll_timeout(priv->base + NPCM_RNGCS_REG,
+ if (readb_poll_timeout(priv->base + NPCM_RNGCS_REG,
ready,
ready & NPCM_RNG_DATA_VALID,
NPCM_RNG_POLL_USEC,
NPCM_RNG_TIMEOUT_USEC))
break;
} else {
- if ((readl(priv->base + NPCM_RNGCS_REG) &
+ if ((readb(priv->base + NPCM_RNGCS_REG) &
NPCM_RNG_DATA_VALID) == 0)
break;
}
- *(u32 *)buf = readl(priv->base + NPCM_RNGD_REG);
- retval += sizeof(u32);
- buf += sizeof(u32);
- max -= sizeof(u32);
+ *(u8 *)buf = readb(priv->base + NPCM_RNGD_REG);
+ retval++;
+ buf++;
+ max--;
}
pm_runtime_mark_last_busy((struct device *)priv->rng.priv);
--
2.22.0
[PATCH v7 4/5] arm: dts: add new device nodes to NPCM7XX device tree
Add the following new device nodes to NPCM7XX:
- NPCM7xx PWM and FAN.
- NPCM7xx EHCI USB.
- NPCM7xx KCS.
- NPCM Reset.
- NPCM Peripheral SPI.
- NPCM FIU SPI.
- NPCM HWRNG.
- NPCM I2C.
- STMicro STMMAC.
Signed-off-by: Tomer Maimon
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 382 +-
arch/arm/boot/dts/nuvoton-npcm750.dtsi| 18 +
2 files changed, 394 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 5df77a617e77..4a69a9f31668 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -4,6 +4,7 @@
#include
#include
+#include
/ {
#address-cells = <1>;
@@ -64,12 +65,6 @@
interrupt-parent = <>;
ranges = <0x0 0xf000 0x0090>;
- gcr: gcr@80 {
- compatible = "nuvoton,npcm750-gcr", "syscon",
- "simple-mfd";
- reg = <0x80 0x1000>;
- };
-
scu: scu@3fe000 {
compatible = "arm,cortex-a9-scu";
reg = <0x3fe000 0x1000>;
@@ -92,6 +87,16 @@
reg = <0x3ff000 0x1000>,
<0x3fe100 0x100>;
};
+
+ gcr: gcr@80 {
+ compatible = "nuvoton,npcm750-gcr", "syscon",
"simple-mfd";
+ reg = <0x80 0x1000>;
+ };
+
+ rst: rst@801000 {
+ compatible = "nuvoton,npcm750-rst", "syscon",
"simple-mfd";
+ reg = <0x801000 0x6C>;
+ };
};
ahb {
@@ -101,6 +106,12 @@
interrupt-parent = <>;
ranges;
+ rstc: rstc@f0801000 {
+ compatible = "nuvoton,npcm750-reset";
+ reg = <0xf0801000 0x70>;
+ #reset-cells = <2>;
+ };
+
clk: clock-controller@f0801000 {
compatible = "nuvoton,npcm750-clk", "syscon";
#clock-cells = <1>;
@@ -110,6 +121,63 @@
clocks = <_refclk>, <_sysbypck>, <_mcbypck>;
};
+ gmac0: eth@f0802000 {
+ device_type = "network";
+ compatible = "snps,dwmac";
+ reg = <0xf0802000 0x2000>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ ethernet = <0>;
+ clocks = <_rg1refck>, < NPCM7XX_CLK_AHB>;
+ clock-names = "stmmaceth", "clk_gmac";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins
+ _pins>;
+ status = "disabled";
+ };
+
+ ehci1: usb@f0806000 {
+ compatible = "nuvoton,npcm750-ehci";
+ reg = <0xf0806000 0x1000>;
+ interrupts = ;
+ status = "disabled";
+ };
+
+ fiu0: spi@fb00 {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfb00 0x1000>;
+ reg-names = "control", "memory";
+ clocks = < NPCM7XX_CLK_SPI0>;
+ clock-names = "clk_spi0";
+ status = "disabled";
+ };
+
+ fiu3: spi@c000 {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc000 0x1000>;
+ reg-names = "control", "memory";
+ clocks = < NPCM7XX_CLK_SPI3>;
+ clock-names = "clk_spi3";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "disabled";
+ };
+
+ fiux: spi@fb001000 {
+ compatible = "nuvoton,npcm750-fiu";
+
[PATCH v7 1/5] arm: dts: modify NPCM7xx device tree clock parameter
Modify NPCM7xx device tree clock parameter to clock constants that
define at include/dt-bindings/clock/nuvoton,npcm7xx-clock.h file.
Signed-off-by: Tomer Maimon
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 19 ++-
arch/arm/boot/dts/nuvoton-npcm750.dtsi| 6 +++---
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index d2d0761295a4..16a28c5c4131 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -3,6 +3,7 @@
// Copyright 2018 Google, Inc.
#include
+#include
/ {
#address-cells = <1>;
@@ -80,7 +81,7 @@
interrupts = ;
cache-unified;
cache-level = <2>;
- clocks = < 10>;
+ clocks = < NPCM7XX_CLK_AXI>;
arm,shared-override;
};
@@ -120,7 +121,7 @@
compatible = "nuvoton,npcm750-timer";
interrupts = ;
reg = <0x8000 0x50>;
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
watchdog0: watchdog@801C {
@@ -128,7 +129,7 @@
interrupts = ;
reg = <0x801C 0x4>;
status = "disabled";
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
watchdog1: watchdog@901C {
@@ -136,7 +137,7 @@
interrupts = ;
reg = <0x901C 0x4>;
status = "disabled";
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
watchdog2: watchdog@a01C {
@@ -144,13 +145,13 @@
interrupts = ;
reg = <0xa01C 0x4>;
status = "disabled";
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
serial0: serial@1000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x1000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
@@ -159,7 +160,7 @@
serial1: serial@2000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x2000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
@@ -168,7 +169,7 @@
serial2: serial@3000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x3000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
@@ -177,7 +178,7 @@
serial3: serial@4000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x4000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
index 6ac340533587..a37bb2294b8f 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -17,7 +17,7 @@
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
- clocks = < 0>;
+
[PATCH v7 2/5] arm: dts: modify NPCM7xx device tree timer register size
Modify NPCM7xx device tree timer register size
from 0x50 to 0x1C to control only the timer registers
and not other hw modules.
Signed-off-by: Tomer Maimon
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 16a28c5c4131..72e364054e72 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -120,7 +120,7 @@
timer0: timer@8000 {
compatible = "nuvoton,npcm750-timer";
interrupts = ;
- reg = <0x8000 0x50>;
+ reg = <0x8000 0x1C>;
clocks = < NPCM7XX_CLK_TIMER>;
};
--
2.22.0
[PATCH v7 3/5] arm: dts: add pinctrl and GPIO node to NPCM7XX device tree
Add pin controller and GPIO node to NPCM7XX device tree.
Signed-off-by: Tomer Maimon
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 565 ++
1 file changed, 565 insertions(+)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 72e364054e72..5df77a617e77 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -185,4 +185,569 @@
};
};
};
+
+ pinctrl: pinctrl@f080 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd";
+ ranges = <0 0xf001 0x8000>;
+ status = "okay";
+ gpio0: gpio@f001 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 0 32>;
+ };
+ gpio1: gpio@f0011000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x1000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 32 32>;
+ };
+ gpio2: gpio@f0012000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x2000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 64 32>;
+ };
+ gpio3: gpio@f0013000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x3000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 96 32>;
+ };
+ gpio4: gpio@f0014000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x4000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 128 32>;
+ };
+ gpio5: gpio@f0015000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x5000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 160 32>;
+ };
+ gpio6: gpio@f0016000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x6000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 192 32>;
+ };
+ gpio7: gpio@f0017000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x7000 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 224 32>;
+ };
+
+ iox1_pins: iox1-pins {
+ groups = "iox1";
+ function = "iox1";
+ };
+ iox2_pins: iox2-pins {
+ groups = "iox2";
+ function = "iox2";
+ };
+ smb1d_pins: smb1d-pins {
+ groups = "smb1d";
+ function = "smb1d";
+ };
+ smb2d_pins: smb2d-pins {
+ groups = "smb2d";
+ function = "smb2d";
+ };
+ lkgpo1_pins: lkgpo1-pins {
+ groups = "lkgpo1";
+ function = "lkgpo1";
+ };
+ lkgpo2_pins: lkgpo2-pins {
+ groups = "lkgpo2";
+ function = "lkgpo2";
+ };
+ ioxh_pins: ioxh-pins {
+ groups = "ioxh";
+ function = "ioxh";
+ };
+ gspi_pins: gspi-pins {
+ groups = "gspi";
+ function = "gspi";
+ };
+ smb5b_pins: smb5b-pins {
+ groups = "smb5b";
+ function = "smb5b";
+ };
+ smb5c_pins: smb5c-pins {
+ groups = "smb5c";
+ function = "smb5c";
+ };
+ lkgpo0_pins: lkgpo0-pins {
+ groups = "lkgpo0";
+ function
[PATCH v7 5/5] arm: dts: add new device nodes to NPCM750 device tree EVB
Add the following new device nodes to
NPCM750 evolution board device tree:
- NPCM7xx Pin controller and GPIO
- NPCM7xx PWM and FAN.
- NPCM7xx EHCI USB.
- NPCM7xx KCS.
- NPCM Reset.
- NPCM Peripheral SPI.
- NPCM FIU SPI.
- NPCM HWRNG.
- NPCM I2C.
- STMicro STMMAC.
Signed-off-by: Tomer Maimon
---
arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 405 +-
.../boot/dts/nuvoton-npcm750-pincfg-evb.dtsi | 157 +++
2 files changed, 546 insertions(+), 16 deletions(-)
create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
index 15f744f1beea..1623a18ac29b 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
@@ -4,36 +4,409 @@
/dts-v1/;
#include "nuvoton-npcm750.dtsi"
+#include "dt-bindings/gpio/gpio.h"
+#include "nuvoton-npcm750-pincfg-evb.dtsi"
/ {
model = "Nuvoton npcm750 Development Board (Device Tree)";
compatible = "nuvoton,npcm750";
+ aliases {
+ ethernet2 =
+ ethernet3 =
+ serial0 =
+ serial1 =
+ serial2 =
+ serial3 =
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ i2c4 =
+ i2c5 =
+ i2c6 =
+ i2c7 =
+ i2c8 =
+ i2c9 =
+ i2c10 =
+ i2c11 =
+ i2c12 =
+ i2c13 =
+ i2c14 =
+ i2c15 =
+ spi0 =
+ spi1 =
+ fiu0 =
+ fiu1 =
+ fiu2 =
+ };
+
chosen {
stdout-path =
};
memory {
- reg = <0 0x4000>;
+ device_type = "memory";
+ reg = <0x0 0x2000>;
};
-};
- {
- status = "okay";
-};
+ ahb {
+ gmac0: eth@f0802000 {
+ phy-mode = "rgmii-id";
+ status = "okay";
+ };
- {
- status = "okay";
-};
+ gmac1: eth@f0804000 {
+ phy-mode = "rgmii-id";
+ status = "okay";
+ };
- {
- status = "okay";
-};
+ ehci1: usb@f0806000 {
+ status = "okay";
+ };
- {
- status = "okay";
-};
+ fiu0: spi@fb00 {
+ status = "okay";
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-rx-bus-width = <2>;
+ reg = <0>;
+ spi-max-frequency = <500>;
+ partitions@8000 {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bbuboot1@0 {
+ label = "bb-uboot-1";
+ reg = <0x000 0x8>;
+ read-only;
+ };
+ bbuboot2@8 {
+ label = "bb-uboot-2";
+ reg = <0x008 0x8>;
+ read-only;
+ };
+ envparam@10 {
+ label = "env-param";
+ reg = <0x010 0x4>;
+ read-only;
+ };
+ spare@14 {
+ label = "spare";
+ reg = <0x014 0xC>;
+ };
+ kernel@20 {
+ label = "kernel";
+
[PATCH v7 0/5] arm: dts: add and modify device node in NPCM7xx device tree
This patch set adds and modify device tree nodes in the NPCM7xx Baseboard Management Controller (BMC) device tree. The following device node add: - NPCM7xx Pin controller and GPIO - NPCM7xx PWM and FAN. - NPCM7xx EHCI USB. - NPCM7xx KCS. - NPCM Reset. - NPCM Peripheral SPI. - NPCM FIU SPI. - NPCM HWRNG. - NPCM I2C. - STMicro STMMAC. The following device node modified: - NPCM7xx timer. - NPCM7xx clock constants parameters. NPCM7xx device tree tested on NPCM750 evaluation board. Changes since version 6: Split commits. Changes since version 5: Address comments from Joel Stanely: https://lkml.org/lkml/2020/9/16/994 Changes since version 4: - Tested patches in Linux kernel 5.9. Changes since version 3: - Tested patches in Linux kernel 5.6. Changes since version 2: - Remove unnecessary output-enable flags. Changes since version 1: - Add NPCM reset device node. - Add reset parameters to NPCM driver device nodes. Tomer Maimon (5): arm: dts: modify NPCM7xx device tree clock parameter arm: dts: modify NPCM7xx device tree timer register size arm: dts: add pinctrl and GPIO node to NPCM7XX device tree arm: dts: add new device nodes to NPCM7XX device tree arm: dts: add new device nodes to NPCM750 device tree EVB arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 968 +- arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 405 +++- .../boot/dts/nuvoton-npcm750-pincfg-evb.dtsi | 157 +++ arch/arm/boot/dts/nuvoton-npcm750.dtsi| 24 +- 4 files changed, 1519 insertions(+), 35 deletions(-) create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi -- 2.22.0
[PATCH v6 1/3] arm: dts: modify NPCM7xx device tree clock parameter
Modify NPCM7xx device tree clock parameter to clock constants that
define at include/dt-bindings/clock/nuvoton,npcm7xx-clock.h file.
Signed-off-by: Tomer Maimon
Reviewed-by: Joel Stanley
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 19 ++-
arch/arm/boot/dts/nuvoton-npcm750.dtsi| 6 +++---
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index d2d0761295a4..16a28c5c4131 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -3,6 +3,7 @@
// Copyright 2018 Google, Inc.
#include
+#include
/ {
#address-cells = <1>;
@@ -80,7 +81,7 @@
interrupts = ;
cache-unified;
cache-level = <2>;
- clocks = < 10>;
+ clocks = < NPCM7XX_CLK_AXI>;
arm,shared-override;
};
@@ -120,7 +121,7 @@
compatible = "nuvoton,npcm750-timer";
interrupts = ;
reg = <0x8000 0x50>;
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
watchdog0: watchdog@801C {
@@ -128,7 +129,7 @@
interrupts = ;
reg = <0x801C 0x4>;
status = "disabled";
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
watchdog1: watchdog@901C {
@@ -136,7 +137,7 @@
interrupts = ;
reg = <0x901C 0x4>;
status = "disabled";
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
watchdog2: watchdog@a01C {
@@ -144,13 +145,13 @@
interrupts = ;
reg = <0xa01C 0x4>;
status = "disabled";
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
serial0: serial@1000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x1000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
@@ -159,7 +160,7 @@
serial1: serial@2000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x2000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
@@ -168,7 +169,7 @@
serial2: serial@3000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x3000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
@@ -177,7 +178,7 @@
serial3: serial@4000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x4000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
index 6ac340533587..a37bb2294b8f 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -17,7 +17,7 @@
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
- clocks = < 0>;
+
[PATCH v6 3/3] arm: dts: add new device nodes to NPCM750 device tree
Add the following new device nodes to NPCM750 and
NPCM750 evolution board device tree:
- NPCM7xx Pin controller and GPIO
- NPCM7xx PWM and FAN.
- NPCM7xx EHCI USB.
- NPCM7xx KCS.
- NPCM Reset.
- NPCM Peripheral SPI.
- NPCM FIU SPI.
- NPCM HWRNG.
- NPCM I2C.
- STMicro STMMAC.
Signed-off-by: Tomer Maimon
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 947 +-
arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 404 +++-
.../boot/dts/nuvoton-npcm750-pincfg-evb.dtsi | 157 +++
arch/arm/boot/dts/nuvoton-npcm750.dtsi| 18 +
4 files changed, 1502 insertions(+), 24 deletions(-)
create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 72e364054e72..4a69a9f31668 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -4,6 +4,7 @@
#include
#include
+#include
/ {
#address-cells = <1>;
@@ -64,12 +65,6 @@
interrupt-parent = <>;
ranges = <0x0 0xf000 0x0090>;
- gcr: gcr@80 {
- compatible = "nuvoton,npcm750-gcr", "syscon",
- "simple-mfd";
- reg = <0x80 0x1000>;
- };
-
scu: scu@3fe000 {
compatible = "arm,cortex-a9-scu";
reg = <0x3fe000 0x1000>;
@@ -92,6 +87,16 @@
reg = <0x3ff000 0x1000>,
<0x3fe100 0x100>;
};
+
+ gcr: gcr@80 {
+ compatible = "nuvoton,npcm750-gcr", "syscon",
"simple-mfd";
+ reg = <0x80 0x1000>;
+ };
+
+ rst: rst@801000 {
+ compatible = "nuvoton,npcm750-rst", "syscon",
"simple-mfd";
+ reg = <0x801000 0x6C>;
+ };
};
ahb {
@@ -101,6 +106,12 @@
interrupt-parent = <>;
ranges;
+ rstc: rstc@f0801000 {
+ compatible = "nuvoton,npcm750-reset";
+ reg = <0xf0801000 0x70>;
+ #reset-cells = <2>;
+ };
+
clk: clock-controller@f0801000 {
compatible = "nuvoton,npcm750-clk", "syscon";
#clock-cells = <1>;
@@ -110,6 +121,63 @@
clocks = <_refclk>, <_sysbypck>, <_mcbypck>;
};
+ gmac0: eth@f0802000 {
+ device_type = "network";
+ compatible = "snps,dwmac";
+ reg = <0xf0802000 0x2000>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ ethernet = <0>;
+ clocks = <_rg1refck>, < NPCM7XX_CLK_AHB>;
+ clock-names = "stmmaceth", "clk_gmac";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins
+ _pins>;
+ status = "disabled";
+ };
+
+ ehci1: usb@f0806000 {
+ compatible = "nuvoton,npcm750-ehci";
+ reg = <0xf0806000 0x1000>;
+ interrupts = ;
+ status = "disabled";
+ };
+
+ fiu0: spi@fb00 {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfb00 0x1000>;
+ reg-names = "control", "memory";
+ clocks = < NPCM7XX_CLK_SPI0>;
+ clock-names = "clk_spi0";
+ status = "disabled";
+ };
+
+ fiu3: spi@c000 {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc000 0x1000>;
+ reg-names = "control", "memory";
+ clocks = < NPCM7XX_CLK_SPI3>;
+ clock-names = "clk_spi3";
+
[PATCH v6 2/3] arm: dts: modify NPCM7xx device tree timer register size
Modify NPCM7xx device tree timer register size
from 0x50 to 0x1C to control only the timer registers
and not other hw modules.
Signed-off-by: Tomer Maimon
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 16a28c5c4131..72e364054e72 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -120,7 +120,7 @@
timer0: timer@8000 {
compatible = "nuvoton,npcm750-timer";
interrupts = ;
- reg = <0x8000 0x50>;
+ reg = <0x8000 0x1C>;
clocks = < NPCM7XX_CLK_TIMER>;
};
--
2.22.0
[PATCH v6 0/3] arm: dts: add and modify device node in NPCM7xx device tree
This patch set adds and modify device tree nodes in the NPCM7xx Baseboard Management Controller (BMC) device tree. The following device node add: - NPCM7xx Pin controller and GPIO - NPCM7xx PWM and FAN. - NPCM7xx EHCI USB. - NPCM7xx KCS. - NPCM Reset. - NPCM Peripheral SPI. - NPCM FIU SPI. - NPCM HWRNG. - NPCM I2C. - STMicro STMMAC. The following device node modified: - NPCM7xx timer. - NPCM7xx clock constants parameters. NPCM7xx device tree tested on NPCM750 evaluation board. Changes since version 5: Address comments from Joel Stanely: https://lkml.org/lkml/2020/9/16/994 Changes since version 4: - Tested patches in Linux kernel 5.9. Changes since version 3: - Tested patches in Linux kernel 5.6. Changes since version 2: - Remove unnecessary output-enable flags. Changes since version 1: - Add NPCM reset device node. - Add reset parameters to NPCM driver device nodes. Tomer Maimon (3): arm: dts: modify NPCM7xx device tree clock parameter arm: dts: modify NPCM7xx device tree timer register size arm: dts: add new device nodes to NPCM750 device tree arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 968 +- arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 404 +++- .../boot/dts/nuvoton-npcm750-pincfg-evb.dtsi | 157 +++ arch/arm/boot/dts/nuvoton-npcm750.dtsi| 24 +- 4 files changed, 1516 insertions(+), 37 deletions(-) create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi -- 2.22.0
[PATCH v5 3/3] arm: dts: add new device nodes to NPCM750 device tree
Add the following new device nodes to NPCM750 and
NPCM750 evolution board device tree:
- NPCM7xx Pin controller and GPIO
- NPCM7xx PWM and FAN.
- NPCM7xx EHCI USB.
- NPCM7xx KCS.
- NPCM Reset.
- NPCM Peripheral SPI.
- NPCM FIU SPI.
- NPCM HWRNG.
- NPCM I2C.
- STMicro STMMAC.
Signed-off-by: Tomer Maimon
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 953 +-
arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 404 +++-
.../boot/dts/nuvoton-npcm750-pincfg-evb.dtsi | 157 +++
arch/arm/boot/dts/nuvoton-npcm750.dtsi| 18 +
4 files changed, 1508 insertions(+), 24 deletions(-)
create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 72e364054e72..7d4be1ded470 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -4,12 +4,18 @@
#include
#include
+#include
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <>;
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x4000>;
+ };
+
/* external reference clock */
clk_refclk: clk_refclk {
compatible = "fixed-clock";
@@ -64,12 +70,6 @@
interrupt-parent = <>;
ranges = <0x0 0xf000 0x0090>;
- gcr: gcr@80 {
- compatible = "nuvoton,npcm750-gcr", "syscon",
- "simple-mfd";
- reg = <0x80 0x1000>;
- };
-
scu: scu@3fe000 {
compatible = "arm,cortex-a9-scu";
reg = <0x3fe000 0x1000>;
@@ -92,6 +92,16 @@
reg = <0x3ff000 0x1000>,
<0x3fe100 0x100>;
};
+
+ gcr: gcr@80 {
+ compatible = "nuvoton,npcm750-gcr", "syscon",
"simple-mfd";
+ reg = <0x80 0x1000>;
+ };
+
+ rst: rst@801000 {
+ compatible = "nuvoton,npcm750-rst", "syscon",
"simple-mfd";
+ reg = <0x801000 0x6C>;
+ };
};
ahb {
@@ -101,6 +111,12 @@
interrupt-parent = <>;
ranges;
+ rstc: rstc@f0801000 {
+ compatible = "nuvoton,npcm750-reset";
+ reg = <0xf0801000 0x70>;
+ #reset-cells = <2>;
+ };
+
clk: clock-controller@f0801000 {
compatible = "nuvoton,npcm750-clk", "syscon";
#clock-cells = <1>;
@@ -110,6 +126,63 @@
clocks = <_refclk>, <_sysbypck>, <_mcbypck>;
};
+ gmac0: eth@f0802000 {
+ device_type = "network";
+ compatible = "snps,dwmac";
+ reg = <0xf0802000 0x2000>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ ethernet = <0>;
+ clocks = <_rg1refck>, < NPCM7XX_CLK_AHB>;
+ clock-names = "stmmaceth", "clk_gmac";
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins
+ _pins>;
+ status = "disabled";
+ };
+
+ ehci1:usb@f0806000 {
+ compatible = "nuvoton,npcm750-ehci";
+ reg = <0xf0806000 0x1000>;
+ interrupts = ;
+ status = "disabled";
+ };
+
+ fiu0: spi@fb00 {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfb00 0x1000>, <0x8000 0x1000>;
+ reg-names = "control", "memory";
+ clocks = < NPCM7XX_CLK_SPI0>;
+ clock-names = "clk_spi0";
+ status = "disabled";
+ };
+
+ fiu3: spi@c000 {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-
[PATCH v5 2/3] arm: dts: modify NPCM7xx device tree timer register size
Modify NPCM7xx device tree timer register size
from 0x50 to 0x1C.
Signed-off-by: Tomer Maimon
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 16a28c5c4131..72e364054e72 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -120,7 +120,7 @@
timer0: timer@8000 {
compatible = "nuvoton,npcm750-timer";
interrupts = ;
- reg = <0x8000 0x50>;
+ reg = <0x8000 0x1C>;
clocks = < NPCM7XX_CLK_TIMER>;
};
--
2.22.0
[PATCH v5 0/3] arm: dts: add and modify device node in NPCM7xx device tree
This patch set adds and modify device tree nodes in the NPCM7xx Baseboard Management Controller (BMC) device tree. The following device node add: - NPCM7xx Pin controller and GPIO - NPCM7xx PWM and FAN. - NPCM7xx EHCI USB. - NPCM7xx KCS. - NPCM Reset. - NPCM Peripheral SPI. - NPCM FIU SPI. - NPCM HWRNG. - NPCM I2C. - STMicro STMMAC. The following device node modified: - NPCM7xx timer. - NPCM7xx clock constants parameters. NPCM7xx device tree tested on NPCM750 evaluation board. Changes since version 4: - Tested patches in Linux kernel 5.9. Changes since version 3: - Tested patches in Linux kernel 5.6. Changes since version 2: - Remove unnecessary output-enable flags. Changes since version 1: - Add NPCM reset device node. - Add reset parameters to NPCM driver device nodes. Tomer Maimon (3): arm: dts: modify NPCM7xx device tree clock parameter arm: dts: modify NPCM7xx device tree timer register size arm: dts: add new device nodes to NPCM750 device tree arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 974 +- arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 404 +++- .../boot/dts/nuvoton-npcm750-pincfg-evb.dtsi | 157 +++ arch/arm/boot/dts/nuvoton-npcm750.dtsi| 24 +- 4 files changed, 1522 insertions(+), 37 deletions(-) create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi -- 2.22.0
[PATCH v5 1/3] arm: dts: modify NPCM7xx device tree clock parameter
Modify NPCM7xx device tree clock parameter to clock constants that
define at include/dt-bindings/clock/nuvoton,npcm7xx-clock.h file.
Signed-off-by: Tomer Maimon
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 19 ++-
arch/arm/boot/dts/nuvoton-npcm750.dtsi| 6 +++---
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index d2d0761295a4..16a28c5c4131 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -3,6 +3,7 @@
// Copyright 2018 Google, Inc.
#include
+#include
/ {
#address-cells = <1>;
@@ -80,7 +81,7 @@
interrupts = ;
cache-unified;
cache-level = <2>;
- clocks = < 10>;
+ clocks = < NPCM7XX_CLK_AXI>;
arm,shared-override;
};
@@ -120,7 +121,7 @@
compatible = "nuvoton,npcm750-timer";
interrupts = ;
reg = <0x8000 0x50>;
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
watchdog0: watchdog@801C {
@@ -128,7 +129,7 @@
interrupts = ;
reg = <0x801C 0x4>;
status = "disabled";
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
watchdog1: watchdog@901C {
@@ -136,7 +137,7 @@
interrupts = ;
reg = <0x901C 0x4>;
status = "disabled";
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
watchdog2: watchdog@a01C {
@@ -144,13 +145,13 @@
interrupts = ;
reg = <0xa01C 0x4>;
status = "disabled";
- clocks = < 5>;
+ clocks = < NPCM7XX_CLK_TIMER>;
};
serial0: serial@1000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x1000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
@@ -159,7 +160,7 @@
serial1: serial@2000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x2000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
@@ -168,7 +169,7 @@
serial2: serial@3000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x3000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
@@ -177,7 +178,7 @@
serial3: serial@4000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x4000 0x1000>;
- clocks = < 6>;
+ clocks = < NPCM7XX_CLK_UART>;
interrupts = ;
reg-shift = <2>;
status = "disabled";
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
index 6ac340533587..a37bb2294b8f 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -17,7 +17,7 @@
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
- clocks = < 0>;
+
[PATCH v3 0/2] hwrng: npcm: add NPCM RNG driver support
This patch set adds Random Number Generator (RNG) support for the Nuvoton NPCM Baseboard Management Controller (BMC). The RNG driver we use power consumption when the RNG is not required. The NPCM RNG driver tested on NPCM750 evaluation board. Addressed comments from:. - Daniel Thompson: https://lkml.org/lkml/2019/9/10/352 - Milton Miller II : https://lkml.org/lkml/2019/9/10/847 - Daniel Thompson: https://lkml.org/lkml/2019/9/10/294 Changes since version 2: - Rearrange wait parameter in npcm_rng_read function. - Calling pm_runtime_enable function before hwrng_register function called to enable the hwrng before add_early_randomness called. - Remove quality dt-binding parameter in the driver and documentation. - Disable CONFIG_PM if devm_hwrng_register failed. - Remove owner setting in the driver struct. Changes since version 1: - Define timout in real-world units. - Using readl_poll_timeout in rng_read function. - Honor wait parameter in rng_read function. - Using local variable instead of #ifndef. - Remove probe print. Tomer Maimon (2): dt-binding: hwrng: add NPCM RNG documentation hwrng: npcm: add NPCM RNG driver .../bindings/rng/nuvoton,npcm-rng.txt | 12 ++ drivers/char/hw_random/Kconfig| 13 ++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/npcm-rng.c | 186 ++ 4 files changed, 212 insertions(+) create mode 100644 Documentation/devicetree/bindings/rng/nuvoton,npcm-rng.txt create mode 100644 drivers/char/hw_random/npcm-rng.c -- 2.18.0
[PATCH v3 1/2] dt-binding: spi: add NPCM FIU controller
Added device tree binding documentation for Nuvoton BMC
NPCM Flash Interface Unit(FIU) SPI master controller
using SPI-MEM interface.
Signed-off-by: Tomer Maimon
---
.../bindings/spi/nuvoton,npcm-fiu.txt | 47 +++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
new file mode 100644
index ..a388005842ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
@@ -0,0 +1,47 @@
+* Nuvoton FLASH Interface Unit (FIU) SPI Controller
+
+NPCM FIU supports single, dual and quad communication interface.
+
+The NPCM7XX supports three FIU modules,
+FIU0 and FIUx supports two chip selects,
+FIU3 support four chip select.
+
+Required properties:
+ - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
+ - #address-cells : should be 1.
+ - #size-cells : should be 0.
+ - reg : the first contains the register location and length,
+ the second contains the memory mapping address and length
+ - reg-names: Should contain the reg names "control" and "memory"
+ - clocks : phandle of FIU reference clock.
+
+Required properties in case the pins can be muxed:
+ - pinctrl-names : a pinctrl state named "default" must be defined.
+ - pinctrl-0 : phandle referencing pin configuration of the device.
+
+Optional property:
+ - nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or
CPLD.
+
+Aliases:
+- All the FIU controller nodes should be represented in the aliases node using
+ the following format 'fiu{n}' where n is a unique number for the alias.
+ In the NPCM7XX BMC:
+ fiu0 represent fiu 0 controller
+ fiu1 represent fiu 3 controller
+ fiu2 represent fiu x controller
+
+Example:
+fiu3: spi@c {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfb00 0x1000>, <0x8000 0x1000>;
+ reg-names = "control", "memory";
+ clocks = < NPCM7XX_CLK_AHB>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ spi-nor@0 {
+ ...
+ };
+};
+
--
2.18.0
[PATCH v3 0/2] spi: add NPCM FIU controller driver
This patch set adds Flash Interface Unit(FIU) SPI master support for the Nuvoton NPCM Baseboard Management Controller (BMC). The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. The NPCM750/730/715/710 supports up to three FIU devices: - FIU0 supports two chip select. - FIU3 supports four chip select. - FIUX supports two chip select. The NPCM FIU driver tested on NPCM750 evaluation board. The FIU controller driver using direct map API SPI-MEM interface and tested with the latest m25p80 driver patch https://www.spinics.net/lists/linux-mtd/msg07358.html According a conversion about direct SPI-MEM API https://www.spinics.net/lists/linux-mtd/msg08225.html The m25p80 driver will merge to the spi-nor driver we need to make sure the m25p80 direct SPI-MEM will merge as well. The FIU controller driver tested with the latest spi-nor driver patch https://www.spinics.net/lists/linux-mtd/msg08472.html Addressed comments from: - Mark Brown: https://www.spinics.net/lists/linux-spi/msg18166.html - Boris Brezillon: https://www.spinics.net/lists/linux-spi/msg18176.html - Rob Herring: https://www.spinics.net/lists/linux-spi/msg18289.html Changes since version 2: - Remove unnecessary dev_info probe print. - Support address SPI memory operation. - Limit address size support. - Add vendor prefix to spi-mode property dt-binding documentation. Changes since version 1: - Support spi-mem no data transferred option (SPI_MEM_NO_DATA) Tomer Maimon (2): dt-binding: spi: add NPCM FIU controller spi: npcm-fiu: add NPCM FIU controller driver .../bindings/spi/nuvoton,npcm-fiu.txt | 47 ++ drivers/spi/Kconfig | 10 + drivers/spi/Makefile | 1 + drivers/spi/spi-npcm-fiu.c| 771 ++ 4 files changed, 829 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt create mode 100644 drivers/spi/spi-npcm-fiu.c -- 2.18.0
[PATCH v3 2/2] spi: npcm-fiu: add NPCM FIU controller driver
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master controller driver using SPI-MEM interface. The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. Signed-off-by: Tomer Maimon --- drivers/spi/Kconfig| 10 + drivers/spi/Makefile | 1 + drivers/spi/spi-npcm-fiu.c | 771 + 3 files changed, 782 insertions(+) create mode 100644 drivers/spi/spi-npcm-fiu.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3a1d8f1170de..6ee514fd0920 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -433,6 +433,16 @@ config SPI_MT7621 help This selects a driver for the MediaTek MT7621 SPI Controller. +config SPI_NPCM_FIU + tristate "Nuvoton NPCM FLASH Interface Unit" + depends on ARCH_NPCM || COMPILE_TEST + depends on OF && HAS_IOMEM + help + This enables support for the Flash Interface Unit SPI controller + in master mode. + This driver does not support generic SPI. The implementation only + supports spi-mem interface. + config SPI_NPCM_PSPI tristate "Nuvoton NPCM PSPI Controller" depends on ARCH_NPCM || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 63dcab552bcb..adbebee93a75 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o obj-$(CONFIG_SPI_MXIC) += spi-mxic.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o +obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o obj-$(CONFIG_SPI_NPCM_PSPI)+= spi-npcm-pspi.o obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o diff --git a/drivers/spi/spi-npcm-fiu.c b/drivers/spi/spi-npcm-fiu.c new file mode 100644 index ..3ea1ec68147e --- /dev/null +++ b/drivers/spi/spi-npcm-fiu.c @@ -0,0 +1,771 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Nuvoton Technology corporation. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* NPCM7xx GCR module */ +#define NPCM7XX_INTCR3_OFFSET 0x9C +#define NPCM7XX_INTCR3_FIU_FIX BIT(6) + +/* Flash Interface Unit (FIU) Registers */ +#define NPCM_FIU_DRD_CFG 0x00 +#define NPCM_FIU_DWR_CFG 0x04 +#define NPCM_FIU_UMA_CFG 0x08 +#define NPCM_FIU_UMA_CTS 0x0C +#define NPCM_FIU_UMA_CMD 0x10 +#define NPCM_FIU_UMA_ADDR 0x14 +#define NPCM_FIU_PRT_CFG 0x18 +#define NPCM_FIU_UMA_DW0 0x20 +#define NPCM_FIU_UMA_DW1 0x24 +#define NPCM_FIU_UMA_DW2 0x28 +#define NPCM_FIU_UMA_DW3 0x2C +#define NPCM_FIU_UMA_DR0 0x30 +#define NPCM_FIU_UMA_DR1 0x34 +#define NPCM_FIU_UMA_DR2 0x38 +#define NPCM_FIU_UMA_DR3 0x3C +#define NPCM_FIU_MAX_REG_LIMIT 0x80 + +/* FIU Direct Read Configuration Register */ +#define NPCM_FIU_DRD_CFG_LCK BIT(31) +#define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24) +#define NPCM_FIU_DRD_CFG_ADDSIZGENMASK(17, 16) +#define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12) +#define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8) +#define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0) +#define NPCM_FIU_DRD_ADDSIZ_SHIFT 16 +#define NPCM_FIU_DRD_DBW_SHIFT 12 +#define NPCM_FIU_DRD_ACCTYPE_SHIFT 8 + +/* FIU Direct Write Configuration Register */ +#define NPCM_FIU_DWR_CFG_LCK BIT(31) +#define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24) +#define NPCM_FIU_DWR_CFG_ADDSIZGENMASK(17, 16) +#define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10) +#define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8) +#define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0) +#define NPCM_FIU_DWR_ADDSIZ_SHIFT 16 +#define NPCM_FIU_DWR_ABPCK_SHIFT 10 +#define NPCM_FIU_DWR_DBPCK_SHIFT 8 + +/* FIU UMA Configuration Register */ +#define NPCM_FIU_UMA_CFG_LCK BIT(31) +#define NPCM_FIU_UMA_CFG_CMMLCKBIT(30) +#define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24) +#define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21) +#define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16) +#define NPCM_FIU_UMA_CFG_ADDSIZGENMASK(13, 11) +#define NPCM_FIU_UMA_CFG_CMDSIZBIT(10) +#define NPCM_FIU_UMA_CFG_RDBPCKGENMASK(9, 8) +#define NPCM_FIU_UMA_CFG_DBPCK
[PATCH v2 1/2] dt-binding: spi: add NPCM FIU controller
Added device tree binding documentation for Nuvoton BMC
NPCM Flash Interface Unit(FIU) SPI master controller
using SPI-MEM interface.
Signed-off-by: Tomer Maimon
---
.../bindings/spi/nuvoton,npcm-fiu.txt | 47 +++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
new file mode 100644
index ..ab37aae91d19
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
@@ -0,0 +1,47 @@
+* Nuvoton FLASH Interface Unit (FIU) SPI Controller
+
+NPCM FIU supports single, dual and quad communication interface.
+
+The NPCM7XX supports three FIU modules,
+FIU0 and FIUx supports two chip selects,
+FIU3 support four chip select.
+
+Required properties:
+ - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
+ - #address-cells : should be 1.
+ - #size-cells : should be 0.
+ - reg : the first contains the register location and length,
+ the second contains the memory mapping address and length
+ - reg-names: Should contain the reg names "control" and "memory"
+ - clocks : phandle of FIU reference clock.
+
+Required properties in case the pins can be muxed:
+ - pinctrl-names : a pinctrl state named "default" must be defined.
+ - pinctrl-0 : phandle referencing pin configuration of the device.
+
+Optional property:
+ - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.
+
+Aliases:
+- All the FIU controller nodes should be represented in the aliases node using
+ the following format 'fiu{n}' where n is a unique number for the alias.
+ In the NPCM7XX BMC:
+ fiu0 represent fiu 0 controller
+ fiu1 represent fiu 3 controller
+ fiu2 represent fiu x controller
+
+Example:
+fiu3: fiu@c {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfb00 0x1000>, <0x8000 0x1000>;
+ reg-names = "control", "memory";
+ clocks = < NPCM7XX_CLK_AHB>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ spi-nor@0 {
+ ...
+ };
+};
+
--
2.18.0
[PATCH v2 0/2] spi: add NPCM FIU controller driver
This patch set adds Flash Interface Unit(FIU) SPI master support for the Nuvoton NPCM Baseboard Management Controller (BMC). The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. The NPCM750/730/715/710 supports up to three FIU devices: - FIU0 supports two chip select. - FIU3 supports four chip select. - FIUX supports two chip select. The NPCM FIU driver tested on NPCM750 evaluation board. The FIU controller driver using direct map API SPI-MEM interface and tested with the latest m25p80 driver patch https://www.spinics.net/lists/linux-mtd/msg07358.html According a conversion about direct SPI-MEM API https://www.spinics.net/lists/linux-mtd/msg08225.html The m25p80 driver will merge to the spi-nor driver we need to make sure the m25p80 direct SPI-MEM will merge as well. The FIU controller driver tested with the latest spi-nor driver patch https://www.spinics.net/lists/linux-mtd/msg08472.html Changes since version 1: - Support spi-mem no data transferred option (SPI_MEM_NO_DATA) Tomer Maimon (2): dt-binding: spi: add NPCM FIU controller spi: npcm-fiu: add NPCM FIU controller driver .../bindings/spi/nuvoton,npcm-fiu.txt | 47 ++ drivers/spi/Kconfig | 10 + drivers/spi/Makefile | 1 + drivers/spi/spi-npcm-fiu.c| 761 ++ 4 files changed, 819 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt create mode 100644 drivers/spi/spi-npcm-fiu.c -- 2.18.0
[PATCH v2 2/2] spi: npcm-fiu: add NPCM FIU controller driver
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master controller driver using SPI-MEM interface. The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. Signed-off-by: Tomer Maimon --- drivers/spi/Kconfig| 10 + drivers/spi/Makefile | 1 + drivers/spi/spi-npcm-fiu.c | 761 + 3 files changed, 772 insertions(+) create mode 100644 drivers/spi/spi-npcm-fiu.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3a1d8f1170de..6ee514fd0920 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -433,6 +433,16 @@ config SPI_MT7621 help This selects a driver for the MediaTek MT7621 SPI Controller. +config SPI_NPCM_FIU + tristate "Nuvoton NPCM FLASH Interface Unit" + depends on ARCH_NPCM || COMPILE_TEST + depends on OF && HAS_IOMEM + help + This enables support for the Flash Interface Unit SPI controller + in master mode. + This driver does not support generic SPI. The implementation only + supports spi-mem interface. + config SPI_NPCM_PSPI tristate "Nuvoton NPCM PSPI Controller" depends on ARCH_NPCM || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 63dcab552bcb..adbebee93a75 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o obj-$(CONFIG_SPI_MXIC) += spi-mxic.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o +obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o obj-$(CONFIG_SPI_NPCM_PSPI)+= spi-npcm-pspi.o obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o diff --git a/drivers/spi/spi-npcm-fiu.c b/drivers/spi/spi-npcm-fiu.c new file mode 100644 index ..2d8c281e8fa9 --- /dev/null +++ b/drivers/spi/spi-npcm-fiu.c @@ -0,0 +1,761 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Nuvoton Technology corporation. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* NPCM7xx GCR module */ +#define NPCM7XX_INTCR3_OFFSET 0x9C +#define NPCM7XX_INTCR3_FIU_FIX BIT(6) + +/* Flash Interface Unit (FIU) Registers */ +#define NPCM_FIU_DRD_CFG 0x00 +#define NPCM_FIU_DWR_CFG 0x04 +#define NPCM_FIU_UMA_CFG 0x08 +#define NPCM_FIU_UMA_CTS 0x0C +#define NPCM_FIU_UMA_CMD 0x10 +#define NPCM_FIU_UMA_ADDR 0x14 +#define NPCM_FIU_PRT_CFG 0x18 +#define NPCM_FIU_UMA_DW0 0x20 +#define NPCM_FIU_UMA_DW1 0x24 +#define NPCM_FIU_UMA_DW2 0x28 +#define NPCM_FIU_UMA_DW3 0x2C +#define NPCM_FIU_UMA_DR0 0x30 +#define NPCM_FIU_UMA_DR1 0x34 +#define NPCM_FIU_UMA_DR2 0x38 +#define NPCM_FIU_UMA_DR3 0x3C +#define NPCM_FIU_MAX_REG_LIMIT 0x80 + +/* FIU Direct Read Configuration Register */ +#define NPCM_FIU_DRD_CFG_LCK BIT(31) +#define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24) +#define NPCM_FIU_DRD_CFG_ADDSIZGENMASK(17, 16) +#define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12) +#define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8) +#define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0) +#define NPCM_FIU_DRD_ADDSIZ_SHIFT 16 +#define NPCM_FIU_DRD_DBW_SHIFT 12 +#define NPCM_FIU_DRD_ACCTYPE_SHIFT 8 + +/* FIU Direct Write Configuration Register */ +#define NPCM_FIU_DWR_CFG_LCK BIT(31) +#define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24) +#define NPCM_FIU_DWR_CFG_ADDSIZGENMASK(17, 16) +#define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10) +#define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8) +#define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0) +#define NPCM_FIU_DWR_ADDSIZ_SHIFT 16 +#define NPCM_FIU_DWR_ABPCK_SHIFT 10 +#define NPCM_FIU_DWR_DBPCK_SHIFT 8 + +/* FIU UMA Configuration Register */ +#define NPCM_FIU_UMA_CFG_LCK BIT(31) +#define NPCM_FIU_UMA_CFG_CMMLCKBIT(30) +#define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24) +#define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21) +#define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16) +#define NPCM_FIU_UMA_CFG_ADDSIZGENMASK(13, 11) +#define NPCM_FIU_UMA_CFG_CMDSIZBIT(10) +#define NPCM_FIU_UMA_CFG_RDBPCKGENMASK(9, 8) +#define NPCM_FIU_UMA_CFG_DBPCK
[PATCH v1 1/2] dt-binding: spi: add NPCM FIU controller
Added device tree binding documentation for Nuvoton BMC
NPCM Flash Interface Unit(FIU) SPI master controller
using SPI-MEM interface.
Signed-off-by: Tomer Maimon
---
.../bindings/spi/nuvoton,npcm-fiu.txt | 47 +++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
new file mode 100644
index ..ab37aae91d19
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
@@ -0,0 +1,47 @@
+* Nuvoton FLASH Interface Unit (FIU) SPI Controller
+
+NPCM FIU supports single, dual and quad communication interface.
+
+The NPCM7XX supports three FIU modules,
+FIU0 and FIUx supports two chip selects,
+FIU3 support four chip select.
+
+Required properties:
+ - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
+ - #address-cells : should be 1.
+ - #size-cells : should be 0.
+ - reg : the first contains the register location and length,
+ the second contains the memory mapping address and length
+ - reg-names: Should contain the reg names "control" and "memory"
+ - clocks : phandle of FIU reference clock.
+
+Required properties in case the pins can be muxed:
+ - pinctrl-names : a pinctrl state named "default" must be defined.
+ - pinctrl-0 : phandle referencing pin configuration of the device.
+
+Optional property:
+ - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.
+
+Aliases:
+- All the FIU controller nodes should be represented in the aliases node using
+ the following format 'fiu{n}' where n is a unique number for the alias.
+ In the NPCM7XX BMC:
+ fiu0 represent fiu 0 controller
+ fiu1 represent fiu 3 controller
+ fiu2 represent fiu x controller
+
+Example:
+fiu3: fiu@c {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfb00 0x1000>, <0x8000 0x1000>;
+ reg-names = "control", "memory";
+ clocks = < NPCM7XX_CLK_AHB>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ spi-nor@0 {
+ ...
+ };
+};
+
--
2.18.0
[PATCH v1 0/2] spi: add NPCM FIU controller driver
This patch set adds Flash Interface Unit(FIU) SPI master support for the Nuvoton NPCM Baseboard Management Controller (BMC). The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. The NPCM750/730/715/710 supports up to three FIU devices: - FIU0 supports two chip select. - FIU3 supports four chip select. - FIUX supports two chip select. The NPCM FIU driver tested on NPCM750 evaluation board. The FIU controller driver using direct map API SPI-MEM interface and tested with the latest m25p80 driver patch https://www.spinics.net/lists/linux-mtd/msg07358.html According a conversion about direct SPI-MEM API https://www.spinics.net/lists/linux-mtd/msg08225.html The m25p80 driver will merge to the spi-nor driver we need to make sure the m25p80 direct SPI-MEM will merge as well. Tomer Maimon (2): dt-binding: spi: add NPCM FIU controller spi: npcm-fiu: add NPCM FIU controller driver .../bindings/spi/nuvoton,npcm-fiu.txt | 47 ++ drivers/spi/Kconfig | 10 + drivers/spi/Makefile | 1 + drivers/spi/spi-npcm-fiu.c| 760 ++ 4 files changed, 818 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt create mode 100644 drivers/spi/spi-npcm-fiu.c -- 2.18.0
[PATCH v1 2/2] spi: npcm-fiu: add NPCM FIU controller driver
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master controller driver using SPI-MEM interface. The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. Signed-off-by: Tomer Maimon --- drivers/spi/Kconfig| 10 + drivers/spi/Makefile | 1 + drivers/spi/spi-npcm-fiu.c | 760 + 3 files changed, 771 insertions(+) create mode 100644 drivers/spi/spi-npcm-fiu.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3a1d8f1170de..6ee514fd0920 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -433,6 +433,16 @@ config SPI_MT7621 help This selects a driver for the MediaTek MT7621 SPI Controller. +config SPI_NPCM_FIU + tristate "Nuvoton NPCM FLASH Interface Unit" + depends on ARCH_NPCM || COMPILE_TEST + depends on OF && HAS_IOMEM + help + This enables support for the Flash Interface Unit SPI controller + in master mode. + This driver does not support generic SPI. The implementation only + supports spi-mem interface. + config SPI_NPCM_PSPI tristate "Nuvoton NPCM PSPI Controller" depends on ARCH_NPCM || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 63dcab552bcb..adbebee93a75 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o obj-$(CONFIG_SPI_MXIC) += spi-mxic.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o +obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o obj-$(CONFIG_SPI_NPCM_PSPI)+= spi-npcm-pspi.o obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o diff --git a/drivers/spi/spi-npcm-fiu.c b/drivers/spi/spi-npcm-fiu.c new file mode 100644 index ..c175c6571237 --- /dev/null +++ b/drivers/spi/spi-npcm-fiu.c @@ -0,0 +1,760 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Nuvoton Technology corporation. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* NPCM7xx GCR module */ +#define NPCM7XX_INTCR3_OFFSET 0x9C +#define NPCM7XX_INTCR3_FIU_FIX BIT(6) + +/* Flash Interface Unit (FIU) Registers */ +#define NPCM_FIU_DRD_CFG 0x00 +#define NPCM_FIU_DWR_CFG 0x04 +#define NPCM_FIU_UMA_CFG 0x08 +#define NPCM_FIU_UMA_CTS 0x0C +#define NPCM_FIU_UMA_CMD 0x10 +#define NPCM_FIU_UMA_ADDR 0x14 +#define NPCM_FIU_PRT_CFG 0x18 +#define NPCM_FIU_UMA_DW0 0x20 +#define NPCM_FIU_UMA_DW1 0x24 +#define NPCM_FIU_UMA_DW2 0x28 +#define NPCM_FIU_UMA_DW3 0x2C +#define NPCM_FIU_UMA_DR0 0x30 +#define NPCM_FIU_UMA_DR1 0x34 +#define NPCM_FIU_UMA_DR2 0x38 +#define NPCM_FIU_UMA_DR3 0x3C +#define NPCM_FIU_MAX_REG_LIMIT 0x80 + +/* FIU Direct Read Configuration Register */ +#define NPCM_FIU_DRD_CFG_LCK BIT(31) +#define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24) +#define NPCM_FIU_DRD_CFG_ADDSIZGENMASK(17, 16) +#define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12) +#define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8) +#define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0) +#define NPCM_FIU_DRD_ADDSIZ_SHIFT 16 +#define NPCM_FIU_DRD_DBW_SHIFT 12 +#define NPCM_FIU_DRD_ACCTYPE_SHIFT 8 + +/* FIU Direct Write Configuration Register */ +#define NPCM_FIU_DWR_CFG_LCK BIT(31) +#define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24) +#define NPCM_FIU_DWR_CFG_ADDSIZGENMASK(17, 16) +#define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10) +#define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8) +#define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0) +#define NPCM_FIU_DWR_ADDSIZ_SHIFT 16 +#define NPCM_FIU_DWR_ABPCK_SHIFT 10 +#define NPCM_FIU_DWR_DBPCK_SHIFT 8 + +/* FIU UMA Configuration Register */ +#define NPCM_FIU_UMA_CFG_LCK BIT(31) +#define NPCM_FIU_UMA_CFG_CMMLCKBIT(30) +#define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24) +#define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21) +#define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16) +#define NPCM_FIU_UMA_CFG_ADDSIZGENMASK(13, 11) +#define NPCM_FIU_UMA_CFG_CMDSIZBIT(10) +#define NPCM_FIU_UMA_CFG_RDBPCKGENMASK(9, 8) +#define NPCM_FIU_UMA_CFG_DBPCK
[RFC v1 3/3] mtd: m25p80: add get Flash size callback support
Add get Flash size function support for
passing Flash size through callback use
to the spi layer.
Add get Flash size function support
Signed-off-by: Tomer Maimon
---
drivers/mtd/devices/m25p80.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index c50888670250..fd14c8c6d8d8 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -151,6 +151,15 @@ static ssize_t m25p80_read(struct spi_nor *nor, loff_t
from, size_t len,
return len;
}
+/* Sending Flash size thourgh callback function to spi layer */
+size_t m25p80_get_flash_size(void *param)
+{
+ struct spi_mem *spimem = param;
+ struct m25p *flash = spi_mem_get_drvdata(spimem);
+
+ return (u32)(flash->spi_nor.mtd.size >> 10) * 1024;
+}
+
/*
* board specific setup should have ensured the SPI clock used here
* matches what the READ command supports, at least until this driver
@@ -188,6 +197,9 @@ static int m25p_probe(struct spi_mem *spimem)
spi_nor_set_flash_node(nor, spi->dev.of_node);
nor->priv = flash;
+ spimem->callback = m25p80_get_flash_size;
+ spimem->callback_param = spimem;
+
spi_mem_set_drvdata(spimem, flash);
flash->spimem = spimem;
--
2.18.0
[RFC v1 1/3] spi: spi-mem: add spi-mem setup function
Add spi-mem setup function support SPI memory
operations the spi-mem setup function running
after the spi-mem probe function if the spi-mem
setup function implemented.
Signed-off-by: Tomer Maimon
---
drivers/spi/spi-mem.c | 27 ++-
include/linux/spi/spi-mem.h | 4
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 9f0fa9f3116d..21fe3a75d636 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -398,6 +398,26 @@ const char *spi_mem_get_name(struct spi_mem *mem)
}
EXPORT_SYMBOL_GPL(spi_mem_get_name);
+/**
+ * spi_mem_setup() - Execute spi memory setup
+ * @mem: the SPI memory
+ *
+ * This function allows SPI mem users to execute spi memory
+ * setup after the probe finished.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int spi_mem_setup(struct spi_mem *mem)
+{
+ struct spi_controller *ctlr = mem->spi->controller;
+
+ if (ctlr->mem_ops && ctlr->mem_ops->setup)
+ return ctlr->mem_ops->setup(mem);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(spi_mem_setup);
+
/**
* spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation to
* match controller limitations
@@ -723,6 +743,7 @@ static int spi_mem_probe(struct spi_device *spi)
struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
struct spi_controller *ctlr = spi->controller;
struct spi_mem *mem;
+ int ret;
mem = devm_kzalloc(>dev, sizeof(*mem), GFP_KERNEL);
if (!mem)
@@ -740,7 +761,11 @@ static int spi_mem_probe(struct spi_device *spi)
spi_set_drvdata(spi, mem);
- return memdrv->probe(mem);
+ ret = memdrv->probe(mem);
+ if (ret)
+ return ret;
+
+ return spi_mem_setup(mem);
}
static int spi_mem_remove(struct spi_device *spi)
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index af9ff2f0f1b2..5f7d20bd2b09 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -222,6 +222,7 @@ static inline void *spi_mem_get_drvdata(struct spi_mem *mem)
* Note that if the implementation of this function allocates memory
* dynamically, then it should do so with devm_xxx(), as we don't
* have a ->free_name() function.
+ * @setup: execute a SPI memory setup
* @dirmap_create: create a direct mapping descriptor that can later be used to
*access the memory device. This method is optional
* @dirmap_destroy: destroy a memory descriptor previous created by
@@ -256,6 +257,7 @@ struct spi_controller_mem_ops {
int (*exec_op)(struct spi_mem *mem,
const struct spi_mem_op *op);
const char *(*get_name)(struct spi_mem *mem);
+ int (*setup)(struct spi_mem *mem);
int (*dirmap_create)(struct spi_mem_dirmap_desc *desc);
void (*dirmap_destroy)(struct spi_mem_dirmap_desc *desc);
ssize_t (*dirmap_read)(struct spi_mem_dirmap_desc *desc,
@@ -334,6 +336,8 @@ int spi_mem_exec_op(struct spi_mem *mem,
const char *spi_mem_get_name(struct spi_mem *mem);
+int spi_mem_setup(struct spi_mem *mem);
+
struct spi_mem_dirmap_desc *
spi_mem_dirmap_create(struct spi_mem *mem,
const struct spi_mem_dirmap_info *info);
--
2.18.0
[RFC v1 0/3] *spi-mem: adding setup and callback function
Lately we have working on Flash interface unit (FIU) SPI driver that using spi-mem interface, Our FIU HW module support direct Flash Rd//Wr. In our SOC (32 bit dual core ARM) we have 3 FIU's that using memory mapping as follow: FIU0 - have 2 chip select and each one have 128MB memory mapping (total 256MB memory mapping) FIU1 - have 4 chip select and each one have 128MB memory mapping (total 512MB memory mapping) FIU2 - have 4 chip select and each one have 16MB memory mapping (total 32MB memory mapping) Totally 800MB memory mapping. When the FIU driver probe it don't know the size of each Flash that connected to the FIU, so the entire memory mapping is allocated for each FIU according the FIU device tree memory map parameters. It means, if we enable all three FIU's the drivers will try to allocate totally 800MB. In 32bit system it is problematic because the kernel have only 1GB of memory allocation so the vmalloc cannot take 800MB. When implementing the FIU driver in the mtd/spi-nor we allocating memory address only for detected Flash with exact size (usually we are not using 128MB Flash), and in that case usually we allocating much less memory. To solve this issue we needed to overcome two things: 1. Get argument from the upper layer (spi-mem layer) 2. Calling the get argument function after SPI_NOR_SCAN function. (the MTD Flash size filled in SPI_NOR_SCAN function) The attach patch set solving the describe issue by: 1. Add spi-mem callback function and value to the SPI device for passing an argument from the spi-mem layer to the spi layer 2. Add spi-mem setup function to the spi-memory operation that running after the spi-mem probe finished. 3. Implement function callback in the m25p80 driver that execute get Flash size. The patch set tested on NPCM750 EVB with FIU driver (implemented with SPI-MEM interface). Thanks for your attention. Tomer Tomer Maimon (3): spi: spi-mem: add spi-mem setup function spi: spi-mem: add callback function to spi-mem device mtd: m25p80: add get Flash size callback support drivers/mtd/devices/m25p80.c | 12 drivers/spi/spi-mem.c| 27 ++- include/linux/spi/spi-mem.h | 11 +++ 3 files changed, 49 insertions(+), 1 deletion(-) -- 2.18.0
[RFC v1 2/3] spi: spi-mem: add callback function to spi-mem device
Add callback function support to the spi-mem device
for passing an argument from the spi-mem layer
to the spi layer.
Signed-off-by: Tomer Maimon
---
include/linux/spi/spi-mem.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index 5f7d20bd2b09..b9841a9030be 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -13,6 +13,8 @@
#include
+typedef size_t (*spi_mem_callback)(void *spi_mem_param);
+
#define SPI_MEM_OP_CMD(__opcode, __buswidth) \
{ \
.buswidth = __buswidth, \
@@ -172,6 +174,9 @@ struct spi_mem_dirmap_desc {
* @spi: the underlying SPI device
* @drvpriv: spi_mem_driver private data
* @name: name of the SPI memory device
+ * @callback: routine for passing an argument from the
+ *spi-mem layer to the spi layer.
+ * @callback_param: general parameter to pass to the callback routine
*
* Extra information that describe the SPI memory device and may be needed by
* the controller to properly handle this device should be placed here.
@@ -183,6 +188,8 @@ struct spi_mem {
struct spi_device *spi;
void *drvpriv;
const char *name;
+ spi_mem_callback callback;
+ void *callback_param;
};
/**
--
2.18.0
[PATCH v1 1/2] dt-binding: soc: Add common LPC snoop documentation
Added device tree binding documentation for Nuvoton BMC
NPCM BIOS Post Code (BPC) and Aspeed AST2500 LPC snoop.
The LPC snoop monitoring two configurable I/O addresses
written by the host on Low Pin Count (LPC) bus.
Signed-off-by: Tomer Maimon
Reviewed-by: Andrew Jeffery
Reviewed-by: Rob Herring
---
.../devicetree/bindings/soc/lpc/lpc-snoop.txt | 27 +++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/lpc/lpc-snoop.txt
diff --git a/Documentation/devicetree/bindings/soc/lpc/lpc-snoop.txt
b/Documentation/devicetree/bindings/soc/lpc/lpc-snoop.txt
new file mode 100644
index ..c21cb8df4ffb
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/lpc/lpc-snoop.txt
@@ -0,0 +1,27 @@
+LPC snoop interface
+
+The LPC snoop (BIOS Post Code) interface can monitor
+two configurable I/O addresses written by the host on
+the Low Pin Count (LPC) bus.
+
+Nuvoton NPCM7xx LPC snoop supports capture double words,
+when using capture double word only I/O address 1 is monitored.
+
+Required properties for lpc-snoop node
+- compatible : "nuvoton,npcm750-lpc-bpc-snoop" for Poleg NPCM7XX
+ "aspeed,ast2500-lpc-snoop" for Aspeed AST2500.
+- reg : specifies physical base address and size of the registers.
+- interrupts : contain the LPC snoop interrupt with flags for falling edge.
+- snoop-ports : contain monitor I/O addresses, at least one monitor I/O
+ address required
+
+Optional property for NPCM7xx lpc-snoop node
+- nuvoton,lpc-en-dwcapture : enable capture double words support.
+
+Example:
+ lpc-snoop: lpc_snoop@f0007040 {
+ compatible = "nuvoton,npcm750-lpc-bpc-snoop";
+ reg = <0xf0007040 0x14>;
+ snoop-ports = <0x80>;
+ interrupts = ;
+ };
--
2.18.0
[PATCH v1 2/2] soc: nuvoton: add NPCM LPC BPC driver
Add Nuvoton BMC NPCM BIOS post code (BPC) driver.
The NPCM BPC monitoring two I/O address written by
the host on the Low Pin Count (LPC) bus, the capure
data stored in 128-word FIFO.
Signed-off-by: Tomer Maimon
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/nuvoton/Kconfig | 16 +
drivers/soc/nuvoton/Makefile | 2 +
drivers/soc/nuvoton/npcm-lpc-bpc-snoop.c | 387 +++
5 files changed, 407 insertions(+)
create mode 100644 drivers/soc/nuvoton/Kconfig
create mode 100644 drivers/soc/nuvoton/Makefile
create mode 100644 drivers/soc/nuvoton/npcm-lpc-bpc-snoop.c
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 833e04a7835c..9a04c7208f8f 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -10,6 +10,7 @@ source "drivers/soc/fsl/Kconfig"
source "drivers/soc/imx/Kconfig"
source "drivers/soc/ixp4xx/Kconfig"
source "drivers/soc/mediatek/Kconfig"
+source "drivers/soc/nuvoton/Kconfig"
source "drivers/soc/qcom/Kconfig"
source "drivers/soc/renesas/Kconfig"
source "drivers/soc/rockchip/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 524ecdc2a9bb..75018b656412 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_MXC)+= imx/
obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/
obj-$(CONFIG_SOC_XWAY) += lantiq/
obj-y += mediatek/
+obj-$(CONFIG_SOC_NUVOTON) += nuvoton/
obj-y += amlogic/
obj-y += qcom/
obj-y += renesas/
diff --git a/drivers/soc/nuvoton/Kconfig b/drivers/soc/nuvoton/Kconfig
new file mode 100644
index ..5490e2e5dade
--- /dev/null
+++ b/drivers/soc/nuvoton/Kconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menu "Nuvoton NPCM BMC SoC drivers"
+
+config SOC_NUVOTON
+ def_bool y
+ depends on ARCH_NPCM || COMPILE_TEST
+
+config NPCM_LPC_BPC_SNOOP
+ tristate "NPCM LPC BIOS Post Code snoop support"
+ depends on (SOC_NUVOTON || COMPILE_TEST)
+ help
+ Provides a NPCM BMC driver to control the LPC BIOS Post Code
+ interface which allows the BMC to monitoring and save
+ the data written by the host to an arbitrary LPC I/O port.
+
+endmenu
diff --git a/drivers/soc/nuvoton/Makefile b/drivers/soc/nuvoton/Makefile
new file mode 100644
index ..ffd0fb05d021
--- /dev/null
+++ b/drivers/soc/nuvoton/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_NPCM_LPC_BPC_SNOOP) += npcm-lpc-bpc-snoop.o
diff --git a/drivers/soc/nuvoton/npcm-lpc-bpc-snoop.c
b/drivers/soc/nuvoton/npcm-lpc-bpc-snoop.c
new file mode 100644
index ..32c7fa254cc1
--- /dev/null
+++ b/drivers/soc/nuvoton/npcm-lpc-bpc-snoop.c
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2014-2018 Nuvoton Technology corporation.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DEVICE_NAME"npcm-lpc-bpc"
+
+/* BIOS POST Code FIFO Registers */
+#define NPCM_BPCFA2L_REG 0x2 //BIOS POST Code FIFO Address 2 LSB
+#define NPCM_BPCFA2M_REG 0x4 //BIOS POST Code FIFO Address 2 MSB
+#define NPCM_BPCFEN_REG0x6 //BIOS POST Code FIFO Enable
+#define NPCM_BPCFSTAT_REG 0x8 //BIOS POST Code FIFO Status
+#define NPCM_BPCFDATA_REG 0xA //BIOS POST Code FIFO Data
+#define NPCM_BPCFMSTAT_REG 0xC //BIOS POST Code FIFO Miscellaneous Status
+#define NPCM_BPCFA1L_REG 0x10 //BIOS POST Code FIFO Address 1 LSB
+#define NPCM_BPCFA1M_REG 0x12 //BIOS POST Code FIFO Address 1 MSB
+
+/*BIOS regiser data*/
+#define FIFO_IOADDR1_ENABLE0x80
+#define FIFO_IOADDR2_ENABLE0x40
+
+/* BPC interface package and structure definition */
+#define BPC_KFIFO_SIZE 0x400
+
+/*BPC regiser data*/
+#define FIFO_DATA_VALID0x80
+#define FIFO_OVERFLOW 0x20
+#define FIFO_READY_INT_ENABLE 0x8
+#define FIFO_DWCAPTURE 0x4
+#define FIFO_ADDR_DECODE 0x1
+
+/*Host Reset*/
+#define HOST_RESET_INT_ENABLE 0x10
+#define HOST_RESET_CHANGED 0x40
+
+#define NUM_BPC_CHANNELS 2
+#define DW_PAD_SIZE3
+
+struct npcm_bpc_channel {
+ struct miscdevice miscdev;
+ wait_queue_head_t wq;
+ struct npcm_bpc *data;
+ struct kfifofifo;
+ boolhost_reset;
+};
+
+struct npcm_bpc {
+ struct npcm_bpc_channel ch[NUM_BPC_CHANNELS];
+ void __iomem*base;
+ int irq;
+ boolen_dwcap;
+};
+
+static struct npcm_bpc_channel *npcm_file_to_ch(struct file *file)
+{
+ return container_of(file->private_da
[PATCH v1 0/2] soc: add NPCM LPC BPC driver support
This patch set adds LPC BIOS Post code (BPC) support for the Nuvoton NPCM Baseboard Management Controller (BMC). Nuvoton BMC NPCM LPC BIOS Post Code (BPC) monitoring two configurable I/O addresses written by the host on the Low Pin Count (LPC) bus, the capture data stored in 128-word FIFO. NPCM BPC can support capture double words. The NPCM7xx BPC driver tested on NPCM750 evaluation board. NPCM BPC driver upstream process start few months ago on misc folder http://lkml.iu.edu/hypermail/linux/kernel/1904.2/00412.html The NPCM LPC BPC is similar to Aspeed LPC snoop, last kernel 5.0.2 Aspeed LPC snoop driver moved from misc folder to soc folder, so it seems NPCM BPC dirver should upstream to soc as well. https://lkml.org/lkml/2019/4/22/377 I have created common lpc-snoop documentation for both Nuvoton and Aspeed drivers as Andrew suggested. Andrew Jeffery: https://patchwork.kernel.org/patch/10506269/ I add Andrew and Rob reviewed signature because they already reviewed and signed the lpc-snoop documentation in the misc folder https://lkml.org/lkml/2019/4/29/998 Tomer Maimon (2): dt-binding: soc: Add common LPC snoop documentation soc: nuvoton: add NPCM LPC BPC driver .../devicetree/bindings/soc/lpc/lpc-snoop.txt | 27 ++ drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/nuvoton/Kconfig | 16 + drivers/soc/nuvoton/Makefile | 2 + drivers/soc/nuvoton/npcm-lpc-bpc-snoop.c | 387 ++ 6 files changed, 434 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/lpc/lpc-snoop.txt create mode 100644 drivers/soc/nuvoton/Kconfig create mode 100644 drivers/soc/nuvoton/Makefile create mode 100644 drivers/soc/nuvoton/npcm-lpc-bpc-snoop.c -- 2.18.0
[PATCH v1] iio: adc: modify NPCM ADC read reference voltage
Checking if regulator is valid before reading
NPCM ADC regulator voltage to avoid system crash
in a case the regulator is not valid.
Signed-off-by: Tomer Maimon
---
drivers/iio/adc/npcm_adc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/adc/npcm_adc.c b/drivers/iio/adc/npcm_adc.c
index 9e25bbec9c70..193b3b81de4d 100644
--- a/drivers/iio/adc/npcm_adc.c
+++ b/drivers/iio/adc/npcm_adc.c
@@ -149,7 +149,7 @@ static int npcm_adc_read_raw(struct iio_dev *indio_dev,
}
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
- if (info->vref) {
+ if (!IS_ERR(info->vref)) {
vref_uv = regulator_get_voltage(info->vref);
*val = vref_uv / 1000;
} else {
--
2.14.1
[PATCH v2 2/2] MAINTAINERS: Add maintainer and replacing reviewer ARM/NUVOTON NPCM
Adding Tali Perry as Nuvoton NPCM maintainer Replacing Brendan Higgins Nuvoton NPCM reviewer with Benjamin Fair. Signed-off-by: Tomer Maimon Reviewed-by: Brendan Higgins --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8b305d2f2a8a..4ece87fcc166 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1893,9 +1893,10 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git ARM/NUVOTON NPCM ARCHITECTURE M: Avi Fishman M: Tomer Maimon +M: Tali Perry R: Patrick Venture R: Nancy Yuen -R: Brendan Higgins +R: Benjamin Fair L: open...@lists.ozlabs.org (moderated for non-subscribers) S: Supported F: arch/arm/mach-npcm/ -- 2.14.1
[PATCH v2 1/2] MAINTAINERS: fix bad pattern in ARM/NUVOTON NPCM
In the process of upstreaming architecture support for ARM/NUVOTON NPCM
include/dt-bindings/clock/nuvoton,npcm7xx-clks.h was renamed
include/dt-bindings/clock/nuvoton,npcm7xx-clock.h without updating
MAINTAINERS. This updates the MAINTAINERS pattern to match the new name
of this file.
Fixes: 6a498e06ba22 ("MAINTAINERS: Add entry for the Nuvoton NPCM architecture")
Reported-by: Joe Perches
Signed-off-by: Brendan Higgins
Signed-off-by: Tomer Maimon
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3e5a5d263f29..8b305d2f2a8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1900,7 +1900,7 @@ L:open...@lists.ozlabs.org (moderated for
non-subscribers)
S: Supported
F: arch/arm/mach-npcm/
F: arch/arm/boot/dts/nuvoton-npcm*
-F: include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
+F: include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
F: drivers/*/*npcm*
F: Documentation/devicetree/bindings/*/*npcm*
F: Documentation/devicetree/bindings/*/*/*npcm*
--
2.14.1
[PATCH v1 1/2] MAINTAINERS: fix bad pattern in ARM/NUVOTON NPCM
In the process of upstreaming architecture support for ARM/NUVOTON NPCM
include/dt-bindings/clock/nuvoton,npcm7xx-clks.h was renamed
include/dt-bindings/clock/nuvoton,npcm7xx-clock.h without updating
MAINTAINERS. This updates the MAINTAINERS pattern to match the new name
of this file.
Fixes: 6a498e06ba22 ("MAINTAINERS: Add entry for the Nuvoton NPCM architecture")
Reported-by: Joe Perches
Signed-off-by: Brendan Higgins
Signed-off-by: Tomer Maimon
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3e5a5d263f29..8b305d2f2a8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1900,7 +1900,7 @@ L:open...@lists.ozlabs.org (moderated for
non-subscribers)
S: Supported
F: arch/arm/mach-npcm/
F: arch/arm/boot/dts/nuvoton-npcm*
-F: include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
+F: include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
F: drivers/*/*npcm*
F: Documentation/devicetree/bindings/*/*npcm*
F: Documentation/devicetree/bindings/*/*/*npcm*
--
2.14.1
[PATCH v1 2/2] MAINTAINERS: Add maintainer and replacing reviewer ARM/NUVOTON NPCM
Adding Tali Perry as Nuvoton NPCM maintainer Replacing Brendan Higgins Nuvoton NPCM reviewer with Benjamin Fair. Signed-off-by: Tomer Maimon --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8b305d2f2a8a..4ece87fcc166 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1893,9 +1893,10 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git ARM/NUVOTON NPCM ARCHITECTURE M: Avi Fishman M: Tomer Maimon +M: Tali Perry R: Patrick Venture R: Nancy Yuen -R: Brendan Higgins +R: Benjamin Fair L: open...@lists.ozlabs.org (moderated for non-subscribers) S: Supported F: arch/arm/mach-npcm/ -- 2.14.1
[PATCH v1 1/1] dt-binding: iio: remove rst node from NPCM ADC document
Remove NPCM7xx rst node for preparing the NPCM ADC
document to describe ADC reset binding.
Signed-off-by: Tomer Maimon
---
.../devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt | 11 ---
1 file changed, 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
index 1b8132cd9060..eb939fe77836 100644
--- a/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
@@ -14,11 +14,6 @@ Optional properties:
vref-supply is not added the ADC will use internal
voltage
reference.
-Required Node in the NPCM7xx BMC:
-An additional register is present in the NPCM7xx SOC which is
-assumed to be in the same device tree, with and marked as
-compatible with "nuvoton,npcm750-rst".
-
Example:
adc: adc@f000c000 {
@@ -27,9 +22,3 @@ adc: adc@f000c000 {
interrupts = ;
clocks = < NPCM7XX_CLK_ADC>;
};
-
-rst: rst@f0801000 {
- compatible = "nuvoton,npcm750-rst", "syscon",
- "simple-mfd";
- reg = <0xf0801000 0x6C>;
-};
--
2.14.1
[PATCH v3 2/2] iio: adc: add NPCM ADC driver
Add Nuvoton NPCM BMC Analog-to-Digital Converter(ADC) driver.
The NPCM ADC is a 10-bit converter for eight channel inputs.
Signed-off-by: Tomer Maimon
---
drivers/iio/adc/Kconfig| 10 ++
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/npcm_adc.c | 335 +
3 files changed, 346 insertions(+)
create mode 100644 drivers/iio/adc/npcm_adc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 7a3ca4ec0cb7..2d1e70a7d5c4 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -576,6 +576,16 @@ config NAU7802
To compile this driver as a module, choose M here: the
module will be called nau7802.
+config NPCM_ADC
+ tristate "Nuvoton NPCM ADC driver"
+ depends on ARCH_NPCM || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ Say yes here to build support for Nuvoton NPCM ADC.
+
+ This driver can also be built as a module. If so, the module
+ will be called npcm_adc.
+
config PALMAS_GPADC
tristate "TI Palmas General Purpose ADC"
depends on MFD_PALMAS
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 07df37f621bd..3337eb1f4c30 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
obj-$(CONFIG_MXS_LRADC_ADC) += mxs-lradc-adc.o
obj-$(CONFIG_NAU7802) += nau7802.o
+obj-$(CONFIG_NPCM_ADC) += npcm_adc.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o
obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
diff --git a/drivers/iio/adc/npcm_adc.c b/drivers/iio/adc/npcm_adc.c
new file mode 100644
index ..1cc377cdf1f7
--- /dev/null
+++ b/drivers/iio/adc/npcm_adc.c
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2019 Nuvoton Technology corporation.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct npcm_adc {
+ bool int_status;
+ u32 adc_sample_hz;
+ struct device *dev;
+ void __iomem *regs;
+ struct clk *adc_clk;
+ wait_queue_head_t wq;
+ struct regulator *vref;
+ struct regmap *rst_regmap;
+};
+
+/* NPCM7xx reset module */
+#define NPCM7XX_IPSRST1_OFFSET 0x020
+#define NPCM7XX_IPSRST1_ADC_RSTBIT(27)
+
+/* ADC registers */
+#define NPCM_ADCCON 0x00
+#define NPCM_ADCDATA0x04
+
+/* ADCCON Register Bits */
+#define NPCM_ADCCON_ADC_INT_EN BIT(21)
+#define NPCM_ADCCON_REFSEL BIT(19)
+#define NPCM_ADCCON_ADC_INT_ST BIT(18)
+#define NPCM_ADCCON_ADC_EN BIT(17)
+#define NPCM_ADCCON_ADC_RSTBIT(16)
+#define NPCM_ADCCON_ADC_CONV BIT(13)
+
+#define NPCM_ADCCON_CH_MASKGENMASK(27, 24)
+#define NPCM_ADCCON_CH(x) ((x) << 24)
+#define NPCM_ADCCON_DIV_SHIFT 1
+#define NPCM_ADCCON_DIV_MASK GENMASK(8, 1)
+#define NPCM_ADC_DATA_MASK(x) ((x) & GENMASK(9, 0))
+
+#define NPCM_ADC_ENABLE(NPCM_ADCCON_ADC_EN |
NPCM_ADCCON_ADC_INT_EN)
+
+/* ADC General Definition */
+#define NPCM_RESOLUTION_BITS 10
+#define NPCM_INT_VREF_MV 2000
+
+#define NPCM_ADC_CHAN(ch) {\
+ .type = IIO_VOLTAGE,\
+ .indexed = 1, \
+ .channel = ch, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
+}
+
+static const struct iio_chan_spec npcm_adc_iio_channels[] = {
+ NPCM_ADC_CHAN(0),
+ NPCM_ADC_CHAN(1),
+ NPCM_ADC_CHAN(2),
+ NPCM_ADC_CHAN(3),
+ NPCM_ADC_CHAN(4),
+ NPCM_ADC_CHAN(5),
+ NPCM_ADC_CHAN(6),
+ NPCM_ADC_CHAN(7),
+};
+
+static irqreturn_t npcm_adc_isr(int irq, void *data)
+{
+ u32 regtemp;
+ struct iio_dev *indio_dev = data;
+ struct npcm_adc *info = iio_priv(indio_dev);
+
+ regtemp = ioread32(info->regs + NPCM_ADCCON);
+ if (regtemp & NPCM_ADCCON_ADC_INT_ST) {
+ iowrite32(regtemp, info->regs + NPCM_ADCCON);
+ wake_up_interruptible(>wq);
+ info->int_status = true;
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int npcm_adc_read(struct npcm_adc *info, int *val, u8 channel)
+{
+ int ret;
+ u32 regtemp;
+
+ /* Select ADC channel */
+ regtemp = ioread32(info->regs + NPCM_ADCCON);
+ regtemp &= ~NPCM_ADCCON_CH_MASK;
+ info->int_status = false;
+ iowrite32(regtemp | NPCM_ADCCON_CH(channel) |
+ NPCM_A
[PATCH v3 0/2] iio: adc: npcm: add NPCM ADC driver
This patch set adds Analog-to-Digital Converter (ADC) support for the Nuvoton NPCM Baseboard Management Controller (BMC). The NPCM ADC is a 10-bit converter for eight channel inputs. The NPCM ADC driver tested on NPCM750 evaluation board. Addressed comments from:. - Jonathan Cameron: https://lore.kernel.org/patchwork/patch/1030483/ Changes since version 2: - Return error if clock have not found in the device tree ADC node. - Modify regulator order for avoid mixing devm and non-devm path. - Modify probe and remove function to have relative ordering. Changes since version 1: - Add NPCM prefix. - Remove unnecessary parameter initialization. - Modify read function to avoid racy condition. - Reading the reference voltage when needed. - Modify dt-binding documentation according Jonathan comments. Tomer Maimon (2): dt-binding: iio: add NPCM ADC documentation iio: adc: add NPCM ADC driver .../bindings/iio/adc/nuvoton,npcm-adc.txt | 35 +++ drivers/iio/adc/Kconfig| 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/npcm_adc.c | 335 + 4 files changed, 381 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt create mode 100644 drivers/iio/adc/npcm_adc.c -- 2.14.1
[PATCH v3 1/2] dt-binding: iio: add NPCM ADC documentation
Added device tree binding documentation for Nuvoton BMC
NPCM Analog-to-Digital Converter(ADC).
Signed-off-by: Tomer Maimon
Reviewed-by: Rob Herring
---
.../bindings/iio/adc/nuvoton,npcm-adc.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644
Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
new file mode 100644
index ..1b8132cd9060
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
@@ -0,0 +1,35 @@
+Nuvoton NPCM Analog to Digital Converter (ADC)
+
+The NPCM ADC is a 10-bit converter for eight channel inputs.
+
+Required properties:
+- compatible: "nuvoton,npcm750-adc" for the NPCM7XX BMC.
+- reg: specifies physical base address and size of the registers.
+- interrupts: Contain the ADC interrupt with flags for falling edge.
+
+Optional properties:
+- clocks: phandle of ADC reference clock, in case the clock is not
+ added the ADC will use the default ADC sample rate.
+- vref-supply: The regulator supply ADC reference voltage, in case the
+ vref-supply is not added the ADC will use internal
voltage
+ reference.
+
+Required Node in the NPCM7xx BMC:
+An additional register is present in the NPCM7xx SOC which is
+assumed to be in the same device tree, with and marked as
+compatible with "nuvoton,npcm750-rst".
+
+Example:
+
+adc: adc@f000c000 {
+ compatible = "nuvoton,npcm750-adc";
+ reg = <0xf000c000 0x8>;
+ interrupts = ;
+ clocks = < NPCM7XX_CLK_ADC>;
+};
+
+rst: rst@f0801000 {
+ compatible = "nuvoton,npcm750-rst", "syscon",
+ "simple-mfd";
+ reg = <0xf0801000 0x6C>;
+};
--
2.14.1
[PATCH v2 2/2] iio: adc: add NPCM ADC driver
Add Nuvoton NPCM BMC Analog-to-Digital Converter(ADC) driver.
The NPCM ADC is a 10-bit converter for eight channel inputs.
Signed-off-by: Tomer Maimon
---
drivers/iio/adc/Kconfig| 10 ++
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/npcm_adc.c | 338 +
3 files changed, 349 insertions(+)
create mode 100644 drivers/iio/adc/npcm_adc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 7a3ca4ec0cb7..2d1e70a7d5c4 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -576,6 +576,16 @@ config NAU7802
To compile this driver as a module, choose M here: the
module will be called nau7802.
+config NPCM_ADC
+ tristate "Nuvoton NPCM ADC driver"
+ depends on ARCH_NPCM || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ Say yes here to build support for Nuvoton NPCM ADC.
+
+ This driver can also be built as a module. If so, the module
+ will be called npcm_adc.
+
config PALMAS_GPADC
tristate "TI Palmas General Purpose ADC"
depends on MFD_PALMAS
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 07df37f621bd..3337eb1f4c30 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
obj-$(CONFIG_MXS_LRADC_ADC) += mxs-lradc-adc.o
obj-$(CONFIG_NAU7802) += nau7802.o
+obj-$(CONFIG_NPCM_ADC) += npcm_adc.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o
obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
diff --git a/drivers/iio/adc/npcm_adc.c b/drivers/iio/adc/npcm_adc.c
new file mode 100644
index ..c364f2dbd702
--- /dev/null
+++ b/drivers/iio/adc/npcm_adc.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2019 Nuvoton Technology corporation.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct npcm_adc {
+ bool int_status;
+ u32 adc_sample_hz;
+ struct device *dev;
+ void __iomem *regs;
+ struct clk *adc_clk;
+ wait_queue_head_t wq;
+ struct regulator *vref;
+ struct regmap *rst_regmap;
+};
+
+/* NPCM7xx reset module */
+#define NPCM7XX_IPSRST1_OFFSET 0x020
+#define NPCM7XX_IPSRST1_ADC_RSTBIT(27)
+
+/* ADC registers */
+#define NPCM_ADCCON 0x00
+#define NPCM_ADCDATA0x04
+
+/* ADCCON Register Bits */
+#define NPCM_ADCCON_ADC_INT_EN BIT(21)
+#define NPCM_ADCCON_REFSEL BIT(19)
+#define NPCM_ADCCON_ADC_INT_ST BIT(18)
+#define NPCM_ADCCON_ADC_EN BIT(17)
+#define NPCM_ADCCON_ADC_RSTBIT(16)
+#define NPCM_ADCCON_ADC_CONV BIT(13)
+
+#define NPCM_ADCCON_CH_MASKGENMASK(27, 24)
+#define NPCM_ADCCON_CH(x) ((x) << 24)
+#define NPCM_ADCCON_DIV_SHIFT 1
+#define NPCM_ADCCON_DIV_MASK GENMASK(8, 1)
+#define NPCM_ADC_DATA_MASK(x) ((x) & GENMASK(9, 0))
+
+#define NPCM_ADC_ENABLE(NPCM_ADCCON_ADC_EN |
NPCM_ADCCON_ADC_INT_EN)
+
+/* ADC General Definition */
+#define NPCM_RESOLUTION_BITS 10
+#define NPCM_ADC_DEFAULT_SAMPLE_RATE 1250
+#define NPCM_INT_VREF_MV 2000
+
+#define NPCM_ADC_CHAN(ch) {\
+ .type = IIO_VOLTAGE,\
+ .indexed = 1, \
+ .channel = ch, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
+}
+
+static const struct iio_chan_spec npcm_adc_iio_channels[] = {
+ NPCM_ADC_CHAN(0),
+ NPCM_ADC_CHAN(1),
+ NPCM_ADC_CHAN(2),
+ NPCM_ADC_CHAN(3),
+ NPCM_ADC_CHAN(4),
+ NPCM_ADC_CHAN(5),
+ NPCM_ADC_CHAN(6),
+ NPCM_ADC_CHAN(7),
+};
+
+static irqreturn_t npcm_adc_isr(int irq, void *data)
+{
+ u32 regtemp;
+ struct iio_dev *indio_dev = data;
+ struct npcm_adc *info = iio_priv(indio_dev);
+
+ regtemp = ioread32(info->regs + NPCM_ADCCON);
+ if (regtemp & NPCM_ADCCON_ADC_INT_ST) {
+ iowrite32(regtemp, info->regs + NPCM_ADCCON);
+ wake_up_interruptible(>wq);
+ info->int_status = true;
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int npcm_adc_read(struct npcm_adc *info, int *val, u8 channel)
+{
+ int ret;
+ u32 regtemp;
+
+ /* Select ADC channel */
+ regtemp = ioread32(info->regs + NPCM_ADCCON);
+ regtemp &= ~NPCM_ADCCON_CH_MASK;
+ info->int_status = false;
+ iowrite32(regtemp | NPCM_ADCCON_CH
[PATCH v2 1/2] dt-binding: iio: add NPCM ADC documentation
Added device tree binding documentation for Nuvoton BMC
NPCM Analog-to-Digital Converter(ADC).
Signed-off-by: Tomer Maimon
---
.../bindings/iio/adc/nuvoton,npcm-adc.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644
Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
new file mode 100644
index ..1b8132cd9060
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
@@ -0,0 +1,35 @@
+Nuvoton NPCM Analog to Digital Converter (ADC)
+
+The NPCM ADC is a 10-bit converter for eight channel inputs.
+
+Required properties:
+- compatible: "nuvoton,npcm750-adc" for the NPCM7XX BMC.
+- reg: specifies physical base address and size of the registers.
+- interrupts: Contain the ADC interrupt with flags for falling edge.
+
+Optional properties:
+- clocks: phandle of ADC reference clock, in case the clock is not
+ added the ADC will use the default ADC sample rate.
+- vref-supply: The regulator supply ADC reference voltage, in case the
+ vref-supply is not added the ADC will use internal
voltage
+ reference.
+
+Required Node in the NPCM7xx BMC:
+An additional register is present in the NPCM7xx SOC which is
+assumed to be in the same device tree, with and marked as
+compatible with "nuvoton,npcm750-rst".
+
+Example:
+
+adc: adc@f000c000 {
+ compatible = "nuvoton,npcm750-adc";
+ reg = <0xf000c000 0x8>;
+ interrupts = ;
+ clocks = < NPCM7XX_CLK_ADC>;
+};
+
+rst: rst@f0801000 {
+ compatible = "nuvoton,npcm750-rst", "syscon",
+ "simple-mfd";
+ reg = <0xf0801000 0x6C>;
+};
--
2.14.1
[PATCH v2 0/2] iio: adc: npcm: add NPCM ADC driver
This patch set adds Analog-to-Digital Converter (ADC) support for the Nuvoton NPCM Baseboard Management Controller (BMC). The NPCM ADC is a 10-bit converter for eight channel inputs. The NPCM ADC driver tested on NPCM750 evaluation board. Addressed comments from:. - Peter Meerwald-Stadler: https://www.spinics.net/lists/linux-iio/msg42159.html - Jonathan Cameron: https://www.spinics.net/lists/linux-iio/msg42183.html Changes since version 1: - Add NPCM prefix. - Remove unnecessary parameter initialization. - Modify read function to avoid racy condition. - Reading the reference voltage when needed. - Modify dt-binding documentation according Jonathan comments. Tomer Maimon (2): dt-binding: iio: add NPCM ADC documentation iio: adc: add NPCM ADC driver .../bindings/iio/adc/nuvoton,npcm-adc.txt | 35 +++ drivers/iio/adc/Kconfig| 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/npcm_adc.c | 338 + 4 files changed, 384 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt create mode 100644 drivers/iio/adc/npcm_adc.c -- 2.14.1
[PATCH v1 1/2] dt-binding: iio: add NPCM ADC documentation
Added device tree binding documentation for Nuvoton BMC
NPCM Analog-to-Digital Converter(ADC).
Signed-off-by: Tomer Maimon
---
.../bindings/iio/adc/nuvoton,npcm-adc.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644
Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
new file mode 100644
index ..6f0843d837cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
@@ -0,0 +1,35 @@
+Nuvoton NPCM Analog to Digital Converter (ADC)
+
+The NPCM ADC is a 10-bit converter for eight channel inputs.
+
+Required properties:
+- compatible : "nuvoton,npcm750-adc" for the NPCM7XX BMC.
+- reg : specifies physical base address and size of the
registers.
+- interrupts : Contain the ADC interrupt with flags for falling edge.
+
+Optional properties:
+- clocks : phandle of ADC reference clock, in case the clock is
not
+ added the ADC will use the default ADC sample
rate.
+- vref-supply : The regulator supply ADC reference voltage, in case the
+ vref-supply is not added the ADC will use
internal voltage
+ reference.
+
+Required Node in the NPCM7xx BMC:
+An additional register is present in the NPCM7xx SOC which is
+assumed to be in the same device tree, with and marked as
+compatible with "nuvoton,npcm750-rst".
+
+Example:
+
+adc: adc@f000c000 {
+ compatible = "nuvoton,npcm750-adc";
+ reg = <0xf000c000 0x8>;
+ interrupts = ;
+ clocks = < NPCM7XX_CLK_ADC>;
+};
+
+rst: rst@f0801000 {
+ compatible = "nuvoton,npcm750-rst", "syscon",
+ "simple-mfd";
+ reg = <0xf0801000 0x6C>;
+};
--
2.14.1
[PATCH v1 2/2] iio: adc: add NPCM ADC driver
Add Nuvoton NPCM BMC Analog-to-Digital Converter(ADC) driver.
The NPCM ADC is a 10-bit converter for eight channel inputs.
Signed-off-by: Tomer Maimon
---
drivers/iio/adc/Kconfig| 10 ++
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/npcm_adc.c | 336 +
3 files changed, 347 insertions(+)
create mode 100644 drivers/iio/adc/npcm_adc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index a52fea8749a9..63a4204c5673 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -555,6 +555,16 @@ config NAU7802
To compile this driver as a module, choose M here: the
module will be called nau7802.
+config NPCM_ADC
+ tristate "Nuvoton NPCM ADC driver"
+ depends on ARCH_NPCM || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ Say yes here to build support for Nuvoton NPCM ADC.
+
+ This driver can also be built as a module. If so, the module
+ will be called npcm_adc.
+
config PALMAS_GPADC
tristate "TI Palmas General Purpose ADC"
depends on MFD_PALMAS
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index a6e6a0b659e2..b0c3f3b73a5f 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
obj-$(CONFIG_MXS_LRADC_ADC) += mxs-lradc-adc.o
obj-$(CONFIG_NAU7802) += nau7802.o
+obj-$(CONFIG_NPCM_ADC) += npcm_adc.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o
obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
diff --git a/drivers/iio/adc/npcm_adc.c b/drivers/iio/adc/npcm_adc.c
new file mode 100644
index ..4f7851472997
--- /dev/null
+++ b/drivers/iio/adc/npcm_adc.c
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2016-2018 Nuvoton Technology corporation.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct npcm_adc {
+ u32 vref_mv;
+ bool int_status;
+ u32 adc_sample_hz;
+ struct device *dev;
+ void __iomem *regs;
+ struct clk *adc_clk;
+ wait_queue_head_t wq;
+ struct regulator *vref;
+ struct regmap *rst_regmap;
+};
+
+/* NPCM7xx reset module */
+#define IPSRST1_OFFSET 0x020
+#define IPSRST1_ADC_RSTBIT(27)
+
+/* ADC registers */
+#define NPCM_ADCCON 0x00
+#define NPCM_ADCDATA0x04
+
+/* ADCCON Register Bits */
+#define NPCM_ADCCON_ADC_INT_EN BIT(21)
+#define NPCM_ADCCON_REFSEL BIT(19)
+#define NPCM_ADCCON_ADC_INT_ST BIT(18)
+#define NPCM_ADCCON_ADC_EN BIT(17)
+#define NPCM_ADCCON_ADC_RSTBIT(16)
+#define NPCM_ADCCON_ADC_CONV BIT(13)
+
+#define NPCM_ADCCON_CH_MASKGENMASK(27, 24)
+#define NPCM_ADCCON_CH(x) ((x) << 24)
+#define NPCM_ADCCON_DIV_SHIFT 1
+#define NPCM_ADCCON_DIV_MASK GENMASK(8, 1)
+#define NPCM_ADC_DATA_MASK(x) ((x) & GENMASK(9, 0))
+
+#define NPCM_ADC_ENABLE(NPCM_ADCCON_ADC_EN |
NPCM_ADCCON_ADC_INT_EN)
+
+/* ADC General Definition */
+#define NPCM_RESOLUTION_BITS 10
+#define ADC_DEFAULT_SAMPLE_RATE1250
+#define INT_VREF_MV2000
+
+#define NPCM_ADC_CHAN(ch) {\
+ .type = IIO_VOLTAGE,\
+ .indexed = 1, \
+ .channel = ch, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+}
+
+static const struct iio_chan_spec npcm_adc_iio_channels[] = {
+ NPCM_ADC_CHAN(0),
+ NPCM_ADC_CHAN(1),
+ NPCM_ADC_CHAN(2),
+ NPCM_ADC_CHAN(3),
+ NPCM_ADC_CHAN(4),
+ NPCM_ADC_CHAN(5),
+ NPCM_ADC_CHAN(6),
+ NPCM_ADC_CHAN(7),
+};
+
+static irqreturn_t npcm_adc_isr(int irq, void *data)
+{
+ u32 regtemp = 0;
+ struct iio_dev *indio_dev = data;
+ struct npcm_adc *info = iio_priv(indio_dev);
+
+ regtemp = ioread32(info->regs + NPCM_ADCCON);
+ if (regtemp & NPCM_ADCCON_ADC_INT_ST) {
+ iowrite32(regtemp, info->regs + NPCM_ADCCON);
+ wake_up_interruptible(>wq);
+ info->int_status = true;
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int npcm_adc_read(struct npcm_adc *info, int *val, u8 channel)
+{
+ int ret;
+ u32 regtemp = 0;
+
+ /* Select ADC channal */
+ regtemp = ioread32(info->regs + NPCM_ADCCON);
+ regtemp &= ~NPCM_ADCCON_CH_MASK;
+ iowrite32(regtemp | NPCM_ADCCON_CH(channel) |
+ NPCM_ADCCON_ADC_CONV, info->regs + NPCM_
[PATCH v1 0/2] iio: adc: npcm: add NPCm ADC driver
This patch set adds Analog-to-Digital Converter (ADC) support for the Nuvoton NPCM Baseboard Management Controller (BMC). The NPCM ADC is a 10-bit converter for eight channel inputs. The NPCM ADC driver tested on NPCM750 evaluation board. Tomer Maimon (2): dt-binding: iio: add NPCM ADC documentation iio: adc: add NPCM ADC driver .../bindings/iio/adc/nuvoton,npcm-adc.txt | 35 +++ drivers/iio/adc/Kconfig| 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/npcm_adc.c | 336 + 4 files changed, 382 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt create mode 100644 drivers/iio/adc/npcm_adc.c -- 2.14.1
[PATCH v1] dt-binding: spi: Update NPCM PSPI controller documentation
Update the PSPI NPCM binding document of the spi aliases use
to define the spi ID number.
Signed-off-by: Tomer Maimon
---
Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt | 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
index 99606b22e5c2..1fd9a4406a1d 100644
--- a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
+++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
@@ -19,8 +19,16 @@ Optional properties:
- clock-frequency : Input clock frequency to the PSPI block in Hz.
Default is 2500 Hz.
+Aliases:
+- All the SPI controller nodes should be represented in the aliases node using
+ the following format 'spi{n}' withe the correct numbered in "aliases" node.
+
Example:
+aliases {
+ spi0 =
+};
+
spi0: spi@f020 {
compatible = "nuvoton,npcm750-pspi";
reg = <0xf020 0x1000>;
--
2.14.1
[PATCH v1] dt-binding: spi: Update NPCM PSPI controller documentation
Update the PSPI NPCM binding document of the spi aliases use
to define the spi ID number.
Signed-off-by: Tomer Maimon
---
Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt | 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
index 99606b22e5c2..1fd9a4406a1d 100644
--- a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
+++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
@@ -19,8 +19,16 @@ Optional properties:
- clock-frequency : Input clock frequency to the PSPI block in Hz.
Default is 2500 Hz.
+Aliases:
+- All the SPI controller nodes should be represented in the aliases node using
+ the following format 'spi{n}' withe the correct numbered in "aliases" node.
+
Example:
+aliases {
+ spi0 =
+};
+
spi0: spi@f020 {
compatible = "nuvoton,npcm750-pspi";
reg = <0xf020 0x1000>;
--
2.14.1
[PATCH v1] spi: npcm: Modify pspi send function
Align pspi send function code with the recieve function
code, Also simplify the code a bit with early return.
Signed-off-by: Tomer Maimon
---
drivers/spi/spi-npcm-pspi.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-npcm-pspi.c b/drivers/spi/spi-npcm-pspi.c
index dda91c19af93..e1dca79b9090 100644
--- a/drivers/spi/spi-npcm-pspi.c
+++ b/drivers/spi/spi-npcm-pspi.c
@@ -199,14 +199,22 @@ static void npcm_pspi_send(struct npcm_pspi *priv)
wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
priv->tx_bytes -= wsize;
- if (priv->tx_buf) {
- if (wsize == 1)
- iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
- if (wsize == 2)
- iowrite16(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
+ if (!priv->tx_buf)
+ return;
- priv->tx_buf += wsize;
+ switch (wsize) {
+ case 1:
+ iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
+ break;
+ case 2:
+ iowrite16(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
+ break;
+ default:
+ WARN_ON_ONCE(1);
+ return;
}
+
+ priv->tx_buf += wsize;
}
static void npcm_pspi_recv(struct npcm_pspi *priv)
--
2.14.1
[PATCH v1] spi: npcm: Modify pspi send function
Align pspi send function code with the recieve function
code, Also simplify the code a bit with early return.
Signed-off-by: Tomer Maimon
---
drivers/spi/spi-npcm-pspi.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-npcm-pspi.c b/drivers/spi/spi-npcm-pspi.c
index dda91c19af93..e1dca79b9090 100644
--- a/drivers/spi/spi-npcm-pspi.c
+++ b/drivers/spi/spi-npcm-pspi.c
@@ -199,14 +199,22 @@ static void npcm_pspi_send(struct npcm_pspi *priv)
wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
priv->tx_bytes -= wsize;
- if (priv->tx_buf) {
- if (wsize == 1)
- iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
- if (wsize == 2)
- iowrite16(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
+ if (!priv->tx_buf)
+ return;
- priv->tx_buf += wsize;
+ switch (wsize) {
+ case 1:
+ iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
+ break;
+ case 2:
+ iowrite16(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
+ break;
+ default:
+ WARN_ON_ONCE(1);
+ return;
}
+
+ priv->tx_buf += wsize;
}
static void npcm_pspi_recv(struct npcm_pspi *priv)
--
2.14.1
[PATCH v1 1/2] dt-binding: mtd: add NPCM FIU controller
Added device tree binding documentation for Nuvoton BMC
NPCM Flash Interface Unit(FIU) SPI-NOR controller.
Signed-off-by: Tomer Maimon
---
Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++
1 file changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt
diff --git a/Documentation/devicetree/bindings/mtd/npcm-fiu.txt
b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt
new file mode 100644
index ..9746cb5b1ced
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt
@@ -0,0 +1,64 @@
+* Nuvoton FLASH Interface Unit (FIU) SPI Controller
+
+NPCM FIU supports single, dual and quad communication interface.
+
+The NPCM7XX supports three FIU modules,
+FIU0 and FIUx supports two chip selects,
+FIU3 support four chip select.
+
+Required properties:
+ - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
+ - #address-cells : should be 1.
+ - #size-cells : should be 0.
+ - reg : the first contains the register location and length,
+ the second contains the memory mapping address and length
+ - reg-names: Should contain the reg names "control" and "memory"
+ - clocks : phandle of F reference clock.
+
+Required properties in case the pins can be muxed:
+ - pinctrl-names : a pinctrl state named "default" must be defined.
+ - pinctrl-0 : phandle referencing pin configuration of the device.
+
+Optional property:
+ - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.
+
+The SPI device must be a child of the FIU node and must have a
+compatible property as specified in bindings/mtd/jedec,spi-nor.txt
+
+Required property:
+- reg: chip select number.
+
+Optional property:
+- spi-rx-bus-width: see ../spi/spi-bus.txt for the description.
+
+Aliases:
+- All the FIU controller nodes should be represented in the aliases node using
+ the following format 'fiu{n}' where n is a unique number for the alias.
+ In the NPCM7XX BMC:
+ fiu0 represent fiu 0 controller
+ fiu1 represent fiu 3 controller
+ fiu2 represent fiu x controller
+
+Example:
+fiu3: fiu@c {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfb00 0x1000>, <0x8000 0x1000>;
+ reg-names = "control", "memory";
+ clocks = < NPCM7XX_CLK_AHB>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ partition@0 {
+ label = "flash_data";
+ reg = <0x0 0x80>;
+ };
+ };
+};
+
--
2.14.1
[PATCH v1 1/2] dt-binding: mtd: add NPCM FIU controller
Added device tree binding documentation for Nuvoton BMC
NPCM Flash Interface Unit(FIU) SPI-NOR controller.
Signed-off-by: Tomer Maimon
---
Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++
1 file changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt
diff --git a/Documentation/devicetree/bindings/mtd/npcm-fiu.txt
b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt
new file mode 100644
index ..9746cb5b1ced
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt
@@ -0,0 +1,64 @@
+* Nuvoton FLASH Interface Unit (FIU) SPI Controller
+
+NPCM FIU supports single, dual and quad communication interface.
+
+The NPCM7XX supports three FIU modules,
+FIU0 and FIUx supports two chip selects,
+FIU3 support four chip select.
+
+Required properties:
+ - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
+ - #address-cells : should be 1.
+ - #size-cells : should be 0.
+ - reg : the first contains the register location and length,
+ the second contains the memory mapping address and length
+ - reg-names: Should contain the reg names "control" and "memory"
+ - clocks : phandle of F reference clock.
+
+Required properties in case the pins can be muxed:
+ - pinctrl-names : a pinctrl state named "default" must be defined.
+ - pinctrl-0 : phandle referencing pin configuration of the device.
+
+Optional property:
+ - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.
+
+The SPI device must be a child of the FIU node and must have a
+compatible property as specified in bindings/mtd/jedec,spi-nor.txt
+
+Required property:
+- reg: chip select number.
+
+Optional property:
+- spi-rx-bus-width: see ../spi/spi-bus.txt for the description.
+
+Aliases:
+- All the FIU controller nodes should be represented in the aliases node using
+ the following format 'fiu{n}' where n is a unique number for the alias.
+ In the NPCM7XX BMC:
+ fiu0 represent fiu 0 controller
+ fiu1 represent fiu 3 controller
+ fiu2 represent fiu x controller
+
+Example:
+fiu3: fiu@c {
+ compatible = "nuvoton,npcm750-fiu";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfb00 0x1000>, <0x8000 0x1000>;
+ reg-names = "control", "memory";
+ clocks = < NPCM7XX_CLK_AHB>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ partition@0 {
+ label = "flash_data";
+ reg = <0x0 0x80>;
+ };
+ };
+};
+
--
2.14.1
[PATCH v1 2/2] mtd: spi-nor: add NPCM FIU controller driver
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI-NOR controller driver The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. Signed-off-by: Tomer Maimon --- drivers/mtd/spi-nor/Kconfig| 8 + drivers/mtd/spi-nor/Makefile | 1 + drivers/mtd/spi-nor/npcm-fiu.c | 930 + 3 files changed, 939 insertions(+) create mode 100644 drivers/mtd/spi-nor/npcm-fiu.c diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index 6cc9c929ff57..e3451637240a 100644 --- a/drivers/mtd/spi-nor/Kconfig +++ b/drivers/mtd/spi-nor/Kconfig @@ -75,6 +75,14 @@ config SPI_HISI_SFC help This enables support for hisilicon SPI-NOR flash controller. +config SPI_NPCM_FIU + tristate "NPCM FLASH Interface unit(FIU) controller " + depends on ARCH_NPCM || COMPILE_TEST + help + This enables support for the FLASH Interface unit(FIU) controller. + This driver does not support generic SPI. The implementation only + supports SPI NOR. + config SPI_NXP_SPIFI tristate "NXP SPI Flash Interface (SPIFI)" depends on OF && (ARCH_LPC18XX || COMPILE_TEST) diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index f4c61d282abd..fe0e2bdef9cd 100644 --- a/drivers/mtd/spi-nor/Makefile +++ b/drivers/mtd/spi-nor/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o obj-$(CONFIG_MTD_MT81xx_NOR)+= mtk-quadspi.o +obj-$(CONFIG_SPI_NPCM_FIU) += npcm-fiu.o obj-$(CONFIG_SPI_NXP_SPIFI)+= nxp-spifi.o obj-$(CONFIG_SPI_INTEL_SPI)+= intel-spi.o obj-$(CONFIG_SPI_INTEL_SPI_PCI)+= intel-spi-pci.o diff --git a/drivers/mtd/spi-nor/npcm-fiu.c b/drivers/mtd/spi-nor/npcm-fiu.c new file mode 100644 index ..9b6e7747d678 --- /dev/null +++ b/drivers/mtd/spi-nor/npcm-fiu.c @@ -0,0 +1,930 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology corporation. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* Flash Interface Unit (FIU) Registers */ +#define NPCM_FIU_DRD_CFG 0x00 +#define NPCM_FIU_DWR_CFG 0x04 +#define NPCM_FIU_UMA_CFG 0x08 +#define NPCM_FIU_UMA_CTS 0x0C +#define NPCM_FIU_UMA_CMD 0x10 +#define NPCM_FIU_UMA_ADDR 0x14 +#define NPCM_FIU_PRT_CFG 0x18 +#define NPCM_FIU_UMA_DW0 0x20 +#define NPCM_FIU_UMA_DW1 0x24 +#define NPCM_FIU_UMA_DW2 0x28 +#define NPCM_FIU_UMA_DW3 0x2C +#define NPCM_FIU_UMA_DR0 0x30 +#define NPCM_FIU_UMA_DR1 0x34 +#define NPCM_FIU_UMA_DR2 0x38 +#define NPCM_FIU_UMA_DR3 0x3C +#define NPCM_FIU_MAX_REG_LIMIT 0x80 + +/* FIU Direct Read Configuration Register */ +#define NPCM_FIU_DRD_CFG_LCK BIT(31) +#define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24) +#define NPCM_FIU_DRD_CFG_ADDSIZGENMASK(17, 16) +#define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12) +#define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8) +#define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0) +#define NPCM_FIU_DRD_ADDSIZ_SHIFT 16 +#define NPCM_FIU_DRD_DBW_SHIFT 12 +#define NPCM_FIU_DRD_ACCTYPE_SHIFT 8 + +/* FIU Direct Write Configuration Register */ +#define NPCM_FIU_DWR_CFG_LCK BIT(31) +#define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24) +#define NPCM_FIU_DWR_CFG_ADDSIZGENMASK(17, 16) +#define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10) +#define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8) +#define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0) +#define NPCM_FIU_DWR_ADDSIZ_SHIFT 16 +#define NPCM_FIU_DWR_ABPCK_SHIFT 10 +#define NPCM_FIU_DWR_DBPCK_SHIFT 8 + +/* FIU UMA Configuration Register */ +#define NPCM_FIU_UMA_CFG_LCK BIT(31) +#define NPCM_FIU_UMA_CFG_CMMLCKBIT(30) +#define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24) +#define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21) +#define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16) +#define NPCM_FIU_UMA_CFG_ADDSIZGENMASK(13, 11) +#define NPCM_FIU_UMA_CFG_CMDSIZBIT(10) +#define NPCM_FIU_UMA_CFG_RDBPCKGENMASK(9, 8) +#define NPCM_FIU_UMA_CFG_DBPCK GENMASK(7, 6) +#define NPCM_FIU_UMA_CFG_WDBPCK
[PATCH v1 2/2] mtd: spi-nor: add NPCM FIU controller driver
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI-NOR controller driver The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. Signed-off-by: Tomer Maimon --- drivers/mtd/spi-nor/Kconfig| 8 + drivers/mtd/spi-nor/Makefile | 1 + drivers/mtd/spi-nor/npcm-fiu.c | 930 + 3 files changed, 939 insertions(+) create mode 100644 drivers/mtd/spi-nor/npcm-fiu.c diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index 6cc9c929ff57..e3451637240a 100644 --- a/drivers/mtd/spi-nor/Kconfig +++ b/drivers/mtd/spi-nor/Kconfig @@ -75,6 +75,14 @@ config SPI_HISI_SFC help This enables support for hisilicon SPI-NOR flash controller. +config SPI_NPCM_FIU + tristate "NPCM FLASH Interface unit(FIU) controller " + depends on ARCH_NPCM || COMPILE_TEST + help + This enables support for the FLASH Interface unit(FIU) controller. + This driver does not support generic SPI. The implementation only + supports SPI NOR. + config SPI_NXP_SPIFI tristate "NXP SPI Flash Interface (SPIFI)" depends on OF && (ARCH_LPC18XX || COMPILE_TEST) diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index f4c61d282abd..fe0e2bdef9cd 100644 --- a/drivers/mtd/spi-nor/Makefile +++ b/drivers/mtd/spi-nor/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o obj-$(CONFIG_MTD_MT81xx_NOR)+= mtk-quadspi.o +obj-$(CONFIG_SPI_NPCM_FIU) += npcm-fiu.o obj-$(CONFIG_SPI_NXP_SPIFI)+= nxp-spifi.o obj-$(CONFIG_SPI_INTEL_SPI)+= intel-spi.o obj-$(CONFIG_SPI_INTEL_SPI_PCI)+= intel-spi-pci.o diff --git a/drivers/mtd/spi-nor/npcm-fiu.c b/drivers/mtd/spi-nor/npcm-fiu.c new file mode 100644 index ..9b6e7747d678 --- /dev/null +++ b/drivers/mtd/spi-nor/npcm-fiu.c @@ -0,0 +1,930 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology corporation. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* Flash Interface Unit (FIU) Registers */ +#define NPCM_FIU_DRD_CFG 0x00 +#define NPCM_FIU_DWR_CFG 0x04 +#define NPCM_FIU_UMA_CFG 0x08 +#define NPCM_FIU_UMA_CTS 0x0C +#define NPCM_FIU_UMA_CMD 0x10 +#define NPCM_FIU_UMA_ADDR 0x14 +#define NPCM_FIU_PRT_CFG 0x18 +#define NPCM_FIU_UMA_DW0 0x20 +#define NPCM_FIU_UMA_DW1 0x24 +#define NPCM_FIU_UMA_DW2 0x28 +#define NPCM_FIU_UMA_DW3 0x2C +#define NPCM_FIU_UMA_DR0 0x30 +#define NPCM_FIU_UMA_DR1 0x34 +#define NPCM_FIU_UMA_DR2 0x38 +#define NPCM_FIU_UMA_DR3 0x3C +#define NPCM_FIU_MAX_REG_LIMIT 0x80 + +/* FIU Direct Read Configuration Register */ +#define NPCM_FIU_DRD_CFG_LCK BIT(31) +#define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24) +#define NPCM_FIU_DRD_CFG_ADDSIZGENMASK(17, 16) +#define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12) +#define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8) +#define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0) +#define NPCM_FIU_DRD_ADDSIZ_SHIFT 16 +#define NPCM_FIU_DRD_DBW_SHIFT 12 +#define NPCM_FIU_DRD_ACCTYPE_SHIFT 8 + +/* FIU Direct Write Configuration Register */ +#define NPCM_FIU_DWR_CFG_LCK BIT(31) +#define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24) +#define NPCM_FIU_DWR_CFG_ADDSIZGENMASK(17, 16) +#define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10) +#define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8) +#define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0) +#define NPCM_FIU_DWR_ADDSIZ_SHIFT 16 +#define NPCM_FIU_DWR_ABPCK_SHIFT 10 +#define NPCM_FIU_DWR_DBPCK_SHIFT 8 + +/* FIU UMA Configuration Register */ +#define NPCM_FIU_UMA_CFG_LCK BIT(31) +#define NPCM_FIU_UMA_CFG_CMMLCKBIT(30) +#define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24) +#define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21) +#define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16) +#define NPCM_FIU_UMA_CFG_ADDSIZGENMASK(13, 11) +#define NPCM_FIU_UMA_CFG_CMDSIZBIT(10) +#define NPCM_FIU_UMA_CFG_RDBPCKGENMASK(9, 8) +#define NPCM_FIU_UMA_CFG_DBPCK GENMASK(7, 6) +#define NPCM_FIU_UMA_CFG_WDBPCK
[PATCH v1 0/2] SPI-NOR add NPCM FIU controller driver
This patch set adds Flash Interface Unit(FIU) SPI-NOR support for the Nuvoton NPCM Baseboard Management Controller (BMC). The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. The NPCM750/730/715/710 supports up to three FIU devices: - FIU0 supports two chip select. - FIU3 supports four chip select. - FIUX supports two chip select. The NPCM FIU driver tested on NPCM750 evaluation board. Tomer Maimon (2): dt-binding: mtd: add NPCM FIU controller mtd: spi-nor: add NPCM FIU controller driver Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++ drivers/mtd/spi-nor/Kconfig| 8 + drivers/mtd/spi-nor/Makefile | 1 + drivers/mtd/spi-nor/npcm-fiu.c | 930 + 4 files changed, 1003 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt create mode 100644 drivers/mtd/spi-nor/npcm-fiu.c -- 2.14.1
[PATCH v1 0/2] SPI-NOR add NPCM FIU controller driver
This patch set adds Flash Interface Unit(FIU) SPI-NOR support for the Nuvoton NPCM Baseboard Management Controller (BMC). The FIU supports single, dual or quad communication interface. the FIU controller can operate in following modes: - User Mode Access(UMA): provides flash access by using an indirect address/data mechanism. - direct rd/wr mode: maps the flash memory into the core address space. - SPI-X mode: used for an expansion bus to an ASIC or CPLD. The NPCM750/730/715/710 supports up to three FIU devices: - FIU0 supports two chip select. - FIU3 supports four chip select. - FIUX supports two chip select. The NPCM FIU driver tested on NPCM750 evaluation board. Tomer Maimon (2): dt-binding: mtd: add NPCM FIU controller mtd: spi-nor: add NPCM FIU controller driver Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++ drivers/mtd/spi-nor/Kconfig| 8 + drivers/mtd/spi-nor/Makefile | 1 + drivers/mtd/spi-nor/npcm-fiu.c | 930 + 4 files changed, 1003 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt create mode 100644 drivers/mtd/spi-nor/npcm-fiu.c -- 2.14.1
[PATCH v1 1/1] spi: npcm: fix uninitialized 'val' warning in receive function
Fix uninitialized 'val' warning receive function, send function
has been modify to be aligned with the receive function.
Signed-off-by: Tomer Maimon
---
drivers/spi/spi-npcm-pspi.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-npcm-pspi.c b/drivers/spi/spi-npcm-pspi.c
index 6dae91091143..f75df49ab84e 100644
--- a/drivers/spi/spi-npcm-pspi.c
+++ b/drivers/spi/spi-npcm-pspi.c
@@ -199,11 +199,11 @@ static void npcm_pspi_send(struct npcm_pspi *priv)
wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
priv->tx_bytes -= wsize;
- if (priv->tx_buf) {
- if (wsize == 1)
- iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
+ if (priv->tx_buf && wsize) {
if (wsize == 2)
iowrite16(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
+ else
+ iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
priv->tx_buf += wsize;
}
@@ -217,11 +217,11 @@ static void npcm_pspi_recv(struct npcm_pspi *priv)
rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
priv->rx_bytes -= rsize;
- if (priv->rx_buf) {
- if (rsize == 1)
- val = ioread8(priv->base + NPCM_PSPI_DATA);
+ if (priv->rx_buf && rsize) {
if (rsize == 2)
val = ioread16(priv->base + NPCM_PSPI_DATA);
+ else
+ val = ioread8(priv->base + NPCM_PSPI_DATA);
*priv->rx_buf = val;
priv->rx_buf += rsize;
--
2.14.1
[PATCH v1 0/1] npcm: fix uninitialized 'val' warning in receive function
Addressed comments from:. - kbuild test robot : drivers/spi/spi-npcm-pspi.c:226:17: warning: 'val' may be used uninitialized in this function. Fix uninitialized 'val' warning receive function. Send function has been modify to be aligned with the receive function. The NPCM PSPI driver tested on NPCM750 evaluation board. Tomer Maimon (1): spi: npcm: fix uninitialized 'val' warning in receive function drivers/spi/spi-npcm-pspi.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.14.1
[PATCH v1 1/1] spi: npcm: fix uninitialized 'val' warning in receive function
Fix uninitialized 'val' warning receive function, send function
has been modify to be aligned with the receive function.
Signed-off-by: Tomer Maimon
---
drivers/spi/spi-npcm-pspi.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-npcm-pspi.c b/drivers/spi/spi-npcm-pspi.c
index 6dae91091143..f75df49ab84e 100644
--- a/drivers/spi/spi-npcm-pspi.c
+++ b/drivers/spi/spi-npcm-pspi.c
@@ -199,11 +199,11 @@ static void npcm_pspi_send(struct npcm_pspi *priv)
wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes);
priv->tx_bytes -= wsize;
- if (priv->tx_buf) {
- if (wsize == 1)
- iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
+ if (priv->tx_buf && wsize) {
if (wsize == 2)
iowrite16(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
+ else
+ iowrite8(*priv->tx_buf, NPCM_PSPI_DATA + priv->base);
priv->tx_buf += wsize;
}
@@ -217,11 +217,11 @@ static void npcm_pspi_recv(struct npcm_pspi *priv)
rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes);
priv->rx_bytes -= rsize;
- if (priv->rx_buf) {
- if (rsize == 1)
- val = ioread8(priv->base + NPCM_PSPI_DATA);
+ if (priv->rx_buf && rsize) {
if (rsize == 2)
val = ioread16(priv->base + NPCM_PSPI_DATA);
+ else
+ val = ioread8(priv->base + NPCM_PSPI_DATA);
*priv->rx_buf = val;
priv->rx_buf += rsize;
--
2.14.1
[PATCH v1 0/1] npcm: fix uninitialized 'val' warning in receive function
Addressed comments from:. - kbuild test robot : drivers/spi/spi-npcm-pspi.c:226:17: warning: 'val' may be used uninitialized in this function. Fix uninitialized 'val' warning receive function. Send function has been modify to be aligned with the receive function. The NPCM PSPI driver tested on NPCM750 evaluation board. Tomer Maimon (1): spi: npcm: fix uninitialized 'val' warning in receive function drivers/spi/spi-npcm-pspi.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.14.1
[PATCH v1 2/2] spi: npcm: add NPCM PSPI controller driver
Add Nuvoton NPCM BMC Peripheral SPI controller driver.
Signed-off-by: Tomer Maimon
---
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile| 1 +
drivers/spi/spi-npcm-pspi.c | 480
3 files changed, 488 insertions(+)
create mode 100644 drivers/spi/spi-npcm-pspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7d3a5c94727e..21eb08405127 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -397,6 +397,13 @@ config SPI_MT65XX
say Y or M here.If you are not sure, say N.
SPI drivers for Mediatek MT65XX and MT81XX series ARM SoCs.
+config SPI_NPCM_PSPI
+ tristate "Nuvoton NPCM PSPI Controller"
+ depends on ARCH_NPCM || COMPILE_TEST
+ help
+ This driver provides support for Nuvoton NPCM BMC
+ Peripheral SPI controller in master mode.
+
config SPI_NUC900
tristate "Nuvoton NUC900 series SPI"
depends on ARCH_W90X900
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3575205c5c27..d40a3611809c 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o
obj-$(CONFIG_SPI_MXS) += spi-mxs.o
+obj-$(CONFIG_SPI_NPCM_PSPI)+= spi-npcm-pspi.o
obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
spi-octeon-objs:= spi-cavium.o
spi-cavium-octeon.o
diff --git a/drivers/spi/spi-npcm-pspi.c b/drivers/spi/spi-npcm-pspi.c
new file mode 100644
index ..51777515c83f
--- /dev/null
+++ b/drivers/spi/spi-npcm-pspi.c
@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology corporation.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+
+struct npcm_pspi {
+ struct completion xfer_done;
+ struct regmap *rst_regmap;
+ struct spi_master *master;
+ unsigned int tx_bytes;
+ unsigned int rx_bytes;
+ void __iomem *base;
+ bool is_save_param;
+ u8 bits_per_word;
+ const u8 *tx_buf;
+ struct clk *clk;
+ u32 speed_hz;
+ u8 *rx_buf;
+ u16 mode;
+ u32 id;
+};
+
+#define DRIVER_NAME "npcm-pspi"
+
+#define NPCM_PSPI_DATA 0x00
+#define NPCM_PSPI_CTL1 0x02
+#define NPCM_PSPI_STAT 0x04
+
+/* definitions for control and status register */
+#define NPCM_PSPI_CTL1_SPIEN BIT(0)
+#define NPCM_PSPI_CTL1_MOD BIT(2)
+#define NPCM_PSPI_CTL1_EIR BIT(5)
+#define NPCM_PSPI_CTL1_EIW BIT(6)
+#define NPCM_PSPI_CTL1_SCM BIT(7)
+#define NPCM_PSPI_CTL1_SCIDL BIT(8)
+#define NPCM_PSPI_CTL1_SCDV6_0 GENMASK(15, 9)
+
+#define NPCM_PSPI_STAT_BSY BIT(0)
+#define NPCM_PSPI_STAT_RBF BIT(1)
+
+/* general definitions */
+#define NPCM_PSPI_TIMEOUT_MS 2000
+#define NPCM_PSPI_MAX_CLK_DIVIDER 256
+#define NPCM_PSPI_MIN_CLK_DIVIDER 4
+#define NPCM_PSPI_DEFAULT_CLK 2500
+
+/* reset register */
+#define NPCM7XX_IPSRST2_OFFSET 0x24
+
+#define NPCM7XX_PSPI1_RESETBIT(22)
+#define NPCM7XX_PSPI2_RESETBIT(23)
+
+static inline unsigned int bytes_per_word(unsigned int bits)
+{
+ return bits <= 8 ? 1 : 2;
+}
+
+static inline void npcm_pspi_irq_enable(struct npcm_pspi *priv, u16 mask)
+{
+ u16 val;
+
+ val = ioread16(priv->base + NPCM_PSPI_CTL1);
+ val |= mask;
+ iowrite16(val, priv->base + NPCM_PSPI_CTL1);
+}
+
+static inline void npcm_pspi_irq_disable(struct npcm_pspi *priv, u16 mask)
+{
+ u16 val;
+
+ val = ioread16(priv->base + NPCM_PSPI_CTL1);
+ val &= ~mask;
+ iowrite16(val, priv->base + NPCM_PSPI_CTL1);
+}
+
+static inline void npcm_pspi_enable(struct npcm_pspi *priv)
+{
+ u16 val;
+
+ val = ioread16(priv->base + NPCM_PSPI_CTL1);
+ val |= NPCM_PSPI_CTL1_SPIEN;
+ iowrite16(val, priv->base + NPCM_PSPI_CTL1);
+}
+
+static inline void npcm_pspi_disable(struct npcm_pspi *priv)
+{
+ u16 val;
+
+ val = ioread16(priv->base + NPCM_PSPI_CTL1);
+ val &= ~NPCM_PSPI_CTL1_SPIEN;
+ iowrite16(val, priv->base + NPCM_PSPI_CTL1);
+}
+
+static void npcm_pspi_set_mode(struct spi_device *spi)
+{
+ struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
+ u16 regtemp;
+ u16 mode_val;
+
+ switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
+ case SPI_MODE_0:
+ mode_val = 0;
+ break;
+ case SPI_MODE_1:
+ mode_val = NPCM_PSPI_CTL1_SCIDL;
+ break;
+ case SPI_MODE_2:
+ mode_val = NPCM_PSPI_CTL1_SCM;
+ brea
[PATCH v1 2/2] spi: npcm: add NPCM PSPI controller driver
Add Nuvoton NPCM BMC Peripheral SPI controller driver.
Signed-off-by: Tomer Maimon
---
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile| 1 +
drivers/spi/spi-npcm-pspi.c | 480
3 files changed, 488 insertions(+)
create mode 100644 drivers/spi/spi-npcm-pspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7d3a5c94727e..21eb08405127 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -397,6 +397,13 @@ config SPI_MT65XX
say Y or M here.If you are not sure, say N.
SPI drivers for Mediatek MT65XX and MT81XX series ARM SoCs.
+config SPI_NPCM_PSPI
+ tristate "Nuvoton NPCM PSPI Controller"
+ depends on ARCH_NPCM || COMPILE_TEST
+ help
+ This driver provides support for Nuvoton NPCM BMC
+ Peripheral SPI controller in master mode.
+
config SPI_NUC900
tristate "Nuvoton NUC900 series SPI"
depends on ARCH_W90X900
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3575205c5c27..d40a3611809c 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o
obj-$(CONFIG_SPI_MXS) += spi-mxs.o
+obj-$(CONFIG_SPI_NPCM_PSPI)+= spi-npcm-pspi.o
obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
spi-octeon-objs:= spi-cavium.o
spi-cavium-octeon.o
diff --git a/drivers/spi/spi-npcm-pspi.c b/drivers/spi/spi-npcm-pspi.c
new file mode 100644
index ..51777515c83f
--- /dev/null
+++ b/drivers/spi/spi-npcm-pspi.c
@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology corporation.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+
+struct npcm_pspi {
+ struct completion xfer_done;
+ struct regmap *rst_regmap;
+ struct spi_master *master;
+ unsigned int tx_bytes;
+ unsigned int rx_bytes;
+ void __iomem *base;
+ bool is_save_param;
+ u8 bits_per_word;
+ const u8 *tx_buf;
+ struct clk *clk;
+ u32 speed_hz;
+ u8 *rx_buf;
+ u16 mode;
+ u32 id;
+};
+
+#define DRIVER_NAME "npcm-pspi"
+
+#define NPCM_PSPI_DATA 0x00
+#define NPCM_PSPI_CTL1 0x02
+#define NPCM_PSPI_STAT 0x04
+
+/* definitions for control and status register */
+#define NPCM_PSPI_CTL1_SPIEN BIT(0)
+#define NPCM_PSPI_CTL1_MOD BIT(2)
+#define NPCM_PSPI_CTL1_EIR BIT(5)
+#define NPCM_PSPI_CTL1_EIW BIT(6)
+#define NPCM_PSPI_CTL1_SCM BIT(7)
+#define NPCM_PSPI_CTL1_SCIDL BIT(8)
+#define NPCM_PSPI_CTL1_SCDV6_0 GENMASK(15, 9)
+
+#define NPCM_PSPI_STAT_BSY BIT(0)
+#define NPCM_PSPI_STAT_RBF BIT(1)
+
+/* general definitions */
+#define NPCM_PSPI_TIMEOUT_MS 2000
+#define NPCM_PSPI_MAX_CLK_DIVIDER 256
+#define NPCM_PSPI_MIN_CLK_DIVIDER 4
+#define NPCM_PSPI_DEFAULT_CLK 2500
+
+/* reset register */
+#define NPCM7XX_IPSRST2_OFFSET 0x24
+
+#define NPCM7XX_PSPI1_RESETBIT(22)
+#define NPCM7XX_PSPI2_RESETBIT(23)
+
+static inline unsigned int bytes_per_word(unsigned int bits)
+{
+ return bits <= 8 ? 1 : 2;
+}
+
+static inline void npcm_pspi_irq_enable(struct npcm_pspi *priv, u16 mask)
+{
+ u16 val;
+
+ val = ioread16(priv->base + NPCM_PSPI_CTL1);
+ val |= mask;
+ iowrite16(val, priv->base + NPCM_PSPI_CTL1);
+}
+
+static inline void npcm_pspi_irq_disable(struct npcm_pspi *priv, u16 mask)
+{
+ u16 val;
+
+ val = ioread16(priv->base + NPCM_PSPI_CTL1);
+ val &= ~mask;
+ iowrite16(val, priv->base + NPCM_PSPI_CTL1);
+}
+
+static inline void npcm_pspi_enable(struct npcm_pspi *priv)
+{
+ u16 val;
+
+ val = ioread16(priv->base + NPCM_PSPI_CTL1);
+ val |= NPCM_PSPI_CTL1_SPIEN;
+ iowrite16(val, priv->base + NPCM_PSPI_CTL1);
+}
+
+static inline void npcm_pspi_disable(struct npcm_pspi *priv)
+{
+ u16 val;
+
+ val = ioread16(priv->base + NPCM_PSPI_CTL1);
+ val &= ~NPCM_PSPI_CTL1_SPIEN;
+ iowrite16(val, priv->base + NPCM_PSPI_CTL1);
+}
+
+static void npcm_pspi_set_mode(struct spi_device *spi)
+{
+ struct npcm_pspi *priv = spi_master_get_devdata(spi->master);
+ u16 regtemp;
+ u16 mode_val;
+
+ switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
+ case SPI_MODE_0:
+ mode_val = 0;
+ break;
+ case SPI_MODE_1:
+ mode_val = NPCM_PSPI_CTL1_SCIDL;
+ break;
+ case SPI_MODE_2:
+ mode_val = NPCM_PSPI_CTL1_SCM;
+ brea
[PATCH v1 0/2] spi: npcm: add NPCM Peripheral SPI driver
This patch set adds Peripheral SPI (PSPI) support for the Nuvoton NPCM Baseboard Management Controller (BMC). The NPCM PSPI operates in master mode. The NPCM750/730/715/710 supports up to two PSPI devices. The NPCM PSPI driver tested on NPCM750 evaluation board. Tomer Maimon (2): dt-binding: spi: add NPCM PSPI controller documentation spi: npcm: add NPCM PSPI controller driver .../devicetree/bindings/spi/nuvoton,npcm-pspi.txt | 35 ++ drivers/spi/Kconfig| 7 + drivers/spi/Makefile | 1 + drivers/spi/spi-npcm-pspi.c| 480 + 4 files changed, 523 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt create mode 100644 drivers/spi/spi-npcm-pspi.c -- 2.14.1
[PATCH v1 0/2] spi: npcm: add NPCM Peripheral SPI driver
This patch set adds Peripheral SPI (PSPI) support for the Nuvoton NPCM Baseboard Management Controller (BMC). The NPCM PSPI operates in master mode. The NPCM750/730/715/710 supports up to two PSPI devices. The NPCM PSPI driver tested on NPCM750 evaluation board. Tomer Maimon (2): dt-binding: spi: add NPCM PSPI controller documentation spi: npcm: add NPCM PSPI controller driver .../devicetree/bindings/spi/nuvoton,npcm-pspi.txt | 35 ++ drivers/spi/Kconfig| 7 + drivers/spi/Makefile | 1 + drivers/spi/spi-npcm-pspi.c| 480 + 4 files changed, 523 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt create mode 100644 drivers/spi/spi-npcm-pspi.c -- 2.14.1
[PATCH v1 1/2] dt-binding: spi: add NPCM PSPI controller documentation
Added device tree binding documentation for Nuvoton BMC
NPCM Peripheral SPI controller.
Signed-off-by: Tomer Maimon
---
.../devicetree/bindings/spi/nuvoton,npcm-pspi.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
new file mode 100644
index ..99606b22e5c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
@@ -0,0 +1,35 @@
+Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver
+
+Nuvoton NPCM7xx SOC support two PSPI channels.
+
+Required properties:
+ - compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC
+ - #address-cells : should be 1. see spi-bus.txt
+ - #size-cells : should be 0. see spi-bus.txt
+ - specifies physical base address and size of the register.
+ - interrupts : contain PSPI interrupt.
+ - clocks : phandle of PSPI reference clock.
+ - clock-names: Should be "clk_apb5".
+ - pinctrl-names : a pinctrl state named "default" must be defined.
+ - pinctrl-0 : phandle referencing pin configuration of the device.
+ - cs-gpios: Specifies the gpio pins to be used for chipselects.
+See: Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Optional properties:
+- clock-frequency : Input clock frequency to the PSPI block in Hz.
+ Default is 2500 Hz.
+
+Example:
+
+spi0: spi@f020 {
+ compatible = "nuvoton,npcm750-pspi";
+ reg = <0xf020 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+ clocks = < NPCM7XX_CLK_APB5>;
+ clock-names = "clk_apb5";
+ cs-gpios = < 11 GPIO_ACTIVE_LOW>;
+};
--
2.14.1
[PATCH v1 1/2] dt-binding: spi: add NPCM PSPI controller documentation
Added device tree binding documentation for Nuvoton BMC
NPCM Peripheral SPI controller.
Signed-off-by: Tomer Maimon
---
.../devicetree/bindings/spi/nuvoton,npcm-pspi.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
new file mode 100644
index ..99606b22e5c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt
@@ -0,0 +1,35 @@
+Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver
+
+Nuvoton NPCM7xx SOC support two PSPI channels.
+
+Required properties:
+ - compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC
+ - #address-cells : should be 1. see spi-bus.txt
+ - #size-cells : should be 0. see spi-bus.txt
+ - specifies physical base address and size of the register.
+ - interrupts : contain PSPI interrupt.
+ - clocks : phandle of PSPI reference clock.
+ - clock-names: Should be "clk_apb5".
+ - pinctrl-names : a pinctrl state named "default" must be defined.
+ - pinctrl-0 : phandle referencing pin configuration of the device.
+ - cs-gpios: Specifies the gpio pins to be used for chipselects.
+See: Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Optional properties:
+- clock-frequency : Input clock frequency to the PSPI block in Hz.
+ Default is 2500 Hz.
+
+Example:
+
+spi0: spi@f020 {
+ compatible = "nuvoton,npcm750-pspi";
+ reg = <0xf020 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+ clocks = < NPCM7XX_CLK_APB5>;
+ clock-names = "clk_apb5";
+ cs-gpios = < 11 GPIO_ACTIVE_LOW>;
+};
--
2.14.1
[PATCH v1 0/1] pinctrl: nuvoton: modify NPCM7xx pin configuration
This patch Modify GPIO direction setting in pin configuration function. please refer patch: Kun Yi https://patchwork.ozlabs.org/patch/985540/ Tomer Maimon (1): pinctrl: nuvoton: modify NPCM7xx pin configuration function drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 13 +++-- 1 file changed, 3 insertions(+), 10 deletions(-) -- 2.14.1
[PATCH v1 1/1] pinctrl: nuvoton: modify NPCM7xx pin configuration function
Modify GPIO direction setting in pin configuration function by using
generic GPIO functions to set the GPIO direction instead of direct
access to the GPIO direction register.
Signed-off-by: Tomer Maimon
---
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
index 7ad50d9268aa..b455209382a5 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
@@ -1799,19 +1799,12 @@ static int npcm7xx_config_set_one(struct
npcm7xx_pinctrl *npcm,
npcm_gpio_set(>gc, bank->base + NPCM7XX_GP_N_PU, gpio);
break;
case PIN_CONFIG_INPUT_ENABLE:
- if (arg) {
- iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
- npcm_gpio_set(>gc, bank->base + NPCM7XX_GP_N_IEM,
- gpio);
- } else
- npcm_gpio_clr(>gc, bank->base + NPCM7XX_GP_N_IEM,
- gpio);
+ iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
+ bank->direction_input(>gc, pin % bank->gc.ngpio);
break;
case PIN_CONFIG_OUTPUT:
- npcm_gpio_clr(>gc, bank->base + NPCM7XX_GP_N_IEM, gpio);
- iowrite32(gpio, arg ? bank->base + NPCM7XX_GP_N_DOS :
- bank->base + NPCM7XX_GP_N_DOC);
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
+ bank->direction_output(>gc, pin % bank->gc.ngpio, arg);
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
npcm_gpio_clr(>gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
--
2.14.1
[PATCH v1 0/1] pinctrl: nuvoton: modify NPCM7xx pin configuration
This patch Modify GPIO direction setting in pin configuration function. please refer patch: Kun Yi https://patchwork.ozlabs.org/patch/985540/ Tomer Maimon (1): pinctrl: nuvoton: modify NPCM7xx pin configuration function drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 13 +++-- 1 file changed, 3 insertions(+), 10 deletions(-) -- 2.14.1
[PATCH v1 1/1] pinctrl: nuvoton: modify NPCM7xx pin configuration function
Modify GPIO direction setting in pin configuration function by using
generic GPIO functions to set the GPIO direction instead of direct
access to the GPIO direction register.
Signed-off-by: Tomer Maimon
---
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
index 7ad50d9268aa..b455209382a5 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
@@ -1799,19 +1799,12 @@ static int npcm7xx_config_set_one(struct
npcm7xx_pinctrl *npcm,
npcm_gpio_set(>gc, bank->base + NPCM7XX_GP_N_PU, gpio);
break;
case PIN_CONFIG_INPUT_ENABLE:
- if (arg) {
- iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
- npcm_gpio_set(>gc, bank->base + NPCM7XX_GP_N_IEM,
- gpio);
- } else
- npcm_gpio_clr(>gc, bank->base + NPCM7XX_GP_N_IEM,
- gpio);
+ iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
+ bank->direction_input(>gc, pin % bank->gc.ngpio);
break;
case PIN_CONFIG_OUTPUT:
- npcm_gpio_clr(>gc, bank->base + NPCM7XX_GP_N_IEM, gpio);
- iowrite32(gpio, arg ? bank->base + NPCM7XX_GP_N_DOS :
- bank->base + NPCM7XX_GP_N_DOC);
iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
+ bank->direction_output(>gc, pin % bank->gc.ngpio, arg);
break;
case PIN_CONFIG_DRIVE_PUSH_PULL:
npcm_gpio_clr(>gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
--
2.14.1
[PATCH v1] watchdog: npcm: Modify npcm watchdog kconfig arch parameter
Modify Nuvoton watchdog Kconfig default supported architecture name to ARCH_NPCM7XX because ARCH_NPCM750 architecture name is not supported. Signed-off-by: Tomer Maimon --- drivers/watchdog/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 2d64333f4782..746759ec8960 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -538,7 +538,7 @@ config COH901327_WATCHDOG config NPCM7XX_WATCHDOG bool "Nuvoton NPCM750 watchdog" depends on ARCH_NPCM || COMPILE_TEST - default y if ARCH_NPCM750 + default y if ARCH_NPCM7XX select WATCHDOG_CORE help Say Y here to include Watchdog timer support for the -- 2.14.1
[PATCH v1] watchdog: npcm: Modify npcm watchdog kconfig arch parameter
Modify Nuvoton watchdog Kconfig default supported architecture name to ARCH_NPCM7XX because ARCH_NPCM750 architecture name is not supported. Signed-off-by: Tomer Maimon --- drivers/watchdog/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 2d64333f4782..746759ec8960 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -538,7 +538,7 @@ config COH901327_WATCHDOG config NPCM7XX_WATCHDOG bool "Nuvoton NPCM750 watchdog" depends on ARCH_NPCM || COMPILE_TEST - default y if ARCH_NPCM750 + default y if ARCH_NPCM7XX select WATCHDOG_CORE help Say Y here to include Watchdog timer support for the -- 2.14.1
[PATCH v6 2/2] pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver
Add Nuvoton BMC NPCM750/730/715/705 Pinmux and GPIO controller driver. Signed-off-by: Tomer Maimon --- drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig | 12 + drivers/pinctrl/nuvoton/Makefile |4 + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2072 + 5 files changed, 2090 insertions(+) create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index dd50371225bc..c966d94c2320 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -345,6 +345,7 @@ source "drivers/pinctrl/freescale/Kconfig" source "drivers/pinctrl/intel/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nomadik/Kconfig" +source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/samsung/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index de40863e7297..1797c09c8981 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -51,6 +51,7 @@ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ obj-y += mvebu/ obj-y += nomadik/ +obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM)+= qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig new file mode 100644 index ..70542c16b656 --- /dev/null +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -0,0 +1,12 @@ +config PINCTRL_NPCM7XX + bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX" + depends on (ARCH_NPCM7XX || COMPILE_TEST) && OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + help + Say Y here to enable pin controller and GPIO support + for Nuvoton NPCM750/730/715/705 SoCs. + diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile new file mode 100644 index ..886d00784cef --- /dev/null +++ b/drivers/pinctrl/nuvoton/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# Nuvoton pinctrl support + +obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c new file mode 100644 index ..7ad50d9268aa --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -0,0 +1,2072 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2016-2018 Nuvoton Technology corporation. +// Copyright (c) 2016, Dell Inc + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* GCR registers */ +#define NPCM7XX_GCR_PDID 0x00 +#define NPCM7XX_GCR_MFSEL1 0x0C +#define NPCM7XX_GCR_MFSEL2 0x10 +#define NPCM7XX_GCR_MFSEL3 0x64 +#define NPCM7XX_GCR_MFSEL4 0xb0 +#define NPCM7XX_GCR_CPCTL 0xD0 +#define NPCM7XX_GCR_CP2BST 0xD4 +#define NPCM7XX_GCR_B2CPNT 0xD8 +#define NPCM7XX_GCR_I2CSEGSEL 0xE0 +#define NPCM7XX_GCR_I2CSEGCTL 0xE4 +#define NPCM7XX_GCR_SRCNT 0x68 +#define NPCM7XX_GCR_FLOCKR10x74 +#define NPCM7XX_GCR_DSCNT 0x78 + +#define SRCNT_ESPI BIT(3) + +/* GPIO registers */ +#define NPCM7XX_GP_N_TLOCK10x00 +#define NPCM7XX_GP_N_DIN 0x04 /* Data IN */ +#define NPCM7XX_GP_N_POL 0x08 /* Polarity */ +#define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */ +#define NPCM7XX_GP_N_OE0x10 /* Output Enable */ +#define NPCM7XX_GP_N_OTYP 0x14 +#define NPCM7XX_GP_N_MP0x18 +#define NPCM7XX_GP_N_PU0x1c /* Pull-up */ +#define NPCM7XX_GP_N_PD0x20 /* Pull-down */ +#define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */ +#define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */ +#define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */ +#define NPCM7XX_GP_N_OBL0 0x30 +#define NPCM7XX_GP_N_OBL1 0x34 +#define NPCM7XX_GP_N_OBL2 0x38 +#define NPCM7XX_GP_N_OBL3 0x3c +#define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */ +#define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */ +#define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */ +#define NPCM7XX_GP_N_EVST 0x4c /* Event Status */ +#define NPCM7XX_GP_N_SPLCK 0x50 +#define NPCM7XX_GP_N_MPLCK 0x54 +#define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */ +#define NPCM7XX_GP_N_OSRC 0x5c +#define NPCM7XX_GP_N_ODSC 0x60 +#define NPC
[PATCH v6 2/2] pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver
Add Nuvoton BMC NPCM750/730/715/705 Pinmux and GPIO controller driver. Signed-off-by: Tomer Maimon --- drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig | 12 + drivers/pinctrl/nuvoton/Makefile |4 + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2072 + 5 files changed, 2090 insertions(+) create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index dd50371225bc..c966d94c2320 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -345,6 +345,7 @@ source "drivers/pinctrl/freescale/Kconfig" source "drivers/pinctrl/intel/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nomadik/Kconfig" +source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/samsung/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index de40863e7297..1797c09c8981 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -51,6 +51,7 @@ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ obj-y += mvebu/ obj-y += nomadik/ +obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM)+= qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig new file mode 100644 index ..70542c16b656 --- /dev/null +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -0,0 +1,12 @@ +config PINCTRL_NPCM7XX + bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX" + depends on (ARCH_NPCM7XX || COMPILE_TEST) && OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + help + Say Y here to enable pin controller and GPIO support + for Nuvoton NPCM750/730/715/705 SoCs. + diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile new file mode 100644 index ..886d00784cef --- /dev/null +++ b/drivers/pinctrl/nuvoton/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# Nuvoton pinctrl support + +obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c new file mode 100644 index ..7ad50d9268aa --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -0,0 +1,2072 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2016-2018 Nuvoton Technology corporation. +// Copyright (c) 2016, Dell Inc + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* GCR registers */ +#define NPCM7XX_GCR_PDID 0x00 +#define NPCM7XX_GCR_MFSEL1 0x0C +#define NPCM7XX_GCR_MFSEL2 0x10 +#define NPCM7XX_GCR_MFSEL3 0x64 +#define NPCM7XX_GCR_MFSEL4 0xb0 +#define NPCM7XX_GCR_CPCTL 0xD0 +#define NPCM7XX_GCR_CP2BST 0xD4 +#define NPCM7XX_GCR_B2CPNT 0xD8 +#define NPCM7XX_GCR_I2CSEGSEL 0xE0 +#define NPCM7XX_GCR_I2CSEGCTL 0xE4 +#define NPCM7XX_GCR_SRCNT 0x68 +#define NPCM7XX_GCR_FLOCKR10x74 +#define NPCM7XX_GCR_DSCNT 0x78 + +#define SRCNT_ESPI BIT(3) + +/* GPIO registers */ +#define NPCM7XX_GP_N_TLOCK10x00 +#define NPCM7XX_GP_N_DIN 0x04 /* Data IN */ +#define NPCM7XX_GP_N_POL 0x08 /* Polarity */ +#define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */ +#define NPCM7XX_GP_N_OE0x10 /* Output Enable */ +#define NPCM7XX_GP_N_OTYP 0x14 +#define NPCM7XX_GP_N_MP0x18 +#define NPCM7XX_GP_N_PU0x1c /* Pull-up */ +#define NPCM7XX_GP_N_PD0x20 /* Pull-down */ +#define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */ +#define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */ +#define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */ +#define NPCM7XX_GP_N_OBL0 0x30 +#define NPCM7XX_GP_N_OBL1 0x34 +#define NPCM7XX_GP_N_OBL2 0x38 +#define NPCM7XX_GP_N_OBL3 0x3c +#define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */ +#define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */ +#define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */ +#define NPCM7XX_GP_N_EVST 0x4c /* Event Status */ +#define NPCM7XX_GP_N_SPLCK 0x50 +#define NPCM7XX_GP_N_MPLCK 0x54 +#define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */ +#define NPCM7XX_GP_N_OSRC 0x5c +#define NPCM7XX_GP_N_ODSC 0x60 +#define NPC
[PATCH v6 1/2] dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation
Added device tree binding documentation for Nuvoton BMC
NPCM750/730/715/705 pinmux and GPIO controller.
Signed-off-by: Tomer Maimon
Reviewed-by: Rob Herring
---
.../bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt | 216 +
1 file changed, 216 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
diff --git
a/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
new file mode 100644
index ..83f4bbac94bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
@@ -0,0 +1,216 @@
+Nuvoton NPCM7XX Pin Controllers
+
+The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
+the multiplexing block, Each pin supports GPIO functionality (GPIOx)
+and multiple functions that directly connect the pin to different
+hardware blocks.
+
+Required properties:
+- #address-cells : should be 1.
+- #size-cells : should be 1.
+- compatible: "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
+- ranges: defines mapping ranges between pin controller node (parent)
+ to GPIO bank node (children).
+
+=== GPIO Bank Subnode ===
+
+The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
+
+Required GPIO Bank subnode-properties:
+- reg : specifies physical base address and size of the GPIO
+ bank registers.
+- gpio-controller : Marks the device node as a GPIO controller.
+- #gpio-cells : Must be <2>. The first cell is the gpio pin number
+ and the second cell is used for optional
parameters.
+- interrupts : contain the GPIO bank interrupt with flags for
falling edge.
+- gpio-ranges : defines the range of pins managed by the GPIO bank
controller.
+
+For example, GPIO bank subnodes like the following:
+ gpio0: gpio@f001 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 0 32>;
+ };
+
+=== Pin Mux Subnode ===
+
+- pin: A string containing the name of the pin
+ An array of strings, each string containing the name of a pin.
+ These pin are used for selecting pin configuration.
+
+The following are the list of pins available:
+ "GPIO0/IOX1DI", "GPIO1/IOX1LD", "GPIO2/IOX1CK", "GPIO3/IOX1D0",
+ "GPIO4/IOX2DI/SMB1DSDA", "GPIO5/IOX2LD/SMB1DSCL",
"GPIO6/IOX2CK/SMB2DSDA",
+ "GPIO7/IOX2D0/SMB2DSCL", "GPIO8/LKGPO1", "GPIO9/LKGPO2",
"GPIO10/IOXHLD",
+ "GPIO11/IOXHCK", "GPIO12/GSPICK/SMB5BSCL", "GPIO13/GSPIDO/SMB5BSDA",
+ "GPIO14/GSPIDI/SMB5CSCL", "GPIO15/GSPICS/SMB5CSDA", "GPIO16/LKGPO0",
+ "GPIO17/PSPI2DI/SMB4DEN","GPIO18/PSPI2D0/SMB4BSDA",
"GPIO19/PSPI2CK/SMB4BSCL",
+ "GPIO20/SMB4CSDA/SMB15SDA", "GPIO21/SMB4CSCL/SMB15SCL",
"GPIO22/SMB4DSDA/SMB14SDA",
+ "GPIO23/SMB4DSCL/SMB14SCL", "GPIO24/IOXHDO", "GPIO25/IOXHDI",
"GPIO26/SMB5SDA",
+ "GPIO27/SMB5SCL", "GPIO28/SMB4SDA", "GPIO29/SMB4SCL", "GPIO30/SMB3SDA",
+ "GPIO31/SMB3SCL", "GPIO32/nSPI0CS1","SPI0D2", "SPI0D3",
"GPIO37/SMB3CSDA",
+ "GPIO38/SMB3CSCL", "GPIO39/SMB3BSDA", "GPIO40/SMB3BSCL",
"GPIO41/BSPRXD",
+ "GPO42/BSPTXD/STRAP11", "GPIO43/RXD1/JTMS2/BU1RXD",
"GPIO44/nCTS1/JTDI2/BU1CTS",
+ "GPIO45/nDCD1/JTDO2", "GPIO46/nDSR1/JTCK2", "GPIO47/nRI1/JCP_RDY2",
+ "GPIO48/TXD2/BSPTXD", "GPIO49/RXD2/BSPRXD", "GPIO50/nCTS2",
"GPO51/nRTS2/STRAP2",
+ "GPIO52/nDCD2", "GPO53/nDTR2_BOUT2/STRAP1", "GPIO54/nDSR2",
"GPIO55/nRI2",
+ "GPIO56/R1RXERR", "GPIO57/R1MDC", "GPIO58/R1MDIO", "GPIO59/SMB3DSDA",
+ "GPIO60/SMB3DSCL", "GPO61/nDTR1_BOUT1/STRAP6", "GPO62/nRTST1/STRAP5",
+ "GPO63/TXD1/STRAP4", "GPIO64/FANIN0", "GPIO65/FANIN1", "GPIO66/FANIN2",
+ "GPIO67/FANIN3", "GPIO68/FANIN4", "GPIO69/FANIN5", "GPIO70/FANIN6",
"GPIO71/FANIN7",
+ "GPIO72/FANIN8", "GPIO73/FANIN9", "GPIO74/FANIN10", "GPIO75/FANIN11",
+ "GPIO76/FANIN12", "GPIO77/FANIN13","GPIO78/FANIN14", "GPIO79/FANIN15",
+
[PATCH v6 1/2] dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation
Added device tree binding documentation for Nuvoton BMC
NPCM750/730/715/705 pinmux and GPIO controller.
Signed-off-by: Tomer Maimon
Reviewed-by: Rob Herring
---
.../bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt | 216 +
1 file changed, 216 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
diff --git
a/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
new file mode 100644
index ..83f4bbac94bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
@@ -0,0 +1,216 @@
+Nuvoton NPCM7XX Pin Controllers
+
+The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
+the multiplexing block, Each pin supports GPIO functionality (GPIOx)
+and multiple functions that directly connect the pin to different
+hardware blocks.
+
+Required properties:
+- #address-cells : should be 1.
+- #size-cells : should be 1.
+- compatible: "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
+- ranges: defines mapping ranges between pin controller node (parent)
+ to GPIO bank node (children).
+
+=== GPIO Bank Subnode ===
+
+The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
+
+Required GPIO Bank subnode-properties:
+- reg : specifies physical base address and size of the GPIO
+ bank registers.
+- gpio-controller : Marks the device node as a GPIO controller.
+- #gpio-cells : Must be <2>. The first cell is the gpio pin number
+ and the second cell is used for optional
parameters.
+- interrupts : contain the GPIO bank interrupt with flags for
falling edge.
+- gpio-ranges : defines the range of pins managed by the GPIO bank
controller.
+
+For example, GPIO bank subnodes like the following:
+ gpio0: gpio@f001 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 0 32>;
+ };
+
+=== Pin Mux Subnode ===
+
+- pin: A string containing the name of the pin
+ An array of strings, each string containing the name of a pin.
+ These pin are used for selecting pin configuration.
+
+The following are the list of pins available:
+ "GPIO0/IOX1DI", "GPIO1/IOX1LD", "GPIO2/IOX1CK", "GPIO3/IOX1D0",
+ "GPIO4/IOX2DI/SMB1DSDA", "GPIO5/IOX2LD/SMB1DSCL",
"GPIO6/IOX2CK/SMB2DSDA",
+ "GPIO7/IOX2D0/SMB2DSCL", "GPIO8/LKGPO1", "GPIO9/LKGPO2",
"GPIO10/IOXHLD",
+ "GPIO11/IOXHCK", "GPIO12/GSPICK/SMB5BSCL", "GPIO13/GSPIDO/SMB5BSDA",
+ "GPIO14/GSPIDI/SMB5CSCL", "GPIO15/GSPICS/SMB5CSDA", "GPIO16/LKGPO0",
+ "GPIO17/PSPI2DI/SMB4DEN","GPIO18/PSPI2D0/SMB4BSDA",
"GPIO19/PSPI2CK/SMB4BSCL",
+ "GPIO20/SMB4CSDA/SMB15SDA", "GPIO21/SMB4CSCL/SMB15SCL",
"GPIO22/SMB4DSDA/SMB14SDA",
+ "GPIO23/SMB4DSCL/SMB14SCL", "GPIO24/IOXHDO", "GPIO25/IOXHDI",
"GPIO26/SMB5SDA",
+ "GPIO27/SMB5SCL", "GPIO28/SMB4SDA", "GPIO29/SMB4SCL", "GPIO30/SMB3SDA",
+ "GPIO31/SMB3SCL", "GPIO32/nSPI0CS1","SPI0D2", "SPI0D3",
"GPIO37/SMB3CSDA",
+ "GPIO38/SMB3CSCL", "GPIO39/SMB3BSDA", "GPIO40/SMB3BSCL",
"GPIO41/BSPRXD",
+ "GPO42/BSPTXD/STRAP11", "GPIO43/RXD1/JTMS2/BU1RXD",
"GPIO44/nCTS1/JTDI2/BU1CTS",
+ "GPIO45/nDCD1/JTDO2", "GPIO46/nDSR1/JTCK2", "GPIO47/nRI1/JCP_RDY2",
+ "GPIO48/TXD2/BSPTXD", "GPIO49/RXD2/BSPRXD", "GPIO50/nCTS2",
"GPO51/nRTS2/STRAP2",
+ "GPIO52/nDCD2", "GPO53/nDTR2_BOUT2/STRAP1", "GPIO54/nDSR2",
"GPIO55/nRI2",
+ "GPIO56/R1RXERR", "GPIO57/R1MDC", "GPIO58/R1MDIO", "GPIO59/SMB3DSDA",
+ "GPIO60/SMB3DSCL", "GPO61/nDTR1_BOUT1/STRAP6", "GPO62/nRTST1/STRAP5",
+ "GPO63/TXD1/STRAP4", "GPIO64/FANIN0", "GPIO65/FANIN1", "GPIO66/FANIN2",
+ "GPIO67/FANIN3", "GPIO68/FANIN4", "GPIO69/FANIN5", "GPIO70/FANIN6",
"GPIO71/FANIN7",
+ "GPIO72/FANIN8", "GPIO73/FANIN9", "GPIO74/FANIN10", "GPIO75/FANIN11",
+ "GPIO76/FANIN12", "GPIO77/FANIN13","GPIO78/FANIN14", "GPIO79/FANIN15",
+
[PATCH v6 0/2] pinctrl: nuvoton: add driver for NPCM7xx
This patch set adds pinmux and GPIO controller for the Nuvoton NPCM750/730/715/705 Baseboard Management Controller (BMC). The Nuvoton BMC NPCM750/730/715/705 Pinmux functions accessible only for pin groups and pinconf parameters available only for individual pins. The Nuvoton BMC NPCM750/730/715/705 has eight identical GPIO modules, each module has 32 GPIO ports. Most of the GPIO ports are multiplexed with other system functions. The NPCM7xx pinctrl and GPIO driver tested on NPCM750 evaluation board. Changes since version 5: - Remove link to unsupported GPIO_GENERIC free function. - Add child device node to each gpio chip. - dt-binding reviewed-by Rob Herring. Changes since version 4: - Use direct access read and write functions. - Modify the probe GPIO and pinctrl order. - Remove unsupported BGPIOF_INVERTED_REG_DIR flag. - dt-binding documentation haven't changed. Changes since version 3: - Remove Kconfig MFD_SYSCON dependency. - Add BGPIOF_INVERTED_REG_DIR flag. - dt-binding documentation haven't changed. Changes since version 2: - Using GPIO_GENERIC (mmio). - Add Kconfig MFD_SYSCON dependency. - Remove unnecessary code from the direction output function. - dt-binding documentation haven't changed. Changes since version 1: - Remove Kconfig MFD_SYSCON dependency. - Modify setfunc function. - Modify dt-binding documentation according Rob comments. Tomer Maimon (2): dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver .../bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt | 216 ++ drivers/pinctrl/Kconfig|1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig| 12 + drivers/pinctrl/nuvoton/Makefile |4 + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2072 6 files changed, 2306 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c -- 2.14.1
[PATCH v6 0/2] pinctrl: nuvoton: add driver for NPCM7xx
This patch set adds pinmux and GPIO controller for the Nuvoton NPCM750/730/715/705 Baseboard Management Controller (BMC). The Nuvoton BMC NPCM750/730/715/705 Pinmux functions accessible only for pin groups and pinconf parameters available only for individual pins. The Nuvoton BMC NPCM750/730/715/705 has eight identical GPIO modules, each module has 32 GPIO ports. Most of the GPIO ports are multiplexed with other system functions. The NPCM7xx pinctrl and GPIO driver tested on NPCM750 evaluation board. Changes since version 5: - Remove link to unsupported GPIO_GENERIC free function. - Add child device node to each gpio chip. - dt-binding reviewed-by Rob Herring. Changes since version 4: - Use direct access read and write functions. - Modify the probe GPIO and pinctrl order. - Remove unsupported BGPIOF_INVERTED_REG_DIR flag. - dt-binding documentation haven't changed. Changes since version 3: - Remove Kconfig MFD_SYSCON dependency. - Add BGPIOF_INVERTED_REG_DIR flag. - dt-binding documentation haven't changed. Changes since version 2: - Using GPIO_GENERIC (mmio). - Add Kconfig MFD_SYSCON dependency. - Remove unnecessary code from the direction output function. - dt-binding documentation haven't changed. Changes since version 1: - Remove Kconfig MFD_SYSCON dependency. - Modify setfunc function. - Modify dt-binding documentation according Rob comments. Tomer Maimon (2): dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver .../bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt | 216 ++ drivers/pinctrl/Kconfig|1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig| 12 + drivers/pinctrl/nuvoton/Makefile |4 + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2072 6 files changed, 2306 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c -- 2.14.1
[PATCH v5 1/2] dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation
Added device tree binding documentation for Nuvoton BMC
NPCM750/730/715/705 pinmux and GPIO controller.
Signed-off-by: Tomer Maimon
---
.../bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt | 216 +
1 file changed, 216 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
diff --git
a/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
new file mode 100644
index ..83f4bbac94bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
@@ -0,0 +1,216 @@
+Nuvoton NPCM7XX Pin Controllers
+
+The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
+the multiplexing block, Each pin supports GPIO functionality (GPIOx)
+and multiple functions that directly connect the pin to different
+hardware blocks.
+
+Required properties:
+- #address-cells : should be 1.
+- #size-cells : should be 1.
+- compatible: "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
+- ranges: defines mapping ranges between pin controller node (parent)
+ to GPIO bank node (children).
+
+=== GPIO Bank Subnode ===
+
+The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
+
+Required GPIO Bank subnode-properties:
+- reg : specifies physical base address and size of the GPIO
+ bank registers.
+- gpio-controller : Marks the device node as a GPIO controller.
+- #gpio-cells : Must be <2>. The first cell is the gpio pin number
+ and the second cell is used for optional
parameters.
+- interrupts : contain the GPIO bank interrupt with flags for
falling edge.
+- gpio-ranges : defines the range of pins managed by the GPIO bank
controller.
+
+For example, GPIO bank subnodes like the following:
+ gpio0: gpio@f001 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 0 32>;
+ };
+
+=== Pin Mux Subnode ===
+
+- pin: A string containing the name of the pin
+ An array of strings, each string containing the name of a pin.
+ These pin are used for selecting pin configuration.
+
+The following are the list of pins available:
+ "GPIO0/IOX1DI", "GPIO1/IOX1LD", "GPIO2/IOX1CK", "GPIO3/IOX1D0",
+ "GPIO4/IOX2DI/SMB1DSDA", "GPIO5/IOX2LD/SMB1DSCL",
"GPIO6/IOX2CK/SMB2DSDA",
+ "GPIO7/IOX2D0/SMB2DSCL", "GPIO8/LKGPO1", "GPIO9/LKGPO2",
"GPIO10/IOXHLD",
+ "GPIO11/IOXHCK", "GPIO12/GSPICK/SMB5BSCL", "GPIO13/GSPIDO/SMB5BSDA",
+ "GPIO14/GSPIDI/SMB5CSCL", "GPIO15/GSPICS/SMB5CSDA", "GPIO16/LKGPO0",
+ "GPIO17/PSPI2DI/SMB4DEN","GPIO18/PSPI2D0/SMB4BSDA",
"GPIO19/PSPI2CK/SMB4BSCL",
+ "GPIO20/SMB4CSDA/SMB15SDA", "GPIO21/SMB4CSCL/SMB15SCL",
"GPIO22/SMB4DSDA/SMB14SDA",
+ "GPIO23/SMB4DSCL/SMB14SCL", "GPIO24/IOXHDO", "GPIO25/IOXHDI",
"GPIO26/SMB5SDA",
+ "GPIO27/SMB5SCL", "GPIO28/SMB4SDA", "GPIO29/SMB4SCL", "GPIO30/SMB3SDA",
+ "GPIO31/SMB3SCL", "GPIO32/nSPI0CS1","SPI0D2", "SPI0D3",
"GPIO37/SMB3CSDA",
+ "GPIO38/SMB3CSCL", "GPIO39/SMB3BSDA", "GPIO40/SMB3BSCL",
"GPIO41/BSPRXD",
+ "GPO42/BSPTXD/STRAP11", "GPIO43/RXD1/JTMS2/BU1RXD",
"GPIO44/nCTS1/JTDI2/BU1CTS",
+ "GPIO45/nDCD1/JTDO2", "GPIO46/nDSR1/JTCK2", "GPIO47/nRI1/JCP_RDY2",
+ "GPIO48/TXD2/BSPTXD", "GPIO49/RXD2/BSPRXD", "GPIO50/nCTS2",
"GPO51/nRTS2/STRAP2",
+ "GPIO52/nDCD2", "GPO53/nDTR2_BOUT2/STRAP1", "GPIO54/nDSR2",
"GPIO55/nRI2",
+ "GPIO56/R1RXERR", "GPIO57/R1MDC", "GPIO58/R1MDIO", "GPIO59/SMB3DSDA",
+ "GPIO60/SMB3DSCL", "GPO61/nDTR1_BOUT1/STRAP6", "GPO62/nRTST1/STRAP5",
+ "GPO63/TXD1/STRAP4", "GPIO64/FANIN0", "GPIO65/FANIN1", "GPIO66/FANIN2",
+ "GPIO67/FANIN3", "GPIO68/FANIN4", "GPIO69/FANIN5", "GPIO70/FANIN6",
"GPIO71/FANIN7",
+ "GPIO72/FANIN8", "GPIO73/FANIN9", "GPIO74/FANIN10", "GPIO75/FANIN11",
+ "GPIO76/FANIN12", "GPIO77/FANIN13","GPIO78/FANIN14", "GPIO79/FANIN15",
+ "GPIO80/PWM0", &
[PATCH v5 1/2] dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation
Added device tree binding documentation for Nuvoton BMC
NPCM750/730/715/705 pinmux and GPIO controller.
Signed-off-by: Tomer Maimon
---
.../bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt | 216 +
1 file changed, 216 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
diff --git
a/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
new file mode 100644
index ..83f4bbac94bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
@@ -0,0 +1,216 @@
+Nuvoton NPCM7XX Pin Controllers
+
+The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
+the multiplexing block, Each pin supports GPIO functionality (GPIOx)
+and multiple functions that directly connect the pin to different
+hardware blocks.
+
+Required properties:
+- #address-cells : should be 1.
+- #size-cells : should be 1.
+- compatible: "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
+- ranges: defines mapping ranges between pin controller node (parent)
+ to GPIO bank node (children).
+
+=== GPIO Bank Subnode ===
+
+The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
+
+Required GPIO Bank subnode-properties:
+- reg : specifies physical base address and size of the GPIO
+ bank registers.
+- gpio-controller : Marks the device node as a GPIO controller.
+- #gpio-cells : Must be <2>. The first cell is the gpio pin number
+ and the second cell is used for optional
parameters.
+- interrupts : contain the GPIO bank interrupt with flags for
falling edge.
+- gpio-ranges : defines the range of pins managed by the GPIO bank
controller.
+
+For example, GPIO bank subnodes like the following:
+ gpio0: gpio@f001 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 0 32>;
+ };
+
+=== Pin Mux Subnode ===
+
+- pin: A string containing the name of the pin
+ An array of strings, each string containing the name of a pin.
+ These pin are used for selecting pin configuration.
+
+The following are the list of pins available:
+ "GPIO0/IOX1DI", "GPIO1/IOX1LD", "GPIO2/IOX1CK", "GPIO3/IOX1D0",
+ "GPIO4/IOX2DI/SMB1DSDA", "GPIO5/IOX2LD/SMB1DSCL",
"GPIO6/IOX2CK/SMB2DSDA",
+ "GPIO7/IOX2D0/SMB2DSCL", "GPIO8/LKGPO1", "GPIO9/LKGPO2",
"GPIO10/IOXHLD",
+ "GPIO11/IOXHCK", "GPIO12/GSPICK/SMB5BSCL", "GPIO13/GSPIDO/SMB5BSDA",
+ "GPIO14/GSPIDI/SMB5CSCL", "GPIO15/GSPICS/SMB5CSDA", "GPIO16/LKGPO0",
+ "GPIO17/PSPI2DI/SMB4DEN","GPIO18/PSPI2D0/SMB4BSDA",
"GPIO19/PSPI2CK/SMB4BSCL",
+ "GPIO20/SMB4CSDA/SMB15SDA", "GPIO21/SMB4CSCL/SMB15SCL",
"GPIO22/SMB4DSDA/SMB14SDA",
+ "GPIO23/SMB4DSCL/SMB14SCL", "GPIO24/IOXHDO", "GPIO25/IOXHDI",
"GPIO26/SMB5SDA",
+ "GPIO27/SMB5SCL", "GPIO28/SMB4SDA", "GPIO29/SMB4SCL", "GPIO30/SMB3SDA",
+ "GPIO31/SMB3SCL", "GPIO32/nSPI0CS1","SPI0D2", "SPI0D3",
"GPIO37/SMB3CSDA",
+ "GPIO38/SMB3CSCL", "GPIO39/SMB3BSDA", "GPIO40/SMB3BSCL",
"GPIO41/BSPRXD",
+ "GPO42/BSPTXD/STRAP11", "GPIO43/RXD1/JTMS2/BU1RXD",
"GPIO44/nCTS1/JTDI2/BU1CTS",
+ "GPIO45/nDCD1/JTDO2", "GPIO46/nDSR1/JTCK2", "GPIO47/nRI1/JCP_RDY2",
+ "GPIO48/TXD2/BSPTXD", "GPIO49/RXD2/BSPRXD", "GPIO50/nCTS2",
"GPO51/nRTS2/STRAP2",
+ "GPIO52/nDCD2", "GPO53/nDTR2_BOUT2/STRAP1", "GPIO54/nDSR2",
"GPIO55/nRI2",
+ "GPIO56/R1RXERR", "GPIO57/R1MDC", "GPIO58/R1MDIO", "GPIO59/SMB3DSDA",
+ "GPIO60/SMB3DSCL", "GPO61/nDTR1_BOUT1/STRAP6", "GPO62/nRTST1/STRAP5",
+ "GPO63/TXD1/STRAP4", "GPIO64/FANIN0", "GPIO65/FANIN1", "GPIO66/FANIN2",
+ "GPIO67/FANIN3", "GPIO68/FANIN4", "GPIO69/FANIN5", "GPIO70/FANIN6",
"GPIO71/FANIN7",
+ "GPIO72/FANIN8", "GPIO73/FANIN9", "GPIO74/FANIN10", "GPIO75/FANIN11",
+ "GPIO76/FANIN12", "GPIO77/FANIN13","GPIO78/FANIN14", "GPIO79/FANIN15",
+ "GPIO80/PWM0", &
[PATCH v5 2/2] pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver
Add Nuvoton BMC NPCM750/730/715/705 Pinmux and GPIO controller driver. Signed-off-by: Tomer Maimon --- drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig | 12 + drivers/pinctrl/nuvoton/Makefile |4 + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2076 + 5 files changed, 2094 insertions(+) create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index dd50371225bc..c966d94c2320 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -345,6 +345,7 @@ source "drivers/pinctrl/freescale/Kconfig" source "drivers/pinctrl/intel/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nomadik/Kconfig" +source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/samsung/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index de40863e7297..1797c09c8981 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -51,6 +51,7 @@ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ obj-y += mvebu/ obj-y += nomadik/ +obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM)+= qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig new file mode 100644 index ..70542c16b656 --- /dev/null +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -0,0 +1,12 @@ +config PINCTRL_NPCM7XX + bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX" + depends on (ARCH_NPCM7XX || COMPILE_TEST) && OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + help + Say Y here to enable pin controller and GPIO support + for Nuvoton NPCM750/730/715/705 SoCs. + diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile new file mode 100644 index ..886d00784cef --- /dev/null +++ b/drivers/pinctrl/nuvoton/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# Nuvoton pinctrl support + +obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c new file mode 100644 index ..3f72c21d6aff --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -0,0 +1,2076 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2016-2018 Nuvoton Technology corporation. +// Copyright (c) 2016, Dell Inc + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* GCR registers */ +#define NPCM7XX_GCR_PDID 0x00 +#define NPCM7XX_GCR_MFSEL1 0x0C +#define NPCM7XX_GCR_MFSEL2 0x10 +#define NPCM7XX_GCR_MFSEL3 0x64 +#define NPCM7XX_GCR_MFSEL4 0xb0 +#define NPCM7XX_GCR_CPCTL 0xD0 +#define NPCM7XX_GCR_CP2BST 0xD4 +#define NPCM7XX_GCR_B2CPNT 0xD8 +#define NPCM7XX_GCR_I2CSEGSEL 0xE0 +#define NPCM7XX_GCR_I2CSEGCTL 0xE4 +#define NPCM7XX_GCR_SRCNT 0x68 +#define NPCM7XX_GCR_FLOCKR10x74 +#define NPCM7XX_GCR_DSCNT 0x78 + +#define SRCNT_ESPI BIT(3) + +/* GPIO registers */ +#define NPCM7XX_GP_N_TLOCK10x00 +#define NPCM7XX_GP_N_DIN 0x04 /* Data IN */ +#define NPCM7XX_GP_N_POL 0x08 /* Polarity */ +#define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */ +#define NPCM7XX_GP_N_OE0x10 /* Output Enable */ +#define NPCM7XX_GP_N_OTYP 0x14 +#define NPCM7XX_GP_N_MP0x18 +#define NPCM7XX_GP_N_PU0x1c /* Pull-up */ +#define NPCM7XX_GP_N_PD0x20 /* Pull-down */ +#define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */ +#define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */ +#define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */ +#define NPCM7XX_GP_N_OBL0 0x30 +#define NPCM7XX_GP_N_OBL1 0x34 +#define NPCM7XX_GP_N_OBL2 0x38 +#define NPCM7XX_GP_N_OBL3 0x3c +#define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */ +#define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */ +#define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */ +#define NPCM7XX_GP_N_EVST 0x4c /* Event Status */ +#define NPCM7XX_GP_N_SPLCK 0x50 +#define NPCM7XX_GP_N_MPLCK 0x54 +#define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */ +#define NPCM7XX_GP_N_OSRC 0x5c +#define NPCM7XX_GP_N_ODSC 0x60 +#define NPC
[PATCH v5 2/2] pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver
Add Nuvoton BMC NPCM750/730/715/705 Pinmux and GPIO controller driver. Signed-off-by: Tomer Maimon --- drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig | 12 + drivers/pinctrl/nuvoton/Makefile |4 + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2076 + 5 files changed, 2094 insertions(+) create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index dd50371225bc..c966d94c2320 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -345,6 +345,7 @@ source "drivers/pinctrl/freescale/Kconfig" source "drivers/pinctrl/intel/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nomadik/Kconfig" +source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/samsung/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index de40863e7297..1797c09c8981 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -51,6 +51,7 @@ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ obj-y += mvebu/ obj-y += nomadik/ +obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM)+= qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig new file mode 100644 index ..70542c16b656 --- /dev/null +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -0,0 +1,12 @@ +config PINCTRL_NPCM7XX + bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX" + depends on (ARCH_NPCM7XX || COMPILE_TEST) && OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + help + Say Y here to enable pin controller and GPIO support + for Nuvoton NPCM750/730/715/705 SoCs. + diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile new file mode 100644 index ..886d00784cef --- /dev/null +++ b/drivers/pinctrl/nuvoton/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# Nuvoton pinctrl support + +obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c new file mode 100644 index ..3f72c21d6aff --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -0,0 +1,2076 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2016-2018 Nuvoton Technology corporation. +// Copyright (c) 2016, Dell Inc + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* GCR registers */ +#define NPCM7XX_GCR_PDID 0x00 +#define NPCM7XX_GCR_MFSEL1 0x0C +#define NPCM7XX_GCR_MFSEL2 0x10 +#define NPCM7XX_GCR_MFSEL3 0x64 +#define NPCM7XX_GCR_MFSEL4 0xb0 +#define NPCM7XX_GCR_CPCTL 0xD0 +#define NPCM7XX_GCR_CP2BST 0xD4 +#define NPCM7XX_GCR_B2CPNT 0xD8 +#define NPCM7XX_GCR_I2CSEGSEL 0xE0 +#define NPCM7XX_GCR_I2CSEGCTL 0xE4 +#define NPCM7XX_GCR_SRCNT 0x68 +#define NPCM7XX_GCR_FLOCKR10x74 +#define NPCM7XX_GCR_DSCNT 0x78 + +#define SRCNT_ESPI BIT(3) + +/* GPIO registers */ +#define NPCM7XX_GP_N_TLOCK10x00 +#define NPCM7XX_GP_N_DIN 0x04 /* Data IN */ +#define NPCM7XX_GP_N_POL 0x08 /* Polarity */ +#define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */ +#define NPCM7XX_GP_N_OE0x10 /* Output Enable */ +#define NPCM7XX_GP_N_OTYP 0x14 +#define NPCM7XX_GP_N_MP0x18 +#define NPCM7XX_GP_N_PU0x1c /* Pull-up */ +#define NPCM7XX_GP_N_PD0x20 /* Pull-down */ +#define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */ +#define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */ +#define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */ +#define NPCM7XX_GP_N_OBL0 0x30 +#define NPCM7XX_GP_N_OBL1 0x34 +#define NPCM7XX_GP_N_OBL2 0x38 +#define NPCM7XX_GP_N_OBL3 0x3c +#define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */ +#define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */ +#define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */ +#define NPCM7XX_GP_N_EVST 0x4c /* Event Status */ +#define NPCM7XX_GP_N_SPLCK 0x50 +#define NPCM7XX_GP_N_MPLCK 0x54 +#define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */ +#define NPCM7XX_GP_N_OSRC 0x5c +#define NPCM7XX_GP_N_ODSC 0x60 +#define NPC
[PATCH v5 0/2] pinctrl: nuvoton: add driver for NPCM7xx
This patch set adds pinmux and GPIO controller for the Nuvoton NPCM750/730/715/705 Baseboard Management Controller (BMC). The Nuvoton BMC NPCM750/730/715/705 Pinmux functions accessible only for pin groups and pinconf parameters available only for individual pins. The Nuvoton BMC NPCM750/730/715/705 has eight identical GPIO modules, each module has 32 GPIO ports. Most of the GPIO ports are multiplexed with other system functions. The NPCM7xx pinctrl and GPIO driver tested on NPCM750 evaluation board. Addressed comments from:. - Linus Walleij: https://www.spinics.net/lists/devicetree/msg243012.html conversion about it with Linus Walleij: - https://www.spinics.net/lists/devicetree/msg241973.html Changes since version 4: - Use direct access read and write functions. - Modify the probe GPIO and pinctrl order. - Remove unsupported BGPIOF_INVERTED_REG_DIR flag. - dt-binding documentation haven't changed. Changes since version 3: - Remove Kconfig MFD_SYSCON dependency. - Add BGPIOF_INVERTED_REG_DIR flag. - dt-binding documentation haven't changed. Changes since version 2: - Using GPIO_GENERIC (mmio). - Add Kconfig MFD_SYSCON dependency. - Remove unnecessary code from the direction output function. - dt-binding documentation haven't changed. Changes since version 1: - Remove Kconfig MFD_SYSCON dependency. - Modify setfunc function. - Modify dt-binding documentation according Rob comments. Tomer Maimon (2): dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver .../bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt | 216 ++ drivers/pinctrl/Kconfig|1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig| 12 + drivers/pinctrl/nuvoton/Makefile |4 + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2076 6 files changed, 2310 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c -- 2.14.1
[PATCH v5 0/2] pinctrl: nuvoton: add driver for NPCM7xx
This patch set adds pinmux and GPIO controller for the Nuvoton NPCM750/730/715/705 Baseboard Management Controller (BMC). The Nuvoton BMC NPCM750/730/715/705 Pinmux functions accessible only for pin groups and pinconf parameters available only for individual pins. The Nuvoton BMC NPCM750/730/715/705 has eight identical GPIO modules, each module has 32 GPIO ports. Most of the GPIO ports are multiplexed with other system functions. The NPCM7xx pinctrl and GPIO driver tested on NPCM750 evaluation board. Addressed comments from:. - Linus Walleij: https://www.spinics.net/lists/devicetree/msg243012.html conversion about it with Linus Walleij: - https://www.spinics.net/lists/devicetree/msg241973.html Changes since version 4: - Use direct access read and write functions. - Modify the probe GPIO and pinctrl order. - Remove unsupported BGPIOF_INVERTED_REG_DIR flag. - dt-binding documentation haven't changed. Changes since version 3: - Remove Kconfig MFD_SYSCON dependency. - Add BGPIOF_INVERTED_REG_DIR flag. - dt-binding documentation haven't changed. Changes since version 2: - Using GPIO_GENERIC (mmio). - Add Kconfig MFD_SYSCON dependency. - Remove unnecessary code from the direction output function. - dt-binding documentation haven't changed. Changes since version 1: - Remove Kconfig MFD_SYSCON dependency. - Modify setfunc function. - Modify dt-binding documentation according Rob comments. Tomer Maimon (2): dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver .../bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt | 216 ++ drivers/pinctrl/Kconfig|1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig| 12 + drivers/pinctrl/nuvoton/Makefile |4 + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2076 6 files changed, 2310 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c -- 2.14.1
[PATCH v4 2/2] pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver
Add Nuvoton BMC NPCM750/730/715/705 Pinmux and GPIO controller driver. Signed-off-by: Tomer Maimon --- drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig | 12 + drivers/pinctrl/nuvoton/Makefile |4 + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2082 + 5 files changed, 2100 insertions(+) create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index dd50371225bc..c966d94c2320 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -345,6 +345,7 @@ source "drivers/pinctrl/freescale/Kconfig" source "drivers/pinctrl/intel/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nomadik/Kconfig" +source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/samsung/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index de40863e7297..1797c09c8981 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -51,6 +51,7 @@ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ obj-y += mvebu/ obj-y += nomadik/ +obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM)+= qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig new file mode 100644 index ..70542c16b656 --- /dev/null +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -0,0 +1,12 @@ +config PINCTRL_NPCM7XX + bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX" + depends on (ARCH_NPCM7XX || COMPILE_TEST) && OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + help + Say Y here to enable pin controller and GPIO support + for Nuvoton NPCM750/730/715/705 SoCs. + diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile new file mode 100644 index ..886d00784cef --- /dev/null +++ b/drivers/pinctrl/nuvoton/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# Nuvoton pinctrl support + +obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c new file mode 100644 index ..f4169699e0f4 --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -0,0 +1,2082 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2016-2018 Nuvoton Technology corporation. +// Copyright (c) 2016, Dell Inc + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* GCR registers */ +#define NPCM7XX_GCR_PDID 0x00 +#define NPCM7XX_GCR_MFSEL1 0x0C +#define NPCM7XX_GCR_MFSEL2 0x10 +#define NPCM7XX_GCR_MFSEL3 0x64 +#define NPCM7XX_GCR_MFSEL4 0xb0 +#define NPCM7XX_GCR_CPCTL 0xD0 +#define NPCM7XX_GCR_CP2BST 0xD4 +#define NPCM7XX_GCR_B2CPNT 0xD8 +#define NPCM7XX_GCR_I2CSEGSEL 0xE0 +#define NPCM7XX_GCR_I2CSEGCTL 0xE4 +#define NPCM7XX_GCR_SRCNT 0x68 +#define NPCM7XX_GCR_FLOCKR10x74 +#define NPCM7XX_GCR_DSCNT 0x78 + +#define SRCNT_ESPI BIT(3) + +/* GPIO registers */ +#define NPCM7XX_GP_N_TLOCK10x00 +#define NPCM7XX_GP_N_DIN 0x04 /* Data IN */ +#define NPCM7XX_GP_N_POL 0x08 /* Polarity */ +#define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */ +#define NPCM7XX_GP_N_OE0x10 /* Output Enable */ +#define NPCM7XX_GP_N_OTYP 0x14 +#define NPCM7XX_GP_N_MP0x18 +#define NPCM7XX_GP_N_PU0x1c /* Pull-up */ +#define NPCM7XX_GP_N_PD0x20 /* Pull-down */ +#define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */ +#define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */ +#define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */ +#define NPCM7XX_GP_N_OBL0 0x30 +#define NPCM7XX_GP_N_OBL1 0x34 +#define NPCM7XX_GP_N_OBL2 0x38 +#define NPCM7XX_GP_N_OBL3 0x3c +#define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */ +#define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */ +#define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */ +#define NPCM7XX_GP_N_EVST 0x4c /* Event Status */ +#define NPCM7XX_GP_N_SPLCK 0x50 +#define NPCM7XX_GP_N_MPLCK 0x54 +#define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */ +#define NPCM7XX_GP_N_OSRC 0x5c +#define NPCM7XX_GP_N_ODSC 0x60 +#define NPC
[PATCH v4 1/2] dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation
Added device tree binding documentation for Nuvoton BMC
NPCM750/730/715/705 pinmux and GPIO controller.
Signed-off-by: Tomer Maimon
---
.../bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt | 216 +
1 file changed, 216 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
diff --git
a/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
new file mode 100644
index ..83f4bbac94bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
@@ -0,0 +1,216 @@
+Nuvoton NPCM7XX Pin Controllers
+
+The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
+the multiplexing block, Each pin supports GPIO functionality (GPIOx)
+and multiple functions that directly connect the pin to different
+hardware blocks.
+
+Required properties:
+- #address-cells : should be 1.
+- #size-cells : should be 1.
+- compatible: "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
+- ranges: defines mapping ranges between pin controller node (parent)
+ to GPIO bank node (children).
+
+=== GPIO Bank Subnode ===
+
+The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
+
+Required GPIO Bank subnode-properties:
+- reg : specifies physical base address and size of the GPIO
+ bank registers.
+- gpio-controller : Marks the device node as a GPIO controller.
+- #gpio-cells : Must be <2>. The first cell is the gpio pin number
+ and the second cell is used for optional
parameters.
+- interrupts : contain the GPIO bank interrupt with flags for
falling edge.
+- gpio-ranges : defines the range of pins managed by the GPIO bank
controller.
+
+For example, GPIO bank subnodes like the following:
+ gpio0: gpio@f001 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 0 32>;
+ };
+
+=== Pin Mux Subnode ===
+
+- pin: A string containing the name of the pin
+ An array of strings, each string containing the name of a pin.
+ These pin are used for selecting pin configuration.
+
+The following are the list of pins available:
+ "GPIO0/IOX1DI", "GPIO1/IOX1LD", "GPIO2/IOX1CK", "GPIO3/IOX1D0",
+ "GPIO4/IOX2DI/SMB1DSDA", "GPIO5/IOX2LD/SMB1DSCL",
"GPIO6/IOX2CK/SMB2DSDA",
+ "GPIO7/IOX2D0/SMB2DSCL", "GPIO8/LKGPO1", "GPIO9/LKGPO2",
"GPIO10/IOXHLD",
+ "GPIO11/IOXHCK", "GPIO12/GSPICK/SMB5BSCL", "GPIO13/GSPIDO/SMB5BSDA",
+ "GPIO14/GSPIDI/SMB5CSCL", "GPIO15/GSPICS/SMB5CSDA", "GPIO16/LKGPO0",
+ "GPIO17/PSPI2DI/SMB4DEN","GPIO18/PSPI2D0/SMB4BSDA",
"GPIO19/PSPI2CK/SMB4BSCL",
+ "GPIO20/SMB4CSDA/SMB15SDA", "GPIO21/SMB4CSCL/SMB15SCL",
"GPIO22/SMB4DSDA/SMB14SDA",
+ "GPIO23/SMB4DSCL/SMB14SCL", "GPIO24/IOXHDO", "GPIO25/IOXHDI",
"GPIO26/SMB5SDA",
+ "GPIO27/SMB5SCL", "GPIO28/SMB4SDA", "GPIO29/SMB4SCL", "GPIO30/SMB3SDA",
+ "GPIO31/SMB3SCL", "GPIO32/nSPI0CS1","SPI0D2", "SPI0D3",
"GPIO37/SMB3CSDA",
+ "GPIO38/SMB3CSCL", "GPIO39/SMB3BSDA", "GPIO40/SMB3BSCL",
"GPIO41/BSPRXD",
+ "GPO42/BSPTXD/STRAP11", "GPIO43/RXD1/JTMS2/BU1RXD",
"GPIO44/nCTS1/JTDI2/BU1CTS",
+ "GPIO45/nDCD1/JTDO2", "GPIO46/nDSR1/JTCK2", "GPIO47/nRI1/JCP_RDY2",
+ "GPIO48/TXD2/BSPTXD", "GPIO49/RXD2/BSPRXD", "GPIO50/nCTS2",
"GPO51/nRTS2/STRAP2",
+ "GPIO52/nDCD2", "GPO53/nDTR2_BOUT2/STRAP1", "GPIO54/nDSR2",
"GPIO55/nRI2",
+ "GPIO56/R1RXERR", "GPIO57/R1MDC", "GPIO58/R1MDIO", "GPIO59/SMB3DSDA",
+ "GPIO60/SMB3DSCL", "GPO61/nDTR1_BOUT1/STRAP6", "GPO62/nRTST1/STRAP5",
+ "GPO63/TXD1/STRAP4", "GPIO64/FANIN0", "GPIO65/FANIN1", "GPIO66/FANIN2",
+ "GPIO67/FANIN3", "GPIO68/FANIN4", "GPIO69/FANIN5", "GPIO70/FANIN6",
"GPIO71/FANIN7",
+ "GPIO72/FANIN8", "GPIO73/FANIN9", "GPIO74/FANIN10", "GPIO75/FANIN11",
+ "GPIO76/FANIN12", "GPIO77/FANIN13","GPIO78/FANIN14", "GPIO79/FANIN15",
+ "GPIO80/PWM0", &
[PATCH v4 2/2] pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver
Add Nuvoton BMC NPCM750/730/715/705 Pinmux and GPIO controller driver. Signed-off-by: Tomer Maimon --- drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig | 12 + drivers/pinctrl/nuvoton/Makefile |4 + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2082 + 5 files changed, 2100 insertions(+) create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index dd50371225bc..c966d94c2320 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -345,6 +345,7 @@ source "drivers/pinctrl/freescale/Kconfig" source "drivers/pinctrl/intel/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" source "drivers/pinctrl/nomadik/Kconfig" +source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/samsung/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index de40863e7297..1797c09c8981 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -51,6 +51,7 @@ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ obj-y += mvebu/ obj-y += nomadik/ +obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM)+= qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig new file mode 100644 index ..70542c16b656 --- /dev/null +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -0,0 +1,12 @@ +config PINCTRL_NPCM7XX + bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX" + depends on (ARCH_NPCM7XX || COMPILE_TEST) && OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + help + Say Y here to enable pin controller and GPIO support + for Nuvoton NPCM750/730/715/705 SoCs. + diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile new file mode 100644 index ..886d00784cef --- /dev/null +++ b/drivers/pinctrl/nuvoton/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# Nuvoton pinctrl support + +obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c new file mode 100644 index ..f4169699e0f4 --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -0,0 +1,2082 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2016-2018 Nuvoton Technology corporation. +// Copyright (c) 2016, Dell Inc + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* GCR registers */ +#define NPCM7XX_GCR_PDID 0x00 +#define NPCM7XX_GCR_MFSEL1 0x0C +#define NPCM7XX_GCR_MFSEL2 0x10 +#define NPCM7XX_GCR_MFSEL3 0x64 +#define NPCM7XX_GCR_MFSEL4 0xb0 +#define NPCM7XX_GCR_CPCTL 0xD0 +#define NPCM7XX_GCR_CP2BST 0xD4 +#define NPCM7XX_GCR_B2CPNT 0xD8 +#define NPCM7XX_GCR_I2CSEGSEL 0xE0 +#define NPCM7XX_GCR_I2CSEGCTL 0xE4 +#define NPCM7XX_GCR_SRCNT 0x68 +#define NPCM7XX_GCR_FLOCKR10x74 +#define NPCM7XX_GCR_DSCNT 0x78 + +#define SRCNT_ESPI BIT(3) + +/* GPIO registers */ +#define NPCM7XX_GP_N_TLOCK10x00 +#define NPCM7XX_GP_N_DIN 0x04 /* Data IN */ +#define NPCM7XX_GP_N_POL 0x08 /* Polarity */ +#define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */ +#define NPCM7XX_GP_N_OE0x10 /* Output Enable */ +#define NPCM7XX_GP_N_OTYP 0x14 +#define NPCM7XX_GP_N_MP0x18 +#define NPCM7XX_GP_N_PU0x1c /* Pull-up */ +#define NPCM7XX_GP_N_PD0x20 /* Pull-down */ +#define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */ +#define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */ +#define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */ +#define NPCM7XX_GP_N_OBL0 0x30 +#define NPCM7XX_GP_N_OBL1 0x34 +#define NPCM7XX_GP_N_OBL2 0x38 +#define NPCM7XX_GP_N_OBL3 0x3c +#define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */ +#define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */ +#define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */ +#define NPCM7XX_GP_N_EVST 0x4c /* Event Status */ +#define NPCM7XX_GP_N_SPLCK 0x50 +#define NPCM7XX_GP_N_MPLCK 0x54 +#define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */ +#define NPCM7XX_GP_N_OSRC 0x5c +#define NPCM7XX_GP_N_ODSC 0x60 +#define NPC
[PATCH v4 1/2] dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation
Added device tree binding documentation for Nuvoton BMC
NPCM750/730/715/705 pinmux and GPIO controller.
Signed-off-by: Tomer Maimon
---
.../bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt | 216 +
1 file changed, 216 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
diff --git
a/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
new file mode 100644
index ..83f4bbac94bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt
@@ -0,0 +1,216 @@
+Nuvoton NPCM7XX Pin Controllers
+
+The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
+the multiplexing block, Each pin supports GPIO functionality (GPIOx)
+and multiple functions that directly connect the pin to different
+hardware blocks.
+
+Required properties:
+- #address-cells : should be 1.
+- #size-cells : should be 1.
+- compatible: "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
+- ranges: defines mapping ranges between pin controller node (parent)
+ to GPIO bank node (children).
+
+=== GPIO Bank Subnode ===
+
+The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
+
+Required GPIO Bank subnode-properties:
+- reg : specifies physical base address and size of the GPIO
+ bank registers.
+- gpio-controller : Marks the device node as a GPIO controller.
+- #gpio-cells : Must be <2>. The first cell is the gpio pin number
+ and the second cell is used for optional
parameters.
+- interrupts : contain the GPIO bank interrupt with flags for
falling edge.
+- gpio-ranges : defines the range of pins managed by the GPIO bank
controller.
+
+For example, GPIO bank subnodes like the following:
+ gpio0: gpio@f001 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x80>;
+ interrupts = ;
+ gpio-ranges = < 0 0 32>;
+ };
+
+=== Pin Mux Subnode ===
+
+- pin: A string containing the name of the pin
+ An array of strings, each string containing the name of a pin.
+ These pin are used for selecting pin configuration.
+
+The following are the list of pins available:
+ "GPIO0/IOX1DI", "GPIO1/IOX1LD", "GPIO2/IOX1CK", "GPIO3/IOX1D0",
+ "GPIO4/IOX2DI/SMB1DSDA", "GPIO5/IOX2LD/SMB1DSCL",
"GPIO6/IOX2CK/SMB2DSDA",
+ "GPIO7/IOX2D0/SMB2DSCL", "GPIO8/LKGPO1", "GPIO9/LKGPO2",
"GPIO10/IOXHLD",
+ "GPIO11/IOXHCK", "GPIO12/GSPICK/SMB5BSCL", "GPIO13/GSPIDO/SMB5BSDA",
+ "GPIO14/GSPIDI/SMB5CSCL", "GPIO15/GSPICS/SMB5CSDA", "GPIO16/LKGPO0",
+ "GPIO17/PSPI2DI/SMB4DEN","GPIO18/PSPI2D0/SMB4BSDA",
"GPIO19/PSPI2CK/SMB4BSCL",
+ "GPIO20/SMB4CSDA/SMB15SDA", "GPIO21/SMB4CSCL/SMB15SCL",
"GPIO22/SMB4DSDA/SMB14SDA",
+ "GPIO23/SMB4DSCL/SMB14SCL", "GPIO24/IOXHDO", "GPIO25/IOXHDI",
"GPIO26/SMB5SDA",
+ "GPIO27/SMB5SCL", "GPIO28/SMB4SDA", "GPIO29/SMB4SCL", "GPIO30/SMB3SDA",
+ "GPIO31/SMB3SCL", "GPIO32/nSPI0CS1","SPI0D2", "SPI0D3",
"GPIO37/SMB3CSDA",
+ "GPIO38/SMB3CSCL", "GPIO39/SMB3BSDA", "GPIO40/SMB3BSCL",
"GPIO41/BSPRXD",
+ "GPO42/BSPTXD/STRAP11", "GPIO43/RXD1/JTMS2/BU1RXD",
"GPIO44/nCTS1/JTDI2/BU1CTS",
+ "GPIO45/nDCD1/JTDO2", "GPIO46/nDSR1/JTCK2", "GPIO47/nRI1/JCP_RDY2",
+ "GPIO48/TXD2/BSPTXD", "GPIO49/RXD2/BSPRXD", "GPIO50/nCTS2",
"GPO51/nRTS2/STRAP2",
+ "GPIO52/nDCD2", "GPO53/nDTR2_BOUT2/STRAP1", "GPIO54/nDSR2",
"GPIO55/nRI2",
+ "GPIO56/R1RXERR", "GPIO57/R1MDC", "GPIO58/R1MDIO", "GPIO59/SMB3DSDA",
+ "GPIO60/SMB3DSCL", "GPO61/nDTR1_BOUT1/STRAP6", "GPO62/nRTST1/STRAP5",
+ "GPO63/TXD1/STRAP4", "GPIO64/FANIN0", "GPIO65/FANIN1", "GPIO66/FANIN2",
+ "GPIO67/FANIN3", "GPIO68/FANIN4", "GPIO69/FANIN5", "GPIO70/FANIN6",
"GPIO71/FANIN7",
+ "GPIO72/FANIN8", "GPIO73/FANIN9", "GPIO74/FANIN10", "GPIO75/FANIN11",
+ "GPIO76/FANIN12", "GPIO77/FANIN13","GPIO78/FANIN14", "GPIO79/FANIN15",
+ "GPIO80/PWM0", &
[PATCH v4 0/2] pinctrl: nuvoton: add driver for NPCM7xx
This patch set adds pinmux and GPIO controller for the Nuvoton NPCM750/730/715/705 Baseboard Management Controller (BMC). The Nuvoton BMC NPCM750/730/715/705 Pinmux functions accessible only for pin groups and pinconf parameters available only for individual pins. The Nuvoton BMC NPCM750/730/715/705 has eight identical GPIO modules, each module has 32 GPIO ports. Most of the GPIO ports are multiplexed with other system functions. The NPCM7xx pinctrl and GPIO driver tested on NPCM750 evaluation board. this patch set depend on gpio: mmio: add inverted direction get_set io support approval. https://lore.kernel.org/patchwork/patch/968891/ without adding BGPIOF_INVERTED_REG_DIR to include/linux/gpio/driver.h the build will failed. Addressed comments from:. - kbuild test robot: https://www.spinics.net/lists/kernel/msg2868491.html conversion about it with Linus Walleij: - https://www.spinics.net/lists/devicetree/msg241973.html Changes since version 3: - Remove Kconfig MFD_SYSCON dependency. - Add BGPIOF_INVERTED_REG_DIR flag. - dt-binding documentation haven't changed. Changes since version 2: - Using GPIO_GENERIC (mmio). - Add Kconfig MFD_SYSCON dependency. - Remove unnecessary code from the direction output function. - dt-binding documentation haven't changed. Changes since version 1: - Remove Kconfig MFD_SYSCON dependency. - Modify setfunc function. - Modify dt-binding documentation according Rob comments. Tomer Maimon (2): dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver .../bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt | 216 ++ drivers/pinctrl/Kconfig|1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig| 12 + drivers/pinctrl/nuvoton/Makefile |4 + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2082 6 files changed, 2316 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c -- 2.14.1
[PATCH v4 0/2] pinctrl: nuvoton: add driver for NPCM7xx
This patch set adds pinmux and GPIO controller for the Nuvoton NPCM750/730/715/705 Baseboard Management Controller (BMC). The Nuvoton BMC NPCM750/730/715/705 Pinmux functions accessible only for pin groups and pinconf parameters available only for individual pins. The Nuvoton BMC NPCM750/730/715/705 has eight identical GPIO modules, each module has 32 GPIO ports. Most of the GPIO ports are multiplexed with other system functions. The NPCM7xx pinctrl and GPIO driver tested on NPCM750 evaluation board. this patch set depend on gpio: mmio: add inverted direction get_set io support approval. https://lore.kernel.org/patchwork/patch/968891/ without adding BGPIOF_INVERTED_REG_DIR to include/linux/gpio/driver.h the build will failed. Addressed comments from:. - kbuild test robot: https://www.spinics.net/lists/kernel/msg2868491.html conversion about it with Linus Walleij: - https://www.spinics.net/lists/devicetree/msg241973.html Changes since version 3: - Remove Kconfig MFD_SYSCON dependency. - Add BGPIOF_INVERTED_REG_DIR flag. - dt-binding documentation haven't changed. Changes since version 2: - Using GPIO_GENERIC (mmio). - Add Kconfig MFD_SYSCON dependency. - Remove unnecessary code from the direction output function. - dt-binding documentation haven't changed. Changes since version 1: - Remove Kconfig MFD_SYSCON dependency. - Modify setfunc function. - Modify dt-binding documentation according Rob comments. Tomer Maimon (2): dt-binding: pinctrl: Add NPCM7xx pinctrl and GPIO documentation pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver .../bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt | 216 ++ drivers/pinctrl/Kconfig|1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/nuvoton/Kconfig| 12 + drivers/pinctrl/nuvoton/Makefile |4 + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2082 6 files changed, 2316 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt create mode 100644 drivers/pinctrl/nuvoton/Kconfig create mode 100644 drivers/pinctrl/nuvoton/Makefile create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c -- 2.14.1
[PATCH v1 0/1] gpio: mmio: add get_set inverted direction io support
When bgpio direction register use dirin and setting BGPIOF_READ_OUTPUT_REG_SET flag, the get_set I/O functions reading the inverted set register of each direction, it means: when direction=in the get_set function read set register. when direction=out the get_set function read dat register. but is should be inverted. conversion about it with Linus Walleij: https://www.spinics.net/lists/devicetree/msg241973.html to solve it, adding get_set_inv_dir and get_set_multiple_inv_dir I/O functions to call the data register when the direction is input and set register when the direction is output. the functions will linked to the I/O get functions if the user set BGPIOF_INVERTED_REG_DIR flag in the bgpio initialization. Tomer Maimon (1): gpio: mmio: add inverted direction get_set io support drivers/gpio/gpio-mmio.c| 48 ++--- include/linux/gpio/driver.h | 1 + 2 files changed, 46 insertions(+), 3 deletions(-) -- 2.14.1
[PATCH v1 0/1] gpio: mmio: add get_set inverted direction io support
When bgpio direction register use dirin and setting BGPIOF_READ_OUTPUT_REG_SET flag, the get_set I/O functions reading the inverted set register of each direction, it means: when direction=in the get_set function read set register. when direction=out the get_set function read dat register. but is should be inverted. conversion about it with Linus Walleij: https://www.spinics.net/lists/devicetree/msg241973.html to solve it, adding get_set_inv_dir and get_set_multiple_inv_dir I/O functions to call the data register when the direction is input and set register when the direction is output. the functions will linked to the I/O get functions if the user set BGPIOF_INVERTED_REG_DIR flag in the bgpio initialization. Tomer Maimon (1): gpio: mmio: add inverted direction get_set io support drivers/gpio/gpio-mmio.c| 48 ++--- include/linux/gpio/driver.h | 1 + 2 files changed, 46 insertions(+), 3 deletions(-) -- 2.14.1
