[PATCH v1] ARM: dts: Fix 64MiB OpenBMC flash layout and aspeed-ast2600-evb.dts

[Troy Lee]

Aspeed AST2600 u-boot requires 600KiB+ flash space. Sharing the same
openbmc-flash-layout-64.dtsi requires to resize the flash partition.

The updated flash layout as follows:
- u-boot: 896 KiB
- u-boot-env: 128 KiB
- kernel: 9MiB
- rofs: 32 MiB
- rwfs: 22 MiB

Signed-off-by: Troy Lee 
---
 arch/arm/boot/dts/aspeed-ast2600-evb.dts  | 32 +--
 .../arm/boot/dts/openbmc-flash-layout-64.dtsi | 18 +--
 2 files changed, 10 insertions(+), 40 deletions(-)

diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts 
b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index 89be13197780..2cfae9cfed3a 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -121,37 +121,7 @@ flash@0 {
m25p,fast-read;
label = "bmc";
spi-max-frequency = <5000>;
-
-   partitions {
-   compatible = "fixed-partitions";
-   #address-cells = <1>;
-   #size-cells = <1>;
-
-   u-boot@0 {
-   reg = <0x0 0xe>; // 896KB
-   label = "u-boot";
-   };
-
-   u-boot-env@e {
-   reg = <0xe 0x2>; // 128KB
-   label = "u-boot-env";
-   };
-
-   kernel@10 {
-   reg = <0x10 0x90>; // 9MB
-   label = "kernel";
-   };
-
-   rofs@a0 {
-   reg = <0xa0 0x200>; // 32MB
-   label = "rofs";
-   };
-
-   rwfs@600 {
-   reg = <0x2a0 0x160>; // 22MB
-   label = "rwfs";
-   };
-   };
+#include "openbmc-flash-layout-64.dtsi"
};
 };
 
diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi 
b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi
index 91163867be34..31f59de5190b 100644
--- a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi
+++ b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi
@@ -9,27 +9,27 @@ partitions {
#size-cells = <1>;
 
u-boot@0 {
-   reg = <0x0 0x6>; // 384KB
+   reg = <0x0 0xe>; // 896KB
label = "u-boot";
};
 
-   u-boot-env@6 {
-   reg = <0x6 0x2>; // 128KB
+   u-boot-env@e {
+   reg = <0xe 0x2>; // 128KB
label = "u-boot-env";
};
 
-   kernel@8 {
-   reg = <0x8 0x50>; // 5MB
+   kernel@10 {
+   reg = <0x10 0x90>; // 9MB
label = "kernel";
};
 
-   rofs@58 {
-   reg = <0x58 0x2a8>; // 42.5MB
+   rofs@a0 {
+   reg = <0xa0 0x200>; // 32MB
label = "rofs";
};
 
-   rwfs@300 {
-   reg = <0x300 0x100>; // 16MB
+   rwfs@600 {
+   reg = <0x2a0 0x160>; // 22MB
label = "rwfs";
};
 };
-- 
2.25.1

Re: [PATCH v3 4/4] hwmon: Support Aspeed AST2600 PWM/Fan tachometer

[Troy Lee]

Hi Andrew,

The 01/22/2021 12:38, Andrew Jeffery wrote:
> Hi Troy,
> 
> On Mon, 18 Jan 2021, at 17:20, Troy Lee wrote:
> > Add Aspeed AST2600 PWM/Fan tacho driver. AST2600 has 16 PWM channel and
> > 16 FAN tacho channel.
> > 
> > Changes since v2:
> >  - declare local function as static function
> > 
> > Changes since v1:
> >  - fixed review comments
> >  - fixed double-looped calculation of div_h and div_l
> >  - moving configuration to device tree
> >  - register hwmon driver with devm_hwmon_device_register_with_info()
> > 
> > Signed-off-by: Troy Lee 
> > Reported-by: kernel test robot 
> > ---
...

> > diff --git a/drivers/hwmon/aspeed2600-pwm-tacho.c 
> > b/drivers/hwmon/aspeed2600-pwm-tacho.c
> > new file mode 100644
> > index ..00ff100db92f
> > --- /dev/null
> > +++ b/drivers/hwmon/aspeed2600-pwm-tacho.c
> > @@ -0,0 +1,756 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +/*
> > + * Copyright (C) ASPEED Technology Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 or 
> > later as
> > + * published by the Free Software Foundation.
> > + */
> 
> The license is captured by the SPDX marker above. This summary text should be 
> dropped (though retain the copyright line).
> 
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +/**
> > + * PWM HW register offset define
> > + */
> 
> Banner comments like this generally aren't preferred. If you think the 
> comment text itself is necessary, just do:
> 
> /* PWM HW register offset define */
> 
> However, the macro names should indicate what we're defining anyway, so I 
> feel we can remove it entirely without too much loss
> 
I'll remove the redundant description and comments.

> > +/* PWM Control Register */
> > +#define ASPEED_PWM_CTRL_CH(ch) (((ch) * 0x10) + 0x00)
> > +/* PWM Duty Cycle Register */
> > +#define ASPEED_PWM_DUTY_CYCLE_CH(ch)   (((ch) * 0x10) + 0x04)
> > +/* TACH Control Register */
> > +#define ASPEED_TACHO_CTRL_CH(ch)   (((ch) * 0x10) + 0x08)
> > +/* TACH Status Register */
> > +#define ASPEED_TACHO_STS_CH(x) (((x) * 0x10) + 0x0C)
> > +
> > +/**
> > + * PWM register Bit field
> > + */
> > +/*PWM_CTRL */
> > +#define PWM_LOAD_SEL_AS_WDT_BIT(19)/* load selection as 
> > WDT */
> 
> The trailing comments don't really add any further information in the context 
> of the macro name. Let's remove these as well.
> 
> > +#define PWM_DUTY_LOAD_AS_WDT_ENBIT(18) /* enable PWM duty load 
> > as 
> > WDT */
> > +#define PWM_DUTY_SYNC_DIS  BIT(17) /* disable PWM duty sync */
> > +#define PWM_CLK_ENABLE BIT(16) /* enable PWM clock */
> > +#define PWM_LEVEL_OUTPUT   BIT(15) /* output PWM level */
> > +#define PWM_INVERSEBIT(14) /* inverse PWM pin */
> > +#define PWM_OPEN_DRAIN_EN  BIT(13) /* enable open-drain */
> > +#define PWM_PIN_EN BIT(12) /* enable PWM pin */
> > +#define PWM_CLK_DIV_H_MASK (0xf << 8) /* PWM clock division H bit 
> > [3:0] */
> > +#define PWM_CLK_DIV_L_MASK (0xff)  /* PWM clock division H bit 
> > [3:0] */
> > +/* [19] */
> > +#define LOAD_SEL_FALLING 0
> > +#define LOAD_SEL_RIGING  1
> 
> It's much easier to track these macros if you place them alongside the 
> associated register, and in a way that makes them self-documenting (i.e. we 
> remove the need for the banner comments). Often the bit/mask macros are 
> indented to help with visuals, for example:
> 
> #define ASPEED_PWM_CTRL_CH(ch)(((ch) * 0x10) + 0x00)
> #define PWM_DUTY_LOAD_AS_WDT_EN   BIT(18)
> #define PWM_DUTY_SYNC_DIS BIT(17)
> ...
> 
> #define ASPEED_PWM_DUTY_CYCLE_CH(ch)  (((ch) * 0x10) + 0x04)
> #define PWM_PERIOD_BIT   

Re: [PATCH v2 4/4] hwmon: Support Aspeed AST2600 PWM/Fan tachometer

[Troy Lee]

Hi Guenter,

The 01/24/2021 00:14, Guenter Roeck wrote:
> On Wed, Jan 13, 2021 at 07:08:48AM +0000, Troy Lee wrote:
> > Add Aspeed AST2600 PWM/Fan tacho driver. AST2600 has 16 PWM channel and
> > 16 FAN tacho channel.
> > 
> > Changes since v1:
> > - fixed review comments
> > - fixed double-looped calculation of div_h and div_l
> > - moving configuration to device tree
> > - register hwmon driver with devm_hwmon_device_register_with_info()
> > 
> > Signed-off-by: Troy Lee 
> 
> checkpatch says:
> 
> total: 0 errors, 9 warnings, 26 checks, 779 lines checked
> 
> This is a bit much. Please run checkpatch --strict and fix the issues
> it reports. Please also fix the issues reported by 0-day as well as
> the issues reported by the bindings robot, and resubmit.
> 
> Thanks,
> Guenter

I'll fix the WARNINGs and CHECKs.

Thanks,
Troy Lee

[PATCH v3 1/4] dt-bindings: hwmon: Add Aspeed AST2600 PWM/Fan

[Troy Lee]

We add binding for supporting a new AST2600 PWM/Fan hwmon driver.

Changes since v2:
 - Fixed yamllint warnings/errors

Changes since v1:
 - dt binding with DT schema format

Signed-off-by: Troy Lee 
Reported-by: Rob Herring 
---
 .../hwmon/aspeed,ast2600-pwm-tachometer.yaml  | 131 ++
 1 file changed, 131 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml

diff --git 
a/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml 
b/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml
new file mode 100644
index ..fa5340f5a43f
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/hwmon/aspeed,ast2600-pwm-tachometer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED AST2600 PWM and Fan Tacho controller device driver
+
+maintainers:
+  - Ryan Chen 
+
+description: |
+  The ASPEED PWM controller can support upto 16 PWM outputs. The ASPEED Fan 
Tacho
+  controller can support upto 16 Fan tachometer inputs.
+  There can be upto 16 fans supported. Each fan can have one PWM output and
+  one Fan tach inputs.
+
+properties:
+  compatible:
+const: aspeed,ast2600-pwm-tachometer
+
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 0
+
+  "#cooling-cells":
+const: 2
+
+  reg:
+maxItems: 1
+
+  clocks:
+maxItems: 1
+
+  resets:
+maxItems: 1
+
+patternProperties:
+  "^fan@[0-9a-f]$":
+type: object
+description:
+  Under fan subnode there can upto 16 child nodes, with each child node
+  representing a fan. There are 16 fans each fan can have one PWM port and 
one
+  Fan tach inputs.
+  For PWM port can be configured cooling-levels to create cooling device.
+  Cooling device could be bound to a thermal zone for the thermal control.
+
+properties:
+  reg:
+minimum: 0
+maximum: 15
+description:
+  This property identify the PWM control channel of this fan.
+
+  fan-tach-ch:
+$ref: /schemas/types.yaml#/definitions/uint8
+minimum: 0
+maximum: 15
+description:
+  This property identify the fan tach input channel.
+
+  pulses-per-revolution:
+$ref: /schemas/types.yaml#/definitions/uint32
+default: 2
+minimum: 1
+description:
+  Specify tacho pulse per revolution of the fan.
+
+  cooling-levels:
+description:
+  PWM duty cycle values in a range from 0 to 255
+  which correspond to thermal cooling states.
+
+  aspeed,pwm-freq-hz:
+default: 25000
+minimum: 24
+maximum: 78
+description:
+  Specify the frequency of PWM.
+
+  aspeed,inverse-pin:
+type: boolean
+description:
+  Inverse PWM output signal.
+
+  aspeed,falling-point:
+$ref: /schemas/types.yaml#/definitions/uint8
+default: 10
+description:
+  Initialize the pulse width.
+
+required:
+  - fan-tach-ch
+  - reg
+
+additionalProperties: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+pwm_tacho: pwm-tacho-controller@1e61 {
+compatible = "aspeed,ast2600-pwm-tachometer";
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0x1e61 0x100>;
+
+fan@1 {
+reg = <0x00>;
+aspeed,pwm-freq-hz = <25000>;
+cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+fan-tach-ch = /bits/ 8 <0x00>;
+pulses-per-revolution = <2>;
+};
+
+fan@2 {
+reg = <0x01>;
+aspeed,pwm-freq-hz = <25000>;
+cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+fan-tach-ch = /bits/ 8 <0x01>;
+pulses-per-revolution = <2>;
+};
+};
+...
-- 
2.25.1

[PATCH v3 4/4] hwmon: Support Aspeed AST2600 PWM/Fan tachometer

[Troy Lee]

Add Aspeed AST2600 PWM/Fan tacho driver. AST2600 has 16 PWM channel and
16 FAN tacho channel.

Changes since v2:
 - declare local function as static function

Changes since v1:
 - fixed review comments
 - fixed double-looped calculation of div_h and div_l
 - moving configuration to device tree
 - register hwmon driver with devm_hwmon_device_register_with_info()

Signed-off-by: Troy Lee 
Reported-by: kernel test robot 
---
 drivers/hwmon/Kconfig|  10 +
 drivers/hwmon/Makefile   |   1 +
 drivers/hwmon/aspeed2600-pwm-tacho.c | 756 +++
 3 files changed, 767 insertions(+)
 create mode 100644 drivers/hwmon/aspeed2600-pwm-tacho.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 1ecf697d8d99..98f89f703161 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -400,6 +400,16 @@ config SENSORS_ASPEED
  This driver can also be built as a module. If so, the module
  will be called aspeed_pwm_tacho.
 
+config SENSORS_ASPEED2600_PWM_TACHO
+   tristate "ASPEED AST2600 PWM and Fan Tachometer"
+   depends on THERMAL || THERMAL=n
+   help
+ This driver provides support for ASPEED AST2600 PWM
+ and Fan Tacho controllers.
+
+ This driver can also be built as a module. If so, the module
+ will be called aspeed2600-pwm-tacho.
+
 config SENSORS_ATXP1
tristate "Attansic ATXP1 VID controller"
depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 09a86c5e1d29..1a415d493ffc 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_SENSORS_ARM_SCPI)+= scpi-hwmon.o
 obj-$(CONFIG_SENSORS_AS370)+= as370-hwmon.o
 obj-$(CONFIG_SENSORS_ASC7621)  += asc7621.o
 obj-$(CONFIG_SENSORS_ASPEED)   += aspeed-pwm-tacho.o
+obj-$(CONFIG_SENSORS_ASPEED2600_PWM_TACHO) += aspeed2600-pwm-tacho.o
 obj-$(CONFIG_SENSORS_ATXP1)+= atxp1.o
 obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o
 obj-$(CONFIG_SENSORS_BT1_PVT)  += bt1-pvt.o
diff --git a/drivers/hwmon/aspeed2600-pwm-tacho.c 
b/drivers/hwmon/aspeed2600-pwm-tacho.c
new file mode 100644
index ..00ff100db92f
--- /dev/null
+++ b/drivers/hwmon/aspeed2600-pwm-tacho.c
@@ -0,0 +1,756 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or later as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+/**
+ * PWM HW register offset define
+ */
+/* PWM Control Register */
+#define ASPEED_PWM_CTRL_CH(ch) (((ch) * 0x10) + 0x00)
+/* PWM Duty Cycle Register */
+#define ASPEED_PWM_DUTY_CYCLE_CH(ch)   (((ch) * 0x10) + 0x04)
+/* TACH Control Register */
+#define ASPEED_TACHO_CTRL_CH(ch)   (((ch) * 0x10) + 0x08)
+/* TACH Status Register */
+#define ASPEED_TACHO_STS_CH(x) (((x) * 0x10) + 0x0C)
+
+/**
+ * PWM register Bit field
+ */
+/*PWM_CTRL */
+#define PWM_LOAD_SEL_AS_WDT_BIT(19)/* load selection as 
WDT */
+#define PWM_DUTY_LOAD_AS_WDT_ENBIT(18) /* enable PWM duty load 
as WDT */
+#define PWM_DUTY_SYNC_DIS  BIT(17) /* disable PWM duty sync */
+#define PWM_CLK_ENABLE BIT(16) /* enable PWM clock */
+#define PWM_LEVEL_OUTPUT   BIT(15) /* output PWM level */
+#define PWM_INVERSEBIT(14) /* inverse PWM pin */
+#define PWM_OPEN_DRAIN_EN  BIT(13) /* enable open-drain */
+#define PWM_PIN_EN BIT(12) /* enable PWM pin */
+#define PWM_CLK_DIV_H_MASK (0xf << 8) /* PWM clock division H bit 
[3:0] */
+#define PWM_CLK_DIV_L_MASK (0xff)  /* PWM clock division H bit 
[3:0] */
+/* [19] */
+#define LOAD_SEL_FALLING 0
+#define LOAD_SEL_RIGING  1
+
+/*PWM_DUTY_CYCLE */
+#define PWM_PERIOD_BIT (24)/* pwm period bit [7:0] 
*/
+#define PWM_PERIOD_BIT_MASK(0xff << 24)/* pwm period bit [7:0] 
*/
+#define PWM_RISING_FALLING_AS_WDT_BIT  (16)
+#define PWM_RISING_FALLING_AS_WDT_MASK (0xff << 16)/* rising/falling point 
bit [7:0] as WDT */
+#define PWM_RISING_FALLING_MASK(0x)
+#define PWM_FALLING_POINT_BIT  (8) /* pwm falling point 
bit [7:0] */
+#define PWM_RISING_POINT_BIT   (0) /* pwm rising point bit 
[7:0] */
+/* [31:24] */
+#define DEFAULT_PWM_PERIOD 0xff
+
+

[PATCH v3 3/4] ARM: dts: aspeed: Add Aspeed AST2600 PWM/Fan node in devicetree

[Troy Lee]

Create a common node in aspeed-g6.dtsi and add fan nodes for ast2600-evb
dts file.

Changes since v2:
 - Change property name pwm-freq to pwm-freq-hz

Changes since v1:
 - rename properties name in child node

Signed-off-by: Troy Lee 
---
 arch/arm/boot/dts/aspeed-ast2600-evb.dts | 152 +++
 arch/arm/boot/dts/aspeed-g6.dtsi |  10 ++
 2 files changed, 162 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts 
b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index 89be13197780..4d24c051eeae 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -23,6 +23,158 @@ memory@8000 {
};
 };
 
+&pwm_tacho {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_tach0_default
+   &pinctrl_pwm1_default &pinctrl_tach1_default
+   &pinctrl_pwm2_default &pinctrl_tach2_default
+   &pinctrl_pwm3_default &pinctrl_tach3_default
+   &pinctrl_pwm4_default &pinctrl_tach4_default
+   &pinctrl_pwm5_default &pinctrl_tach5_default
+   &pinctrl_pwm6_default &pinctrl_tach6_default
+   &pinctrl_pwm7_default &pinctrl_tach7_default
+   &pinctrl_pwm8g1_default &pinctrl_tach8_default
+   &pinctrl_pwm9g1_default &pinctrl_tach9_default
+   &pinctrl_pwm10g1_default &pinctrl_tach10_default
+   &pinctrl_pwm11g1_default &pinctrl_tach11_default
+   &pinctrl_pwm12g1_default &pinctrl_tach12_default
+   &pinctrl_pwm13g1_default &pinctrl_tach13_default
+   &pinctrl_pwm14g1_default &pinctrl_tach14_default
+   &pinctrl_pwm15g1_default &pinctrl_tach15_default>;
+
+   fan@0 {
+   reg = <0x00>;
+   aspeed,pwm-freq-hz = <25000>;
+   aspeed,falling-point = /bits/ 8 <100>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x00>;
+   aspeed,tacho-div = <3>;
+   pulses-per-revolution = <1>;
+   };
+
+   fan@1 {
+   reg = <0x01>;
+   aspeed,pwm-freq-hz = <25000>;
+   aspeed,falling-point = /bits/ 8 <100>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x01>;
+   pulses-per-revolution = <1>;
+   };
+
+   fan@2 {
+   reg = <0x02>;
+   aspeed,pwm-freq-hz = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x02>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@3 {
+   reg = <0x03>;
+   aspeed,pwm-freq-hz = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x03>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@4 {
+   reg = <0x04>;
+   aspeed,pwm-freq-hz = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x04>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@5 {
+   reg = <0x05>;
+   aspeed,pwm-freq-hz = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x05>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@6 {
+   reg = <0x06>;
+   aspeed,pwm-freq-hz = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x06>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@7 {
+   reg = <0x07>;
+   aspeed,pwm-freq-hz = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x07>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@8 {
+   reg = <0x08>;
+   aspeed,pwm-freq-hz = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x08>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@9 {
+   reg = <0x09>;
+   aspeed,pwm-freq-hz = <25000&

[PATCH v3 2/4] hwmon: Add Aspeed AST2600 support

[Troy Lee]

Updating index.rst and adding aspeed2600-pwm-tachometer.rst to address
the driver.

Changes since v1:
 - rename to aspeed2600-pwm-tachometer.rst
 - add license identifier

Signed-off-by: Troy Lee 
---
 .../hwmon/aspeed2600-pwm-tachometer.rst   | 27 +++
 Documentation/hwmon/index.rst |  1 +
 2 files changed, 28 insertions(+)
 create mode 100644 Documentation/hwmon/aspeed2600-pwm-tachometer.rst

diff --git a/Documentation/hwmon/aspeed2600-pwm-tachometer.rst 
b/Documentation/hwmon/aspeed2600-pwm-tachometer.rst
new file mode 100644
index ..cf0d31a19597
--- /dev/null
+++ b/Documentation/hwmon/aspeed2600-pwm-tachometer.rst
@@ -0,0 +1,27 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+===
+Kernel driver aspeed2600-pwm-tachometer
+===
+
+Supported chips:
+   ASPEED AST2600
+
+Authors:
+   Ryan Chen 
+
+Description:
+
+This driver implements support for ASPEED AST2600 PWM and Fan Tacho
+controller. The PWM controller supports upto 16 PWM outputs. The Fan tacho
+controller supports up to 16 tachometer inputs.
+
+The driver provides the following sensor accesses in sysfs:
+
+=== === =
+fanX_input ro  provide current fan rotation value in RPM as reported
+   by the fan to the device.
+
+pwmX   rw  get or set PWM fan control value. This is an integer
+   value between 0(off) and 255(full speed).
+=== === =
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index fcb870ce6286..02020c282549 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -44,6 +44,7 @@ Hardware Monitoring Kernel Drivers
asb100
asc7621
aspeed-pwm-tacho
+   aspeed2600-pwm-tachometer
bcm54140
bel-pfe
bt1-pvt
-- 
2.25.1

[PATCH v3 0/4] hwmon: aspeed2600-pwm-tacho: Add driver support

[Troy Lee]

Aspeed AST2600 is a server management SoC which has 16 PWM channels and
16 fan tacho channel.

This series of patch provides AST2600 PWM/Fan tacho support in hwmon
class.

The driver provides a sysfs interface, and user can configure PWM duty
cycle and read current FAN speed in RPM.

Changes since v2:
 - declare local function as static function
 - fixed dt binding yamllint warnings/errors
 - rename dt property property name from pwm-freq to pwm-freq-hz

Changes since v1:
 - dt-binding rewrote with dt schema format
 - register hwmon driver with devm_hwmon_device_register_with_info()
 - moving default configurations to device tree

Troy Lee (4):
  dt-bindings: hwmon: Add Aspeed AST2600 PWM/Fan
  hwmon: Add Aspeed AST2600 support
  ARM: dts: aspeed: Add Aspeed AST2600 PWM/Fan node in devicetree
  hwmon: Support Aspeed AST2600 PWM/Fan tachometer

 .../hwmon/aspeed,ast2600-pwm-tachometer.yaml  | 131 +++
 .../hwmon/aspeed2600-pwm-tachometer.rst   |  27 +
 Documentation/hwmon/index.rst |   1 +
 arch/arm/boot/dts/aspeed-ast2600-evb.dts  | 152 
 arch/arm/boot/dts/aspeed-g6.dtsi  |  10 +
 drivers/hwmon/Kconfig |  10 +
 drivers/hwmon/Makefile|   1 +
 drivers/hwmon/aspeed2600-pwm-tacho.c  | 756 ++
 8 files changed, 1088 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml
 create mode 100644 Documentation/hwmon/aspeed2600-pwm-tachometer.rst
 create mode 100644 drivers/hwmon/aspeed2600-pwm-tacho.c


base-commit: 1d011777cdbe7ae38a854a0cbeb6bdfbf724cce0
-- 
2.25.1

Re: [PATCH v2 1/4] dt-bindings: hwmon: Add Aspeed AST2600 PWM/Fan

[Troy Lee]

Hi Rob,

Thanks for reviewing.

The 01/14/2021 22:13, Rob Herring wrote:
> On Wed, Jan 13, 2021 at 07:08:45AM +0000, Troy Lee wrote:
> > We add binding for supporting a new AST2600 PWM/Fan hwmon driver.
> > 
> > Changes since v1:
> > - dt binding with DT schema format
> > 
> > Signed-off-by: Troy Lee 
> > ---
> >  .../hwmon/aspeed,ast2600-pwm-tachometer.yaml  | 137 ++
> >  1 file changed, 137 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml
> >  
> > b/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml
> > new file mode 100644
> > index ..b84076a4a338
> > --- /dev/null
> > +++ 
> > b/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml
> > @@ -0,0 +1,137 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +
> > +$id: 
> > http://devicetree.org/schemas/hwmon/aspeed,ast2600-pwm-tachometer.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: ASPEED AST2600 PWM and Fan Tacho controller device driver
> > +
> > +maintainers:
> > +  - Ryan Chen 
> > +
> > +description: |
> > +  The ASPEED PWM controller can support upto 16 PWM outputs. The ASPEED 
> > Fan Tacho
> > +  controller can support upto 16 Fan tachometer inputs.
> > +  There can be upto 16 fans supported. Each fan can have one PWM output and
> > +  one Fan tach inputs.
> > +
> > +properties:
> > +  compatible:
> > +const: aspeed,ast2600-pwm-tachometer
> > +
> > +  "#address-cells":
> > +const: 1
> > +
> > +  "#size-cells":
> > +const: 0
> > +
> > +  "#cooling-cells":
> > +const: 2
> > +
> > +  reg:
> > +description:
> > +  Address and length of the register set for the device.
> 
> No need for generic descriptions. That's every 'reg'.
> 
> What you need is how many entries and what each one is if more than 1. 
> If only 1, then just 'maxItems: 1'
> 
> > +
> > +  clocks:
> > +description:
> > +  phandle to clock provider with the clock number in the second cell
> 
> Same here.
> 
> > +
> > +  resets:
> > +description:
> > +  phandle to reset controller with the reset number in the second cell
> 
> And here.
> 
> > +
> > +patternProperties:
> > +  "@[0-9]+$":
> 
> If every node is a fan and there are up to 16:
> 
> ^fan@[0-9a-f]$
> 
I will update these in v3 patch set.

> > +type: object
> > +description:
> > +  Under fan subnode there can upto 16 child nodes, with each child node
> > +  representing a fan. There are 16 fans each fan can have one PWM port 
> > and one
> > +  Fan tach inputs.
> > +  For PWM port can be configured cooling-levels to create cooling 
> > device.
> > +  Cooling device could be bound to a thermal zone for the thermal 
> > control.
> > +
> > +properties:
> > +  reg:
> > +minimum: 0
> > +maximum: 15
> > +description:
> > +  This property identify the PWM control channel of this fan.
> > +
> > +  fan-tach-ch:
> > +$ref: /schemas/types.yaml#/definitions/uint8
> > +minimum: 0
> > +maximum: 15
> > +description:
> > +  This property identify the fan tach input channel.
> > +
> > +  pulses-per-revolution:
> > +$ref: /schemas/types.yaml#/definitions/uint32
> > +default: 2
> > +minimum: 1
> > +description:
> > +  Specify tacho pulse per revolution of the fan.
> > +
> > +  cooling-levels:
> > +description:
> > +  PWM duty cycle values in a range from 0 to 255
> > +  which correspond to thermal cooling states.
> > +
> > +  aspeed,pwm-freq:
> > +$ref: /schemas/types.yaml#/definitions/uint32
> > +default: 25000
> > +minimum: 24
> > +maximum: 78
> > +description:
> > +  Specify the frequency of PWM.
> 
> Units? Use a unit suffix and then drop the $ref.
> 
I'll change it to pwm-freq-hz.

> > +
> > +  aspeed,inverse-pin:
> > + 

Re: [PATCH v2 1/4] dt-bindings: hwmon: Add Aspeed AST2600 PWM/Fan

[Troy Lee]

Hi Rob,
The 01/13/2021 23:45, Rob Herring wrote:
> On Wed, 13 Jan 2021 07:08:45 +0000, Troy Lee wrote:
> > We add binding for supporting a new AST2600 PWM/Fan hwmon driver.
> > 
> > Changes since v1:
> > - dt binding with DT schema format
> > 
> > Signed-off-by: Troy Lee 
> > ---
> >  .../hwmon/aspeed,ast2600-pwm-tachometer.yaml  | 137 ++
> >  1 file changed, 137 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml
> > 
> 
> My bot found errors running 'make dt_binding_check' on your patch:
> 
> yamllint warnings/errors:
> ./Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml:108:2:
>  [warning] wrong indentation: expected 2 but found 1 (indentation)
> 
> dtschema/dtc warnings/errors:
> 
> See https://patchwork.ozlabs.org/patch/1425628
> 
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit.
> 

After install yamllint and ran 'make dt_binding_check' again, I can see
the same issue. I'll fix it in v3 patch set.

Thanks,
Troy Lee

[PATCH v2 2/4] hwmon: Add Aspeed AST2600 support

[Troy Lee]

Updating index.rst and adding aspeed2600-pwm-tachometer.rst to address
the driver.

Changes since v1:
- rename to aspeed2600-pwm-tachometer.rst
- add license identifier

Signed-off-by: Troy Lee 
---
 .../hwmon/aspeed2600-pwm-tachometer.rst   | 27 +++
 Documentation/hwmon/index.rst |  1 +
 2 files changed, 28 insertions(+)
 create mode 100644 Documentation/hwmon/aspeed2600-pwm-tachometer.rst

diff --git a/Documentation/hwmon/aspeed2600-pwm-tachometer.rst 
b/Documentation/hwmon/aspeed2600-pwm-tachometer.rst
new file mode 100644
index ..cf0d31a19597
--- /dev/null
+++ b/Documentation/hwmon/aspeed2600-pwm-tachometer.rst
@@ -0,0 +1,27 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+===
+Kernel driver aspeed2600-pwm-tachometer
+===
+
+Supported chips:
+   ASPEED AST2600
+
+Authors:
+   Ryan Chen 
+
+Description:
+
+This driver implements support for ASPEED AST2600 PWM and Fan Tacho
+controller. The PWM controller supports upto 16 PWM outputs. The Fan tacho
+controller supports up to 16 tachometer inputs.
+
+The driver provides the following sensor accesses in sysfs:
+
+=== === =
+fanX_input ro  provide current fan rotation value in RPM as reported
+   by the fan to the device.
+
+pwmX   rw  get or set PWM fan control value. This is an integer
+   value between 0(off) and 255(full speed).
+=== === =
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index fcb870ce6286..02020c282549 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -44,6 +44,7 @@ Hardware Monitoring Kernel Drivers
asb100
asc7621
aspeed-pwm-tacho
+   aspeed2600-pwm-tachometer
bcm54140
bel-pfe
bt1-pvt
-- 
2.25.1

[PATCH v2 1/4] dt-bindings: hwmon: Add Aspeed AST2600 PWM/Fan

[Troy Lee]

We add binding for supporting a new AST2600 PWM/Fan hwmon driver.

Changes since v1:
- dt binding with DT schema format

Signed-off-by: Troy Lee 
---
 .../hwmon/aspeed,ast2600-pwm-tachometer.yaml  | 137 ++
 1 file changed, 137 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml

diff --git 
a/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml 
b/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml
new file mode 100644
index ..b84076a4a338
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/hwmon/aspeed,ast2600-pwm-tachometer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED AST2600 PWM and Fan Tacho controller device driver
+
+maintainers:
+  - Ryan Chen 
+
+description: |
+  The ASPEED PWM controller can support upto 16 PWM outputs. The ASPEED Fan 
Tacho
+  controller can support upto 16 Fan tachometer inputs.
+  There can be upto 16 fans supported. Each fan can have one PWM output and
+  one Fan tach inputs.
+
+properties:
+  compatible:
+const: aspeed,ast2600-pwm-tachometer
+
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 0
+
+  "#cooling-cells":
+const: 2
+
+  reg:
+description:
+  Address and length of the register set for the device.
+
+  clocks:
+description:
+  phandle to clock provider with the clock number in the second cell
+
+  resets:
+description:
+  phandle to reset controller with the reset number in the second cell
+
+patternProperties:
+  "@[0-9]+$":
+type: object
+description:
+  Under fan subnode there can upto 16 child nodes, with each child node
+  representing a fan. There are 16 fans each fan can have one PWM port and 
one
+  Fan tach inputs.
+  For PWM port can be configured cooling-levels to create cooling device.
+  Cooling device could be bound to a thermal zone for the thermal control.
+
+properties:
+  reg:
+minimum: 0
+maximum: 15
+description:
+  This property identify the PWM control channel of this fan.
+
+  fan-tach-ch:
+$ref: /schemas/types.yaml#/definitions/uint8
+minimum: 0
+maximum: 15
+description:
+  This property identify the fan tach input channel.
+
+  pulses-per-revolution:
+$ref: /schemas/types.yaml#/definitions/uint32
+default: 2
+minimum: 1
+description:
+  Specify tacho pulse per revolution of the fan.
+
+  cooling-levels:
+description:
+  PWM duty cycle values in a range from 0 to 255
+  which correspond to thermal cooling states.
+
+  aspeed,pwm-freq:
+$ref: /schemas/types.yaml#/definitions/uint32
+default: 25000
+minimum: 24
+maximum: 78
+description:
+  Specify the frequency of PWM.
+
+  aspeed,inverse-pin:
+type: boolean
+description:
+  Inverse PWM output signal.
+
+  aspeed,falling-point:
+$ref: /schemas/types.yaml#/definitions/uint8
+default: 10
+minimum: 0
+maximum: 255
+description:
+  Initialize the pulse width.
+
+required:
+  - fan-tach-ch
+  - reg
+
+additionalProperties: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+  - |
+pwm_tacho: pwm-tacho-controller@1e61 {
+compatible = "aspeed,ast2600-pwm-tachometer";
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0x1e61 0x100>;
+
+fan@1 {
+reg = <0x00>;
+aspeed,pwm-freq = <25000>;
+cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+fan-tach-ch = /bits/ 8 <0x00>;
+pulses-per-revolution = <2>;
+};
+
+fan@2 {
+reg = <0x01>;
+aspeed,pwm-freq = <25000>;
+cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+fan-tach-ch = /bits/ 8 <0x01>;
+pulses-per-revolution = <2>;
+};
+};
+...
-- 
2.25.1

[PATCH v2 3/4] ARM: dts: aspeed: Add Aspeed AST2600 PWM/Fan node in devicetree

[Troy Lee]

Create a common node in aspeed-g6.dtsi and add fan nodes for 
aspeed-ast2600-evb.dts file.

Changes since v1:
- rename properties name in child node

Signed-off-by: Troy Lee 
---
 arch/arm/boot/dts/aspeed-ast2600-evb.dts | 152 +++
 arch/arm/boot/dts/aspeed-g6.dtsi |  10 ++
 2 files changed, 162 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts 
b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index 89be13197780..d94e70b957fb 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -23,6 +23,158 @@ memory@8000 {
};
 };
 
+&pwm_tacho {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_tach0_default
+   &pinctrl_pwm1_default &pinctrl_tach1_default
+   &pinctrl_pwm2_default &pinctrl_tach2_default
+   &pinctrl_pwm3_default &pinctrl_tach3_default
+   &pinctrl_pwm4_default &pinctrl_tach4_default
+   &pinctrl_pwm5_default &pinctrl_tach5_default
+   &pinctrl_pwm6_default &pinctrl_tach6_default
+   &pinctrl_pwm7_default &pinctrl_tach7_default
+   &pinctrl_pwm8g1_default &pinctrl_tach8_default
+   &pinctrl_pwm9g1_default &pinctrl_tach9_default
+   &pinctrl_pwm10g1_default &pinctrl_tach10_default
+   &pinctrl_pwm11g1_default &pinctrl_tach11_default
+   &pinctrl_pwm12g1_default &pinctrl_tach12_default
+   &pinctrl_pwm13g1_default &pinctrl_tach13_default
+   &pinctrl_pwm14g1_default &pinctrl_tach14_default
+   &pinctrl_pwm15g1_default &pinctrl_tach15_default>;
+
+   fan@1 {
+   reg = <0x00>;
+   aspeed,pwm-freq = <25000>;
+   aspeed,falling-point = /bits/ 8 <100>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x00>;
+   aspeed,tacho-div = <3>;
+   pulses-per-revolution = <1>;
+   };
+
+   fan@2 {
+   reg = <0x01>;
+   aspeed,pwm-freq = <25000>;
+   aspeed,falling-point = /bits/ 8 <100>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x01>;
+   pulses-per-revolution = <1>;
+   };
+
+   fan@3 {
+   reg = <0x02>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x02>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@4 {
+   reg = <0x03>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x03>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@5 {
+   reg = <0x04>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x04>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@6 {
+   reg = <0x05>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x05>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@7 {
+   reg = <0x06>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x06>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@8 {
+   reg = <0x07>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x07>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@9 {
+   reg = <0x08>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-ch = /bits/ 8 <0x08>;
+   pulses-per-revolution = <2>;
+   };
+
+   fan@10 {
+   reg = <0x09>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   fan-tach-

[PATCH v2 4/4] hwmon: Support Aspeed AST2600 PWM/Fan tachometer

[Troy Lee]

Add Aspeed AST2600 PWM/Fan tacho driver. AST2600 has 16 PWM channel and
16 FAN tacho channel.

Changes since v1:
- fixed review comments
- fixed double-looped calculation of div_h and div_l
- moving configuration to device tree
- register hwmon driver with devm_hwmon_device_register_with_info()

Signed-off-by: Troy Lee 
---
 drivers/hwmon/Kconfig|  10 +
 drivers/hwmon/Makefile   |   1 +
 drivers/hwmon/aspeed2600-pwm-tacho.c | 756 +++
 3 files changed, 767 insertions(+)
 create mode 100644 drivers/hwmon/aspeed2600-pwm-tacho.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 1ecf697d8d99..98f89f703161 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -400,6 +400,16 @@ config SENSORS_ASPEED
  This driver can also be built as a module. If so, the module
  will be called aspeed_pwm_tacho.
 
+config SENSORS_ASPEED2600_PWM_TACHO
+   tristate "ASPEED AST2600 PWM and Fan Tachometer"
+   depends on THERMAL || THERMAL=n
+   help
+ This driver provides support for ASPEED AST2600 PWM
+ and Fan Tacho controllers.
+
+ This driver can also be built as a module. If so, the module
+ will be called aspeed2600-pwm-tacho.
+
 config SENSORS_ATXP1
tristate "Attansic ATXP1 VID controller"
depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 09a86c5e1d29..1a415d493ffc 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_SENSORS_ARM_SCPI)+= scpi-hwmon.o
 obj-$(CONFIG_SENSORS_AS370)+= as370-hwmon.o
 obj-$(CONFIG_SENSORS_ASC7621)  += asc7621.o
 obj-$(CONFIG_SENSORS_ASPEED)   += aspeed-pwm-tacho.o
+obj-$(CONFIG_SENSORS_ASPEED2600_PWM_TACHO) += aspeed2600-pwm-tacho.o
 obj-$(CONFIG_SENSORS_ATXP1)+= atxp1.o
 obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o
 obj-$(CONFIG_SENSORS_BT1_PVT)  += bt1-pvt.o
diff --git a/drivers/hwmon/aspeed2600-pwm-tacho.c 
b/drivers/hwmon/aspeed2600-pwm-tacho.c
new file mode 100644
index ..150cf65243ee
--- /dev/null
+++ b/drivers/hwmon/aspeed2600-pwm-tacho.c
@@ -0,0 +1,756 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or later as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+/**
+ * PWM HW register offset define
+ */
+/* PWM Control Register */
+#define ASPEED_PWM_CTRL_CH(ch) (((ch) * 0x10) + 0x00)
+/* PWM Duty Cycle Register */
+#define ASPEED_PWM_DUTY_CYCLE_CH(ch)   (((ch) * 0x10) + 0x04)
+/* TACH Control Register */
+#define ASPEED_TACHO_CTRL_CH(ch)   (((ch) * 0x10) + 0x08)
+/* TACH Status Register */
+#define ASPEED_TACHO_STS_CH(x) (((x) * 0x10) + 0x0C)
+
+/**
+ * PWM register Bit field
+ */
+/*PWM_CTRL */
+#define PWM_LOAD_SEL_AS_WDT_BIT(19)/* load selection as 
WDT */
+#define PWM_DUTY_LOAD_AS_WDT_ENBIT(18) /* enable PWM duty load 
as WDT */
+#define PWM_DUTY_SYNC_DIS  BIT(17) /* disable PWM duty sync */
+#define PWM_CLK_ENABLE BIT(16) /* enable PWM clock */
+#define PWM_LEVEL_OUTPUT   BIT(15) /* output PWM level */
+#define PWM_INVERSEBIT(14) /* inverse PWM pin */
+#define PWM_OPEN_DRAIN_EN  BIT(13) /* enable open-drain */
+#define PWM_PIN_EN BIT(12) /* enable PWM pin */
+#define PWM_CLK_DIV_H_MASK (0xf << 8) /* PWM clock division H bit 
[3:0] */
+#define PWM_CLK_DIV_L_MASK (0xff)  /* PWM clock division H bit 
[3:0] */
+/* [19] */
+#define LOAD_SEL_FALLING 0
+#define LOAD_SEL_RIGING  1
+
+/*PWM_DUTY_CYCLE */
+#define PWM_PERIOD_BIT (24)/* pwm period bit [7:0] 
*/
+#define PWM_PERIOD_BIT_MASK(0xff << 24)/* pwm period bit [7:0] 
*/
+#define PWM_RISING_FALLING_AS_WDT_BIT  (16)
+#define PWM_RISING_FALLING_AS_WDT_MASK (0xff << 16)/* rising/falling point 
bit [7:0] as WDT */
+#define PWM_RISING_FALLING_MASK(0x)
+#define PWM_FALLING_POINT_BIT  (8) /* pwm falling point 
bit [7:0] */
+#define PWM_RISING_POINT_BIT   (0) /* pwm rising point bit 
[7:0] */
+/* [31:24] */
+#define DEFAULT_PWM_PERIOD 0xff
+
+/*PWM_TACHO_CTRL */
+#define TACHO_IER  BIT(31) /* enable tacho 
in

[PATCH v2 0/4] hwmon: aspeed2600-pwm-tacho: Add driver support

[Troy Lee]

Aspeed AST2600 is a server management SoC which has 16 PWM channels and
16 fan tacho channel.

This series of patch provides AST2600 PWM/Fan tacho support in hwmon
class.

The driver provides a sysfs interface, and user can configure PWM duty
cycle and read current FAN speed in RPM.


Change since v1:
- dt-binding rewrote with dt schema format
- register hwmon driver with devm_hwmon_device_register_with_info()
- moving default configurations to device tree

*** BLURB HERE ***

Troy Lee (4):
  dt-bindings: hwmon: Add Aspeed AST2600 PWM/Fan
  hwmon: Add Aspeed AST2600 support
  ARM: dts: aspeed: Add Aspeed AST2600 PWM/Fan node in devicetree
  hwmon: Support Aspeed AST2600 PWM/Fan tachometer

 .../hwmon/aspeed,ast2600-pwm-tachometer.yaml  | 137 
 .../hwmon/aspeed2600-pwm-tachometer.rst   |  27 +
 Documentation/hwmon/index.rst |   1 +
 arch/arm/boot/dts/aspeed-ast2600-evb.dts  | 152 
 arch/arm/boot/dts/aspeed-g6.dtsi  |  10 +
 drivers/hwmon/Kconfig |  10 +
 drivers/hwmon/Makefile|   1 +
 drivers/hwmon/aspeed2600-pwm-tacho.c  | 756 ++
 8 files changed, 1094 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/hwmon/aspeed,ast2600-pwm-tachometer.yaml
 create mode 100644 Documentation/hwmon/aspeed2600-pwm-tachometer.rst
 create mode 100644 drivers/hwmon/aspeed2600-pwm-tacho.c

-- 
2.25.1

Re: [PATCH 4/4] hwmon: Support Aspeed AST2600 PWM/Fan tachometer

[Troy Lee]

The 12/11/2020 00:16, Guenter Roeck wrote:
> On Wed, Dec 09, 2020 at 03:59:20PM +0800, Troy Lee wrote:
> > Add Aspeed AST2600 PWM/Fan tacho driver. AST2600 has 16 PWM channel and
> > 16 FAN tacho channel.
> > 
> > Signed-off-by: Troy Lee 
> > ---
> >  drivers/hwmon/Kconfig|   10 +
> >  drivers/hwmon/Makefile   |1 +
> >  drivers/hwmon/aspeed2600-pwm-tacho.c | 1053 ++
> >  3 files changed, 1064 insertions(+)
> >  create mode 100644 drivers/hwmon/aspeed2600-pwm-tacho.c
> > 
> > diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
> > index 9aa89d7d4193..097c01430259 100644
> > --- a/drivers/hwmon/Kconfig
> > +++ b/drivers/hwmon/Kconfig
> > @@ -400,6 +400,16 @@ config SENSORS_ASPEED
> >   This driver can also be built as a module. If so, the module
> >   will be called aspeed_pwm_tacho.
> >  
> > +config SENSORS_ASPEED2600_PWM_TACHO
> > +tristate "ASPEED AST2600 PWM and Fan Tachometer"
> > +depends on THERMAL || THERMAL=n
> > +help
> > +  This driver provides support for ASPEED AST2600 PWM
> > +  and Fan Tacho controllers.
> > +
> > + This driver can also be built as a module. If so, the module
> > + will be called aspeed2600-pwm-tacho.
> > +
> >  config SENSORS_ATXP1
> > tristate "Attansic ATXP1 VID controller"
> > depends on I2C
> > diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
> > index ae41ee71a71b..10be45768d36 100644
> > --- a/drivers/hwmon/Makefile
> > +++ b/drivers/hwmon/Makefile
> > @@ -52,6 +52,7 @@ obj-$(CONFIG_SENSORS_ARM_SCPI)+= scpi-hwmon.o
> >  obj-$(CONFIG_SENSORS_AS370)+= as370-hwmon.o
> >  obj-$(CONFIG_SENSORS_ASC7621)  += asc7621.o
> >  obj-$(CONFIG_SENSORS_ASPEED)   += aspeed-pwm-tacho.o
> > +obj-$(CONFIG_SENSORS_ASPEED2600_PWM_TACHO)  += aspeed2600-pwm-tacho.o
> >  obj-$(CONFIG_SENSORS_ATXP1)+= atxp1.o
> >  obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o
> >  obj-$(CONFIG_SENSORS_BT1_PVT)  += bt1-pvt.o
> > diff --git a/drivers/hwmon/aspeed2600-pwm-tacho.c 
> > b/drivers/hwmon/aspeed2600-pwm-tacho.c
> > new file mode 100644
> > index ..083eb3b253ff
> > --- /dev/null
> > +++ b/drivers/hwmon/aspeed2600-pwm-tacho.c
> > @@ -0,0 +1,1053 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +/*
> > + * Copyright (C) ASPEED Technology Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 or later 
> > as
> > + * published by the Free Software Foundation.
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +/**
> > + * PWM HW register offset define
> > + */
> > +//PWM Control Register
> 
> Please no C++ comments, and please use standard multi-line comments.
> 
Understood.

> > +#define ASPEED_PWM_CTRL_CH(ch) ((ch * 0x10) + 0x00)
> > +//PWM Duty Cycle Register
> > +#define ASPEED_PWM_DUTY_CYCLE_CH(ch)   ((ch * 0x10) + 0x04)
> > +//TACH Control Register
> > +#define ASPEED_TACHO_CTRL_CH(ch)   ((ch * 0x10) + 0x08)
> 
> (ch)
> 
> > +//TACH Status Register
> > +#define ASPEED_TACHO_STS_CH(x) ((x * 0x10) + 0x0C)
> 
> (x)
> 
Good catch.

> > +/**
> > + * PWM register Bit field
> > + */
> > +/*PWM_CTRL */
> > +#define  PWM_LOAD_SEL_AS_WDT_BIT   (19)//load selection as WDT
> > +#define  PWM_DUTY_LOAD_AS_WDT_EN   BIT(18) //enable PWM duty load as WDT
> > +#define  PWM_DUTY_SYNC_DIS BIT(17) //disable PWM duty sync
> > +#define PWM_CLK_ENABLE BIT(16) //enable PWM clock
> > +#define  PWM_LEVEL_OUTPUT  BIT(15) //output PWM level
> > +#define  PWM_INVERSE   BIT(14) //inverse PWM pin
> > +#define  PWM_OPEN_DRAIN_EN BIT(13) //enable open-drain
> > +#define  PWM_PIN_ENBIT(12) //enable PWM pin
> &

Re: [PATCH 1/4] dt-bindings: hwmon: Add Aspeed AST2600 PWM/Fan

[Troy Lee]

The 12/11/2020 11:26, Rob Herring wrote:
> On Wed, Dec 09, 2020 at 03:59:17PM +0800, Troy Lee wrote:
> > For supporting a new AST2600 PWM/Fan hwmon driver, we add a new binding.
> > 
> > Signed-off-by: Troy Lee 
> > ---
> >  .../bindings/hwmon/aspeed2600-pwm-tacho.txt   | 69 +++
> 
> Bindings are in DT schema format now.
> 
I'll submit a new binding with DT schema.

> >  1 file changed, 69 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/hwmon/aspeed2600-pwm-tacho.txt
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/hwmon/aspeed2600-pwm-tacho.txt 
> > b/Documentation/devicetree/bindings/hwmon/aspeed2600-pwm-tacho.txt
> > new file mode 100644
> > index ..61b11914352f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/hwmon/aspeed2600-pwm-tacho.txt
> > @@ -0,0 +1,69 @@
> > +ASPEED AST2600 PWM and Fan Tacho controller device driver
> > +
> > +The ASPEED PWM controller can support upto 16 PWM outputs. The ASPEED Fan 
> > Tacho
> > +controller can support upto 16 Fan tachometer inputs.
> > +
> > +There can be upto 16 fans supported. Each fan can have one PWM output and
> > +one Fan tach inputs.
> > +
> > +Required properties for pwm-tacho node:
> > +- #address-cells : should be 1.
> > +
> > +- #size-cells : should be 0.
> > +
> > +- #cooling-cells: should be 2.
> > +
> > +- reg : address and length of the register set for the device.
> > +
> > +- pinctrl-names : a pinctrl state named "default" must be defined.
> > +
> > +- pinctrl-0 : phandle referencing pin configuration of the PWM ports.
> > +
> > +- compatible : should be "aspeed,ast2600-pwm-tachometer".
> > +
> > +- clocks : phandle to clock provider with the clock number in the second 
> > cell
> > +
> > +- resets : phandle to reset controller with the reset number in the second 
> > cell
> > +
> > +fan subnode format:
> > +===
> > +Under fan subnode there can upto 16 child nodes, with each child node
> > +representing a fan. There are 16 fans each fan can have one PWM port and 
> > one
> > +Fan tach inputs.
> > +For PWM port can be configured cooling-levels to create cooling device.
> > +Cooling device could be bound to a thermal zone for the thermal control.
> > +
> > +Required properties for each child node:
> > +- reg : should specify PWM source port.
> > +   integer value in the range 0x00 to 0x0f with 0x00 indicating PWM port 0
> > +   and 0x0f indicating PWM port F.
> > +
> > +- cooling-levels: PWM duty cycle values in a range from 0 to 255
> > +  which correspond to thermal cooling states.
> > +
> > +- aspeed,fan-tach-ch : should specify the Fan tach input channel.
> > +integer value in the range 0 through 15, with 0 indicating
> > +   Fan tach channel 0 and 15 indicating Fan tach channel 15.
> > +   Atleast one Fan tach input channel is required.
> 
> Already has 'fan-tach-ch' in npcm750-pwm-fan.txt.
> 
OK.

> > +
> > +- aspeed,target-pwm : Specify the frequency of PWM. The value range from 
> > 24 to
> > + 78. Default value will be set to 25000.
> > +
> > +- aspeed,pulse-pr : Specify tacho pulse per revolution of the fan. A 
> > general
> > +   parameter of pulse-pr is 2.
> 
> Already have 'pulses-per-revolution' property in pwm-fan.txt. Use that.
> 
OK.

> Really, all these should be in a common fan schema that you reference.
> 
Are you suggesting that I should also update these properties into
pwm-fan.txt with a separeated patch, perhaps?

> > +
> > +Examples:
> > +
> > +&pwm_tacho {
> > +   status = "okay";
> 
> Don't show status in examples.
> 
Understood, it will be removed in v2.

> > +   pinctrl-names = "default";
> > +   pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_tach0_default>;
> > +
> > +   fan@0 {
> > +   reg = <0x00>;
> > +   aspeed,target-pwm = <25000>;
> > +   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
> > +   aspeed,fan-tach-ch = /bits/ 8 <0x00>;
> > +   aspeed,pulse-pr = <2>;
> > +   };
> > +};
> > -- 
> > 2.17.1
> > 

[PATCH] gpio: aspeed: Lock GPIO pin used as IRQ

[Troy Lee]

GPIO pins can be used as IRQ indicators. When they do,
those pins should be flaged with locks to avoid kernel
warning message.

Signed-off-by: Chia-Wei, Wang 
Signed-off-by: Troy Lee 
---
 drivers/gpio/gpio-aspeed.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index b966f5e28ebf..f5b3e1d89fbf 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -651,6 +651,13 @@ static int aspeed_gpio_set_type(struct irq_data *d, 
unsigned int type)
aspeed_gpio_copro_release(gpio, offset);
spin_unlock_irqrestore(&gpio->lock, flags);
 
+   rc = gpiochip_lock_as_irq(&gpio->chip, d->hwirq);
+   if (rc) {
+   dev_err(gpio->chip.parent, "unable to lock GPIO %lu as IRQ\n",
+   d->hwirq);
+   return rc;
+   }
+
irq_set_handler_locked(d, handler);
 
return 0;
-- 
2.17.1

[PATCH 3/4] hwmon: Add Aspeed AST2600 support

[Troy Lee]

Updating index.rst and adding aspeed_pwm_tachometer.rst to address the
driver.

Signed-off-by: Troy Lee 
---
 Documentation/hwmon/aspeed_pwm_tachometer.rst | 24 +++
 Documentation/hwmon/index.rst |  1 +
 2 files changed, 25 insertions(+)
 create mode 100644 Documentation/hwmon/aspeed_pwm_tachometer.rst

diff --git a/Documentation/hwmon/aspeed_pwm_tachometer.rst 
b/Documentation/hwmon/aspeed_pwm_tachometer.rst
new file mode 100644
index ..301448002e6e
--- /dev/null
+++ b/Documentation/hwmon/aspeed_pwm_tachometer.rst
@@ -0,0 +1,24 @@
+Kernel driver aspeed_pwm_tachometer
+===
+
+Supported chips:
+   ASPEED AST2600
+
+Authors:
+   Ryan Chen 
+
+Description:
+
+This driver implements support for ASPEED AST2600 PWM and Fan Tacho
+controller. The PWM controller supports upto 16 PWM outputs. The Fan tacho
+controller supports up to 16 tachometer inputs.
+
+The driver provides the following sensor accesses in sysfs:
+
+=== === =
+fanX_input ro  provide current fan rotation value in RPM as reported
+   by the fan to the device.
+
+pwmX   rw  get or set PWM fan control value. This is an integer
+   value between 0(off) and 255(full speed).
+=== === =
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index 89e1a824021f..26d277c1d211 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -43,6 +43,7 @@ Hardware Monitoring Kernel Drivers
asb100
asc7621
aspeed-pwm-tacho
+   aspeed_pwm_tachometer
bcm54140
bel-pfe
bt1-pvt
-- 
2.17.1

[PATCH 2/4] ARM: dts: aspeed: Add Aspeed AST2600 PWM/Fan node in devicetree

[Troy Lee]

Create a common node in aspeed-g6.dtsi and add fan nodes for ast2600-evb
dts file.

Signed-off-by: Troy Lee 
---
 arch/arm/boot/dts/aspeed-ast2600-evb.dts | 149 +++
 arch/arm/boot/dts/aspeed-g6.dtsi |  10 ++
 2 files changed, 159 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts 
b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index 89be13197780..51e00cf60749 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -23,6 +23,155 @@
};
 };
 
+&pwm_tacho {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_tach0_default
+   &pinctrl_pwm1_default &pinctrl_tach1_default
+   &pinctrl_pwm2_default &pinctrl_tach2_default
+   &pinctrl_pwm3_default &pinctrl_tach3_default
+   &pinctrl_pwm4_default &pinctrl_tach4_default
+   &pinctrl_pwm5_default &pinctrl_tach5_default
+   &pinctrl_pwm6_default &pinctrl_tach6_default
+   &pinctrl_pwm7_default &pinctrl_tach7_default
+   &pinctrl_pwm8g1_default &pinctrl_tach8_default
+   &pinctrl_pwm9g1_default &pinctrl_tach9_default
+   &pinctrl_pwm10g1_default &pinctrl_tach10_default
+   &pinctrl_pwm11g1_default &pinctrl_tach11_default
+   &pinctrl_pwm12g1_default &pinctrl_tach12_default
+   &pinctrl_pwm13g1_default &pinctrl_tach13_default
+   &pinctrl_pwm14g1_default &pinctrl_tach14_default
+   &pinctrl_pwm15g1_default &pinctrl_tach15_default>;
+
+   fan@0 {
+   reg = <0x00>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+   aspeed,pulse-pr = <2>;
+   };
+
+   fan@1 {
+   reg = <0x01>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+   aspeed,pulse-pr = <2>;
+   };
+
+   fan@2 {
+   reg = <0x02>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+   aspeed,pulse-pr = <2>;
+   };
+
+   fan@3 {
+   reg = <0x03>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+   aspeed,pulse-pr = <2>;
+   };
+
+   fan@4 {
+   reg = <0x04>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+   aspeed,pulse-pr = <2>;
+   };
+
+   fan@5 {
+   reg = <0x05>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+   aspeed,pulse-pr = <2>;
+   };
+
+   fan@6 {
+   reg = <0x06>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+   aspeed,pulse-pr = <2>;
+   };
+
+   fan@7 {
+   reg = <0x07>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+   aspeed,pulse-pr = <2>;
+   };
+
+   fan@8 {
+   reg = <0x08>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   aspeed,fan-tach-ch = /bits/ 8 <0x08>;
+   aspeed,pulse-pr = <2>;
+   };
+
+   fan@9 {
+   reg = <0x09>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   aspeed,fan-tach-ch = /bits/ 8 <0x09>;
+   aspeed,pulse-pr = <2>;
+   };
+
+   fan@10 {
+   reg = <0x0a>;
+   aspeed,pwm-freq = <25000>;
+   cooling-levels = /bits/ 8 <12

[PATCH 1/4] dt-bindings: hwmon: Add Aspeed AST2600 PWM/Fan

[Troy Lee]

For supporting a new AST2600 PWM/Fan hwmon driver, we add a new binding.

Signed-off-by: Troy Lee 
---
 .../bindings/hwmon/aspeed2600-pwm-tacho.txt   | 69 +++
 1 file changed, 69 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/hwmon/aspeed2600-pwm-tacho.txt

diff --git a/Documentation/devicetree/bindings/hwmon/aspeed2600-pwm-tacho.txt 
b/Documentation/devicetree/bindings/hwmon/aspeed2600-pwm-tacho.txt
new file mode 100644
index ..61b11914352f
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/aspeed2600-pwm-tacho.txt
@@ -0,0 +1,69 @@
+ASPEED AST2600 PWM and Fan Tacho controller device driver
+
+The ASPEED PWM controller can support upto 16 PWM outputs. The ASPEED Fan Tacho
+controller can support upto 16 Fan tachometer inputs.
+
+There can be upto 16 fans supported. Each fan can have one PWM output and
+one Fan tach inputs.
+
+Required properties for pwm-tacho node:
+- #address-cells : should be 1.
+
+- #size-cells : should be 0.
+
+- #cooling-cells: should be 2.
+
+- reg : address and length of the register set for the device.
+
+- pinctrl-names : a pinctrl state named "default" must be defined.
+
+- pinctrl-0 : phandle referencing pin configuration of the PWM ports.
+
+- compatible : should be "aspeed,ast2600-pwm-tachometer".
+
+- clocks : phandle to clock provider with the clock number in the second cell
+
+- resets : phandle to reset controller with the reset number in the second cell
+
+fan subnode format:
+===
+Under fan subnode there can upto 16 child nodes, with each child node
+representing a fan. There are 16 fans each fan can have one PWM port and one
+Fan tach inputs.
+For PWM port can be configured cooling-levels to create cooling device.
+Cooling device could be bound to a thermal zone for the thermal control.
+
+Required properties for each child node:
+- reg : should specify PWM source port.
+   integer value in the range 0x00 to 0x0f with 0x00 indicating PWM port 0
+   and 0x0f indicating PWM port F.
+
+- cooling-levels: PWM duty cycle values in a range from 0 to 255
+  which correspond to thermal cooling states.
+
+- aspeed,fan-tach-ch : should specify the Fan tach input channel.
+integer value in the range 0 through 15, with 0 indicating
+   Fan tach channel 0 and 15 indicating Fan tach channel 15.
+   Atleast one Fan tach input channel is required.
+
+- aspeed,target-pwm : Specify the frequency of PWM. The value range from 24 to
+ 78. Default value will be set to 25000.
+
+- aspeed,pulse-pr : Specify tacho pulse per revolution of the fan. A general
+   parameter of pulse-pr is 2.
+
+Examples:
+
+&pwm_tacho {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_tach0_default>;
+
+   fan@0 {
+   reg = <0x00>;
+   aspeed,target-pwm = <25000>;
+   cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
+   aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+   aspeed,pulse-pr = <2>;
+   };
+};
-- 
2.17.1

[PATCH 4/4] hwmon: Support Aspeed AST2600 PWM/Fan tachometer

[Troy Lee]

Add Aspeed AST2600 PWM/Fan tacho driver. AST2600 has 16 PWM channel and
16 FAN tacho channel.

Signed-off-by: Troy Lee 
---
 drivers/hwmon/Kconfig|   10 +
 drivers/hwmon/Makefile   |1 +
 drivers/hwmon/aspeed2600-pwm-tacho.c | 1053 ++
 3 files changed, 1064 insertions(+)
 create mode 100644 drivers/hwmon/aspeed2600-pwm-tacho.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 9aa89d7d4193..097c01430259 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -400,6 +400,16 @@ config SENSORS_ASPEED
  This driver can also be built as a module. If so, the module
  will be called aspeed_pwm_tacho.
 
+config SENSORS_ASPEED2600_PWM_TACHO
+tristate "ASPEED AST2600 PWM and Fan Tachometer"
+depends on THERMAL || THERMAL=n
+help
+  This driver provides support for ASPEED AST2600 PWM
+  and Fan Tacho controllers.
+
+ This driver can also be built as a module. If so, the module
+ will be called aspeed2600-pwm-tacho.
+
 config SENSORS_ATXP1
tristate "Attansic ATXP1 VID controller"
depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index ae41ee71a71b..10be45768d36 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_SENSORS_ARM_SCPI)+= scpi-hwmon.o
 obj-$(CONFIG_SENSORS_AS370)+= as370-hwmon.o
 obj-$(CONFIG_SENSORS_ASC7621)  += asc7621.o
 obj-$(CONFIG_SENSORS_ASPEED)   += aspeed-pwm-tacho.o
+obj-$(CONFIG_SENSORS_ASPEED2600_PWM_TACHO)  += aspeed2600-pwm-tacho.o
 obj-$(CONFIG_SENSORS_ATXP1)+= atxp1.o
 obj-$(CONFIG_SENSORS_AXI_FAN_CONTROL) += axi-fan-control.o
 obj-$(CONFIG_SENSORS_BT1_PVT)  += bt1-pvt.o
diff --git a/drivers/hwmon/aspeed2600-pwm-tacho.c 
b/drivers/hwmon/aspeed2600-pwm-tacho.c
new file mode 100644
index ..083eb3b253ff
--- /dev/null
+++ b/drivers/hwmon/aspeed2600-pwm-tacho.c
@@ -0,0 +1,1053 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or later as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+/**
+ * PWM HW register offset define
+ */
+//PWM Control Register
+#define ASPEED_PWM_CTRL_CH(ch) ((ch * 0x10) + 0x00)
+//PWM Duty Cycle Register
+#define ASPEED_PWM_DUTY_CYCLE_CH(ch)   ((ch * 0x10) + 0x04)
+//TACH Control Register
+#define ASPEED_TACHO_CTRL_CH(ch)   ((ch * 0x10) + 0x08)
+//TACH Status Register
+#define ASPEED_TACHO_STS_CH(x) ((x * 0x10) + 0x0C)
+/**
+ * PWM register Bit field
+ */
+/*PWM_CTRL */
+#define  PWM_LOAD_SEL_AS_WDT_BIT   (19)//load selection as WDT
+#define  PWM_DUTY_LOAD_AS_WDT_EN   BIT(18) //enable PWM duty load as WDT
+#define  PWM_DUTY_SYNC_DIS BIT(17) //disable PWM duty sync
+#define PWM_CLK_ENABLE BIT(16) //enable PWM clock
+#define  PWM_LEVEL_OUTPUT  BIT(15) //output PWM level
+#define  PWM_INVERSE   BIT(14) //inverse PWM pin
+#define  PWM_OPEN_DRAIN_EN BIT(13) //enable open-drain
+#define  PWM_PIN_ENBIT(12) //enable PWM pin
+#define  PWM_CLK_DIV_H_MASK(0xf << 8) //PWM clock division H bit 
[3:0]
+#define  PWM_CLK_DIV_L_MASK(0xff)  //PWM clock division H bit [3:0]
+/* [19] */
+#define LOAD_SEL_FALLING 0
+#define LOAD_SEL_RIGING  1
+
+/*PWM_DUTY_CYCLE */
+#define  PWM_PERIOD_BIT(24)//pwm 
period bit [7:0]
+#define  PWM_PERIOD_BIT_MASK   (0xff << 24)//pwm period 
bit [7:0]
+#define  PWM_RISING_FALLING_AS_WDT_BIT  (16)
+#define  PWM_RISING_FALLING_AS_WDT_MASK (0xff << 16)   //pwm rising/falling 
point bit [7:0] as WDT
+#define  PWM_RISING_FALLING_MASK   (0x)
+#define  PWM_FALLING_POINT_BIT (8) //pwm falling point bit 
[7:0]
+#define  PWM_RISING_POINT_BIT  (0) //pwm rising point bit 
[7:0]
+/* [31:24] */
+#define  DEFAULT_PWM_PERIOD 0xff
+
+/*PWM_TACHO_CTRL */
+#define  TACHO_IER BIT(31) 
//enable tacho interrupt
+#define  TACHO_INVERS_LIMITBIT(30) //inverse tacho 
limit comparison
+#define  TACHO_LOOPBACKBIT(29) //tacho 
loopback
+#define  TACHO_ENABLE 

[PATCH 0/4] hwmon: aspeed2600-pwm-tacho: Add driver support

[Troy Lee]

Aspeed AST2600 is a server management SoC which has 16 PWM channels and 
16 fan tacho channel.

This series of patch provides AST2600 PWM/Fan tacho support in hwmon class.

The driver provides a sysfs interface, and user can configure PWM duty cycle
and read current FAN speed in RPM.

Troy Lee (4):
  dt-bindings: hwmon: Add Aspeed AST2600 PWM/Fan
  ARM: dts: aspeed: Add Aspeed AST2600 PWM/Fan node in devicetree
  hwmon: Add Aspeed AST2600 support
  hwmon: Support Aspeed AST2600 PWM/Fan tachometer

 .../bindings/hwmon/aspeed2600-pwm-tacho.txt   |   69 ++
 Documentation/hwmon/aspeed_pwm_tachometer.rst |   24 +
 Documentation/hwmon/index.rst |1 +
 arch/arm/boot/dts/aspeed-ast2600-evb.dts  |  149 +++
 arch/arm/boot/dts/aspeed-g6.dtsi  |   10 +
 drivers/hwmon/Kconfig |   10 +
 drivers/hwmon/Makefile|1 +
 drivers/hwmon/aspeed2600-pwm-tacho.c  | 1053 +
 8 files changed, 1317 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/hwmon/aspeed2600-pwm-tacho.txt
 create mode 100644 Documentation/hwmon/aspeed_pwm_tachometer.rst
 create mode 100644 drivers/hwmon/aspeed2600-pwm-tacho.c

-- 
2.17.1

[PATCH v4 3/3] edac: Supporting AST2400 and AST2600 edac driver

[Troy Lee]

Adding AST2400 and AST2600 edac driver support.

Signed-off-by: Troy Lee 
---
 drivers/edac/Kconfig   | 6 +++---
 drivers/edac/aspeed_edac.c | 7 +--
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 7a47680d6f07..c410331e8ee8 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -515,10 +515,10 @@ config EDAC_QCOM
  health, you should probably say 'Y' here.
 
 config EDAC_ASPEED
-   tristate "Aspeed AST 2500 SoC"
-   depends on MACH_ASPEED_G5
+   tristate "Aspeed AST BMC SoC"
+   depends on ARCH_ASPEED
help
- Support for error detection and correction on the Aspeed AST 2500 SoC.
+ Support for error detection and correction on the Aspeed AST BMC SoC.
 
  First, ECC must be configured in the bootloader. Then, this driver
  will expose error counters via the EDAC kernel framework.
diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
index fde809efc520..a46da56d6d54 100644
--- a/drivers/edac/aspeed_edac.c
+++ b/drivers/edac/aspeed_edac.c
@@ -239,7 +239,7 @@ static int init_csrows(struct mem_ctl_info *mci)
int rc;
 
/* retrieve info about physical memory from device tree */
-   np = of_find_node_by_path("/memory");
+   np = of_find_node_by_name(NULL, "memory");
if (!np) {
dev_err(mci->pdev, "dt: missing /memory node\n");
return -ENODEV;
@@ -375,10 +375,13 @@ static int aspeed_remove(struct platform_device *pdev)
 
 
 static const struct of_device_id aspeed_of_match[] = {
+   { .compatible = "aspeed,ast2400-sdram-edac" },
{ .compatible = "aspeed,ast2500-sdram-edac" },
+   { .compatible = "aspeed,ast2600-sdram-edac" },
{},
 };
 
+MODULE_DEVICE_TABLE(of, aspeed_of_match);
 
 static struct platform_driver aspeed_driver = {
.driver = {
@@ -392,5 +395,5 @@ module_platform_driver(aspeed_driver);
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Stefan Schaeckeler ");
-MODULE_DESCRIPTION("Aspeed AST2500 EDAC driver");
+MODULE_DESCRIPTION("Aspeed BMC SoC EDAC driver");
 MODULE_VERSION("1.0");
-- 
2.17.1

[PATCH v4 2/3] ARM: dts: aspeed: Add AST2600 edac into common devicetree

[Troy Lee]

Adding Aspeed AST2600 edac node into common devicetree.

Signed-off-by: Troy Lee 
Reviewed-by: Joel Stanley 
---
 arch/arm/boot/dts/aspeed-g6.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index b58220a49cbd..74367ee96f20 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -69,6 +69,12 @@
always-on;
};
 
+   edac: sdram@1e6e {
+   compatible = "aspeed,ast2600-sdram-edac", "syscon";
+   reg = <0x1e6e 0x174>;
+   interrupts = ;
+   };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
-- 
2.17.1

[PATCH v4 1/3] dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support

[Troy Lee]

Adding Aspeed AST2400 and AST2600 binding for edac driver.

Signed-off-by: Troy Lee 
Acked-by: Joel Stanley 
---
 .../devicetree/bindings/edac/aspeed-sdram-edac.txt   | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt 
b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
index 6a0f3d90d682..8ca9e0a049d8 100644
--- a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
+++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
@@ -1,6 +1,6 @@
-Aspeed AST2500 SoC EDAC node
+Aspeed BMC SoC EDAC node
 
-The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC 
(error
+The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
 correction check).
 
 The memory controller supports SECDED (single bit error correction, double bit
@@ -11,7 +11,10 @@ Note, the bootloader must configure ECC mode in the memory 
controller.
 
 
 Required properties:
-- compatible: should be "aspeed,ast2500-sdram-edac"
+- compatible: should be one of
+   - "aspeed,ast2400-sdram-edac"
+   - "aspeed,ast2500-sdram-edac"
+   - "aspeed,ast2600-sdram-edac"
 - reg:sdram controller register set should be <0x1e6e 0x174>
 - interrupts: should be AVIC interrupt #0
 
-- 
2.17.1

RE: [PATCH v2 3/3] edac: Supporting AST2400 and AST2600 edac driver

[Troy Lee]

Hi Broislav and Andrew,

I removed these exported function and submitted v3 PATCH.

Thanks,
Troy Lee

> -Original Message-
> From: Borislav Petkov 
> Sent: Thursday, December 3, 2020 2:24 AM
> To: Andrew Jeffery 
> Cc: Troy Lee ; Joel Stanley ; open
> list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> ; Tony Luck ; Ryan Chen
> ; James Morse ;
> moderated list:ARM/ASPEED MACHINE SUPPORT
> ; open list ;
> Robert Richter ; leet...@gmail.com; Rob Herring
> ; Stefan M Schaeckeler ; Mauro
> Carvalho Chehab ; moderated list:ARM/ASPEED
> MACHINE SUPPORT ; open
> list:EDAC-CORE 
> Subject: Re: [PATCH v2 3/3] edac: Supporting AST2400 and AST2600 edac
> driver
> 
> On Thu, Dec 03, 2020 at 01:32:44AM +1030, Andrew Jeffery wrote:
> > On Wed, 2 Dec 2020, at 19:11, Troy Lee wrote:
> > > Hi Joel,
> > >
> > > Thanks for the suggestion, I'll fix the review and create an new
> > > patch against latest Linux branch. Those exported function will be
> > > referenced in other driver yet to be upstream, so should I move
> > > those exported functions out of this patch?
> > >
> >
> > Yes, let's leave the exports out of this patch, and add them in when
> > you send the patch that depends on them.
> 
> And when you do, almost all new exports are EXPORT_SYMBOL_GPL - not
> EXPORT_SYMBOL.
> 
> Also, I'd like to see how those exports are going to be used. An EDAC driver
> function exported to another driver sounds strange. We have only one other
> case like this in the EDAC tree:
> 
> drivers/edac/amd64_edac.c:554:EXPORT_SYMBOL_GPL(amd64_get_dram_hol
> e_info);
> 
> and even that is not really needed...
> 
> Thx.
> 
> --
> Regards/Gruss,
> Boris.
> 
> https://people.kernel.org/tglx/notes-about-netiquette

[PATCH v3 3/3] edac: Supporting AST2400 and AST2600 edac driver

[Troy Lee]

Adding AST2400 and AST2600 edac driver support.

Signed-off-by: Troy Lee 
---
Changes since v2:
- Remove cross dependencies export functions
- Update Kconfig depends on ARCH_ASPEED
- Patch create against latest Linux kernel mainline

---
 drivers/edac/Kconfig   |  6 +++---
 drivers/edac/aspeed_edac.c | 15 +--
 2 files changed, 8 insertions(+), 13 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 7a47680d6f07..c410331e8ee8 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -515,10 +515,10 @@ config EDAC_QCOM
  health, you should probably say 'Y' here.
 
 config EDAC_ASPEED
-   tristate "Aspeed AST 2500 SoC"
-   depends on MACH_ASPEED_G5
+   tristate "Aspeed AST BMC SoC"
+   depends on ARCH_ASPEED
help
- Support for error detection and correction on the Aspeed AST 2500 SoC.
+ Support for error detection and correction on the Aspeed AST BMC SoC.
 
  First, ECC must be configured in the bootloader. Then, this driver
  will expose error counters via the EDAC kernel framework.
diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
index fde809efc520..c9d1d8a8fcba 100644
--- a/drivers/edac/aspeed_edac.c
+++ b/drivers/edac/aspeed_edac.c
@@ -239,7 +239,7 @@ static int init_csrows(struct mem_ctl_info *mci)
int rc;
 
/* retrieve info about physical memory from device tree */
-   np = of_find_node_by_path("/memory");
+   np = of_find_node_by_name(NULL, "memory");
if (!np) {
dev_err(mci->pdev, "dt: missing /memory node\n");
return -ENODEV;
@@ -282,7 +282,6 @@ static int aspeed_probe(struct platform_device *pdev)
struct edac_mc_layer layers[2];
struct mem_ctl_info *mci;
void __iomem *regs;
-   u32 reg04;
int rc;
 
regs = devm_platform_ioremap_resource(pdev, 0);
@@ -294,13 +293,6 @@ static int aspeed_probe(struct platform_device *pdev)
if (IS_ERR(aspeed_regmap))
return PTR_ERR(aspeed_regmap);
 
-   /* bail out if ECC mode is not configured */
-   regmap_read(aspeed_regmap, ASPEED_MCR_CONF, ®04);
-   if (!(reg04 & ASPEED_MCR_CONF_ECC)) {
-   dev_err(&pdev->dev, "ECC mode is not configured in u-boot\n");
-   return -EPERM;
-   }
-
edac_op_state = EDAC_OPSTATE_INT;
 
/* allocate & init EDAC MC data structure */
@@ -375,10 +367,13 @@ static int aspeed_remove(struct platform_device *pdev)
 
 
 static const struct of_device_id aspeed_of_match[] = {
+   { .compatible = "aspeed,ast2400-sdram-edac" },
{ .compatible = "aspeed,ast2500-sdram-edac" },
+   { .compatible = "aspeed,ast2600-sdram-edac" },
{},
 };
 
+MODULE_DEVICE_TABLE(of, aspeed_of_match);
 
 static struct platform_driver aspeed_driver = {
.driver = {
@@ -392,5 +387,5 @@ module_platform_driver(aspeed_driver);
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Stefan Schaeckeler ");
-MODULE_DESCRIPTION("Aspeed AST2500 EDAC driver");
+MODULE_DESCRIPTION("Aspeed BMC SoC EDAC driver");
 MODULE_VERSION("1.0");
-- 
2.17.1

[PATCH v3 1/3] dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support

[Troy Lee]

Adding Aspeed AST2400 and AST2600 binding for edac driver.

Signed-off-by: Troy Lee 
---
 .../devicetree/bindings/edac/aspeed-sdram-edac.txt   | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt 
b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
index 6a0f3d90d682..8ca9e0a049d8 100644
--- a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
+++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
@@ -1,6 +1,6 @@
-Aspeed AST2500 SoC EDAC node
+Aspeed BMC SoC EDAC node
 
-The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC 
(error
+The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
 correction check).
 
 The memory controller supports SECDED (single bit error correction, double bit
@@ -11,7 +11,10 @@ Note, the bootloader must configure ECC mode in the memory 
controller.
 
 
 Required properties:
-- compatible: should be "aspeed,ast2500-sdram-edac"
+- compatible: should be one of
+   - "aspeed,ast2400-sdram-edac"
+   - "aspeed,ast2500-sdram-edac"
+   - "aspeed,ast2600-sdram-edac"
 - reg:sdram controller register set should be <0x1e6e 0x174>
 - interrupts: should be AVIC interrupt #0
 
-- 
2.17.1

[PATCH v3 2/3] ARM: dts: aspeed: Add AST2600 edac into common devicetree

[Troy Lee]

Adding Aspeed AST2600 edac node into common devicetree.

Signed-off-by: Troy Lee 
---
 arch/arm/boot/dts/aspeed-g6.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index b58220a49cbd..74367ee96f20 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -69,6 +69,12 @@
always-on;
};
 
+   edac: sdram@1e6e {
+   compatible = "aspeed,ast2600-sdram-edac", "syscon";
+   reg = <0x1e6e 0x174>;
+   interrupts = ;
+   };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
-- 
2.17.1

RE: [PATCH v2 3/3] edac: Supporting AST2400 and AST2600 edac driver

[Troy Lee]

Hi Joel,

Thanks for the suggestion, I'll fix the review and create an new patch against 
latest Linux branch. Those exported function will be referenced in other driver 
yet 
to be upstream, so should I move those exported functions out of this patch?

Thanks,
Troy Lee

> -Original Message-
> From: Joel Stanley 
> Sent: Wednesday, December 2, 2020 3:02 PM
> To: Troy Lee 
> Cc: Stefan Schaeckeler ; Rob Herring
> ; Andrew Jeffery ; Borislav Petkov
> ; Mauro Carvalho Chehab ; Tony Luck
> ; James Morse ; Robert
> Richter ; open list:OPEN FIRMWARE AND FLATTENED
> DEVICE TREE BINDINGS ; moderated
> list:ARM/ASPEED MACHINE SUPPORT ;
> moderated list:ARM/ASPEED MACHINE SUPPORT
> ; open list ;
> open list:EDAC-CORE ; leet...@gmail.com; Ryan
> Chen 
> Subject: Re: [PATCH v2 3/3] edac: Supporting AST2400 and AST2600 edac
> driver
> 
> On Wed, 2 Dec 2020 at 06:37, Troy Lee  wrote:
> >
> > Adding AST2400 and AST2600 edac driver support.
> >
> > Signed-off-by: Troy Lee 
> > ---
> > Change since v1:
> > 1. Removing SoC specific code
> > 2. Changing numerical representation of memory sizing
> > ---
> >  drivers/edac/Kconfig   |   6 +--
> >  drivers/edac/aspeed_edac.c | 103
> > +
> >  2 files changed, 85 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index
> > fc30f2ef9782..8ea70746d0bf 100644
> > --- a/drivers/edac/Kconfig
> > +++ b/drivers/edac/Kconfig
> > @@ -508,10 +508,10 @@ config EDAC_QCOM
> >   health, you should probably say 'Y' here.
> >
> >  config EDAC_ASPEED
> > -   tristate "Aspeed AST 2500 SoC"
> > -   depends on MACH_ASPEED_G5
> > +   tristate "Aspeed AST BMC SoC"
> > +   depends on (MACH_ASPEED_G4 || MACH_ASPEED_G5 ||
> > + MACH_ASPEED_G6)
> 
> Change this to ARCH_ASPEED.
> 
Fixed.

> > help
> > - Support for error detection and correction on the Aspeed AST
> 2500 SoC.
> > + Support for error detection and correction on the Aspeed AST
> BMC SoC.
> >
> >   First, ECC must be configured in the bootloader. Then, this
> driver
> >   will expose error counters via the EDAC kernel framework.
> > diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
> > index fbec28dc661d..b8c8d6a05f91 100644
> > --- a/drivers/edac/aspeed_edac.c
> > +++ b/drivers/edac/aspeed_edac.c
> > @@ -14,12 +14,11 @@
> >  #include 
> >  #include "edac_module.h"
> >
> > -
> 
> These whitespace cleanups are ok, but can probably go in a different patch so
> they aren't mixed up with the functional changes.
> 
Okay, that make sense.

> >  #define DRV_NAME "aspeed-edac"
> >
> > -
> >  #define ASPEED_MCR_PROT0x00 /* protection key register */
> >  #define ASPEED_MCR_CONF0x04 /* configuration register */
> > +#define ASPEED_MCR_REQ 0x08 /* Graphics Memory Protection
> register */
> >  #define ASPEED_MCR_INTR_CTRL   0x50 /* interrupt control/status
> register */
> >  #define ASPEED_MCR_ADDR_UNREC  0x58 /* address of first
> un-recoverable error */
> >  #define ASPEED_MCR_ADDR_REC0x5c /* address of last recoverable
> error */
> > @@ -29,15 +28,17 @@
> >  #define ASPEED_MCR_PROT_PASSWD 0xfc600309
> >  #define ASPEED_MCR_CONF_DRAM_TYPE   BIT(4)
> >  #define ASPEED_MCR_CONF_ECC BIT(7)
> > +#define ASPEED_MCR_CONF_DRAM_CTRL_TYPE
> > +(BIT(28)|BIT(29)|BIT(30)|BIT(31))
> 
> We can use GENMASK here:
> 
>  GENMASK(31, 28)
> 
> >  #define ASPEED_MCR_INTR_CTRL_CLEAR BIT(31)
> >  #define ASPEED_MCR_INTR_CTRL_CNT_REC   GENMASK(23, 16)
> >  #define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)
> #define
> > ASPEED_MCR_INTR_CTRL_ENABLE  (BIT(0) | BIT(1))
> >
> > +#define ASPEED_MCR_CONF_DRAM_CTRL_TYPE_AST2500  0x01 #define
> > +ASPEED_MCR_CONF_DRAM_CTRL_TYPE_AST2600  0x03
> >
> >  static struct regmap *aspeed_regmap;
> >
> > -
> >  static int regmap_reg_write(void *context, unsigned int reg, unsigned
> > int val)  {
> > void __iomem *regs = (void __iomem *)context; @@ -53,7 +54,6
> > @@ static int regmap_reg_write(void *context, unsigned int reg, unsigned
> int val)
> > return 0;
> >  }
> >
> > -
> >  static int regmap_reg_read(void *context, unsigned int reg, unsigned
> > int *val)  {
> > void __iomem *regs = (void __iomem *)context; @

[PATCH v2 1/3] dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support

[Troy Lee]

Adding Aspeed AST2400 and AST2600 binding for edac driver.

Signed-off-by: Troy Lee 
---
 .../devicetree/bindings/edac/aspeed-sdram-edac.txt   | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt 
b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
index 6a0f3d90d682..8ca9e0a049d8 100644
--- a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
+++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
@@ -1,6 +1,6 @@
-Aspeed AST2500 SoC EDAC node
+Aspeed BMC SoC EDAC node
 
-The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC 
(error
+The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
 correction check).
 
 The memory controller supports SECDED (single bit error correction, double bit
@@ -11,7 +11,10 @@ Note, the bootloader must configure ECC mode in the memory 
controller.
 
 
 Required properties:
-- compatible: should be "aspeed,ast2500-sdram-edac"
+- compatible: should be one of
+   - "aspeed,ast2400-sdram-edac"
+   - "aspeed,ast2500-sdram-edac"
+   - "aspeed,ast2600-sdram-edac"
 - reg:sdram controller register set should be <0x1e6e 0x174>
 - interrupts: should be AVIC interrupt #0
 
-- 
2.17.1

[PATCH v2 3/3] edac: Supporting AST2400 and AST2600 edac driver

[Troy Lee]

Adding AST2400 and AST2600 edac driver support.

Signed-off-by: Troy Lee 
---
Change since v1:
1. Removing SoC specific code
2. Changing numerical representation of memory sizing
---
 drivers/edac/Kconfig   |   6 +--
 drivers/edac/aspeed_edac.c | 103 +
 2 files changed, 85 insertions(+), 24 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index fc30f2ef9782..8ea70746d0bf 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -508,10 +508,10 @@ config EDAC_QCOM
  health, you should probably say 'Y' here.
 
 config EDAC_ASPEED
-   tristate "Aspeed AST 2500 SoC"
-   depends on MACH_ASPEED_G5
+   tristate "Aspeed AST BMC SoC"
+   depends on (MACH_ASPEED_G4 || MACH_ASPEED_G5 || MACH_ASPEED_G6)
help
- Support for error detection and correction on the Aspeed AST 2500 SoC.
+ Support for error detection and correction on the Aspeed AST BMC SoC.
 
  First, ECC must be configured in the bootloader. Then, this driver
  will expose error counters via the EDAC kernel framework.
diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
index fbec28dc661d..b8c8d6a05f91 100644
--- a/drivers/edac/aspeed_edac.c
+++ b/drivers/edac/aspeed_edac.c
@@ -14,12 +14,11 @@
 #include 
 #include "edac_module.h"
 
-
 #define DRV_NAME "aspeed-edac"
 
-
 #define ASPEED_MCR_PROT0x00 /* protection key register */
 #define ASPEED_MCR_CONF0x04 /* configuration register */
+#define ASPEED_MCR_REQ 0x08 /* Graphics Memory Protection register */
 #define ASPEED_MCR_INTR_CTRL   0x50 /* interrupt control/status register */
 #define ASPEED_MCR_ADDR_UNREC  0x58 /* address of first un-recoverable error */
 #define ASPEED_MCR_ADDR_REC0x5c /* address of last recoverable error */
@@ -29,15 +28,17 @@
 #define ASPEED_MCR_PROT_PASSWD 0xfc600309
 #define ASPEED_MCR_CONF_DRAM_TYPE   BIT(4)
 #define ASPEED_MCR_CONF_ECC BIT(7)
+#define ASPEED_MCR_CONF_DRAM_CTRL_TYPE (BIT(28)|BIT(29)|BIT(30)|BIT(31))
 #define ASPEED_MCR_INTR_CTRL_CLEAR BIT(31)
 #define ASPEED_MCR_INTR_CTRL_CNT_REC   GENMASK(23, 16)
 #define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)
 #define ASPEED_MCR_INTR_CTRL_ENABLE  (BIT(0) | BIT(1))
 
+#define ASPEED_MCR_CONF_DRAM_CTRL_TYPE_AST2500  0x01
+#define ASPEED_MCR_CONF_DRAM_CTRL_TYPE_AST2600  0x03
 
 static struct regmap *aspeed_regmap;
 
-
 static int regmap_reg_write(void *context, unsigned int reg, unsigned int val)
 {
void __iomem *regs = (void __iomem *)context;
@@ -53,7 +54,6 @@ static int regmap_reg_write(void *context, unsigned int reg, 
unsigned int val)
return 0;
 }
 
-
 static int regmap_reg_read(void *context, unsigned int reg, unsigned int *val)
 {
void __iomem *regs = (void __iomem *)context;
@@ -63,6 +63,79 @@ static int regmap_reg_read(void *context, unsigned int reg, 
unsigned int *val)
return 0;
 }
 
+extern void aspeed_sdmc_disable_mem_protection(u8 req)
+{
+   u32 req_val = 0;
+
+   regmap_read(aspeed_regmap, ASPEED_MCR_REQ, &req_val);
+
+   req_val &= ~BIT(req);
+
+   regmap_write(aspeed_regmap, ASPEED_MCR_REQ, req_val);
+}
+EXPORT_SYMBOL(aspeed_sdmc_disable_mem_protection);
+
+static const u32 ast2400_dram_table[] = {
+   64 << 20,
+   128 << 20,
+   256 << 20,
+   512 << 20,
+};
+
+static const u32 ast2500_dram_table[] = {
+   128 << 20,
+   256 << 20,
+   512 << 20,
+   1024 << 20,
+};
+
+static const u32 ast2600_dram_table[] = {
+   256 << 20,
+   512 << 20,
+   1024 << 20,
+   2048 << 20,
+};
+
+extern u32 aspeed_get_dram_size(void)
+{
+   u32 reg04;
+   u32 size;
+   u8 type;
+
+   regmap_read(aspeed_regmap, ASPEED_MCR_CONF, ®04);
+
+   type = (reg04 & ASPEED_MCR_CONF_DRAM_CTRL_TYPE) >> 28;
+
+   if (type == ASPEED_MCR_CONF_DRAM_CTRL_TYPE_AST2600)
+   size = ast2600_dram_table[reg04 & 0x3];
+   else if (type == ASPEED_MCR_CONF_DRAM_CTRL_TYPE_AST2500)
+   size = ast2500_dram_table[reg04 & 0x3];
+   else
+   size = ast2400_dram_table[reg04 & 0x3];
+
+   return size;
+}
+EXPORT_SYMBOL(aspeed_get_dram_size);
+
+static const u32 aspeed_vga_table[] = {
+   8 << 20,
+   16 << 20,
+   32 << 20,
+   64 << 20,
+};
+
+extern u32 aspeed_get_vga_size(void)
+{
+   u32 reg04;
+   u32 size;
+
+   regmap_read(aspeed_regmap, ASPEED_MCR_CONF, ®04);
+
+   size = aspeed_vga_table[((reg04 & 0xC) >> 2)];
+   return size;
+}
+EXPORT_SYMBOL(aspeed_get_vga_size);
+
 static bool regmap_is_volatile(struct device *dev, unsigned int reg)
 {
switch (reg) {
@@ -227,7 +300,6 @@ static int config_irq(void *ctx, struct platform_device 

[PATCH v2 2/3] ARM: dts: aspeed: Add AST2600 edac into common devicetree

[Troy Lee]

Adding Aspeed AST2600 edac node into common devicetree.

Signed-off-by: Troy Lee 
---
 arch/arm/boot/dts/aspeed-g6.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 97ca743363d7..fb144515f397 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -69,6 +69,12 @@
always-on;
};
 
+   edac: sdram@1e6e {
+   compatible = "aspeed,ast2600-sdram-edac", "syscon";
+   reg = <0x1e6e 0x174>;
+   interrupts = ;
+   };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
-- 
2.17.1

RE: [PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver

[Troy Lee]

Hi Stefan,

The driver was ported from latest ASPEED BSP, so I only test with ECC-on/off 
from u-boot and check if driver runs correctly.

The test doc you provided is very nice and detailed, I'll try to reproduce the 
injection test in v2 patch.

Thanks,
Troy Lee

> -Original Message-
> From: Stefan Schaeckeler (sschaeck) 
> Sent: Monday, November 30, 2020 5:16 PM
> To: Troy Lee ; Rob Herring ;
> Joel Stanley ; Andrew Jeffery ; Borislav
> Petkov ; Mauro Carvalho Chehab ;
> Tony Luck ; James Morse ;
> Robert Richter ; open list:OPEN FIRMWARE AND
> FLATTENED DEVICE TREE BINDINGS ; moderated
> list:ARM/ASPEED MACHINE SUPPORT ;
> moderated list:ARM/ASPEED MACHINE SUPPORT
> ; open list ;
> open list:EDAC-CORE 
> Cc: leet...@gmail.com; Ryan Chen ; Stefan
> Schaeckeler 
> Subject: Re: [PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver
> 
> Hello Troy,
> 
> > Adding AST2400 and AST2600 edac driver support.
> >
> > Signed-off-by: Troy Lee 
> > ---
> > drivers/edac/Kconfig   |   6 +-
> > drivers/edac/aspeed_edac.c | 114 +
> > 2 files changed, 94 insertions(+), 26 deletions(-)
> 
> Uh, there are quite some non-trivial changes. I'll have a look over the coming
> weekend.
> 
> Testing an edac driver comes with challenges. Did you test your code? If so,
> how?
> 
> That's how I was testing my original edac 2500 driver
> http://students.engr.scu.edu/~sschaeck/misc/aspeed-edac.html
> 
>  Stefan

RE: [PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver

[Troy Lee]

Hi Andrew,

Great suggestion, responses inline below. We'll remove build-time SoC 
dependency driver code and submit an updated v2 patch.

Thanks,
Troy Lee

> -Original Message-
> From: Andrew Jeffery 
> Sent: Tuesday, December 1, 2020 9:12 AM
> To: Troy Lee ; Stefan M Schaeckeler
> ; Rob Herring ; Joel Stanley
> ; Borislav Petkov ; Mauro Carvalho Chehab
> ; Tony Luck ; James Morse
> ; Robert Richter ; open
> list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> ; moderated list:ARM/ASPEED MACHINE
> SUPPORT ; moderated
> list:ARM/ASPEED MACHINE SUPPORT ; open
> list ; open list:EDAC-CORE
> 
> Cc: leet...@gmail.com; Ryan Chen 
> Subject: Re: [PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver
> 
> Hi Troy,
> 
> I like the idea of expanding the driver's support to cover the other SoC
> generations, but not at the cost of making the build of the driver 
> SoC-specific.
> I've made some comments below in this regard.
> 
> On Mon, 30 Nov 2020, at 19:03, Troy Lee wrote:
> > Adding AST2400 and AST2600 edac driver support.
> >
> > Signed-off-by: Troy Lee 
> > ---
> >  drivers/edac/Kconfig   |   6 +-
> >  drivers/edac/aspeed_edac.c | 114
> > +
> >  2 files changed, 94 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index
> > fc30f2ef9782..8ea70746d0bf 100644
> > --- a/drivers/edac/Kconfig
> > +++ b/drivers/edac/Kconfig
> > @@ -508,10 +508,10 @@ config EDAC_QCOM
> >   health, you should probably say 'Y' here.
> >
> >  config EDAC_ASPEED
> > -   tristate "Aspeed AST 2500 SoC"
> > -   depends on MACH_ASPEED_G5
> > +   tristate "Aspeed AST BMC SoC"
> > +   depends on (MACH_ASPEED_G4 || MACH_ASPEED_G5 ||
> MACH_ASPEED_G6)
> > help
> > - Support for error detection and correction on the Aspeed AST 2500 SoC.
> > + Support for error detection and correction on the Aspeed AST BMC SoC.
> >
> >   First, ECC must be configured in the bootloader. Then, this driver
> >   will expose error counters via the EDAC kernel framework.
> > diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
> > index fbec28dc661d..03a3c12f6bf6 100644
> > --- a/drivers/edac/aspeed_edac.c
> > +++ b/drivers/edac/aspeed_edac.c
> > @@ -14,12 +14,11 @@
> >  #include 
> >  #include "edac_module.h"
> >
> > -
> >  #define DRV_NAME "aspeed-edac"
> >
> > -
> >  #define ASPEED_MCR_PROT0x00 /* protection key register */
> >  #define ASPEED_MCR_CONF0x04 /* configuration register */
> > +#define ASPEED_MCR_REQ 0x08 /* Graphics Memory Protection
> register */
> >  #define ASPEED_MCR_INTR_CTRL   0x50 /* interrupt control/status
> register */
> >  #define ASPEED_MCR_ADDR_UNREC  0x58 /* address of first
> un-recoverable error */
> >  #define ASPEED_MCR_ADDR_REC0x5c /* address of last recoverable
> error */
> > @@ -34,10 +33,8 @@
> >  #define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)
> #define
> > ASPEED_MCR_INTR_CTRL_ENABLE  (BIT(0) | BIT(1))
> >
> > -
> >  static struct regmap *aspeed_regmap;
> >
> > -
> >  static int regmap_reg_write(void *context, unsigned int reg, unsigned
> > int val)  {
> > void __iomem *regs = (void __iomem *)context; @@ -53,7 +50,6 @@
> > static int regmap_reg_write(void *context, unsigned int reg, unsigned
> > int val)
> > return 0;
> >  }
> >
> > -
> >  static int regmap_reg_read(void *context, unsigned int reg, unsigned
> > int *val)  {
> > void __iomem *regs = (void __iomem *)context; @@ -63,6 +59,76 @@
> > static int regmap_reg_read(void *context, unsigned int reg, unsigned
> > int *val)
> > return 0;
> >  }
> >
> > +extern void aspeed_sdmc_disable_mem_protection(u8 req) {
> > +   u32 req_val = 0;
> > +
> > +   regmap_read(aspeed_regmap, ASPEED_MCR_REQ, &req_val);
> > +
> > +   req_val &= ~BIT(req);
> > +
> > +   regmap_write(aspeed_regmap, ASPEED_MCR_REQ, req_val); }
> > +EXPORT_SYMBOL(aspeed_sdmc_disable_mem_protection);
> > +
> > +static const u32 ast2400_dram_table[] = {
> > +   0x0400, //64MB
> > +   0x0800, //128MB
> > +   0x1000, //256MB
> > +   0x2000, //512MB
> > +};
> 
> You could perhaps save us from the size comments here by using e.g.
> 
> static const u32 ast2400_dram_table[] = {
> 64 << 20,
>  

[PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver

[Troy Lee]

Adding AST2400 and AST2600 edac driver support.

Signed-off-by: Troy Lee 
---
 drivers/edac/Kconfig   |   6 +-
 drivers/edac/aspeed_edac.c | 114 +
 2 files changed, 94 insertions(+), 26 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index fc30f2ef9782..8ea70746d0bf 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -508,10 +508,10 @@ config EDAC_QCOM
  health, you should probably say 'Y' here.
 
 config EDAC_ASPEED
-   tristate "Aspeed AST 2500 SoC"
-   depends on MACH_ASPEED_G5
+   tristate "Aspeed AST BMC SoC"
+   depends on (MACH_ASPEED_G4 || MACH_ASPEED_G5 || MACH_ASPEED_G6)
help
- Support for error detection and correction on the Aspeed AST 2500 SoC.
+ Support for error detection and correction on the Aspeed AST BMC SoC.
 
  First, ECC must be configured in the bootloader. Then, this driver
  will expose error counters via the EDAC kernel framework.
diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
index fbec28dc661d..03a3c12f6bf6 100644
--- a/drivers/edac/aspeed_edac.c
+++ b/drivers/edac/aspeed_edac.c
@@ -14,12 +14,11 @@
 #include 
 #include "edac_module.h"
 
-
 #define DRV_NAME "aspeed-edac"
 
-
 #define ASPEED_MCR_PROT0x00 /* protection key register */
 #define ASPEED_MCR_CONF0x04 /* configuration register */
+#define ASPEED_MCR_REQ 0x08 /* Graphics Memory Protection register */
 #define ASPEED_MCR_INTR_CTRL   0x50 /* interrupt control/status register */
 #define ASPEED_MCR_ADDR_UNREC  0x58 /* address of first un-recoverable error */
 #define ASPEED_MCR_ADDR_REC0x5c /* address of last recoverable error */
@@ -34,10 +33,8 @@
 #define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)
 #define ASPEED_MCR_INTR_CTRL_ENABLE  (BIT(0) | BIT(1))
 
-
 static struct regmap *aspeed_regmap;
 
-
 static int regmap_reg_write(void *context, unsigned int reg, unsigned int val)
 {
void __iomem *regs = (void __iomem *)context;
@@ -53,7 +50,6 @@ static int regmap_reg_write(void *context, unsigned int reg, 
unsigned int val)
return 0;
 }
 
-
 static int regmap_reg_read(void *context, unsigned int reg, unsigned int *val)
 {
void __iomem *regs = (void __iomem *)context;
@@ -63,6 +59,76 @@ static int regmap_reg_read(void *context, unsigned int reg, 
unsigned int *val)
return 0;
 }
 
+extern void aspeed_sdmc_disable_mem_protection(u8 req)
+{
+   u32 req_val = 0;
+
+   regmap_read(aspeed_regmap, ASPEED_MCR_REQ, &req_val);
+
+   req_val &= ~BIT(req);
+
+   regmap_write(aspeed_regmap, ASPEED_MCR_REQ, req_val);
+}
+EXPORT_SYMBOL(aspeed_sdmc_disable_mem_protection);
+
+static const u32 ast2400_dram_table[] = {
+   0x0400, //64MB
+   0x0800, //128MB
+   0x1000, //256MB
+   0x2000, //512MB
+};
+
+static const u32 ast2500_dram_table[] = {
+   0x0800, //128MB
+   0x1000, //256MB
+   0x2000, //512MB
+   0x4000, //1024MB
+};
+
+static const u32 ast2600_dram_table[] = {
+   0x1000, //256MB
+   0x2000, //512MB
+   0x4000, //1024MB
+   0x8000, //2048MB
+};
+
+extern u32 aspeed_get_dram_size(void)
+{
+   u32 reg04;
+   u32 size;
+
+   regmap_read(aspeed_regmap, ASPEED_MCR_CONF, ®04);
+
+#if defined(CONFIG_MACH_ASPEED_G6)
+   size = ast2600_dram_table[reg04 & 0x3];
+#elif defined(CONFIG_MACH_ASPEED_G5)
+   size = ast2500_dram_table[reg04 & 0x3];
+#else
+   size = ast2400_dram_table[reg04 & 0x3];
+#endif
+   return size;
+}
+EXPORT_SYMBOL(aspeed_get_dram_size);
+
+static const u32 aspeed_vga_table[] = {
+   0x80,   //8MB
+   0x100,  //16MB
+   0x200,  //32MB
+   0x400,  //64MB
+};
+
+extern u32 aspeed_get_vga_size(void)
+{
+   u32 reg04;
+   u32 size;
+
+   regmap_read(aspeed_regmap, ASPEED_MCR_CONF, ®04);
+
+   size = aspeed_vga_table[((reg04 & 0xC) >> 2)];
+   return size;
+}
+EXPORT_SYMBOL(aspeed_get_vga_size);
+
 static bool regmap_is_volatile(struct device *dev, unsigned int reg)
 {
switch (reg) {
@@ -209,8 +275,8 @@ static int config_irq(void *ctx, struct platform_device 
*pdev)
/* register interrupt handler */
irq = platform_get_irq(pdev, 0);
dev_dbg(&pdev->dev, "got irq %d\n", irq);
-   if (irq < 0)
-   return irq;
+   if (!irq)
+   return -ENODEV;
 
rc = devm_request_irq(&pdev->dev, irq, mcr_isr, IRQF_TRIGGER_HIGH,
  DRV_NAME, ctx);
@@ -239,7 +305,11 @@ static int init_csrows(struct mem_ctl_info *mci)
int rc;
 
/* retrieve info about physical memory from device tree */
-   np = of_find_node_by_path("/memory");
+#ifdef CONFIG_MA

[PATCH 2/3] ARM: dts: aspeed: Add AST2600 edac into common devicetree

[Troy Lee]

Adding Aspeed AST2600 edac node into common devicetree.

Signed-off-by: Troy Lee 
---
 arch/arm/boot/dts/aspeed-g6.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 97ca743363d7..fb144515f397 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -69,6 +69,12 @@
always-on;
};
 
+   edac: sdram@1e6e {
+   compatible = "aspeed,ast2600-sdram-edac", "syscon";
+   reg = <0x1e6e 0x174>;
+   interrupts = ;
+   };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
-- 
2.17.1

[PATCH 1/3] dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support

[Troy Lee]

Adding Aspeed AST2400 and AST2600 binding for edac driver.

Signed-off-by: Troy Lee 
---
 .../devicetree/bindings/edac/aspeed-sdram-edac.txt   | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt 
b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
index 6a0f3d90d682..8ca9e0a049d8 100644
--- a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
+++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
@@ -1,6 +1,6 @@
-Aspeed AST2500 SoC EDAC node
+Aspeed BMC SoC EDAC node
 
-The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC 
(error
+The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
 correction check).
 
 The memory controller supports SECDED (single bit error correction, double bit
@@ -11,7 +11,10 @@ Note, the bootloader must configure ECC mode in the memory 
controller.
 
 
 Required properties:
-- compatible: should be "aspeed,ast2500-sdram-edac"
+- compatible: should be one of
+   - "aspeed,ast2400-sdram-edac"
+   - "aspeed,ast2500-sdram-edac"
+   - "aspeed,ast2600-sdram-edac"
 - reg:sdram controller register set should be <0x1e6e 0x174>
 - interrupts: should be AVIC interrupt #0
 
-- 
2.17.1