Re: [PATCH v6 2/2] watchdog: Add new arm_smc_wdt watchdog driver
Tested on the Meson-A1.
Tested-by: Xingyu Chen
On 2020/5/5 11:13, Evan Benn wrote:
From: Julius Werner
This patch adds a watchdog driver that can be used on ARM systems
with the appropriate watchdog implemented in Secure Monitor firmware.
The driver communicates with firmware via a Secure Monitor Call.
This may be useful for platforms using TrustZone that want
the Secure Monitor firmware to have the final control over the watchdog.
This is implemented on mt8173 chromebook devices oak, elm and hana in
arm trusted firmware file plat/mediatek/mt8173/drivers/wdt/wdt.c.
Signed-off-by: Julius Werner
Signed-off-by: Evan Benn
---
Changes in v6:
- Use default arm,smc-id value if non provided by dt
Changes in v5:
- Make timeleft return 0 on error
- Use type punning on smc_func_id to save an alloc
- Change compatible to arm,smc-wdt
Changes in v4:
- Get smc-id from of property
- Return a1 instead of a0 in timeleft
Changes in v3:
- Add optional get_timeleft op
- change name to arm_smc_wdt
Changes in v2:
- use watchdog_stop_on_reboot
- use watchdog_stop_on_unregister
- use devm_watchdog_register_device
- remove smcwd_shutdown, smcwd_remove
- change error codes
MAINTAINERS| 1 +
arch/arm64/configs/defconfig | 1 +
drivers/watchdog/Kconfig | 13 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/arm_smc_wdt.c | 188 +
5 files changed, 204 insertions(+)
create mode 100644 drivers/watchdog/arm_smc_wdt.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 0f2b39767bfa9..2b782bbff200a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1462,6 +1462,7 @@ M:Julius Werner
R:Evan Benn
S:Maintained
F:devicetree/bindings/watchdog/arm-smc-wdt.yaml
+F: drivers/watchdog/arm_smc_wdt.c
ARM SMMU DRIVERS
M:Will Deacon
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 24e534d850454..0619df80f7575 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -513,6 +513,7 @@ CONFIG_UNIPHIER_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_ARM_SP805_WATCHDOG=y
CONFIG_ARM_SBSA_WATCHDOG=y
+CONFIG_ARM_SMC_WATCHDOG=y
CONFIG_S3C2410_WATCHDOG=y
CONFIG_DW_WATCHDOG=y
CONFIG_SUNXI_WATCHDOG=m
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 0663c604bd642..c440b576d23bf 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -867,6 +867,19 @@ config DIGICOLOR_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called digicolor_wdt.
+config ARM_SMC_WATCHDOG
+ tristate "ARM Secure Monitor Call based watchdog support"
+ depends on ARM || ARM64
+ depends on OF
+ depends on HAVE_ARM_SMCCC
+ select WATCHDOG_CORE
+ help
+ Say Y here to include support for a watchdog timer
+ implemented by the EL3 Secure Monitor on ARM platforms.
+ Requires firmware support.
+ To compile this driver as a module, choose M here: the
+ module will be called arm_smc_wdt.
+
config LPC18XX_WATCHDOG
tristate "LPC18xx/43xx Watchdog"
depends on ARCH_LPC18XX || COMPILE_TEST
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 6de2e4ceef190..97bed1d3d97cb 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -94,6 +94,7 @@ obj-$(CONFIG_UNIPHIER_WATCHDOG) += uniphier_wdt.o
obj-$(CONFIG_RTD119X_WATCHDOG) += rtd119x_wdt.o
obj-$(CONFIG_SPRD_WATCHDOG) += sprd_wdt.o
obj-$(CONFIG_PM8916_WATCHDOG) += pm8916_wdt.o
+obj-$(CONFIG_ARM_SMC_WATCHDOG) += arm_smc_wdt.o
# X86 (i386 + ia64 + x86_64) Architecture
obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o
diff --git a/drivers/watchdog/arm_smc_wdt.c b/drivers/watchdog/arm_smc_wdt.c
new file mode 100644
index 0..8f3d0c3a005fb
--- /dev/null
+++ b/drivers/watchdog/arm_smc_wdt.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * ARM Secure Monitor Call watchdog driver
+ *
+ * Copyright 2020 Google LLC.
+ * Julius Werner
+ * Based on mtk_wdt.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DRV_NAME "arm_smc_wdt"
+#define DRV_VERSION"1.0"
+
+enum smcwd_call {
+ SMCWD_INIT = 0,
+ SMCWD_SET_TIMEOUT = 1,
+ SMCWD_ENABLE= 2,
+ SMCWD_PET = 3,
+ SMCWD_GET_TIMELEFT = 4,
+};
+
+static bool nowayout = WATCHDOG_NOWAYOUT;
+static unsigned int timeout;
+
+static int smcwd_call(struct watchdog_device *wdd, enum smcwd_call call,
+ unsigned long arg, struct arm_smccc_res *res)
+{
+ struct arm_smccc_res local_res;
+
+ if (!res)
+ res = _res;
+
+ arm_smccc_smc((u32)(uintptr_t)watchdog_get_drvdata(wdd), call, arg, 0,
+ 0, 0, 0, 0, res);
+
+
Re: [PATCH v2 3/4] watchdog: add meson secure watchdog driver
Hi, Guenter
On 2019/10/21 21:38, Guenter Roeck wrote:
On 10/21/19 1:03 AM, Xingyu Chen wrote:
Hi, Guenter
On 2019/10/21 0:56, Guenter Roeck wrote:
On 10/18/19 1:33 AM, Xingyu Chen wrote:
The watchdog controller on the Meson-A/C series SoCs is moved to secure
world, watchdog operation needs to be done in secure EL3 mode via ATF,
Non-secure world can call SMC instruction to trap to AFT for watchdog
operation.
Signed-off-by: Xingyu Chen
---
drivers/watchdog/Kconfig | 17
drivers/watchdog/Makefile | 1 +
drivers/watchdog/meson_sec_wdt.c | 187
+++
3 files changed, 205 insertions(+)
create mode 100644 drivers/watchdog/meson_sec_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 58e7c10..e84be42 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -826,6 +826,23 @@ config MESON_GXBB_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called meson_gxbb_wdt.
+config MESON_SEC_WATCHDOG
+ tristate "Amlogic Meson Secure watchdog support"
+ depends on MESON_SM
+ depends on ARCH_MESON || COMPILE_TEST
This dependency is pointless. MESON_SM already depends on ARCH_MESON,
thus specifying "COMPILE_TEST" here adds no value but only
creates confusion.
Thanks for your analysis, perhaps i should remove the line below.
- depends on ARCH_MESON || COMPILE_TEST
Is it ok to modify code above like this ?
Yes.
Thanks, fix it in next version.
[ ... ]
+static unsigned int meson_sec_wdt_get_timeleft(struct
watchdog_device *wdt_dev)
+{
+ int ret;
+ unsigned int timeleft;
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ ret = meson_sm_call(data->fw, SM_WATCHDOG_OPS, Thanks,
+ MESON_SIP_WDT_GETTIMELEFT, 0, 0, 0, 0);
+
+ if (ret)
+ return ret;
Meh, that doesn't work. I just realized that the return type is
unsigned,
so returning a negative error code is pointless. Guess we'll have to
live with returning 0 in this case after all. I wonder if we should
fix the API and return an integer (with negative error code), but that
is a different question.
Thanks for your review.
IMO, if returning an integer, and the value which copy to user buf
should be formatted with %d instead of %u (see timeleft_show), it will
cause the max value of timeleft is reduced from 4294967295 to
2147483647. but i'am not sure whether it will bring risk.
Not that it matters right now, but I don't think that limiting 'timeleft'
reporting to 2147483647 seconds, or ~68 years, would cause any risk.
It would just be a large patch changing several drivers all at once,
that is all.
So i also think returning 0 may be better in this case.
Yes, please do that.
Thanks, fix it in next version.
Thanks,
Guenter
.
Re: [PATCH v2 3/4] watchdog: add meson secure watchdog driver
Hi, Guenter
On 2019/10/21 0:56, Guenter Roeck wrote:
On 10/18/19 1:33 AM, Xingyu Chen wrote:
The watchdog controller on the Meson-A/C series SoCs is moved to secure
world, watchdog operation needs to be done in secure EL3 mode via ATF,
Non-secure world can call SMC instruction to trap to AFT for watchdog
operation.
Signed-off-by: Xingyu Chen
---
drivers/watchdog/Kconfig | 17
drivers/watchdog/Makefile | 1 +
drivers/watchdog/meson_sec_wdt.c | 187
+++
3 files changed, 205 insertions(+)
create mode 100644 drivers/watchdog/meson_sec_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 58e7c10..e84be42 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -826,6 +826,23 @@ config MESON_GXBB_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called meson_gxbb_wdt.
+config MESON_SEC_WATCHDOG
+ tristate "Amlogic Meson Secure watchdog support"
+ depends on MESON_SM
+ depends on ARCH_MESON || COMPILE_TEST
This dependency is pointless. MESON_SM already depends on ARCH_MESON,
thus specifying "COMPILE_TEST" here adds no value but only
creates confusion.
Thanks for your analysis, perhaps i should remove the line below.
- depends on ARCH_MESON || COMPILE_TEST
Is it ok to modify code above like this ?
+ select WATCHDOG_CORE
+ help
+ The watchdog controller on the Meson-A/C series SoCs is moved to
+ secure world, watchdog operation needs to be done in secure EL3
+ mode via ATF, non-secure world can call SMC instruction to trap
+ to ATF for the watchdog operation.
+
+ Say Y here if watchdog controller on Meson SoCs is located in
+ secure world.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_sec_wdt.
+
config MESON_WATCHDOG
tristate "Amlogic Meson SoCs watchdog support"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 2ee352b..5e6b73d 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -78,6 +78,7 @@ obj-$(CONFIG_QCOM_WDT) += qcom-wdt.o
obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o
obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o
obj-$(CONFIG_MESON_GXBB_WATCHDOG) += meson_gxbb_wdt.o
+obj-$(CONFIG_MESON_SEC_WATCHDOG) += meson_sec_wdt.o
obj-$(CONFIG_MESON_WATCHDOG) += meson_wdt.o
obj-$(CONFIG_MEDIATEK_WATCHDOG) += mtk_wdt.o
obj-$(CONFIG_DIGICOLOR_WATCHDOG) += digicolor_wdt.o
diff --git a/drivers/watchdog/meson_sec_wdt.c
b/drivers/watchdog/meson_sec_wdt.c
new file mode 100644
index ..86bd87c
--- /dev/null
+++ b/drivers/watchdog/meson_sec_wdt.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MESON_SIP_WDT_DISABLE 0x1
+#define MESON_SIP_WDT_ENABLE 0x2
+#define MESON_SIP_WDT_PING 0x3
+#define MESON_SIP_WDT_INIT 0x4
+#define MESON_SIP_WDT_RESETNOW 0x5
+#define MESON_SIP_WDT_SETTIMEOUT 0x6
+#define MESON_SIP_WDT_GETTIMELEFT 0x7
+
+#define DEFAULT_TIMEOUT 30 /* seconds */
+
+/*
+ * Watchdog timer tick is set to 1ms in secfw side, and tick count is
+ * stored in the bit[16-31] of WATCHDOG_CNT register, so the maximum
+ * timeout value is 0x ms.
+ */
+#define MAX_TIMEOUT_MS 0x
+
+struct meson_sec_wdt {
+ struct watchdog_device wdt_dev;
+ struct meson_sm_firmware *fw;
+};
+
+static int meson_sec_wdt_start(struct watchdog_device *wdt_dev)
+{
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ return meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+ MESON_SIP_WDT_ENABLE, 0, 0, 0, 0);
+}
+
+static int meson_sec_wdt_stop(struct watchdog_device *wdt_dev)
+{
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ return meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+ MESON_SIP_WDT_DISABLE, 0, 0, 0, 0);
+}
+
+static int meson_sec_wdt_ping(struct watchdog_device *wdt_dev)
+{
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ return meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+ MESON_SIP_WDT_PING, 0, 0, 0, 0);
+}
+
+static int meson_sec_wdt_set_timeout(struct watchdog_device *wdt_dev,
+ unsigned int timeout)
+{
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ wdt_dev->timeout = timeout;
+
+ return meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+ MESON_SIP_WDT_SETTIMEOUT,
+ wdt_dev->timeout, 0, 0, 0);
+}
+
+static unsigned int meson_sec_wdt_get_timeleft(struct watchdog_device
*wdt_dev)
+{
+ int ret;
+ unsigned int timeleft;
+ struct meson_sec_wdt *
[PATCH v2 3/4] watchdog: add meson secure watchdog driver
The watchdog controller on the Meson-A/C series SoCs is moved to secure
world, watchdog operation needs to be done in secure EL3 mode via ATF,
Non-secure world can call SMC instruction to trap to AFT for watchdog
operation.
Signed-off-by: Xingyu Chen
---
drivers/watchdog/Kconfig | 17
drivers/watchdog/Makefile| 1 +
drivers/watchdog/meson_sec_wdt.c | 187 +++
3 files changed, 205 insertions(+)
create mode 100644 drivers/watchdog/meson_sec_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 58e7c10..e84be42 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -826,6 +826,23 @@ config MESON_GXBB_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called meson_gxbb_wdt.
+config MESON_SEC_WATCHDOG
+ tristate "Amlogic Meson Secure watchdog support"
+ depends on MESON_SM
+ depends on ARCH_MESON || COMPILE_TEST
+ select WATCHDOG_CORE
+ help
+ The watchdog controller on the Meson-A/C series SoCs is moved to
+ secure world, watchdog operation needs to be done in secure EL3
+ mode via ATF, non-secure world can call SMC instruction to trap
+ to ATF for the watchdog operation.
+
+ Say Y here if watchdog controller on Meson SoCs is located in
+ secure world.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_sec_wdt.
+
config MESON_WATCHDOG
tristate "Amlogic Meson SoCs watchdog support"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 2ee352b..5e6b73d 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -78,6 +78,7 @@ obj-$(CONFIG_QCOM_WDT) += qcom-wdt.o
obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o
obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o
obj-$(CONFIG_MESON_GXBB_WATCHDOG) += meson_gxbb_wdt.o
+obj-$(CONFIG_MESON_SEC_WATCHDOG) += meson_sec_wdt.o
obj-$(CONFIG_MESON_WATCHDOG) += meson_wdt.o
obj-$(CONFIG_MEDIATEK_WATCHDOG) += mtk_wdt.o
obj-$(CONFIG_DIGICOLOR_WATCHDOG) += digicolor_wdt.o
diff --git a/drivers/watchdog/meson_sec_wdt.c b/drivers/watchdog/meson_sec_wdt.c
new file mode 100644
index ..86bd87c
--- /dev/null
+++ b/drivers/watchdog/meson_sec_wdt.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MESON_SIP_WDT_DISABLE 0x1
+#define MESON_SIP_WDT_ENABLE 0x2
+#define MESON_SIP_WDT_PING 0x3
+#define MESON_SIP_WDT_INIT 0x4
+#define MESON_SIP_WDT_RESETNOW 0x5
+#define MESON_SIP_WDT_SETTIMEOUT 0x6
+#define MESON_SIP_WDT_GETTIMELEFT 0x7
+
+#define DEFAULT_TIMEOUT30 /* seconds */
+
+/*
+ * Watchdog timer tick is set to 1ms in secfw side, and tick count is
+ * stored in the bit[16-31] of WATCHDOG_CNT register, so the maximum
+ * timeout value is 0x ms.
+ */
+#define MAX_TIMEOUT_MS 0x
+
+struct meson_sec_wdt {
+ struct watchdog_device wdt_dev;
+ struct meson_sm_firmware *fw;
+};
+
+static int meson_sec_wdt_start(struct watchdog_device *wdt_dev)
+{
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ return meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+MESON_SIP_WDT_ENABLE, 0, 0, 0, 0);
+}
+
+static int meson_sec_wdt_stop(struct watchdog_device *wdt_dev)
+{
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ return meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+MESON_SIP_WDT_DISABLE, 0, 0, 0, 0);
+}
+
+static int meson_sec_wdt_ping(struct watchdog_device *wdt_dev)
+{
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ return meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+MESON_SIP_WDT_PING, 0, 0, 0, 0);
+}
+
+static int meson_sec_wdt_set_timeout(struct watchdog_device *wdt_dev,
+unsigned int timeout)
+{
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ wdt_dev->timeout = timeout;
+
+ return meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+MESON_SIP_WDT_SETTIMEOUT,
+wdt_dev->timeout, 0, 0, 0);
+}
+
+static unsigned int meson_sec_wdt_get_timeleft(struct watchdog_device *wdt_dev)
+{
+ int ret;
+ unsigned int timeleft;
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ ret = meson_sm_call(data->fw, SM_WATCHDOG_OPS, ,
+ MESON_SIP_WDT_GETTIMELEFT, 0, 0, 0, 0);
+
+ if (ret)
+ return ret;
+
+ return timelef
[PATCH v2 4/4] arm64: dts: a1: add secure watchdog controller
Enable secure watchdog controller for Meson-A1 SoC
Signed-off-by: Xingyu Chen
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..047c323 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -93,6 +93,12 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ watchdog {
+ compatible = "amlogic,meson-sec-wdt";
+ secure-monitor = <>;
+ status = "okay";
+ };
};
gic: interrupt-controller@ff901000 {
--
2.7.4
[PATCH v2 1/4] firmware: meson_sm: add new SMC ID support for accessing secure watchdog
The new SMC ID is used to access secure registers by meson secure
watchdog driver.
Signed-off-by: Xingyu Chen
---
drivers/firmware/meson/meson_sm.c | 1 +
include/linux/firmware/meson/meson_sm.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/firmware/meson/meson_sm.c
b/drivers/firmware/meson/meson_sm.c
index 1d5b4d7..46a44de 100644
--- a/drivers/firmware/meson/meson_sm.c
+++ b/drivers/firmware/meson/meson_sm.c
@@ -44,6 +44,7 @@ static const struct meson_sm_chip gxbb_chip = {
CMD(SM_EFUSE_WRITE, 0x8231),
CMD(SM_EFUSE_USER_MAX, 0x8233),
CMD(SM_GET_CHIP_ID, 0x8244),
+ CMD(SM_WATCHDOG_OPS,0x8286),
{ /* sentinel */ },
},
};
diff --git a/include/linux/firmware/meson/meson_sm.h
b/include/linux/firmware/meson/meson_sm.h
index 6669e2a..0934718 100644
--- a/include/linux/firmware/meson/meson_sm.h
+++ b/include/linux/firmware/meson/meson_sm.h
@@ -12,6 +12,7 @@ enum {
SM_EFUSE_WRITE,
SM_EFUSE_USER_MAX,
SM_GET_CHIP_ID,
+ SM_WATCHDOG_OPS,
};
struct meson_sm_firmware;
--
2.7.4
[PATCH v2 0/4] add meson secure watchdog driver
The watchdog controller on the Meson-A/C series SoCs is moved to secure world, We have to call SMC instruction to trap the ATF for watchdog operation. These operations are different from previous SoCs, so we introduce a new watchdog driver to support this kind of SoCs. Changes since v1 at [0]: - add a new dependency in Kconfig - simplify/add the return operation - remove useless ping operation when setting the timeout - fix some return values - fix the license statement [0]:https://lore.kernel.org/linux-amlogic/1570874721-36077-1-git-send-email-xingyu.c...@amlogic.com Xingyu Chen (4): firmware: meson_sm: add new SMC ID support for accessing secure watchdog dt-bindings: watchdog: add new binding for meson secure watchdog watchdog: add meson secure watchdog driver arm64: dts: a1: add secure watchdog controller .../bindings/watchdog/amlogic,meson-sec-wdt.yaml | 34 arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 + drivers/firmware/meson/meson_sm.c | 1 + drivers/watchdog/Kconfig | 17 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/meson_sec_wdt.c | 187 + include/linux/firmware/meson/meson_sm.h| 1 + 7 files changed, 247 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/amlogic,meson-sec-wdt.yaml create mode 100644 drivers/watchdog/meson_sec_wdt.c -- 2.7.4
[PATCH v2 2/4] dt-bindings: watchdog: add new binding for meson secure watchdog
The binding targets the Meson-A/C series compatible SoCs, in which the
watchdog registers are in secure world.
Signed-off-by: Xingyu Chen
---
.../bindings/watchdog/amlogic,meson-sec-wdt.yaml | 34 ++
1 file changed, 34 insertions(+)
create mode 100644
Documentation/devicetree/bindings/watchdog/amlogic,meson-sec-wdt.yaml
diff --git
a/Documentation/devicetree/bindings/watchdog/amlogic,meson-sec-wdt.yaml
b/Documentation/devicetree/bindings/watchdog/amlogic,meson-sec-wdt.yaml
new file mode 100644
index ..0bbc807
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/amlogic,meson-sec-wdt.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+# Copyright (c) 2019 Amlogic, Inc
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/amlogic,meson-sec-wdt.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson Secure Watchdog Timer
+
+maintainers:
+ - Xingyu Chen
+
+description: |+
+ Secure Watchdog Timer used in Meson-A/C series Compatible SoCs
+
+properties:
+ compatible:
+enum:
+ - amlogic,meson-sec-wdt
+
+ secure-monitor:
+description: phandle to the secure-monitor node
+$ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+ - compatible
+ - secure-monitor
+
+examples:
+ - |
+watchdog {
+ compatible = "amlogic,meson-sec-wdt";
+ secure-monitor = <>;
+};
--
2.7.4
Re: [PATCH 3/4] watchdog: add meson secure watchdog driver
Hi, Guenter
On 2019/10/14 21:49, Guenter Roeck wrote:
On 10/14/19 4:42 AM, Xingyu Chen wrote:
Hi, Guenter
Thanks for your review.
On 2019/10/12 22:29, Guenter Roeck wrote:
On 10/12/19 3:05 AM, Xingyu Chen wrote:
The watchdog controller on the Meson-A/C series SoCs is moved to secure
world, watchdog operation needs to be done in secure EL3 mode via ATF,
Non-secure world can call SMC instruction to trap to AFT for watchdog
operation.
Signed-off-by: Xingyu Chen
---
drivers/watchdog/Kconfig | 16 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/meson_sec_wdt.c | 205
+++
3 files changed, 222 insertions(+)
create mode 100644 drivers/watchdog/meson_sec_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 58e7c10..e6b0707 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -826,6 +826,22 @@ config MESON_GXBB_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called meson_gxbb_wdt.
+config MESON_SEC_WATCHDOG
+ tristate "Amlogic Meson Secure watchdog support"
+ depends on ARCH_MESON || COMPILE_TEST
Did you try COMPILE_TEST (eg allmodconfig) on, say x86_64 ?
AFAICS the meson sm calls are only available if MESON_SM is
enabled, and that depends on both ARCH_MESON and ARM64_4K_PAGES.
This dependency is not expressed here, and neither is enabled
with COMPILE_TEST.Sorry, I have't done this kind of test before for
this patchset. There
is a kernel build error which related to the current driver when i try
to use allmodconfig with x86. I will fix it by adding "depends on
MESON_SM" in next version.
+ select WATCHDOG_CORE
+ help
+ The watchdog controller on the Meson-A/C series SoCs is moved to
+ secure world, watchdog operation needs to be done in secure EL3
+ mode via ATF, non-secure world can call SMC instruction to trap
+ to ATF for the watchdog operation.
+
+ Say Y here if watchdog controller on Meson SoCs is located in
+ secure world.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_sec_wdt.
+
config MESON_WATCHDOG
tristate "Amlogic Meson SoCs watchdog support"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 2ee352b..5e6b73d 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -78,6 +78,7 @@ obj-$(CONFIG_QCOM_WDT) += qcom-wdt.o
obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o
obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o
obj-$(CONFIG_MESON_GXBB_WATCHDOG) += meson_gxbb_wdt.o
+obj-$(CONFIG_MESON_SEC_WATCHDOG) += meson_sec_wdt.o
obj-$(CONFIG_MESON_WATCHDOG) += meson_wdt.o
obj-$(CONFIG_MEDIATEK_WATCHDOG) += mtk_wdt.o
obj-$(CONFIG_DIGICOLOR_WATCHDOG) += digicolor_wdt.o
diff --git a/drivers/watchdog/meson_sec_wdt.c
b/drivers/watchdog/meson_sec_wdt.c
new file mode 100644
index ..2b5357c
--- /dev/null
+++ b/drivers/watchdog/meson_sec_wdt.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MESON_SIP_WDT_DISABLE 0x1
+#define MESON_SIP_WDT_ENABLE 0x2
+#define MESON_SIP_WDT_PING 0x3
+#define MESON_SIP_WDT_INIT 0x4
+#define MESON_SIP_WDT_RESETNOW 0x5
+#define MESON_SIP_WDT_SETTIMEOUT 0x6
+#define MESON_SIP_WDT_GETTIMELEFT 0x7
+
+#define DEFAULT_TIMEOUT 30 /* seconds */
+
+/*
+ * Watchdog timer tick is set to 1ms in secfw side, and tick count is
+ * stored in the bit[16-31] of WATCHDOG_CNT register, so the maximum
+ * timeout value is 0x ms.
+ */
+#define MAX_TIMEOUT_MS 0x
+
+struct meson_sec_wdt {
+ struct watchdog_device wdt_dev;
+ struct meson_sm_firmware *fw;
+};
+
+static int meson_sec_wdt_start(struct watchdog_device *wdt_dev)
+{
+ int ret;
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ ret = meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+ MESON_SIP_WDT_ENABLE, 0, 0, 0, 0); > + if (ret)
+ return ret;
+
+ return 0;
This is equivalent to
return ret;
or even
return meson_sm_call(...);
I will fix it in next version.
+}
+
+static int meson_sec_wdt_stop(struct watchdog_device *wdt_dev)
+{
+ int ret;
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ ret = meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+ MESON_SIP_WDT_DISABLE, 0, 0, 0, 0);
+ if (ret)
+ return ret;
+
+ return 0;
Same as above.
I will fix it in next version.
+}
+
+static int meson_sec_wdt_ping(struct watchdog_device *wdt_dev)
+{
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+
Re: [PATCH 3/4] watchdog: add meson secure watchdog driver
Hi, Guenter
Thanks for your review.
On 2019/10/12 22:29, Guenter Roeck wrote:
On 10/12/19 3:05 AM, Xingyu Chen wrote:
The watchdog controller on the Meson-A/C series SoCs is moved to secure
world, watchdog operation needs to be done in secure EL3 mode via ATF,
Non-secure world can call SMC instruction to trap to AFT for watchdog
operation.
Signed-off-by: Xingyu Chen
---
drivers/watchdog/Kconfig | 16 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/meson_sec_wdt.c | 205
+++
3 files changed, 222 insertions(+)
create mode 100644 drivers/watchdog/meson_sec_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 58e7c10..e6b0707 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -826,6 +826,22 @@ config MESON_GXBB_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called meson_gxbb_wdt.
+config MESON_SEC_WATCHDOG
+ tristate "Amlogic Meson Secure watchdog support"
+ depends on ARCH_MESON || COMPILE_TEST
Did you try COMPILE_TEST (eg allmodconfig) on, say x86_64 ?
AFAICS the meson sm calls are only available if MESON_SM is
enabled, and that depends on both ARCH_MESON and ARM64_4K_PAGES.
This dependency is not expressed here, and neither is enabled
with COMPILE_TEST.Sorry, I have't done this kind of test before for this
patchset. There
is a kernel build error which related to the current driver when i try
to use allmodconfig with x86. I will fix it by adding "depends on
MESON_SM" in next version.
+ select WATCHDOG_CORE
+ help
+ The watchdog controller on the Meson-A/C series SoCs is moved to
+ secure world, watchdog operation needs to be done in secure EL3
+ mode via ATF, non-secure world can call SMC instruction to trap
+ to ATF for the watchdog operation.
+
+ Say Y here if watchdog controller on Meson SoCs is located in
+ secure world.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_sec_wdt.
+
config MESON_WATCHDOG
tristate "Amlogic Meson SoCs watchdog support"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 2ee352b..5e6b73d 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -78,6 +78,7 @@ obj-$(CONFIG_QCOM_WDT) += qcom-wdt.o
obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o
obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o
obj-$(CONFIG_MESON_GXBB_WATCHDOG) += meson_gxbb_wdt.o
+obj-$(CONFIG_MESON_SEC_WATCHDOG) += meson_sec_wdt.o
obj-$(CONFIG_MESON_WATCHDOG) += meson_wdt.o
obj-$(CONFIG_MEDIATEK_WATCHDOG) += mtk_wdt.o
obj-$(CONFIG_DIGICOLOR_WATCHDOG) += digicolor_wdt.o
diff --git a/drivers/watchdog/meson_sec_wdt.c
b/drivers/watchdog/meson_sec_wdt.c
new file mode 100644
index ..2b5357c
--- /dev/null
+++ b/drivers/watchdog/meson_sec_wdt.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MESON_SIP_WDT_DISABLE 0x1
+#define MESON_SIP_WDT_ENABLE 0x2
+#define MESON_SIP_WDT_PING 0x3
+#define MESON_SIP_WDT_INIT 0x4
+#define MESON_SIP_WDT_RESETNOW 0x5
+#define MESON_SIP_WDT_SETTIMEOUT 0x6
+#define MESON_SIP_WDT_GETTIMELEFT 0x7
+
+#define DEFAULT_TIMEOUT 30 /* seconds */
+
+/*
+ * Watchdog timer tick is set to 1ms in secfw side, and tick count is
+ * stored in the bit[16-31] of WATCHDOG_CNT register, so the maximum
+ * timeout value is 0x ms.
+ */
+#define MAX_TIMEOUT_MS 0x
+
+struct meson_sec_wdt {
+ struct watchdog_device wdt_dev;
+ struct meson_sm_firmware *fw;
+};
+
+static int meson_sec_wdt_start(struct watchdog_device *wdt_dev)
+{
+ int ret;
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ ret = meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+ MESON_SIP_WDT_ENABLE, 0, 0, 0, 0); > + if (ret)
+ return ret;
+
+ return 0;
This is equivalent to
return ret;
or even
return meson_sm_call(...);
I will fix it in next version.
+}
+
+static int meson_sec_wdt_stop(struct watchdog_device *wdt_dev)
+{
+ int ret;
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ ret = meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+ MESON_SIP_WDT_DISABLE, 0, 0, 0, 0);
+ if (ret)
+ return ret;
+
+ return 0;
Same as above.
I will fix it in next version.
+}
+
+static int meson_sec_wdt_ping(struct watchdog_device *wdt_dev)
+{
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+ MESON_SIP_WDT_PING, 0, 0, 0, 0);
+
+ return 0;
Why ignore errors ?
I
[PATCH 2/4] dt-bindings: watchdog: add new binding for meson secure watchdog
The binding targets the Meson-A/C series compatible SoCs, in which the
watchdog registers are in secure world.
Signed-off-by: Xingyu Chen
---
.../bindings/watchdog/amlogic,meson-sec-wdt.yaml | 34 ++
1 file changed, 34 insertions(+)
create mode 100644
Documentation/devicetree/bindings/watchdog/amlogic,meson-sec-wdt.yaml
diff --git
a/Documentation/devicetree/bindings/watchdog/amlogic,meson-sec-wdt.yaml
b/Documentation/devicetree/bindings/watchdog/amlogic,meson-sec-wdt.yaml
new file mode 100644
index ..0bbc807
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/amlogic,meson-sec-wdt.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+# Copyright (c) 2019 Amlogic, Inc
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/amlogic,meson-sec-wdt.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson Secure Watchdog Timer
+
+maintainers:
+ - Xingyu Chen
+
+description: |+
+ Secure Watchdog Timer used in Meson-A/C series Compatible SoCs
+
+properties:
+ compatible:
+enum:
+ - amlogic,meson-sec-wdt
+
+ secure-monitor:
+description: phandle to the secure-monitor node
+$ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+ - compatible
+ - secure-monitor
+
+examples:
+ - |
+watchdog {
+ compatible = "amlogic,meson-sec-wdt";
+ secure-monitor = <>;
+};
--
2.7.4
[PATCH 4/4] arm64: dts: a1: add secure watchdog controller
Enable secure watchdog controller for Meson-A1 SoC
Signed-off-by: Xingyu Chen
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..047c323 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -93,6 +93,12 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ watchdog {
+ compatible = "amlogic,meson-sec-wdt";
+ secure-monitor = <>;
+ status = "okay";
+ };
};
gic: interrupt-controller@ff901000 {
--
2.7.4
[PATCH 1/4] firmware: meson_sm: add new SMC ID support for accessing secure watchdog
The new SMC ID is used to access secure registers by meson secure
watchdog driver.
Signed-off-by: Xingyu Chen
---
drivers/firmware/meson/meson_sm.c | 1 +
include/linux/firmware/meson/meson_sm.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/firmware/meson/meson_sm.c
b/drivers/firmware/meson/meson_sm.c
index 1d5b4d7..46a44de 100644
--- a/drivers/firmware/meson/meson_sm.c
+++ b/drivers/firmware/meson/meson_sm.c
@@ -44,6 +44,7 @@ static const struct meson_sm_chip gxbb_chip = {
CMD(SM_EFUSE_WRITE, 0x8231),
CMD(SM_EFUSE_USER_MAX, 0x8233),
CMD(SM_GET_CHIP_ID, 0x8244),
+ CMD(SM_WATCHDOG_OPS,0x8286),
{ /* sentinel */ },
},
};
diff --git a/include/linux/firmware/meson/meson_sm.h
b/include/linux/firmware/meson/meson_sm.h
index 6669e2a..0934718 100644
--- a/include/linux/firmware/meson/meson_sm.h
+++ b/include/linux/firmware/meson/meson_sm.h
@@ -12,6 +12,7 @@ enum {
SM_EFUSE_WRITE,
SM_EFUSE_USER_MAX,
SM_GET_CHIP_ID,
+ SM_WATCHDOG_OPS,
};
struct meson_sm_firmware;
--
2.7.4
[PATCH 3/4] watchdog: add meson secure watchdog driver
The watchdog controller on the Meson-A/C series SoCs is moved to secure
world, watchdog operation needs to be done in secure EL3 mode via ATF,
Non-secure world can call SMC instruction to trap to AFT for watchdog
operation.
Signed-off-by: Xingyu Chen
---
drivers/watchdog/Kconfig | 16 +++
drivers/watchdog/Makefile| 1 +
drivers/watchdog/meson_sec_wdt.c | 205 +++
3 files changed, 222 insertions(+)
create mode 100644 drivers/watchdog/meson_sec_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 58e7c10..e6b0707 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -826,6 +826,22 @@ config MESON_GXBB_WATCHDOG
To compile this driver as a module, choose M here: the
module will be called meson_gxbb_wdt.
+config MESON_SEC_WATCHDOG
+ tristate "Amlogic Meson Secure watchdog support"
+ depends on ARCH_MESON || COMPILE_TEST
+ select WATCHDOG_CORE
+ help
+ The watchdog controller on the Meson-A/C series SoCs is moved to
+ secure world, watchdog operation needs to be done in secure EL3
+ mode via ATF, non-secure world can call SMC instruction to trap
+ to ATF for the watchdog operation.
+
+ Say Y here if watchdog controller on Meson SoCs is located in
+ secure world.
+
+ To compile this driver as a module, choose M here: the
+ module will be called meson_sec_wdt.
+
config MESON_WATCHDOG
tristate "Amlogic Meson SoCs watchdog support"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 2ee352b..5e6b73d 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -78,6 +78,7 @@ obj-$(CONFIG_QCOM_WDT) += qcom-wdt.o
obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o
obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o
obj-$(CONFIG_MESON_GXBB_WATCHDOG) += meson_gxbb_wdt.o
+obj-$(CONFIG_MESON_SEC_WATCHDOG) += meson_sec_wdt.o
obj-$(CONFIG_MESON_WATCHDOG) += meson_wdt.o
obj-$(CONFIG_MEDIATEK_WATCHDOG) += mtk_wdt.o
obj-$(CONFIG_DIGICOLOR_WATCHDOG) += digicolor_wdt.o
diff --git a/drivers/watchdog/meson_sec_wdt.c b/drivers/watchdog/meson_sec_wdt.c
new file mode 100644
index ..2b5357c
--- /dev/null
+++ b/drivers/watchdog/meson_sec_wdt.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MESON_SIP_WDT_DISABLE 0x1
+#define MESON_SIP_WDT_ENABLE 0x2
+#define MESON_SIP_WDT_PING 0x3
+#define MESON_SIP_WDT_INIT 0x4
+#define MESON_SIP_WDT_RESETNOW 0x5
+#define MESON_SIP_WDT_SETTIMEOUT 0x6
+#define MESON_SIP_WDT_GETTIMELEFT 0x7
+
+#define DEFAULT_TIMEOUT30 /* seconds */
+
+/*
+ * Watchdog timer tick is set to 1ms in secfw side, and tick count is
+ * stored in the bit[16-31] of WATCHDOG_CNT register, so the maximum
+ * timeout value is 0x ms.
+ */
+#define MAX_TIMEOUT_MS 0x
+
+struct meson_sec_wdt {
+ struct watchdog_device wdt_dev;
+ struct meson_sm_firmware *fw;
+};
+
+static int meson_sec_wdt_start(struct watchdog_device *wdt_dev)
+{
+ int ret;
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ ret = meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+ MESON_SIP_WDT_ENABLE, 0, 0, 0, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int meson_sec_wdt_stop(struct watchdog_device *wdt_dev)
+{
+ int ret;
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ ret = meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+ MESON_SIP_WDT_DISABLE, 0, 0, 0, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int meson_sec_wdt_ping(struct watchdog_device *wdt_dev)
+{
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+ MESON_SIP_WDT_PING, 0, 0, 0, 0);
+
+ return 0;
+}
+
+static int meson_sec_wdt_set_timeout(struct watchdog_device *wdt_dev,
+unsigned int timeout)
+{
+ int ret;
+ struct meson_sec_wdt *data = watchdog_get_drvdata(wdt_dev);
+
+ wdt_dev->timeout = timeout;
+ meson_sec_wdt_ping(wdt_dev);
+
+ ret = meson_sm_call(data->fw, SM_WATCHDOG_OPS, NULL,
+ MESON_SIP_WDT_SETTIMEOUT,
+ wdt_dev->timeout, 0, 0, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static unsigned int meson_sec_wdt_get_timeleft(struct watchdog_device *wdt_dev)
+{
+ int ret;
+ int timeleft;
+ struct meso
[PATCH 0/4] add meson secure watchdog driver
The watchdog controller on the Meson-A/C series SoCs is moved to secure world, We have to call SMC instruction to trap the ATF for watchdog operation. These operations are different from previous SoCs, so we introduce a new watchdog driver to support this kind of SoCs. Xingyu Chen (4): firmware: meson_sm: add new SMC ID support for accessing secure watchdog dt-bindings: watchdog: add new binding for meson secure watchdog watchdog: add meson secure watchdog driver arm64: dts: a1: add secure watchdog controller .../bindings/watchdog/amlogic,meson-sec-wdt.yaml | 34 arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 + drivers/firmware/meson/meson_sm.c | 1 + drivers/watchdog/Kconfig | 16 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/meson_sec_wdt.c | 205 + include/linux/firmware/meson/meson_sm.h| 1 + 7 files changed, 264 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/amlogic,meson-sec-wdt.yaml create mode 100644 drivers/watchdog/meson_sec_wdt.c -- 2.7.4
[PATCH] watchdog: meson: Fix the wrong value of left time
The left time value is wrong when we get it by sysfs. The left time value
should be equal to preset timeout value minus elapsed time value. According
to the Meson-GXB/GXL datasheets which can be found at [0], the timeout value
is saved to BIT[0-15] of the WATCHDOG_TCNT, and elapsed time value is saved
to BIT[16-31] of the WATCHDOG_TCNT.
[0]: http://linux-meson.com
Fixes: 683fa50f0e18 ("watchdog: Add Meson GXBB Watchdog Driver")
Signed-off-by: Xingyu Chen
---
drivers/watchdog/meson_gxbb_wdt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/watchdog/meson_gxbb_wdt.c
b/drivers/watchdog/meson_gxbb_wdt.c
index d17c1a6..5a9ca10 100644
--- a/drivers/watchdog/meson_gxbb_wdt.c
+++ b/drivers/watchdog/meson_gxbb_wdt.c
@@ -89,8 +89,8 @@ static unsigned int meson_gxbb_wdt_get_timeleft(struct
watchdog_device *wdt_dev)
reg = readl(data->reg_base + GXBB_WDT_TCNT_REG);
- return ((reg >> GXBB_WDT_TCNT_CNT_SHIFT) -
- (reg & GXBB_WDT_TCNT_SETUP_MASK)) / 1000;
+ return ((reg & GXBB_WDT_TCNT_SETUP_MASK) -
+ (reg >> GXBB_WDT_TCNT_CNT_SHIFT)) / 1000;
}
static const struct watchdog_ops meson_gxbb_wdt_ops = {
--
2.7.4
[PATCH v3 1/3] arm64: dts: meson: add reset controller for Meson-A1 SoC
Add the reset controller device of Meson-A1 SoC family
Signed-off-by: Xingyu Chen
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..1c588ab 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -74,6 +74,12 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe00 0x0 0x100>;
+ reset: reset-controller@0 {
+ compatible = "amlogic,meson-a1-reset";
+ reg = <0x0 0x0 0x0 0x8c>;
+ #reset-cells = <1>;
+ };
+
uart_AO: serial@1c00 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
--
2.7.4
[PATCH v3 2/3] dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller
Add DT bindings for the Meson-A1 SoC Reset Controller include file, and also slightly update documentation. Signed-off-by: Xingyu Chen --- .../bindings/reset/amlogic,meson-reset.yaml| 1 + include/dt-bindings/reset/amlogic,meson-a1-reset.h | 74 ++ 2 files changed, 75 insertions(+) create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml index 00917d8..b3f57d8 100644 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml @@ -16,6 +16,7 @@ properties: - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs + - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs reg: maxItems: 1 diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h new file mode 100644 index ..f1a3a79 --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-a1-reset.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H + +/* RESET0 */ +/* 0 */ +#define RESET_AM2AXI_VAD 1 +/* 2-3 */ +#define RESET_PSRAM4 +#define RESET_PAD_CTRL 5 +/* 6 */ +#define RESET_TEMP_SENSOR 7 +#define RESET_AM2AXI_DEV 8 +/* 9 */ +#define RESET_SPICC_A 10 +#define RESET_MSR_CLK 11 +#define RESET_AUDIO12 +#define RESET_ANALOG_CTRL 13 +#define RESET_SAR_ADC 14 +#define RESET_AUDIO_VAD15 +#define RESET_CEC 16 +#define RESET_PWM_EF 17 +#define RESET_PWM_CD 18 +#define RESET_PWM_AB 19 +/* 20 */ +#define RESET_IR_CTRL 21 +#define RESET_I2C_S_A 22 +/* 23 */ +#define RESET_I2C_M_D 24 +#define RESET_I2C_M_C 25 +#define RESET_I2C_M_B 26 +#define RESET_I2C_M_A 27 +#define RESET_I2C_PROD_AHB 28 +#define RESET_I2C_PROD 29 +/* 30-31 */ + +/* RESET1 */ +#define RESET_ACODEC 32 +#define RESET_DMA 33 +#define RESET_SD_EMMC_A34 +/* 35 */ +#define RESET_USBCTRL 36 +/* 37 */ +#define RESET_USBPHY 38 +/* 39-41 */ +#define RESET_RSA 42 +#define RESET_DMC 43 +/* 44 */ +#define RESET_IRQ_CTRL 45 +/* 46 */ +#define RESET_NIC_VAD 47 +#define RESET_NIC_AXI 48 +#define RESET_RAMA 49 +#define RESET_RAMB 50 +/* 51-52 */ +#define RESET_ROM 53 +#define RESET_SPIFC54 +#define RESET_GIC 55 +#define RESET_UART_C 56 +#define RESET_UART_B 57 +#define RESET_UART_A 58 +#define RESET_OSC_RING 59 +/* 60-63 */ + +/* RESET2 */ +/* 64-95 */ + +#endif -- 2.7.4
[PATCH v3 0/3] reset: meson: add Meson-A1 SoC support
This patchset adds support for Meson-A1 SoC Reset Controller. A new struct meson_reset_param is introduced to describe the register differences between Meson-A1 and previous SoCs. Changes since v2 at [1]: - add comments in header file to indicate holes - reorder the Signed-off-by and Reviewed-by - remove Jianxin's Signed-off-by - add Kevin's Reviewed-by Changes since v1 at [0]: - rebase on linux-next - add Neil's Reviewed-by [0] https://lore.kernel.org/linux-amlogic/1568808746-1153-1-git-send-email-xingyu.c...@amlogic.com [1] https://lore.kernel.org/linux-amlogic/1569227661-4261-1-git-send-email-xingyu.c...@amlogic.com Xingyu Chen (3): arm64: dts: meson: add reset controller for Meson-A1 SoC dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller reset: add support for the Meson-A1 SoC Reset Controller .../bindings/reset/amlogic,meson-reset.yaml| 1 + arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 ++ drivers/reset/reset-meson.c| 35 -- include/dt-bindings/reset/amlogic,meson-a1-reset.h | 74 ++ 4 files changed, 109 insertions(+), 7 deletions(-) create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h -- 2.7.4
[PATCH v3 3/3] reset: add support for the Meson-A1 SoC Reset Controller
The number of RESET registers and offset of RESET_LEVEL register for
Meson-A1 are different from previous SoCs, In order to describe these
differences, we introduce the struct meson_reset_param.
Reviewed-by: Kevin Hilman
Reviewed-by: Neil Armstrong
Signed-off-by: Xingyu Chen
---
drivers/reset/reset-meson.c | 35 ---
1 file changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index 7d05d76..94d7ba8 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -15,12 +15,16 @@
#include
#include
-#define REG_COUNT 8
#define BITS_PER_REG 32
-#define LEVEL_OFFSET 0x7c
+
+struct meson_reset_param {
+ int reg_count;
+ int level_offset;
+};
struct meson_reset {
void __iomem *reg_base;
+ const struct meson_reset_param *param;
struct reset_controller_dev rcdev;
spinlock_t lock;
};
@@ -46,10 +50,12 @@ static int meson_reset_level(struct reset_controller_dev
*rcdev,
container_of(rcdev, struct meson_reset, rcdev);
unsigned int bank = id / BITS_PER_REG;
unsigned int offset = id % BITS_PER_REG;
- void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
+ void __iomem *reg_addr;
unsigned long flags;
u32 reg;
+ reg_addr = data->reg_base + data->param->level_offset + (bank << 2);
+
spin_lock_irqsave(>lock, flags);
reg = readl(reg_addr);
@@ -81,10 +87,21 @@ static const struct reset_control_ops meson_reset_ops = {
.deassert = meson_reset_deassert,
};
+static const struct meson_reset_param meson8b_param = {
+ .reg_count = 8,
+ .level_offset = 0x7c,
+};
+
+static const struct meson_reset_param meson_a1_param = {
+ .reg_count = 3,
+ .level_offset = 0x40,
+};
+
static const struct of_device_id meson_reset_dt_ids[] = {
-{ .compatible = "amlogic,meson8b-reset" },
-{ .compatible = "amlogic,meson-gxbb-reset" },
-{ .compatible = "amlogic,meson-axg-reset" },
+{ .compatible = "amlogic,meson8b-reset",.data = _param},
+{ .compatible = "amlogic,meson-gxbb-reset", .data = _param},
+{ .compatible = "amlogic,meson-axg-reset", .data = _param},
+{ .compatible = "amlogic,meson-a1-reset", .data = _a1_param},
{ /* sentinel */ },
};
@@ -102,12 +119,16 @@ static int meson_reset_probe(struct platform_device *pdev)
if (IS_ERR(data->reg_base))
return PTR_ERR(data->reg_base);
+ data->param = of_device_get_match_data(>dev);
+ if (!data->param)
+ return -ENODEV;
+
platform_set_drvdata(pdev, data);
spin_lock_init(>lock);
data->rcdev.owner = THIS_MODULE;
- data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
+ data->rcdev.nr_resets = data->param->reg_count * BITS_PER_REG;
data->rcdev.ops = _reset_ops;
data->rcdev.of_node = pdev->dev.of_node;
--
2.7.4
Re: [PATCH v2 3/3] reset: add support for the Meson-A1 SoC Reset Controller
Hi, Kevin Thanks for your reminder On 2019/9/26 6:57, Kevin Hilman wrote: Hi Xingyu, Xingyu Chen writes: The number of RESET registers and offset of RESET_LEVEL register for Meson-A1 are different from previous SoCs, In order to describe these differences, we introduce the struct meson_reset_param. Signed-off-by: Xingyu Chen Signed-off-by: Jianxin Pan Reviewed-by: Neil Armstrong Again, order here isn't quite right. Add the reviewed-by tags first, and the sender should be the last sign-off. I will reorder Signed-off and Reviewed in next version Other than that, driver looks good. Reviewed-by: Kevin Hilman Kevin .
Re: [PATCH v2 2/3] dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller
Hi, Kevin Thanks for your review On 2019/9/26 6:55, Kevin Hilman wrote: Xingyu Chen writes: Add DT bindings for the Meson-A1 SoC Reset Controller include file, and also slightly update documentation. Signed-off-by: Xingyu Chen Signed-off-by: Jianxin Pan The order here doesn't look right. As the sender, your sign-off should be last. Is Jianxin the author or are you? If Jianxin, there should be a "From:" line at the beginning of the changelog to indicate authorship that's different from the sender. I am an author for this patchset, i will reorder Signed-off in next version. --- .../bindings/reset/amlogic,meson-reset.yaml| 1 + include/dt-bindings/reset/amlogic,meson-a1-reset.h | 59 ++ 2 files changed, 60 insertions(+) create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml index 00917d8..b3f57d8 100644 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml @@ -16,6 +16,7 @@ properties: - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs + - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs reg: maxItems: 1 diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h new file mode 100644 index ..8d76a47 --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-a1-reset.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H + +/* RESET0 */ +#define RESET_AM2AXI_VAD 1 minor nit: can you use comments/whitespace here to indicate holes? Please see the other amlogic files in this dir for examples. I will fix it in next version. Kevin .
[PATCH v2 1/3] arm64: dts: meson: add reset controller for Meson-A1 SoC
Add the reset controller device of Meson-A1 SoC family
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..1c588ab 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -74,6 +74,12 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe00 0x0 0x100>;
+ reset: reset-controller@0 {
+ compatible = "amlogic,meson-a1-reset";
+ reg = <0x0 0x0 0x0 0x8c>;
+ #reset-cells = <1>;
+ };
+
uart_AO: serial@1c00 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
--
2.7.4
[PATCH v2 2/3] dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller
Add DT bindings for the Meson-A1 SoC Reset Controller include file, and also slightly update documentation. Signed-off-by: Xingyu Chen Signed-off-by: Jianxin Pan --- .../bindings/reset/amlogic,meson-reset.yaml| 1 + include/dt-bindings/reset/amlogic,meson-a1-reset.h | 59 ++ 2 files changed, 60 insertions(+) create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml index 00917d8..b3f57d8 100644 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml @@ -16,6 +16,7 @@ properties: - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs + - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs reg: maxItems: 1 diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h new file mode 100644 index ..8d76a47 --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-a1-reset.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H + +/* RESET0 */ +#define RESET_AM2AXI_VAD 1 +#define RESET_PSRAM4 +#define RESET_PAD_CTRL 5 +#define RESET_TEMP_SENSOR 7 +#define RESET_AM2AXI_DEV 8 +#define RESET_SPICC_A 10 +#define RESET_MSR_CLK 11 +#define RESET_AUDIO12 +#define RESET_ANALOG_CTRL 13 +#define RESET_SAR_ADC 14 +#define RESET_AUDIO_VAD15 +#define RESET_CEC 16 +#define RESET_PWM_EF 17 +#define RESET_PWM_CD 18 +#define RESET_PWM_AB 19 +#define RESET_IR_CTRL 21 +#define RESET_I2C_S_A 22 +#define RESET_I2C_M_D 24 +#define RESET_I2C_M_C 25 +#define RESET_I2C_M_B 26 +#define RESET_I2C_M_A 27 +#define RESET_I2C_PROD_AHB 28 +#define RESET_I2C_PROD 29 + +/* RESET1 */ +#define RESET_ACODEC 32 +#define RESET_DMA 33 +#define RESET_SD_EMMC_A34 +#define RESET_USBCTRL 36 +#define RESET_USBPHY 38 +#define RESET_RSA 42 +#define RESET_DMC 43 +#define RESET_IRQ_CTRL 45 +#define RESET_NIC_VAD 47 +#define RESET_NIC_AXI 48 +#define RESET_RAMA 49 +#define RESET_RAMB 50 +#define RESET_ROM 53 +#define RESET_SPIFC54 +#define RESET_GIC 55 +#define RESET_UART_C 56 +#define RESET_UART_B 57 +#define RESET_UART_A 58 +#define RESET_OSC_RING 59 + +/* RESET2 Reserved */ + +#endif -- 2.7.4
[PATCH v2 3/3] reset: add support for the Meson-A1 SoC Reset Controller
The number of RESET registers and offset of RESET_LEVEL register for
Meson-A1 are different from previous SoCs, In order to describe these
differences, we introduce the struct meson_reset_param.
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
Reviewed-by: Neil Armstrong
---
drivers/reset/reset-meson.c | 35 ---
1 file changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index 7d05d76..94d7ba8 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -15,12 +15,16 @@
#include
#include
-#define REG_COUNT 8
#define BITS_PER_REG 32
-#define LEVEL_OFFSET 0x7c
+
+struct meson_reset_param {
+ int reg_count;
+ int level_offset;
+};
struct meson_reset {
void __iomem *reg_base;
+ const struct meson_reset_param *param;
struct reset_controller_dev rcdev;
spinlock_t lock;
};
@@ -46,10 +50,12 @@ static int meson_reset_level(struct reset_controller_dev
*rcdev,
container_of(rcdev, struct meson_reset, rcdev);
unsigned int bank = id / BITS_PER_REG;
unsigned int offset = id % BITS_PER_REG;
- void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
+ void __iomem *reg_addr;
unsigned long flags;
u32 reg;
+ reg_addr = data->reg_base + data->param->level_offset + (bank << 2);
+
spin_lock_irqsave(>lock, flags);
reg = readl(reg_addr);
@@ -81,10 +87,21 @@ static const struct reset_control_ops meson_reset_ops = {
.deassert = meson_reset_deassert,
};
+static const struct meson_reset_param meson8b_param = {
+ .reg_count = 8,
+ .level_offset = 0x7c,
+};
+
+static const struct meson_reset_param meson_a1_param = {
+ .reg_count = 3,
+ .level_offset = 0x40,
+};
+
static const struct of_device_id meson_reset_dt_ids[] = {
-{ .compatible = "amlogic,meson8b-reset" },
-{ .compatible = "amlogic,meson-gxbb-reset" },
-{ .compatible = "amlogic,meson-axg-reset" },
+{ .compatible = "amlogic,meson8b-reset",.data = _param},
+{ .compatible = "amlogic,meson-gxbb-reset", .data = _param},
+{ .compatible = "amlogic,meson-axg-reset", .data = _param},
+{ .compatible = "amlogic,meson-a1-reset", .data = _a1_param},
{ /* sentinel */ },
};
@@ -102,12 +119,16 @@ static int meson_reset_probe(struct platform_device *pdev)
if (IS_ERR(data->reg_base))
return PTR_ERR(data->reg_base);
+ data->param = of_device_get_match_data(>dev);
+ if (!data->param)
+ return -ENODEV;
+
platform_set_drvdata(pdev, data);
spin_lock_init(>lock);
data->rcdev.owner = THIS_MODULE;
- data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
+ data->rcdev.nr_resets = data->param->reg_count * BITS_PER_REG;
data->rcdev.ops = _reset_ops;
data->rcdev.of_node = pdev->dev.of_node;
--
2.7.4
[PATCH v2 0/3] reset: meson: add Meson-A1 SoC support
This patchset adds support for Meson-A1 SoC Reset Controller. A new struct meson_reset_param is introduced to describe the register differences between Meson-A1 and previous SoCs. This patchset is based on A1 DTBv4[0]. Changes since v1 at [1]: - rebase on linux-next - add Neil's Reviewed-by [0] https://lore.kernel.org/linux-amlogic/1568276370-54181-1-git-send-email-jianxin@amlogic.com [1] https://lore.kernel.org/linux-amlogic/1568808746-1153-1-git-send-email-xingyu.c...@amlogic.com Xingyu Chen (3): arm64: dts: meson: add reset controller for Meson-A1 SoC dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller reset: add support for the Meson-A1 SoC Reset Controller .../bindings/reset/amlogic,meson-reset.yaml| 1 + arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 +++ drivers/reset/reset-meson.c| 35 ++--- include/dt-bindings/reset/amlogic,meson-a1-reset.h | 59 ++ 4 files changed, 94 insertions(+), 7 deletions(-) create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h -- 2.7.4
Re: [PATCH 2/3] dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller
Hi, Neil Thanks for your review On 2019/9/18 20:39, Neil Armstrong wrote: Hi, On 18/09/2019 14:12, Xingyu Chen wrote: Add DT bindings for the Meson-A1 SoC Reset Controller include file, and also slightly update documentation. Signed-off-by: Xingyu Chen Signed-off-by: Jianxin Pan --- .../bindings/reset/amlogic,meson-reset.txt | 4 +- The reset bindings has been moved to yaml, either rebase on linux-next or wait for v5.4-rc1 : https://kernel.googlesource.com/pub/scm/linux/kernel/git/next/linux-next/+/refs/tags/next-20190917/Documentation/devicetree/bindings/reset/amlogic%2Cmeson-reset.yaml NeilI will fix it in next version. include/dt-bindings/reset/amlogic,meson-a1-reset.h | 59 ++ 2 files changed, 61 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt index 28ef6c2..011151a 100644 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt @@ -5,8 +5,8 @@ Please also refer to reset.txt in this directory for common reset controller binding usage. Required properties: -- compatible: Should be "amlogic,meson8b-reset", "amlogic,meson-gxbb-reset" or - "amlogic,meson-axg-reset". +- compatible: Should be "amlogic,meson8b-reset", "amlogic,meson-gxbb-reset", + "amlogic,meson-axg-reset" or "amlogic,meson-a1-reset". - reg: should contain the register address base - #reset-cells: 1, see below diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h new file mode 100644 index ..8d76a47 --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-a1-reset.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H + +/* RESET0 */ +#define RESET_AM2AXI_VAD 1 +#define RESET_PSRAM4 +#define RESET_PAD_CTRL 5 +#define RESET_TEMP_SENSOR 7 +#define RESET_AM2AXI_DEV 8 +#define RESET_SPICC_A 10 +#define RESET_MSR_CLK 11 +#define RESET_AUDIO12 +#define RESET_ANALOG_CTRL 13 +#define RESET_SAR_ADC 14 +#define RESET_AUDIO_VAD15 +#define RESET_CEC 16 +#define RESET_PWM_EF 17 +#define RESET_PWM_CD 18 +#define RESET_PWM_AB 19 +#define RESET_IR_CTRL 21 +#define RESET_I2C_S_A 22 +#define RESET_I2C_M_D 24 +#define RESET_I2C_M_C 25 +#define RESET_I2C_M_B 26 +#define RESET_I2C_M_A 27 +#define RESET_I2C_PROD_AHB 28 +#define RESET_I2C_PROD 29 + +/* RESET1 */ +#define RESET_ACODEC 32 +#define RESET_DMA 33 +#define RESET_SD_EMMC_A34 +#define RESET_USBCTRL 36 +#define RESET_USBPHY 38 +#define RESET_RSA 42 +#define RESET_DMC 43 +#define RESET_IRQ_CTRL 45 +#define RESET_NIC_VAD 47 +#define RESET_NIC_AXI 48 +#define RESET_RAMA 49 +#define RESET_RAMB 50 +#define RESET_ROM 53 +#define RESET_SPIFC54 +#define RESET_GIC 55 +#define RESET_UART_C 56 +#define RESET_UART_B 57 +#define RESET_UART_A 58 +#define RESET_OSC_RING 59 + +/* RESET2 Reserved */ + +#endif .
[PATCH 0/3] reset: meson: add Meson-A1 SoC support
This patchset adds support for Meson-A1 SoC Reset Controller. A new struct meson_reset_param is introduced to describe the register differences between Meson-A1 and previous SoCs This patchset is based on A1 DTBv4[1]. [1] https://lore.kernel.org/linux-amlogic/1568276370-54181-1-git-send-email-jianxin@amlogic.com Xingyu Chen (3): arm64: dts: meson: add reset controller for Meson-A1 SoC dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller reset: add support for the Meson-A1 SoC Reset Controller .../bindings/reset/amlogic,meson-reset.txt | 4 +- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 +++ drivers/reset/reset-meson.c| 35 ++--- include/dt-bindings/reset/amlogic,meson-a1-reset.h | 59 ++ 4 files changed, 95 insertions(+), 9 deletions(-) create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h -- 2.7.4
[PATCH 2/3] dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller
Add DT bindings for the Meson-A1 SoC Reset Controller include file, and also slightly update documentation. Signed-off-by: Xingyu Chen Signed-off-by: Jianxin Pan --- .../bindings/reset/amlogic,meson-reset.txt | 4 +- include/dt-bindings/reset/amlogic,meson-a1-reset.h | 59 ++ 2 files changed, 61 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt index 28ef6c2..011151a 100644 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt @@ -5,8 +5,8 @@ Please also refer to reset.txt in this directory for common reset controller binding usage. Required properties: -- compatible: Should be "amlogic,meson8b-reset", "amlogic,meson-gxbb-reset" or - "amlogic,meson-axg-reset". +- compatible: Should be "amlogic,meson8b-reset", "amlogic,meson-gxbb-reset", + "amlogic,meson-axg-reset" or "amlogic,meson-a1-reset". - reg: should contain the register address base - #reset-cells: 1, see below diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h new file mode 100644 index ..8d76a47 --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-a1-reset.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H + +/* RESET0 */ +#define RESET_AM2AXI_VAD 1 +#define RESET_PSRAM4 +#define RESET_PAD_CTRL 5 +#define RESET_TEMP_SENSOR 7 +#define RESET_AM2AXI_DEV 8 +#define RESET_SPICC_A 10 +#define RESET_MSR_CLK 11 +#define RESET_AUDIO12 +#define RESET_ANALOG_CTRL 13 +#define RESET_SAR_ADC 14 +#define RESET_AUDIO_VAD15 +#define RESET_CEC 16 +#define RESET_PWM_EF 17 +#define RESET_PWM_CD 18 +#define RESET_PWM_AB 19 +#define RESET_IR_CTRL 21 +#define RESET_I2C_S_A 22 +#define RESET_I2C_M_D 24 +#define RESET_I2C_M_C 25 +#define RESET_I2C_M_B 26 +#define RESET_I2C_M_A 27 +#define RESET_I2C_PROD_AHB 28 +#define RESET_I2C_PROD 29 + +/* RESET1 */ +#define RESET_ACODEC 32 +#define RESET_DMA 33 +#define RESET_SD_EMMC_A34 +#define RESET_USBCTRL 36 +#define RESET_USBPHY 38 +#define RESET_RSA 42 +#define RESET_DMC 43 +#define RESET_IRQ_CTRL 45 +#define RESET_NIC_VAD 47 +#define RESET_NIC_AXI 48 +#define RESET_RAMA 49 +#define RESET_RAMB 50 +#define RESET_ROM 53 +#define RESET_SPIFC54 +#define RESET_GIC 55 +#define RESET_UART_C 56 +#define RESET_UART_B 57 +#define RESET_UART_A 58 +#define RESET_OSC_RING 59 + +/* RESET2 Reserved */ + +#endif -- 2.7.4
[PATCH 3/3] reset: add support for the Meson-A1 SoC Reset Controller
The number of RESET registers and offset of RESET_LEVEL register for
Meson-A1 are different from previous SoCs, In order to describe these
differences, we introduce the struct meson_reset_param.
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/reset/reset-meson.c | 35 ---
1 file changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index 5242e06..d9541c1 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -64,12 +64,16 @@
#include
#include
-#define REG_COUNT 8
#define BITS_PER_REG 32
-#define LEVEL_OFFSET 0x7c
+
+struct meson_reset_param {
+ int reg_count;
+ int level_offset;
+};
struct meson_reset {
void __iomem *reg_base;
+ const struct meson_reset_param *param;
struct reset_controller_dev rcdev;
spinlock_t lock;
};
@@ -95,10 +99,12 @@ static int meson_reset_level(struct reset_controller_dev
*rcdev,
container_of(rcdev, struct meson_reset, rcdev);
unsigned int bank = id / BITS_PER_REG;
unsigned int offset = id % BITS_PER_REG;
- void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
+ void __iomem *reg_addr;
unsigned long flags;
u32 reg;
+ reg_addr = data->reg_base + data->param->level_offset + (bank << 2);
+
spin_lock_irqsave(>lock, flags);
reg = readl(reg_addr);
@@ -130,10 +136,21 @@ static const struct reset_control_ops meson_reset_ops = {
.deassert = meson_reset_deassert,
};
+static const struct meson_reset_param meson8b_param = {
+ .reg_count = 8,
+ .level_offset = 0x7c,
+};
+
+static const struct meson_reset_param meson_a1_param = {
+ .reg_count = 3,
+ .level_offset = 0x40,
+};
+
static const struct of_device_id meson_reset_dt_ids[] = {
-{ .compatible = "amlogic,meson8b-reset" },
-{ .compatible = "amlogic,meson-gxbb-reset" },
-{ .compatible = "amlogic,meson-axg-reset" },
+{ .compatible = "amlogic,meson8b-reset",.data = _param},
+{ .compatible = "amlogic,meson-gxbb-reset", .data = _param},
+{ .compatible = "amlogic,meson-axg-reset", .data = _param},
+{ .compatible = "amlogic,meson-a1-reset", .data = _a1_param},
{ /* sentinel */ },
};
@@ -151,12 +168,16 @@ static int meson_reset_probe(struct platform_device *pdev)
if (IS_ERR(data->reg_base))
return PTR_ERR(data->reg_base);
+ data->param = of_device_get_match_data(>dev);
+ if (!data->param)
+ return -ENODEV;
+
platform_set_drvdata(pdev, data);
spin_lock_init(>lock);
data->rcdev.owner = THIS_MODULE;
- data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
+ data->rcdev.nr_resets = data->param->reg_count * BITS_PER_REG;
data->rcdev.ops = _reset_ops;
data->rcdev.of_node = pdev->dev.of_node;
--
2.7.4
[PATCH 1/3] arm64: dts: meson: add reset controller for Meson-A1 SoC
Add the reset controller device of Meson-A1 SoC family
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..1c588ab 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -74,6 +74,12 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe00 0x0 0x100>;
+ reset: reset-controller@0 {
+ compatible = "amlogic,meson-a1-reset";
+ reg = <0x0 0x0 0x0 0x8c>;
+ #reset-cells = <1>;
+ };
+
uart_AO: serial@1c00 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
--
2.7.4
[PATCH v2 0/2] irqchip/meson-gpio: Add support for Meson-G12A SoC
This series try to add GPIO interrupt controller support for Meson-G12A SoCs. Although the total number of pins is the same as the Meson-AXG SoC, the gpio banks and irq numbers are different. To avoid confusion on use, i think the new compatible string is needed. Changes since v1: [1] - share the device data with Meson-AXG [1]: https://lore.kernel.org/lkml/20181203061324.36248-1-xingyu.c...@amlogic.com Xingyu Chen (2): dt-bindings: interrupt-controller: New binding for Meson-G12A SoC irqchip/meson-gpio: Add support for Meson-G12A SoC .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt| 1 + drivers/irqchip/irq-meson-gpio.c | 1 + 2 files changed, 2 insertions(+) -- 2.19.2
[PATCH v2 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC
The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
- 223:100 undefined (no interrupt)
- 99:97 3 pins on bank GPIOE
- 96:77 20 pins on bank GPIOX
- 76:61 16 pins on bank GPIOA
- 60:53 8 pins on bank GPIOC
- 52:37 16 pins on bank BOOT
- 36:28 9 pins on bank GPIOH
- 27:12 16 pins on bank GPIOZ
- 11:012 pins in the AO domain
Change-Id: I977b19380b3dc730b5b81583178af743d0ba0338
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/irqchip/irq-meson-gpio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index 7b531fd075b8..7599b10ecf09 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -73,6 +73,7 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-axg-gpio-intc", .data = _params },
+ { .compatible = "amlogic,meson-g12a-gpio-intc", .data = _params },
{ }
};
--
2.19.2
[PATCH v2 0/2] irqchip/meson-gpio: Add support for Meson-G12A SoC
This series try to add GPIO interrupt controller support for Meson-G12A SoCs. Although the total number of pins is the same as the Meson-AXG SoC, the gpio banks and irq numbers are different. To avoid confusion on use, i think the new compatible string is needed. Changes since v1: [1] - share the device data with Meson-AXG [1]: https://lore.kernel.org/lkml/20181203061324.36248-1-xingyu.c...@amlogic.com Xingyu Chen (2): dt-bindings: interrupt-controller: New binding for Meson-G12A SoC irqchip/meson-gpio: Add support for Meson-G12A SoC .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt| 1 + drivers/irqchip/irq-meson-gpio.c | 1 + 2 files changed, 2 insertions(+) -- 2.19.2
[PATCH v2 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC
The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
- 223:100 undefined (no interrupt)
- 99:97 3 pins on bank GPIOE
- 96:77 20 pins on bank GPIOX
- 76:61 16 pins on bank GPIOA
- 60:53 8 pins on bank GPIOC
- 52:37 16 pins on bank BOOT
- 36:28 9 pins on bank GPIOH
- 27:12 16 pins on bank GPIOZ
- 11:012 pins in the AO domain
Change-Id: I977b19380b3dc730b5b81583178af743d0ba0338
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/irqchip/irq-meson-gpio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index 7b531fd075b8..7599b10ecf09 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -73,6 +73,7 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-axg-gpio-intc", .data = _params },
+ { .compatible = "amlogic,meson-g12a-gpio-intc", .data = _params },
{ }
};
--
2.19.2
[PATCH v2 1/2] dt-bindings: interrupt-controller: New binding for Meson-G12A SoC
Update the dt-binding document to support new compatible string for the GPIO interrupt controller which found in Amlogic's Meson-G12A SoC. Signed-off-by: Xingyu Chen Signed-off-by: Jianxin Pan --- .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt| 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt index 1502a51548bb..7d531d5fff29 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -15,6 +15,7 @@ Required properties: "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912) "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X) +"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2) - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an -- 2.19.2
[PATCH v2 1/2] dt-bindings: interrupt-controller: New binding for Meson-G12A SoC
Update the dt-binding document to support new compatible string for the GPIO interrupt controller which found in Amlogic's Meson-G12A SoC. Signed-off-by: Xingyu Chen Signed-off-by: Jianxin Pan --- .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt| 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt index 1502a51548bb..7d531d5fff29 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -15,6 +15,7 @@ Required properties: "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912) "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X) +"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2) - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an -- 2.19.2
Re: [PATCH] pinctrl: meson: fix G12A ao pull registers base address
On 2018/12/3 18:36, Jerome Brunet wrote:
On Mon, 2018-12-03 at 11:27 +0100, Neil Armstrong wrote:
Hi Xingyu,
On 03/12/2018 04:05, Xingyu Chen wrote:
Since Meson G12A SoC, Introduce new ao registers AO_RTI_PULL_UP_EN_REG
and AO_GPIO_O.
These bits of controlling output level are remapped to the new register
AO_GPIO_O, and the AO_GPIO_O_EN_N support only controlling output enable.
These bits of controlling pull enable are remapped to the new register
AO_RTI_PULL_UP_EN_REG, and the AO_RTI_PULL_UP_REG support only controlling
pull type(up/down).
The new layout of ao gpio/pull registers is as follows:
- AO_GPIO_O_EN_N[offset: 0x9 << 2]
- AO_GPIO_I [offset: 0xa << 2]
- AO_RTI_PULL_UP_REG[offset: 0xb << 2]
- AO_RTI_PULL_UP_EN_REG [offset: 0xc << 2]
- AO_GPIO_O [offset: 0xd << 2]
From above, we can see ao GPIO registers region has been separated by the
ao pull registers. In order to ensure the continuity of the region on
software, the ao GPIO and ao pull registers use the same base address, but
can be identified by the offset.
Fixes: 29ae0952e85f ("pinctrl: meson-g12a: add pinctrl driver support")
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/pinctrl/meson/pinctrl-meson.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c
b/drivers/pinctrl/meson/pinctrl-meson.c
index 53d449076dee..7ff40cd7a0cb 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -31,6 +31,9 @@
* In some cases the register ranges for pull enable and pull
* direction are the same and thus there are only 3 register ranges.
*
+ * Since Meson G12A SoC, the ao register ranges for gpio, pull enable
+ * and pull direction are the same, so there are only 2 register ranges.
+ *
* For the pull and GPIO configuration every bank uses a contiguous
* set of bits in the register sets described above; the same register
* can be shared by more banks with different offsets.
@@ -487,23 +490,22 @@ static int meson_pinctrl_parse_dt(struct
meson_pinctrl *pc,
return PTR_ERR(pc->reg_mux);
}
- pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
- if (IS_ERR(pc->reg_pull)) {
- dev_err(pc->dev, "pull registers not found\n");
- return PTR_ERR(pc->reg_pull);
+ pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
+ if (IS_ERR(pc->reg_gpio)) {
+ dev_err(pc->dev, "gpio registers not found\n");
+ return PTR_ERR(pc->reg_gpio);
}
+ pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
+ /* Use gpio region if pull one is not present */
+ if (IS_ERR(pc->reg_pull))
+ pc->reg_pull = pc->reg_gpio;
+
pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
/* Use pull region if pull-enable one is not present */
if (IS_ERR(pc->reg_pullen))
pc->reg_pullen = pc->reg_pull;
- pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
- if (IS_ERR(pc->reg_gpio)) {
- dev_err(pc->dev, "gpio registers not found\n");
- return PTR_ERR(pc->reg_gpio);
- }
-
return 0;
}
Doesn't it need an update of the bindings ?
Going even further, shouldn't we stop trying make multiple regions out of
this, and have just one ?
On all the Amlogic SoC we have seen so far, all the regions a very (VERY)
close to each other. It seems very unlikely that there something unrelated to
GPIO in between.
It looks like everything is mostly there in the driver to deal with offset, so
change would be minimal.
Of course, for DT stability we will need to carry the legacy, but for newer
SoC, such as the g12, does it really makes sense to have multiple regions ?
Hi, Jerome
the ee gpio, pull and pull-en register regions are discontinuous, some
addresses are reserved between them and maybe used for other module. For
example [G12A]:
range of gpio register address offset:(0x010 << 2) - (0x022 << 2)
range of pull register address offset:(0x03a << 2) - (0x03f << 2)
range of pull-en register address offset: (0x048 << 2) - (0x04d << 2)
keeping the multiple register regions seems to be more flexible and
friendly for Meson Series SoCs at present.
Neil
.
Re: [PATCH] pinctrl: meson: fix G12A ao pull registers base address
On 2018/12/3 18:36, Jerome Brunet wrote:
On Mon, 2018-12-03 at 11:27 +0100, Neil Armstrong wrote:
Hi Xingyu,
On 03/12/2018 04:05, Xingyu Chen wrote:
Since Meson G12A SoC, Introduce new ao registers AO_RTI_PULL_UP_EN_REG
and AO_GPIO_O.
These bits of controlling output level are remapped to the new register
AO_GPIO_O, and the AO_GPIO_O_EN_N support only controlling output enable.
These bits of controlling pull enable are remapped to the new register
AO_RTI_PULL_UP_EN_REG, and the AO_RTI_PULL_UP_REG support only controlling
pull type(up/down).
The new layout of ao gpio/pull registers is as follows:
- AO_GPIO_O_EN_N[offset: 0x9 << 2]
- AO_GPIO_I [offset: 0xa << 2]
- AO_RTI_PULL_UP_REG[offset: 0xb << 2]
- AO_RTI_PULL_UP_EN_REG [offset: 0xc << 2]
- AO_GPIO_O [offset: 0xd << 2]
From above, we can see ao GPIO registers region has been separated by the
ao pull registers. In order to ensure the continuity of the region on
software, the ao GPIO and ao pull registers use the same base address, but
can be identified by the offset.
Fixes: 29ae0952e85f ("pinctrl: meson-g12a: add pinctrl driver support")
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/pinctrl/meson/pinctrl-meson.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c
b/drivers/pinctrl/meson/pinctrl-meson.c
index 53d449076dee..7ff40cd7a0cb 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -31,6 +31,9 @@
* In some cases the register ranges for pull enable and pull
* direction are the same and thus there are only 3 register ranges.
*
+ * Since Meson G12A SoC, the ao register ranges for gpio, pull enable
+ * and pull direction are the same, so there are only 2 register ranges.
+ *
* For the pull and GPIO configuration every bank uses a contiguous
* set of bits in the register sets described above; the same register
* can be shared by more banks with different offsets.
@@ -487,23 +490,22 @@ static int meson_pinctrl_parse_dt(struct
meson_pinctrl *pc,
return PTR_ERR(pc->reg_mux);
}
- pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
- if (IS_ERR(pc->reg_pull)) {
- dev_err(pc->dev, "pull registers not found\n");
- return PTR_ERR(pc->reg_pull);
+ pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
+ if (IS_ERR(pc->reg_gpio)) {
+ dev_err(pc->dev, "gpio registers not found\n");
+ return PTR_ERR(pc->reg_gpio);
}
+ pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
+ /* Use gpio region if pull one is not present */
+ if (IS_ERR(pc->reg_pull))
+ pc->reg_pull = pc->reg_gpio;
+
pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
/* Use pull region if pull-enable one is not present */
if (IS_ERR(pc->reg_pullen))
pc->reg_pullen = pc->reg_pull;
- pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
- if (IS_ERR(pc->reg_gpio)) {
- dev_err(pc->dev, "gpio registers not found\n");
- return PTR_ERR(pc->reg_gpio);
- }
-
return 0;
}
Doesn't it need an update of the bindings ?
Going even further, shouldn't we stop trying make multiple regions out of
this, and have just one ?
On all the Amlogic SoC we have seen so far, all the regions a very (VERY)
close to each other. It seems very unlikely that there something unrelated to
GPIO in between.
It looks like everything is mostly there in the driver to deal with offset, so
change would be minimal.
Of course, for DT stability we will need to carry the legacy, but for newer
SoC, such as the g12, does it really makes sense to have multiple regions ?
Hi, Jerome
the ee gpio, pull and pull-en register regions are discontinuous, some
addresses are reserved between them and maybe used for other module. For
example [G12A]:
range of gpio register address offset:(0x010 << 2) - (0x022 << 2)
range of pull register address offset:(0x03a << 2) - (0x03f << 2)
range of pull-en register address offset: (0x048 << 2) - (0x04d << 2)
keeping the multiple register regions seems to be more flexible and
friendly for Meson Series SoCs at present.
Neil
.
Re: [PATCH] pinctrl: meson: fix G12A ao pull registers base address
On 2018/12/3 18:27, Neil Armstrong wrote:
Hi Xingyu,
On 03/12/2018 04:05, Xingyu Chen wrote:
Since Meson G12A SoC, Introduce new ao registers AO_RTI_PULL_UP_EN_REG
and AO_GPIO_O.
These bits of controlling output level are remapped to the new register
AO_GPIO_O, and the AO_GPIO_O_EN_N support only controlling output enable.
These bits of controlling pull enable are remapped to the new register
AO_RTI_PULL_UP_EN_REG, and the AO_RTI_PULL_UP_REG support only controlling
pull type(up/down).
The new layout of ao gpio/pull registers is as follows:
- AO_GPIO_O_EN_N[offset: 0x9 << 2]
- AO_GPIO_I [offset: 0xa << 2]
- AO_RTI_PULL_UP_REG[offset: 0xb << 2]
- AO_RTI_PULL_UP_EN_REG [offset: 0xc << 2]
- AO_GPIO_O [offset: 0xd << 2]
From above, we can see ao GPIO registers region has been separated by the
ao pull registers. In order to ensure the continuity of the region on
software, the ao GPIO and ao pull registers use the same base address, but
can be identified by the offset.
Fixes: 29ae0952e85f ("pinctrl: meson-g12a: add pinctrl driver support")
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/pinctrl/meson/pinctrl-meson.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c
b/drivers/pinctrl/meson/pinctrl-meson.c
index 53d449076dee..7ff40cd7a0cb 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -31,6 +31,9 @@
* In some cases the register ranges for pull enable and pull
* direction are the same and thus there are only 3 register ranges.
*
+ * Since Meson G12A SoC, the ao register ranges for gpio, pull enable
+ * and pull direction are the same, so there are only 2 register ranges.
+ *
* For the pull and GPIO configuration every bank uses a contiguous
* set of bits in the register sets described above; the same register
* can be shared by more banks with different offsets.
@@ -487,23 +490,22 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl
*pc,
return PTR_ERR(pc->reg_mux);
}
- pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
- if (IS_ERR(pc->reg_pull)) {
- dev_err(pc->dev, "pull registers not found\n");
- return PTR_ERR(pc->reg_pull);
+ pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
+ if (IS_ERR(pc->reg_gpio)) {
+ dev_err(pc->dev, "gpio registers not found\n");
+ return PTR_ERR(pc->reg_gpio);
}
+ pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
+ /* Use gpio region if pull one is not present */
+ if (IS_ERR(pc->reg_pull))
+ pc->reg_pull = pc->reg_gpio;
+
pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
/* Use pull region if pull-enable one is not present */
if (IS_ERR(pc->reg_pullen))
pc->reg_pullen = pc->reg_pull;
- pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
- if (IS_ERR(pc->reg_gpio)) {
- dev_err(pc->dev, "gpio registers not found\n");
- return PTR_ERR(pc->reg_gpio);
- }
-
return 0;
}
Doesn't it need an update of the bindings ?
Neil
Thanks, I will update it in next patch
.
Re: [PATCH] pinctrl: meson: fix G12A ao pull registers base address
On 2018/12/3 18:27, Neil Armstrong wrote:
Hi Xingyu,
On 03/12/2018 04:05, Xingyu Chen wrote:
Since Meson G12A SoC, Introduce new ao registers AO_RTI_PULL_UP_EN_REG
and AO_GPIO_O.
These bits of controlling output level are remapped to the new register
AO_GPIO_O, and the AO_GPIO_O_EN_N support only controlling output enable.
These bits of controlling pull enable are remapped to the new register
AO_RTI_PULL_UP_EN_REG, and the AO_RTI_PULL_UP_REG support only controlling
pull type(up/down).
The new layout of ao gpio/pull registers is as follows:
- AO_GPIO_O_EN_N[offset: 0x9 << 2]
- AO_GPIO_I [offset: 0xa << 2]
- AO_RTI_PULL_UP_REG[offset: 0xb << 2]
- AO_RTI_PULL_UP_EN_REG [offset: 0xc << 2]
- AO_GPIO_O [offset: 0xd << 2]
From above, we can see ao GPIO registers region has been separated by the
ao pull registers. In order to ensure the continuity of the region on
software, the ao GPIO and ao pull registers use the same base address, but
can be identified by the offset.
Fixes: 29ae0952e85f ("pinctrl: meson-g12a: add pinctrl driver support")
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/pinctrl/meson/pinctrl-meson.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c
b/drivers/pinctrl/meson/pinctrl-meson.c
index 53d449076dee..7ff40cd7a0cb 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -31,6 +31,9 @@
* In some cases the register ranges for pull enable and pull
* direction are the same and thus there are only 3 register ranges.
*
+ * Since Meson G12A SoC, the ao register ranges for gpio, pull enable
+ * and pull direction are the same, so there are only 2 register ranges.
+ *
* For the pull and GPIO configuration every bank uses a contiguous
* set of bits in the register sets described above; the same register
* can be shared by more banks with different offsets.
@@ -487,23 +490,22 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl
*pc,
return PTR_ERR(pc->reg_mux);
}
- pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
- if (IS_ERR(pc->reg_pull)) {
- dev_err(pc->dev, "pull registers not found\n");
- return PTR_ERR(pc->reg_pull);
+ pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
+ if (IS_ERR(pc->reg_gpio)) {
+ dev_err(pc->dev, "gpio registers not found\n");
+ return PTR_ERR(pc->reg_gpio);
}
+ pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
+ /* Use gpio region if pull one is not present */
+ if (IS_ERR(pc->reg_pull))
+ pc->reg_pull = pc->reg_gpio;
+
pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
/* Use pull region if pull-enable one is not present */
if (IS_ERR(pc->reg_pullen))
pc->reg_pullen = pc->reg_pull;
- pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
- if (IS_ERR(pc->reg_gpio)) {
- dev_err(pc->dev, "gpio registers not found\n");
- return PTR_ERR(pc->reg_gpio);
- }
-
return 0;
}
Doesn't it need an update of the bindings ?
Neil
Thanks, I will update it in next patch
.
Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC
On 2018/12/3 18:06, Neil Armstrong wrote:
On 03/12/2018 10:28, Xingyu Chen wrote:
On 2018/12/3 17:19, Jerome Brunet wrote:
On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
- 223:100 undefined (no interrupt)
- 99:97 3 pins on bank GPIOE
- 96:77 20 pins on bank GPIOX
- 76:61 16 pins on bank GPIOA
- 60:53 8 pins on bank GPIOC
- 52:37 16 pins on bank BOOT
- 36:28 9 pins on bank GPIOH
- 27:12 16 pins on bank GPIOZ
- 11:0 12 pins in the AO domain
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/irqchip/irq-meson-gpio.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
gpio.c
index 7b531fd075b8..971e8dea069a 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
.nr_hwirq = 100,
};
+static const struct meson_gpio_irq_params g12a_params = {
+ .nr_hwirq = 100,
+};
+
Same comment as on i2c, the g12 seems compatible with the axg.
Is this patchset patchset really necessary ?
Although the total number of pins is the same as the Meson-AXG SoC, the gpio
banks and irq numbers are different. To avoid confusion on use, i think the new
compatible string is needed.
OK for the new compatible, but you can re-use the same struct like for i2c.
Neil
Thanks for your comment, I will fix it in the next version.
static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson8-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson8b-gpio-intc", .data = _params
},
{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = _params
},
{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-axg-gpio-intc", .data = _params },
+ { .compatible = "amlogic,meson-g12a-gpio-intc", .data = _params
},
{ }
};
.
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Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC
On 2018/12/3 18:06, Neil Armstrong wrote:
On 03/12/2018 10:28, Xingyu Chen wrote:
On 2018/12/3 17:19, Jerome Brunet wrote:
On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
- 223:100 undefined (no interrupt)
- 99:97 3 pins on bank GPIOE
- 96:77 20 pins on bank GPIOX
- 76:61 16 pins on bank GPIOA
- 60:53 8 pins on bank GPIOC
- 52:37 16 pins on bank BOOT
- 36:28 9 pins on bank GPIOH
- 27:12 16 pins on bank GPIOZ
- 11:0 12 pins in the AO domain
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/irqchip/irq-meson-gpio.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
gpio.c
index 7b531fd075b8..971e8dea069a 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
.nr_hwirq = 100,
};
+static const struct meson_gpio_irq_params g12a_params = {
+ .nr_hwirq = 100,
+};
+
Same comment as on i2c, the g12 seems compatible with the axg.
Is this patchset patchset really necessary ?
Although the total number of pins is the same as the Meson-AXG SoC, the gpio
banks and irq numbers are different. To avoid confusion on use, i think the new
compatible string is needed.
OK for the new compatible, but you can re-use the same struct like for i2c.
Neil
Thanks for your comment, I will fix it in the next version.
static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson8-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson8b-gpio-intc", .data = _params
},
{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = _params
},
{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-axg-gpio-intc", .data = _params },
+ { .compatible = "amlogic,meson-g12a-gpio-intc", .data = _params
},
{ }
};
.
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Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC
On 2018/12/3 17:19, Jerome Brunet wrote:
On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
- 223:100 undefined (no interrupt)
- 99:97 3 pins on bank GPIOE
- 96:77 20 pins on bank GPIOX
- 76:61 16 pins on bank GPIOA
- 60:53 8 pins on bank GPIOC
- 52:37 16 pins on bank BOOT
- 36:28 9 pins on bank GPIOH
- 27:12 16 pins on bank GPIOZ
- 11:012 pins in the AO domain
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/irqchip/irq-meson-gpio.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
gpio.c
index 7b531fd075b8..971e8dea069a 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
.nr_hwirq = 100,
};
+static const struct meson_gpio_irq_params g12a_params = {
+ .nr_hwirq = 100,
+};
+
Same comment as on i2c, the g12 seems compatible with the axg.
Is this patchset patchset really necessary ?
Although the total number of pins is the same as the Meson-AXG SoC, the
gpio banks and irq numbers are different. To avoid confusion on use, i
think the new compatible string is needed.
static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson8-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson8b-gpio-intc", .data = _params
},
{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = _params
},
{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-axg-gpio-intc", .data = _params },
+ { .compatible = "amlogic,meson-g12a-gpio-intc", .data = _params
},
{ }
};
.
Re: [PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC
On 2018/12/3 17:19, Jerome Brunet wrote:
On Mon, 2018-12-03 at 14:13 +0800, Xingyu Chen wrote:
The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
- 223:100 undefined (no interrupt)
- 99:97 3 pins on bank GPIOE
- 96:77 20 pins on bank GPIOX
- 76:61 16 pins on bank GPIOA
- 60:53 8 pins on bank GPIOC
- 52:37 16 pins on bank BOOT
- 36:28 9 pins on bank GPIOH
- 27:12 16 pins on bank GPIOZ
- 11:012 pins in the AO domain
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/irqchip/irq-meson-gpio.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-
gpio.c
index 7b531fd075b8..971e8dea069a 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
.nr_hwirq = 100,
};
+static const struct meson_gpio_irq_params g12a_params = {
+ .nr_hwirq = 100,
+};
+
Same comment as on i2c, the g12 seems compatible with the axg.
Is this patchset patchset really necessary ?
Although the total number of pins is the same as the Meson-AXG SoC, the
gpio banks and irq numbers are different. To avoid confusion on use, i
think the new compatible string is needed.
static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson8-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson8b-gpio-intc", .data = _params
},
{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = _params
},
{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-axg-gpio-intc", .data = _params },
+ { .compatible = "amlogic,meson-g12a-gpio-intc", .data = _params
},
{ }
};
.
[PATCH 1/2] dt-bindings: interrupt-controller: New binding for Meson-G12A SoC
Update the dt-binding document to support new compatible string for the GPIO interrupt controller which found in Amlogic's Meson-G12A SoC. Signed-off-by: Xingyu Chen Signed-off-by: Jianxin Pan --- .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt| 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt index 1502a51548bb..7d531d5fff29 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -15,6 +15,7 @@ Required properties: "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912) "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X) +"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2) - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an -- 2.19.2
[PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC
The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
- 223:100 undefined (no interrupt)
- 99:97 3 pins on bank GPIOE
- 96:77 20 pins on bank GPIOX
- 76:61 16 pins on bank GPIOA
- 60:53 8 pins on bank GPIOC
- 52:37 16 pins on bank BOOT
- 36:28 9 pins on bank GPIOH
- 27:12 16 pins on bank GPIOZ
- 11:012 pins in the AO domain
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/irqchip/irq-meson-gpio.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index 7b531fd075b8..971e8dea069a 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
.nr_hwirq = 100,
};
+static const struct meson_gpio_irq_params g12a_params = {
+ .nr_hwirq = 100,
+};
+
static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson8-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson8b-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-axg-gpio-intc", .data = _params },
+ { .compatible = "amlogic,meson-g12a-gpio-intc", .data = _params },
{ }
};
--
2.19.2
[PATCH 1/2] dt-bindings: interrupt-controller: New binding for Meson-G12A SoC
Update the dt-binding document to support new compatible string for the GPIO interrupt controller which found in Amlogic's Meson-G12A SoC. Signed-off-by: Xingyu Chen Signed-off-by: Jianxin Pan --- .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt| 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt index 1502a51548bb..7d531d5fff29 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -15,6 +15,7 @@ Required properties: "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912) "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X) +"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2) - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an -- 2.19.2
[PATCH 2/2] irqchip/meson-gpio: Add support for Meson-G12A SoC
The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the
other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of:
- 223:100 undefined (no interrupt)
- 99:97 3 pins on bank GPIOE
- 96:77 20 pins on bank GPIOX
- 76:61 16 pins on bank GPIOA
- 60:53 8 pins on bank GPIOC
- 52:37 16 pins on bank BOOT
- 36:28 9 pins on bank GPIOH
- 27:12 16 pins on bank GPIOZ
- 11:012 pins in the AO domain
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/irqchip/irq-meson-gpio.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index 7b531fd075b8..971e8dea069a 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -67,12 +67,17 @@ static const struct meson_gpio_irq_params axg_params = {
.nr_hwirq = 100,
};
+static const struct meson_gpio_irq_params g12a_params = {
+ .nr_hwirq = 100,
+};
+
static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson8-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson8b-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = _params },
{ .compatible = "amlogic,meson-axg-gpio-intc", .data = _params },
+ { .compatible = "amlogic,meson-g12a-gpio-intc", .data = _params },
{ }
};
--
2.19.2
[PATCH 0/2] irqchip/meson-gpio: Add support for Meson-G12A SoC
This series try to add GPIO interrupt controller support for Meson-G12A SoCs. Although the total number of pins is the same as the Meson-AXG SoC, the gpio banks and irq numbers are different. To avoid confusion on use, i think the new compatible string is needed. Xingyu Chen (2): dt-bindings: interrupt-controller: New binding for Meson-G12A SoC irqchip/meson-gpio: Add support for Meson-G12A SoC .../interrupt-controller/amlogic,meson-gpio-intc.txt | 1 + drivers/irqchip/irq-meson-gpio.c | 5 + 2 files changed, 6 insertions(+) -- 2.19.2
[PATCH 0/2] irqchip/meson-gpio: Add support for Meson-G12A SoC
This series try to add GPIO interrupt controller support for Meson-G12A SoCs. Although the total number of pins is the same as the Meson-AXG SoC, the gpio banks and irq numbers are different. To avoid confusion on use, i think the new compatible string is needed. Xingyu Chen (2): dt-bindings: interrupt-controller: New binding for Meson-G12A SoC irqchip/meson-gpio: Add support for Meson-G12A SoC .../interrupt-controller/amlogic,meson-gpio-intc.txt | 1 + drivers/irqchip/irq-meson-gpio.c | 5 + 2 files changed, 6 insertions(+) -- 2.19.2
[PATCH] pinctrl: meson: fix G12A ao pull registers base address
Since Meson G12A SoC, Introduce new ao registers AO_RTI_PULL_UP_EN_REG
and AO_GPIO_O.
These bits of controlling output level are remapped to the new register
AO_GPIO_O, and the AO_GPIO_O_EN_N support only controlling output enable.
These bits of controlling pull enable are remapped to the new register
AO_RTI_PULL_UP_EN_REG, and the AO_RTI_PULL_UP_REG support only controlling
pull type(up/down).
The new layout of ao gpio/pull registers is as follows:
- AO_GPIO_O_EN_N[offset: 0x9 << 2]
- AO_GPIO_I [offset: 0xa << 2]
- AO_RTI_PULL_UP_REG[offset: 0xb << 2]
- AO_RTI_PULL_UP_EN_REG [offset: 0xc << 2]
- AO_GPIO_O [offset: 0xd << 2]
>From above, we can see ao GPIO registers region has been separated by the
ao pull registers. In order to ensure the continuity of the region on
software, the ao GPIO and ao pull registers use the same base address, but
can be identified by the offset.
Fixes: 29ae0952e85f ("pinctrl: meson-g12a: add pinctrl driver support")
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/pinctrl/meson/pinctrl-meson.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c
b/drivers/pinctrl/meson/pinctrl-meson.c
index 53d449076dee..7ff40cd7a0cb 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -31,6 +31,9 @@
* In some cases the register ranges for pull enable and pull
* direction are the same and thus there are only 3 register ranges.
*
+ * Since Meson G12A SoC, the ao register ranges for gpio, pull enable
+ * and pull direction are the same, so there are only 2 register ranges.
+ *
* For the pull and GPIO configuration every bank uses a contiguous
* set of bits in the register sets described above; the same register
* can be shared by more banks with different offsets.
@@ -487,23 +490,22 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl
*pc,
return PTR_ERR(pc->reg_mux);
}
- pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
- if (IS_ERR(pc->reg_pull)) {
- dev_err(pc->dev, "pull registers not found\n");
- return PTR_ERR(pc->reg_pull);
+ pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
+ if (IS_ERR(pc->reg_gpio)) {
+ dev_err(pc->dev, "gpio registers not found\n");
+ return PTR_ERR(pc->reg_gpio);
}
+ pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
+ /* Use gpio region if pull one is not present */
+ if (IS_ERR(pc->reg_pull))
+ pc->reg_pull = pc->reg_gpio;
+
pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
/* Use pull region if pull-enable one is not present */
if (IS_ERR(pc->reg_pullen))
pc->reg_pullen = pc->reg_pull;
- pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
- if (IS_ERR(pc->reg_gpio)) {
- dev_err(pc->dev, "gpio registers not found\n");
- return PTR_ERR(pc->reg_gpio);
- }
-
return 0;
}
--
2.19.2
[PATCH] pinctrl: meson: fix G12A ao pull registers base address
Since Meson G12A SoC, Introduce new ao registers AO_RTI_PULL_UP_EN_REG
and AO_GPIO_O.
These bits of controlling output level are remapped to the new register
AO_GPIO_O, and the AO_GPIO_O_EN_N support only controlling output enable.
These bits of controlling pull enable are remapped to the new register
AO_RTI_PULL_UP_EN_REG, and the AO_RTI_PULL_UP_REG support only controlling
pull type(up/down).
The new layout of ao gpio/pull registers is as follows:
- AO_GPIO_O_EN_N[offset: 0x9 << 2]
- AO_GPIO_I [offset: 0xa << 2]
- AO_RTI_PULL_UP_REG[offset: 0xb << 2]
- AO_RTI_PULL_UP_EN_REG [offset: 0xc << 2]
- AO_GPIO_O [offset: 0xd << 2]
>From above, we can see ao GPIO registers region has been separated by the
ao pull registers. In order to ensure the continuity of the region on
software, the ao GPIO and ao pull registers use the same base address, but
can be identified by the offset.
Fixes: 29ae0952e85f ("pinctrl: meson-g12a: add pinctrl driver support")
Signed-off-by: Xingyu Chen
Signed-off-by: Jianxin Pan
---
drivers/pinctrl/meson/pinctrl-meson.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c
b/drivers/pinctrl/meson/pinctrl-meson.c
index 53d449076dee..7ff40cd7a0cb 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -31,6 +31,9 @@
* In some cases the register ranges for pull enable and pull
* direction are the same and thus there are only 3 register ranges.
*
+ * Since Meson G12A SoC, the ao register ranges for gpio, pull enable
+ * and pull direction are the same, so there are only 2 register ranges.
+ *
* For the pull and GPIO configuration every bank uses a contiguous
* set of bits in the register sets described above; the same register
* can be shared by more banks with different offsets.
@@ -487,23 +490,22 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl
*pc,
return PTR_ERR(pc->reg_mux);
}
- pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
- if (IS_ERR(pc->reg_pull)) {
- dev_err(pc->dev, "pull registers not found\n");
- return PTR_ERR(pc->reg_pull);
+ pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
+ if (IS_ERR(pc->reg_gpio)) {
+ dev_err(pc->dev, "gpio registers not found\n");
+ return PTR_ERR(pc->reg_gpio);
}
+ pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
+ /* Use gpio region if pull one is not present */
+ if (IS_ERR(pc->reg_pull))
+ pc->reg_pull = pc->reg_gpio;
+
pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
/* Use pull region if pull-enable one is not present */
if (IS_ERR(pc->reg_pullen))
pc->reg_pullen = pc->reg_pull;
- pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
- if (IS_ERR(pc->reg_gpio)) {
- dev_err(pc->dev, "gpio registers not found\n");
- return PTR_ERR(pc->reg_gpio);
- }
-
return 0;
}
--
2.19.2
