[PATCH 1/2] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings

[Yixun Lan]

Add dt-bindings headers for the Meson-AXG's AO clock and
reset controller.

CC: <devicet...@vger.kernel.org>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 include/dt-bindings/clock/axg-aoclkc.h | 26 ++
 include/dt-bindings/reset/axg-aoclkc.h | 20 
 2 files changed, 46 insertions(+)
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

diff --git a/include/dt-bindings/clock/axg-aoclkc.h 
b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index ..78683abb4247
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstr...@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE0
+#define CLKID_AO_I2C_MASTER1
+#define CLKID_AO_I2C_SLAVE 2
+#define CLKID_AO_UART1 3
+#define CLKID_AO_UART2 4
+#define CLKID_AO_IR_BLASTER5
+#define CLKID_AO_SAR_ADC   6
+#define CLKID_AO_CLK81 7
+#define CLKID_AO_SAR_ADC_SEL   8
+#define CLKID_AO_SAR_ADC_DIV   9
+#define CLKID_AO_SAR_ADC_CLK   10
+#define CLKID_AO_ALT_XTAL  11
+
+#endif
diff --git a/include/dt-bindings/reset/axg-aoclkc.h 
b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index ..307f58161bbb
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstr...@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE0
+#define RESET_AO_I2C_MASTER1
+#define RESET_AO_I2C_SLAVE 2
+#define RESET_AO_UART1 3
+#define RESET_AO_UART2 4
+#define RESET_AO_IR_BLASTER5
+
+#endif
-- 
2.15.1

[PATCH 1/2] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings

[Yixun Lan]

Add dt-bindings headers for the Meson-AXG's AO clock and
reset controller.

CC: 
Signed-off-by: Yixun Lan 
---
 include/dt-bindings/clock/axg-aoclkc.h | 26 ++
 include/dt-bindings/reset/axg-aoclkc.h | 20 
 2 files changed, 46 insertions(+)
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

diff --git a/include/dt-bindings/clock/axg-aoclkc.h 
b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index ..78683abb4247
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong 
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai 
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE0
+#define CLKID_AO_I2C_MASTER1
+#define CLKID_AO_I2C_SLAVE 2
+#define CLKID_AO_UART1 3
+#define CLKID_AO_UART2 4
+#define CLKID_AO_IR_BLASTER5
+#define CLKID_AO_SAR_ADC   6
+#define CLKID_AO_CLK81 7
+#define CLKID_AO_SAR_ADC_SEL   8
+#define CLKID_AO_SAR_ADC_DIV   9
+#define CLKID_AO_SAR_ADC_CLK   10
+#define CLKID_AO_ALT_XTAL  11
+
+#endif
diff --git a/include/dt-bindings/reset/axg-aoclkc.h 
b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index ..307f58161bbb
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong 
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai 
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE0
+#define RESET_AO_I2C_MASTER1
+#define RESET_AO_I2C_SLAVE 2
+#define RESET_AO_UART1 3
+#define RESET_AO_UART2 4
+#define RESET_AO_IR_BLASTER5
+
+#endif
-- 
2.15.1

[PATCH 0/2] clk: meson-axg: Add AO Cloclk and Reset driver

[Yixun Lan]

  This patch try to add AO clock and Reset driver in Amlogic's
Meson-AXG SoC.

  Please note this patchset actually depend on the clock regmap
conversion series [1].

[1] clk: meson: use regmap in clock controllers
 https://lkml.kernel.org/r/20180131180945.18025-1-jbru...@baylibre.com


Yixun Lan (2):
  dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
  clk: meson-axg: Add AO Clock and Reset controller driver

 drivers/clk/meson/Makefile |   2 +-
 drivers/clk/meson/axg-aoclk.c  | 236 +
 drivers/clk/meson/axg-aoclk.h  |  25 
 include/dt-bindings/clock/axg-aoclkc.h |  26 
 include/dt-bindings/reset/axg-aoclkc.h |  20 +++
 5 files changed, 308 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/meson/axg-aoclk.c
 create mode 100644 drivers/clk/meson/axg-aoclk.h
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

-- 
2.15.1

[PATCH 0/2] clk: meson-axg: Add AO Cloclk and Reset driver

[Yixun Lan]

  This patch try to add AO clock and Reset driver in Amlogic's
Meson-AXG SoC.

  Please note this patchset actually depend on the clock regmap
conversion series [1].

[1] clk: meson: use regmap in clock controllers
 https://lkml.kernel.org/r/20180131180945.18025-1-jbru...@baylibre.com


Yixun Lan (2):
  dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
  clk: meson-axg: Add AO Clock and Reset controller driver

 drivers/clk/meson/Makefile |   2 +-
 drivers/clk/meson/axg-aoclk.c  | 236 +
 drivers/clk/meson/axg-aoclk.h  |  25 
 include/dt-bindings/clock/axg-aoclkc.h |  26 
 include/dt-bindings/reset/axg-aoclkc.h |  20 +++
 5 files changed, 308 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/meson/axg-aoclk.c
 create mode 100644 drivers/clk/meson/axg-aoclk.h
 create mode 100644 include/dt-bindings/clock/axg-aoclkc.h
 create mode 100644 include/dt-bindings/reset/axg-aoclkc.h

-- 
2.15.1

[PATCH 2/2] clk: meson-axg: Add AO Clock and Reset controller driver

[Yixun Lan]

Adds a Clock and Reset controller driver for the Always-On part
of the Amlogic Meson-AXG SoC.

Signed-off-by: Qiufang Dai <qiufang@amlogic.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 drivers/clk/meson/Makefile|   2 +-
 drivers/clk/meson/axg-aoclk.c | 236 ++
 drivers/clk/meson/axg-aoclk.h |  25 +
 3 files changed, 262 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/meson/axg-aoclk.c
 create mode 100644 drivers/clk/meson/axg-aoclk.h

diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 11f99139b844..c7510744406a 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -6,6 +6,6 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o 
clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
-obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o
+obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
 obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)  += clk-regmap.o
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
new file mode 100644
index ..832aa19dd76c
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AmLogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette <mturque...@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang@amlogic.com>
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "clkc.h"
+#include "axg-aoclk.h"
+
+struct axg_aoclk_reset_controller {
+   struct reset_controller_dev reset;
+   unsigned int *data;
+   struct regmap *regmap;
+};
+
+static int axg_aoclk_do_reset(struct reset_controller_dev *rcdev,
+  unsigned long id)
+{
+   struct axg_aoclk_reset_controller *reset =
+   container_of(rcdev, struct axg_aoclk_reset_controller, reset);
+
+   return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
+   BIT(reset->data[id]));
+}
+
+static const struct reset_control_ops axg_aoclk_reset_ops = {
+   .reset = axg_aoclk_do_reset,
+};
+
+#define AXG_AO_GATE(_name, _bit)   \
+static struct clk_regmap _name##_ao = {
\
+   .data = &(struct clk_regmap_gate_data) {\
+   .offset = (AO_RTI_GEN_CNTL_REG0),   \
+   .bit_idx = (_bit),  \
+   },  \
+   .hw.init = &(struct clk_init_data) {\
+   .name = #_name "_ao",   \
+   .ops = _regmap_gate_ops,\
+   .parent_names = (const char *[]){ "clk81" },\
+   .num_parents = 1,   \
+   .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
+   },  \
+}
+
+AXG_AO_GATE(remote, 0);
+AXG_AO_GATE(i2c_master, 1);
+AXG_AO_GATE(i2c_slave, 2);
+AXG_AO_GATE(uart1, 3);
+AXG_AO_GATE(uart2, 5);
+AXG_AO_GATE(ir_blaster, 6);
+AXG_AO_GATE(saradc, 7);
+
+static struct clk_fixed_rate ao_alt_xtal = {
+   .fixed_rate = 32000,
+   .hw.init = &(struct clk_init_data){
+   .name = "ao_alt_xtal",
+   .num_parents = 0,
+   .ops = _fixed_rate_ops,
+   },
+};
+
+static struct clk_regmap ao_clk81 = {
+   .data = &(struct clk_regmap_mux_data) {
+   .offset = AO_RTI_PWR_CNTL_REG0,
+   .mask = 0x1,
+   .shift = 8,
+   },
+   .hw.init = &(struct clk_init_data){
+   .name = "ao_clk81",
+   .ops = _regmap_mux_ro_ops,
+   .parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
+   .num_parents = 2,
+   },
+};
+
+static struct clk_regmap axg_saradc_mux = {
+   .data = &(struct clk_regmap_mux_data) {
+   .offset = AO_SAR_CLK,
+   .mask = 0x3,
+   .shift = 9,
+   },
+   .hw.init = &(struct clk_init_data){
+   .name = "axg_saradc_mux",
+   .ops = _regmap_mux_ops,
+   .parent_names = (const char *[]){ "xtal", "ao_clk81" },
+   .num_parents = 2,
+   },
+};
+
+static struct clk_regmap axg_saradc_div = {
+   .data = &(struct clk_regmap_div_data) 

[PATCH 2/2] clk: meson-axg: Add AO Clock and Reset controller driver

[Yixun Lan]

Adds a Clock and Reset controller driver for the Always-On part
of the Amlogic Meson-AXG SoC.

Signed-off-by: Qiufang Dai 
Signed-off-by: Yixun Lan 
---
 drivers/clk/meson/Makefile|   2 +-
 drivers/clk/meson/axg-aoclk.c | 236 ++
 drivers/clk/meson/axg-aoclk.h |  25 +
 3 files changed, 262 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/meson/axg-aoclk.c
 create mode 100644 drivers/clk/meson/axg-aoclk.h

diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 11f99139b844..c7510744406a 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -6,6 +6,6 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o 
clk-audio-divider.o
 obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o
 obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 obj-$(CONFIG_COMMON_CLK_GXBB)   += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
-obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o
+obj-$(CONFIG_COMMON_CLK_AXG)+= axg.o axg-aoclk.o
 obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
 obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)  += clk-regmap.o
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
new file mode 100644
index ..832aa19dd76c
--- /dev/null
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AmLogic Meson-AXG Clock Controller Driver
+ *
+ * Copyright (c) 2016 Baylibre SAS.
+ * Author: Michael Turquette 
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai 
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "clkc.h"
+#include "axg-aoclk.h"
+
+struct axg_aoclk_reset_controller {
+   struct reset_controller_dev reset;
+   unsigned int *data;
+   struct regmap *regmap;
+};
+
+static int axg_aoclk_do_reset(struct reset_controller_dev *rcdev,
+  unsigned long id)
+{
+   struct axg_aoclk_reset_controller *reset =
+   container_of(rcdev, struct axg_aoclk_reset_controller, reset);
+
+   return regmap_write(reset->regmap, AO_RTI_GEN_CNTL_REG0,
+   BIT(reset->data[id]));
+}
+
+static const struct reset_control_ops axg_aoclk_reset_ops = {
+   .reset = axg_aoclk_do_reset,
+};
+
+#define AXG_AO_GATE(_name, _bit)   \
+static struct clk_regmap _name##_ao = {
\
+   .data = &(struct clk_regmap_gate_data) {\
+   .offset = (AO_RTI_GEN_CNTL_REG0),   \
+   .bit_idx = (_bit),  \
+   },  \
+   .hw.init = &(struct clk_init_data) {\
+   .name = #_name "_ao",   \
+   .ops = _regmap_gate_ops,\
+   .parent_names = (const char *[]){ "clk81" },\
+   .num_parents = 1,   \
+   .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
+   },  \
+}
+
+AXG_AO_GATE(remote, 0);
+AXG_AO_GATE(i2c_master, 1);
+AXG_AO_GATE(i2c_slave, 2);
+AXG_AO_GATE(uart1, 3);
+AXG_AO_GATE(uart2, 5);
+AXG_AO_GATE(ir_blaster, 6);
+AXG_AO_GATE(saradc, 7);
+
+static struct clk_fixed_rate ao_alt_xtal = {
+   .fixed_rate = 32000,
+   .hw.init = &(struct clk_init_data){
+   .name = "ao_alt_xtal",
+   .num_parents = 0,
+   .ops = _fixed_rate_ops,
+   },
+};
+
+static struct clk_regmap ao_clk81 = {
+   .data = &(struct clk_regmap_mux_data) {
+   .offset = AO_RTI_PWR_CNTL_REG0,
+   .mask = 0x1,
+   .shift = 8,
+   },
+   .hw.init = &(struct clk_init_data){
+   .name = "ao_clk81",
+   .ops = _regmap_mux_ro_ops,
+   .parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
+   .num_parents = 2,
+   },
+};
+
+static struct clk_regmap axg_saradc_mux = {
+   .data = &(struct clk_regmap_mux_data) {
+   .offset = AO_SAR_CLK,
+   .mask = 0x3,
+   .shift = 9,
+   },
+   .hw.init = &(struct clk_init_data){
+   .name = "axg_saradc_mux",
+   .ops = _regmap_mux_ops,
+   .parent_names = (const char *[]){ "xtal", "ao_clk81" },
+   .num_parents = 2,
+   },
+};
+
+static struct clk_regmap axg_saradc_div = {
+   .data = &(struct clk_regmap_div_data) {
+   .offset = AO_SAR_CLK,
+   .shift = 0,
+   .width = 8,
+   },
+   .hw.init = &(

Re: [PATCH 05/19] clk: meson: add regmap clocks

[Yixun Lan]

HI Jerome:

On 02/01/18 02:09, Jerome Brunet wrote:
> Meson clock controllers needs to move the classical iomem registers to
> regmap. This is triggered because the HHI controllers found on the GXBB
> and GXL host more than just clocks. To properly handle this, we would
> like to migrate HHI to syscon. Also GXBB AO clock controller already use
> regmap, AXG AO and Audio clock controllers will as well.
> 
> The purpose of this change is to provide a common structure to these
> meson controllers (and possibly others) for regmap based clocks.
> 
> This change provides the basic gate, mux and divider, based on the
> helpers provided by the related generic clocks
> 
> Signed-off-by: Jerome Brunet 
> ---
>  drivers/clk/meson/Kconfig  |   4 +
>  drivers/clk/meson/Makefile |   1 +
>  drivers/clk/meson/clk-regmap.c | 166 
> +
>  drivers/clk/meson/clk-regmap.h | 111 +++
>  4 files changed, 282 insertions(+)
>  create mode 100644 drivers/clk/meson/clk-regmap.c
>  create mode 100644 drivers/clk/meson/clk-regmap.h
> 
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 7694302c70a4..e97e85077da1 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -3,6 +3,10 @@ config COMMON_CLK_AMLOGIC
>   depends on OF
>   depends on ARCH_MESON || COMPILE_TEST
>  
> +config COMMON_CLK_REGMAP_MESON
> + bool
> + select REGMAP
> +
>  config COMMON_CLK_MESON8B
>   bool
>   depends on COMMON_CLK_AMLOGIC
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 3c03ce583798..11a5058a 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o 
> clk-mpll.o clk-audio-div
>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>  obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o 
> gxbb-aoclk-regmap.o gxbb-aoclk-32k.o
>  obj-$(CONFIG_COMMON_CLK_AXG)  += axg.o
> +obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)+= clk-regmap.o
> diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c
> new file mode 100644
> index ..3645fdb62343
> --- /dev/null
> +++ b/drivers/clk/meson/clk-regmap.c
> @@ -0,0 +1,166 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018 BayLibre, SAS.
> +// Author: Jerome Brunet 
> +
> +#include "clk-regmap.h"
> +
> +static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk);
> + int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
> +
> + set ^= enable;
> +
> + return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx),
> +   set ? BIT(gate->bit_idx) : 0);
> +}
> +
> +static int clk_regmap_gate_enable(struct clk_hw *hw)
> +{
> + return clk_regmap_gate_endisable(hw, 1);
> +}
> +
> +static void clk_regmap_gate_disable(struct clk_hw *hw)
> +{
> + clk_regmap_gate_endisable(hw, 0);
> +}
> +
> +static int clk_regmap_gate_is_enabled(struct clk_hw *hw)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk);
> + unsigned int val;
> +
> + regmap_read(clk->map, gate->offset, );
> + if (gate->flags & CLK_GATE_SET_TO_DISABLE)
> + val ^= BIT(gate->bit_idx);
> +
> + val &= BIT(gate->bit_idx);
> +
> + return val ? 1 : 0;
> +}
> +
> +const struct clk_ops clk_regmap_gate_ops = {
> + .enable = clk_regmap_gate_enable,
> + .disable = clk_regmap_gate_disable,
> + .is_enabled = clk_regmap_gate_is_enabled,
> +};
> +EXPORT_SYMBOL_GPL(clk_regmap_gate_ops);
> +
> +static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,
> + unsigned long prate)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
> + unsigned int val;
> + int ret;
> +
> + ret = regmap_read(clk->map, div->offset, );
> + if (ret)
> + /* Gives a hint that something is wrong */
> + return 0;
> +
> + val >>= div->shift;
> + val &= clk_div_mask(div->width);
> + return divider_recalc_rate(hw, prate, val, div->table, div->flags,
> +div->width);
> +}
> +
> +static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
> +   unsigned long *prate)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
> + unsigned int val;
> + int ret;
> +
> + /* if read only, just return current value */
> + if (div->flags & CLK_DIVIDER_READ_ONLY) {
> + ret = regmap_read(clk->map, div->offset, 

Re: [PATCH 05/19] clk: meson: add regmap clocks

[Yixun Lan]

HI Jerome:

On 02/01/18 02:09, Jerome Brunet wrote:
> Meson clock controllers needs to move the classical iomem registers to
> regmap. This is triggered because the HHI controllers found on the GXBB
> and GXL host more than just clocks. To properly handle this, we would
> like to migrate HHI to syscon. Also GXBB AO clock controller already use
> regmap, AXG AO and Audio clock controllers will as well.
> 
> The purpose of this change is to provide a common structure to these
> meson controllers (and possibly others) for regmap based clocks.
> 
> This change provides the basic gate, mux and divider, based on the
> helpers provided by the related generic clocks
> 
> Signed-off-by: Jerome Brunet 
> ---
>  drivers/clk/meson/Kconfig  |   4 +
>  drivers/clk/meson/Makefile |   1 +
>  drivers/clk/meson/clk-regmap.c | 166 
> +
>  drivers/clk/meson/clk-regmap.h | 111 +++
>  4 files changed, 282 insertions(+)
>  create mode 100644 drivers/clk/meson/clk-regmap.c
>  create mode 100644 drivers/clk/meson/clk-regmap.h
> 
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 7694302c70a4..e97e85077da1 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -3,6 +3,10 @@ config COMMON_CLK_AMLOGIC
>   depends on OF
>   depends on ARCH_MESON || COMPILE_TEST
>  
> +config COMMON_CLK_REGMAP_MESON
> + bool
> + select REGMAP
> +
>  config COMMON_CLK_MESON8B
>   bool
>   depends on COMMON_CLK_AMLOGIC
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 3c03ce583798..11a5058a 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o 
> clk-mpll.o clk-audio-div
>  obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
>  obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o 
> gxbb-aoclk-regmap.o gxbb-aoclk-32k.o
>  obj-$(CONFIG_COMMON_CLK_AXG)  += axg.o
> +obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)+= clk-regmap.o
> diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c
> new file mode 100644
> index ..3645fdb62343
> --- /dev/null
> +++ b/drivers/clk/meson/clk-regmap.c
> @@ -0,0 +1,166 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018 BayLibre, SAS.
> +// Author: Jerome Brunet 
> +
> +#include "clk-regmap.h"
> +
> +static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk);
> + int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
> +
> + set ^= enable;
> +
> + return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx),
> +   set ? BIT(gate->bit_idx) : 0);
> +}
> +
> +static int clk_regmap_gate_enable(struct clk_hw *hw)
> +{
> + return clk_regmap_gate_endisable(hw, 1);
> +}
> +
> +static void clk_regmap_gate_disable(struct clk_hw *hw)
> +{
> + clk_regmap_gate_endisable(hw, 0);
> +}
> +
> +static int clk_regmap_gate_is_enabled(struct clk_hw *hw)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk);
> + unsigned int val;
> +
> + regmap_read(clk->map, gate->offset, );
> + if (gate->flags & CLK_GATE_SET_TO_DISABLE)
> + val ^= BIT(gate->bit_idx);
> +
> + val &= BIT(gate->bit_idx);
> +
> + return val ? 1 : 0;
> +}
> +
> +const struct clk_ops clk_regmap_gate_ops = {
> + .enable = clk_regmap_gate_enable,
> + .disable = clk_regmap_gate_disable,
> + .is_enabled = clk_regmap_gate_is_enabled,
> +};
> +EXPORT_SYMBOL_GPL(clk_regmap_gate_ops);
> +
> +static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,
> + unsigned long prate)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
> + unsigned int val;
> + int ret;
> +
> + ret = regmap_read(clk->map, div->offset, );
> + if (ret)
> + /* Gives a hint that something is wrong */
> + return 0;
> +
> + val >>= div->shift;
> + val &= clk_div_mask(div->width);
> + return divider_recalc_rate(hw, prate, val, div->table, div->flags,
> +div->width);
> +}
> +
> +static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
> +   unsigned long *prate)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
> + unsigned int val;
> + int ret;
> +
> + /* if read only, just return current value */
> + if (div->flags & CLK_DIVIDER_READ_ONLY) {
> + ret = regmap_read(clk->map, div->offset, );
> + if (ret)
> + 

Re: [PATCH v3 0/5] ARM64: dts: meson-axg: UART DT updates

[Yixun Lan]

On 01/31/18 08:22, Kevin Hilman wrote:
> On Tue, Jan 30, 2018 at 4:04 PM, Kevin Hilman <khil...@baylibre.com> wrote:
>> Yixun Lan <yixun@amlogic.com> writes:
>>
>>> HI Kevin
>>>  These are the UART DT updates for the Meson-AXG platform.
>>>
>>>  The patch 1 is a general fix.
>>> Other patches are about adding clock & pinctrl info, then using them.
>>> Last patch enable UART_A which connect to a BT module on the S400 board.
>>
>> Applied to v4.16/dt64,
> 
> Oops, I meant v4.17.
> 

Hi Kevin
 I should warn you about the patch 3 [1], it actually depend on the gpio
renaming patch [2]

 I'm still waiting Linus to take patch [2], then update according
(or you could help amend the patch? it's simply a
's/uart_ao_b_gpioz/uart_ao_b_z/g)

Yixun



[1] [PATCH v3 3/5] ARM64: dts: meson-axg: uart: Add the pinctrl info
description

http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006096.html


[2] [PATCH] pinctrl: meson-axg: adjust uart_ao_b pin group naming
http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006201.html

Re: [PATCH v3 0/5] ARM64: dts: meson-axg: UART DT updates

[Yixun Lan]

On 01/31/18 08:22, Kevin Hilman wrote:
> On Tue, Jan 30, 2018 at 4:04 PM, Kevin Hilman  wrote:
>> Yixun Lan  writes:
>>
>>> HI Kevin
>>>  These are the UART DT updates for the Meson-AXG platform.
>>>
>>>  The patch 1 is a general fix.
>>> Other patches are about adding clock & pinctrl info, then using them.
>>> Last patch enable UART_A which connect to a BT module on the S400 board.
>>
>> Applied to v4.16/dt64,
> 
> Oops, I meant v4.17.
> 

Hi Kevin
 I should warn you about the patch 3 [1], it actually depend on the gpio
renaming patch [2]

 I'm still waiting Linus to take patch [2], then update according
(or you could help amend the patch? it's simply a
's/uart_ao_b_gpioz/uart_ao_b_z/g)

Yixun



[1] [PATCH v3 3/5] ARM64: dts: meson-axg: uart: Add the pinctrl info
description

http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006096.html


[2] [PATCH] pinctrl: meson-axg: adjust uart_ao_b pin group naming
http://lists.infradead.org/pipermail/linux-amlogic/2018-January/006201.html

[PATCH] i2c: meson: update doc description to fix build warnings

[Yixun Lan]

Add description for 'data' parameter and drop unused 'irq' memeber.

Here is the warnings:
drivers/i2c/busses/i2c-meson.c:103: warning: No description found for
parameter 'data'
drivers/i2c/busses/i2c-meson.c:103: warning: Excess struct member 'irq'
description in 'meson_i2c'

Suggested-by: Wolfram Sang <w...@the-dreams.de>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 drivers/i2c/busses/i2c-meson.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-meson.c b/drivers/i2c/busses/i2c-meson.c
index 37c4aa76f37a..90f5d0407d73 100644
--- a/drivers/i2c/busses/i2c-meson.c
+++ b/drivers/i2c/busses/i2c-meson.c
@@ -69,7 +69,6 @@ struct meson_i2c_data {
  * @dev:   Pointer to device structure
  * @regs:  Base address of the device memory mapped registers
  * @clk:   Pointer to clock structure
- * @irq:   IRQ number
  * @msg:   Pointer to the current I2C message
  * @state: Current state in the driver state machine
  * @last:  Flag set for the last message in the transfer
@@ -80,6 +79,7 @@ struct meson_i2c_data {
  * @done:  Completion used to wait for transfer termination
  * @tokens:Sequence of tokens to be written to the device
  * @num_tokens:Number of tokens
+ * @data:  Pointer to the controlller's platform data
  */
 struct meson_i2c {
struct i2c_adapter  adap;
-- 
2.15.1

[PATCH] i2c: meson: update doc description to fix build warnings

[Yixun Lan]

Add description for 'data' parameter and drop unused 'irq' memeber.

Here is the warnings:
drivers/i2c/busses/i2c-meson.c:103: warning: No description found for
parameter 'data'
drivers/i2c/busses/i2c-meson.c:103: warning: Excess struct member 'irq'
description in 'meson_i2c'

Suggested-by: Wolfram Sang 
Signed-off-by: Yixun Lan 
---
 drivers/i2c/busses/i2c-meson.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-meson.c b/drivers/i2c/busses/i2c-meson.c
index 37c4aa76f37a..90f5d0407d73 100644
--- a/drivers/i2c/busses/i2c-meson.c
+++ b/drivers/i2c/busses/i2c-meson.c
@@ -69,7 +69,6 @@ struct meson_i2c_data {
  * @dev:   Pointer to device structure
  * @regs:  Base address of the device memory mapped registers
  * @clk:   Pointer to clock structure
- * @irq:   IRQ number
  * @msg:   Pointer to the current I2C message
  * @state: Current state in the driver state machine
  * @last:  Flag set for the last message in the transfer
@@ -80,6 +79,7 @@ struct meson_i2c_data {
  * @done:  Completion used to wait for transfer termination
  * @tokens:Sequence of tokens to be written to the device
  * @num_tokens:Number of tokens
+ * @data:  Pointer to the controlller's platform data
  */
 struct meson_i2c {
struct i2c_adapter  adap;
-- 
2.15.1

Re: [v2,2/5] i2c: meson: add configurable divider factors

[Yixun Lan]

Hi Wolfram：



On 01/24/18 14:28, Wolfram Sang wrote:
> On Mon, Nov 20, 2017 at 10:54:12PM +0800, Yixun Lan wrote:
>> From: Jian Hu <jian...@amlogic.com>
>>
>> This patch try to add support for I2C controller in Meson-AXG SoC,
>> Due to the IP changes between I2C controller, we need to introduce
>> a compatible data to make the divider factor configurable.
>>
>> Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
>> Signed-off-by: Jian Hu <jian...@amlogic.com>
>> Signed-off-by: Yixun Lan <yixun@amlogic.com>
> 
> Applied to for-next, thanks!
> 
> But I got two build warnings, please fix them with an incremental patch:
> 
> drivers/i2c/busses/i2c-meson.c:103: warning: No description found for 
> parameter 'data'
> drivers/i2c/busses/i2c-meson.c:103: warning: Excess struct member 'irq' 
> description in 'meson_i2c'
> 
first, many thanks for pushing this..

I understand from above warnings, and can compose a patch to fix this.

but, I didn't get this build warnings while test locally, so is there
any specific compiler option that I need to pass to?

Yixun

Re: [v2,2/5] i2c: meson: add configurable divider factors

[Yixun Lan]

Hi Wolfram：



On 01/24/18 14:28, Wolfram Sang wrote:
> On Mon, Nov 20, 2017 at 10:54:12PM +0800, Yixun Lan wrote:
>> From: Jian Hu 
>>
>> This patch try to add support for I2C controller in Meson-AXG SoC,
>> Due to the IP changes between I2C controller, we need to introduce
>> a compatible data to make the divider factor configurable.
>>
>> Reviewed-by: Neil Armstrong 
>> Signed-off-by: Jian Hu 
>> Signed-off-by: Yixun Lan 
> 
> Applied to for-next, thanks!
> 
> But I got two build warnings, please fix them with an incremental patch:
> 
> drivers/i2c/busses/i2c-meson.c:103: warning: No description found for 
> parameter 'data'
> drivers/i2c/busses/i2c-meson.c:103: warning: Excess struct member 'irq' 
> description in 'meson_i2c'
> 
first, many thanks for pushing this..

I understand from above warnings, and can compose a patch to fix this.

but, I didn't get this build warnings while test locally, so is there
any specific compiler option that I need to pass to?

Yixun

[PATCH] clk: meson: axg: fix the od shift of the sys_pll

[Yixun Lan]

According to datasheet, the od shift of sys_pll is 16,
fix the typo which introduced at previous commit.

Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers')
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 drivers/clk/meson/axg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 7988dc8506b0..04a231eaf648 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -64,7 +64,7 @@ static struct meson_clk_pll axg_sys_pll = {
},
.od = {
.reg_off = HHI_SYS_PLL_CNTL,
-   .shift   = 10,
+   .shift   = 16,
.width   = 2,
},
.lock = _clk_lock,
-- 
2.15.1

[PATCH] clk: meson: axg: fix the od shift of the sys_pll

[Yixun Lan]

According to datasheet, the od shift of sys_pll is 16,
fix the typo which introduced at previous commit.

Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers')
Signed-off-by: Yixun Lan 
---
 drivers/clk/meson/axg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 7988dc8506b0..04a231eaf648 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -64,7 +64,7 @@ static struct meson_clk_pll axg_sys_pll = {
},
.od = {
.reg_off = HHI_SYS_PLL_CNTL,
-   .shift   = 10,
+   .shift   = 16,
.width   = 2,
},
.lock = _clk_lock,
-- 
2.15.1

Re: [PATCH 3/9] clk: meson: remove unnecessary rounding in the pll clock

[Yixun Lan]

On 01/19/18 02:45, Jerome Brunet wrote:
> The pll driver perform the rate calculation in Mhz, which adds an
> unnecessary rounding down to the Mhz of the rate. Use 64bits long
> integer to perform this calculation safely on meson8b and perform the
> calculation in Hz instead
> 
> Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller")
> Signed-off-by: Jerome Brunet 
> ---
>  drivers/clk/meson/clk-pll.c | 16 
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
> index 2614341fc4ad..fa4cec13d6e8 100644
> --- a/drivers/clk/meson/clk-pll.c
> +++ b/drivers/clk/meson/clk-pll.c
> @@ -51,8 +51,7 @@ static unsigned long meson_clk_pll_recalc_rate(struct 
> clk_hw *hw,
>  {
>   struct meson_clk_pll *pll = to_meson_clk_pll(hw);
>   struct parm *p;
> - unsigned long parent_rate_mhz = parent_rate / 100;
> - unsigned long rate_mhz;
> + u64 rate;
>   u16 n, m, frac = 0, od, od2 = 0;
>   u32 reg;
>  
> @@ -74,17 +73,18 @@ static unsigned long meson_clk_pll_recalc_rate(struct 
> clk_hw *hw,
>   od2 = PARM_GET(p->width, p->shift, reg);
>   }
>  
> + rate = (u64)m * parent_rate;
> +
>   p = >frac;
>   if (p->width) {
>   reg = readl(pll->base + p->reg_off);
>   frac = PARM_GET(p->width, p->shift, reg);
> - rate_mhz = (parent_rate_mhz * m + \
> - (parent_rate_mhz * frac >> 12)) * 2 / n;
> - rate_mhz = rate_mhz >> od >> od2;
> - } else
> - rate_mhz = (parent_rate_mhz * m / n) >> od >> od2;
>  
> - return rate_mhz * 100;
> + rate += (u64)parent_rate * frac >> 12;
> + rate *= 2;
> + }
> +
> + return (rate / n) >> od >> od2;
>  }
>  
>  static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> 

Hi Jerome:
 This is exactly what I want to propose, thanks for pushing this!

 With the whole series, the fixed_pll is more accurate, and the ethernet
driver on axg is capable of choosing fclk_div2..

Yixun

Re: [PATCH 3/9] clk: meson: remove unnecessary rounding in the pll clock

[Yixun Lan]

On 01/19/18 02:45, Jerome Brunet wrote:
> The pll driver perform the rate calculation in Mhz, which adds an
> unnecessary rounding down to the Mhz of the rate. Use 64bits long
> integer to perform this calculation safely on meson8b and perform the
> calculation in Hz instead
> 
> Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller")
> Signed-off-by: Jerome Brunet 
> ---
>  drivers/clk/meson/clk-pll.c | 16 
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
> index 2614341fc4ad..fa4cec13d6e8 100644
> --- a/drivers/clk/meson/clk-pll.c
> +++ b/drivers/clk/meson/clk-pll.c
> @@ -51,8 +51,7 @@ static unsigned long meson_clk_pll_recalc_rate(struct 
> clk_hw *hw,
>  {
>   struct meson_clk_pll *pll = to_meson_clk_pll(hw);
>   struct parm *p;
> - unsigned long parent_rate_mhz = parent_rate / 100;
> - unsigned long rate_mhz;
> + u64 rate;
>   u16 n, m, frac = 0, od, od2 = 0;
>   u32 reg;
>  
> @@ -74,17 +73,18 @@ static unsigned long meson_clk_pll_recalc_rate(struct 
> clk_hw *hw,
>   od2 = PARM_GET(p->width, p->shift, reg);
>   }
>  
> + rate = (u64)m * parent_rate;
> +
>   p = >frac;
>   if (p->width) {
>   reg = readl(pll->base + p->reg_off);
>   frac = PARM_GET(p->width, p->shift, reg);
> - rate_mhz = (parent_rate_mhz * m + \
> - (parent_rate_mhz * frac >> 12)) * 2 / n;
> - rate_mhz = rate_mhz >> od >> od2;
> - } else
> - rate_mhz = (parent_rate_mhz * m / n) >> od >> od2;
>  
> - return rate_mhz * 100;
> + rate += (u64)parent_rate * frac >> 12;
> + rate *= 2;
> + }
> +
> + return (rate / n) >> od >> od2;
>  }
>  
>  static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> 

Hi Jerome:
 This is exactly what I want to propose, thanks for pushing this!

 With the whole series, the fixed_pll is more accurate, and the ethernet
driver on axg is capable of choosing fclk_div2..

Yixun

[PATCH] pinctrl: meson-axg: adjust uart_ao_b pin group naming

[Yixun Lan]

Simply adjust the pin group to _x _y _z style, as to
keep the consistency in DT with previous naming scheme.

Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG 
SoC")
Signed-off-by: Yixun Lan <yixun@amlogic.com>

---
Hi Linus,

 Please also consider merging this patch into 'for-next', since it
fixes issue added in the same cycle.
 This patch will also obsolete previous one patches [1]

[1] pinctrl: meson: use one uniform 'function' name
http://lkml.kernel.org/r/20180108073328.205769-1-yixun@amlogic.com
---
 drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c 
b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index 1fda9d6c7ea3..4b91ff74779b 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -716,7 +716,7 @@ static const char * const uart_b_groups[] = {
"uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x",
 };
 
-static const char * const uart_ao_b_gpioz_groups[] = {
+static const char * const uart_ao_b_z_groups[] = {
"uart_ao_tx_b_z", "uart_ao_rx_b_z",
"uart_ao_cts_b_z", "uart_ao_rts_b_z",
 };
@@ -855,7 +855,7 @@ static struct meson_pmx_func meson_axg_periphs_functions[] 
= {
FUNCTION(nand),
FUNCTION(uart_a),
FUNCTION(uart_b),
-   FUNCTION(uart_ao_b_gpioz),
+   FUNCTION(uart_ao_b_z),
FUNCTION(i2c0),
FUNCTION(i2c1),
FUNCTION(i2c2),
-- 
2.15.1

[PATCH] pinctrl: meson-axg: adjust uart_ao_b pin group naming

[Yixun Lan]

Simply adjust the pin group to _x _y _z style, as to
keep the consistency in DT with previous naming scheme.

Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG 
SoC")
Signed-off-by: Yixun Lan 

---
Hi Linus,

 Please also consider merging this patch into 'for-next', since it
fixes issue added in the same cycle.
 This patch will also obsolete previous one patches [1]

[1] pinctrl: meson: use one uniform 'function' name
http://lkml.kernel.org/r/20180108073328.205769-1-yixun@amlogic.com
---
 drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c 
b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index 1fda9d6c7ea3..4b91ff74779b 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -716,7 +716,7 @@ static const char * const uart_b_groups[] = {
"uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x",
 };
 
-static const char * const uart_ao_b_gpioz_groups[] = {
+static const char * const uart_ao_b_z_groups[] = {
"uart_ao_tx_b_z", "uart_ao_rx_b_z",
"uart_ao_cts_b_z", "uart_ao_rts_b_z",
 };
@@ -855,7 +855,7 @@ static struct meson_pmx_func meson_axg_periphs_functions[] 
= {
FUNCTION(nand),
FUNCTION(uart_a),
FUNCTION(uart_b),
-   FUNCTION(uart_ao_b_gpioz),
+   FUNCTION(uart_ao_b_z),
FUNCTION(i2c0),
FUNCTION(i2c1),
FUNCTION(i2c2),
-- 
2.15.1

Re: [PATCH 0/2] pinctrl: meson: use one uniform 'function' name

[Yixun Lan]

On 01/17/2018 08:14 AM, Kevin Hilman wrote:
> Yixun Lan <yixun@amlogic.com> writes:
> 
>> Hi Jerome:
>>
>> On 01/10/2018 03:28 PM, Jerome Brunet wrote:
>>> On Wed, 2018-01-10 at 10:12 +0800, Yixun Lan wrote:
>>>>
>>>> On 01/08/18 16:52, Jerome Brunet wrote:
>>>>> On Mon, 2018-01-08 at 15:33 +0800, Yixun Lan wrote:
>>>>>> These two patches are general improvement for meson pinctrl driver.
>>>>>> It make the two pinctrl trees (ee/ao) to share one uniform 'function' 
>>>>>> name for
>>>>>> one hardware block even its pin groups live inside two differet hardware 
>>>>>> domains,
>>>>>> which for example EE vs AO domain here.
>>>>>>
>>>>>> This idea is motivated by Martin's question at [1]
>>>>>>
>>>>>> [1]
>>>>>>  
>>>>>> http://lkml.kernel.org/r/CAFBinCCuQ-NK747+GHDkhZty_UMMgzCYOYFcNTrRDJgU8OM=g...@mail.gmail.com
>>>>>>
>>>>>>
>>>>>> Yixun Lan (2):
>>>>>>   pinctrl: meson: introduce a macro to have name/groups seperated
>>>>>>   pinctrl: meson-axg: correct the pin expansion of UART_AO_B
>>>>>>
>>>>>>  drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
>>>>>>  drivers/pinctrl/meson/pinctrl-meson.h | 8 +---
>>>>>>  2 files changed, 7 insertions(+), 5 deletions(-)
>>>>>
>>>>> Hi Yixun,
>>>>>
>>>>> Honestly, I don't like the idea. I think it adds an unnecessary 
>>>>> complexity.
>>>>> I don't see the point of FUNCTION_EX(uart_ao_b, _z) when you could simply 
>>>>> write 
>>>>> FUNCTION(uart_ao_b_z) ... especially when there is just a couple of 
>>>>> function per
>>>>> SoC available on different domains.
>>>>>
>>>>> A pinctrl driver can already be challenging to understand at first, let's 
>>>>> keep
>>>>> it simple and avoid adding more macros.
>>>>>
>>>>
>>>> Hi Jerome：
>>>>   In my opinion, the idea of keeping one uniform 'function' in DT (thus
>>>> introducing another macro) is worth considering. It would make the DT
>>>> part much clean.
>>>
>>> Ok this is your opinion. I don't share it. Keeping function names tidy is 
>>> good,
>>> I don't think we need another macro to do so.
>>>
>>>>   And yes, it's a trade-off here, either we 1) do more in code to make
>>>> DT clean or 2) do nothing in the code level to make DT live with it.
>>>
>>> I don't see how adding a macro doing just string concatenation is going to 
>>> make
>>> anything more clean. It does not prevent one to write FUNCTION_EX(uart_ao_b,
>>> _gpioz), resulting in uart_ao_b_gpioz, which is what is apparently 
>>> considered
>>> 'not clean'
>>>
>> for the benefits of introducing macro 'FUNCTION_EX', it will end with
>>  .name = "uart_ao_b", -> same for both EE, AO domain, and it will match
>> the DT part (although still different for '.groups')
>>
>>
>>> BTW, there no cleanness issue here, the name is just out of the 'usual 
>>> scheme'
>>> but there is no problem with. If you want to change this, and
>>> s/uart_ao_b_gpioz/uart_ao_b_z/, now is the time to change it. 
>>>
>> I'd rather *NOT* to push a pinctrl patch for just changing
>> 'uart_ao_b_gpioz' to 'uart_ao_b_z' (it's a cosmetic change, and still
>> end with two different name - 'uart_ao_b_gpioz/z' & 'uart_ao_b' in DT)
> 
> FWIW, I agree with Jerome.
> 
> Rather than this patch adding a(nother) hard-to-understand macro, please
> submit a pinctrl rename/cleanup to s/uart_ao_b_gpioz/uart_ao_b_z/.
> Since there are not any users of the _gpioz name, now is the time to do
> it.
> 
> We're already using the _x _y _z suffixes all over the place, and IMO,
> adding this new macro would make that even more confusing that it
> already is.
> 
> Kevin
> 

HI Linus
  In this case, please drop this series, and I will send another patch
which simply adjust the pin group name.
  Thanks

Yixun

Re: [PATCH 0/2] pinctrl: meson: use one uniform 'function' name

[Yixun Lan]

On 01/17/2018 08:14 AM, Kevin Hilman wrote:
> Yixun Lan  writes:
> 
>> Hi Jerome:
>>
>> On 01/10/2018 03:28 PM, Jerome Brunet wrote:
>>> On Wed, 2018-01-10 at 10:12 +0800, Yixun Lan wrote:
>>>>
>>>> On 01/08/18 16:52, Jerome Brunet wrote:
>>>>> On Mon, 2018-01-08 at 15:33 +0800, Yixun Lan wrote:
>>>>>> These two patches are general improvement for meson pinctrl driver.
>>>>>> It make the two pinctrl trees (ee/ao) to share one uniform 'function' 
>>>>>> name for
>>>>>> one hardware block even its pin groups live inside two differet hardware 
>>>>>> domains,
>>>>>> which for example EE vs AO domain here.
>>>>>>
>>>>>> This idea is motivated by Martin's question at [1]
>>>>>>
>>>>>> [1]
>>>>>>  
>>>>>> http://lkml.kernel.org/r/CAFBinCCuQ-NK747+GHDkhZty_UMMgzCYOYFcNTrRDJgU8OM=g...@mail.gmail.com
>>>>>>
>>>>>>
>>>>>> Yixun Lan (2):
>>>>>>   pinctrl: meson: introduce a macro to have name/groups seperated
>>>>>>   pinctrl: meson-axg: correct the pin expansion of UART_AO_B
>>>>>>
>>>>>>  drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
>>>>>>  drivers/pinctrl/meson/pinctrl-meson.h | 8 +---
>>>>>>  2 files changed, 7 insertions(+), 5 deletions(-)
>>>>>
>>>>> Hi Yixun,
>>>>>
>>>>> Honestly, I don't like the idea. I think it adds an unnecessary 
>>>>> complexity.
>>>>> I don't see the point of FUNCTION_EX(uart_ao_b, _z) when you could simply 
>>>>> write 
>>>>> FUNCTION(uart_ao_b_z) ... especially when there is just a couple of 
>>>>> function per
>>>>> SoC available on different domains.
>>>>>
>>>>> A pinctrl driver can already be challenging to understand at first, let's 
>>>>> keep
>>>>> it simple and avoid adding more macros.
>>>>>
>>>>
>>>> Hi Jerome：
>>>>   In my opinion, the idea of keeping one uniform 'function' in DT (thus
>>>> introducing another macro) is worth considering. It would make the DT
>>>> part much clean.
>>>
>>> Ok this is your opinion. I don't share it. Keeping function names tidy is 
>>> good,
>>> I don't think we need another macro to do so.
>>>
>>>>   And yes, it's a trade-off here, either we 1) do more in code to make
>>>> DT clean or 2) do nothing in the code level to make DT live with it.
>>>
>>> I don't see how adding a macro doing just string concatenation is going to 
>>> make
>>> anything more clean. It does not prevent one to write FUNCTION_EX(uart_ao_b,
>>> _gpioz), resulting in uart_ao_b_gpioz, which is what is apparently 
>>> considered
>>> 'not clean'
>>>
>> for the benefits of introducing macro 'FUNCTION_EX', it will end with
>>  .name = "uart_ao_b", -> same for both EE, AO domain, and it will match
>> the DT part (although still different for '.groups')
>>
>>
>>> BTW, there no cleanness issue here, the name is just out of the 'usual 
>>> scheme'
>>> but there is no problem with. If you want to change this, and
>>> s/uart_ao_b_gpioz/uart_ao_b_z/, now is the time to change it. 
>>>
>> I'd rather *NOT* to push a pinctrl patch for just changing
>> 'uart_ao_b_gpioz' to 'uart_ao_b_z' (it's a cosmetic change, and still
>> end with two different name - 'uart_ao_b_gpioz/z' & 'uart_ao_b' in DT)
> 
> FWIW, I agree with Jerome.
> 
> Rather than this patch adding a(nother) hard-to-understand macro, please
> submit a pinctrl rename/cleanup to s/uart_ao_b_gpioz/uart_ao_b_z/.
> Since there are not any users of the _gpioz name, now is the time to do
> it.
> 
> We're already using the _x _y _z suffixes all over the place, and IMO,
> adding this new macro would make that even more confusing that it
> already is.
> 
> Kevin
> 

HI Linus
  In this case, please drop this series, and I will send another patch
which simply adjust the pin group name.
  Thanks

Yixun

Re: [PATCH] ARM64: dts: meson-axg: add RMII pins for ethernet controller

[Yixun Lan]

Hi Jerome：

On 01/11/18 16:37, Jerome Brunet wrote:
> On Thu, 2018-01-11 at 11:04 +0800, Yixun Lan wrote:
>> Comparing to RGMII interface, the RMII interface require few pins.
>> So it's worth describing them here.
>>
>> Signed-off-by: Yixun Lan <yixun@amlogic.com>
> 
> The only axg platform we have upstream is the s400 and is using rgmii.
> May I ask how this was tested ?
> 
It's true that S400 using RGMII interface.

but, we have customer using RTL8201FR-VB/VD which is a RMII PHY,

This is actually tested with the 'eth_rmii_x_pins' group.

Yixun

Re: [PATCH] ARM64: dts: meson-axg: add RMII pins for ethernet controller

[Yixun Lan]

Hi Jerome：

On 01/11/18 16:37, Jerome Brunet wrote:
> On Thu, 2018-01-11 at 11:04 +0800, Yixun Lan wrote:
>> Comparing to RGMII interface, the RMII interface require few pins.
>> So it's worth describing them here.
>>
>> Signed-off-by: Yixun Lan 
> 
> The only axg platform we have upstream is the s400 and is using rgmii.
> May I ask how this was tested ?
> 
It's true that S400 using RGMII interface.

but, we have customer using RTL8201FR-VB/VD which is a RMII PHY,

This is actually tested with the 'eth_rmii_x_pins' group.

Yixun

[PATCH] ARM64: dts: meson-axg: add RMII pins for ethernet controller

[Yixun Lan]

Comparing to RGMII interface, the RMII interface require few pins.
So it's worth describing them here.

Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index a80632641b39..ab4a0e8bc446 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -251,6 +251,36 @@
gpio-ranges = <_periphs 0 0 86>;
};
 
+   eth_rmii_x_pins: eth-x-rmii {
+   mux {
+   groups = "eth_mdio_x",
+  "eth_mdc_x",
+  "eth_rgmii_rx_clk_x",
+  "eth_rx_dv_x",
+  "eth_rxd0_x",
+  "eth_rxd1_x",
+  "eth_txen_x",
+  "eth_txd0_x",
+  "eth_txd1_x";
+   function = "eth";
+   };
+   };
+
+   eth_rmii_y_pins: eth-y-rmii {
+   mux {
+   groups = "eth_mdio_y",
+  "eth_mdc_y",
+  "eth_rgmii_rx_clk_y",
+  "eth_rx_dv_y",
+  "eth_rxd0_y",
+  "eth_rxd1_y",
+  "eth_txen_y",
+  "eth_txd0_y",
+  "eth_txd1_y";
+   function = "eth";
+   };
+   };
+
eth_rgmii_x_pins: eth-x-rgmii {
mux {
groups = "eth_mdio_x",
-- 
2.15.1

[PATCH] ARM64: dts: meson-axg: add RMII pins for ethernet controller

[Yixun Lan]

Comparing to RGMII interface, the RMII interface require few pins.
So it's worth describing them here.

Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index a80632641b39..ab4a0e8bc446 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -251,6 +251,36 @@
gpio-ranges = <_periphs 0 0 86>;
};
 
+   eth_rmii_x_pins: eth-x-rmii {
+   mux {
+   groups = "eth_mdio_x",
+  "eth_mdc_x",
+  "eth_rgmii_rx_clk_x",
+  "eth_rx_dv_x",
+  "eth_rxd0_x",
+  "eth_rxd1_x",
+  "eth_txen_x",
+  "eth_txd0_x",
+  "eth_txd1_x";
+   function = "eth";
+   };
+   };
+
+   eth_rmii_y_pins: eth-y-rmii {
+   mux {
+   groups = "eth_mdio_y",
+  "eth_mdc_y",
+  "eth_rgmii_rx_clk_y",
+  "eth_rx_dv_y",
+  "eth_rxd0_y",
+  "eth_rxd1_y",
+  "eth_txen_y",
+  "eth_txd0_y",
+  "eth_txd1_y";
+   function = "eth";
+   };
+   };
+
eth_rgmii_x_pins: eth-x-rgmii {
mux {
groups = "eth_mdio_x",
-- 
2.15.1

[PATCH v3 1/5] ARM64: dts: meson: uart: fix address space range

[Yixun Lan]

The address space range is actually 0x18, fixed here.

Reviewed-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi |  4 ++--
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi  | 10 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index a80632641b39..70c776ef7aa7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -165,14 +165,14 @@
 
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
-   reg = <0x0 0x24000 0x0 0x14>;
+   reg = <0x0 0x24000 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_B: serial@23000 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
-   reg = <0x0 0x23000 0x0 0x14>;
+   reg = <0x0 0x23000 0x0 0x18>;
interrupts = ;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 6cb3c2a52baf..4ee2e7951482 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -235,14 +235,14 @@
 
uart_A: serial@84c0 {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x84c0 0x0 0x14>;
+   reg = <0x0 0x84c0 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_B: serial@84dc {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x84dc 0x0 0x14>;
+   reg = <0x0 0x84dc 0x0 0x18>;
interrupts = ;
status = "disabled";
};
@@ -287,7 +287,7 @@
 
uart_C: serial@8700 {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x8700 0x0 0x14>;
+   reg = <0x0 0x8700 0x0 0x18>;
interrupts = ;
status = "disabled";
};
@@ -404,14 +404,14 @@
 
uart_AO: serial@4c0 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-ao-uart";
-   reg = <0x0 0x004c0 0x0 0x14>;
+   reg = <0x0 0x004c0 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_AO_B: serial@4e0 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-ao-uart";
-   reg = <0x0 0x004e0 0x0 0x14>;
+   reg = <0x0 0x004e0 0x0 0x18>;
interrupts = ;
status = "disabled";
};
-- 
2.15.1

[PATCH v3 5/5] ARM64: dts: meson-axg: enable the UART_A controller

[Yixun Lan]

The UART_A is connected to a BT module on the S400 board.

Acked-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 9c1b78028ccb..d56894dbb209 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -14,6 +14,7 @@
 
aliases {
serial0 = _AO;
+   serial1 = _A;
};
 };
 
@@ -24,6 +25,12 @@
pinctrl-names = "default";
 };
 
+_A {
+   status = "okay";
+   pinctrl-0 = <_a_pins>;
+   pinctrl-names = "default";
+};
+
 _AO {
status = "okay";
pinctrl-0 = <_ao_a_pins>;
-- 
2.15.1

[PATCH v3 1/5] ARM64: dts: meson: uart: fix address space range

[Yixun Lan]

The address space range is actually 0x18, fixed here.

Reviewed-by: Jerome Brunet 
Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi |  4 ++--
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi  | 10 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index a80632641b39..70c776ef7aa7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -165,14 +165,14 @@
 
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
-   reg = <0x0 0x24000 0x0 0x14>;
+   reg = <0x0 0x24000 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_B: serial@23000 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
-   reg = <0x0 0x23000 0x0 0x14>;
+   reg = <0x0 0x23000 0x0 0x18>;
interrupts = ;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 6cb3c2a52baf..4ee2e7951482 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -235,14 +235,14 @@
 
uart_A: serial@84c0 {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x84c0 0x0 0x14>;
+   reg = <0x0 0x84c0 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_B: serial@84dc {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x84dc 0x0 0x14>;
+   reg = <0x0 0x84dc 0x0 0x18>;
interrupts = ;
status = "disabled";
};
@@ -287,7 +287,7 @@
 
uart_C: serial@8700 {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x8700 0x0 0x14>;
+   reg = <0x0 0x8700 0x0 0x18>;
interrupts = ;
status = "disabled";
};
@@ -404,14 +404,14 @@
 
uart_AO: serial@4c0 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-ao-uart";
-   reg = <0x0 0x004c0 0x0 0x14>;
+   reg = <0x0 0x004c0 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_AO_B: serial@4e0 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-ao-uart";
-   reg = <0x0 0x004e0 0x0 0x14>;
+   reg = <0x0 0x004e0 0x0 0x18>;
interrupts = ;
status = "disabled";
};
-- 
2.15.1

[PATCH v3 5/5] ARM64: dts: meson-axg: enable the UART_A controller

[Yixun Lan]

The UART_A is connected to a BT module on the S400 board.

Acked-by: Jerome Brunet 
Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 9c1b78028ccb..d56894dbb209 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -14,6 +14,7 @@
 
aliases {
serial0 = _AO;
+   serial1 = _A;
};
 };
 
@@ -24,6 +25,12 @@
pinctrl-names = "default";
 };
 
+_A {
+   status = "okay";
+   pinctrl-0 = <_a_pins>;
+   pinctrl-names = "default";
+};
+
 _AO {
status = "okay";
pinctrl-0 = <_ao_a_pins>;
-- 
2.15.1

[PATCH v3 0/5] ARM64: dts: meson-axg: UART DT updates

[Yixun Lan]

HI Kevin
 These are the UART DT updates for the Meson-AXG platform.

 The patch 1 is a general fix.
Other patches are about adding clock & pinctrl info, then using them.
Last patch enable UART_A which connect to a BT module on the S400 board.

Note: 
This series depend on previous UART_AO clock switch patch[1]
also, these patch request clocks, so they need the
tag:meson-clk-for-v4.16-2 from clk-meson's tree in order to compile.

Changes since v2 at [3]:
  -- add Jerome's Reviewed-by to patch 1
  -- adjust commit message, drop snip of code
  -- drop extra blank line

Changes since v1 at [2]:
  -- fix address range for all platform
  -- squash patch 1, 3 (drop compatible & add clock)
  -- fix typo in pinctrl info
  -- add Jerome's Ack

[3]
 http://lkml.kernel.org/r/20180106001044.108163-1-yixun@amlogic.com

[2]
 http://lkml.kernel.org/r/20180105095621.196472-1-yixun@amlogic.com

[1] 
 http://lkml.kernel.org/r/20171215141741.175985-1-yixun@amlogic.com


Yixun Lan (5):
  ARM64: dts: meson: uart: fix address space range
  ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART
  ARM64: dts: meson-axg: uart: Add the pinctrl info description
  ARM64: dts: meson-axg: complete the pinctrl info for UART_AO_A
  ARM64: dts: meson-axg: enable the UART_A controller

 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |   9 +++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 108 -
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi  |  10 +--
 3 files changed, 118 insertions(+), 9 deletions(-)

-- 
2.15.1

[PATCH v3 2/5] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

When update the clock info for the UART controller in the EE domain,
the driver explicitly require 'pclk' in order to work properly.

With current logic of the code, the driver will go for the legacy clock probe
routine if it find current compatible string match to 'amlogic,meson-uart',
which result in not requesting the 'pclk' clock, thus break the driver in the 
end.

Acked-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 70c776ef7aa7..644d0f9eaf8c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -164,17 +164,21 @@
};
 
uart_A: serial@24000 {
-   compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
+   compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x24000 0x0 0x18>;
interrupts = ;
status = "disabled";
+   clocks = <>, < CLKID_UART0>, <>;
+   clock-names = "xtal", "pclk", "baud";
};
 
uart_B: serial@23000 {
-   compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
+   compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x23000 0x0 0x18>;
interrupts = ;
status = "disabled";
+   clocks = <>, < CLKID_UART1>, <>;
+   clock-names = "xtal", "pclk", "baud";
};
};
 
-- 
2.15.1

[PATCH v3 3/5] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

Describe the pinctrl info for the UART controller which is found
in the Meson-AXG SoCs.

Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++
 1 file changed, 96 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 644d0f9eaf8c..6cd28045e89c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -448,6 +448,70 @@
function = "spi1";
};
};
+
+   uart_a_pins: uart_a {
+   mux {
+   groups = "uart_tx_a",
+   "uart_rx_a";
+   function = "uart_a";
+   };
+   };
+
+   uart_a_cts_rts_pins: uart_a_cts_rts {
+   mux {
+   groups = "uart_cts_a",
+   "uart_rts_a";
+   function = "uart_a";
+   };
+   };
+
+   uart_b_x_pins: uart_b_x {
+   mux {
+   groups = "uart_tx_b_x",
+   "uart_rx_b_x";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+   mux {
+   groups = "uart_cts_b_x",
+   "uart_rts_b_x";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_z_pins: uart_b_z {
+   mux {
+   groups = "uart_tx_b_z",
+   "uart_rx_b_z";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+   mux {
+   groups = "uart_cts_b_z",
+   "uart_rts_b_z";
+   function = "uart_b";
+   };
+   };
+
+   uart_ao_b_z_pins: uart_ao_b_z {
+   mux {
+   groups = "uart_ao_tx_b_z",
+   "uart_ao_rx_b_z";
+   function = "uart_ao_b_gpioz";
+   };
+   };
+
+   uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+   mux {
+   groups = "uart_ao_cts_b_z",
+   "uart_ao_rts_b_z";
+   function = "uart_ao_b_gpioz";
+   };
+   };
};
};
 
@@ -498,6 +562,38 @@
function = "remote_input_ao";
};
};
+
+   uart_ao_a_pins: uart_ao_a {
+   mux {
+   groups = "uart_ao_tx_a",
+   "uart_ao_rx_a";
+   function = "uart_ao_a";
+   };
+   };
+
+   uart_ao_a_

[PATCH v3 0/5] ARM64: dts: meson-axg: UART DT updates

[Yixun Lan]

HI Kevin
 These are the UART DT updates for the Meson-AXG platform.

 The patch 1 is a general fix.
Other patches are about adding clock & pinctrl info, then using them.
Last patch enable UART_A which connect to a BT module on the S400 board.

Note: 
This series depend on previous UART_AO clock switch patch[1]
also, these patch request clocks, so they need the
tag:meson-clk-for-v4.16-2 from clk-meson's tree in order to compile.

Changes since v2 at [3]:
  -- add Jerome's Reviewed-by to patch 1
  -- adjust commit message, drop snip of code
  -- drop extra blank line

Changes since v1 at [2]:
  -- fix address range for all platform
  -- squash patch 1, 3 (drop compatible & add clock)
  -- fix typo in pinctrl info
  -- add Jerome's Ack

[3]
 http://lkml.kernel.org/r/20180106001044.108163-1-yixun@amlogic.com

[2]
 http://lkml.kernel.org/r/20180105095621.196472-1-yixun@amlogic.com

[1] 
 http://lkml.kernel.org/r/20171215141741.175985-1-yixun@amlogic.com


Yixun Lan (5):
  ARM64: dts: meson: uart: fix address space range
  ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART
  ARM64: dts: meson-axg: uart: Add the pinctrl info description
  ARM64: dts: meson-axg: complete the pinctrl info for UART_AO_A
  ARM64: dts: meson-axg: enable the UART_A controller

 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |   9 +++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 108 -
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi  |  10 +--
 3 files changed, 118 insertions(+), 9 deletions(-)

-- 
2.15.1

[PATCH v3 2/5] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

When update the clock info for the UART controller in the EE domain,
the driver explicitly require 'pclk' in order to work properly.

With current logic of the code, the driver will go for the legacy clock probe
routine if it find current compatible string match to 'amlogic,meson-uart',
which result in not requesting the 'pclk' clock, thus break the driver in the 
end.

Acked-by: Jerome Brunet 
Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 70c776ef7aa7..644d0f9eaf8c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -164,17 +164,21 @@
};
 
uart_A: serial@24000 {
-   compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
+   compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x24000 0x0 0x18>;
interrupts = ;
status = "disabled";
+   clocks = <>, < CLKID_UART0>, <>;
+   clock-names = "xtal", "pclk", "baud";
};
 
uart_B: serial@23000 {
-   compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
+   compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x23000 0x0 0x18>;
interrupts = ;
status = "disabled";
+   clocks = <>, < CLKID_UART1>, <>;
+   clock-names = "xtal", "pclk", "baud";
};
};
 
-- 
2.15.1

[PATCH v3 3/5] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

Describe the pinctrl info for the UART controller which is found
in the Meson-AXG SoCs.

Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++
 1 file changed, 96 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 644d0f9eaf8c..6cd28045e89c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -448,6 +448,70 @@
function = "spi1";
};
};
+
+   uart_a_pins: uart_a {
+   mux {
+   groups = "uart_tx_a",
+   "uart_rx_a";
+   function = "uart_a";
+   };
+   };
+
+   uart_a_cts_rts_pins: uart_a_cts_rts {
+   mux {
+   groups = "uart_cts_a",
+   "uart_rts_a";
+   function = "uart_a";
+   };
+   };
+
+   uart_b_x_pins: uart_b_x {
+   mux {
+   groups = "uart_tx_b_x",
+   "uart_rx_b_x";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+   mux {
+   groups = "uart_cts_b_x",
+   "uart_rts_b_x";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_z_pins: uart_b_z {
+   mux {
+   groups = "uart_tx_b_z",
+   "uart_rx_b_z";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+   mux {
+   groups = "uart_cts_b_z",
+   "uart_rts_b_z";
+   function = "uart_b";
+   };
+   };
+
+   uart_ao_b_z_pins: uart_ao_b_z {
+   mux {
+   groups = "uart_ao_tx_b_z",
+   "uart_ao_rx_b_z";
+   function = "uart_ao_b_gpioz";
+   };
+   };
+
+   uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+   mux {
+   groups = "uart_ao_cts_b_z",
+   "uart_ao_rts_b_z";
+   function = "uart_ao_b_gpioz";
+   };
+   };
};
};
 
@@ -498,6 +562,38 @@
function = "remote_input_ao";
};
};
+
+   uart_ao_a_pins: uart_ao_a {
+   mux {
+   groups = "uart_ao_tx_a",
+   "uart_ao_rx_a";
+   function = "uart_ao_a";
+   };
+   };
+
+   uart_ao_a_cts_rt

[PATCH v3 4/5] ARM64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Yixun Lan]

Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we may need to rely on bootloader for the initialization.

Acked-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 447b98d30921..9c1b78028ccb 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -26,6 +26,8 @@
 
 _AO {
status = "okay";
+   pinctrl-0 = <_ao_a_pins>;
+   pinctrl-names = "default";
 };
 
  {
-- 
2.15.1

[PATCH v3 4/5] ARM64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Yixun Lan]

Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we may need to rely on bootloader for the initialization.

Acked-by: Jerome Brunet 
Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 447b98d30921..9c1b78028ccb 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -26,6 +26,8 @@
 
 _AO {
status = "okay";
+   pinctrl-0 = <_ao_a_pins>;
+   pinctrl-names = "default";
 };
 
  {
-- 
2.15.1

Re: [PATCH 0/2] pinctrl: meson: use one uniform 'function' name

[Yixun Lan]

Hi Jerome:

On 01/10/2018 03:28 PM, Jerome Brunet wrote:
> On Wed, 2018-01-10 at 10:12 +0800, Yixun Lan wrote:
>>
>> On 01/08/18 16:52, Jerome Brunet wrote:
>>> On Mon, 2018-01-08 at 15:33 +0800, Yixun Lan wrote:
>>>> These two patches are general improvement for meson pinctrl driver.
>>>> It make the two pinctrl trees (ee/ao) to share one uniform 'function' name 
>>>> for
>>>> one hardware block even its pin groups live inside two differet hardware 
>>>> domains,
>>>> which for example EE vs AO domain here.
>>>>
>>>> This idea is motivated by Martin's question at [1]
>>>>
>>>> [1]
>>>>  
>>>> http://lkml.kernel.org/r/CAFBinCCuQ-NK747+GHDkhZty_UMMgzCYOYFcNTrRDJgU8OM=g...@mail.gmail.com
>>>>
>>>>
>>>> Yixun Lan (2):
>>>>   pinctrl: meson: introduce a macro to have name/groups seperated
>>>>   pinctrl: meson-axg: correct the pin expansion of UART_AO_B
>>>>
>>>>  drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
>>>>  drivers/pinctrl/meson/pinctrl-meson.h | 8 +---
>>>>  2 files changed, 7 insertions(+), 5 deletions(-)
>>>
>>> Hi Yixun,
>>>
>>> Honestly, I don't like the idea. I think it adds an unnecessary complexity.
>>> I don't see the point of FUNCTION_EX(uart_ao_b, _z) when you could simply 
>>> write 
>>> FUNCTION(uart_ao_b_z) ... especially when there is just a couple of 
>>> function per
>>> SoC available on different domains.
>>>
>>> A pinctrl driver can already be challenging to understand at first, let's 
>>> keep
>>> it simple and avoid adding more macros.
>>>
>>
>> Hi Jerome：
>>   In my opinion, the idea of keeping one uniform 'function' in DT (thus
>> introducing another macro) is worth considering. It would make the DT
>> part much clean.
> 
> Ok this is your opinion. I don't share it. Keeping function names tidy is 
> good,
> I don't think we need another macro to do so.
> 
>>   And yes, it's a trade-off here, either we 1) do more in code to make
>> DT clean or 2) do nothing in the code level to make DT live with it.
> 
> I don't see how adding a macro doing just string concatenation is going to 
> make
> anything more clean. It does not prevent one to write FUNCTION_EX(uart_ao_b,
> _gpioz), resulting in uart_ao_b_gpioz, which is what is apparently considered
> 'not clean'
> 
for the benefits of introducing macro 'FUNCTION_EX', it will end with
 .name = "uart_ao_b", -> same for both EE, AO domain, and it will match
the DT part (although still different for '.groups')


> BTW, there no cleanness issue here, the name is just out of the 'usual scheme'
> but there is no problem with. If you want to change this, and
> s/uart_ao_b_gpioz/uart_ao_b_z/, now is the time to change it. 
> 
I'd rather *NOT* to push a pinctrl patch for just changing
'uart_ao_b_gpioz' to 'uart_ao_b_z' (it's a cosmetic change, and still
end with two different name - 'uart_ao_b_gpioz/z' & 'uart_ao_b' in DT)

>>
>> Yixun
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-gpio" in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 
> ___
> linux-amlogic mailing list
> linux-amlo...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
> 

Re: [PATCH 0/2] pinctrl: meson: use one uniform 'function' name

[Yixun Lan]

Hi Jerome:

On 01/10/2018 03:28 PM, Jerome Brunet wrote:
> On Wed, 2018-01-10 at 10:12 +0800, Yixun Lan wrote:
>>
>> On 01/08/18 16:52, Jerome Brunet wrote:
>>> On Mon, 2018-01-08 at 15:33 +0800, Yixun Lan wrote:
>>>> These two patches are general improvement for meson pinctrl driver.
>>>> It make the two pinctrl trees (ee/ao) to share one uniform 'function' name 
>>>> for
>>>> one hardware block even its pin groups live inside two differet hardware 
>>>> domains,
>>>> which for example EE vs AO domain here.
>>>>
>>>> This idea is motivated by Martin's question at [1]
>>>>
>>>> [1]
>>>>  
>>>> http://lkml.kernel.org/r/CAFBinCCuQ-NK747+GHDkhZty_UMMgzCYOYFcNTrRDJgU8OM=g...@mail.gmail.com
>>>>
>>>>
>>>> Yixun Lan (2):
>>>>   pinctrl: meson: introduce a macro to have name/groups seperated
>>>>   pinctrl: meson-axg: correct the pin expansion of UART_AO_B
>>>>
>>>>  drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
>>>>  drivers/pinctrl/meson/pinctrl-meson.h | 8 +---
>>>>  2 files changed, 7 insertions(+), 5 deletions(-)
>>>
>>> Hi Yixun,
>>>
>>> Honestly, I don't like the idea. I think it adds an unnecessary complexity.
>>> I don't see the point of FUNCTION_EX(uart_ao_b, _z) when you could simply 
>>> write 
>>> FUNCTION(uart_ao_b_z) ... especially when there is just a couple of 
>>> function per
>>> SoC available on different domains.
>>>
>>> A pinctrl driver can already be challenging to understand at first, let's 
>>> keep
>>> it simple and avoid adding more macros.
>>>
>>
>> Hi Jerome：
>>   In my opinion, the idea of keeping one uniform 'function' in DT (thus
>> introducing another macro) is worth considering. It would make the DT
>> part much clean.
> 
> Ok this is your opinion. I don't share it. Keeping function names tidy is 
> good,
> I don't think we need another macro to do so.
> 
>>   And yes, it's a trade-off here, either we 1) do more in code to make
>> DT clean or 2) do nothing in the code level to make DT live with it.
> 
> I don't see how adding a macro doing just string concatenation is going to 
> make
> anything more clean. It does not prevent one to write FUNCTION_EX(uart_ao_b,
> _gpioz), resulting in uart_ao_b_gpioz, which is what is apparently considered
> 'not clean'
> 
for the benefits of introducing macro 'FUNCTION_EX', it will end with
 .name = "uart_ao_b", -> same for both EE, AO domain, and it will match
the DT part (although still different for '.groups')


> BTW, there no cleanness issue here, the name is just out of the 'usual scheme'
> but there is no problem with. If you want to change this, and
> s/uart_ao_b_gpioz/uart_ao_b_z/, now is the time to change it. 
> 
I'd rather *NOT* to push a pinctrl patch for just changing
'uart_ao_b_gpioz' to 'uart_ao_b_z' (it's a cosmetic change, and still
end with two different name - 'uart_ao_b_gpioz/z' & 'uart_ao_b' in DT)

>>
>> Yixun
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-gpio" in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 
> ___
> linux-amlogic mailing list
> linux-amlo...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
> 

Re: [PATCH 0/2] pinctrl: meson: use one uniform 'function' name

[Yixun Lan]

On 01/08/18 16:52, Jerome Brunet wrote:
> On Mon, 2018-01-08 at 15:33 +0800, Yixun Lan wrote:
>> These two patches are general improvement for meson pinctrl driver.
>> It make the two pinctrl trees (ee/ao) to share one uniform 'function' name 
>> for
>> one hardware block even its pin groups live inside two differet hardware 
>> domains,
>> which for example EE vs AO domain here.
>>
>> This idea is motivated by Martin's question at [1]
>>
>> [1]
>>  
>> http://lkml.kernel.org/r/CAFBinCCuQ-NK747+GHDkhZty_UMMgzCYOYFcNTrRDJgU8OM=g...@mail.gmail.com
>>
>>
>> Yixun Lan (2):
>>   pinctrl: meson: introduce a macro to have name/groups seperated
>>   pinctrl: meson-axg: correct the pin expansion of UART_AO_B
>>
>>  drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
>>  drivers/pinctrl/meson/pinctrl-meson.h | 8 +---
>>  2 files changed, 7 insertions(+), 5 deletions(-)
> 
> Hi Yixun,
> 
> Honestly, I don't like the idea. I think it adds an unnecessary complexity.
> I don't see the point of FUNCTION_EX(uart_ao_b, _z) when you could simply 
> write 
> FUNCTION(uart_ao_b_z) ... especially when there is just a couple of function 
> per
> SoC available on different domains.
> 
> A pinctrl driver can already be challenging to understand at first, let's keep
> it simple and avoid adding more macros.
> 

Hi Jerome：
  In my opinion, the idea of keeping one uniform 'function' in DT (thus
introducing another macro) is worth considering. It would make the DT
part much clean.
  And yes, it's a trade-off here, either we 1) do more in code to make
DT clean or 2) do nothing in the code level to make DT live with it.

Yixun

Re: [PATCH 0/2] pinctrl: meson: use one uniform 'function' name

[Yixun Lan]

On 01/08/18 16:52, Jerome Brunet wrote:
> On Mon, 2018-01-08 at 15:33 +0800, Yixun Lan wrote:
>> These two patches are general improvement for meson pinctrl driver.
>> It make the two pinctrl trees (ee/ao) to share one uniform 'function' name 
>> for
>> one hardware block even its pin groups live inside two differet hardware 
>> domains,
>> which for example EE vs AO domain here.
>>
>> This idea is motivated by Martin's question at [1]
>>
>> [1]
>>  
>> http://lkml.kernel.org/r/CAFBinCCuQ-NK747+GHDkhZty_UMMgzCYOYFcNTrRDJgU8OM=g...@mail.gmail.com
>>
>>
>> Yixun Lan (2):
>>   pinctrl: meson: introduce a macro to have name/groups seperated
>>   pinctrl: meson-axg: correct the pin expansion of UART_AO_B
>>
>>  drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
>>  drivers/pinctrl/meson/pinctrl-meson.h | 8 +---
>>  2 files changed, 7 insertions(+), 5 deletions(-)
> 
> Hi Yixun,
> 
> Honestly, I don't like the idea. I think it adds an unnecessary complexity.
> I don't see the point of FUNCTION_EX(uart_ao_b, _z) when you could simply 
> write 
> FUNCTION(uart_ao_b_z) ... especially when there is just a couple of function 
> per
> SoC available on different domains.
> 
> A pinctrl driver can already be challenging to understand at first, let's keep
> it simple and avoid adding more macros.
> 

Hi Jerome：
  In my opinion, the idea of keeping one uniform 'function' in DT (thus
introducing another macro) is worth considering. It would make the DT
part much clean.
  And yes, it's a trade-off here, either we 1) do more in code to make
DT clean or 2) do nothing in the code level to make DT live with it.

Yixun

[PATCH 0/2] pinctrl: meson: use one uniform 'function' name

[Yixun Lan]

These two patches are general improvement for meson pinctrl driver.
It make the two pinctrl trees (ee/ao) to share one uniform 'function' name for
one hardware block even its pin groups live inside two differet hardware 
domains,
which for example EE vs AO domain here.

This idea is motivated by Martin's question at [1]

[1]
 
http://lkml.kernel.org/r/CAFBinCCuQ-NK747+GHDkhZty_UMMgzCYOYFcNTrRDJgU8OM=g...@mail.gmail.com


Yixun Lan (2):
  pinctrl: meson: introduce a macro to have name/groups seperated
  pinctrl: meson-axg: correct the pin expansion of UART_AO_B

 drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
 drivers/pinctrl/meson/pinctrl-meson.h | 8 +---
 2 files changed, 7 insertions(+), 5 deletions(-)

-- 
2.15.1

[PATCH 0/2] pinctrl: meson: use one uniform 'function' name

[Yixun Lan]

These two patches are general improvement for meson pinctrl driver.
It make the two pinctrl trees (ee/ao) to share one uniform 'function' name for
one hardware block even its pin groups live inside two differet hardware 
domains,
which for example EE vs AO domain here.

This idea is motivated by Martin's question at [1]

[1]
 
http://lkml.kernel.org/r/CAFBinCCuQ-NK747+GHDkhZty_UMMgzCYOYFcNTrRDJgU8OM=g...@mail.gmail.com


Yixun Lan (2):
  pinctrl: meson: introduce a macro to have name/groups seperated
  pinctrl: meson-axg: correct the pin expansion of UART_AO_B

 drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
 drivers/pinctrl/meson/pinctrl-meson.h | 8 +---
 2 files changed, 7 insertions(+), 5 deletions(-)

-- 
2.15.1

[PATCH 1/2] pinctrl: meson: introduce a macro to have name/groups seperated

[Yixun Lan]

We introduce a macro FUNCTION_EX here, the main motivation is
trying to have the possibility to expand the macro with the same of the
'.name' number but different multiple '.groups/.num_groups' numbers.

With this change, the meson pinctrl drivr is capable of have one uniform
'function' name but with different pin 'groups', as we face the sitiuation
that two pin groups may live inside different hardware domain (EE vs AO domain),
which mean we couldn't put them in one single group.

Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 drivers/pinctrl/meson/pinctrl-meson.h | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson.h 
b/drivers/pinctrl/meson/pinctrl-meson.h
index 12a391109329..d8f705098810 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -124,13 +124,15 @@ struct meson_pinctrl {
struct device_node *of_node;
 };
 
-#define FUNCTION(fn)   \
+#define FUNCTION_EX(fn, ex)\
{   \
.name = #fn,\
-   .groups = fn ## _groups,\
-   .num_groups = ARRAY_SIZE(fn ## _groups),\
+   .groups = fn ## ex ## _groups,  \
+   .num_groups = ARRAY_SIZE(fn ## ex ## _groups),  \
}
 
+#define FUNCTION(fn)   FUNCTION_EX(fn, )
+
 #define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib)
\
{   \
.name   = n,\
-- 
2.15.1

[PATCH 1/2] pinctrl: meson: introduce a macro to have name/groups seperated

[Yixun Lan]

We introduce a macro FUNCTION_EX here, the main motivation is
trying to have the possibility to expand the macro with the same of the
'.name' number but different multiple '.groups/.num_groups' numbers.

With this change, the meson pinctrl drivr is capable of have one uniform
'function' name but with different pin 'groups', as we face the sitiuation
that two pin groups may live inside different hardware domain (EE vs AO domain),
which mean we couldn't put them in one single group.

Signed-off-by: Yixun Lan 
---
 drivers/pinctrl/meson/pinctrl-meson.h | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson.h 
b/drivers/pinctrl/meson/pinctrl-meson.h
index 12a391109329..d8f705098810 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -124,13 +124,15 @@ struct meson_pinctrl {
struct device_node *of_node;
 };
 
-#define FUNCTION(fn)   \
+#define FUNCTION_EX(fn, ex)\
{   \
.name = #fn,\
-   .groups = fn ## _groups,\
-   .num_groups = ARRAY_SIZE(fn ## _groups),\
+   .groups = fn ## ex ## _groups,  \
+   .num_groups = ARRAY_SIZE(fn ## ex ## _groups),  \
}
 
+#define FUNCTION(fn)   FUNCTION_EX(fn, )
+
 #define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib)
\
{   \
.name   = n,\
-- 
2.15.1

[PATCH 2/2] pinctrl: meson-axg: correct the pin expansion of UART_AO_B

[Yixun Lan]

The 'uart_ao_b_groups' for the UART_AO_B pins is already defined which is
living inside the AO domain, for these pins which are routed out from EE domain,
we need to correct them with the 'FUNCTION_EX' macro, otherwise there is
a conflict in the code level.

Also slightly adjust the name to make it short and more consistent.

Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c 
b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index 1fda9d6c7ea3..308e5433bd04 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -716,7 +716,7 @@ static const char * const uart_b_groups[] = {
"uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x",
 };
 
-static const char * const uart_ao_b_gpioz_groups[] = {
+static const char * const uart_ao_b_z_groups[] = {
"uart_ao_tx_b_z", "uart_ao_rx_b_z",
"uart_ao_cts_b_z", "uart_ao_rts_b_z",
 };
@@ -855,7 +855,7 @@ static struct meson_pmx_func meson_axg_periphs_functions[] 
= {
FUNCTION(nand),
FUNCTION(uart_a),
FUNCTION(uart_b),
-   FUNCTION(uart_ao_b_gpioz),
+   FUNCTION_EX(uart_ao_b, _z),
FUNCTION(i2c0),
FUNCTION(i2c1),
FUNCTION(i2c2),
-- 
2.15.1

[PATCH 2/2] pinctrl: meson-axg: correct the pin expansion of UART_AO_B

[Yixun Lan]

The 'uart_ao_b_groups' for the UART_AO_B pins is already defined which is
living inside the AO domain, for these pins which are routed out from EE domain,
we need to correct them with the 'FUNCTION_EX' macro, otherwise there is
a conflict in the code level.

Also slightly adjust the name to make it short and more consistent.

Signed-off-by: Yixun Lan 
---
 drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c 
b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index 1fda9d6c7ea3..308e5433bd04 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -716,7 +716,7 @@ static const char * const uart_b_groups[] = {
"uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x",
 };
 
-static const char * const uart_ao_b_gpioz_groups[] = {
+static const char * const uart_ao_b_z_groups[] = {
"uart_ao_tx_b_z", "uart_ao_rx_b_z",
"uart_ao_cts_b_z", "uart_ao_rts_b_z",
 };
@@ -855,7 +855,7 @@ static struct meson_pmx_func meson_axg_periphs_functions[] 
= {
FUNCTION(nand),
FUNCTION(uart_a),
FUNCTION(uart_b),
-   FUNCTION(uart_ao_b_gpioz),
+   FUNCTION_EX(uart_ao_b, _z),
FUNCTION(i2c0),
FUNCTION(i2c1),
FUNCTION(i2c2),
-- 
2.15.1

Re: [PATCH v2 3/5] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

HI Martin:

On 01/08/18 14:07, Yixun Lan wrote:
> Hi Martin
> 
> On 01/08/18 04:19, Martin Blumenstingl wrote:
>> Hi Yixun,
>>
>> On Sat, Jan 6, 2018 at 1:10 AM, Yixun Lan <yixun@amlogic.com> wrote:
>>> Describe the pinctrl info for the UART controller which is found
>>> in the Meson-AXG SoCs.
>>>
>>> Signed-off-by: Yixun Lan <yixun@amlogic.com>
>>> ---
>>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 97 
>>> ++
>>>  1 file changed, 97 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
>>> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>>> index 644d0f9eaf8c..1eb45781c850 100644
>>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>>> @@ -448,6 +448,70 @@
>>> function = "spi1";
>>> };

.

>>>
>>> +
>> did you add this additional newline on purpose?
oops, this is added by mistake..
thanks for catching this, I will fix it

>>> remote_input_ao_pins: remote_input_ao {
>>> mux {
>>> groups = "remote_input_ao";
>>> function = 
>>> "remote_input_ao";
>>> };
>>> };
>>> +
>>> +   uart_ao_a_pins: uart_ao_a {
>>> +   mux {
>>> +   groups = "uart_ao_tx_a",
>>> +   "uart_ao_rx_a";
>>> +   function = "uart_ao_a";
>>> +   };
>>> +   };
>>> +
>>> +   uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
>>> +   mux {
>>> +   groups = "uart_ao_cts_a",
>>> +   "uart_ao_rts_a";
>>> +   function = "uart_ao_a";
>>> +   };
>>> +   };
>>> +
>>> +   uart_ao_b_pins: uart_ao_b {
>>> +   mux {
>>> +   groups = "uart_ao_tx_b",
>>> +   "uart_ao_rx_b";
>>> +   function = "uart_ao_b";
>>> +   };
>>> +   };
>>> +
>>> +   uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
>>> +   mux {
>>> +   groups = "uart_ao_cts_b",
>>> +   "uart_ao_rts_b";
>>> +   function = "uart_ao_b";
>>> +   };
>>> +   };
>>> };
>>>
>>> pwm_AO_ab: pwm@7000 {
>>> --
>>> 2.15.1
>>>
>>>
>>> ___
>>> linux-amlogic mailing list
>>> linux-amlo...@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
>>
>> Regards
>> Martin
>>
>> .
>>
> .
> 

Re: [PATCH v2 3/5] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

HI Martin:

On 01/08/18 14:07, Yixun Lan wrote:
> Hi Martin
> 
> On 01/08/18 04:19, Martin Blumenstingl wrote:
>> Hi Yixun,
>>
>> On Sat, Jan 6, 2018 at 1:10 AM, Yixun Lan  wrote:
>>> Describe the pinctrl info for the UART controller which is found
>>> in the Meson-AXG SoCs.
>>>
>>> Signed-off-by: Yixun Lan 
>>> ---
>>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 97 
>>> ++
>>>  1 file changed, 97 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
>>> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>>> index 644d0f9eaf8c..1eb45781c850 100644
>>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>>> @@ -448,6 +448,70 @@
>>> function = "spi1";
>>> };

.

>>>
>>> +
>> did you add this additional newline on purpose?
oops, this is added by mistake..
thanks for catching this, I will fix it

>>> remote_input_ao_pins: remote_input_ao {
>>> mux {
>>> groups = "remote_input_ao";
>>> function = 
>>> "remote_input_ao";
>>> };
>>> };
>>> +
>>> +   uart_ao_a_pins: uart_ao_a {
>>> +   mux {
>>> +   groups = "uart_ao_tx_a",
>>> +   "uart_ao_rx_a";
>>> +   function = "uart_ao_a";
>>> +   };
>>> +   };
>>> +
>>> +   uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
>>> +   mux {
>>> +   groups = "uart_ao_cts_a",
>>> +   "uart_ao_rts_a";
>>> +   function = "uart_ao_a";
>>> +   };
>>> +   };
>>> +
>>> +   uart_ao_b_pins: uart_ao_b {
>>> +   mux {
>>> +   groups = "uart_ao_tx_b",
>>> +   "uart_ao_rx_b";
>>> +   function = "uart_ao_b";
>>> +   };
>>> +   };
>>> +
>>> +   uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
>>> +   mux {
>>> +   groups = "uart_ao_cts_b",
>>> +   "uart_ao_rts_b";
>>> +   function = "uart_ao_b";
>>> +   };
>>> +   };
>>> };
>>>
>>> pwm_AO_ab: pwm@7000 {
>>> --
>>> 2.15.1
>>>
>>>
>>> ___
>>> linux-amlogic mailing list
>>> linux-amlo...@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
>>
>> Regards
>> Martin
>>
>> .
>>
> .
> 

Re: [PATCH v2 3/5] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

Hi Martin

On 01/08/18 04:19, Martin Blumenstingl wrote:
> Hi Yixun,
> 
> On Sat, Jan 6, 2018 at 1:10 AM, Yixun Lan <yixun@amlogic.com> wrote:
>> Describe the pinctrl info for the UART controller which is found
>> in the Meson-AXG SoCs.
>>
>> Signed-off-by: Yixun Lan <yixun@amlogic.com>
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 97 
>> ++
>>  1 file changed, 97 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
>> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index 644d0f9eaf8c..1eb45781c850 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -448,6 +448,70 @@
>> function = "spi1";
>> };
>> };
>> +
>> +   uart_a_pins: uart_a {
>> +   mux {
>> +   groups = "uart_tx_a",
>> +   "uart_rx_a";
>> +   function = "uart_a";
>> +   };
>> +   };
>> +
>> +   uart_a_cts_rts_pins: uart_a_cts_rts {
>> +   mux {
>> +   groups = "uart_cts_a",
>> +   "uart_rts_a";
>> +   function = "uart_a";
>> +   };
>> +   };
>> +
>> +   uart_b_x_pins: uart_b_x {
>> +   mux {
>> +   groups = "uart_tx_b_x",
>> +   "uart_rx_b_x";
>> +   function = "uart_b";
>> +   };
>> +   };
>> +
>> +   uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
>> +   mux {
>> +   groups = "uart_cts_b_x",
>> +   "uart_rts_b_x";
>> +   function = "uart_b";
>> +   };
>> +   };
>> +
>> +   uart_b_z_pins: uart_b_z {
>> +   mux {
>> +   groups = "uart_tx_b_z",
>> +   "uart_rx_b_z";
>> +   function = "uart_b";
>> +   };
>> +   };
>> +
>> +   uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
>> +   mux {
>> +   groups = "uart_cts_b_z",
>> +   "uart_rts_b_z";
>> +   function = "uart_b";
>> +   };
>> +   };
>> +
>> +   uart_ao_b_z_pins: uart_ao_b_z {
>> +   mux {
>> +   groups = "uart_ao_tx_b_z",
>> +   "uart_ao_rx_b_z";
>> +   function = "uart_ao_b_gpioz";
> (the following question just came up while I was looking at this
> patch, but I guess it's more a question towards the pinctrl driver)
> the name of the function looks a bit "weird" since below you are also
> using "uart_ao_b"
you right here, it's a question related to pinctrl subsystem.
from my point of view, it's even weird from the hardware perspective:
 that, the UART function of AO domain route the pin of EE domain..

> did you choose "uart_ao_b_gpioz" here because we cannot have

Re: [PATCH v2 3/5] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

Hi Martin

On 01/08/18 04:19, Martin Blumenstingl wrote:
> Hi Yixun,
> 
> On Sat, Jan 6, 2018 at 1:10 AM, Yixun Lan  wrote:
>> Describe the pinctrl info for the UART controller which is found
>> in the Meson-AXG SoCs.
>>
>> Signed-off-by: Yixun Lan 
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 97 
>> ++
>>  1 file changed, 97 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
>> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index 644d0f9eaf8c..1eb45781c850 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -448,6 +448,70 @@
>> function = "spi1";
>> };
>> };
>> +
>> +   uart_a_pins: uart_a {
>> +   mux {
>> +   groups = "uart_tx_a",
>> +   "uart_rx_a";
>> +   function = "uart_a";
>> +   };
>> +   };
>> +
>> +   uart_a_cts_rts_pins: uart_a_cts_rts {
>> +   mux {
>> +   groups = "uart_cts_a",
>> +   "uart_rts_a";
>> +   function = "uart_a";
>> +   };
>> +   };
>> +
>> +   uart_b_x_pins: uart_b_x {
>> +   mux {
>> +   groups = "uart_tx_b_x",
>> +   "uart_rx_b_x";
>> +   function = "uart_b";
>> +   };
>> +   };
>> +
>> +   uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
>> +   mux {
>> +   groups = "uart_cts_b_x",
>> +   "uart_rts_b_x";
>> +   function = "uart_b";
>> +   };
>> +   };
>> +
>> +   uart_b_z_pins: uart_b_z {
>> +   mux {
>> +   groups = "uart_tx_b_z",
>> +   "uart_rx_b_z";
>> +   function = "uart_b";
>> +   };
>> +   };
>> +
>> +   uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
>> +   mux {
>> +   groups = "uart_cts_b_z",
>> +   "uart_rts_b_z";
>> +   function = "uart_b";
>> +   };
>> +   };
>> +
>> +   uart_ao_b_z_pins: uart_ao_b_z {
>> +   mux {
>> +   groups = "uart_ao_tx_b_z",
>> +   "uart_ao_rx_b_z";
>> +   function = "uart_ao_b_gpioz";
> (the following question just came up while I was looking at this
> patch, but I guess it's more a question towards the pinctrl driver)
> the name of the function looks a bit "weird" since below you are also
> using "uart_ao_b"
you right here, it's a question related to pinctrl subsystem.
from my point of view, it's even weird from the hardware perspective:
 that, the UART function of AO domain route the pin of EE domain..

> did you choose "uart_ao_b_gpioz" here because we cannot have the same
&g

[PATCH v2 1/5] ARM64: dts: meson: uart: fix address space range

[Yixun Lan]

The address space range is actually 0x18, fixed here.

Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi |  4 ++--
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi  | 10 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index a80632641b39..70c776ef7aa7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -165,14 +165,14 @@
 
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
-   reg = <0x0 0x24000 0x0 0x14>;
+   reg = <0x0 0x24000 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_B: serial@23000 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
-   reg = <0x0 0x23000 0x0 0x14>;
+   reg = <0x0 0x23000 0x0 0x18>;
interrupts = ;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 6cb3c2a52baf..4ee2e7951482 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -235,14 +235,14 @@
 
uart_A: serial@84c0 {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x84c0 0x0 0x14>;
+   reg = <0x0 0x84c0 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_B: serial@84dc {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x84dc 0x0 0x14>;
+   reg = <0x0 0x84dc 0x0 0x18>;
interrupts = ;
status = "disabled";
};
@@ -287,7 +287,7 @@
 
uart_C: serial@8700 {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x8700 0x0 0x14>;
+   reg = <0x0 0x8700 0x0 0x18>;
interrupts = ;
status = "disabled";
};
@@ -404,14 +404,14 @@
 
uart_AO: serial@4c0 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-ao-uart";
-   reg = <0x0 0x004c0 0x0 0x14>;
+   reg = <0x0 0x004c0 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_AO_B: serial@4e0 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-ao-uart";
-   reg = <0x0 0x004e0 0x0 0x14>;
+   reg = <0x0 0x004e0 0x0 0x18>;
interrupts = ;
status = "disabled";
};
-- 
2.15.1

[PATCH v2 3/5] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

Describe the pinctrl info for the UART controller which is found
in the Meson-AXG SoCs.

Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 97 ++
 1 file changed, 97 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 644d0f9eaf8c..1eb45781c850 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -448,6 +448,70 @@
function = "spi1";
};
};
+
+   uart_a_pins: uart_a {
+   mux {
+   groups = "uart_tx_a",
+   "uart_rx_a";
+   function = "uart_a";
+   };
+   };
+
+   uart_a_cts_rts_pins: uart_a_cts_rts {
+   mux {
+   groups = "uart_cts_a",
+   "uart_rts_a";
+   function = "uart_a";
+   };
+   };
+
+   uart_b_x_pins: uart_b_x {
+   mux {
+   groups = "uart_tx_b_x",
+   "uart_rx_b_x";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+   mux {
+   groups = "uart_cts_b_x",
+   "uart_rts_b_x";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_z_pins: uart_b_z {
+   mux {
+   groups = "uart_tx_b_z",
+   "uart_rx_b_z";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+   mux {
+   groups = "uart_cts_b_z",
+   "uart_rts_b_z";
+   function = "uart_b";
+   };
+   };
+
+   uart_ao_b_z_pins: uart_ao_b_z {
+   mux {
+   groups = "uart_ao_tx_b_z",
+   "uart_ao_rx_b_z";
+   function = "uart_ao_b_gpioz";
+   };
+   };
+
+   uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+   mux {
+   groups = "uart_ao_cts_b_z",
+   "uart_ao_rts_b_z";
+   function = "uart_ao_b_gpioz";
+   };
+   };
};
};
 
@@ -492,12 +556,45 @@
gpio-ranges = <_aobus 0 0 15>;
};
 
+
remote_input_ao_pins: remote_input_ao {
mux {
groups = "remote_input_ao";
function = "remote_input_ao";
};
};
+
+   uart_ao_a_pins: uart_ao_a {
+   mux {
+   groups = "uart_ao_tx_a",
+  

[PATCH v2 5/5] ARM64: dts: meson-axg: enable the UART_A controller

[Yixun Lan]

The UART_A is connected to a BT module on the S400 board.

Acked-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 9c1b78028ccb..d56894dbb209 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -14,6 +14,7 @@
 
aliases {
serial0 = _AO;
+   serial1 = _A;
};
 };
 
@@ -24,6 +25,12 @@
pinctrl-names = "default";
 };
 
+_A {
+   status = "okay";
+   pinctrl-0 = <_a_pins>;
+   pinctrl-names = "default";
+};
+
 _AO {
status = "okay";
pinctrl-0 = <_ao_a_pins>;
-- 
2.15.1

[PATCH v2 5/5] ARM64: dts: meson-axg: enable the UART_A controller

[Yixun Lan]

The UART_A is connected to a BT module on the S400 board.

Acked-by: Jerome Brunet 
Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 9c1b78028ccb..d56894dbb209 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -14,6 +14,7 @@
 
aliases {
serial0 = _AO;
+   serial1 = _A;
};
 };
 
@@ -24,6 +25,12 @@
pinctrl-names = "default";
 };
 
+_A {
+   status = "okay";
+   pinctrl-0 = <_a_pins>;
+   pinctrl-names = "default";
+};
+
 _AO {
status = "okay";
pinctrl-0 = <_ao_a_pins>;
-- 
2.15.1

[PATCH v2 1/5] ARM64: dts: meson: uart: fix address space range

[Yixun Lan]

The address space range is actually 0x18, fixed here.

Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi |  4 ++--
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi  | 10 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index a80632641b39..70c776ef7aa7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -165,14 +165,14 @@
 
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
-   reg = <0x0 0x24000 0x0 0x14>;
+   reg = <0x0 0x24000 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_B: serial@23000 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
-   reg = <0x0 0x23000 0x0 0x14>;
+   reg = <0x0 0x23000 0x0 0x18>;
interrupts = ;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 6cb3c2a52baf..4ee2e7951482 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -235,14 +235,14 @@
 
uart_A: serial@84c0 {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x84c0 0x0 0x14>;
+   reg = <0x0 0x84c0 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_B: serial@84dc {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x84dc 0x0 0x14>;
+   reg = <0x0 0x84dc 0x0 0x18>;
interrupts = ;
status = "disabled";
};
@@ -287,7 +287,7 @@
 
uart_C: serial@8700 {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x8700 0x0 0x14>;
+   reg = <0x0 0x8700 0x0 0x18>;
interrupts = ;
status = "disabled";
};
@@ -404,14 +404,14 @@
 
uart_AO: serial@4c0 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-ao-uart";
-   reg = <0x0 0x004c0 0x0 0x14>;
+   reg = <0x0 0x004c0 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_AO_B: serial@4e0 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-ao-uart";
-   reg = <0x0 0x004e0 0x0 0x14>;
+   reg = <0x0 0x004e0 0x0 0x18>;
interrupts = ;
status = "disabled";
};
-- 
2.15.1

[PATCH v2 3/5] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

Describe the pinctrl info for the UART controller which is found
in the Meson-AXG SoCs.

Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 97 ++
 1 file changed, 97 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 644d0f9eaf8c..1eb45781c850 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -448,6 +448,70 @@
function = "spi1";
};
};
+
+   uart_a_pins: uart_a {
+   mux {
+   groups = "uart_tx_a",
+   "uart_rx_a";
+   function = "uart_a";
+   };
+   };
+
+   uart_a_cts_rts_pins: uart_a_cts_rts {
+   mux {
+   groups = "uart_cts_a",
+   "uart_rts_a";
+   function = "uart_a";
+   };
+   };
+
+   uart_b_x_pins: uart_b_x {
+   mux {
+   groups = "uart_tx_b_x",
+   "uart_rx_b_x";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+   mux {
+   groups = "uart_cts_b_x",
+   "uart_rts_b_x";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_z_pins: uart_b_z {
+   mux {
+   groups = "uart_tx_b_z",
+   "uart_rx_b_z";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+   mux {
+   groups = "uart_cts_b_z",
+   "uart_rts_b_z";
+   function = "uart_b";
+   };
+   };
+
+   uart_ao_b_z_pins: uart_ao_b_z {
+   mux {
+   groups = "uart_ao_tx_b_z",
+   "uart_ao_rx_b_z";
+   function = "uart_ao_b_gpioz";
+   };
+   };
+
+   uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+   mux {
+   groups = "uart_ao_cts_b_z",
+   "uart_ao_rts_b_z";
+   function = "uart_ao_b_gpioz";
+   };
+   };
};
};
 
@@ -492,12 +556,45 @@
gpio-ranges = <_aobus 0 0 15>;
};
 
+
remote_input_ao_pins: remote_input_ao {
mux {
groups = "remote_input_ao";
function = "remote_input_ao";
};
};
+
+   uart_ao_a_pins: uart_ao_a {
+   mux {
+   groups = "uart_ao_tx_a",
+   &

[PATCH v2 0/5] ARM64: dts: meson-axg: UART DT updates

[Yixun Lan]

HI Kevin
 These are the UART DT updates for the Meson-AXG platform.

 The patch 1 is a general fix.
Other patches are about adding clock & pinctrl info, then using them.
Last patch enable UART_A which connect to a BT module on the S400 board.

Note: 
This series depend on previous UART_AO clock switch patch[1]
also, these patch request clocks, so they need the
tag:meson-clk-for-v4.16-2 from clk-meson's tree in order to compile.

Changes since v1 at [2]:
  -- fix address range for all platform
  -- squash patch 1, 3 (drop compatible & add clock)
  -- fix typo in pinctrl info
  -- add Jerome's Ack

[1] 
 http://lkml.kernel.org/r/20171215141741.175985-1-yixun@amlogic.com

[2]
 http://lkml.kernel.org/r/20180105095621.196472-1-yixun@amlogic.com


Yixun Lan (5):
  ARM64: dts: meson: uart: fix address space range
  ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART
  ARM64: dts: meson-axg: uart: Add the pinctrl info description
  ARM64: dts: meson-axg: complete the pinctrl info for UART_AO_A
  ARM64: dts: meson-axg: enable the UART_A controller

 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |   9 ++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 109 -
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi  |  10 +--
 3 files changed, 119 insertions(+), 9 deletions(-)

-- 
2.15.1

[PATCH v2 0/5] ARM64: dts: meson-axg: UART DT updates

[Yixun Lan]

HI Kevin
 These are the UART DT updates for the Meson-AXG platform.

 The patch 1 is a general fix.
Other patches are about adding clock & pinctrl info, then using them.
Last patch enable UART_A which connect to a BT module on the S400 board.

Note: 
This series depend on previous UART_AO clock switch patch[1]
also, these patch request clocks, so they need the
tag:meson-clk-for-v4.16-2 from clk-meson's tree in order to compile.

Changes since v1 at [2]:
  -- fix address range for all platform
  -- squash patch 1, 3 (drop compatible & add clock)
  -- fix typo in pinctrl info
  -- add Jerome's Ack

[1] 
 http://lkml.kernel.org/r/20171215141741.175985-1-yixun@amlogic.com

[2]
 http://lkml.kernel.org/r/20180105095621.196472-1-yixun@amlogic.com


Yixun Lan (5):
  ARM64: dts: meson: uart: fix address space range
  ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART
  ARM64: dts: meson-axg: uart: Add the pinctrl info description
  ARM64: dts: meson-axg: complete the pinctrl info for UART_AO_A
  ARM64: dts: meson-axg: enable the UART_A controller

 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |   9 ++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 109 -
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi  |  10 +--
 3 files changed, 119 insertions(+), 9 deletions(-)

-- 
2.15.1

[PATCH v2 4/5] ARM64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Yixun Lan]

Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we may need to rely on bootloader for the initialization.

Acked-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 447b98d30921..9c1b78028ccb 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -26,6 +26,8 @@
 
 _AO {
status = "okay";
+   pinctrl-0 = <_ao_a_pins>;
+   pinctrl-names = "default";
 };
 
  {
-- 
2.15.1

[PATCH v2 2/5] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

When update the clock info for the UART controller in the EE domain,
the driver explicitly require 'pclk' in order to work properly.

With current logic of the code, the driver will go for the legacy clock probe
routine[1] if it find current compatible string match to 'amlogic,meson-uart',
which result in not requesting the 'pclk' clock, thus break the driver in the 
end.

[1] drivers/tty/serial/meson_uart.c:685

/* Use legacy way until all platforms switch to new bindings */
if (of_device_is_compatible(pdev->dev.of_node, "amlogic,meson-uart"))
ret = meson_uart_probe_clocks_legacy(pdev, port);
else
ret = meson_uart_probe_clocks(pdev, port);

Acked-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 70c776ef7aa7..644d0f9eaf8c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -164,17 +164,21 @@
};
 
uart_A: serial@24000 {
-   compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
+   compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x24000 0x0 0x18>;
interrupts = ;
status = "disabled";
+   clocks = <>, < CLKID_UART0>, <>;
+   clock-names = "xtal", "pclk", "baud";
};
 
uart_B: serial@23000 {
-   compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
+   compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x23000 0x0 0x18>;
interrupts = ;
status = "disabled";
+   clocks = <>, < CLKID_UART1>, <>;
+   clock-names = "xtal", "pclk", "baud";
};
};
 
-- 
2.15.1

[PATCH v2 4/5] ARM64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Yixun Lan]

Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we may need to rely on bootloader for the initialization.

Acked-by: Jerome Brunet 
Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 447b98d30921..9c1b78028ccb 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -26,6 +26,8 @@
 
 _AO {
status = "okay";
+   pinctrl-0 = <_ao_a_pins>;
+   pinctrl-names = "default";
 };
 
  {
-- 
2.15.1

[PATCH v2 2/5] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

When update the clock info for the UART controller in the EE domain,
the driver explicitly require 'pclk' in order to work properly.

With current logic of the code, the driver will go for the legacy clock probe
routine[1] if it find current compatible string match to 'amlogic,meson-uart',
which result in not requesting the 'pclk' clock, thus break the driver in the 
end.

[1] drivers/tty/serial/meson_uart.c:685

/* Use legacy way until all platforms switch to new bindings */
if (of_device_is_compatible(pdev->dev.of_node, "amlogic,meson-uart"))
ret = meson_uart_probe_clocks_legacy(pdev, port);
else
ret = meson_uart_probe_clocks(pdev, port);

Acked-by: Jerome Brunet 
Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 70c776ef7aa7..644d0f9eaf8c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -164,17 +164,21 @@
};
 
uart_A: serial@24000 {
-   compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
+   compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x24000 0x0 0x18>;
interrupts = ;
status = "disabled";
+   clocks = <>, < CLKID_UART0>, <>;
+   clock-names = "xtal", "pclk", "baud";
};
 
uart_B: serial@23000 {
-   compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
+   compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x23000 0x0 0x18>;
interrupts = ;
status = "disabled";
+   clocks = <>, < CLKID_UART1>, <>;
+   clock-names = "xtal", "pclk", "baud";
};
};
 
-- 
2.15.1

Re: [PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

On 01/05/2018 06:28 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> Describe the pinctrl info for the UART controller which 
.

>> +uart_a_cts_rts_pins: uart_a_cts_rts {
>> +mux {
>> +groups = "uart_ctx_a",
> 
> uart_ctx_a does not exist in pinctrl
> 
sorry, it's a typo, it's uart_cts_a

em. end of the Friday is really bad time for me to compose the patches..


>> +"uart_rts_a";
>> +function = "uart_a";
>> +};
>> +};
>> +
>> +uart_b_x_pins: uart_b_x {
>> +mux {
>> +groups = "uart_tx_b_x",
>> +"uart_rx_b_x";
>> +function = "uart_b";
>> +};
>> +};
>> +
>> +uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
>> +mux {
>> +groups = "uart_cts_b_x",
>> +"uart_rts_b_x";
>> +function = "uart_b";
>> +};
>> +};
>> +
>> +uart_b_z_pins: uart_b_z {
>> +mux {
>> +groups = "uart_tx_b_z",
>> +"uart_rx_b_z";
>> +function = "uart_b";
>> +};
>> +};
>> +
>> +uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
>> +mux {
>> +groups = "uart_cts_b_z",
>> +"uart_rts_b_z";
>> +function = "uart_b";
>> +};
>> +};
>> +
>> +uart_ao_b_z_pins: uart_ao_b_z {
>> +mux {
>> +groups = "uart_ao_tx_b_z",
>> +"uart_ao_rx_b_z";
>> +function = "uart_ao_b_groupz";
> 
> "uart_ao_b_groupz" function does not exist in pinctrl
typo, uart_ao_b_gpioz

> 
.

Re: [PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

On 01/05/2018 06:28 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> Describe the pinctrl info for the UART controller which 
.

>> +uart_a_cts_rts_pins: uart_a_cts_rts {
>> +mux {
>> +groups = "uart_ctx_a",
> 
> uart_ctx_a does not exist in pinctrl
> 
sorry, it's a typo, it's uart_cts_a

em. end of the Friday is really bad time for me to compose the patches..


>> +"uart_rts_a";
>> +function = "uart_a";
>> +};
>> +};
>> +
>> +uart_b_x_pins: uart_b_x {
>> +mux {
>> +groups = "uart_tx_b_x",
>> +"uart_rx_b_x";
>> +function = "uart_b";
>> +};
>> +};
>> +
>> +uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
>> +mux {
>> +groups = "uart_cts_b_x",
>> +"uart_rts_b_x";
>> +function = "uart_b";
>> +};
>> +};
>> +
>> +uart_b_z_pins: uart_b_z {
>> +mux {
>> +groups = "uart_tx_b_z",
>> +"uart_rx_b_z";
>> +function = "uart_b";
>> +};
>> +};
>> +
>> +uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
>> +mux {
>> +groups = "uart_cts_b_z",
>> +"uart_rts_b_z";
>> +function = "uart_b";
>> +};
>> +};
>> +
>> +uart_ao_b_z_pins: uart_ao_b_z {
>> +mux {
>> +groups = "uart_ao_tx_b_z",
>> +"uart_ao_rx_b_z";
>> +function = "uart_ao_b_groupz";
> 
> "uart_ao_b_groupz" function does not exist in pinctrl
typo, uart_ao_b_gpioz

> 
.

Re: [PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Yixun Lan]

On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> The address space range is actually 0x18, fixed here.
> 
> Isn't it the same for other meson SoC ? If they are compatible, it should.
> Could you please re-submit this change addressing all the required platforms ?
> 

sure

sorry, I was in hurry to send the patch set without do a full tree check..

you right, the fix should also apply to other SoCs, I will fold them
into this patch together, thanks for raising the idea.



>>
>> Signed-off-by: Yixun Lan <yixun@amlogic.com>
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
>> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index 1c6002b3fe34..9636a7c5f6ed 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -143,14 +143,14 @@
>>  
>>  uart_A: serial@24000 {
>>  compatible = "amlogic,meson-gx-uart";
>> -reg = <0x0 0x24000 0x0 0x14>;
>> +reg = <0x0 0x24000 0x0 0x18>;
>>  interrupts = ;
>>  status = "disabled";
>>  };
>>  
>>  uart_B: serial@23000 {
>>  compatible = "amlogic,meson-gx-uart";
>> -reg = <0x0 0x23000 0x0 0x14>;
>> +reg = <0x0 0x23000 0x0 0x18>;
>>  interrupts = ;
>>  status = "disabled";
>>  };
> 
> .
> 

Re: [PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Yixun Lan]

On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> The address space range is actually 0x18, fixed here.
> 
> Isn't it the same for other meson SoC ? If they are compatible, it should.
> Could you please re-submit this change addressing all the required platforms ?
> 

sure

sorry, I was in hurry to send the patch set without do a full tree check..

you right, the fix should also apply to other SoCs, I will fold them
into this patch together, thanks for raising the idea.



>>
>> Signed-off-by: Yixun Lan 
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
>> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index 1c6002b3fe34..9636a7c5f6ed 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -143,14 +143,14 @@
>>  
>>  uart_A: serial@24000 {
>>  compatible = "amlogic,meson-gx-uart";
>> -reg = <0x0 0x24000 0x0 0x14>;
>> +reg = <0x0 0x24000 0x0 0x18>;
>>  interrupts = ;
>>  status = "disabled";
>>  };
>>  
>>  uart_B: serial@23000 {
>>  compatible = "amlogic,meson-gx-uart";
>> -reg = <0x0 0x23000 0x0 0x14>;
>> +reg = <0x0 0x23000 0x0 0x18>;
>>  interrupts = ;
>>  status = "disabled";
>>  };
> 
> .
> 

Re: [PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> For the UART controller in EE domain, they require 'pclk' to work.
> 
> they ? "the driver" maybe ?
> 
>> Current logic of the code will force to go for legacy clock probe
>> if it found current compatible string match to 'amlogic,meson-ao-uart'.
> 
> did you mean "amlogic,meson-uart" instead ?
> 
good catch! it's "amlogic,meson-uart"


> Apart from that
> 
> Acked-by: Jerome Brunet <jbru...@baylibre.com>
> 
>>
>> Signed-off-by: Yixun Lan <yixun@amlogic.com>
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
>> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index e2b8a9c8bf0b..1c6002b3fe34 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -142,14 +142,14 @@
>>  };
>>  
>>  uart_A: serial@24000 {
>> -compatible = "amlogic,meson-gx-uart", 
>> "amlogic,meson-uart";
>> +compatible = "amlogic,meson-gx-uart";
>>  reg = <0x0 0x24000 0x0 0x14>;
>>  interrupts = ;
>>  status = "disabled";
>>  };
>>  
>>  uart_B: serial@23000 {
>> -compatible = "amlogic,meson-gx-uart", 
>> "amlogic,meson-uart";
>> +compatible = "amlogic,meson-gx-uart";
>>  reg = <0x0 0x23000 0x0 0x14>;
>>  interrupts = ;
>>  status = "disabled";
> 
> .
> 

Re: [PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> For the UART controller in EE domain, they require 'pclk' to work.
> 
> they ? "the driver" maybe ?
> 
>> Current logic of the code will force to go for legacy clock probe
>> if it found current compatible string match to 'amlogic,meson-ao-uart'.
> 
> did you mean "amlogic,meson-uart" instead ?
> 
good catch! it's "amlogic,meson-uart"


> Apart from that
> 
> Acked-by: Jerome Brunet 
> 
>>
>> Signed-off-by: Yixun Lan 
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
>> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index e2b8a9c8bf0b..1c6002b3fe34 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -142,14 +142,14 @@
>>  };
>>  
>>  uart_A: serial@24000 {
>> -compatible = "amlogic,meson-gx-uart", 
>> "amlogic,meson-uart";
>> +compatible = "amlogic,meson-gx-uart";
>>  reg = <0x0 0x24000 0x0 0x14>;
>>  interrupts = ;
>>  status = "disabled";
>>  };
>>  
>>  uart_B: serial@23000 {
>> -compatible = "amlogic,meson-gx-uart", 
>> "amlogic,meson-uart";
>> +compatible = "amlogic,meson-gx-uart";
>>  reg = <0x0 0x23000 0x0 0x14>;
>>  interrupts = ;
>>  status = "disabled";
> 
> .
> 

[PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Yixun Lan]

The address space range is actually 0x18, fixed here.

Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 1c6002b3fe34..9636a7c5f6ed 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -143,14 +143,14 @@
 
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x24000 0x0 0x14>;
+   reg = <0x0 0x24000 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_B: serial@23000 {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x23000 0x0 0x14>;
+   reg = <0x0 0x23000 0x0 0x18>;
interrupts = ;
status = "disabled";
};
-- 
2.15.1

[PATCH 2/6] ARM64: dts: meson-axg: uart: fix address space range

[Yixun Lan]

The address space range is actually 0x18, fixed here.

Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 1c6002b3fe34..9636a7c5f6ed 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -143,14 +143,14 @@
 
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x24000 0x0 0x14>;
+   reg = <0x0 0x24000 0x0 0x18>;
interrupts = ;
status = "disabled";
};
 
uart_B: serial@23000 {
compatible = "amlogic,meson-gx-uart";
-   reg = <0x0 0x23000 0x0 0x14>;
+   reg = <0x0 0x23000 0x0 0x18>;
interrupts = ;
status = "disabled";
};
-- 
2.15.1

[PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

For the UART controller in EE domain, they require 'pclk' to work.
Current logic of the code will force to go for legacy clock probe
if it found current compatible string match to 'amlogic,meson-ao-uart'.

Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index e2b8a9c8bf0b..1c6002b3fe34 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -142,14 +142,14 @@
};
 
uart_A: serial@24000 {
-   compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
+   compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x24000 0x0 0x14>;
interrupts = ;
status = "disabled";
};
 
uart_B: serial@23000 {
-   compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
+   compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x23000 0x0 0x14>;
interrupts = ;
status = "disabled";
-- 
2.15.1

[PATCH 1/6] ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART

[Yixun Lan]

For the UART controller in EE domain, they require 'pclk' to work.
Current logic of the code will force to go for legacy clock probe
if it found current compatible string match to 'amlogic,meson-ao-uart'.

Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index e2b8a9c8bf0b..1c6002b3fe34 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -142,14 +142,14 @@
};
 
uart_A: serial@24000 {
-   compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
+   compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x24000 0x0 0x14>;
interrupts = ;
status = "disabled";
};
 
uart_B: serial@23000 {
-   compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
+   compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x23000 0x0 0x14>;
interrupts = ;
status = "disabled";
-- 
2.15.1

[PATCH 6/6] ARM64: dts: meson-axg: enable the UART_A controller

[Yixun Lan]

The UART_A is connect to a BT module in the S400 board.

Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 2b79be356996..7e03b8da4856 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -14,9 +14,16 @@
 
aliases {
serial0 = _AO;
+   serial1 = _A;
};
 };
 
+_A {
+   status = "okay";
+   pinctrl-0 = <_a_pins>;
+   pinctrl-names = "default";
+};
+
 _AO {
status = "okay";
pinctrl-0 = <_ao_a_pins>;
-- 
2.15.1

[PATCH 6/6] ARM64: dts: meson-axg: enable the UART_A controller

[Yixun Lan]

The UART_A is connect to a BT module in the S400 board.

Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 2b79be356996..7e03b8da4856 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -14,9 +14,16 @@
 
aliases {
serial0 = _AO;
+   serial1 = _A;
};
 };
 
+_A {
+   status = "okay";
+   pinctrl-0 = <_a_pins>;
+   pinctrl-names = "default";
+};
+
 _AO {
status = "okay";
pinctrl-0 = <_ao_a_pins>;
-- 
2.15.1

[PATCH 5/6] arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Yixun Lan]

Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we my rely on bootloader for the initialization.

Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..2b79be356996 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -19,4 +19,6 @@
 
 _AO {
status = "okay";
+   pinctrl-0 = <_ao_a_pins>;
+   pinctrl-names = "default";
 };
-- 
2.15.1

[PATCH 5/6] arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A

[Yixun Lan]

Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we my rely on bootloader for the initialization.

Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..2b79be356996 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -19,4 +19,6 @@
 
 _AO {
status = "okay";
+   pinctrl-0 = <_ao_a_pins>;
+   pinctrl-names = "default";
 };
-- 
2.15.1

[PATCH 3/6] ARM64: dts: meson-axg: uart: Add the clock info description

[Yixun Lan]

Add the clock info description for the EE UART controller.

Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 9636a7c5f6ed..f6bf01cfff4b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -146,6 +146,8 @@
reg = <0x0 0x24000 0x0 0x18>;
interrupts = ;
status = "disabled";
+   clocks = <>, < CLKID_UART0>, <>;
+   clock-names = "xtal", "pclk", "baud";
};
 
uart_B: serial@23000 {
@@ -153,6 +155,8 @@
reg = <0x0 0x23000 0x0 0x18>;
interrupts = ;
status = "disabled";
+   clocks = <>, < CLKID_UART1>, <>;
+   clock-names = "xtal", "pclk", "baud";
};
};
 
-- 
2.15.1

[PATCH 3/6] ARM64: dts: meson-axg: uart: Add the clock info description

[Yixun Lan]

Add the clock info description for the EE UART controller.

Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 9636a7c5f6ed..f6bf01cfff4b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -146,6 +146,8 @@
reg = <0x0 0x24000 0x0 0x18>;
interrupts = ;
status = "disabled";
+   clocks = <>, < CLKID_UART0>, <>;
+   clock-names = "xtal", "pclk", "baud";
};
 
uart_B: serial@23000 {
@@ -153,6 +155,8 @@
reg = <0x0 0x23000 0x0 0x18>;
interrupts = ;
status = "disabled";
+   clocks = <>, < CLKID_UART1>, <>;
+   clock-names = "xtal", "pclk", "baud";
};
};
 
-- 
2.15.1

[PATCH 0/6] ARM64: dts: meson-axg: UART DT updates

[Yixun Lan]

HI Kevin
 These are the UART DT updates for the Meson-AXG platform.

The patch 1, 2 are two general fixes.
Other patches are about adding clock & pinctrl info, then using them.
Last patch enable UART_A which connect to BT module in the S400 board.

Note: 
This series depend on previous UART_AO clock switch patch[1]
also, these patch request clocks, so they need the
tag:meson-clk-for-v4.16-2 from clk-meson's tree in order to compile.

[1] 
http://lkml.kernel.org/r/20171215141741.175985-1-yixun@amlogic.com

Yixun Lan (6):
  ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART
  ARM64: dts: meson-axg: uart: fix address space range
  ARM64: dts: meson-axg: uart: Add the clock info description
  ARM64: dts: meson-axg: uart: Add the pinctrl info description
  arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A
  ARM64: dts: meson-axg: enable the UART_A controller

 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |   9 +++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 108 -
 2 files changed, 113 insertions(+), 4 deletions(-)

-- 
2.15.1

[PATCH 0/6] ARM64: dts: meson-axg: UART DT updates

[Yixun Lan]

HI Kevin
 These are the UART DT updates for the Meson-AXG platform.

The patch 1, 2 are two general fixes.
Other patches are about adding clock & pinctrl info, then using them.
Last patch enable UART_A which connect to BT module in the S400 board.

Note: 
This series depend on previous UART_AO clock switch patch[1]
also, these patch request clocks, so they need the
tag:meson-clk-for-v4.16-2 from clk-meson's tree in order to compile.

[1] 
http://lkml.kernel.org/r/20171215141741.175985-1-yixun@amlogic.com

Yixun Lan (6):
  ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART
  ARM64: dts: meson-axg: uart: fix address space range
  ARM64: dts: meson-axg: uart: Add the clock info description
  ARM64: dts: meson-axg: uart: Add the pinctrl info description
  arm64: dts: meson-axg: complete the pinctrl info for UART_AO_A
  ARM64: dts: meson-axg: enable the UART_A controller

 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |   9 +++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 108 -
 2 files changed, 113 insertions(+), 4 deletions(-)

-- 
2.15.1

[PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

Describe the pinctrl info for the UART controller which found
in the Meson-AXG SoCs.

Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++
 1 file changed, 96 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index f6bf01cfff4b..78bb206e2897 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -303,6 +303,70 @@
function = "pwm_d";
};
};
+
+   uart_a_pins: uart_a {
+   mux {
+   groups = "uart_tx_a",
+   "uart_rx_a";
+   function = "uart_a";
+   };
+   };
+
+   uart_a_cts_rts_pins: uart_a_cts_rts {
+   mux {
+   groups = "uart_ctx_a",
+   "uart_rts_a";
+   function = "uart_a";
+   };
+   };
+
+   uart_b_x_pins: uart_b_x {
+   mux {
+   groups = "uart_tx_b_x",
+   "uart_rx_b_x";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+   mux {
+   groups = "uart_cts_b_x",
+   "uart_rts_b_x";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_z_pins: uart_b_z {
+   mux {
+   groups = "uart_tx_b_z",
+   "uart_rx_b_z";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+   mux {
+   groups = "uart_cts_b_z",
+   "uart_rts_b_z";
+   function = "uart_b";
+   };
+   };
+
+   uart_ao_b_z_pins: uart_ao_b_z {
+   mux {
+   groups = "uart_ao_tx_b_z",
+   "uart_ao_rx_b_z";
+   function = "uart_ao_b_groupz";
+   };
+   };
+
+   uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+   mux {
+   groups = "uart_ao_cts_b_z",
+   "uart_ao_rts_b_z";
+   function = "uart_ao_b_groupz";
+   };
+   };
};
};
 
@@ -346,6 +410,38 @@
#gpio-cells = <2>;
gpio-ranges = <_aobus 0 0 15>;
};
+
+   uart_ao_a_pins: uart_ao_a {
+   mux {
+   groups = "uart_ao_tx_a",
+   "uart_ao_rx_a";
+   function = "uart_ao_a";
+   };
+   };
+
+   uart_ao_

[PATCH 4/6] ARM64: dts: meson-axg: uart: Add the pinctrl info description

[Yixun Lan]

Describe the pinctrl info for the UART controller which found
in the Meson-AXG SoCs.

Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++
 1 file changed, 96 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index f6bf01cfff4b..78bb206e2897 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -303,6 +303,70 @@
function = "pwm_d";
};
};
+
+   uart_a_pins: uart_a {
+   mux {
+   groups = "uart_tx_a",
+   "uart_rx_a";
+   function = "uart_a";
+   };
+   };
+
+   uart_a_cts_rts_pins: uart_a_cts_rts {
+   mux {
+   groups = "uart_ctx_a",
+   "uart_rts_a";
+   function = "uart_a";
+   };
+   };
+
+   uart_b_x_pins: uart_b_x {
+   mux {
+   groups = "uart_tx_b_x",
+   "uart_rx_b_x";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+   mux {
+   groups = "uart_cts_b_x",
+   "uart_rts_b_x";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_z_pins: uart_b_z {
+   mux {
+   groups = "uart_tx_b_z",
+   "uart_rx_b_z";
+   function = "uart_b";
+   };
+   };
+
+   uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+   mux {
+   groups = "uart_cts_b_z",
+   "uart_rts_b_z";
+   function = "uart_b";
+   };
+   };
+
+   uart_ao_b_z_pins: uart_ao_b_z {
+   mux {
+   groups = "uart_ao_tx_b_z",
+   "uart_ao_rx_b_z";
+   function = "uart_ao_b_groupz";
+   };
+   };
+
+   uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+   mux {
+   groups = "uart_ao_cts_b_z",
+   "uart_ao_rts_b_z";
+   function = "uart_ao_b_groupz";
+   };
+   };
};
};
 
@@ -346,6 +410,38 @@
#gpio-cells = <2>;
gpio-ranges = <_aobus 0 0 15>;
};
+
+   uart_ao_a_pins: uart_ao_a {
+   mux {
+   groups = "uart_ao_tx_a",
+   "uart_ao_rx_a";
+   function = "uart_ao_a";
+   };
+   };
+
+   uart_ao_a_cts_

[PATCH v4 1/2] ARM64: dts: meson-axg: add ethernet mac controller

[Yixun Lan]

Add DT info for the stmmac ethernet MAC which found in
the Amlogic's Meson-AXG SoC, also describe the ethernet
pinctrl & clock information here.

Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 54 ++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index d288d4724ae3..dea1bc31b4de 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
compatible = "amlogic,meson-axg";
@@ -155,6 +156,19 @@
};
};
 
+   ethmac: ethernet@ff3f {
+   compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
+   reg = <0x0 0xff3f 0x0 0x1
+   0x0 0xff634540 0x0 0x8>;
+   interrupts = ;
+   interrupt-names = "macirq";
+   clocks = < CLKID_ETH>,
+< CLKID_FCLK_DIV2>,
+< CLKID_MPLL2>;
+   clock-names = "stmmaceth", "clkin0", "clkin1";
+   status = "disabled";
+   };
+
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
reg = <0x0 0xffc01000 0 0x1000>,
@@ -215,6 +229,46 @@
gpio-ranges = <_periphs 0 0 86>;
};
 
+   eth_rgmii_x_pins: eth-x-rgmii {
+   mux {
+   groups = "eth_mdio_x",
+  "eth_mdc_x",
+  "eth_rgmii_rx_clk_x",
+  "eth_rx_dv_x",
+  "eth_rxd0_x",
+  "eth_rxd1_x",
+  "eth_rxd2_rgmii",
+  "eth_rxd3_rgmii",
+  "eth_rgmii_tx_clk",
+  "eth_txen_x",
+  "eth_txd0_x",
+  "eth_txd1_x",
+  "eth_txd2_rgmii",
+  "eth_txd3_rgmii";
+   function = "eth";
+   };
+   };
+
+   eth_rgmii_y_pins: eth-y-rgmii {
+   mux {
+   groups = "eth_mdio_y",
+  "eth_mdc_y",
+  "eth_rgmii_rx_clk_y",
+  "eth_rx_dv_y",
+  "eth_rxd0_y",
+  "eth_rxd1_y",
+  "eth_rxd2_rgmii",
+  "eth_rxd3_rgmii",
+  "eth_rgmii_tx_clk",
+  "eth_txen_y",
+  "eth_txd0_y",
+  "eth_txd1_y",
+  "eth_txd2_rgmii",
+  "eth_txd3_rgmii";
+   function = "eth";
+   };
+   };
+
pwm_a_a_pins: pwm_a_a {
mux {
groups = "pwm_a_a";
-- 
2.15.1

[PATCH v4 1/2] ARM64: dts: meson-axg: add ethernet mac controller

[Yixun Lan]

Add DT info for the stmmac ethernet MAC which found in
the Amlogic's Meson-AXG SoC, also describe the ethernet
pinctrl & clock information here.

Reviewed-by: Neil Armstrong 
Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 54 ++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index d288d4724ae3..dea1bc31b4de 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
compatible = "amlogic,meson-axg";
@@ -155,6 +156,19 @@
};
};
 
+   ethmac: ethernet@ff3f {
+   compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
+   reg = <0x0 0xff3f 0x0 0x1
+   0x0 0xff634540 0x0 0x8>;
+   interrupts = ;
+   interrupt-names = "macirq";
+   clocks = < CLKID_ETH>,
+< CLKID_FCLK_DIV2>,
+< CLKID_MPLL2>;
+   clock-names = "stmmaceth", "clkin0", "clkin1";
+   status = "disabled";
+   };
+
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
reg = <0x0 0xffc01000 0 0x1000>,
@@ -215,6 +229,46 @@
gpio-ranges = <_periphs 0 0 86>;
};
 
+   eth_rgmii_x_pins: eth-x-rgmii {
+   mux {
+   groups = "eth_mdio_x",
+  "eth_mdc_x",
+  "eth_rgmii_rx_clk_x",
+  "eth_rx_dv_x",
+  "eth_rxd0_x",
+  "eth_rxd1_x",
+  "eth_rxd2_rgmii",
+  "eth_rxd3_rgmii",
+  "eth_rgmii_tx_clk",
+  "eth_txen_x",
+  "eth_txd0_x",
+  "eth_txd1_x",
+  "eth_txd2_rgmii",
+  "eth_txd3_rgmii";
+   function = "eth";
+   };
+   };
+
+   eth_rgmii_y_pins: eth-y-rgmii {
+   mux {
+   groups = "eth_mdio_y",
+  "eth_mdc_y",
+  "eth_rgmii_rx_clk_y",
+  "eth_rx_dv_y",
+  "eth_rxd0_y",
+  "eth_rxd1_y",
+  "eth_rxd2_rgmii",
+  "eth_rxd3_rgmii",
+  "eth_rgmii_tx_clk",
+  "eth_txen_y",
+  "eth_txd0_y",
+  "eth_txd1_y",
+  "eth_txd2_rgmii",
+  "eth_txd3_rgmii";
+   function = "eth";
+   };
+   };
+
pwm_a_a_pins: pwm_a_a {
mux {
groups = "pwm_a_a";
-- 
2.15.1

[PATCH v4 2/2] ARM64: dts: meson-axg: enable ethernet for A113D S400 board

[Yixun Lan]

This is tested in the S400 dev board which use a RTL8211F PHY,
and the pins connect to the 'eth_rgmii_y_pins' group.

Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..8932654f5090 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -17,6 +17,13 @@
};
 };
 
+ {
+   status = "okay";
+   phy-mode = "rgmii";
+   pinctrl-0 = <_rgmii_y_pins>;
+   pinctrl-names = "default";
+};
+
 _AO {
status = "okay";
 };
-- 
2.15.1

[PATCH v4 2/2] ARM64: dts: meson-axg: enable ethernet for A113D S400 board

[Yixun Lan]

This is tested in the S400 dev board which use a RTL8211F PHY,
and the pins connect to the 'eth_rgmii_y_pins' group.

Reviewed-by: Neil Armstrong 
Signed-off-by: Yixun Lan 
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..8932654f5090 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -17,6 +17,13 @@
};
 };
 
+ {
+   status = "okay";
+   phy-mode = "rgmii";
+   pinctrl-0 = <_rgmii_y_pins>;
+   pinctrl-names = "default";
+};
+
 _AO {
status = "okay";
 };
-- 
2.15.1

[PATCH v4 0/2] Add ethernet support for Meson-AXG SoC

[Yixun Lan]

This series try to add support for the ethernet MAC controller
found in Meson-AXG SoC, and also enable it in the S400 board.

Hi Kevin:
  You still need to at least merge the clock patch[3] in order to
compile the DTS, or just merge the tag from meson-clock's tree[6]
- the tag is 'meson-clk-for-v4.16-2', since the clock part already
taken there.


Changes in v4 since [5]:
 - rebase to kevin's v4.16/dt64
 - fix order

Changes in v3 since [4]:
 - put clock DT info in soc.dtsi
 - separate DT for 'add support for the controller' vs 'enable in board'

Changes in v2 since [1]:
 - rebase to kevin's v4.16/dt64 branch
 - add Neil's Reviewed-by
 - move clock info to board.dts instead of in soc.dtsi
 - drop "meson-axg-dwmac" compatible string, since we didn't use this
   we could re-add it later when we really need.
 - note: to make ethernet work properly,it depend on clock & pinctrl[2],
   to compile the DTS, the patch [3] is required.
   the code part will be taken via clock & pinctrl subsystem tree.

[5]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005783.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005784.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005785.html

[4]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005768.html

[1]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005301.html

[2]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005735.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005694.html

[3]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005738.html

[6] git://github.com/BayLibre/clk-meson.git

Yixun Lan (2):
  ARM64: dts: meson-axg: add ethernet mac controller
  ARM64: dts: meson-axg: enable ethernet for A113D S400 board

 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |  7 
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 54 ++
 2 files changed, 61 insertions(+)

-- 
2.15.1

[PATCH v4 0/2] Add ethernet support for Meson-AXG SoC

[Yixun Lan]

This series try to add support for the ethernet MAC controller
found in Meson-AXG SoC, and also enable it in the S400 board.

Hi Kevin:
  You still need to at least merge the clock patch[3] in order to
compile the DTS, or just merge the tag from meson-clock's tree[6]
- the tag is 'meson-clk-for-v4.16-2', since the clock part already
taken there.


Changes in v4 since [5]:
 - rebase to kevin's v4.16/dt64
 - fix order

Changes in v3 since [4]:
 - put clock DT info in soc.dtsi
 - separate DT for 'add support for the controller' vs 'enable in board'

Changes in v2 since [1]:
 - rebase to kevin's v4.16/dt64 branch
 - add Neil's Reviewed-by
 - move clock info to board.dts instead of in soc.dtsi
 - drop "meson-axg-dwmac" compatible string, since we didn't use this
   we could re-add it later when we really need.
 - note: to make ethernet work properly,it depend on clock & pinctrl[2],
   to compile the DTS, the patch [3] is required.
   the code part will be taken via clock & pinctrl subsystem tree.

[5]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005783.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005784.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005785.html

[4]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005768.html

[1]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005301.html

[2]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005735.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005694.html

[3]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005738.html

[6] git://github.com/BayLibre/clk-meson.git

Yixun Lan (2):
  ARM64: dts: meson-axg: add ethernet mac controller
  ARM64: dts: meson-axg: enable ethernet for A113D S400 board

 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |  7 
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 54 ++
 2 files changed, 61 insertions(+)

-- 
2.15.1

Re: [PATCH v3 1/2] ARM64: dts: meson-axg: add ethernet mac controller

[Yixun Lan]

HI Kevin


On 12/16/2017 03:29 AM, Kevin Hilman wrote:
> Yixun Lan <yixun@amlogic.com> writes:
> 
>> Add DT info for the stmmac ethernet MAC which found in
>> the Amlogic's Meson-AXG SoC, also describe the ethernet
>> pinctrl & clock information here.
>>
>> Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
>> Signed-off-by: Yixun Lan <yixun@amlogic.com>
> 
> This patch does not apply, and dependencies are not described.
> 
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 54 
>> ++
>>  1 file changed, 54 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
>> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index d356ce74ad89..94c497b7 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -7,6 +7,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  
>>  / {
>>  compatible = "amlogic,meson-axg";
>> @@ -148,6 +149,19 @@
>>  #address-cells = <0>;
>>  };
>>  
>> +ethmac: ethernet@ff3f {
>> +compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
>> +reg = <0x0 0xff3f 0x0 0x1
>> +0x0 0xff634540 0x0 0x8>;
>> +interrupts = ;
>> +interrupt-names = "macirq";
>> +clocks = < CLKID_ETH>,
>> + < CLKID_FCLK_DIV2>,
>> + < CLKID_MPLL2>;
>> +clock-names = "stmmaceth", "clkin0", "clkin1";
>> +status = "disabled";
>> +};
>> +
>>  hiubus: bus@ff63c000 {
>>  compatible = "simple-bus";
>>  reg = <0x0 0xff63c000 0x0 0x1c00>;
> 
> Based on the hiubus node, presumably this depends on the patch from the
> clock series.
> 
yes, it depend on clock, also the pinctrl patch

>> @@ -194,6 +208,46 @@
>>  #gpio-cells = <2>;
>>  gpio-ranges = <_periphs 0 0 86>;
>>  };
> 
> I'm not sure where this part is coming from, but it causes the rest of
> it to not apply.
> 
> Please be sure to describe all dependencies.
> 
.
exactly, it depend on pinctrl

actually, once you apply the clock & pinctrl DT patch, this one should
go fine. I will send another v4 which base on your recent v4.16/dt64
branch for your convenience.

Yixun

Re: [PATCH v3 1/2] ARM64: dts: meson-axg: add ethernet mac controller

[Yixun Lan]

HI Kevin


On 12/16/2017 03:29 AM, Kevin Hilman wrote:
> Yixun Lan  writes:
> 
>> Add DT info for the stmmac ethernet MAC which found in
>> the Amlogic's Meson-AXG SoC, also describe the ethernet
>> pinctrl & clock information here.
>>
>> Reviewed-by: Neil Armstrong 
>> Signed-off-by: Yixun Lan 
> 
> This patch does not apply, and dependencies are not described.
> 
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 54 
>> ++
>>  1 file changed, 54 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
>> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index d356ce74ad89..94c497b7 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -7,6 +7,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  
>>  / {
>>  compatible = "amlogic,meson-axg";
>> @@ -148,6 +149,19 @@
>>  #address-cells = <0>;
>>  };
>>  
>> +ethmac: ethernet@ff3f {
>> +compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
>> +reg = <0x0 0xff3f 0x0 0x1
>> +0x0 0xff634540 0x0 0x8>;
>> +interrupts = ;
>> +interrupt-names = "macirq";
>> +clocks = < CLKID_ETH>,
>> + < CLKID_FCLK_DIV2>,
>> + < CLKID_MPLL2>;
>> +clock-names = "stmmaceth", "clkin0", "clkin1";
>> +status = "disabled";
>> +};
>> +
>>  hiubus: bus@ff63c000 {
>>  compatible = "simple-bus";
>>  reg = <0x0 0xff63c000 0x0 0x1c00>;
> 
> Based on the hiubus node, presumably this depends on the patch from the
> clock series.
> 
yes, it depend on clock, also the pinctrl patch

>> @@ -194,6 +208,46 @@
>>  #gpio-cells = <2>;
>>  gpio-ranges = <_periphs 0 0 86>;
>>  };
> 
> I'm not sure where this part is coming from, but it causes the rest of
> it to not apply.
> 
> Please be sure to describe all dependencies.
> 
.
exactly, it depend on pinctrl

actually, once you apply the clock & pinctrl DT patch, this one should
go fine. I will send another v4 which base on your recent v4.16/dt64
branch for your convenience.

Yixun

Re: [PATCH v4 0/2] dt: add pinctrl driver for Meson-AXG SoC

[Yixun Lan]

On 12/16/2017 03:48 AM, Kevin Hilman wrote:
> Yixun Lan <yixun@amlogic.com> writes:
> 
>> This is DT part patchset for adding pinctrl support for
>> the Amlogic's Meson-AXG SoC.
>>   
>> Changes since v3 at [3]
>>   -- rebase to khilman's v4.16/dt64 branch and re-send
>>   -- add Rob's Ack
>>
>> Changes since v2 at [2]:
>>   -- Resend this patch series due to fail to send patch [2/2]
>>
>> Changes since v1 at [1]:
>>   -- Separate DT part patches
>>   -- Add Neil Armstrong's Ack
>>
>> [3]
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005392.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005393.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005394.html
>>
>> [2]
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005390.html
>>
>> [1] 
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005270.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005271.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005272.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005273.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005274.html
>>
>> Xingyu Chen (2):
>>   documentation: Add compatibles for Amlogic Meson AXG pin controllers
>>   ARM64: dts: meson-axg: add pinctrl DT info for Meson-AXG SoC
> 
> Applied both to v4.14/dt64
> 
> Normally, the documentation patch should go with the driver, but since
> Linus has already merged the driver, this time I'll take it with the DT
> itself.
> 

Hi Kevin
 sorry, I just checked Linus' pinctrl tree - the for-next branch, the
documentation patch is already taken there. so probably you could drop
it here?

Yixun

Re: [PATCH v4 0/2] dt: add pinctrl driver for Meson-AXG SoC

[Yixun Lan]

On 12/16/2017 03:48 AM, Kevin Hilman wrote:
> Yixun Lan  writes:
> 
>> This is DT part patchset for adding pinctrl support for
>> the Amlogic's Meson-AXG SoC.
>>   
>> Changes since v3 at [3]
>>   -- rebase to khilman's v4.16/dt64 branch and re-send
>>   -- add Rob's Ack
>>
>> Changes since v2 at [2]:
>>   -- Resend this patch series due to fail to send patch [2/2]
>>
>> Changes since v1 at [1]:
>>   -- Separate DT part patches
>>   -- Add Neil Armstrong's Ack
>>
>> [3]
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005392.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005393.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005394.html
>>
>> [2]
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005390.html
>>
>> [1] 
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005270.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005271.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005272.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005273.html
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005274.html
>>
>> Xingyu Chen (2):
>>   documentation: Add compatibles for Amlogic Meson AXG pin controllers
>>   ARM64: dts: meson-axg: add pinctrl DT info for Meson-AXG SoC
> 
> Applied both to v4.14/dt64
> 
> Normally, the documentation patch should go with the driver, but since
> Linus has already merged the driver, this time I'll take it with the DT
> itself.
> 

Hi Kevin
 sorry, I just checked Linus' pinctrl tree - the for-next branch, the
documentation patch is already taken there. so probably you could drop
it here?

Yixun

Re: [PATCH v3] ARM64: dts: meson-axg: enable IR controller

[Yixun Lan]

Hi Jerome


On 12/15/2017 11:01 PM, Jerome Brunet wrote:
> On Fri, 2017-12-15 at 22:59 +0800, Yixun Lan wrote:
>> Enable IR remote controller which found in Amlogic's Meson-AXG SoCs.
>>
>> Signed-off-by: Yixun Lan <yixun@amlogic.com>
>>
>> ---
>>
>> Changes since v2 at [2]
>>  - rebase to Kevin's v4.16/dt64 branch
>>  - this patch depend on pinctrl DT driver
>>
>> Changes since v1 at [1]:
>>  - drop the compatbile 'amlogic,meson-gx-ir'
>>
>> [2]
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005574.html
>>
>> [1]
>>  http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005527.html
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |  6 ++
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 14 ++
>>  2 files changed, 20 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
>> b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
>> index 70eca1f8736a..e85fb665f12e 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
>> @@ -20,3 +20,9 @@
>>  _AO {
>>  status = "okay";
>>  };
>> +
>> + {
>> +status = "okay";
>> +pinctrl-0 = <_input_ao_pins>;
>> +pinctrl-names = "default";
>> +};
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
>> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index a0d7b10da512..1cd34141a5c1 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -223,6 +223,13 @@
>>  #gpio-cells = <2>;
>>  gpio-ranges = <_aobus 0 0 15>;
>>  };
>> +
>> +remote_input_ao_pins: remote_input_ao {
>> +mux {
>> +groups = "remote_input_ao";
>> +function = "remote_input_ao";
>> +};
>> +};
>>  };
>>  
>>  uart_AO: serial@3000 {
>> @@ -242,6 +249,13 @@
>>  clock-names = "xtal", "pclk", "baud";
>>  status = "disabled";
>>  };
>> +
>> +ir: ir@8000 {
>> +compatible = "amlogic,meson-gxbb-ir";
> 
> compatible = "amlogic,meson-axg-ir", "amlogic,meson-gxbb-ir";
> 
> please (and the binding doc patch)

what's the policy for adding new compatible string?

is this a must even we don't use it for now?
or what's the problem if adding it when we really need it

> 
>> +reg = <0x0 0x8000 0x0 0x20>;
>> +interrupts = ;
>> +status = "disabled";
>> +};
>>  };
>>  };
>>  };
> 
> .
> 

Re: [PATCH v3] ARM64: dts: meson-axg: enable IR controller

[Yixun Lan]

Hi Jerome


On 12/15/2017 11:01 PM, Jerome Brunet wrote:
> On Fri, 2017-12-15 at 22:59 +0800, Yixun Lan wrote:
>> Enable IR remote controller which found in Amlogic's Meson-AXG SoCs.
>>
>> Signed-off-by: Yixun Lan 
>>
>> ---
>>
>> Changes since v2 at [2]
>>  - rebase to Kevin's v4.16/dt64 branch
>>  - this patch depend on pinctrl DT driver
>>
>> Changes since v1 at [1]:
>>  - drop the compatbile 'amlogic,meson-gx-ir'
>>
>> [2]
>> http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005574.html
>>
>> [1]
>>  http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005527.html
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |  6 ++
>>  arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 14 ++
>>  2 files changed, 20 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
>> b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
>> index 70eca1f8736a..e85fb665f12e 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
>> @@ -20,3 +20,9 @@
>>  _AO {
>>  status = "okay";
>>  };
>> +
>> + {
>> +status = "okay";
>> +pinctrl-0 = <_input_ao_pins>;
>> +pinctrl-names = "default";
>> +};
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
>> b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> index a0d7b10da512..1cd34141a5c1 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>> @@ -223,6 +223,13 @@
>>  #gpio-cells = <2>;
>>  gpio-ranges = <_aobus 0 0 15>;
>>  };
>> +
>> +remote_input_ao_pins: remote_input_ao {
>> +mux {
>> +groups = "remote_input_ao";
>> +function = "remote_input_ao";
>> +};
>> +};
>>  };
>>  
>>  uart_AO: serial@3000 {
>> @@ -242,6 +249,13 @@
>>  clock-names = "xtal", "pclk", "baud";
>>  status = "disabled";
>>  };
>> +
>> +ir: ir@8000 {
>> +compatible = "amlogic,meson-gxbb-ir";
> 
> compatible = "amlogic,meson-axg-ir", "amlogic,meson-gxbb-ir";
> 
> please (and the binding doc patch)

what's the policy for adding new compatible string?

is this a must even we don't use it for now?
or what's the problem if adding it when we really need it

> 
>> +reg = <0x0 0x8000 0x0 0x20>;
>> +interrupts = ;
>> +status = "disabled";
>> +};
>>  };
>>  };
>>  };
> 
> .
> 

[PATCH v3] ARM64: dts: meson-axg: enable IR controller

[Yixun Lan]

Enable IR remote controller which found in Amlogic's Meson-AXG SoCs.

Signed-off-by: Yixun Lan <yixun@amlogic.com>

---

Changes since v2 at [2]
 - rebase to Kevin's v4.16/dt64 branch
 - this patch depend on pinctrl DT driver

Changes since v1 at [1]:
 - drop the compatbile 'amlogic,meson-gx-ir'

[2]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005574.html

[1]
 http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005527.html
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |  6 ++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 14 ++
 2 files changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..e85fb665f12e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -20,3 +20,9 @@
 _AO {
status = "okay";
 };
+
+ {
+   status = "okay";
+   pinctrl-0 = <_input_ao_pins>;
+   pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index a0d7b10da512..1cd34141a5c1 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -223,6 +223,13 @@
#gpio-cells = <2>;
gpio-ranges = <_aobus 0 0 15>;
};
+
+   remote_input_ao_pins: remote_input_ao {
+   mux {
+   groups = "remote_input_ao";
+   function = "remote_input_ao";
+   };
+   };
};
 
uart_AO: serial@3000 {
@@ -242,6 +249,13 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+   ir: ir@8000 {
+   compatible = "amlogic,meson-gxbb-ir";
+   reg = <0x0 0x8000 0x0 0x20>;
+   interrupts = ;
+   status = "disabled";
+   };
};
};
 };
-- 
2.15.1

[PATCH v3] ARM64: dts: meson-axg: enable IR controller

[Yixun Lan]

Enable IR remote controller which found in Amlogic's Meson-AXG SoCs.

Signed-off-by: Yixun Lan 

---

Changes since v2 at [2]
 - rebase to Kevin's v4.16/dt64 branch
 - this patch depend on pinctrl DT driver

Changes since v1 at [1]:
 - drop the compatbile 'amlogic,meson-gx-ir'

[2]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005574.html

[1]
 http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005527.html
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |  6 ++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 14 ++
 2 files changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..e85fb665f12e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -20,3 +20,9 @@
 _AO {
status = "okay";
 };
+
+ {
+   status = "okay";
+   pinctrl-0 = <_input_ao_pins>;
+   pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index a0d7b10da512..1cd34141a5c1 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -223,6 +223,13 @@
#gpio-cells = <2>;
gpio-ranges = <_aobus 0 0 15>;
};
+
+   remote_input_ao_pins: remote_input_ao {
+   mux {
+   groups = "remote_input_ao";
+   function = "remote_input_ao";
+   };
+   };
};
 
uart_AO: serial@3000 {
@@ -242,6 +249,13 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+   ir: ir@8000 {
+   compatible = "amlogic,meson-gxbb-ir";
+   reg = <0x0 0x8000 0x0 0x20>;
+   interrupts = ;
+   status = "disabled";
+   };
};
};
 };
-- 
2.15.1

[PATCH v2] ARM64: dts: meson-axg: add the SPICC controller

[Yixun Lan]

From: Sunny Luo <sunny@amlogic.com>

Add DT info for the SPICC controller which found in
the Amlogic's Meson-AXG SoC.

Signed-off-by: Sunny Luo <sunny@amlogic.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>

---
Changes int v2 since [1]
 - rebase to Kevin's tree, branch v4.16/dt64
 - this patch depend on clock & pinctrl DT patch

[1]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005495.html
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 93 ++
 1 file changed, 93 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index d356ce74ad89..d33721005748 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
compatible = "amlogic,meson-axg";
@@ -120,6 +121,28 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffd0 0x0 0x25000>;
 
+   spicc0: spi@13000 {
+   compatible = "amlogic,meson-axg-spicc";
+   reg = <0x0 0x13000 0x0 0x3c>;
+   interrupts = ;
+   clocks = < CLKID_SPICC0>;
+   clock-names = "core";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   spicc1: spi@15000 {
+   compatible = "amlogic,meson-axg-spicc";
+   reg = <0x0 0x15000 0x0 0x3c>;
+   interrupts = ;
+   clocks = < CLKID_SPICC1>;
+   clock-names = "core";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
reg = <0x0 0x24000 0x0 0x14>;
@@ -194,6 +217,76 @@
#gpio-cells = <2>;
gpio-ranges = <_periphs 0 0 86>;
};
+
+   spi0_pins: spi0 {
+   mux {
+   groups = "spi0_miso",
+   "spi0_mosi",
+   "spi0_clk";
+   function = "spi0";
+   };
+   };
+
+   spi0_ss0_pins: spi0_ss0 {
+   mux {
+   groups = "spi0_ss0";
+   function = "spi0";
+   };
+   };
+
+   spi0_ss1_pins: spi0_ss1 {
+   mux {
+   groups = "spi0_ss1";
+   function = "spi0";
+   };
+   };
+
+   spi0_ss2_pins: spi0_ss2 {
+   mux {
+   groups = "spi0_ss2";
+   function = "spi0";
+   };
+   };
+
+
+   spi1_a_pins: spi1_a {
+   mux {
+   groups = "spi1_miso_a",
+   "spi1_mosi_a",
+   "spi1_clk_a";
+   function = "spi1";
+   };
+   };
+
+   spi1_ss0_a_pins: spi1_ss0_a {
+   mux {
+   groups = "spi1_ss0_a";
+   

[PATCH v2] ARM64: dts: meson-axg: add the SPICC controller

[Yixun Lan]

From: Sunny Luo 

Add DT info for the SPICC controller which found in
the Amlogic's Meson-AXG SoC.

Signed-off-by: Sunny Luo 
Signed-off-by: Yixun Lan 

---
Changes int v2 since [1]
 - rebase to Kevin's tree, branch v4.16/dt64
 - this patch depend on clock & pinctrl DT patch

[1]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005495.html
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 93 ++
 1 file changed, 93 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index d356ce74ad89..d33721005748 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
compatible = "amlogic,meson-axg";
@@ -120,6 +121,28 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffd0 0x0 0x25000>;
 
+   spicc0: spi@13000 {
+   compatible = "amlogic,meson-axg-spicc";
+   reg = <0x0 0x13000 0x0 0x3c>;
+   interrupts = ;
+   clocks = < CLKID_SPICC0>;
+   clock-names = "core";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   spicc1: spi@15000 {
+   compatible = "amlogic,meson-axg-spicc";
+   reg = <0x0 0x15000 0x0 0x3c>;
+   interrupts = ;
+   clocks = < CLKID_SPICC1>;
+   clock-names = "core";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart", 
"amlogic,meson-uart";
reg = <0x0 0x24000 0x0 0x14>;
@@ -194,6 +217,76 @@
#gpio-cells = <2>;
gpio-ranges = <_periphs 0 0 86>;
};
+
+   spi0_pins: spi0 {
+   mux {
+   groups = "spi0_miso",
+   "spi0_mosi",
+   "spi0_clk";
+   function = "spi0";
+   };
+   };
+
+   spi0_ss0_pins: spi0_ss0 {
+   mux {
+   groups = "spi0_ss0";
+   function = "spi0";
+   };
+   };
+
+   spi0_ss1_pins: spi0_ss1 {
+   mux {
+   groups = "spi0_ss1";
+   function = "spi0";
+   };
+   };
+
+   spi0_ss2_pins: spi0_ss2 {
+   mux {
+   groups = "spi0_ss2";
+   function = "spi0";
+   };
+   };
+
+
+   spi1_a_pins: spi1_a {
+   mux {
+   groups = "spi1_miso_a",
+   "spi1_mosi_a",
+   "spi1_clk_a";
+   function = "spi1";
+   };
+   };
+
+   spi1_ss0_a_pins: spi1_ss0_a {
+   mux {
+   groups = "spi1_ss0_a";
+   function = "spi1";
+   };
+   };
+
+   spi1_ss