[PATCH] mmc: dw_mmc-k3: Fix DDR52 mode by setting required clock divisor

[oscardagrach]

Signed-off-by: oscardagrach 
---
 drivers/mmc/host/dw_mmc-k3.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
index 89cdb3d533bb..efc546cb4db8 100644
--- a/drivers/mmc/host/dw_mmc-k3.c
+++ b/drivers/mmc/host/dw_mmc-k3.c
@@ -194,8 +194,14 @@ static void dw_mci_hi6220_set_ios(struct dw_mci *host, 
struct mmc_ios *ios)
int ret;
unsigned int clock;
 
-   clock = (ios->clock <= 2500) ? 2500 : ios->clock;
-
+   /* CLKDIV must be 1 for DDR52/8-bit mode */
+   if (ios->bus_width == MMC_BUS_WIDTH_8 &&
+   ios->timing == MMC_TIMING_MMC_DDR52) {
+   mci_writel(host, CLKDIV, 0x1);
+   clock = ios->clock;
+   } else {
+   clock = (ios->clock <= 2500) ? 2500 : ios->clock;
+   }
ret = clk_set_rate(host->biu_clk, clock);
if (ret)
dev_warn(host->dev, "failed to set rate %uHz\n", clock);
-- 
2.11.0

[PATCH] arm64: dts: hikey: Enable HS200 mode on eMMC

[oscardagrach]

According to the hi6220 datasheet, the MMC controller is JEDEC eMMC 4.5
compliant, in addition to supporting a clock of up to 150MHz. The Hikey
schematic also indicates the device utilizes 1.8v signaling. Define these
parameters in the device tree to enable HS200 mode.

Signed-off-by: Ryan Grachek 
---
 arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts 
b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index 3aee6123d161..964e43e05ac6 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -299,7 +299,9 @@
/* GPIO blocks 16 thru 19 do not appear to be routed to pins */
 
dwmmc_0: dwmmc0@f723d000 {
+   max-frequency = <15000>;
cap-mmc-highspeed;
+   mmc-hs200-1_8v;
non-removable;
bus-width = <0x8>;
vmmc-supply = <&ldo19>;
-- 
2.11.0