Re: [PATCH] net: stmmac: dwmac-meson8b: fix mask definition of the m250_sel mux

2020-12-07 Thread Jakub Kicinski 
On Mon, 07 Dec 2020 10:31:46 +0100 Jerome Brunet wrote:
> > The m250_sel mux clock uses bit 4 in the PRG_ETH0 register. Fix this by
> > shifting the PRG_ETH0_CLK_M250_SEL_MASK accordingly as the "mask" in
> > struct clk_mux expects the mask relative to the "shift" field in the
> > same struct.
> >
> > While here, get rid of the PRG_ETH0_CLK_M250_SEL_SHIFT macro and use
> > __ffs() to determine it from the existing PRG_ETH0_CLK_M250_SEL_MASK
> > macro.
> >
> > Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic 
> > Meson 8b / GXBB DWMAC")
> > Signed-off-by: Martin Blumenstingl   
> 
> Reviewed-by: Jerome Brunet 

Applied, thanks!

Re: [PATCH] net: stmmac: dwmac-meson8b: fix mask definition of the m250_sel mux

2020-12-07 Thread Jerome Brunet 


On Sat 05 Dec 2020 at 22:32, Martin Blumenstingl 
 wrote:

> The m250_sel mux clock uses bit 4 in the PRG_ETH0 register. Fix this by
> shifting the PRG_ETH0_CLK_M250_SEL_MASK accordingly as the "mask" in
> struct clk_mux expects the mask relative to the "shift" field in the
> same struct.
>
> While here, get rid of the PRG_ETH0_CLK_M250_SEL_SHIFT macro and use
> __ffs() to determine it from the existing PRG_ETH0_CLK_M250_SEL_MASK
> macro.
>
> Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 
> 8b / GXBB DWMAC")
> Signed-off-by: Martin Blumenstingl 

Reviewed-by: Jerome Brunet 

> ---
>  drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c 
> b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> index dc0b8b6d180d..459ae715b33d 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
> @@ -30,7 +30,6 @@
>  #define PRG_ETH0_EXT_RMII_MODE   4
>  
>  /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
> -#define PRG_ETH0_CLK_M250_SEL_SHIFT  4
>  #define PRG_ETH0_CLK_M250_SEL_MASK   GENMASK(4, 4)
>  
>  /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
> @@ -155,8 +154,9 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac 
> *dwmac)
>   return -ENOMEM;
>  
>   clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
> - clk_configs->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT;
> - clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK;
> + clk_configs->m250_mux.shift = __ffs(PRG_ETH0_CLK_M250_SEL_MASK);
> + clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK >>
> +  clk_configs->m250_mux.shift;
>   clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parents,
>ARRAY_SIZE(mux_parents), _mux_ops,
>_configs->m250_mux.hw);

[PATCH] net: stmmac: dwmac-meson8b: fix mask definition of the m250_sel mux

2020-12-05 Thread Martin Blumenstingl 
The m250_sel mux clock uses bit 4 in the PRG_ETH0 register. Fix this by
shifting the PRG_ETH0_CLK_M250_SEL_MASK accordingly as the "mask" in
struct clk_mux expects the mask relative to the "shift" field in the
same struct.

While here, get rid of the PRG_ETH0_CLK_M250_SEL_SHIFT macro and use
__ffs() to determine it from the existing PRG_ETH0_CLK_M250_SEL_MASK
macro.

Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b 
/ GXBB DWMAC")
Signed-off-by: Martin Blumenstingl 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index dc0b8b6d180d..459ae715b33d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -30,7 +30,6 @@
 #define PRG_ETH0_EXT_RMII_MODE 4
 
 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
-#define PRG_ETH0_CLK_M250_SEL_SHIFT4
 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
 
 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
@@ -155,8 +154,9 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac 
*dwmac)
return -ENOMEM;
 
clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
-   clk_configs->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT;
-   clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK;
+   clk_configs->m250_mux.shift = __ffs(PRG_ETH0_CLK_M250_SEL_MASK);
+   clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK >>
+clk_configs->m250_mux.shift;
clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parents,
 ARRAY_SIZE(mux_parents), _mux_ops,
 _configs->m250_mux.hw);
-- 
2.29.2