Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
On Thu, May 2, 2019 at 2:40 PM Sudeep Holla wrote: > > > Sorry if I created confusion. I just wanted a note saying all the properties > in ePAPR/DeviceTree specification applies for this platform. That would > help me check if the standard cacheinfo infrastruction works as is or not. Sure, will add this note. - Yash > > -- > Regards, > Sudeep
Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
On Thu, May 02, 2019 at 10:50:12AM +0530, Yash Shah wrote: > On Thu, May 2, 2019 at 6:11 AM Rob Herring wrote: > > > > On Tue, Apr 30, 2019 at 09:50:45AM +0530, Yash Shah wrote: > > > On Fri, Apr 26, 2019 at 3:04 PM Sudeep Holla wrote: > > > > > > > > On Fri, Apr 26, 2019 at 11:20:17AM +0530, Yash Shah wrote: > > > > > On Thu, Apr 25, 2019 at 3:43 PM Sudeep Holla > > > > > wrote: > > > > > > > > > > > > On Thu, Apr 25, 2019 at 11:24:55AM +0530, Yash Shah wrote: > > > > > > > Add device tree bindings for SiFive FU540 L2 cache controller > > > > > > > driver > > > > > > > > > > > > > > Signed-off-by: Yash Shah > > > > > > > --- > > > > > > > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 > > > > > > > ++ > > > > > > > 1 file changed, 53 insertions(+) > > > > > > > create mode 100644 > > > > > > > Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > > > > > > > > diff --git > > > > > > > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > new file mode 100644 > > > > > > > index 000..15132e2 > > > > > > > --- /dev/null > > > > > > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > @@ -0,0 +1,53 @@ > > > > > > > +SiFive L2 Cache Controller > > > > > > > +-- > > > > > > > +The SiFive Level 2 Cache Controller is used to provide access to > > > > > > > fast copies > > > > > > > +of memory for masters in a Core Complex. The Level 2 Cache > > > > > > > Controller also > > > > > > > +acts as directory-based coherency manager. > > > > > > > + > > > > > > > +Required Properties: > > > > > > > + > > > > > > > +- compatible: Should be "sifive,fu540-c000-ccache" > > > > > > > + > > > > > > > +- cache-block-size: Specifies the block size in bytes of the > > > > > > > cache > > > > > > > + > > > > > > > +- cache-level: Should be set to 2 for a level 2 cache > > > > > > > + > > > > > > > +- cache-sets: Specifies the number of associativity sets of the > > > > > > > cache > > > > > > > + > > > > > > > +- cache-size: Specifies the size in bytes of the cache > > > > > > > + > > > > > > > +- cache-unified: Specifies the cache is a unified cache > > > > > > > + > > > > > > > +- interrupt-parent: Must be core interrupt controller > > > > > > > + > > > > > > > +- interrupts: Must contain 3 entries (DirError, DataError and > > > > > > > DataFail signals) > > > > > > > + > > > > > > > +- reg: Physical base address and size of L2 cache controller > > > > > > > registers map > > > > > > > + > > > > > > > +- reg-names: Should be "control" > > > > > > > + > > > > > > > > > > > > It would be good if you mark the properties that are present in DT > > > > > > specification and those that are added for sifive,fu540-c000-ccache > > > > > > > > > > I believe there isn't any property which is added explicitly for > > > > > sifive,fu540-c000-ccache. > > > > > > > > > > > > > reg and interrupts are generally optional for normal cache and may be > > > > required for cache controller like this. DT specification[1] covers > > > > only caches and not cache controllers. > > > > > > Are you suggesting something like this: > > > > > > Required Properties: > > > > > > Standard Properties: > > > > I don't think we need this separation. > > Ok. Won't include this "Standard/Non-standard properties" separation > in the next revision of this patch. > Sorry if I created confusion. I just wanted a note saying all the properties in ePAPR/DeviceTree specification applies for this platform. That would help me check if the standard cacheinfo infrastruction works as is or not. -- Regards, Sudeep
Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
On Thu, May 2, 2019 at 6:11 AM Rob Herring wrote: > > On Tue, Apr 30, 2019 at 09:50:45AM +0530, Yash Shah wrote: > > On Fri, Apr 26, 2019 at 3:04 PM Sudeep Holla wrote: > > > > > > On Fri, Apr 26, 2019 at 11:20:17AM +0530, Yash Shah wrote: > > > > On Thu, Apr 25, 2019 at 3:43 PM Sudeep Holla > > > > wrote: > > > > > > > > > > On Thu, Apr 25, 2019 at 11:24:55AM +0530, Yash Shah wrote: > > > > > > Add device tree bindings for SiFive FU540 L2 cache controller driver > > > > > > > > > > > > Signed-off-by: Yash Shah > > > > > > --- > > > > > > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 > > > > > > ++ > > > > > > 1 file changed, 53 insertions(+) > > > > > > create mode 100644 > > > > > > Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > > > > > > diff --git > > > > > > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > new file mode 100644 > > > > > > index 000..15132e2 > > > > > > --- /dev/null > > > > > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > @@ -0,0 +1,53 @@ > > > > > > +SiFive L2 Cache Controller > > > > > > +-- > > > > > > +The SiFive Level 2 Cache Controller is used to provide access to > > > > > > fast copies > > > > > > +of memory for masters in a Core Complex. The Level 2 Cache > > > > > > Controller also > > > > > > +acts as directory-based coherency manager. > > > > > > + > > > > > > +Required Properties: > > > > > > + > > > > > > +- compatible: Should be "sifive,fu540-c000-ccache" > > > > > > + > > > > > > +- cache-block-size: Specifies the block size in bytes of the cache > > > > > > + > > > > > > +- cache-level: Should be set to 2 for a level 2 cache > > > > > > + > > > > > > +- cache-sets: Specifies the number of associativity sets of the > > > > > > cache > > > > > > + > > > > > > +- cache-size: Specifies the size in bytes of the cache > > > > > > + > > > > > > +- cache-unified: Specifies the cache is a unified cache > > > > > > + > > > > > > +- interrupt-parent: Must be core interrupt controller > > > > > > + > > > > > > +- interrupts: Must contain 3 entries (DirError, DataError and > > > > > > DataFail signals) > > > > > > + > > > > > > +- reg: Physical base address and size of L2 cache controller > > > > > > registers map > > > > > > + > > > > > > +- reg-names: Should be "control" > > > > > > + > > > > > > > > > > It would be good if you mark the properties that are present in DT > > > > > specification and those that are added for sifive,fu540-c000-ccache > > > > > > > > I believe there isn't any property which is added explicitly for > > > > sifive,fu540-c000-ccache. > > > > > > > > > > reg and interrupts are generally optional for normal cache and may be > > > required for cache controller like this. DT specification[1] covers > > > only caches and not cache controllers. > > > > Are you suggesting something like this: > > > > Required Properties: > > > > Standard Properties: > > I don't think we need this separation. Ok. Won't include this "Standard/Non-standard properties" separation in the next revision of this patch. > > > - cache-block-size: Specifies the block size in bytes of the cache > > > > - cache-level: Should be set to 2 for a level 2 cache > > > > - cache-sets: Specifies the number of associativity sets of the cache > > > > - cache-size: Specifies the size in bytes of the cache > > What are the possible valid values for these? That's what's important. > What the properties mean are already defined in the spec. Sure, will mention the valid values for these properties. > > > > > - cache-unified: Specifies the cache is a unified cache > > > > Non-Standard Properties: > > I wouldn't call these non-standard. > > > - interrupt-parent: Must be core interrupt controller > > This is implied. Will remove this redundant description. > > > - reg: Physical base address and size of L2 cache controller registers map > > > > - reg-names: Should be "control" > > -names is not really needed when there is only 1 entry. Will remove this property. > > > > > - Yash > > > > > > -- > > > Regards, > > > Sudeep > > > > > > [1] > > > https://github.com/devicetree-org/devicetree-specification/releases/download/v0.2/devicetree-specification-v0.2.pdf
Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
On Tue, Apr 30, 2019 at 09:50:45AM +0530, Yash Shah wrote: > On Fri, Apr 26, 2019 at 3:04 PM Sudeep Holla wrote: > > > > On Fri, Apr 26, 2019 at 11:20:17AM +0530, Yash Shah wrote: > > > On Thu, Apr 25, 2019 at 3:43 PM Sudeep Holla wrote: > > > > > > > > On Thu, Apr 25, 2019 at 11:24:55AM +0530, Yash Shah wrote: > > > > > Add device tree bindings for SiFive FU540 L2 cache controller driver > > > > > > > > > > Signed-off-by: Yash Shah > > > > > --- > > > > > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 > > > > > ++ > > > > > 1 file changed, 53 insertions(+) > > > > > create mode 100644 > > > > > Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > > > > diff --git > > > > > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > new file mode 100644 > > > > > index 000..15132e2 > > > > > --- /dev/null > > > > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > @@ -0,0 +1,53 @@ > > > > > +SiFive L2 Cache Controller > > > > > +-- > > > > > +The SiFive Level 2 Cache Controller is used to provide access to > > > > > fast copies > > > > > +of memory for masters in a Core Complex. The Level 2 Cache > > > > > Controller also > > > > > +acts as directory-based coherency manager. > > > > > + > > > > > +Required Properties: > > > > > + > > > > > +- compatible: Should be "sifive,fu540-c000-ccache" > > > > > + > > > > > +- cache-block-size: Specifies the block size in bytes of the cache > > > > > + > > > > > +- cache-level: Should be set to 2 for a level 2 cache > > > > > + > > > > > +- cache-sets: Specifies the number of associativity sets of the cache > > > > > + > > > > > +- cache-size: Specifies the size in bytes of the cache > > > > > + > > > > > +- cache-unified: Specifies the cache is a unified cache > > > > > + > > > > > +- interrupt-parent: Must be core interrupt controller > > > > > + > > > > > +- interrupts: Must contain 3 entries (DirError, DataError and > > > > > DataFail signals) > > > > > + > > > > > +- reg: Physical base address and size of L2 cache controller > > > > > registers map > > > > > + > > > > > +- reg-names: Should be "control" > > > > > + > > > > > > > > It would be good if you mark the properties that are present in DT > > > > specification and those that are added for sifive,fu540-c000-ccache > > > > > > I believe there isn't any property which is added explicitly for > > > sifive,fu540-c000-ccache. > > > > > > > reg and interrupts are generally optional for normal cache and may be > > required for cache controller like this. DT specification[1] covers > > only caches and not cache controllers. > > Are you suggesting something like this: > > Required Properties: > > Standard Properties: I don't think we need this separation. > - compatible: Should be "sifive,-ccache" > Supported compatible strings are: > "sifive,fu540-c000-ccache" and "sifive,fu740-c000-ccache" > > - cache-block-size: Specifies the block size in bytes of the cache > > - cache-level: Should be set to 2 for a level 2 cache > > - cache-sets: Specifies the number of associativity sets of the cache > > - cache-size: Specifies the size in bytes of the cache What are the possible valid values for these? That's what's important. What the properties mean are already defined in the spec. > > - cache-unified: Specifies the cache is a unified cache > > Non-Standard Properties: I wouldn't call these non-standard. > - interrupt-parent: Must be core interrupt controller This is implied. > > - interrupts: Must contain 3 entries for FU540 (DirError, DataError and > DataFail signals) or 4 entries for other chips (DirError, DirFail, > DataError, > DataFail signals) > > - reg: Physical base address and size of L2 cache controller registers map > > - reg-names: Should be "control" -names is not really needed when there is only 1 entry. > > - Yash > > > > -- > > Regards, > > Sudeep > > > > [1] > > https://github.com/devicetree-org/devicetree-specification/releases/download/v0.2/devicetree-specification-v0.2.pdf
Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
On Fri, Apr 26, 2019 at 3:04 PM Sudeep Holla wrote: > > On Fri, Apr 26, 2019 at 11:20:17AM +0530, Yash Shah wrote: > > On Thu, Apr 25, 2019 at 3:43 PM Sudeep Holla wrote: > > > > > > On Thu, Apr 25, 2019 at 11:24:55AM +0530, Yash Shah wrote: > > > > Add device tree bindings for SiFive FU540 L2 cache controller driver > > > > > > > > Signed-off-by: Yash Shah > > > > --- > > > > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 > > > > ++ > > > > 1 file changed, 53 insertions(+) > > > > create mode 100644 > > > > Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > > > diff --git > > > > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > new file mode 100644 > > > > index 000..15132e2 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > @@ -0,0 +1,53 @@ > > > > +SiFive L2 Cache Controller > > > > +-- > > > > +The SiFive Level 2 Cache Controller is used to provide access to fast > > > > copies > > > > +of memory for masters in a Core Complex. The Level 2 Cache Controller > > > > also > > > > +acts as directory-based coherency manager. > > > > + > > > > +Required Properties: > > > > + > > > > +- compatible: Should be "sifive,fu540-c000-ccache" > > > > + > > > > +- cache-block-size: Specifies the block size in bytes of the cache > > > > + > > > > +- cache-level: Should be set to 2 for a level 2 cache > > > > + > > > > +- cache-sets: Specifies the number of associativity sets of the cache > > > > + > > > > +- cache-size: Specifies the size in bytes of the cache > > > > + > > > > +- cache-unified: Specifies the cache is a unified cache > > > > + > > > > +- interrupt-parent: Must be core interrupt controller > > > > + > > > > +- interrupts: Must contain 3 entries (DirError, DataError and DataFail > > > > signals) > > > > + > > > > +- reg: Physical base address and size of L2 cache controller registers > > > > map > > > > + > > > > +- reg-names: Should be "control" > > > > + > > > > > > It would be good if you mark the properties that are present in DT > > > specification and those that are added for sifive,fu540-c000-ccache > > > > I believe there isn't any property which is added explicitly for > > sifive,fu540-c000-ccache. > > > > reg and interrupts are generally optional for normal cache and may be > required for cache controller like this. DT specification[1] covers > only caches and not cache controllers. Are you suggesting something like this: Required Properties: Standard Properties: - compatible: Should be "sifive,-ccache" Supported compatible strings are: "sifive,fu540-c000-ccache" and "sifive,fu740-c000-ccache" - cache-block-size: Specifies the block size in bytes of the cache - cache-level: Should be set to 2 for a level 2 cache - cache-sets: Specifies the number of associativity sets of the cache - cache-size: Specifies the size in bytes of the cache - cache-unified: Specifies the cache is a unified cache Non-Standard Properties: - interrupt-parent: Must be core interrupt controller - interrupts: Must contain 3 entries for FU540 (DirError, DataError and DataFail signals) or 4 entries for other chips (DirError, DirFail, DataError, DataFail signals) - reg: Physical base address and size of L2 cache controller registers map - reg-names: Should be "control" - Yash > > -- > Regards, > Sudeep > > [1] > https://github.com/devicetree-org/devicetree-specification/releases/download/v0.2/devicetree-specification-v0.2.pdf
Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
On Fri, Apr 26, 2019 at 11:20:17AM +0530, Yash Shah wrote: > On Thu, Apr 25, 2019 at 3:43 PM Sudeep Holla wrote: > > > > On Thu, Apr 25, 2019 at 11:24:55AM +0530, Yash Shah wrote: > > > Add device tree bindings for SiFive FU540 L2 cache controller driver > > > > > > Signed-off-by: Yash Shah > > > --- > > > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 > > > ++ > > > 1 file changed, 53 insertions(+) > > > create mode 100644 > > > Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > new file mode 100644 > > > index 000..15132e2 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > @@ -0,0 +1,53 @@ > > > +SiFive L2 Cache Controller > > > +-- > > > +The SiFive Level 2 Cache Controller is used to provide access to fast > > > copies > > > +of memory for masters in a Core Complex. The Level 2 Cache Controller > > > also > > > +acts as directory-based coherency manager. > > > + > > > +Required Properties: > > > + > > > +- compatible: Should be "sifive,fu540-c000-ccache" > > > + > > > +- cache-block-size: Specifies the block size in bytes of the cache > > > + > > > +- cache-level: Should be set to 2 for a level 2 cache > > > + > > > +- cache-sets: Specifies the number of associativity sets of the cache > > > + > > > +- cache-size: Specifies the size in bytes of the cache > > > + > > > +- cache-unified: Specifies the cache is a unified cache > > > + > > > +- interrupt-parent: Must be core interrupt controller > > > + > > > +- interrupts: Must contain 3 entries (DirError, DataError and DataFail > > > signals) > > > + > > > +- reg: Physical base address and size of L2 cache controller registers > > > map > > > + > > > +- reg-names: Should be "control" > > > + > > > > It would be good if you mark the properties that are present in DT > > specification and those that are added for sifive,fu540-c000-ccache > > I believe there isn't any property which is added explicitly for > sifive,fu540-c000-ccache. > reg and interrupts are generally optional for normal cache and may be required for cache controller like this. DT specification[1] covers only caches and not cache controllers. -- Regards, Sudeep [1] https://github.com/devicetree-org/devicetree-specification/releases/download/v0.2/devicetree-specification-v0.2.pdf
Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
On Thu, Apr 25, 2019 at 3:43 PM Sudeep Holla wrote: > > On Thu, Apr 25, 2019 at 11:24:55AM +0530, Yash Shah wrote: > > Add device tree bindings for SiFive FU540 L2 cache controller driver > > > > Signed-off-by: Yash Shah > > --- > > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 > > ++ > > 1 file changed, 53 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > new file mode 100644 > > index 000..15132e2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > @@ -0,0 +1,53 @@ > > +SiFive L2 Cache Controller > > +-- > > +The SiFive Level 2 Cache Controller is used to provide access to fast > > copies > > +of memory for masters in a Core Complex. The Level 2 Cache Controller also > > +acts as directory-based coherency manager. > > + > > +Required Properties: > > + > > +- compatible: Should be "sifive,fu540-c000-ccache" > > + > > +- cache-block-size: Specifies the block size in bytes of the cache > > + > > +- cache-level: Should be set to 2 for a level 2 cache > > + > > +- cache-sets: Specifies the number of associativity sets of the cache > > + > > +- cache-size: Specifies the size in bytes of the cache > > + > > +- cache-unified: Specifies the cache is a unified cache > > + > > +- interrupt-parent: Must be core interrupt controller > > + > > +- interrupts: Must contain 3 entries (DirError, DataError and DataFail > > signals) > > + > > +- reg: Physical base address and size of L2 cache controller registers map > > + > > +- reg-names: Should be "control" > > + > > It would be good if you mark the properties that are present in DT > specification and those that are added for sifive,fu540-c000-ccache I believe there isn't any property which is added explicitly for sifive,fu540-c000-ccache. > explicitly. Also I assume you can retain the stardard "cache" compatible > in addition to above. I am interested to see if the cacheinfo infrastructure > can be used without any issues. Yes, I will add the "cache" string to the compatible property. > > -- > Regards, > Sudeep Thanks for your comments. - Yash
Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
On Thu, Apr 25, 2019 at 11:24:55AM +0530, Yash Shah wrote: > Add device tree bindings for SiFive FU540 L2 cache controller driver > > Signed-off-by: Yash Shah > --- > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 > ++ > 1 file changed, 53 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > new file mode 100644 > index 000..15132e2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt > @@ -0,0 +1,53 @@ > +SiFive L2 Cache Controller > +-- > +The SiFive Level 2 Cache Controller is used to provide access to fast copies > +of memory for masters in a Core Complex. The Level 2 Cache Controller also > +acts as directory-based coherency manager. > + > +Required Properties: > + > +- compatible: Should be "sifive,fu540-c000-ccache" > + > +- cache-block-size: Specifies the block size in bytes of the cache > + > +- cache-level: Should be set to 2 for a level 2 cache > + > +- cache-sets: Specifies the number of associativity sets of the cache > + > +- cache-size: Specifies the size in bytes of the cache > + > +- cache-unified: Specifies the cache is a unified cache > + > +- interrupt-parent: Must be core interrupt controller > + > +- interrupts: Must contain 3 entries (DirError, DataError and DataFail > signals) > + > +- reg: Physical base address and size of L2 cache controller registers map > + > +- reg-names: Should be "control" > + It would be good if you mark the properties that are present in DT specification and those that are added for sifive,fu540-c000-ccache explicitly. Also I assume you can retain the stardard "cache" compatible in addition to above. I am interested to see if the cacheinfo infrastructure can be used without any issues. -- Regards, Sudeep
[PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
Add device tree bindings for SiFive FU540 L2 cache controller driver
Signed-off-by: Yash Shah
---
.../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 ++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
new file mode 100644
index 000..15132e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
@@ -0,0 +1,53 @@
+SiFive L2 Cache Controller
+--
+The SiFive Level 2 Cache Controller is used to provide access to fast copies
+of memory for masters in a Core Complex. The Level 2 Cache Controller also
+acts as directory-based coherency manager.
+
+Required Properties:
+
+- compatible: Should be "sifive,fu540-c000-ccache"
+
+- cache-block-size: Specifies the block size in bytes of the cache
+
+- cache-level: Should be set to 2 for a level 2 cache
+
+- cache-sets: Specifies the number of associativity sets of the cache
+
+- cache-size: Specifies the size in bytes of the cache
+
+- cache-unified: Specifies the cache is a unified cache
+
+- interrupt-parent: Must be core interrupt controller
+
+- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals)
+
+- reg: Physical base address and size of L2 cache controller registers map
+
+- reg-names: Should be "control"
+
+Optional Properties:
+
+- next-level-cache: phandle to the next level cache if present.
+
+- memory-region: reference to the reserved-memory for the L2 Loosely Integrated
+ Memory region. The reserved memory node should be defined as per the bindings
+ in reserved-memory.txt
+
+
+Example:
+
+ cache-controller@201 {
+ compatible = "sifive,fu540-c000-ccache";
+ cache-block-size = <0x40>;
+ cache-level = <0x2>;
+ cache-sets = <0x400>;
+ cache-size = <0x10>;
+ cache-unified;
+ interrupt-parent = <>;
+ interrupts = <1 2 3>;
+ reg = <0x0 0x201 0x0 0x1000>;
+ reg-names = "control";
+ next-level-cache = < >;
+ memory-region = <_lim>;
+ };
--
1.9.1
