RE: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m

[Anson Huang]

Hi, Stephen

> Quoting anson.hu...@nxp.com (2019-06-25 00:06:02)
> > From: Anson Huang 
> >
> > i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m, NOT
> > sys_pll1_800m, correct it.
> >
> > Signed-off-by: Anson Huang 
> 
> Any Fixes tags?

Oops, I forgot to add fixed tags, just resent the patch set, sorry for that.

Thanks,
Anson

Re: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m

[Stephen Boyd]

Quoting anson.hu...@nxp.com (2019-06-25 00:06:02)
> From: Anson Huang 
> 
> i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m,
> NOT sys_pll1_800m, correct it.
> 
> Signed-off-by: Anson Huang 

Any Fixes tags?

RE: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m

[Jacky Bai]

OK for me.

BR
Jacky Bai
> -Original Message-
> From: anson.hu...@nxp.com [mailto:anson.hu...@nxp.com]
> Sent: Tuesday, June 25, 2019 3:06 PM
> To: mturque...@baylibre.com; sb...@kernel.org; shawn...@kernel.org;
> s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> Leonard Crestez ; Jacky Bai ;
> Peng Fan ; linux-...@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org
> Cc: dl-linux-imx 
> Subject: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be
> sys_pll1_80m
> 
> From: Anson Huang 
> 
> i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m, NOT
> sys_pll1_800m, correct it.
> 
> Signed-off-by: Anson Huang 
> ---
>  drivers/clk/imx/clk-imx8mm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index 516e68d..d1a84f7 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -293,7 +293,7 @@ static const char *imx8mm_pwm4_sels[] =
> {"osc_24m", "sys_pll2_100m", "sys_pll1_1
>"sys_pll3_out", "clk_ext2", 
> "sys_pll1_80m",
> "video_pll1_out", };
> 
>  static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m",
> "sys_pll1_400m", "sys_pll1_40m",
> -  "video_pll1_out", "sys_pll1_800m",
> "audio_pll1_out", "clk_ext1" };
> +  "video_pll1_out", "sys_pll1_80m", 
> "audio_pll1_out",
> "clk_ext1" };
> 
>  static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m",
> "sys_pll1_160m", "vpu_pll_out",
>"sys_pll2_125m", "sys_pll3_out", 
> "sys_pll1_80m",
> "sys_pll2_166m", };
> --
> 2.7.4

Recall: [PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m

[Jacky Bai]

Jacky Bai would like to recall the message, "[PATCH 2/2] clk: imx8mm: GPT1 
clock mux option #5 should be sys_pll1_80m".

[PATCH 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m

[Anson . Huang]

From: Anson Huang 

i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m,
NOT sys_pll1_800m, correct it.

Signed-off-by: Anson Huang 
---
 drivers/clk/imx/clk-imx8mm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 516e68d..d1a84f7 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -293,7 +293,7 @@ static const char *imx8mm_pwm4_sels[] = {"osc_24m", 
"sys_pll2_100m", "sys_pll1_1
 "sys_pll3_out", "clk_ext2", 
"sys_pll1_80m", "video_pll1_out", };
 
 static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", 
"sys_pll1_400m", "sys_pll1_40m",
-"video_pll1_out", "sys_pll1_800m", 
"audio_pll1_out", "clk_ext1" };
+"video_pll1_out", "sys_pll1_80m", 
"audio_pll1_out", "clk_ext1" };
 
 static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", 
"sys_pll1_160m", "vpu_pll_out",
 "sys_pll2_125m", "sys_pll3_out", 
"sys_pll1_80m", "sys_pll2_166m", };
-- 
2.7.4