Re: [PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver
Hello Troy, > Hi Stefan, > > The driver was ported from latest ASPEED BSP, so I only test with ECC-on/off > from u-boot and check if driver runs correctly. I noticed now most changes are these "exports". As you removed them a later revision, the patch looks now lean and clean. I'll give you my Reviewed-by tag after you addressed Andrew's last comment. > The test doc you provided is very nice and detailed, I'll try to reproduce > the > injection test in v2 patch. It does not harm to redo the testing. That is time-consuming and with your current, now trivial changes, it's not really necessary. Stefan
RE: [PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver
Hi Stefan, The driver was ported from latest ASPEED BSP, so I only test with ECC-on/off from u-boot and check if driver runs correctly. The test doc you provided is very nice and detailed, I'll try to reproduce the injection test in v2 patch. Thanks, Troy Lee > -Original Message- > From: Stefan Schaeckeler (sschaeck) > Sent: Monday, November 30, 2020 5:16 PM > To: Troy Lee ; Rob Herring ; > Joel Stanley ; Andrew Jeffery ; Borislav > Petkov ; Mauro Carvalho Chehab ; > Tony Luck ; James Morse ; > Robert Richter ; open list:OPEN FIRMWARE AND > FLATTENED DEVICE TREE BINDINGS ; moderated > list:ARM/ASPEED MACHINE SUPPORT ; > moderated list:ARM/ASPEED MACHINE SUPPORT > ; open list ; > open list:EDAC-CORE > Cc: leet...@gmail.com; Ryan Chen ; Stefan > Schaeckeler > Subject: Re: [PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver > > Hello Troy, > > > Adding AST2400 and AST2600 edac driver support. > > > > Signed-off-by: Troy Lee > > --- > > drivers/edac/Kconfig | 6 +- > > drivers/edac/aspeed_edac.c | 114 + > > 2 files changed, 94 insertions(+), 26 deletions(-) > > Uh, there are quite some non-trivial changes. I'll have a look over the coming > weekend. > > Testing an edac driver comes with challenges. Did you test your code? If so, > how? > > That's how I was testing my original edac 2500 driver > http://students.engr.scu.edu/~sschaeck/misc/aspeed-edac.html > > Stefan
RE: [PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver
Hi Andrew,
Great suggestion, responses inline below. We'll remove build-time SoC
dependency driver code and submit an updated v2 patch.
Thanks,
Troy Lee
> -Original Message-
> From: Andrew Jeffery
> Sent: Tuesday, December 1, 2020 9:12 AM
> To: Troy Lee ; Stefan M Schaeckeler
> ; Rob Herring ; Joel Stanley
> ; Borislav Petkov ; Mauro Carvalho Chehab
> ; Tony Luck ; James Morse
> ; Robert Richter ; open
> list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> ; moderated list:ARM/ASPEED MACHINE
> SUPPORT ; moderated
> list:ARM/ASPEED MACHINE SUPPORT ; open
> list ; open list:EDAC-CORE
>
> Cc: leet...@gmail.com; Ryan Chen
> Subject: Re: [PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver
>
> Hi Troy,
>
> I like the idea of expanding the driver's support to cover the other SoC
> generations, but not at the cost of making the build of the driver
> SoC-specific.
> I've made some comments below in this regard.
>
> On Mon, 30 Nov 2020, at 19:03, Troy Lee wrote:
> > Adding AST2400 and AST2600 edac driver support.
> >
> > Signed-off-by: Troy Lee
> > ---
> > drivers/edac/Kconfig | 6 +-
> > drivers/edac/aspeed_edac.c | 114
> > +
> > 2 files changed, 94 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index
> > fc30f2ef9782..8ea70746d0bf 100644
> > --- a/drivers/edac/Kconfig
> > +++ b/drivers/edac/Kconfig
> > @@ -508,10 +508,10 @@ config EDAC_QCOM
> > health, you should probably say 'Y' here.
> >
> > config EDAC_ASPEED
> > - tristate "Aspeed AST 2500 SoC"
> > - depends on MACH_ASPEED_G5
> > + tristate "Aspeed AST BMC SoC"
> > + depends on (MACH_ASPEED_G4 || MACH_ASPEED_G5 ||
> MACH_ASPEED_G6)
> > help
> > - Support for error detection and correction on the Aspeed AST 2500 SoC.
> > + Support for error detection and correction on the Aspeed AST BMC SoC.
> >
> > First, ECC must be configured in the bootloader. Then, this driver
> > will expose error counters via the EDAC kernel framework.
> > diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
> > index fbec28dc661d..03a3c12f6bf6 100644
> > --- a/drivers/edac/aspeed_edac.c
> > +++ b/drivers/edac/aspeed_edac.c
> > @@ -14,12 +14,11 @@
> > #include
> > #include "edac_module.h"
> >
> > -
> > #define DRV_NAME "aspeed-edac"
> >
> > -
> > #define ASPEED_MCR_PROT0x00 /* protection key register */
> > #define ASPEED_MCR_CONF0x04 /* configuration register */
> > +#define ASPEED_MCR_REQ 0x08 /* Graphics Memory Protection
> register */
> > #define ASPEED_MCR_INTR_CTRL 0x50 /* interrupt control/status
> register */
> > #define ASPEED_MCR_ADDR_UNREC 0x58 /* address of first
> un-recoverable error */
> > #define ASPEED_MCR_ADDR_REC0x5c /* address of last recoverable
> error */
> > @@ -34,10 +33,8 @@
> > #define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)
> #define
> > ASPEED_MCR_INTR_CTRL_ENABLE (BIT(0) | BIT(1))
> >
> > -
> > static struct regmap *aspeed_regmap;
> >
> > -
> > static int regmap_reg_write(void *context, unsigned int reg, unsigned
> > int val) {
> > void __iomem *regs = (void __iomem *)context; @@ -53,7 +50,6 @@
> > static int regmap_reg_write(void *context, unsigned int reg, unsigned
> > int val)
> > return 0;
> > }
> >
> > -
> > static int regmap_reg_read(void *context, unsigned int reg, unsigned
> > int *val) {
> > void __iomem *regs = (void __iomem *)context; @@ -63,6 +59,76 @@
> > static int regmap_reg_read(void *context, unsigned int reg, unsigned
> > int *val)
> > return 0;
> > }
> >
> > +extern void aspeed_sdmc_disable_mem_protection(u8 req) {
> > + u32 req_val = 0;
> > +
> > + regmap_read(aspeed_regmap, ASPEED_MCR_REQ, _val);
> > +
> > + req_val &= ~BIT(req);
> > +
> > + regmap_write(aspeed_regmap, ASPEED_MCR_REQ, req_val); }
> > +EXPORT_SYMBOL(aspeed_sdmc_disable_mem_protection);
> > +
> > +static const u32 ast2400_dram_table[] = {
> > + 0x0400, //64MB
> > + 0x0800, //128MB
> > + 0x1000, //256MB
> > + 0x2000, //512MB
> > +};
>
> You could perhaps save us from the size comments here by using e.g.
>
> static const u32 ast2400_dram_table[] = {
> 64 << 20,
> 128 << 20,
> 256 <&l
Re: [PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver
Hi Troy,
I like the idea of expanding the driver's support to cover the other SoC
generations, but not at the cost of making the build of the driver
SoC-specific. I've made some comments below in this regard.
On Mon, 30 Nov 2020, at 19:03, Troy Lee wrote:
> Adding AST2400 and AST2600 edac driver support.
>
> Signed-off-by: Troy Lee
> ---
> drivers/edac/Kconfig | 6 +-
> drivers/edac/aspeed_edac.c | 114 +
> 2 files changed, 94 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index fc30f2ef9782..8ea70746d0bf 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -508,10 +508,10 @@ config EDAC_QCOM
> health, you should probably say 'Y' here.
>
> config EDAC_ASPEED
> - tristate "Aspeed AST 2500 SoC"
> - depends on MACH_ASPEED_G5
> + tristate "Aspeed AST BMC SoC"
> + depends on (MACH_ASPEED_G4 || MACH_ASPEED_G5 || MACH_ASPEED_G6)
> help
> - Support for error detection and correction on the Aspeed AST 2500 SoC.
> + Support for error detection and correction on the Aspeed AST BMC SoC.
>
> First, ECC must be configured in the bootloader. Then, this driver
> will expose error counters via the EDAC kernel framework.
> diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
> index fbec28dc661d..03a3c12f6bf6 100644
> --- a/drivers/edac/aspeed_edac.c
> +++ b/drivers/edac/aspeed_edac.c
> @@ -14,12 +14,11 @@
> #include
> #include "edac_module.h"
>
> -
> #define DRV_NAME "aspeed-edac"
>
> -
> #define ASPEED_MCR_PROT0x00 /* protection key register */
> #define ASPEED_MCR_CONF0x04 /* configuration register */
> +#define ASPEED_MCR_REQ 0x08 /* Graphics Memory Protection register */
> #define ASPEED_MCR_INTR_CTRL 0x50 /* interrupt control/status register */
> #define ASPEED_MCR_ADDR_UNREC 0x58 /* address of first un-recoverable error
> */
> #define ASPEED_MCR_ADDR_REC0x5c /* address of last recoverable error */
> @@ -34,10 +33,8 @@
> #define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)
> #define ASPEED_MCR_INTR_CTRL_ENABLE (BIT(0) | BIT(1))
>
> -
> static struct regmap *aspeed_regmap;
>
> -
> static int regmap_reg_write(void *context, unsigned int reg, unsigned
> int val)
> {
> void __iomem *regs = (void __iomem *)context;
> @@ -53,7 +50,6 @@ static int regmap_reg_write(void *context, unsigned
> int reg, unsigned int val)
> return 0;
> }
>
> -
> static int regmap_reg_read(void *context, unsigned int reg, unsigned
> int *val)
> {
> void __iomem *regs = (void __iomem *)context;
> @@ -63,6 +59,76 @@ static int regmap_reg_read(void *context, unsigned
> int reg, unsigned int *val)
> return 0;
> }
>
> +extern void aspeed_sdmc_disable_mem_protection(u8 req)
> +{
> + u32 req_val = 0;
> +
> + regmap_read(aspeed_regmap, ASPEED_MCR_REQ, _val);
> +
> + req_val &= ~BIT(req);
> +
> + regmap_write(aspeed_regmap, ASPEED_MCR_REQ, req_val);
> +}
> +EXPORT_SYMBOL(aspeed_sdmc_disable_mem_protection);
> +
> +static const u32 ast2400_dram_table[] = {
> + 0x0400, //64MB
> + 0x0800, //128MB
> + 0x1000, //256MB
> + 0x2000, //512MB
> +};
You could perhaps save us from the size comments here by using e.g.
static const u32 ast2400_dram_table[] = {
64 << 20,
128 << 20,
256 << 20,
512 << 20,
};
> +
> +static const u32 ast2500_dram_table[] = {
> + 0x0800, //128MB
> + 0x1000, //256MB
> + 0x2000, //512MB
> + 0x4000, //1024MB
> +};
> +
> +static const u32 ast2600_dram_table[] = {
> + 0x1000, //256MB
> + 0x2000, //512MB
> + 0x4000, //1024MB
> + 0x8000, //2048MB
> +};
> +
> +extern u32 aspeed_get_dram_size(void)
> +{
> + u32 reg04;
> + u32 size;
> +
> + regmap_read(aspeed_regmap, ASPEED_MCR_CONF, );
> +
> +#if defined(CONFIG_MACH_ASPEED_G6)
> + size = ast2600_dram_table[reg04 & 0x3];
> +#elif defined(CONFIG_MACH_ASPEED_G5)
> + size = ast2500_dram_table[reg04 & 0x3];
> +#else
> + size = ast2400_dram_table[reg04 & 0x3];
> +#endif
> + return size;
> +}
> +EXPORT_SYMBOL(aspeed_get_dram_size);
The driver must support running on any of the SoC generations without being
recompiled. This requires the driver be compiled for a specific SoC generation.
The right way to do this is to use the OF match table data. Please fix it.
> +
> +static const u32 aspeed_vga_table[] = {
> + 0x80, //8MB
> + 0x100, //16MB
> + 0x200, //32MB
> + 0x400, //64MB
> +};
> +
> +extern u32 aspeed_get_vga_size(void)
> +{
> + u32 reg04;
> + u32 size;
> +
> + regmap_read(aspeed_regmap, ASPEED_MCR_CONF, );
> +
> + size = aspeed_vga_table[((reg04 & 0xC) >> 2)];
> + return size;
> +}
> +EXPORT_SYMBOL(aspeed_get_vga_size);
> +
> static bool
Re: [PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver
Hello Troy, > Adding AST2400 and AST2600 edac driver support. > > Signed-off-by: Troy Lee > --- > drivers/edac/Kconfig | 6 +- > drivers/edac/aspeed_edac.c | 114 + > 2 files changed, 94 insertions(+), 26 deletions(-) Uh, there are quite some non-trivial changes. I'll have a look over the coming weekend. Testing an edac driver comes with challenges. Did you test your code? If so, how? That's how I was testing my original edac 2500 driver http://students.engr.scu.edu/~sschaeck/misc/aspeed-edac.html Stefan
[PATCH 3/3] edac: Supporting AST2400 and AST2600 edac driver
Adding AST2400 and AST2600 edac driver support.
Signed-off-by: Troy Lee
---
drivers/edac/Kconfig | 6 +-
drivers/edac/aspeed_edac.c | 114 +
2 files changed, 94 insertions(+), 26 deletions(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index fc30f2ef9782..8ea70746d0bf 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -508,10 +508,10 @@ config EDAC_QCOM
health, you should probably say 'Y' here.
config EDAC_ASPEED
- tristate "Aspeed AST 2500 SoC"
- depends on MACH_ASPEED_G5
+ tristate "Aspeed AST BMC SoC"
+ depends on (MACH_ASPEED_G4 || MACH_ASPEED_G5 || MACH_ASPEED_G6)
help
- Support for error detection and correction on the Aspeed AST 2500 SoC.
+ Support for error detection and correction on the Aspeed AST BMC SoC.
First, ECC must be configured in the bootloader. Then, this driver
will expose error counters via the EDAC kernel framework.
diff --git a/drivers/edac/aspeed_edac.c b/drivers/edac/aspeed_edac.c
index fbec28dc661d..03a3c12f6bf6 100644
--- a/drivers/edac/aspeed_edac.c
+++ b/drivers/edac/aspeed_edac.c
@@ -14,12 +14,11 @@
#include
#include "edac_module.h"
-
#define DRV_NAME "aspeed-edac"
-
#define ASPEED_MCR_PROT0x00 /* protection key register */
#define ASPEED_MCR_CONF0x04 /* configuration register */
+#define ASPEED_MCR_REQ 0x08 /* Graphics Memory Protection register */
#define ASPEED_MCR_INTR_CTRL 0x50 /* interrupt control/status register */
#define ASPEED_MCR_ADDR_UNREC 0x58 /* address of first un-recoverable error */
#define ASPEED_MCR_ADDR_REC0x5c /* address of last recoverable error */
@@ -34,10 +33,8 @@
#define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)
#define ASPEED_MCR_INTR_CTRL_ENABLE (BIT(0) | BIT(1))
-
static struct regmap *aspeed_regmap;
-
static int regmap_reg_write(void *context, unsigned int reg, unsigned int val)
{
void __iomem *regs = (void __iomem *)context;
@@ -53,7 +50,6 @@ static int regmap_reg_write(void *context, unsigned int reg,
unsigned int val)
return 0;
}
-
static int regmap_reg_read(void *context, unsigned int reg, unsigned int *val)
{
void __iomem *regs = (void __iomem *)context;
@@ -63,6 +59,76 @@ static int regmap_reg_read(void *context, unsigned int reg,
unsigned int *val)
return 0;
}
+extern void aspeed_sdmc_disable_mem_protection(u8 req)
+{
+ u32 req_val = 0;
+
+ regmap_read(aspeed_regmap, ASPEED_MCR_REQ, _val);
+
+ req_val &= ~BIT(req);
+
+ regmap_write(aspeed_regmap, ASPEED_MCR_REQ, req_val);
+}
+EXPORT_SYMBOL(aspeed_sdmc_disable_mem_protection);
+
+static const u32 ast2400_dram_table[] = {
+ 0x0400, //64MB
+ 0x0800, //128MB
+ 0x1000, //256MB
+ 0x2000, //512MB
+};
+
+static const u32 ast2500_dram_table[] = {
+ 0x0800, //128MB
+ 0x1000, //256MB
+ 0x2000, //512MB
+ 0x4000, //1024MB
+};
+
+static const u32 ast2600_dram_table[] = {
+ 0x1000, //256MB
+ 0x2000, //512MB
+ 0x4000, //1024MB
+ 0x8000, //2048MB
+};
+
+extern u32 aspeed_get_dram_size(void)
+{
+ u32 reg04;
+ u32 size;
+
+ regmap_read(aspeed_regmap, ASPEED_MCR_CONF, );
+
+#if defined(CONFIG_MACH_ASPEED_G6)
+ size = ast2600_dram_table[reg04 & 0x3];
+#elif defined(CONFIG_MACH_ASPEED_G5)
+ size = ast2500_dram_table[reg04 & 0x3];
+#else
+ size = ast2400_dram_table[reg04 & 0x3];
+#endif
+ return size;
+}
+EXPORT_SYMBOL(aspeed_get_dram_size);
+
+static const u32 aspeed_vga_table[] = {
+ 0x80, //8MB
+ 0x100, //16MB
+ 0x200, //32MB
+ 0x400, //64MB
+};
+
+extern u32 aspeed_get_vga_size(void)
+{
+ u32 reg04;
+ u32 size;
+
+ regmap_read(aspeed_regmap, ASPEED_MCR_CONF, );
+
+ size = aspeed_vga_table[((reg04 & 0xC) >> 2)];
+ return size;
+}
+EXPORT_SYMBOL(aspeed_get_vga_size);
+
static bool regmap_is_volatile(struct device *dev, unsigned int reg)
{
switch (reg) {
@@ -209,8 +275,8 @@ static int config_irq(void *ctx, struct platform_device
*pdev)
/* register interrupt handler */
irq = platform_get_irq(pdev, 0);
dev_dbg(>dev, "got irq %d\n", irq);
- if (irq < 0)
- return irq;
+ if (!irq)
+ return -ENODEV;
rc = devm_request_irq(>dev, irq, mcr_isr, IRQF_TRIGGER_HIGH,
DRV_NAME, ctx);
@@ -239,7 +305,11 @@ static int init_csrows(struct mem_ctl_info *mci)
int rc;
/* retrieve info about physical memory from device tree */
- np = of_find_node_by_path("/memory");
+#ifdef CONFIG_MACH_ASPEED_G4
+ np = of_find_node_by_path("/memory@4000");
+#else
+ np = of_find_node_by_path("/memory@8000");
+#endif
