Re: [PATCH 4/6] clk: qcom: Add ipq6018 Global Clock Controller support
On Mon 10 Jun 04:47 PDT 2019, Sricharan R wrote:
> Hi Bjorn,
>
> On 6/8/2019 9:02 AM, Bjorn Andersson wrote:
> > On Wed 05 Jun 10:15 PDT 2019, Sricharan R wrote:
> >
> >> This patch adds support for the global clock controller found on
> >> the ipq6018 based devices.
> >>
> >> Signed-off-by: Sricharan R
> >> Signed-off-by: anusha
> >> Signed-off-by: Abhishek Sahu
> >
> > Please fix your s-o-b chain, as described in my reply to 1/8..
> >
>
> ok.
>
> >> ---
> >> drivers/clk/qcom/Kconfig |9 +
> >> drivers/clk/qcom/Makefile |1 +
> >> drivers/clk/qcom/gcc-ipq6018.c | 5267
> >>
> >> 3 files changed, 5277 insertions(+)
> >> create mode 100644 drivers/clk/qcom/gcc-ipq6018.c
> >>
> >> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> >> index e1ff83c..e5fb091 100644
> >> --- a/drivers/clk/qcom/Kconfig
> >> +++ b/drivers/clk/qcom/Kconfig
> >> @@ -120,6 +120,15 @@ config IPQ_GCC_8074
> >> i2c, USB, SD/eMMC, etc. Select this for the root clock
> >> of ipq8074.
> >>
> >> +config IPQ_GCC_6018
> >
> > Please maintain sort order.
> >
>
> ok.
>
> >> + tristate "IPQ6018 Global Clock Controller"
> >> + depends on COMMON_CLK_QCOM
> >> + help
> >> +Support for global clock controller on ipq6018 devices.
> >> +Say Y if you want to use peripheral devices such as UART, SPI,
> >> +i2c, USB, SD/eMMC, etc. Select this for the root clock
> >> +of ipq6018.
> >> +
> >> config MSM_GCC_8660
> >>tristate "MSM8660 Global Clock Controller"
> >>help
> >> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> >> index f0768fb..025137d 100644
> >> --- a/drivers/clk/qcom/Makefile
> >> +++ b/drivers/clk/qcom/Makefile
> >> @@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
> >> obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
> >> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
> >> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> >> +obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
> >
> > Ditto.
> >
>
> ok.
>
> >> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
> >> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
> >> obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
> >> diff --git a/drivers/clk/qcom/gcc-ipq6018.c
> >> b/drivers/clk/qcom/gcc-ipq6018.c
> > [..]
> >> +static int gcc_ipq6018_probe(struct platform_device *pdev)
> >> +{
> >> + return qcom_cc_probe(pdev, &gcc_ipq6018_desc);
> >> +}
> >> +
> >> +static int gcc_ipq6018_remove(struct platform_device *pdev)
> >> +{
> >> + return 0;
> >
> > Just omit .remove from the gcc_ipq6018_driver instead of providing a
> > dummy function.
> >
>
> ok.
>
> >> +}
> >> +
> >> +static struct platform_driver gcc_ipq6018_driver = {
> >> + .probe = gcc_ipq6018_probe,
> >> + .remove = gcc_ipq6018_remove,
> >> + .driver = {
> >> + .name = "qcom,gcc-ipq6018",
> >> + .owner = THIS_MODULE,
> >
> > Don't specify .owner in platform drivers.
> >
>
> ok.
>
> > [..]
> >> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ6018 Driver");
> >> +MODULE_LICENSE("GPL v2");
> >> +MODULE_ALIAS("platform:gcc-ipq6018");
> >
> > This modalias won't be used.
> >
>
> ok. But it looks to be there in other clk drivers as well.
>
It serves the purpose that the driver will be automatically modprobed if
someone calls:
platform_device_register*(..., "gcc-ipq6018", ...);
So for everything that is only going be probed from DT (or ACPI) this
does not add any value. As such there are several other places where
these aliases should be dropped.
Regards,
Bjorn
Re: [PATCH 4/6] clk: qcom: Add ipq6018 Global Clock Controller support
Quoting Sricharan R (2019-06-05 10:28:56)
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index e1ff83c..e5fb091 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -120,6 +120,15 @@ config IPQ_GCC_8074
> i2c, USB, SD/eMMC, etc. Select this for the root clock
> of ipq8074.
>
> +config IPQ_GCC_6018
> + tristate "IPQ6018 Global Clock Controller"
> + depends on COMMON_CLK_QCOM
Not sure I commented on this, but this should be removed. The whole
thing is inside an if now.
> + help
> + Support for global clock controller on ipq6018 devices.
> + Say Y if you want to use peripheral devices such as UART, SPI,
> + i2c, USB, SD/eMMC, etc. Select this for the root clock
> + of ipq6018.
> +
> config MSM_GCC_8660
> tristate "MSM8660 Global Clock Controller"
> help
> diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
> new file mode 100644
> index 000..9f4552b
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-ipq6018.c
> @@ -0,0 +1,5267 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +
> +#include "common.h"
> +#include "clk-regmap.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-branch.h"
> +#include "clk-alpha-pll.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "reset.h"
> +
> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
[...]
> +
> +static struct clk_alpha_pll gpll0_main = {
> + .offset = 0x21000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x0b000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll0_main",
> + .parent_names = (const char *[]){
> + "xo"
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + .flags = CLK_IS_CRITICAL,
Can you add a comment on why this is critical?
> + },
> + },
> +};
> +
> +static struct clk_fixed_factor gpll0_out_main_div2 = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll0_out_main_div2",
> + .parent_names = (const char *[]){
> + "gpll0_main"
> + },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll0 = {
> + .offset = 0x21000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll0",
> + .parent_names = (const char *[]){
> + "gpll0_main"
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_alpha_pll ubi32_pll_main = {
> + .offset = 0x25000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
> + .flags = SUPPORTS_DYNAMIC_UPDATE,
> + .clkr = {
> + .enable_reg = 0x0b000,
> + .enable_mask = BIT(6),
> + .hw.init = &(struct clk_init_data){
> + .name = "ubi32_pll_main",
> + .parent_names = (const char *[]){
> + "xo"
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_huayra_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv ubi32_pll = {
> + .offset = 0x25000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
> + .width = 2,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "ubi32_pll",
> + .parent_names = (const char *[]){
> + "ubi32_pll_main"
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_alpha_pll gpll6_main = {
> + .offset = 0x37000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
> + .clkr = {
> + .enable_reg = 0x0b000,
> + .enable_mask = BIT(7),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll6_main",
> + .parent_names = (const char
Re: [PATCH 4/6] clk: qcom: Add ipq6018 Global Clock Controller support
Hi Bjorn,
On 6/8/2019 9:02 AM, Bjorn Andersson wrote:
> On Wed 05 Jun 10:15 PDT 2019, Sricharan R wrote:
>
>> This patch adds support for the global clock controller found on
>> the ipq6018 based devices.
>>
>> Signed-off-by: Sricharan R
>> Signed-off-by: anusha
>> Signed-off-by: Abhishek Sahu
>
> Please fix your s-o-b chain, as described in my reply to 1/8..
>
ok.
>> ---
>> drivers/clk/qcom/Kconfig |9 +
>> drivers/clk/qcom/Makefile |1 +
>> drivers/clk/qcom/gcc-ipq6018.c | 5267
>>
>> 3 files changed, 5277 insertions(+)
>> create mode 100644 drivers/clk/qcom/gcc-ipq6018.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index e1ff83c..e5fb091 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -120,6 +120,15 @@ config IPQ_GCC_8074
>>i2c, USB, SD/eMMC, etc. Select this for the root clock
>>of ipq8074.
>>
>> +config IPQ_GCC_6018
>
> Please maintain sort order.
>
ok.
>> +tristate "IPQ6018 Global Clock Controller"
>> +depends on COMMON_CLK_QCOM
>> +help
>> + Support for global clock controller on ipq6018 devices.
>> + Say Y if you want to use peripheral devices such as UART, SPI,
>> + i2c, USB, SD/eMMC, etc. Select this for the root clock
>> + of ipq6018.
>> +
>> config MSM_GCC_8660
>> tristate "MSM8660 Global Clock Controller"
>> help
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index f0768fb..025137d 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
>> obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
>> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>> +obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>
> Ditto.
>
ok.
>> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>> obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
>> diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
> [..]
>> +static int gcc_ipq6018_probe(struct platform_device *pdev)
>> +{
>> +return qcom_cc_probe(pdev, &gcc_ipq6018_desc);
>> +}
>> +
>> +static int gcc_ipq6018_remove(struct platform_device *pdev)
>> +{
>> +return 0;
>
> Just omit .remove from the gcc_ipq6018_driver instead of providing a
> dummy function.
>
ok.
>> +}
>> +
>> +static struct platform_driver gcc_ipq6018_driver = {
>> +.probe = gcc_ipq6018_probe,
>> +.remove = gcc_ipq6018_remove,
>> +.driver = {
>> +.name = "qcom,gcc-ipq6018",
>> +.owner = THIS_MODULE,
>
> Don't specify .owner in platform drivers.
>
ok.
> [..]
>> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ6018 Driver");
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_ALIAS("platform:gcc-ipq6018");
>
> This modalias won't be used.
>
ok. But it looks to be there in other clk drivers as well.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of
Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 4/6] clk: qcom: Add ipq6018 Global Clock Controller support
On Wed 05 Jun 10:15 PDT 2019, Sricharan R wrote:
> This patch adds support for the global clock controller found on
> the ipq6018 based devices.
>
> Signed-off-by: Sricharan R
> Signed-off-by: anusha
> Signed-off-by: Abhishek Sahu
Please fix your s-o-b chain, as described in my reply to 1/8..
> ---
> drivers/clk/qcom/Kconfig |9 +
> drivers/clk/qcom/Makefile |1 +
> drivers/clk/qcom/gcc-ipq6018.c | 5267
>
> 3 files changed, 5277 insertions(+)
> create mode 100644 drivers/clk/qcom/gcc-ipq6018.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index e1ff83c..e5fb091 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -120,6 +120,15 @@ config IPQ_GCC_8074
> i2c, USB, SD/eMMC, etc. Select this for the root clock
> of ipq8074.
>
> +config IPQ_GCC_6018
Please maintain sort order.
> + tristate "IPQ6018 Global Clock Controller"
> + depends on COMMON_CLK_QCOM
> + help
> + Support for global clock controller on ipq6018 devices.
> + Say Y if you want to use peripheral devices such as UART, SPI,
> + i2c, USB, SD/eMMC, etc. Select this for the root clock
> + of ipq6018.
> +
> config MSM_GCC_8660
> tristate "MSM8660 Global Clock Controller"
> help
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index f0768fb..025137d 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
> obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> +obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
Ditto.
> obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
> obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
> obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
> diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
[..]
> +static int gcc_ipq6018_probe(struct platform_device *pdev)
> +{
> + return qcom_cc_probe(pdev, &gcc_ipq6018_desc);
> +}
> +
> +static int gcc_ipq6018_remove(struct platform_device *pdev)
> +{
> + return 0;
Just omit .remove from the gcc_ipq6018_driver instead of providing a
dummy function.
> +}
> +
> +static struct platform_driver gcc_ipq6018_driver = {
> + .probe = gcc_ipq6018_probe,
> + .remove = gcc_ipq6018_remove,
> + .driver = {
> + .name = "qcom,gcc-ipq6018",
> + .owner = THIS_MODULE,
Don't specify .owner in platform drivers.
[..]
> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ6018 Driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:gcc-ipq6018");
This modalias won't be used.
Regards,
Bjorn
[PATCH 4/6] clk: qcom: Add ipq6018 Global Clock Controller support
This patch adds support for the global clock controller found on
the ipq6018 based devices.
Signed-off-by: Sricharan R
Signed-off-by: anusha
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc-ipq6018.c | 5267
3 files changed, 5277 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-ipq6018.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e1ff83c..e5fb091 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -120,6 +120,15 @@ config IPQ_GCC_8074
i2c, USB, SD/eMMC, etc. Select this for the root clock
of ipq8074.
+config IPQ_GCC_6018
+ tristate "IPQ6018 Global Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for global clock controller on ipq6018 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc. Select this for the root clock
+ of ipq6018.
+
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f0768fb..025137d 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
+obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
new file mode 100644
index 000..9f4552b
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -0,0 +1,5267 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "reset.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+ P_XO,
+ P_BIAS_PLL,
+ P_UNIPHY0_RX,
+ P_UNIPHY0_TX,
+ P_UNIPHY1_RX,
+ P_BIAS_PLL_NSS_NOC,
+ P_UNIPHY1_TX,
+ P_PCIE20_PHY0_PIPE,
+ P_USB3PHY_0_PIPE,
+ P_GPLL0,
+ P_GPLL0_DIV2,
+ P_GPLL2,
+ P_GPLL4,
+ P_GPLL6,
+ P_SLEEP_CLK,
+ P_UBI32_PLL,
+ P_NSS_CRYPTO_PLL,
+ P_PI_SLEEP,
+};
+
+static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll0",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
+ "xo",
+ "bias_pll_cc_clk",
+ "gpll0",
+ "gpll4",
+ "nss_crypto_pll",
+ "ubi32_pll",
+};
+
+static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL4, 3 },
+ { P_NSS_CRYPTO_PLL, 4 },
+ { P_UBI32_PLL, 5 },
+};
+
+static const char * const gcc_xo_gpll0[] = {
+ "xo",
+ "gpll0",
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
+ "xo",
+ "bias_pll_nss_noc_clk",
+ "gpll0",
+ "gpll2",
+};
+
+static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] =
{
+ { P_XO, 0 },
+ { P_BIAS_PLL_NSS_NOC, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL2, 3 },
+};
+
+static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_rx_clk",
+ "uniphy0_gcc_tx_clk",
+ "uniphy1_gcc_rx_clk",
+ "uniphy1_gcc_tx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map
+gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_RX, 1 },
+ { P_UNIPHY0_TX, 2 },
+ { P_UNIPHY1_RX, 3 },
+ { P_UNIPHY1_TX, 4 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_tx_clk",
+ "uniphy0_gcc_rx_clk",
+ "uniphy1_gcc_tx_clk",
+ "uniphy1_gcc_rx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map
+gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+
[PATCH 4/6] clk: qcom: Add ipq6018 Global Clock Controller support
This patch adds support for the global clock controller found on
the ipq6018 based devices.
Signed-off-by: Sricharan R
Signed-off-by: anusha
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc-ipq6018.c | 5267
3 files changed, 5277 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-ipq6018.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e1ff83c..e5fb091 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -120,6 +120,15 @@ config IPQ_GCC_8074
i2c, USB, SD/eMMC, etc. Select this for the root clock
of ipq8074.
+config IPQ_GCC_6018
+ tristate "IPQ6018 Global Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for global clock controller on ipq6018 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc. Select this for the root clock
+ of ipq6018.
+
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f0768fb..025137d 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
+obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
new file mode 100644
index 000..9f4552b
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -0,0 +1,5267 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "reset.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+ P_XO,
+ P_BIAS_PLL,
+ P_UNIPHY0_RX,
+ P_UNIPHY0_TX,
+ P_UNIPHY1_RX,
+ P_BIAS_PLL_NSS_NOC,
+ P_UNIPHY1_TX,
+ P_PCIE20_PHY0_PIPE,
+ P_USB3PHY_0_PIPE,
+ P_GPLL0,
+ P_GPLL0_DIV2,
+ P_GPLL2,
+ P_GPLL4,
+ P_GPLL6,
+ P_SLEEP_CLK,
+ P_UBI32_PLL,
+ P_NSS_CRYPTO_PLL,
+ P_PI_SLEEP,
+};
+
+static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll0",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
+ "xo",
+ "bias_pll_cc_clk",
+ "gpll0",
+ "gpll4",
+ "nss_crypto_pll",
+ "ubi32_pll",
+};
+
+static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL4, 3 },
+ { P_NSS_CRYPTO_PLL, 4 },
+ { P_UBI32_PLL, 5 },
+};
+
+static const char * const gcc_xo_gpll0[] = {
+ "xo",
+ "gpll0",
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
+ "xo",
+ "bias_pll_nss_noc_clk",
+ "gpll0",
+ "gpll2",
+};
+
+static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] =
{
+ { P_XO, 0 },
+ { P_BIAS_PLL_NSS_NOC, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL2, 3 },
+};
+
+static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_rx_clk",
+ "uniphy0_gcc_tx_clk",
+ "uniphy1_gcc_rx_clk",
+ "uniphy1_gcc_tx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map
+gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_RX, 1 },
+ { P_UNIPHY0_TX, 2 },
+ { P_UNIPHY1_RX, 3 },
+ { P_UNIPHY1_TX, 4 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_tx_clk",
+ "uniphy0_gcc_rx_clk",
+ "uniphy1_gcc_tx_clk",
+ "uniphy1_gcc_rx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map
+gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+
