Re: [PATCH 4/6] phy: qcom-qmp: Add QMP V3 USB3 UNI PHY support for sdm845
On Tue, Mar 20, 2018 at 12:00 AM Manu Gautam wrote: > Hi, > On 3/19/2018 11:21 PM, Evan Green wrote: > > Hi Manu, > > > > On Fri, Mar 16, 2018 at 2:46 AM Manu Gautam wrote: > [snip] > >> index d1c6905..5d78d43 100644 > >> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h > >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h > >> @@ -214,6 +214,8 @@ > >> #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN0x030 > >> #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE0x034 > >> #define QSERDES_V3_RX_RX_TERM_BW 0x07c > >> +#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc > > I noticed you add this definition, but never use it. Are you missing a > > QMP_PHY_INIT_CFG line for this register in qmp_v3_usb3_uniphy_rx_tbl[], or > > is that register "don't care"? It looks important, and while its default > > value out of reset might be valid, you never know what nutty value boot > > firmware might set it to. > > > Yes POR value of this register is valid for this soc. > QMP driver resets (asserts and de-asserts reset_control) in probe. So, that should > ensure that PHY registers are indeed set to POR value. Left the definition there > if different setting needed to be done for a different variant of h/w in future. Sounds good. Thanks, Manu. Reviewed-by: Evan Green
Re: [PATCH 4/6] phy: qcom-qmp: Add QMP V3 USB3 UNI PHY support for sdm845
Hi, On 3/19/2018 11:21 PM, Evan Green wrote: > Hi Manu, > > On Fri, Mar 16, 2018 at 2:46 AM Manu Gautam wrote: [snip] >> index d1c6905..5d78d43 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h >> @@ -214,6 +214,8 @@ >> #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN0x030 >> #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE0x034 >> #define QSERDES_V3_RX_RX_TERM_BW 0x07c >> +#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc > I noticed you add this definition, but never use it. Are you missing a > QMP_PHY_INIT_CFG line for this register in qmp_v3_usb3_uniphy_rx_tbl[], or > is that register "don't care"? It looks important, and while its default > value out of reset might be valid, you never know what nutty value boot > firmware might set it to. > Yes POR value of this register is valid for this soc. QMP driver resets (asserts and de-asserts reset_control) in probe. So, that should ensure that PHY registers are indeed set to POR value. Left the definition there if different setting needed to be done for a different variant of h/w in future. -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH 4/6] phy: qcom-qmp: Add QMP V3 USB3 UNI PHY support for sdm845
Hi Manu, On Fri, Mar 16, 2018 at 2:46 AM Manu Gautam wrote: > QMP V3 UNI PHY is a single lane USB3 PHY without support > for DisplayPort (DP). > Main difference from DP combo QMPv3 PHY is that UNI PHY > doesn't have dual RX/TX lanes and no separate DP_COM > block for configuration related to type-c or DP. > While at it, fix has_pwrdn_delay attribute for USB-DP > PHY configuration. > Signed-off-by: Manu Gautam > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 148 > drivers/phy/qualcomm/phy-qcom-qmp.h | 5 ++ > 2 files changed, 153 insertions(+) ... > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h > index d1c6905..5d78d43 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp.h > +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h > @@ -214,6 +214,8 @@ > #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN0x030 > #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE0x034 > #define QSERDES_V3_RX_RX_TERM_BW 0x07c > +#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc I noticed you add this definition, but never use it. Are you missing a QMP_PHY_INIT_CFG line for this register in qmp_v3_usb3_uniphy_rx_tbl[], or is that register "don't care"? It looks important, and while its default value out of reset might be valid, you never know what nutty value boot firmware might set it to. > +#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 > #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 > #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc > #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL20x0d4 > @@ -227,6 +229,7 @@ > #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL0x10c > #define QSERDES_V3_RX_RX_BAND 0x110 > #define QSERDES_V3_RX_RX_INTERFACE_MODE0x11c > +#define QSERDES_V3_RX_RX_MODE_00 0x164 > /* Only for QMP V3 PHY - PCS registers */ > #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 > @@ -273,6 +276,8 @@ > #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 > #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 > #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 > +#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c > +#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 > /* Only for QMP V3 PHY - PCS_MISC registers */ > #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > -- > To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/6] phy: qcom-qmp: Add QMP V3 USB3 UNI PHY support for sdm845
QMP V3 UNI PHY is a single lane USB3 PHY without support
for DisplayPort (DP).
Main difference from DP combo QMPv3 PHY is that UNI PHY
doesn't have dual RX/TX lanes and no separate DP_COM
block for configuration related to type-c or DP.
While at it, fix has_pwrdn_delay attribute for USB-DP
PHY configuration.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 148
drivers/phy/qualcomm/phy-qcom-qmp.h | 5 ++
2 files changed, 153 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 73aa282..689951d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -490,6 +490,118 @@ enum qphy_reg_layout {
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
};
+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
+};
+
+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
+};
+
+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
+};
+
+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
+ /* FLL settings */
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+
+ /* Lock Det settings */
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L
